To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
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incurred by you resulting from errors in or omissions from the information included herein.
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8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific chara cterist ics such as the o ccurren ce of failure at a certai n rate an d malfunct ion s under certai n u se cond ition s. Further,
Renesas Electronics pr oducts are not subject to radiation resi stance design. Please be sure to implement safety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
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manufactured by you.
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(Note 1) “Renesas Electronics” as us ed in this document means Renesas Electronics Corporation and also includes its majo ri ty-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
R8C/2E Group,
R8C/2F Group
Hardware Manual
16
User’s Manual
Rev.1.00 2007.12
RENESAS MCU
R8C FAMILY / R8C/2x SERIES
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
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Notes regarding these materials
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical
characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic
knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral
functions, and electrical characteristics; and usage notes.
Particular attention should be paid to the precautionary notes when using the manual. These notes occur
within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer
to the text of the manual for details.
The following documents apply to the R8C/2E Group, R8C/2 F Group. Make sure to refer to the latest versions of
these documents. Th e newest versions of the docum ents listed may be obtai ned from the Renesas Technolo gy Web
site.
Document Type Description Document Title Document No.
Datasheet Hardware overview and electrical characteristics R8C/2E, R8C/2F
Group Datasheet REJ03B0222
Hardware manual Hardware specifications (pin assignments,
memory maps, peripheral function
specifications, electrical characteristics, timing
charts) and operation description
Note: Refer to the application notes for details on
using peripheral functions.
R8C/2E Group,
R8C/2F Group
Hardware Manual
This hardware
manual
Software manual Description of CPU instruction set R8C/Tiny Series
Software Manual REJ09B0001
Application note Information on using peripheral functions and
application examples
Sample programs
Information on writing programs in assembly
language and C
Available from Renesas
Technology Web site.
Renesas
technical update Product specifications, updates on documents,
etc.
2. Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described
below.
(1) Register Names, Bit Names, and Pin Names
Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word
“register,” “bit,” or “pin” to distinguish the three categories.
Examples the PM03 bit in the PM0 register
P3_5 pin, VCC pin
(2) Notation of Numbers
The indication “b ” is append ed to numer ic values gi ven in binary fo rmat. Ho wever, nothing is ap pended t o the
values of single bits. The indication “h” is appended to numeric values given in hexadecim al format. Nothi ng
is appended to numeric values given in decimal format.
Examples Binary: 11b
Hexadecimal: EFA0h
Decimal: 123 4
3. Register Notation
The symbols and terms used in register diagrams are described below.
*1 Blank: Set to 0 or 1 according to the application.
0: Set to 0.
1: Set to 1.
X: Nothing is assigned.
*2 RW: Read and write.
RO: Read only.
WO: Write only.
−: Nothing is assigned.
*3• Reserved bit
Reserved bit. Set to specified value.
*4• Nothing is assigned
Nothing is assigned to the bit. As the bit may be used fo r future functions, if necessary, set to 0.
• Do not set to a value
Operation is not guaranteed when a value is set.
• Function varies according to the operating mode.
The function of the bit varies with the peripheral function mode. Refer to the register diagram for information
on the individual mode s.
XXX Register
Symbol Address After Reset
XXX XXX 00h
Bit NameBit Symbol RW
b7 b6 b5 b4 b3 b2 b1 b0
XXX bits 1 0: XXX
0 1: XXX
1 0: Do not set.
1 1: XXX
b1 b0
XXX1
XXX0
XXX4
Reserved bits
XXX5
XXX7
XXX6
Function
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
XXX bit
Function varies according to the operating
mode.
Set to 0.
0
(b3)
(b2)
RW
RW
RW
RW
WO
RW
RO
XXX bits
0: XXX
1: XXX
*1
*2
*3
*4
4. List of Abbreviations and Acronyms
All trademarks and registered trademarks are the property of their respective owners.
Abbreviation Full Form
ACIA Asynchronous Communication Interface Adapter
bps bits per second
CRC Cyclic Redundancy Check
DMA Direct Memory Access
DMAC Direct Memory Access Controller
GSM Global System for Mobile Communications
Hi-Z High Impedance
IEBus Inter Equipment Bus
I/O Input / Output
IrDA Infrared Data Association
LSB Least Significant Bit
MSB Most Significant Bit
NC Non-Connect
PLL Phase Locked Loop
PWM Pulse Width Modulation
SFR Special Function Registers
SIM Subscriber Identity Module
UART Universal Asynchronous Receiver / Transmitter
VCO Voltage Controlled Oscillator
A - 1
SFR Page Reference ........................................................................................................................... B - 1
1. Overview ......................................................................................................................................... 1
1.1 Features ..................................................................................................................................................... 1
1.1.1 Applications .......................................................................................................................................... 1
1.1.2 Specifications ........................................................................................................................................ 2
1.2 Product List ............................................................................................................................................... 6
1.3 Block Diagram ......................................................................................................................................... 8
1.4 Pin Assignment .......................................................................................................................................... 9
1.5 Pin Functions ........................................................................................................................................... 11
2. Central Processing Unit (CPU) .............. ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ....................... 12
2.1 Data Registers (R0, R1, R2, and R3) ...................................................................................................... 13
2.2 Address Registers (A0 and A1) ............................................................................................................... 13
2.3 Frame Base Register (FB) ....................................................................................................................... 13
2.4 Interrupt Table Register (INTB) .............................................................................................................. 13
2.5 Program Counter (PC) ................ ..................................... ........................................................................ 13
2.6 User Stack Pointer (USP ) and Interrupt Stack Pointer (ISP) .................................................................. 13
2.7 Static Base Register (SB) ............................................. ........................................................................... 13
2.8 Flag Register (FLG) ................................................................................................................................ 13
2.8.1 Carry Flag (C) ..................................................................................................................................... 13
2.8.2 Debug Flag (D) ................................................................................................................................... 13
2.8.3 Zero Flag (Z) ....................................................................................................................................... 13
2.8.4 Sign Flag (S) ....................................................................................................................................... 13
2.8.5 Register Bank Select Flag (B) ............................................................................................................ 13
2.8.6 Overflow Flag (O) .............................................................................................................................. 13
2.8.7 Interrupt Enable Flag (I) ..................................................................................................................... 14
2.8.8 Stack Pointer Select Flag (U) .............................................................................................................. 14
2.8.9 Processor Interrupt Priority Le vel (IPL) ............................................................................................. 14
2.8.10 Reserved Bit ............. ........................................................................................................................... 14
3. Memory ......................................................................................................................................... 15
3.1 R8C/2E Group ........... ....................................................................................... ....................................... 15
3.2 R8C/2F Group ......................................................................................................................................... 16
4. Special Function Registers (SFRs) ............................................................................................... 17
5. Resets ................ .......................... .......................... .......................... ............................................. 24
5.1 Hardware Reset ....................................................................................................................................... 27
5.1.1 When Power Supply is Stable ............................................................................................................. 27
5.1.2 Power On ............................................................................................................................................ 27
5.2 Power-On Reset Function ....................................................................................................................... 29
5.3 Voltage Monitor 1 Reset ......................................................................................................................... 30
5.4 Voltage Monitor 2 Reset ......................................................................................................................... 30
5.5 Watchdog Timer Reset ............................................................................................................................ 30
5.6 Software Reset ......................................................................................................................................... 30
6. Voltage Detection Circuit .............................................................................................................. 31
6.1 VCC Input Voltage .................................................................................................................................. 36
Table of Contents
A - 2
6.1.1 Monitoring Vdet1 ............................. .................................................................................................. 36
6.1.2 Monitoring Vdet2 ............................. .................................................................................................. 36
6.2 Voltage Monitor 1 Interru pt and Voltage Monitor 1 Reset ..................................................................... 37
6.3 Voltage Monitor 2 Interru pt and Voltage Monitor 2 Reset ..................................................................... 39
7. Programmable I/O Ports ............................................................................................................... 41
7.1 Functions of Programmable I/O Ports ..................................................................................................... 41
7.2 Effect on Peripheral Functions ................................................................................................................ 42
7.3 Pins Other than Programmable I/O Ports ................................................................................................ 42
7.4 Port Setting ............................................................................................................. ................................. 52
7.5 Unassigned Pin Handling ........................................................................................................................ 62
8. Processor Mode ............................................................................................................................ 63
8.1 Processor Modes ................................. ..................................................................................................... 63
9. Bus ............... ................ ................ ................ ................ ................. ................ ................................ 64
10. Clock Generation Circuit ............................................................................................................... 65
10.1 X IN Clock ................................................................................................................. .............................. 73
10.2 On-Chip Oscillator Clocks ...................................................................................................................... 74
10.2.1 Low-Speed On-Chip Oscillator Clock ................................................................................................ 74
10.2.2 High-Speed On-Chip Oscillator Clock ............................................................................................... 74
10.3 CPU Clock and Peripheral Function Clock ............................................................................................. 75
10.3.1 System Clock ...................................................................................................................................... 75
10.3.2 CPU Clock .......................................................................................................................................... 75
10.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32) ............................................................................. 75
10.3.4 fOCO ................................................................................................................................................... 75
10.3.5 fOCO40M ........................................................................................................................................... 75
10.3.6 fOCO-F ............................................................................................................................................... 75
10.3.7 fOCO-S ............................................................................................................................................... 75
10.3.8 fOCO128 ............................................................................................................................................. 75
10.4 Power Control .......................................................................................................................................... 76
10.4.1 Standard Operating Mode ................................................................................................................... 76
10.4.2 Wait Mode .................... ...................................................................................................................... 78
10.4.3 Stop Mode ........................................................................................................................................... 82
10.5 Oscillation Stop Detection Function ....................................................................................................... 85
10.5.1 How to Use Oscillation Stop Detection Function .......................... .................... .................... ............. 85
10.6 Notes on Clock Generation Circuit ......................................................................................................... 88
10.6.1 Stop Mode ........................................................................................................................................... 88
10.6.2 Wait Mode .................... ...................................................................................................................... 88
10.6.3 Oscillation Stop Detection Function ................................................................................................... 88
10.6.4 Oscillation Circuit Constants .............................................................................................................. 88
11. Protection .............. ................. ................ ................ ................ ................ ............. .......................... 89
12. Interrupts ...................... ....................... ...................... ....................... ............................................. 90
12.1 I nterrupt Overview ........................ .......................................................................................................... 90
12.1.1 Types of Interrupts .............................................................................................................................. 90
12.1.2 Software Interrupts ............................................................................................................................. 91
A - 3
12.1.3 Special Interrupts ................................................................................................................................ 92
12.1.4 Peripheral Function Interrupt .............................................................................................................. 92
12.1.5 Interrupts and Interrupt Vectors .......................................................................................................... 93
12.1.6 Interrupt Control ........... ... ....................................................................... ............................................ 95
12.2 INT Interrupt ......................................................................................................................................... 104
12.2.1 INTi Interrupt (i = 0, 1, 3) ................................................................................................................. 104
12.2.2 INTi Input Filter (i = 0, 1, 3) ....................................................................................................... ...... 106
12.3 Key Input Interrupt ................................................................................................................................ 107
12.4 A ddress Match Interrupt .............................. ..................................... ................................ ..................... 109
12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt ........................................... 111
12.6 Notes on Interrupts ..................................................................................................................... ........... 112
12.6.1 Reading Address 00000h .................................................................................................................. 112
12.6.2 SP Setting ...................................................................................................................... .................... 112
12.6.3 External Interrupt and Key Input In terrupt ............................................................................... ........ 112
12.6.4 Changing In t e rrupt Sources .............................................................................................................. 113
12.6.5 Changing Interrupt Control Register Contents ................................................................................. 114
13. Watchdog Timer ........................................................................................................................... 115
13.1 Count Source Protection Mode Disabled ........................................................................................ ...... 118
13.2 Count Source Protection Mode Enabled ............................................................................................... 119
14. Timers ......................................................................................................................................... 120
14.1 Timer RA ...................................................................................................................... ......................... 122
14.1.1 Timer Mode ........................................................................................................................ .............. 125
14.1.2 Pulse Output Mode .. ..................................................... ................................................ .................... 127
14.1.3 Event Counter Mode .............................................................................................................. ........... 129
14.1.4 Pulse Width Measurement Mode .............................................................................................. ........ 131
14.1.5 Pulse Period Measurement Mode .................................................. ..................................... .............. 134
14.1.6 Notes on Timer RA ................................................................................................................ ........... 137
14.2 Timer RB ................................................................................................................................. .............. 138
14.2.1 Timer Mode ........................................................................................................................ .............. 142
14.2.2 Programmable Waveform Generation Mode ................... .................... ............................................. 145
14.2.3 Programmable One-shot Generation Mode ...................................................................................... 148
14.2.4 Programmable Wait One-Shot Generation Mode ............................................................................. 152
14.2.5 Notes on Timer RB .......................................................................................................... ................. 155
14.3 Timer RC ................................................................................................................................. .............. 159
14.3.1 Overview ................................................................................................................................ ........... 159
14.3.2 Registers Associated with Timer RC ................................................................................................ 161
14.3.3 Common Items for Multiple Modes ........................................................................................... ...... 171
14.3.4 Timer Mode (Input Capture Function) ............................................................................................. 177
14.3.5 Timer Mode (Output Compare Function) ......................................................................................... 182
14.3.6 PWM Mode ....................................................................................................................................... 188
14.3.7 PWM2 Mode .................................................................................................................... ................. 193
14.3.8 Timer RC Interrupt ........................................................................................................................... 199
14.3.9 Notes on Timer RC .......................................................................................................... ................. 200
14.4 Timer RE ......................................................................................................................... ...................... 201
14.4.1 Output Compare Mode ....................................................... .............................................................. 202
14.4.2 Notes on Timer RE ........................................................................................................................... 206
A - 4
15. Serial Interface ............................................................................................................................ 207
15.1 Clock Synchronous Serial I/O Mode ............................................................................................... ...... 213
15.1.1 Polarity Select Function ................................................................................................... ................. 216
15.1.2 LSB First/MSB First Select Function ......................................................................................... ...... 216
15.1.3 Continuous Receive Mode ................................................................................................................ 217
15.2 Clock Asynchronous Serial I/O (UART) Mode ......................... ..................................... ...................... 218
15.2.1 Bit Rate ......... ..................................................................................................... ............................... 222
15.3 Notes on Serial Interface ............................................................................................................... ........ 223
16. Hardware LIN .. ... ... .... ................... ... .... ................... ... ... .... ................... ... ... .... .............................. 224
16.1 Features ................................................................................................................................................. 224
16.2 Input/Output Pins ................. ...................................................... ........................................................... 225
16.3 Register Configuration .......................................................................................................................... 226
16.4 Functional Description .................................................................................................................... ...... 228
16.4.1 Master Mode ....................................................................................................................... .............. 228
16.4.2 Slave Mode ................................................................................................................. ...................... 231
16.4.3 Bus Collision Detection Function ..................................................................................................... 235
16.4.4 Hardware LIN End Processing ......................................................................................................... 236
16.5 Interrupt Requests ....................... ...................................................... ..................................................... 237
16.6 Notes on Hardware LIN ............................................................................................................. ........... 238
17. A/D Converter ............................................................................................................................. 239
17.1 One-Shot Mode ..................................................................................................................................... 243
17.2 Repeat Mode ...................................................................................................................... .................... 246
17.3 Sample and Hold ........................... .................................................................................. ...................... 249
17.4 A /D Conversion Cycles ....................................... ...................................................... .............. .............. 249
17.5 Internal Equivalent Circuit of Analog Input .......................................................................................... 250
17.6 Output Impedance of Sensor under A/D Conversion ............................................................................ 251
17.7 Notes on A/D Converter ..................................................................................................................... ... 252
18. D/A Converter ............................................................................................................................. 253
19. Comparator ................................................................................................................................. 256
19.1 Overview ............................................................................................................................................... 256
19.2 Register Functions ................................................................................................................................. 258
19.3 Functional Description .................................................................................................................... ...... 260
19.3.1 Comparison Result Output ................................................................................................................ 261
19.3.2 Digital Filter ........................................................................ .............................................................. 262
19.4 Comparator 0 Interrupt and Comparator 1 Interrupt ............................................................................. 263
20. Flash Memory Version ................................................................................................................ 264
20.1 Overview ............................................................................................................................................... 264
20.2 Memory Map ................................................................ ................................................ ......................... 265
20.3 Functions to Prevent Rewriting of Flash Memory ................................................................................ 267
20.3.1 ID Code Check Function .......................................................................................................... ........ 267
20.3.2 ROM Code Protect Function ............................................................................................................ 268
20.4 CPU Rewrite Mode ........................................................... ................................................... ................. 269
20.4.1 EW0 Mode ........................................................................................................................................ 270
20.4.2 EW1 Mode ........................................................................................................................................ 270
A - 5
20.4.3 Software Commands ................................................................................................................. ........ 279
20.4.4 Status Registers ................................................................................................................................. 284
20.4.5 Full Status Check .............................................................................................................................. 285
20.5 Standard Serial I/O Mode ................................................................................................................... ... 287
20.5.1 ID Code Check Function .......................................................................................................... ........ 287
20.6 Parallel I/O Mode .......................... ..................................................... .................................. ................. 290
20.6.1 ROM Code Protect Function ............................................................................................................ 290
20.7 Notes on Flash Memory Version ........................................................................................................... 291
20.7.1 CPU Rewrite Mode ........................................................................... ................................................ 291
21. Electrical Characteristics ............................................................................................................ 294
22. Usage Notes ............................................................................................................................... 309
22.1 Notes on Clock Generation Circuit ............................................................................................ ........... 309
22.1.1 Stop Mode ................................................................................................................ ......................... 309
22.1.2 Wait Mode .................... ................................................................................................... ................. 309
22.1.3 Oscillation Stop Detection Function ................................................................................................. 309
22.1.4 Oscillation Circuit Constants ............................................................................................................ 309
22.2 Notes on Interrupts ..................................................................................................................... ........... 310
22.2.1 Reading Address 00000h .................................................................................................................. 310
22.2.2 SP Setting ...................................................................................................................... .................... 310
22.2.3 External Interrupt and Key Input In terrupt ............................................................................... ........ 310
22.2.4 Changing In t e rrupt Sources .............................................................................................................. 311
22.2.5 Changing Interrupt Control Register Contents ................................................................................. 312
22.3 Notes on Timers ...................................................................................................................... .............. 313
22.3.1 Notes on Timer RA ................................................................................................................ ........... 313
22.3.2 Notes on Timer RB .......................................................................................................... ................. 314
22.3.3 Notes on Timer RC .......................................................................................................... ................. 318
22.3.4 Notes on Timer RE ........................................................................................................................... 319
22.4 Notes on Serial Interface ............................................................................................................... ........ 320
22.5 Notes on Hardware LIN ............................................................................................................. ........... 321
22.6 Notes on A/D Converter ..................................................................................................................... ... 322
22.7 Notes on Flash Memory Version ........................................................................................................... 323
22.7.1 CPU Rewrite Mode ........................................................................... ................................................ 323
22.8 Notes on Noise ...................................................................................................................................... 326
22.8.1 Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and
Latch-up ................................................................................................................................. ........... 326
22.8.2 Countermeasures against Noise Error of Port Control Registers ................ ..................................... 326
23. Notes for On-Chip Debugger ...................................................................................................... 327
Appendix 1. Package Dimensions ........................................................................................................ 328
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator ............ 329
Appendix 3. Example of Oscillation Evaluation Circuit ......................................................................... 330
Index ..................................................................................................................................................... 331
B - 1
NOTE:
1. The blank regions are reserved. Do not acce ss locations in these
regions.
Address Register Symbol Page
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 63
0005h Processor Mode Register 1 PM1 63
0006h System Clock Control Register 0 CM0 67
0007h System Clock Control Register 1 CM1 68
0008h
0009h
000Ah Protect Register PRCR 89
000Bh
000Ch Oscillation Stop Detection Register OCD 69
000Dh Watchdog Timer Reset Register WDTR 116
000Eh Watchdog Timer Start Register WDTS 116
000Fh Watchdog Timer Control Register WDC 116
0010h Address Match Interrupt Register 0 RMAD0 110
0011h
0012h
0013h Address Match Interrupt Enable Register AIER 110
0014h Address Match Interrupt Register 1 RMAD1 110
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 117
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control
Register 0 FRA0 70
0024h High-Speed On-Chip Oscillator Control
Register 1 FRA1 70
0025h High-Speed On-Chip Oscillator Control
Register 2 FRA2 70
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch High-Speed On-Chip Oscillator Control
Register 7 FRA7 71
0030h
0031h Voltage Detection Register 1 VCA1 33
0032h Voltage Detection Register 2 VCA2 33, 71
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register VW1C 34
0037h Voltage Monitor 2 Circuit Control Register VW2C 35
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Address Register Symbol Page
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h Timer RC Interrupt Control Register TRCIC 96
0048h
0049h
004Ah Timer RE Interrupt Control Register TREIC 95
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC 95
004Eh A/D Conversion Interrupt Control Register ADIC 95
004Fh
0050h
0051h UART0 Transmit Interrupt Control Register S0TIC 95
0052h UART0 Receive Interrupt Control Register S0R IC 95
0053h
0054h
0055h
0056h Timer RA Interrupt Control Register TRAIC 95
0057h
0058h Timer RB Interrupt Control Register TRBIC 95
0059h INT1 Interrupt Control Register INT1IC 97
005Ah INT3 Interrupt Control Register INT3IC 97
005Bh Comparator 0 Interrupt Contro l Register CM0IC 96
005Ch Comparator 1 Interrupt Control Register CM1IC 96
005Dh INT0 Interrupt Control Register INT0IC 97
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
SFR Page Reference
B - 2
NOTE:
1. The blank regions are reserved. Do not acce ss locations in these
regions.
Address Register Symbol Page
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 210
00A1h UART0 Bit Rate Register U0BRG 210
00A2h UART0 Transmit Buffer Register U0TB 209
00A3h
00A4h UART0 Transmit / Receive Control Register 0 U0C0 211
00A5h UART0 Transmit / Receive Control Register 1 U0C1 212
00A6h UART0 Receive Buffer Register U0RB 209
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Address Register Symbol Page
00C0h A/D Register AD 242
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Control Register 2 ADCON2 242
00D5h
00D6h A/D Control Register 0 ADCON0 241
00D7h A/D Control Register 1 ADCON1 242
00D8h D/A Register 0 DA0 254
00D9h
00DAh D/A Register 1 DA1 254
00DBh
00DCh D/A Control Register DACON 254
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 49
00E1h Port P1 Register P1 49
00E2h Port P0 Direction Register PD0 48
00E3h Port P1 Direction Register PD1 48
00E4h
00E5h Port P3 Register P3 49
00E6h
00E7h Port P3 Direction Register PD3 48
00E8h Port P4 Register P4 49
00E9h Port P5 Register P5 49
00EAh Port P4 Direction Register PD4 48
00EBh Port P5 Direction Register PD5 48
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h Pin Se lect Register 2 PINSR2 50
00F7h Pin Se lect Register 3 PINSR3 50
00F8h Port Mode Register PMR 50, 212
00F9h E xternal Input E nable Register INTEN 104
00FAh INT Input Filter Select Register INTF 105
00FBh Key Input Enable Register KIEN 108
00FCh Pull-Up Contro l Register 0 PUR0 51
00FDh Pull-Up Contro l Register 1 PUR1 51
00FEh Port P1 Drive Capacity Control Register P1DRR 51
00FFh
B - 3
NOTE:
1. The blank regions are reserved. Do not acce ss locations in these
regions.
Address Register Symbol Page
0100h Timer RA Control Regist e r TRACR 123
0101h Timer RA I/O Control Register TRAIOC 123, 125, 128,
130, 132, 135
0102h Timer RA Mode Register TRAMR 124
0103h Timer RA Prescal e r Re gi ste r TRAPRE 124
0104h Timer RA Register TRA 124
0105h
0106h LIN Control Register LINCR 226
0107h LIN Status Register LINST 227
0108h Timer RB Control Regist e r TRBCR 139
0109h Timer RB One-Shot Control Register TRBOCR 139
010Ah Timer RB I/O Control Register TRBIOC 140, 142, 146,
149, 153
010Bh Timer RB Mode Register TRBMR 140
010Ch Timer RB Pr escaler Register TRBPRE 141
010Dh Timer RB Secondary Register TRBSC 141
010Eh Timer RB Primary Register TRBPR 141
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Counter Data Register TRESEC 203
0119h Timer RE Compare Data Register TREMIN 203
011Ah
011Bh
011Ch Tim er RE Co ntr ol Register 1 TRECR1 203
011Dh Tim er RE Co ntr ol Register 2 TRECR2 204
011Eh Timer RE Clock Source Select Register TRECSR 204
011Fh
0120h Timer RC Mode Register TRCMR 162
0121h Timer RC Control Register 1 TRCCR1 163, 186, 190,
195
0122h Timer RC Interrupt Enable Register TRCIER 164
0123h Timer RC Status Register TRCSR 165
0124h Timer RC I/O Control Register 0 TRCIOR0 170, 179, 184
0125h Timer RC I/O Control Register 1 TRCIOR1 170, 180, 185
0126h Timer RC Counter TRC 166
0127h
0128h Timer RC General Register A TRCGRA 166
0129h
012Ah Timer RC General Register B TRCGRB 166
012Bh
012Ch Timer RC General Register C TRCGRC 166
012Dh
012Eh Timer RC General Register D TRCGRD 166
012Fh
Address Register Symbol Page
0130h Timer RC Control Register 2 TRCCR2 167
0131h Timer RC Digital Filter Function Select
Register TRCDF 168
0132h Timer RC Output Master Enable Register TRCOER 169
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
B - 4
NOTE:
1. The blank regions are reserved. Do not acce ss locations in these
regions.
Address Register Symbol Page
0170h
0171h
0172h
0173h
0174h Comparator 0 Control Register ACCR0 255, 258
0175h Comparator 1 Control Register ACCR1 255, 258
0176h
0177h Comparator Mode Register ACMR 259
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
Address Register Symbol Page
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 275
01B4h
01B5h Flash Memory Control Register 1 FMR1 274
01B6h
01B7h Flash Memory Control Register 0 FMR0 273
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
FFFFh Option Function Select Register OFS 26, 117, 268
Rev.1.00 Dec 14, 2007 Page 1 of 332
REJ09B0349-0100
R8C/2E Group, R8C/2F Group
RENESAS MCU
1. Overview
1.1 Features
The R8C/2E Group and R8C/2F Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core,
employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable
of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation
processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
Furthermore, the R8C/2F Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/2E Group and R8C/2F Group is only the presence or absence of data flash. Their
peripheral functions are the same.
1.1.1 Applications
Electronic household appli a nces, office equipment, audio equipment, consumer equipment, etc.
REJ09B0349-0100
Rev.1.00
Dec 14, 2007
R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 2 of 332
REJ09B0349-0100
1.1.2 Specifications
Tables 1.1 and 1.2 outlines the Specifications for R8C/2E Group and Tables 1.3 and 1.4 outlines the
Specifications for R8C/2F Group.
Table 1.1 Specifications for R8C/2E Group (1)
Item Function Specification
CPU Central
processing unit R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Sing le-chip mode (address space: 1 Mbyte)
Memory ROM, RAM Refer to Table 1.5 Product List for R8C/2E Group.
Power Supply
Voltage
Detection
Voltage
detection circuit • Power-on reset
• Voltage detection 2
I/O Ports Programmable
I/O ports • Input-only: 3 pins
• CMOS I/O ports: 25, selectable pull-up resistor
• High current driv e po rts: 8
Clock Clock generation
circuits 2 circuits: XIN clock oscillation circuit (with on-c hip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment
function)
• Oscillation stop detection: XIN clock oscillation stop detection
function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip
oscillator, low-speed on-chip oscillator), wait mode, stop mode
Interrupt s • External: 4 sources, Internal: 13 sources, Software: 4 sources
• Priority levels: 7 levels
Watchdog Ti mer 15 bits × 1 (with prescaler), reset start selectable
Timer Timer RA 8 bits × 1 (with 8-bit pre scaler)
Timer mode (period timer), pulse output mode (output level inverted
every period), even t counter mode, p ulse width measuremen t mode,
pulse period measurement mode
Timer RB 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform gen eration
mode (PWM output), programmable one-shot generation mode,
programmable wait one-shot generation mode
Timer RC 16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM
mode (output 3 pins), PWM2 mode (PWM output pin)
Ti m e r RE 8 bits × 1
Output compare mode
Serial
Interface UART0 Clock synchronous serial I/O/UART × 1
LIN Module Hardware LIN: 1 (timer RA, UART0)
A/D Converter 10-bit resolution × 12 channels, includes sample and hold function
D/A Converter 8-bit resolution × 2 circuits
Comparator 2 circuits
R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 3 of 332
REJ09B0349-0100
NOTE:
1. S pecify the D version if D version functions are to be used.
Table 1.2 Specifications for R8C/2E Group (2)
Item Specification
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 100 times
• Program security: ROM code protect, ID code check
• Debug functions: On-chip de bug, on-boar d fla sh re wr ite fu nction
Operating Frequency/Supply
Voltage f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V),
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 23 µA (VCC = 3.0 V, wait mode (peripheral clock off))
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(1)
Package 32-pin LQFP
Package code: PLQP0032GB-A (previous code: 32P6U-A)
R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 4 of 332
REJ09B0349-0100
Table 1.3 Specifications for R8C/2F Group (1)
Item Function Specification
CPU Central
processing unit R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Memory ROM, RAM Refer to Table 1.6 Product List for R8C/2F Group.
Power Supply
Voltage
Detection
Voltage detectio n
circuit • Power-on reset
• Voltage detection 2
I/O Ports Programmable
I/O ports • Input-only: 3 pins
• CMOS I/O ports: 25, selectable pull-up resistor
• High current drive ports: 8
Clock Clock generation
circuits 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor),
On-chip oscillator (high-speed, low-speed)
(high-speed on-chip oscillator has a frequency adjustment
function)
• Oscillation stop detection: XIN clock oscillation stop detection
function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, high-speed on-chip
oscillator, low-speed on-chip oscillator), wait mode, stop mode
Interrupts • External: 4 sources, Internal: 13 sources, Software: 4 sources
• Priority levels: 7 levels
Watchdog Timer 15 bits × 1 (with prescaler), reset start selectable
Timer Timer RA 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse o utput mode (o utput level inver ted
every period), event counte r mode, pulse width measurement m ode,
pulse period measurement mode
Timer RB 8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation
mode (PWM output), programmable one-shot generation mode,
programm ab le wa it on e- sh ot ge n er at ion mo de
Timer RC 16 bits × 1 (with 4 capture/compare registers)
T imer mode ( input capture function, outpu t compare function), PWM
mode (output 3 pins), PWM2 mode (PWM output pin)
Timer RE 8 bits × 1
Output compare mode
Serial
Interface UART0 Clock synchronous serial I/O/UART × 1
LIN Module Hardware LIN: 1 (timer RA, UART0)
A/D Converter 10-bit resolution × 12 channels, includes sample and hold function
D/A Converter 8-bit resolution × 2 circuits
Comparator 2 circuits
R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 5 of 332
REJ09B0349-0100
NOTE:
1. S pecify the D version if D version functions are to be used.
Table 1.4 Specifications for R8C/2F Group (2)
Item Specification
Flash Memory • Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
Operating Frequency/Supply
Voltage f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V),
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 23 µA (VCC = 3.0 V, wait mode (peripheral clock off))
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D version)(1)
Package 32-pin LQFP
Package code: PLQP0032GB-A (previous code: 32P6U-A)
R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 6 of 332
REJ09B0349-0100
1.2 Product List
Table 1.5 lists Product List for R8C/2E Group, Figure 1.1 shows a Part Number, Memory Size, and Package of
R8C/2E Group, Table 1.6 lists Product List for R8C/2F Group, and Figure 1.2 shows a Part Number , Memory Size,
and Package of R8C/2F Group.
NOTE:
1. The user ROM is programmed before shipment.
Figure 1.1 Part Number, Memory Size, and Package of R8C/2E Group
Table 1.5 Product List for R8C/2E Group Current of Dec. 2007
Part No. ROM Capacity RAM Capacity Package Ty pe Remarks
R5F212E2NFP 8 Kbytes 512 bytes PLQP0032GB-A N version
R5F212E4NFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F212E2DFP 8 Kbytes 512 bytes PLQP0032GB-A D version
R5F212E4DFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F212E2NXXXFP 8 Kbytes 512 bytes PLQP0032GB-A N version
Factory prog ra m min g
product(1)
R5F212E4NXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F212E2DXXXFP 8 Kbytes 512 bytes PLQP0032GB-A D version
Factory prog ra m min g
product(1)
R5F212E4DXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A
Part No. R 5 F 21 2E 2 N XXX FP
Package type:
FP: PLQP0032GB-A
ROM number (only factory programming product)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
2: 8 KB
4: 16 KB
R8C/2E Group
R8C/Tiny Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductor
R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 7 of 332
REJ09B0349-0100
NOTE:
1. The user ROM is programmed before shipment.
Figure 1.2 Part Number, Memory Size, and Package of R8C/2F Group
Table 1.6 Product List for R8C/2F Group Current of Dec. 2007
Part No. ROM Capacity RAM
Capacity Package Type Remarks
P r o g r a m R O M Data flash
R5F212F2NFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A N version
R5F212F4NFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F212F2DFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A D version
R5F212F4DFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F212F2NXXXFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A N version
Factory programming
product(1)
R5F212F4NXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F212F2DXXXFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A D version
Factory programming
product(1)
R5F212F4DXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
Part No. R 5 F 21 2F 2 N XXX FP
Package type:
FP: PLQP0032GB-A
ROM number (only factory programming product)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
2: 8 KB
4: 16 KB
R8C/2F Group
R8C/Tiny Series
Memory type
F: Flash memory version
Renesas MCU
Renesas semiconductor
R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 8 of 332
REJ09B0349-0100
1.3 Block Diagram
Figure 1.3 shows a Block Diagram.
Figure 1.3 Block Diagram
Watchdog timer
(15 bits)
R8C/Tiny Series CPU core Memory
ROM(1)
RAM(2)
Multiplier
R0H R0L
R1H R2
R3
R1L
A0
A1
FB
SB
USP
ISP
INTB
PC
FLG
I/O ports
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
System clock
generation circuit
XIN-XOUT
High-speed on-chip oscillator
Low- Sp ee d o n-c h ip os cilla tor
Timers
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
A/D converter
(10 bits × 12 channels)
UART or
clock synchronous serial I/O
(8 bits × 1)
Comparator
(× 2)
LIN module
8
Port P0
8
Port P1
6
Port P3
1 3
Port P4
2
Port P5
Peripheral functions
D/A converter
(8 bits × 2)
R8C/2E Group, R8C/2F Group 1. Overview
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1.4 Pin Assignment
Figure 1.4 shows Pin Assignments (Top View). Table 1.7 outlines the Pin Name Information by Pin Number.
Figure 1.4 Pin Assignments (Top View)
NOTES:
1. P4_7 is an i nput-only port.
2. Can be assigned to th e pin in parentheses by a program.
3. Confir m the pin 1 position on the package by ref erring to the package dimensions.
XIN/P4_6
XOUT/P4_7(1)
VSS/AVSS
RESET
VCC/AVCC
P3_7/TRAO
MODE
P4_5/INT0
P1_7/TRAIO/INT1
P3_6/(INT1)(2)
P3_5/(TRCIOD)(2)
P1_0/KI0/AN8
P1_4/TXD0
VREF/P4_2
P1_3/KI3/AN11/(TRBO)(2)
P3_3/INT3/TRCCLK
P1_1/KI1/AN9/TRCIOA/TRCTRG
P1_2/KI2/AN10/TRCIOB
P0_3/AN4/AVREF1
P0_2/AN5/ACMP1
P0_1/AN6
P0_0/AN7
P0_7/AN0/DA1
P0_6/AN1/DA0
P0_5/AN2/AVREF0
P1_5/RXD0/(TRAIO)/(INT1)(2)
P1_6/CLK0
P5_3/TRCIOC/ACOUT0
P5_4/TRCIOD/ACOUT1
P3_1/TRBO
P3_4/(TRCIOC)(2)
P0_4/AN3/TREO/ACMP0 29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
24 23 22 21 20 19 18 17
5781234 6
R8C/2E Group,
R8C/2F Group
PLQP0032GB-A
(32P6U-A)
(top view)
R8C/2E Group, R8C/2F Group 1. Overview
Rev.1.00 Dec 14, 2007 Page 10 of 332
REJ09B0349-0100
NOTE:
1. Can be assigned to the pin in parentheses by a program.
Table 1.7 Pin Name Information by Pin Numb er
Pin
Number Control Pin Port I/O Pin Functions for of Peripheral Modules
Interrupt Timer Serial
Interface A/D
Converter D/A
Converter Comparator
1 P3_5 (TRCIOD)(1)
2 P3_7 TRAO
3RESET
4 XOUT P4_7
5 VSS/AVSS
6 XIN P4_6
7VCC/AVCC
8MODE
9 P4_5 INT0
10 P1_7 INT1 TRAIO
11 P3_6 (INT1)(1)
12 P3_1 TRBO
13 P5_4 TRCIOD ACOUT1
14 P5_3 TRCIOC ACOUT0
15 P1_6 CLK0
16 P1_5 (INT1)(1) (TRAIO)(1) RXD0
17 P1_4 TXD0
18 P1_3 KI3 (TRBO)(1) AN11
19 P1_2 KI2 TRCIOB AN10
20 VREF P4_2
21 P1_1 KI1 TRCIOA/
TRCTRG AN9
22 P1_0 KI0 AN8
23 P3_3 INT3 TRCCLK
24 P3_4 (TRCIOC)(1)
25 P0_7 AN0 DA1
26 P0_6 AN1 DA0
27 P0_5 AN2 AVREF0
28 P0_4 TREO AN3 ACMP0
29 P0_3 AN4 AVREF1
30 P0_2 AN5 ACMP1
31 P0_1 AN6
32 P0_0 AN7
R8C/2E Group, R8C/2F Group 1. Overview
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1.5 Pin Functions
Table 1.8 list Pin Functions.
I: Input O: Output I/O: Input and output
NOTE:
1. Refer to the oscillator manufacturer for oscillation characteristics.
Table 1.8 Pin Functions
Type Symbol I/O Type Description
Power supply input VCC, VSS I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input AVCC, AVSS I Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
XIN clock input XIN I These pins are provid e d for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins.(1) To use an external clock, input it to
the XIN pin and leave the XOUT pin open.
XIN clock output XOUT O
INT interrupt input INT0, INT1, INT3 IINT interrupt input pins
Key input interrupt KI0 to KI3 I Key input interrupt input pins
Timer RA TRAO O Timer RA output pin
TRAIO I/O Timer RA I/O pin
Timer RB TRBO O Timer RB output pin
Timer RC TRCCLK I External clock input pin
TRCTRG I External trigger input pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD I/O Sharing output-compare output / input-capture input / PWM /
PWM2 output pins
Timer RE TREO O Timer RE output pin
Serial interface CLK0 I/O Clock I/O pin
RXD0 I Receive data input pin
TXD0 O Transmit dat a output pin
Reference voltage
input VREF I Reference voltage input pin to A/D converter
A/D converter AN0 to AN11 I Analog input pins to A/D converter
D/A converter DA0 to DA1 O Output pins from D/A converter
Comparator AVREF0 to AVREF1 I Reference voltage input pins to comparator
ACMP0 to ACMP1 I Analog voltage input pins to comparator
ACOUT0 to ACOUT1 O Comparison result output pins of comparator
I/O port P0_0 to P0_7,
P1_0 to P1_7,
P3_1, P3_3 to P3_7,
P4_5,
P5_3, P5_4
I/O CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
P1_0 to P1_7 also function as LED drive ports.
Input port P4_2, P4_6, P4_7 I Input-only ports
R8C/2E Group, R8C/2F Group 2. Central Processing Unit (CPU)
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
Figure 2.1 CPU Registers
R2
b31 b15 b8b7 b0
Data registers(1)
Address registers(1)
R3 R0H (high-order of R0)
R2
R3
A0
A1
INTBHb15b19 b0
INTBL
FB Frame base register(1)
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
Interrupt table register
b19 b0
USP
Program counter
ISP
SB
User stack pointer
Interrupt stack pointer
Static base register
PC
FLG Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
NOTE:
1. These registers comprise a register bank. There are two register banks.
R1H (high-order of R1)
R0L (low-order of R0)
R1L (low-order of R1)
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2.1 Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R 0H) and low-order bit s (R0L) to be used sep aratel y as 8-bit data regist ers. R1H and R 1L are
analogous to R0H and R0L. R2 can be combined with R0 and used a s a 32-bit data regi ster (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogou s to A0. A1 can be combined with A0 to be used
as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative valu e; otherwise to 0.
2.8.5 Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R8C/2E Group, R8C/2F Group 2. Central Processing Unit (CPU)
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2.8.7 Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor inte rrupt priorit y levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R8C/2E Group, R8C/2F Group 3. Memory
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3. Memory
3.1 R8C/2E Group
Figure 3.1 is a Memory Map of R8C/2E Group. The R8C/2E group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0 FFFFh. For exam ple, a 16 -Kbyte i nternal
ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal
RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for
calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
Figure 3.1 Memory Map of R8C/2E Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer/oscillation stop detection/voltage monitor 2
(Reserved)
(Reserved)
Reset
00400h
002FFh
00000h
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
NOTE:
1. The blan k regions are res e rv ed . Do no t ac cess loc at i o ns in t he s e reg ions.
FFFFFh
0FFFFh
0YYYYh Internal ROM
(program ROM)
0XXXh
Part Number Internal ROM Internal RAM
Size Size
R5F212E2NFP, R5F212E2DFP,
R5F212E2NXXXFP, R5F212E2DXXXFP
R5F212E4NFP, R5F212E4DFP,
R5F212E4NXXXFP, R5F212E4DXXXFP
8 Kbyte s
16 Kbytes
0E000h
0C000h
512 bytes
1 Kbyt e
005FFh
007FFh
Address 0YYYYh Address 0XXXXh
R8C/2E Group, R8C/2F Group 3. Memory
Rev.1.00 Dec 14, 2007 Page 16 of 332
REJ09B0349-0100
3.2 R8C/2F Group
Figure 3.2 is a Memory Map of R8C/2F Group. The R8C/2F group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
16-Kbyte internal ROM area is allocated addresses 0C00 0h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte
internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
Figure 3.2 Memory Map of R8C/2F Group
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer/oscillation stop detection/voltage monitor 2
(Reserved)
(Reserved)
Reset
FFFFFh
0FFFFh
0YYYYh
00400h
002FFh
00000h
Internal ROM
(program ROM)
Internal RAM
SFR
(Refer to 4. Special
Function Registers
(SFRs))
0FFFFh
0FFDCh
Internal ROM
(data flash)(1)
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
2. The blank regions are reserved. Do not access locations in these regions.
0XXXXh
02400h
02BFFh
Part Number Internal ROM Internal RAM
Size Size
R5F212F2NFP, R5F212F2DFP,
R5F212F2NXXXFP, R5F212F2DXXXFP
R5F212F4NFP, R5F212F4DFP,
R5F212F4NXXXFP, R5F212F4DXXXFP
8 Kbytes
16 Kbytes
0E000h
0C000h
512 bytes
1 Kbyte
005FFh
007FFh
Address 0YYYYh Address 0XXXXh
R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs)
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4. Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special
function registers.
Table 4.1 SFR Information (1)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register.
3. Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3.
4. The CSPROINI bit in the OFS register is set to 0 .
Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01101000b
0007h System Clock Control Register 1 CM1 00100000b
0008h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillatio n Stop Detection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enab le Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Coun t Source Protection Mode Register CSPR 00h
10000000b(4)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch High-Speed On-Chip Oscillator Control Register 7 FRA7 When Shipping
0030h
0031h Voltage Detection Register 1 (2) VCA1 00001000b
0032h Voltage Detection Register 2 (2) VCA2 00100000b
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register(3) VW1C 00001000b
0037h Voltage Monitor 2 Circuit Control Register(3) VW2C 00h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs)
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Table 4.2 SFR Information (2)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h T imer RC Interrupt Control Register TRCIC XXXXX000b
0048h
0049h
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
004Fh
0050h
0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h
0054h
0055h
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah INT3 Interrupt Control Register INT3IC XX00X000b
005Bh Comparator 0 Interrupt Control Register CM0IC XXXXX000b
005Ch Comparator 1 Interrupt Control Register CM1IC XXXXX000b
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs)
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Table 4.3 SFR Information (3)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Ra te Register U0BRG XXh
00A2h UART0 Transmit Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b
00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs)
Rev.1.00 Dec 14, 2007 Page 20 of 332
REJ09B0349-0100
Table 4.4 SFR Information (4)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
00C0h A/D Register AD XXh
00C1h XXh
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Contr ol Regist er 2 ADCON2 00h
00D5h
00D6h A/D Contr ol Regist er 0 ADCON0 00h
00D7h A/D Contr ol Regist er 1 ADCON1 00h
00D8h D/A Register 0 DA0 00h
00D9h
00DAh D/A Register 1 DA1 00h
00DBh
00DCh D/A Control Register DACON 00h
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 00h
00E1h Port P1 Register P1 00h
00E2h Port P0 Direc ti on Register PD0 00h
00E3h Port P1 Direc ti on Register PD1 00h
00E4h
00E5h Port P3 Register P3 00h
00E6h
00E7h Port P3 Direc ti on Register PD3 00h
00E8h Port P4 Register P4 00h
00E9h Port P5 Register P5 00h
00EAh Port P4 Direction Register PD4 00h
00EBh Port P5 Direction Register PD5 00h
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h Pin Sele ct R e gi ster 2 PINSR2 00h
00F7h Pin Sele ct R e gi ster 3 PINSR3 00h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Register INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 00h
00FEh Port P1 Drive Capacity Control Register P1DRR 00h
00FFh
R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs)
Rev.1.00 Dec 14, 2007 Page 21 of 332
REJ09B0349-0100
Table 4.5 SFR Information (5)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary Register TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Counter Data Register TRESEC 00h
0119h Timer RE Compare Data Register TREMIN 00h
011Ah
011Bh
011Ch Timer RE Control Register 1 TRECR1 00h
011Dh Timer RE Control Register 2 TRECR2 00h
011Eh Timer RE Clock Source Select Register TRECSR 00001000b
011Fh
0120h T imer RC Mode Register TRCMR 01001000b
0121h Timer RC Control Register 1 TRCCR1 00h
0122h T imer RC Interrupt Enable Register TRCIER 01110000b
0123h Timer RC Status Register TRCSR 01110000b
0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b
0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b
0126h Timer RC Counter TRC 00h
0127h 00h
0128h T imer RC General Register A TRCGRA FFh
0129h FFh
012Ah Timer RC General Register B TRCGRB FFh
012Bh FFh
012Ch Timer RC General Register C TRCGRC FFh
012Dh FFh
012Eh Timer RC General Register D TRCGRD FFh
012Fh FFh
0130h Timer RC Control Register 2 TRCCR2 000111 11b
0131h Timer RC Digital Filter Function Select Register TRCDF 00h
0132h Timer RC Output Master Enable Register TRCOER 01111111b
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs)
Rev.1.00 Dec 14, 2007 Page 22 of 332
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Table 4.6 SFR Information (6)(1)
X: Undefined
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Address Register Symbol After reset
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h Comparator 0 Control Register ACCR0 00001000b
0175h Comparator 1 Control Register ACCR1 00001000b
0176h
0177h Comparator Mode Register ACMR 00h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
R8C/2E Group, R8C/2F Group 4. Special Function Registers (SFRs)
Rev.1.00 Dec 14, 2007 Page 23 of 332
REJ09B0349-0100
Table 4.7 SFR Information (7)(1)
X: Undefined
NOTES:
1. The blank regions are reserved. Do not access locations in these regions.
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Address Register Symbol After reset
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh Option Function Select Register OFS (Note 2)
R8C/2E Group, R8C/2F Group 5. Resets
Rev.1.00 Dec 14, 2007 Page 24 of 332
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5. Resets
The following resets are implemented: hardware reset, power-on reset, voltage monitor 1 reset, voltage monitor 2 reset,
watchdog timer reset, and software reset.
Table 5.1 lists the Reset Names and Sources. Figure 5.1 shows the Block Diagram of Reset Circuit.
Figure 5.1 B lock Diag ra m of Rese t Circui t
Tab le 5.1 Reset Name s an d Sour ce s
Reset Name Source
Hardware reset Input vo ltage of RESET pin is held “L”
Power-on reset VCC rises
Voltage moni tor 1 reset VCC falls (monitor voltage: Vdet1)
Voltage moni tor 2 reset VCC falls (monitor voltage: Vdet2)
Watchdog timer reset Underflow of watchdog timer
Software reset Write 1 to PM03 bit in PM0 register
RESET
Power-on reset
circuit
Voltage
detection
circuit
Watchdog
timer
CPU
SFRs
b5 bit in VCA2
register
SFRs
Bits VCA13, VCA26 , VCA27 ,
VW1C2, VW 1C3,
VW2C2, VW 2C3
Pin, CPU, and
SFR bits other than
those listed above
VCC
Hardware reset
Power-on reset
Voltage monitor 1 reset
Watchdog timer
reset
Software re set
VCA13: Bit in VCA1 regi ster
VCA26, VCA27: Bits in VCA2 register
VW1C2, VW1C3: Bits in VW1C register
VW2C2, VW2C3: Bits in VW2C register
Voltage mo nit o r 2
reset
R8C/2E Group, R8C/2F Group 5. Resets
Rev.1.00 Dec 14, 2007 Page 25 of 332
REJ09B0349-0100
Table 5.2 shows the Pin Functions while RESET Pin Level is “L”, Figure 5.2 shows the CPU Register Status after
Reset, Figure 5.3 shows the Reset Sequence, and Figure 5.4 shows the OFS Register.
Figure 5.2 CPU Register Status after Reset
Figure 5.3 Reset Sequence
Table 5.2 Pin Functions while RESET Pin Level is “L”
Pin Name Pin Functions
P0, P1 Input port
P3_1, P3_3 to P3_7 Input port
P4_2, P4_5 to P4_7 Input port
P5_3, P5_4 Input port
b19 b0
Interrupt table register(INTB)
Program counter(PC)
User stack pointer(USP)
Interrupt stack pointer(ISP)
Static base register(SB)
Content of addresses 0FFFEh to 0FFFCh
Flag register(FLG)
C
IPL DZSBOIU
b15 b0
b15 b0
b15 b0
b8 b7
b15 b0
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Data register(R0)
Data register(R1)
Data register(R2)
Data register(R3)
Address register(A0)
Address register(A1)
Frame base register(FB )
00000h
0000h
0000h
0000h
0000h
Start time of f lash memory
(CPU clock × 14 cycles)
0FFFCh 0FFFEh
0FFFDh Content of reset vector
CPU clock
Address
(internal addre s s
signal)
NOTES:
1. Hardware reset.
2. When the “L” input width to the RESET pin is set to fOCO-S clock × 32 cycles or more, setting the RESET pin to “H” also sets the internal
reset sig nal to “H” at the same.
CPU clock × 28 cycles
fOCO-S clock × 32 cycles(2)
fOCO-S
Internal reset
signal
RESET pin
10 cycles or more are needed(1)
R8C/2E Group, R8C/2F Group 5. Resets
Rev.1.00 Dec 14, 2007 Page 26 of 332
REJ09B0349-0100
Figure 5.4 OFS Register
Opti on Fu nct i on Select Register(1)
Symbol Address Wh en Shipping
OFS 0FFFFh FFh(2)
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2.
—
(b5) Reserved bit Set to 0. RW
—
(b4) Reserved bit Set to 1. RW
b3 b2 b1 b0b7 b6 b5 b4
101
WDTON RW
Watchdog timer start
select bit 0 : Starts w atchdog timer automatically after reset
1 : W a tchdog timer i s inactive after reset
1
—
(b1) RW
Reserved bit Set to 1.
ROMCR ROM code protect
di sabled bi t 0 : ROM code protect disabled
1 : RO MCP1 enabled RW
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : RO M code protect di sabled RW
If the block includi ng the OFS register is erased, FFh is set to the OFS register.
—
(b6) Reserved bit Set to 1. RW
CSPROINI Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
The OFS register is on the flash memory. Write to the OFS register with a program. After writing is completed, do not
write additions to the OFS register.
R8C/2E Group, R8C/2F Group 5. Resets
Rev.1.00 Dec 14, 2007 Page 27 of 332
REJ09B0349-0100
5.1 Hardware Reset
A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the suppl y voltage
meets the recommended operating conditions, pins, CPU, and SFRs are all reset (refer to Table 5.2 Pin Functions
while RESET Pin Level is “L”). When the input level applied to the RESET pin changes from “L” to “H”, a
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
Refer to 4. Special Function Registers (SFRs) for the state of the SFRs after reset.
The internal RAM is not reset. If the RESET pin is pulled “L” while writing to the internal RAM is in progress, the
contents of internal RAM will be undefined.
Figure 5.5 shows a n Example of Hardware Reset Circuit and O peration and Figure 5.6 shows an Example of
Hardware Reset Circuit (Usage Example of External Supply Voltage Detection Circuit) and Operation.
5.1.1 When Power Supply is Stable
(1) Apply “L” to the RESET pin.
(2) Wait for 10 µs or more.
(3) Apply “H” to the RESET pin.
5.1.2 Power On
(1) Apply “L” to the RESET pin.
(2) Let the supply voltage increase until it meets the recommended operating conditions.
(3) Wait for td(P-R) or more to allow the internal power supply to stabilize (refer to 21. Electrical
Characteristics).
(4) Wait for 10 µs or more.
(5) Apply “H” to the RESET pin.
R8C/2E Group, R8C/2F Group 5. Resets
Rev.1.00 Dec 14, 2007 Page 28 of 332
REJ09B0349-0100
Figure 5.5 Example of Hardware Reset Circuit and Operation
Figure 5.6 Ex a m ple o f Hard wa re Rese t Circ ui t (Us a ge Exam pl e of Exte rnal Sup pl y Voltage
Detection Circuit) and Operation
RESET
VCC VCC
RESET
2.2 V
0 V 0.2 VCC or below
td(P-R) + 10 µs or more
0 V
NOTE:
1. Refer to 21. Electrical Characteristics.
RESET VCC VCC
RESET
2.2 V
0 V
td(P-R) + 10 µs or more
0 V
5 V
5 V
Example when
VCC = 5 V
Supply volt ag e
detection circuit
NOTE:
1. Refer to 21. Electrical Characteristics.
R8C/2E Group, R8C/2F Group 5. Resets
Rev.1.00 Dec 14, 2007 Page 29 of 332
REJ09B0349-0100
5.2 Power-On Reset Function
When the RESET pin is connected to the V CC pin via a pull-up resistor, and the VCC pin voltage level rises while
the rise gradient is trth or more, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, too, always keep the voltage to the RESET pin 0.8VCC or more.
When the input voltage to the VCC pin reaches the maximum 2.6 V or above, the low-speed on-chip oscillator
clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the internal reset signal is held
“H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-chi p os cillat or clo ck di vided by
8 is automatically selected as the CPU clock after reset.
Refer to 4. Special Function Registers (SFRs) for the states of the SFR after power-on reset.
Figure 5.7 shows an Example of Power-On Reset Circuit and Operation.
Figure 5.7 Example of Power-On Reset Circuit and Operation
RESET
VCC
4.7 kΩ
(reference)
NOTES:
1. Ensure that the voltage is 2.2 V or above during the sampling time.
2. The sampling time is fOCO-S divided by 1 × 4 cycles.
3. Refer to 21. Electrical Characteristics.
max. 2.6 V
Vpor1
Internal
reset signal
(“L” valid)
tw(por1) Sampling time(1, 2)
max. 2.6 V
1
fOCO-S × 32 1
fOCO-S × 32
Vpor2
2.2 V
External
Power VCC trth trth
R8C/2E Group, R8C/2F Group 5. Resets
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5.3 Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin drops the Vdet1 level or below, the pins, CPU, and SFR are
reset and a program
is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip oscillator
clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 1 does not reset some portions of the SFR. Refer to 4. Special Function Registers (SFRs) for
details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.4 Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input
voltage to the VCC pin. The voltage monitored is Vdet2.
When the input voltage to the VCC pin drops the Vdet2 level or below, the p ins, CPU, a nd SFR are reset and the
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below while
writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
5.5 Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its pins,
CPU, and SFR if the watchd og timer underflows. Then t he program beginning with t he address indicated by the
reset vector is executed. After reset, the low-speed on-chip oscillator clock divided by 8 is automatically selected as
the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog tim er underflows, the contents of internal RAM are undefined.
Refer to 13. Watchdog Timer for details of the watchdog timer.
5.6 Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program beginning with the address indicated by the reset vector is executed. After reset, the low-speed on-chip
oscillator clock divided by 8 is auto matically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for detai ls.
The internal RAM is not reset.
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
Rev.1.00 Dec 14, 2007 Page 31 of 332
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6. Voltage Detection Circuit
The voltage detection circuit monitors the input voltage to the VCC pin. This circuit can be used to monitor th e VCC
input voltage by a program. Alternately, voltage monitor 1 interru pt, voltage monitor 1 reset, voltage monitor 2
interrupt, and voltage monitor 2 reset can also be us ed.
Table 6.1 lists the Specifications of Voltage Detection Circuit and Figures 6.1 to 6.3 show the Block Diagrams. Figures
6.4 to 6.6 show the Associated Registers.
Figure 6.1 B lo ck Diag ra m of Voltage Detection Circuit
Table 6.1 Specifications of Voltage Detection Circuit
Item Voltage Detecti on 1 Voltage Detection 2
VCC Monitor Voltage to monitor Vde t1 Vdet2
Detection t a rg et Passing through Vdet1 by rising or
falling Passing through Vdet2 by ri si ng or
falling
Monitor VW1C3 bit in VW1C register VCA13 bit in VCA1 register
Whether VCC is higher or lower than
Vdet1 Whether VCC is higher or lower than
Vdet2
Process
When Voltage
is Detected
Reset Voltage monitor 1 reset Voltage monitor 2 reset
Reset at Vdet1 > VCC; restart CPU
operation after a specified time Reset at Vdet2 > VCC; restart CPU
operation after a specified time
Interrupt Voltage monitor 1 interrupt Voltage monitor 2 interrupt
Interrupt request at Vdet1 > VCC and
VCC > Vdet1 when digital filter is
enabled;
interrupt requ e s t at Vdet 1 > VC C or
VCC > Vdet1 when digital filter is
disabled
Interrupt request at Vdet2 > VCC and
VCC > Vdet2 when digital filter is
enabled;
interrupt requ e s t at Vdet 2 > VC C o r
VCC > Vdet2 when digital filter is
disabled
Digital Filter Switch
enabled/disabled Available Available
Sampling time (Divide-by-n of fOCO-S) × 4
n: 1, 2, 4, and 8 (Divide-by-n of fOCO-S) × 4
n: 1, 2, 4, and 8
≥ Vdet2
VCA27
+
-
VCC
b3
VCA13 bit
VCA1 register
Voltage detection 2
signal
Voltage detection 1
signal
Internal
reference
voltage
VCA26
+
-≥ Vdet1
b3
VW1C3 bit
VW1C register
Noise
filter
Noise
filter
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
Rev.1.00 Dec 14, 2007 Page 32 of 332
REJ09B0349-0100
Figure 6.2 Block Diagram of Voltage Monitor 1 Interrupt/Reset Generation Circuit
Figure 6.3 Block Diagram of Voltage Monitor 2 Interrupt/Reset Generation Circuit
+
-
1/2 1/2 1/2
Voltage detection 1 circuit
VCA26
VCC
Internal
reference
voltage
VW1C3
Noise filt er
(Filter width: 200 ns)
Voltage det ect ion 1 signal
is held “H” when VCA26 bit
is set to 0 (disabled)
Voltage
detection
1 signal
Digital
filter
fOCO-S
VW1F1 to VW1F0
= 00b
= 01b
= 10b
= 11b
VW1C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA26 bit is set to 0 (voltage
detection 1 circuit disabled), VW1C2
bit is set to 0
Voltage monitor 1 interrupt/reset generation circuit
VW1C0 to VW1C3 , VW1F0, VW1F1, VW1C6, VW1C7: Bit s in VW1C register
VCA26: Bit in VCA2 register
VW1C1
VW1C1
VW1C2
VW1C7
VW1C0
VW1C6
Non-maskable
interrupt signal
Voltage monitor 1
interrupt signal
Watchdog
timer interrupt
signal
Oscillation stop
detection
interrupt signal
Voltage monit or 1
reset signal
+
-
1/2 1/2 1/2
Voltage detection 2 circuit
VCA27
VCC
Internal
reference
voltage
VCA13
Noise filter
(Filter width: 200 ns)
Voltage detection 2 signal
is held “H” when VCA27 bit
is set to 0 (disabled)
Voltage
detection
2 signal
Digital
filter
fOCO-S
VW2F1 to VW2F0
= 00b
= 01b
= 10b
= 11b VW2C2 bit is set to 0 (not detected) by
writing 0 by a program.
When VCA27 bit is set to 0 (voltage
detection 2 circuit disabled), VW2C2
bit is set to 0
VW2C3
Watchdog timer block
Watchdog timer
underflow signal This bit is set to 0 (not detected) by writing 0
by a program.
Voltage monitor 2 interrupt/reset generation circuit
VW2C0 to VW2C3, VW2F0, VW2F1, VW2C6, VW2C7: Bits in VW2C register
VCA13: Bit in VCA1 register
VCA27: Bit in VCA2 register
VW2C1
VW2C1
VW2C2
VW2C7
VW2C0
VW2C6
Non-maskable
interrupt signal
Voltage monitor 2
interrupt signal
Watchdog
timer interrupt
signal
Oscillation stop
detection
interrupt signal
Voltage monitor 2
reset signal
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
Rev.1.00 Dec 14, 2007 Page 33 of 332
REJ09B0349-0100
Figure 6.4 R eg is te rs VCA1 an d VCA2
V ol tage Det ection Regi ster 1
Symbol Address After Reset(2)
VCA1 0031h 00001000b
Bit Symbol Bi t Name Function RW
NOTES:
1.
2. The softw are reset, watchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect thi s
register.
VCA13 Voltage detecti on 2 signal monitor
flag(1)
00
—
(b2-b0) RW
0 : VCC < Vdet2
1 : VCC ≥ Vdet2 or voltage detection 2
circuit disabled RO
Reserved bits
b0
0000
S e t to 0 .
0
b7 b6 b5 b4 b3 b2 b1
The VCA13 bi t is enabled when the VCA27 bit in the VCA2 register is set to 1 (vol tage detection 2 ci rcuit enabled ).
The VCA13 bi t is set to 1 (VCC ≥ Vdet 2) when the VCA27 bit in the VCA2 register i s set to 0 (voltage detection 2
circuit disabled).
—
(b7-b4) Reserved bits Set to 0. RW
V ol t age Detect i on Regis ter 2(1)
Symbol Address After Reset(4)
VCA2 0032h
B it Symbol Bit Name Functi o n RW
NOTES:
1.
2.
3.
4.
5.
Power-on reset or hardware reset : 00100000b
—
(b5) Reserved bit Set to 1. RW
—
(b4-b1) Reserved bits Set to 0. RW
b7 b6 b5 b4 b3 b2 b1 b0
10000
Voltage detection 2 enable
bit(3) 0 : Vol tage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled RW
VCA26 Voltage detection 1 enable
bit(2) 0 : Vol tage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled RW
Use the VCA20 bi t only when entering to wait mode. T o set the VCA20 bit, follow the procedure shown in Figure
10.8 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
VCA20 Internal power low
consumption enable bit(5) 0 : Disables low consumption
1 : Enables low consumption RW
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bi t is set to 1 from 0, the voltage detection circuit waits for td(E-A) to elapse before starti ng
operation.
To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bi t to 1.
After the VCA27 bi t is set to 1 from 0, the voltage detection circuit waits for td(E-A) to elapse before starti ng
operation.
Software reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
VCA27
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
Rev.1.00 Dec 14, 2007 Page 34 of 332
REJ09B0349-0100
Figure 6.5 VW1C Register
Volta
g
e Moni t or 1 Circ ui t Cont rol Re
g
iste
r
(1)
Symbol Address After Reset(8)
VW1C 0036h 00001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
b2
0 : Not detected
1 : Vdet1 pass detected RW
b1 b0b3b7 b6 b5 b4
VW1C0 RW
Voltage monitor 1 interrupt/reset
enable bit(6) 0 : Disable
1 : Enable
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabl ed)
RW
VW1C2 Voltage change detecti o n
flag(3, 4, 8)
VW1C1
Voltage monitor 1 digital filter
disable mode select bit(2)
VW1C3 Voltage detection 1 signal
monitor flag(3, 8)
VW1F1 RW
Sampl ing clock sel ect bits b5 b4
0 0 : fOCO-S di vi ded by 1
0 1 : fOCO-S di vi ded by 2
1 0 : fOCO-S di vi ded by 4
1 1 : fOCO-S di vi ded by 8
VW1F0 RW
0 : VCC < Vdet1
1 : VCC ≥ Vdet1 or voltage detection 1
circuit di sabled RO
VW1C6 Voltage monitor 1 circuit mode
select bit (5) 0 : Voltage monitor 1 interrupt mode
1 : Voltage monitor 1 reset mode RW
VW1C7
Voltage monitor 1 interrupt/reset
generation conditi on sel ect
bit(7,9)
0 : When VCC reaches Vdet1 or above
1 : When VCC reaches Vdet1 or below RW
When the VW1C6 bit is set to 1 (voltage monitor 1 reset mode), set the VW1C7 bit to 1 (when VCC reaches Vdet1 or
bel ow). (Do not set to 0.)
Set the PRC3 bit in the PRCR register to 1 (rewrite enabl e) before w riting to the VW1C register.
To use the voltage monitor 1 interrupt to exit stop mode and to return again, write 0 to the VW1C1 bit before writing
1.
Bits VW1C2 and VW1C3 are enabled when the VCA26 bi t in the VCA2 register is set to 1 (voltage detecti on 1 ci rcuit
enabled).
Set thi s bit to 0 by a program. When 0 i s w ri tten by a program, it is set to 0 (and remains unchanged even i f 1 i s
w ritten to it).
The VW1C6 bit i s enabl ed when the VW1 C0 bit i s set to 1 (vol tage moni tor 1 interrupt/enabl ed reset).
The VW1C0 bit i s enabl ed when the VCA26 bit in the VCA2 register i s set to 1 (voltage detection 1 circuit enabl ed ).
Set the VW1C0 bi t to 0 (di sable) wh en the VCA26 bit is set to 0 (voltage detection 1 circuit disabled).
The VW1C7 bit i s enabl ed when the VW1C1 bit is set to 1 (digital filter disabled mode).
Bits VW1C2 and VW1C3 remain unchanged after a softw are reset, w atchdog timer reset, voltage monitor 1 reset, or
voltage monitor 2 reset.
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
Rev.1.00 Dec 14, 2007 Page 35 of 332
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Figure 6.6 VW2C Register
Volta
g
e Moni t or 2 Circ ui t Cont rol Re
g
iste
r
(1)
Symbol Address After Reset(8)
VW2C 0037h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
b3 b2
0 : Not detected
1 : VCC has crossed Vdet2 RW
b1 b0b7 b6 b5 b4
VW2C0 RW
Voltage monitor 2 interrupt/reset
enable bit(6) 0 : Disable
1 : Enable
0 : Digital filter enabled mode
(digital filter circuit enabled)
1 : Digital filter disabled mode
(digital filter circuit disabl ed)
RW
VW2C2 Voltage change detecti o n
flag(3,4,8)
VW2C1
Voltage monitor 2 digital filter
disable mode select bit(2)
VW2C3 WDT detection flag(4,8)
VW2F1 RW
Sampl ing clock sel ect bits b5 b4
0 0 : fOCO-S di vi ded by 1
0 1 : fOCO-S di vi ded by 2
1 0 : fOCO-S di vi ded by 4
1 1 : fOCO-S di vi ded by 8
VW2F0 RW
0 : Not detected
1 : Detected RW
VW2C6 Voltage monitor 2 circuit mode
select bit (5) 0 : Voltage monitor 2 interrupt mode
1 : Voltage monitor 2 reset mode RW
VW2C7
Voltage monitor 2 interrupt/reset
generation conditi on sel ect
bit(7,9)
0 : When VCC reaches Vdet2 or above
1 : When VCC reaches Vdet2 or below RW
When the VW2C6 bit is set to 1 (voltage monitor 2 reset mode), set the VW2C7 bit to 1 (when VCC reaches Vdet2 or
bel ow). (Do not set to 0.)
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before writin g to the VW2C regi ster.
To use the voltage monitor 2 interrupt to exit stop mode and to return again, write 0 to the VW2C1
bit before writi ng 1.
The VW2C2 bit i s enabl ed when the VCA27 bit in the VCA2 register i s set to 1 (voltage detection 2 ci rcuit
enabled).
Set thi s bit to 0 by a program. When 0 i s w ri tten by a program, it is set to 0 (and remains unchanged even i f 1 is
w ritten to it).
The VW2C6 bit i s enabl ed when the VW2 C0 bit i s set to 1 (vol tage moni tor 2 interrupt/enables reset).
The VW2C0 bit i s enabl ed when the VCA27 bit in the VCA2 register i s set to 1 (voltage detection 2 ci rcuit
enabl ed). Set the VW2C0 bit to 0 (disable) when the VCA27 bit is set to 0 (voltage detection 2 circuit disabl e d).
The VW2C7 bit is enabled when the VW2C1 bit i s set to 1 (digi tal fi lter di sabled mode).
Bits VW2C2 and VW2C3 remain unchanged after a software reset, w atchdog timer reset, voltage monitor 1 reset, or
voltage moni tor 2 reset.
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
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6.1 VCC Input Voltage
6.1.1 Monitoring Vdet1
Set the VCA 26 bit in the VCA2 r egister to 1 (vol tage detection 1 circuit enabled ). After td(E-A ) has elapsed
(refer to 21. Electrical Characteristics), Vdet1 can be monitored by the VW1C3 bit in the VW 1C register.
6.1.2 Monitoring Vdet2
Set the VCA 27 bit in the VCA2 r egister to 1 (vol tage detection 2 circuit enabled ). After td(E-A ) has elapsed
(refer to 21. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the VCA 1 regi ster.
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
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6.2 Voltage Monitor 1 Interrupt and Voltage Monitor 1 Reset
Ta ble 6.2 lists the Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset. Figure 6.7
shows an Example of Voltage Monitor 1 Interrupt an d Voltage Monitor 1 Reset Operation. To use the voltage
monitor 1 interrupt or voltage monitor 1 reset to exit stop mode, set the VW1C1 bit in the VW1C register to 1
(digital filter disabled).
NOTES:
1. Set the VW1C7 bit to 1 (when VCC reaches Vdet1 or below) for the voltage monitor 1 reset.
2. When the VW1C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
Table 6.2 Procedure for Setting Bits Associated with Voltage Monitor 1 Interrupt and Reset
Step When Using Digital Filter When Not Using Digital Filter
Voltage Monitor 1
Interrupt Voltage Monitor 1
Reset Voltage Monitor 1
Interrupt Voltage Monitor 1
Reset
1 Set the VCA26 bit in the VCA2 register to 1 (voltage detection 1 circuit enabled)
2 Wait for td(E-A)
3Select the sampling clock of the digital filter
by the VW1F0 to VW1F1 bits in the VW1C
register
Select the timing of the interrupt and reset
request by the VW1C7 bit in the VW1C
register(1)
4(2) Set the VW1C1 bit in the VW1C register to 0
(digital filter enabled) Set the VW1C1 bit in the VW1C register to 1
(digital filter disabled)
5(2) Set the VW1C6 bit in
the VW1C register to
0 (voltage monitor 1
interrupt mode)
Set the VW1C6 bit in
the VW1C register to
1 (voltage monitor 1
reset mode)
Set the VW1C6 bit in
the VW1C register to
0 (voltage monitor 1
interrupt mode)
Set the VW1C6 bit in
the VW1C register to
1 (voltage monitor 1
reset mode)
6 Set the VW1C2 bit in the VW1C register to 0 (passing of Vdet1 is not detected)
7 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on) −
8 Wait for 4 cycles of the sampling clock of the
digital filter − (No wait time required)
9 Set the VW1C0 bit in the VW1C register to 1 (voltage moni to r 1 inte r ru pt /re se t en ab le d)
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
Rev.1.00 Dec 14, 2007 Page 38 of 332
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Figure 6.7 Example of Volt age Monitor 1 Interrupt and Voltage Monitor 1 Reset Operation
Vdet1
VW1C3 bit
Internal reset signal
(VW1C6 = 1)
VCC
The above applies under the following conditions.
• VCA26 bit in VCA2 register = 1 (voltage detection 1 circuit enabled)
• VW1C0 bit in VW1C register = 1 (vol tage monitor 1 interrupt and vo ltage monitor 1 reset enabled)
0
1
4 cycles of sampling clock of
digital filter
VW1C2 bit 0
1
When VW1C1 bit is set to 0
(digital filter enabled)
VW1C2 bit 0
1
When VW1C1 bit is set to 1
(digital filter disabled) and
VW1C7 bit is set to 0
(Vdet1 or above)
VW1C1, VW1C2, VW1C3, VW1C6, VW1C7: Bit in VW1C Register
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Voltage m on ito r 1
interrupt request
(VW1C6 = 0)
Voltage m on ito r 1
interrupt request
(VW1C6 = 0)
VW1C2 bit 0
1
When VW1C1 bit is set to 1
(digital filter disabled) and
VW1C7 bit is set to 1
(Vdet1 or below)
Voltage m on ito r 1
interrupt request
(VW1C6 = 0)
Internal reset signal
(VW1C6 = 1)
4 cycles of sampling clock of
digital filter
Set to 0 by a program
Set to 0 by interrupt
request
acknowledgement
Set to 0 by a program
Set to 0 by interrupt
request ackn owl ed gement
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
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6.3 Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset
Ta ble 6.3 lists the Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset. Figure 6.8
shows an Example of Voltage Monitor 2 Interrupt an d Voltage Monitor 2 Reset Operation. To use the voltage
monitor 2 interrupt or voltage monitor 2 reset to exit stop mode, set the VW2C1 bit in the VW2C register to 1
(digital filter disabled).
NOTES:
1. Set the VW2C7 bit to 1 (when VCC reaches Vdet2 or below) for the voltage monitor 2 reset.
2. When the VW2C0 bit is set to 0, steps 3, 4, and 5 can be executed simultaneously (with 1
instruction).
Table 6.3 Procedure for Setting Bits Associated with Voltage Monitor 2 Interrupt and Reset
Step When Using Digital Filter When Not Using Digital Filter
Voltage Monitor 2
Interrupt Voltage Monitor 2
Reset Voltage Monitor 2
Interrupt Voltage Monitor 2
Reset
1 Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled)
2 Wait for td(E-A)
3Select the sampling clock of the digital filter
by the VW2F0 to VW2F1 bits in the VW2C
register
Select the timing of the interrupt and reset
request by the VW2C7 bit in the VW2C
register(1)
4Set the VW2C1 bit in the VW2C register to 0
(digital filter enabled) Set the VW2C1 bit in the VW2C register to 1
(digital filter disabled)
5(2) Set the VW2C6 bit in
the VW2C register to
0 (voltage monitor 2
interrupt mode)
Set the VW2C6 bit in
the VW2C register to
1 (voltage monitor 2
reset mode)
Set the VW2C6 bit in
the VW2C register to
0 (voltage monitor 2
interrupt mode)
Set the VW2C6 bit in
the VW2C register to
1 (voltage monitor 2
reset mode)
6 Set the VW2C2 bit in the VW2C register to 0 (passing of Vdet2 is not detected)
7 Set the CM14 bit in the CM1 register to 0
(low-speed on-chip oscillator on) −
8 Wait for 4 cycles of the sampling clock of the
digital filter − (No wait time required)
9 Set the VW2C0 bit in the VW2C register to 1 (voltage moni to r 2 inte r ru pt /re se t en ab le d)
R8C/2E Group, R8C/2F Group 6. V oltage Detection Circuit
Rev.1.00 Dec 14, 2007 Page 40 of 332
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Figure 6.8 Example of Volt age Monitor 2 Interrupt and Voltage Monitor 2 Reset Operation
Vdet2
VCA13 bit
Internal reset signal
(VW2C6 = 1)
VCC
The above applies under the following conditions.
• VCA27 bit in VCA2 register = 1 (voltage detection 2 circuit enabled)
• VW2C0 bit in VW2C register = 1 (vol tage monitor 2 interrupt and vo ltage monitor 2 reset enabled)
0
1
4 cycles of sampling clock of
digital filter
VW2C2 bit 0
1
When VW2C1 bit is set to 0
(digital filter enabled)
VW2C2 bit 0
1
When VW2C1 bit is set to 1
(digital filter disabled) and
VW2C7 bit is set to 0
(Vdet2 or above)
VCA13: Bit in VCA1 reg i ster
VW2C1, VW2C2, VW2C6, VW2C7: Bits in VW2C register
Set to 0 by interrupt request
acknowledgement
Set to 0 by a program
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Voltage monitor 2
interrupt request
(VW2C6 = 0)
VW2C2 bit 0
1
When VW2C1 bit is set to 1
(digital filter disabled) and
VW2C7 bit is set to 1
(Vdet2 or below)
Voltage monitor 2
interrupt request
(VW2C6 = 0)
Internal reset signal
(VW2C6 = 1)
4 cycles of sampling clock of
digital filter
Set to 0 by a program
Set to 0 by interrupt
request
acknowledgement
Set to 0 by a program
Set to 0 by interrupt
request ackn owl ed gement
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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7. Programmable I/O Ports
There are 25 programmable Input/Output ports (I/O ports) P0, P1, P3_1, P3_3 to P3_7, P4_5, P5_3, and P5_4. Also,
P4_6 and P4_7 can be used as input-only ports if the XIN clock oscillation circuit is not used, and the P4_2 can be used
as an input-only port if the A/D converter is not used.
Table 7.1 lists an Overview of Programmable I/O Ports.
NOTES:
1. In input mode, whether an internal pull-up resistor is connected or not can be selected by registers
PUR0 and PUR1.
2. When the A/D converter is not used, this port can be used as the input-only port.
3. When the XIN clock oscillation circuit is not used, these ports can be used as the input-only ports.
7.1 Functions of Programmable I/O Ports
The PDi_j (j = 0 to 7) bit in the PDi (i = 0, 1, 3 to 5) register control s I/O of the po rts P0, P1, P3_1, P3_3 t o P3_7,
P4_5, P5_3, and P5_4. The Pi register consists of a port latch to hold output data and a circuit to read pin states.
Figures 7.1 to 7.5 show the Configurations of Programmable I/O Ports. Table 7.2 lists the Functions of
Programmable I/O Ports. Also, Figure 7.7 shows the PDi (i = 0, 1, and 3 to 5) Register. Figure 7.8 shows the Pi (i =
0, 1, and 3 to 5) Register, Figure 7.9 shows Registers PINSR2 and PINSR3, Figure 7.10 shows the PMR Register,
Figure 7.11 shows Registers PUR0 and PU R1, and Fi gure 7.12 shows the P1DRR Register.
i = 0, 1, 3 to 5 j = 0 to 7
NOTE:
1. Nothing is assigned to bits PD3_0, PD3_2, PD4_0 to PD4_4, PD4_6, and PD4_7.
Tab le 7. 1 Overview of Programmable I/O Ports
Ports I/O Type of Output I/O Setting Internal Pull-Up Resister
P0, P1 I/O CMOS3 State Set per bit Set every 4 bits(1)
P3_1, P3_3 to P3_7 I/O CMOS3 State Set per bit Set every 2 bits, 4 bits(1)
P4_5 I/O CMOS3 State Set per bit Set every bit(1)
P5_3, P5_4 I/O CMOS3 State Set per bit Set every bit(1)
P4_2(2)
P4_6, P4_7(3) I (No output function) None None
Table 7.2 Functions of Programmable I/O Ports
Operation When
Accessing
Pi Register
Value of PDi_j Bit in PDi Register(1)
When PDi_j Bit is Set to 0 (Input Mode) When PDi_j Bit is Set to 1 (Output Mode)
Reading Read pin input level Read the port latch
Writing Write to the port latch Write to th e port latch. Th e value written to
the port latch is output from the pin.
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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7.2 Effect on Peripheral Functions
Programmable I/ O port s function as I/O ports for peripheral functions (Refer to Table 1.7 Pin Name Information
by Pin Number).
Table 7.3 lists the Setting of PDi_j Bit when Functioning as I/O Ports for Peripheral Functions (i = 0, 1, 3 to 5 j = 0
to 7). Refer to the description of each function for information on how to set peripheral functions.
7.3 Pins Other than Programmable I/O Ports
Figure 7.6 shows the Configuratio n of I/ O Pins.
Table 7.3
Setting of PDi_j Bit when Functioning as I/O Port s for Peripheral Functions (i = 0, 1, 3 to 5 j = 0 to 7)
I/O of Peripheral Functions PDi_j Bit Settings for Shared Pin Functions
Input Set this bit to 0 (input mode).
Output This bit can be set to either 0 or 1 (output regardless of the port setting)
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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Figure 7.1 Configuration of Programmable I/O Ports (1)
P0
Port latch
Data bus
Pull-up selection
Analog input
Direction
register
NOTE:
1. symbolizes a parasit ic diode.
Ensure the input voltage to each port does not exceed VCC.
(Note 1)
(Note 1)
P1_0 to P1_3
1
Output from individual peripheral function
Analog input
Port latchData bus
Pull-up selection
Input to individual peripheral function
P1_4
1
Port latchData bus
Pull-up selection
Output from individual peripheral function
Direction
register
Direction
register
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Drive capacity select
Drive capacity select
Drive capacity select
Drive capacity select
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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Figure 7.2 Configuration of Programmable I/O Ports (2)
P1_6
Direction
register
Data bus
Pull-up selection
Input to individual peripheral f unction
1
Output from individual peripheral function
P1_5 and P1_7
Direction
register
Data bus
Pull-up selection
Input to individual peripheral function
1
Input to exte rnal interrupt Digital
filter
Output from individual peripheral function
Port latch
Port latch
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Drive capacity select
Drive capacity select
Drive capacity select
Drive capacity select
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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Figure 7.3 Configuration of Programmable I/O Ports (3)
P3_4, P3_5, and P3_7
1
Direction
register
Data bus
Pull-up selection
Input to individual peripheral f unction
Output from in dividual p eripheral function
P3_1
Direction
register
Data bus
Pull-up selection
1
Output from individual p eripheral function
P3_3 and P3_6
Direction
register
Data bus
Pull-up selection
Input to individual peripheral funct ion
1
Output from in dividual p eripheral function
Input to external interrupt Digital
filter
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage t o each port does not exceed VCC.
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Port latch
Port latch
Port latch
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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Figure 7.4 Configuration of Programmable I/O Ports (4)
P4_2/VREF
Data bus
(Note 1)
2. This pin is pulled up in one of the f ollowing conditions:
• CM05 = CM13 = 1
• CM10 = CM13 = 1
• CM10 = 1
(Note 1)
P4_5
Direction
register
Data bus
Pull-up selection
Input to individual peripheral function
1
Output from individual p eripheral function
Input to external interrupt Digital
filter
(Note 1)
(Note 1)
P4_6/XIN
Data bus
P4_7/XOUT
Data bus
CM05: Bit in CM0 register
CM10, CM13: Bits in CM1 register
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
NOTES:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Port latch
CM05 CM11
RfXIN
XIN
oscillation
circuit
CM13
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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Figure 7.5 Configuration of Programmable I/O Ports (5)
Figure 7.6 Configuration of I/O Pins
P5_3 and P5_4
Direction
register
Data bus
Pull-up selection
Input to indivi dual peripheral function
1
Output f rom in divi du al perip he ral func ti on
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage to each port does not exceed VCC.
Port latch
(Note 1)
(Note 1)
MODE
MODE signal input
RESET
RESET signal input
NOTE:
1. symbolizes a parasitic diode.
Ensure the input voltage t o each port does not exceed VCC.
(Note 1)
(Note 1)
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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Figure 7.7 PDi (i = 0, 1, and 3 to 5) Register
Port Pi Direction Register (i = 0, 1, 3 to 5)(1, 2, 3, 4)
Symbol Address After Reset
PD0 00E2h 00h
PD1 00E3h 00h
PD3 00E7h 00h
PD4 00EAh 00h
PD5 00EBh 00h
Bit Symbol Bi t Name Function RW
NOTES:
1.
2.
3.
4.
Set the PD0 register by using the next instructi o n after setting the PRC2 bit in the PRCR regi ster to 1 (write enable).
PDi_6
RW
PDi_7 Port Pi_7 direction bit RW
PDi_5
b3 b2
PDi_2
b1 b0
PDi_1
PDi_0
b7 b6 b5 b4
RW
RW
Port Pi_5 direction bit
RW0 : Input mode
(functions as an input port)
1 : O utput mode
(functions as an output port)
RW
RW
Port Pi_6 direction bit RW
Port Pi_0 direction bit
Port Pi_1 direction bit
Port Pi_4 direction bit
Port Pi_2 direction bit
PDi_4
Bits PD4_0, PD4_1, PD4_3, PD4_4, PD4_6, and PD4_7 i n the PD4 register are unavail able on this MCU.
If it is necessary to set bits D4_0, PD4_1, PD4_3, PD4_4, PD4_6, and PD4_7, set to 0 (input mode). When read, the
content is 0.
Bits PD5_0 to PD5_2 and PD5_5 to PD5_7 in the PD5 register are unavailable on thi s MCU.
If it is necessary to set bits PD5_0 to PD5_2 and PD5_5 to PD5_7, set to 0 (input mode). When read, the content is 0.
Bits PD3_0 and PD3_2 in the PD3 register are unavailable on this MCU.
If it is necessary to set bits PD3_0 and PD3_2, set to 0 (input mode). When read, the content is 0.
PDi_3 Port Pi_3 direction bit
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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Figure 7.8 Pi (i = 0, 1, and 3 to 5) Register
Port Pi Register (i = 0, 1, 3 to 5)(1, 2, 3)
Symbol Address After Reset
P0 00E0h 00h
P1 00E1h 00h
P3 00E5h 00h
P4 00E8h 00h
P5 00E9h 00h
Bit Symbol Bi t Name Function RW
NOTES:
1.
2.
3.
Bits P4_0 to P4_4, P4_6, and P4_7 in the P4 register are unavailable on this MCU.
If it is necessary to set bits P4_0 to P4_4, P4_6, and P4_7, set to 0 (“L” level). When read, the content is 0.
Bits P5_0 to P5_2, P5_5 to P5_7 in the P5 register are unavailabl e on this MCU.
If it is necessary to set bits P5_0 to P5_2, P5_5 to P5_7, set to 0 (“L” level). When read, the content i s 0.
Pi_7
Pi_6
RW
Bits P3_0 and P3_2 in the P3 register are unavailable on this MCU.
If it is necessary to set bits P3_0 and P3_2, set to 0 (“L” level ). When read, the content i s 0.
b3 b2 b1 b0
Pi_1
Pi_5
Pi_0
Pi_2
Pi_4
Pi_3
b7 b6 b5 b4
Port Pi_0 bit
Port Pi_1 bit
Port Pi_7 bit
Port Pi_5 bit
Port Pi_4 bit
Port Pi_3 bit
RW
Port Pi_6 bit RW
Port Pi_2 bit
RW
The pin level of any I/O port w hi ch i s set
to input mode can be read by reading the
corresponding bit in thi s register. T he pin
l evel of any I/O port which is set to output
mode can be controlled by writi ng to the
corresponding bit in thi s register.
0 : “L” le vel
1 : “H” le vel
RW
RW
RW
RW
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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Figure 7.9 Registers PINSR2 and PINSR3
Figure 7.10 PMR Regist er
Pin Select Register 2
Symbol Address After Reset
PINSR2 00F6h 00h
Bit Symbol Bit Name Functi on RW
0 : P3_1
1 : P1_3
TRBO pin select bit
RW
RW
RW
Set to 0. W hen read, the content is 0.
Set to 0. W hen read, the content is 0.Reserved bits
Reserved bit
TRBOSEL
000
b7 b6 b5 b4
—
(b7)
—
(b5-b0)
b3 b2
0b1
00 b0
0
P i n Select Register 3
Symbol Address After Reset
PINSR3 00F7h 00h
Bit Symbol Bit Name Function RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
TRCIODSEL TRCIOD pin select bit 0 : P5_4
1 : P3_5
—
(b5)
—
(b7-b6)
Set to 1. Whe n read, the content is 0.Reserved bit
RW
RW
RW
—
RW
TRCIOCSEL
—
(b2-b0)
1
Reserved bits Set to 1. When read, the content is 0.
TRCIOC pin select bit
b7 b6 b5 b4 b0
1
0 : P5_3
1 : P3_4
b3 b2
1b1
1
P ort M ode Regi s te
r
Symbol Address After Reset
PMR 00F8h 00h
Bit Symbol Bit Name Function RW
INT1
_
___ pi n sel ect bi t
000
b7 b6 b5 b4 b0b3 b2 b1
INT1SEL 0 : P1_5, P1_7
1 : P3_6 RW
—
(b3-b1) —
Nothi ng is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7) —
Nothi ng is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b6-b4) Reserved bi t s Set to 0. RW
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
Rev.1.00 Dec 14, 2007 Page 51 of 332
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Figure 7.11 Registers PUR0 and PUR1
Figure 7.12 P1DRR Register
P ull-Up Control Regi ster 0
Symbol Address After Reset
PUR0 00FCh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
RW
RW
RW
RW
0
RW
P0_4 to P0_7 pull-up(1)
P0_0 to P0_3 pull-up(1)
PU03 P1_4 to P1_7 pull -up(1)
P1_0 to P1_3 pull-up(1)
PU01
b0
PU00
b7 b6 b5 b4
0b3 b2 b1
0 : Not pulled up
1 : Pulled up
When this bit is set to 1 (pul led up), the pi n whose direction bit is set to 0 (input mode) is pulled up.
PU07 RWP3_4 to P3_7 pull-up(1)
PU06 P3_1 and P3_3 pull-up(1) RW
—
(b5-b4)
PU02
Set to 0. When read, the content is 0.
0 : Not pulled up
1 : Pulled up
Reserved bits
P ul l -Up Cont rol Regi s ter 1
Symbol Address After Reset
PUR1 00FDh 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
b0
0
—
Wh en this bit is set to 1 (pulled up), the pi n whose direction bit i s set to 0 (input mode) is pulled up.
b3 b2 b1b7 b6 b5 b4
—
(b7-b6) Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
00
—
(b0) Reserved bit Set to 0. When read, the content is 0.
P5_3 pull-up(1)
—
(b5-b4) Reserved bi ts RW
PU11 P4_5 pull-up(1) RW
PU12 RW
RW
Set to 0. When read, the content is 0.
PU13 P5_4 pull-up(1)
0 : Not pulled up
1 : Pulled up
RW
P ort P 1 Drive Capaci ty Control Regi st er
Symbol Address After Reset
P1DRR 00FEh 00h
Bit Symbol Bit Name Function RW
NOTE:
1. Both “H” and “L” output are set to hig h drive capacity.
P1DRR7
P1DRR5
RW
Set P1 output transistor drive capacity
0 : Low
1 : High(1)
P1DRR2
P1_7 drive capacity
P1_3 drive capacity
P1DRR6 P1_6 drive capacity
b3 b2 b1 b0
P1DRR0
b7 b6 b5 b4
RW
P1_1 drive capacity
P1_0 drive capacity
P1DRR3 P1_2 drive capacity
P1DRR1 RW
RW
RW
P1DRR4
RW
P1_4 drive capacity RW
P1_5 drive capacity RW
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
Rev.1.00 Dec 14, 2007 Page 52 of 332
REJ09B0349-0100
7.4 Port Setting
Table 7.4 to Table 7.39 list the port setting.
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU00 bit in the PUR0 register to 1.
Ta ble 7.4 Port P0 _0 /AN 7
Register PD0 ADCON0 Function
Bit PD0_0 CH2 CH1 CH0 ADGSEL0
Setting
value
0 Other than 1110b Input port(1)
1 Other than 1110b Output port
0 1 1 1 0 A/D converter input (AN7)
Ta ble 7.5 Port P0 _1 /AN 6
Register PD0 ADCON0 Function
Bit PD0_1 CH2 CH1 CH0 ADGSEL0
Setting
value
0XXXX
Input port(1)
1 X X X X Output port
0 1 1 0 0 A/D converter input (AN6)
Tab le 7. 6 Port P0_2/AN5/ ACM P1
Register PD0 ADCON0 ACCR1 Function
Bit PD0_2 CH2 CH1 CH0 ADGSEL0 CM1E
Setting
value
0XXXX0
Input port(1)
1 X X X X 0 Output port
010100A/D converter input (AN5)
0 X X X X 1 ACMP1 input
Tab le 7. 7 Port P0_3/AN 4/ AVREF1
Register PD0 ADCON0 ACCR1 Function
Bit PD0_3 CH2 CH1 CH0 ADGSEL0 CM1E VR1SEL
Setting
value
0XXXX0X
Input port(1)
1 X X X X 0 X Output port
010000X
A/D converter input (AN4)
11
0 X X X X 1 0 AVREF1 input
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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REJ09B0349-0100
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU01 bit in the PUR0 register to 1.
Tab le 7. 8 Port P0_4/AN 3/TR E O/ ACM P0
Register PD0 TRECR1 ADCON0 ACCR0 Function
Bit PD0_4 TOENA CH2 CH1 CH0 ADGSEL0 CM0E
Setting
value
00XXXX0
Input port(1)
1 0 X X X X 0 Outp u t port
0 0 0 1 1 0 0 A/D converter input (AN3)
X 1 X X X X 0 TREO output
00XXXX1ACMP0 input
Tab le 7. 9 Port P0_5/AN 2/ AVREF0
Register PD0 ADCON0 ACCR0 Function
Bit PD0_5 CH2 CH1 CH0 ADGSEL0 CM0E VR0SEL
Setting
value
0XXXX0X
Input port(1)
XXXX0X
1 X X X X 0 X Output port
001000X
A/D converter input (AN2)
11
0 X X X X 1 0 AVREF0 input
Tab le 7. 10 Port P0_6/AN1/DA0
Register PD0 ADCON0 DACON ACCR0 Function
Bit PD0_6 CH2 CH1 CH0 ADGSEL0 DA0E VR0SEL
Setting
value
0XXXX0X
Input port(1)
11
1XXXX0X
Output port
11
000100X
A/D converter input (AN1)
11
0 X X X X 1 0 DA0 output
Tab le 7. 11 Port P0_7/AN0/DA1
Register PD0 ADCON0 DACON ACCR1 Function
Bit PD0_7 CH2 CH1 CH0 ADGSEL0 DA1E VR1SEL
Setting
value
0XXXX0X
Input port(1)
11
1XXXX0X
Output port
11
000000X
A/D converter input (AN0)
11
0 X X X X 1 0 DA1 output
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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REJ09B0349-0100
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
Tab le 7. 12 Port P1_0/KI0/AN8
Register PD1 KIEN ADCON0 Function
Bit PD1_0 KI0EN CH2 CH1 CH0 ADGSEL0
Setting
value
00XXXX
Input port(1)
1 0 X X X X Output port
01XXXX
KI0 input(1)
0 0 1 0 0 1 A/D converter input (AN8)
Tab le 7. 13 Port P1_1/KI1/AN9/TRCIOA/TRCTRG
Register PD1 KIEN Timer RC Setting ADCON0 Function
Bit PD1_1 KI1EN −CH2 CH1 CH0 ADGSEL0
Setting
value
0 0 Other than TRCIOA usage conditions X X X X Input port(1)
1 0 Other than TRCIOA usage conditions X X X X Output port
0 0 Other than TRCIOA usage conditions 1 0 1 1 A/D converter input (AN9)
0 1 Other than TRCIOA usage conditions X X X X KI1 input(1)
X0Refer to Table 7.14 TRCIOA Pin
Setting XXX X TRCIOA output
00Refer to Table 7.14 TRCIOA Pin
Setting XXX X TRCIOA input(1)
Ta bl e 7. 14 TRCIOA Pin Setti ng
Register TRCOER TRCMR TRCIOR0 TRCCR2 Function
Bit EA PWM2 IOA2 IOA1 IOA0 TCEG1 TCEG2
Setting
value
01001XX
Timer waveform output
(output compare function)
01XXX
011XXXX
Timer mode (input capture function)
1XX
00XXX01
PWM2 mode TRCTRG input
11X
Other than above Other than TRCIOA usage conditions
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
X: 0 or 1
X: 0 or 1
NOTE:
1. Pulled up by setting the PU02 bit in the PUR0 register to 1.
NOTE:
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.
Tab le 7. 15 Port P1_2/KI2/AN10/TRCIOB
Register PD1 KIEN Timer RC Setting ADCON0 Function
Bit PD1_2 KI2EN −CH2 CH1 CH0 ADGSEL0
Setting
value
0 0 Other than TRCIOB usage conditions X X X X Input port(1)
1 0 Other than TRCIOB usage conditions X X X X Output port
0 0 Other than TRCIOB usage conditions 1 1 0 1 A/D converter input (AN10)
0 1 Other than TRCIOB usage conditions X X X X KI2 input(1)
X0Refer to Table 7.16 TRCIOB Pin
Setting XXX X TRCIOB output
00
Refer to Table 7.16 TRCIOB Pin
Setting XXX X TRCIOB input(1)
Ta bl e 7. 16 TRCIOB Pin Setti ng
Register TRCOER TRCMR TRCIOR0 Function
Bit EB PWM2 PWMB IOB2 IOB1 IOB0
Setting
value
00XXXXPWM2 mode waveform output
0 1 1 X X X PWM mode waveform output
010001
Timer waveform output (output compare
function)
01X
01 0 1 X X Timer mode (input capture function)
1Other than above Other than TRCIOB usage conditions
Tab le 7. 17 Port P1_3/KI3/AN11/(TRBO)
Register PD1 KIEN Timer RB Setting ADCON0 Function
Bit PD1_3 KI3EN −CH2 CH1 CH0 ADGSEL0
Setting
value
0 0 Other than TRBO usage conditions X X X X Input port(1)
1 0 Other than TRBO usage conditions X X X X Output port
0 0 Other than TRBO usage conditions 1 1 1 1 A/D converter input (AN11)
0 1 Other than TRBO usage conditions X X X X KI3 input
X0
Refer to Table 7.18 TRBO Pin
Setting X X X X TRBO output
Tab le 7. 18 TRBO Pin Setting
Register PINSR2 TRBIOC TRBMR Function
Bit TRBOSEL TOCNT(1) TMOD1 TMOD0
Setting
value
1 0 0 1 Programmable waveform generation mode
1 0 1 0 Programmable one-shot generation mode
1 0 1 1 Programmable wait one-shot generation mode
1101
P1_3 output port
Other than above Other than TRBO usage conditions
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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REJ09B0349-0100
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the NCH bit in the U0C0 register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set the INT1SEL bit in the PMR register to 0 (P1_5, P1_7).
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
Tab le 7. 19 Port P1_4/TXD0
Register PD1 U0MR Function
Bit PD1_4 SMD2 SMD1 SMD0
Setting
value
0000
Input port(1)
1000Output port
X
001
TXD0 output(2)
100
101
110
Tab le 7. 20 Port P1_5/RXD0/(T RAI O) /(INT 1 )
Register PD1 TRAIOC TRAMR INTEN Function
Bit PD1_5 TIOSEL TOPCR(3) TMOD2 TMOD1 TMOD0 INT1EN
Setting
value
00XXXXX
Input port(1)
110010
100000
10XXXXX
Output port
10000X
0
0XXXXX
RXD0 input(1)
1 0 Other than 001b 0
1 0 Other than 000b, 001b 0 TRAIO input(1)
100001
INT1(2)
110011
1 0 Other than 000b, 001b 1 TRAIO input/INT1(1, 2)
X10001XTRAIO pulse output
Tab le 7. 21 Port P1_6/CLK0
Register PD1 U0MR Function
Bit PD1_6 CKDIR SMD2 SMD1 SMD0
Setting
value
0XXXX
Input port(1)
1 X Other than 001b Output port
X 0 0 0 1 CLK0 output
01XXX
CLK0 input(1)
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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REJ09B0349-0100
X: 0 or 1
NOTES:
1. Pulled up by setting the PU03 bit in the PUR0 register to 1.
2. Set the INT1SEL bit in the PMR register to 0 (P1_5, P1_7).
3. Set the TOPCR bit in the TRAIOC register to 0 in modes except for pulse output mode.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
NOTE:
1. Set the TOCNT bit in the TRBIOC register to 0 in modes except for programmable waveform generation mode.
Tab le 7. 22 Port P1_7/TRAIO/INT 1
Register PD1 TRAIOC TRAMR INTEN Function
Bit PD1_7 TIOSEL TOPCR(3) TMOD2 TMOD1 TMOD0 INT1EN
Setting
value
01 X XXXX
Input port(1)
010010
000000
11 X XXXX
Output port
00000X
0
0 0 Other than 000b, 001b 0 TRAIO input(1)
000001
INT1(2)
010011
0 0 Other than 000b, 001b 1 TRAIO input/INT1(1, 2)
X 0 0 0 0 1 X TRAIO pulse output
Tab le 7. 23 Port P3_1/TRBO
Register PD3 Timer RB Setting Function
Bit PD3_1 −
Setting
value
0 Other than TRBO usage conditions Input port(1)
1 Other than TRBO usage conditions Output port
X Refer to Table 7.24 TRBO Pin Setting TRBO output
Tab le 7. 24 TRBO Pin Setting
Register PINSR2 TRBIOC TRBMR Function
Bit TRBOSEL TOCNT(1) TMOD1 TMOD0
Setting
value
0 0 0 1 Programmable waveform generation mode
0 0 1 0 Programmable one-shot generation mode
0 0 1 1 Programmable wait one-shot generation mode
0110
P3_1 output port
Other than above Other than TRBO usage conditions
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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REJ09B0349-0100
NOTE:
1. Pulled up by setting the PU06 bit in the PUR0 register to 1.
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
X: 0 or 1
Tab le 7. 25 Port P3_3/INT3 /TRCCLK
Register PD3 TRCCR1 INTEN Function
Bit PD3_3 TCK2 TCK1 TCK0 INT3EN
Setting
value
0 Other than 101b 0 Input port(1)
1 Other than 101b 0 Output port
0 Other than 101b 1 INT3 input(1)
0101 0
TRCCLK input(1)
Tab le 7. 26 Port P3_4/(TRCIO C )
Register PD3 Timer RC setting Function
Bit PD3_4 −
Setting
value
0Other than TRCIOC usage conditions Input port(1)
Other than TRCIOC usage conditions
1Other than TRCIOC usage conditions Output port
Other than TRCIOC usage conditions
X Refer to Table 7.27 TRCIOC Pin Setting TRCI OC output
0 Refer to Table 7.27 TRCIOC Pin Setting TRCIOC input(1)
Ta bl e 7. 27 TRCIOC Pin Setti ng
Register PINSR3 TRCOER TRCMR TRCIOR1 Function
Bit TRCIOCSEL EC PWM2 PWMC IOC2 IOC1 IOC0
Setting
value
1 0 1 1 X X X PWM mode waveform output
1010
001
Timer waveform output (output compare
function)
101X
10
1 0 1 X X Timer mode (input capture function)
11
Other than above Other than TRCIOC usage conditions
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
Rev.1.00 Dec 14, 2007 Page 59 of 332
REJ09B0349-0100
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
X: 0 or 1
NOTES:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. Set the INT1SEL bit in the PMR register to 1 (P3_6).
X: 0 or 1
NOTE:
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Tab le 7. 28 Port P3_5/(TRCIO D )
Register PD3 Timer RC setting Function
Bit PD3_5 −
Setting
value
0 Other than TRCIOD usage conditions Input port(1)
1 Other than TRCIOD usage conditions Output port
X Refer to Table 7.29 TRCIOD Pin Setting TRCIOD output
0 Refer to Table 7.29 TRCIOD Pin Setting TRCIOD input(1)
Ta bl e 7. 29 TRCIOD Pin Setti ng
Register PINSR3 TRCOER TRCMR TRCIOR1 Function
Bit TRCIODSEL EC PWM2 PWMD IOD2 IOD1 IOD0
Setting
value
1 0 1 1 X X X P WM mode waveform output
1010
001
Timer waveform output (output
compare function)
101X
10
1 0 1 X X Timer mode (input capture function)
11
Other than above Other than TRCIOD usage conditions
Tab le 7. 30 Port P3_6/(INT1)
Register PD3 INTEN Function
Bit PD3_6 INT1EN
Setting
value
00
Input port(1)
1 0 Output port
01
INT1 input(1, 2)
Tab le 7. 31 Port P3_7/TRAO
Register PD3 TRAMR Function
Bit PD3_7 TOENA
Setting
value
00
Input port(1)
1 0 Output port
X 1 TRAO output
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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REJ09B0349-0100
NOTE:
1. Pulled up by setting the PU11 bit in the PUR1 register to 1.
X: 0 or 1
X: 0 or 1
Tab le 7. 32 Port P4_2/VREF
Register ADCON1 Function
Bit VCUT
Setting
value 0 Input port
1 Input port/VREF input
Tab le 7. 33 Port P4_5/INT0
Register PD4 INTEN Function
Bit PD4_5 INT0EN
Setting
value
00
Input port(1)
1 0 Output port
01
INT0 input(1)
Tab le 7. 34 Port P4_6/XIN
Register CM0 CM1 Circuit specifications Function
Bit CM05 CM13 CM11 CM10 Oscillation
buffer Feedback
resistor
Setting
value
10X0OFF−Input port
0
1
0
0
ON ON XIN clock oscillation (on-chip
feedback resistor enabled)
1ONOFF
XIN clock oscillation (on-chip
feedback resistor disabled)
1
0 OFF ON External clock input
0OFFON
XIN clock oscillation stop (on-chip
feedback resistor enabled)
1 OFF OFF XIN clock oscillation stop (on-chip
feedback resistor disabled)
11OFFOFF
XIN clock oscillation stop (stop
mode)
Tab le 7. 35 Port P4_7/XOUT
Register CM0 CM1 Circuit specifications Function
Bit CM05 CM13 CM11 CM10 Oscillation
buffer Feedback
resistor
Setting
value
10X0OFF−Input port
0
1
0
0
ON ON XIN clock oscillation (on-chip
feedback resistor enabled)
1ONOFF
XIN clock oscillation (on-chip
feedback resistor disabled)
1
0 OFF ON External clock input
0OFFON
XIN clock oscillation stop (on-chip
feedback resistor enabled)
1 OFF OFF XIN clock oscillation stop (on-chip
feedback resistor disabled)
1 1 OFF OFF XOUT pulled up
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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REJ09B0349-0100
X: 0 or 1
NOTE:
1. Pulled up by setting the PU12 bit in the PUR1 register to 1.
X: 0 or 1
X: 0 or 1
NOTE:
1. Pulled up by setting the PU13 bit in the PUR1 register to 1.
X: 0 or 1
Tab le 7. 36 Port P5_3/TRCIO C/ACOUT0
Register PD5 Timer RC setting ACCR0 Function
Bit PD5_3 −CM0OE
Setting
value
0 Other than TRCIOC usage conditions 0 Input port(1)
1 Other than TRCIOC usage conditions 0 Output port
X Refer to Table 7.37 TRCIOC Pin Setting 0 TRCIOC output
0 Refer to Table 7.37 TRCIOC Pin Setting 0TRCIOC input(1)
X Other than TRCIOC usage conditions 1 ACOUT0 output
Ta bl e 7. 37 TRCIOC Pin Setti ng
Register PINSR3 TRCOER TRCMR TRCIOR1 Function
Bit TRCIOCSEL EC PWM2 PWMC IOC2 IOC1 IOC0
Setting
value
0 0 1 1 X X X PWM mode waveform output
0010001
Timer waveform output (output
compare function)
001X
00
1 0 1 X X Timer mode (input capture function)
01
Other than above Other than TRCIOC usage conditions
Tab le 7. 38 Port P5_4/TRCIOD/ACO UT 1
Register PD5 Timer RC setting ACCR1 Function
Bit PD5_4 −CM1OE
Setting
value
0 Other than TRCIOD usage conditions 0 Input port(1)
1 Other than TRCIOD usage conditions 0 Output port
X Refer to Table 7.39 TRCIOD Pin Setting 0 TRCIOD output
0 Refer to Table 7.39 TRCIOD Pin Setting 0TRCIOD input(1)
X Other than TRCIOD usage conditions 1 ACOUT1 output
Ta bl e 7. 39 TRCIOD Pin Setti ng
Register PINSR3 TRCOER TRCMR TRCIOR1 Function
Bit TRCIODSEL ED PWM2 PWMD IOD2 IOD1 IOD0
Setting
value
0 0 1 1 X X X PWM mode waveform output
0010001
Timer waveform output (output
compare function)
001X
00
1 0 1 X X Timer mode (input capture function)
01
Other than above Other than TRCIOD usage conditions
R8C/2E Group, R8C/2F Group 7. Programmable I/O Ports
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7.5 Unassigned Pin Handling
Table 7.40 lists Unassigned Pin Handling.
NOTES:
1. If these ports are set to outpu t mode and left o pen, they remain in input mo de until they are switched
to output mode by a program. The voltage level of these pins may be undefined and the power
current may increase while the ports rem ain in input mode.
The content of the direction registers may change due to noise or program runaway caused by
noise. In order to enhance program reliability, the program should periodically repeat the setting of
the direction registers.
2. Connect these unassigned pins to the MCU using the shortest wire length (2 cm or less) possible.
3. When the power-on reset function is in use.
Figure 7.13 Unassigned Pin Handling
Table 7.40 Unassigned Pin Handling
Pin Name Connection
Ports P0, P1, P3_1, P3_3 to P3_7,
P4_3 to P4_5, P5_3, P5_4 •After setting to input mode, connect each pin to VSS via a resistor
(pull-down) or connect each pin to VCC via a resistor (pull-up).(2)
• After setting to output mode, leave these pins open.(1, 2)
Ports P4_6, P4_7 Connect to VCC via a pull-up resistor(2)
Port P4_2, VREF Connect to VCC
RESET (3) Connect to VCC via a pull-up resistor(2)
NOTE:
1. When the power-on reset functi on is in use.
MCU
Port P0, P1,
P3_1, P3_3 to P3_7,
P4_3 to P4_5,
P5_3, P5_4
(Input mode )
:
:
(Input mode)
(Output mode)
Port P4_6, P4_7
RESET(1)
Port P4_2/VREF
:
:
Open
R8C/2E Group, R8C/2F Group 8. Processor Mode
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8. Processor Mode
8.1 Processor Modes
Single-chip mode can be selected as the processor mode.
Table 8.1 lists Features of Processor Mode. Figu re 8.1 shows the PM0 Register and Figure 8.2 shows the PM1
Register.
Figure 8.1 PM0 Register
Figure 8.2 PM1 Register
Table 8.1 Features of Processor Mode
Processor Mode Accessible Areas Pins Assignable as I/O Port Pins
Single-chip mode SFR, internal RAM, internal ROM All pins are I/O ports or peripheral
function I/O pins
P rocessor M od e Register 0(1)
Symbol Address After Reset
PM0 0004h 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
b3 b2
—
b1 b0
000
—
(b2-b0)
b7 b6 b5 b4
RW
Reserved bits Set to 0.
Set the PRC1 bit in the PRCR register to 1 (write enable) before rew ri ting the PM0 register.
The MCU i s reset w hen this bit i s set to 1.
When read, the content is 0. RW
—
(b7-b4)
PM03 Software reset bit
Nothing is assigne d. If n ecessary, set to 0.
When read, the content is 0.
P rocessor M od e Register 1(1)
Symbol Address After Reset
PM1 0005h 00h
Bit Symbol Bi t Name Function RW
NOTES:
1.
2.
0
—
(b1-b0) RW
Reserved bits Set to 0.
b7 b6 b5 b4 b3 b2
—
b1 b0
00
0 : Watchdog timer i nterrupt
1 : Watchdog timer reset(2) RW
The PM12 bit is set to 1 by a program (It remains unchanged even if 0 is written to it).
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bi t is
automaticall
y
set to 1.
Reserved bit Set to 0.
Set the PRC1 bit in the PRCR register to 1 (write enable) before rew ri ting the PM1 register.
—
(b7) RW
—
(b6-b3)
PM12 WDT in terrupt/reset switch bit
Nothing is a ssigned. If nece ssary, set to 0.
When read, the content is 0.
R8C/2E Group, R8C/2F Group 9. Bus
Rev.1.00 Dec 14, 2007 Page 64 of 332
REJ09B0349-0100
9. Bus
The bus cycles differ when accessing ROM/RAM, and when accessing SFR.
Table 9.1 lists Bus Cycles by Access Space of the R8C/2E Group and Table 9.2 lists Bus Cycles by Access Space of
the R8C/2F Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units, these areas are
accessed twice in 8-bit units.
Table 9.3 lists Access Units and Bus Operations.
Table 9.3 Access Units and Bus Operations
However, only following SFRs are connected with the 16-bit bus:
Timer RC: registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD
Therefore, when accessing in word (16-bit) unit, 16-bit data is accessed at a time. The bus operation is the same as
“Area: SFR, data flash, e ven address byte access” in Table 9.3 Access Units and Bus Operations, and 16-bit data is
accessed at a time.
Table 9.1 Bus Cycles by Access Space of the R8C/2E Group
Access Area Bus Cycle
SFR 2 cycles of CPU clock
ROM/RAM 1 cycle of CPU clock
Table 9.2 Bus Cycles by Access Space of the R8C/2F Group
Access Area Bus Cycle
SFR/Data flash 2 cycles of CPU clock
Program ROM/RAM 1 cycle of CPU clock
Area SFR, data flash
Even address
Byte access
ROM (program ROM), RAM
Odd address
Byte acce s s
Even address
Word access
Odd address
Word access
CPU clock
Data
Data
Data
Data
Data
Data
Data Data Data
Even Even
Odd Odd
Even+1Even
Odd+1Odd
Address
Even+1
Odd+1
Odd
Data
Data
Even
Data
CPU clock
Data
Address
CPU clock
Data
Address
CPU clock
Data
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
Rev.1.00 Dec 14, 2007 Page 65 of 332
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10. Clock Generation Circuit
The clock generation circuit has:
• XIN clock oscillation circuit
• Low-speed on-chip oscill ator
• High-speed on-chip oscillator
Table 10.1 lists Specifications of Clock Generation Circuit. Figure 10.1 shows a Clock Generation Circuit. Figures
10.2 to 10.7 show clock associated registers.
NOTES:
1. These pins can be used as P4_6 or P4_7 when using the on-chip oscillator clock as the CPU clock while the
XIN clock oscillation circuit is not used.
2. Set the CM05 bit in the CM0 register to 1 (XIN clock stopped) and the CM13 bit in the CM1 register to 1 (XIN-
XOUT pin) when an external clock is input.
3. The clock frequency is automatically set to up to 20 MHz by a divider when using the high-speed on-chip
oscillator as the CPU clock source.
Table 10.1 Specifications of Clock Generation Circuit
Item XIN Clock Oscillation Circuit On-Chip Oscillator
High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator
Applications • CPU clock source
• Peripheral function clock
source
• CPU clock source
• Peripheral function clock
source
• CPU a nd peripheral function
clock sources when XIN clock
stops oscillating
• CPU clock source
• Peripheral function clock
source
• CPU and perip heral function
clock sources when XIN clock
stops oscillating
Clock frequency 0 to 20 MHz Approx. 40 MHz(3) Approx. 125 kHz
Connectable
oscillator • Ceramic resonator
• Crystal oscillator −−
Oscillator
connect pins XIN, XOUT(1) −(1) −(1)
Oscillation stop,
restart function Usable Usable Usable
Oscillator status
after reset Stop Stop Oscillate
Others • Externally generated clock
can be input(2)
• On-chip feedback resistor
RfXIN (connected/ not
connected, selectable)
−−
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
Rev.1.00 Dec 14, 2007 Page 66 of 332
REJ09B0349-0100
Figure 10.1 Clock Generation Circuit
Oscillation
stop
detection
Divider
SQ
R
1/2 1/2 1/2 1/2 1/2
Pulse generati on
circuit for clock
edge detection and
charge, disc ha r ge
control circuit
Charge,
discharge
circuit Oscillation stop detection
interrupt generation
circuit detection
SQ
R
FRA00 High-speed
on-chip
oscillator
FRA01 = 1
FRA01 = 0
CM14
CPU clock
a
b
c
d
e
OCD2 = 0
OCD2 = 1
XIN
clock
CM02
WAIT instruction
RESET
CM10 = 1 (stop mode )
a
d
c
h
b
CM06 = 0
CM17 to CM16 = 11b
CM06 = 1
CM06 = 0
CM17 to CM16 = 10b
CM06 = 0
CM17 to CM16 = 01b
CM06 = 0
CM17 to CM16 = 00b
Detail of divider
Oscillation Stop Detection Circuit
XIN clock
Forcible discharge when OCD0 = 0
OCD1 Oscillation stop detection ,
Watchdog time r,
Voltage monito r 1 int err upt ,
Voltage monito r 2 int err upt
eg
UART0
A/D
converter
Timer RCTimer RBTimer RA
FRA2 register
fOCO
fOCO-S
g
f1
f2
f4
f8
f32
INT0
Watchdog
timer
System clock
FRA1 register
Frequency adjusta ble
Divider
fOCO40M
On-chip oscillator
clock Timer RE
fOCO-F
XOUT
XIN
Power-on
reset circuit
Voltage
detection
circuit
Power-on rese t
Softwar e rese t
Interrupt request
CM13
CM05
Low-speed
on-chip
oscillator
CM02, CM05, CM06: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM 1 register
OCD0, OCD1, OCD2: Bits in OC D register
FRA00, FRA01: Bits in FRA0 register
Watchdog time r
interrupt
OCD2 bit switch signal
CM14 bit switch signal
Voltage monitor 2
interrupt
Voltage monitor 1
interrupt
Stop signal
D/A
converter Comparator
Divider
(1/128) fOCO128
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
Rev.1.00 Dec 14, 2007 Page 67 of 332
REJ09B0349-0100
Figure 10.2 CM0 Register
S yst e m Clock Cont rol Regi ster 0(1)
Symbol Address After Reset
CM0 0006h 01101000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
b7 b6 b5 b4 b3 b2 b1 b0
00100
—
(b1-b0) Reserved bits Set to 0. RW
CM02
WAIT peripheral function clock
stop bit 0 : Peripheral function clock does not stop
in wait mode
1 : Peripheral function clock stops in wait
mode
RW
—
(b3) Reserved bit Set to 1. RW
—
(b4) Reserved bit Set to 0. RW
CM05 XIN clock (XIN-XOUT)
stop bit(2 , 3) 0 : XIN clock oscillates
1 : XIN cl ock stops(4) RW
CM06 System clock division select bit
0(5) 0 : CM16, CM17 enabl ed
1 : Divide-by-8 mode RW
—
(b7) Reserved bit Set to 0. RW
Set the PRC0 bit in the PRCR register to 1 (w rite enable) before rewriting the CM0 register.
During external clock input, only the clock oscillation buffer is turned off and clock input is acknowledged.
When entering stop mode, the CM06 bit is set to 1 (divide-by-8 mode).
P4_6 and P4_7 can be used as input ports when the CM05 bit is set to 1 (XIN clock stops) and the CM13 bi t in the
CM1 register is set to 0 (P4_6, P4_7).
The CM05 bit stops the XIN clock w hen the high-speed on-chip oscillator mode or l o w-speed on-chi p oscillator mode
i s selected. Do not use thi s bi t to detect whether the XIN clock is stopped. T o stop the XIN clock, set the bits in the
follow ing order:
(a) Set bits OCD1 to OCD0 in the OCD regi ster to 00b.
(b) Set the OCD2 bit to 1 (selects on-chip oscillator clock).
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
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REJ09B0349-0100
Figure 10.3 CM1 Register
S yst e m Clock Cont rol Regi ster 1(1)
Symbol Address After Reset
CM1 0007h 00100000b
B it Symbol Bit Name Functio n RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
When the CM10 bi t is set to 1 (stop mode) and the CM13 bit i s set to 1 (XIN-XOUT pin), the XOUT (P4_7) pin goes “H”.
When the CM13 bi t is set to 0 (i n put ports, P4_6, P4_7), P4_7 (XO UT) enters input mode.
In count source protect mode (Refer to 13.2 Count Source Protect Mode Ena bled), the val ue remains
unchanged even if bits CM10 and CM14 are set.
When the CM06 bi t is set to 0 (bits CM16, CM17 enabl ed), bits CM16 to CM17 are enabled.
If the CM10 bit is set to 1 (stop mode), the on-chip feedback resi stor i s di sabled.
When the OCD2 bit is set to 0 (XIN clock selected), the CM14 bit is set to 1 (low-speed on-chip oscillator stopped).
When the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low -speed on-chip
oscillator on). It remains unchanged even i f 1 i s w ritten to it.
When usi ng the vol tage moni tor 1 interrupt or voltage monitor 2 interrupt (when using the digital filter), set the CM14
bi t to 0 (low-speed on-chip oscillator on).
Once the CM13 bit is set to 1 by a program, it cannot be set to 0.
When entering stop mode, the CM15 bit is set to 1 (drive capacity high).
CM17 RW
b7 b6
0 0 : No division mode
0 1 : Divide-by-2 mode
1 0 : Divide-by-4 mode
1 1 : Divide-by-16 mode
System clock division select bits 1(9)
CM16 RW
CM15 XIN-XOUT drive capaci ty select bi t(8) 0 : Low
1 : High RW
CM14 Low-speed on-chip oscillation stop
bit(4, 6, 7) 0 : Low-speed on-chip oscillator on
1 : Low-speed on-chip oscillator off RW
CM13 Port XIN-XOUT sw itch bit(3, 5) 0 : Input ports P4_6, P4_7
1 : XIN-XOUT pin RW
—
(b2) Reserved bit Set to 0. RW
All clock stop control bi t(2, 3, 4) 0 : Clock operates
1 : Stops all clocks (stop mode) RW
CM11 XIN-XOUT on-chip feedback resistor
select bit 0 : On-chip feedback resistor enabled
1 : On-chip feedback resistor disabled RW
0
CM10
Set the PRC0 bit in the PRCR register to 1 (w rite enabl e) before rewriting the CM1 register.
b7 b6 b5 b4 b3 b2 b1 b0
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
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REJ09B0349-0100
Figure 10.4 OCD Regi st er
Oscil l ati on S top Det ectio n Register(1)
Symbol Address After Reset
OCD 000Ch 00000100b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5.
6.
7.
b7 b6 b5 b4 b3 b2 b1 b0
0000
OCD1 RW
OCD0 RW
Oscillation stop detection enable
bit(7)
Oscillation stop detection
i nterrupt enable bi t
0 : Oscillation stop detection function
disabled(2)
1 : Oscillation stop detection function
enabled
0 : Disabled(2)
1 : Enabled
OCD2 System clock select bit(4) 0 : Select s XIN clock(7)
1 : Selects on-chip oscillator clock(3) RW
OCD3 Clock monitor bi t(5, 6) 0 : XIN clock oscillates
1 : XIN clock stops RO
—
(b7-b4) Reserved bits Set to 0. RW
The OCD3 bit remains 0 (XI N clock oscillates) if bits OCD1 to OCD 0 are set to 00b.
The CM14 bit is set to 0 (low-speed on-chip oscillator on) if the OCD2 bit is set to 1 (on-chip oscillator clock
selected).
Refer to Figure 10.1 4 Procedure for Switching Cloc k Source from Low-speed On-Chip Osci llator to XIN
Clock for the switching procedure when the XIN clock re-oscillates after detecting an oscillation stop.
Set the PRC0 bit in the PRCR register to 1 (write enable) before rew ri ting to the OCD register.
The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if a XIN clock oscillation stop is detected
whil e bits O CD1 to O CD0 are set to 11b. If the OCD3 bit is set to 1 (XIN cl ock stopped), the OCD2 bit remains
unchanged even when set to 0 (XIN cl ock selected).
The OCD3 bit i s enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled).
Set bits OCD1 to OCD0 to 00b before entering stop mode, high-speed on-chip oscillator mode, or low -speed on-chip
oscillator mode (XIN clock stops).
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
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REJ09B0349-0100
Figure 10.5 Registers FRA0 and FRA1, FRA2
Hig h-S peed On -Chip Osci l l at or Control Regi st er 0(1)
Symbol Address After Reset
FRA0 0023h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
Change the FRA01 bit under the follow ing conditions.
• FRA00 = 1 (high-speed on-chip oscillation)
• The CM14 bit in the CM1 register = 0 (low -speed on-chip oscillator on)
When setting the FRA01 bit to 0 (low-speed on-chip oscillator selected), do not set the FRA00 bit to 0 (high-speed
on-chip oscillator off) at the same time. Set the FRA00 bit to 0 after setting the FRA01 bit to 0.
—
(b7-b2) Reserved bits Set to 0. RW
Set the PRC0 bit in the PRCR register to 1 (write enable) before rew ri ting the F RA0 register.
FRA00 RW
FRA01 RW
Hi gh-speed on-chip oscillator
enabl e bit 0 : High-speed on-chip oscillator off
1 : High-speed on-chip oscillator on
Hi gh-speed on-chip oscillator
select bit (2) 0 : Selects low -speed on-chip oscillator(3)
1 : Selects high-speed on-chip oscillator
000000b3 b2 b1 b0b7 b6 b5 b4
Hig h-S peed On -Chip Osci l lator Cont rol Regi st er 1(1)
Symbol Address After Reset
FRA1 0024h When Shipping RW
NOTES:
1.
2. Set the PRC0 bit in the PRCR register to 1 (write enable) before rew ri ting the F RA1 register.
RW
Function
The frequency of the high-speed on-chip oscillator is adjusted w ith bits 0 to 7.
High-speed on-chip oscillator frequency = 40 MHz (FRA1 register = value when shipping)
Setting the FRA1 register to a lower value results i n a higher frequency.
Setting the FRA1 register to a higher value results in a low er frequency.(2)
When changi n g the val ues of the FRA1 register, adj ust the FRA1 register so that the frequency of the high-speed
on-chip oscillator clock w ill be 40 MHz or less.
b7 b6 b5 b4 b3 b2 b1 b0
Hig h-S peed On -Chip Osci l l at or Control Regi st er 2(1)
Symbol Address After Reset
FRA2 0025h 00h
B it Symbol Bit Name Function RW
NOTE:
1. Set the PRC0 bit in the PRCR register to 1 (w ri te enable) before rewriting the FRA2 register.
b7 b6 b5 b4 b3 b2 b1 b0
00000
Selects the dividing ratio for the high-
speed on-chip oscillator clock.
b2 b1 b0
0 0 0: Divide-by-2 mode
0 0 1: Divide-by-3 mode
0 1 0: Divide-by-4 mode
0 1 1: Divide-by-5 mode
1 0 0: Divide-by-6 mode
1 0 1: Divide-by-7 mode
1 1 0: Divide-by-8 mode
1 1 1: Divide-by-9 mode
FRA20
FRA22 RW
—
(b7-b3) RW
Reserved bits Set to 0.
High-speed on-chip oscillator
frequency sw i tching bi ts RW
FRA21 RW
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
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REJ09B0349-0100
Figure 10.6 FRA7 Register
Figure 10.7 VCA2 Register
Hig h-S peed O n-Chip O sc i l l at or Control Register 7
Symbol Address After Reset
FRA7 002Ch When Shipping RW
b7 b6 b5 b4 b3 b2 b1 b0
RO
Function
36.864 MHz frequency correction data is stored.
The oscillation frequency of the high-speed on-chip oscillator can be adjusted to 36.864 MHz
by transferring this value to the FRA1 register.
V ol t age Detect i on Regis ter 2(1)
Symbol Address After Reset(4)
VCA2 0032h
B it Symbol Bit Name Functi o n RW
NOTES:
1.
2.
3.
4.
5.
Power-on reset or hardware reset : 00100000b
—
(b5) Reserved bi t Set to 1. RW
—
(b4-b1) Reserved bi ts Set to 0. RW
b7 b6 b5 b4 b3 b2 b1 b0
10000
Voltage detection 2 enable
bit(3) 0 : Vol tage detection 2 circuit disabled
1 : Voltage detection 2 circuit enabled RW
VCA26 Voltage detection 1 enable
bit(2) 0 : Vol tage detection 1 circuit disabled
1 : Voltage detection 1 circuit enabled RW
Use the VCA20 bi t only when entering to wait mode. T o set the VCA20 bit, follow the procedure show n i n Figure
10.8 Procedure for Enabling Reduced Internal Power Consumptio n Using VCA20 bit.
VCA20 Internal power low
consumption enable bit(5) 0 : Disables low consumption
1 : Enables low consumption RW
Set the PRC3 bit in the PRCR register to 1 (w rite enable) before w riting to the VCA2 register.
To use the voltage monitor 1 interrupt/reset or the VW1C3 bit in the VW1C register, set the VCA26 bit to 1.
After the VCA26 bi t is set to 1 from 0, the voltage detection ci rcui t wai ts for td(E-A) to elapse before starting
operation.
To use the voltage monitor 2 interrupt/reset or the VCA13 bit in the VCA1 register, set the VCA27 bit to 1.
After the VCA27 bi t is set to 1 from 0, the voltage detection ci rcui t wai ts for td(E-A) to elapse before starting
operation.
Software reset, w atchdog timer reset, voltage monitor 1 reset, and voltage monitor 2 reset do not affect this
register.
VCA27
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
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REJ09B0349-0100
Figure 10.8 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does no t apply if it is not nec es s ary t o s t art t he hi gh-s peed clock or high-speed on-c hi p os c illator during the interrupt routine.
2. Do not set the VCA2 0 bit to 0 with the instruction immediately aft er s etting the VCA20 bit to 1. A ls o , do not do the opposite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.6.2 Wait Mode.
Handling procedure of in te rn al power
low consumptio n enabled by VCA20 bit
Enter low-speed on-chi p osc illator mode
Stop XIN clo c k and high-spe ed on-c hip
oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Enter wait mode(4)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start XIN clock or high-speed on-chip
oscillator clock
(Wait until XIN clock oscillation stabilizes)
Enter high-speed cl ock mode or
high-speed on-ch ip os c i llator mode
In inter rupt routine
VCA20 ← 0 (internal power low consumpti on
disabled)(2)
Start XIN clock or high-speed on-ch ip
oscillator clock
Enter high-speed c lo c k mode or
high-speed on-chip oscillator mode
Enter low-speed on-chi p oscillator mode
Exit wait mode by interrupt
Stop XIN cloc k and high-speed on-c h ip
oscillator clock
VCA20 ← 1 (internal power low consumpti on
enabled)(2, 3)
Interrupt handling c ompleted
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
Step (5)
Step (6)
Step (7)
Step (8)
(Wait until XIN clock oscilla tion stabilizes)
Step (1)
Step (2)
Step (3)
If it is necessary to start
the high-speed clock or
the high-speed on-c hip
oscillator in the interrupt
routine, ex ec ute steps (5)
to (7) in the interrupt
routine.
If the high-s peed clock or
high-speed on-ch ip
oscillat or is s tarted in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt rout ine .
(Note 1)
Interrupt handling
VCA20: Bit in VCA2 register
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
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The clocks generated by the clock generation circuits are described below.
10.1 XIN Clock
This clock is supplied by the XIN clock oscillat ion circuit. This clock is used as the clock source for the CPU and
peripheral function clocks. The XIN clock oscillation circuit is configured by connecting a resonator between the
XIN and XOUT pins. The XIN clock oscillation circuit includes an on-chip feedback resistor, which is
disconnected from the oscillation circuit in stop mode in order to reduce the amount of power consumed by the
chip. The XIN clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN
pin.
Figure 10.9 shows Examples of XIN Clock Connect ion Circuit.
In reset and after reset, the XIN clock stops.
The XIN clock starts oscillating when the CM05 bi t in the CM0 register is set to 0 (XIN clock oscillates) after
setting the CM13 bit in the CM1 register to 1 (XIN- XOU T pin). To use the XIN clock for t he CPU clock source ,
set the OCD2 bit in the OCD register to 0 (select XIN clock) after the XIN clock is oscillating stably.
The power consu mption can be reduced by setting the CM0 5 bit in the CM0 reg ister to 1 (XIN clock stops) i f the
OCD2 bit is set to 1 (select on-chip oscillator clock ).
When an external clock is input to the XIN pin are input, the XIN clock does not stop if the CM05 bit is set to 1. If
necessary, use an external circuit to stop the clock.
This MCU has an on-chi p feedback resist or and on-chip resistor disab le/enable switching is possible by the CM11
bit in the CM1 register.
In stop mode, all clocks including the XIN clock stop. Refer to 10.4 Power Control for details.
Figure 10.9 Examples of XIN Clock Connection Circuit
XIN XOUT
MCU
(on-chip feedback resistor)
Rd(1)
COUTCIN
XIN XOUT
MCU
(on-chip feedback resistor)
Externally derived clock
VCC
VSS
NOTE:
1. Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the manufacturer of the oscillator.
Use high drive when oscillation starts and, if it is necessary to switch the oscillation drive capacity, do so after
oscillation stabilizes.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added to the chip ext ernally, insert a feedback resistor between XIN
and XOUT following the instruct ions.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1 register
to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the feedback resistor
to the chip externally.
Open
Ceramic resonator external circuit External clock in put circui t
Rf(1)
R8C/2E Group, R8C/2F Group 10. Clock Generation Circuit
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REJ09B0349-0100
10.2 On-Chip Oscillator Clocks
These clocks are supplied by the on-chip oscillators (high-speed on-chip oscillator and a low-speed on-chip
oscillator). The on-chip oscillator clock is selected by the FRA01 bit in the FRA0 register.
10.2.1 Low-Speed On-Chip Oscillator Clock
The clock generated by the low-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, and fOCO-S.
After reset, the on-chip oscillator clock generated by the low-speed on-chip oscillator divided by 8 is selected as
the CPU clock.
If the XIN clock stops oscillating when bits OCD1 to OCD0 in the OCD register are set to 11b, the low-speed
on-chip oscillator automatically starts operating, supplying the necessary clock for the MCU.
The frequency of the low-speed on-chip oscillator var ies depending on the supply voltage and the operating
ambient temperature. Application products must be designed with sufficient margin to allow for frequency
changes.
10.2.2 High-Speed On-Chip Oscillator Clock
The clock generated by the high-speed on-chip oscillator is used as the clock source for the CPU clock,
peripheral function clock, fOCO, fO CO-F, and fOCO40M.
After reset, the on-chip oscillator clock ge nerated by the high-speed on-chip oscillator stop s. Oscillation is
started by setting the FRA00 bit in the FRA0 register to 1 (high-speed on-chip oscillator on). The frequency can
be adjusted by registers FRA1 and FRA2.
The frequency correc tion data of 36.8 64 MHz is stored in the FRA7 register. To set the frequency of the high -
speed on-chip oscillator to 36.864 MHz, transfer the correction value in the FRA7 register to the FRA1 register
before use.
Since there are differences in the amount of frequency adjustment among t he bits in the FRA1 register, make
adjustments by changing t he settings of individual bits. Adjust the FRA1 register so that the frequency of the
high-speed on-chip oscillator clock will be 40 MHz or less.
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10.3 CPU Clock and Peripheral Function Clock
There are a CPU clock to operate the CPU and a peripheral function clock to operate the peripheral functions. Refer
to Figure 10.1 Clock Generation Circuit.
10.3.1 System Clock
The system clock is the clock source for the CPU and peripheral function clocks. Either the XIN clock or the
on-chip oscillator clock can be selected.
10.3.2 CPU Clock
The CPU clock is an operating clock for the CPU and watchdog timer.
The system clock can b e divid ed by 1 (no division ), 2, 4, 8, or 16 to produce the CPU clock. Use the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register to select the value of the division.
After reset, the low-speed on-chip oscillator cl ock div ided by 8 provides the CPU clock.
When entering stop mode from high-speed clock mode, the CM06 bit is set to 1 (divide-by-8 mode).
10.3.3 Peripheral Function Clock (f1, f2, f4, f8, and f32)
The peripheral function clock is the operating clock for the peripheral functions.
The clock fi (i = 1, 2, 4, 8, and 32) is generated by the system clock divided by i. The clock fi is used for tim ers
RA, RB, RC, and RE, the serial interface and the A/D converter.
When the WAIT instruction is executed after setting the CM02 bit i n the CM0 register to 1 (peripheral function
clock stops in wait mode), the clock fi stop.
10.3.4 fOCO
fOCO is an operating clock for the peripheral functions.
fOCO runs at the same frequency as the on-chip oscillator clock and can be used as the source for timer RA.
When the WAIT instruction is executed, the clock s fOCO does not stop.
10.3.5 fOCO40M
fOCO40M is used as the count source for timer RC. fOCO40M is generated by the high-speed on-chip
oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO40M does not stop.
fOCO40M can be used with supply voltage VCC = 3.0 to 5.5 V.
10.3.6 fOCO-F
fOCO-F is used as the count source for the A/D converter. fOCO-F is generated by the high-speed on-chip
oscillator and supplied by setting the FRA00 bit to 1.
When the WAIT instruction is executed, the clock fOCO-F does no t stop.
10.3.7 fOCO-S
fOCO-S is an operating clock for the watchdog timer and voltage detection circuit. fOCO-S is supplied by
setting the CM14 bit to 0 (low-speed on-chip oscillator on) and uses the clock generated by the low-speed on-
chip oscillator. When the WAIT instruction is executed or in count source protect mode of the wat chdog timer,
fOCO-S does not stop.
10.3.8 fOCO128
fOCO128 is generated by fOCO divided by 128.
The clock fOCO128 is used for capture signal of the timer RC’s TRCGRA register.
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10.4 Power Control
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
10.4.1 Standard Operating Mode
Standard operating mode is further separated into four mo des.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XIN clock, allow sufficient wait time in a program until oscillation is
stabilized before exiting.
−: can be 0 or 1, no change in outcome
Table 10.2 Settings and Modes of Clock Associated Bits
Modes OCD Register CM1 Register CM0 Register FRA0 Register
OCD2 CM17, CM16 CM14 CM13 CM06 CM05 FRA01 FRA00
High-speed
clock mode No division 0 00b −100−−
Divide-by-2 0 01b −100−−
Divide-by-4 0 10b −100−−
Divide-by-8 0 −−110−−
Divide-by-16 0 11b −100−−
High-speed
on-chip
oscillator
mode
No division 1 00b −−0−11
Divide-by-2 1 01b −−0−11
Divide-by-4 1 10b −−0−11
Divide-by-8 1 −−−1−11
Divide-by-16 1 11b −−0−11
Low-speed
on-chip
oscillator
mode
No division 1 00b 0 −0−0−
Divide-by-2 1 01b 0 −0−0−
Divide-by-4 1 10b 0 −0−0−
Divide-by-8 1 −0−1−0−
Divide-by-16 1 11b 0 −0−0−
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10.4.1.1 High-Speed Clock Mode
The XIN clock divided by 1 (no division), 2, 4, 8, or 16 provides the CPU clock. Set the CM06 bit to 1 (divide-
by-8 mode) when transiting to high-speed on-chip oscillator mod e, low-speed on-chip oscillator mode. If the
CM14 bit is set to 0 (low-speed on-chip oscillator on) or the FRA00 bit in the FRA0 register is set to 1 (high-
speed on-chip oscillator on), fOCO can be used as timer RA. When the FRA00 bit is set to 1, fOCO40M can be
used as timer RC.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit.
10.4.1.2 High-Speed On-Chip Oscillator Mode
The high-speed on-chip oscillator is used as the on-chip osci llator clock when the FRA00 bit in the FRA0
register is set to 1 (high-speed on-chip oscillator on) and the FRA01 bit in the FRA0 register is set to 1. The on-
chip oscillator divided by 1 (no division ), 2, 4, 8, or 16 provides the CPU clo ck. Set the CM06 bit to 1 (divide-
by-8 mode) when transiting to high-speed clock mode. If the FRA00 bit is set to 1, fOCO40M can be used as
timer RC.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit.
10.4.1.3 Low-Speed On-Chip Oscillator Mode
If the CM14 bit in the CM1 register is set t o 0 (low-speed on-chip osci llator on) or the FRA 01bit in the FR A0
register is set to 0, the low-speed on-chip oscillator provides the on-chip oscillato r clock.
The on-chip oscillator clock divided by 1 (no division), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. Set the CM06 bit to 1 (divide-by-8
mode) when transiting to high-speed clock mode. When the FRA00 bit is set to 1, fOCO40M can be used as
timer RC.
When the CM14 bit is set to 0 (low-speed on-chip oscillator on), fOCO-S can be used as the watchdog timer
and voltage detection circuit.
In this mode, stopping the XIN clock and high-speed on-chip oscillator, and setting the FMR47 bit in the FMR4
register to 1 (flash memory low consum pti on current read mode enabled) enables low consumption operation.
To enter wait mode from low-speed on-chip oscillator mode, setting the VCA20 bit in the VCA2 register to 1
(internal power low consumptio n enabled) enables lower consumption current in wait mod e .
When enabling reduced internal power consumpti on using the VCA 20 bit, follow Figure 10.11 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
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10.4.2 Wait Mode
Since the CPU clock stops in wait mode, the CPU, which operates using the CPU clock, and the watchdog
timer, when count so urce protection m ode is disabled, stop. The XIN clock and on-chip oscillator clock do n ot
stop and the peripheral function s using these clocks continue operating.
10.4.2.1 Peripheral Function Clock Stop Function
If the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the f1 , f2, f4, f 8, and f32 clocks st op
in wait mode. This reduces power consumption.
10.4.2.2 Entering Wait Mode
The MCU enters wait mode when the WAIT instruction is executed.
When the OCD2 bit in the OCD register is set to 1 (on-chip oscillator selected as system clock), set the OCD1
bit in the OCD register to 0 (oscillation stop detection interrupt disabled) before executing the WAIT
instruction.
If the MCU enters wa it mode while the OCD1 bit is set to 1 (osci llation stop detection interru pt enabled),
current consumption is not reduced because the CPU clock does not stop.
10.4.2.3 Pin Status in Wait Mode
The I/O port is the status before wait mode was entered is maintained.
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10.4.2.4 Exiting Wait Mode
The MCU exits wait mode by a reset or a peripheral function inte rrupt .
The peripheral function interrupts are affected by the CM02 bit. When the CM02 bit is set to 0 (peripheral
function clock does not stop in wait mode), all peripheral function interrupts can be used to exit wait mode.
When the CM02 bit is set to 1 (peripheral function clock stops in wait mode), the peripheral functions using the
peripheral function clock stop operating and the peripheral functions operated by external signals or on-chip
oscillator clock can be used to exit wait mode.
Ta ble 10.3 li sts Interrupts to Exit Wait Mode and Usage Conditi ons.
Table 10.3 Interrupts to Exit Wait Mode and Usage Conditions
Interrupt CM02 = 0 CM02 = 1
Serial interface interrupt Usable when operating with
internal or external clock Usable when operating with external
clock
Key input interrupt Usable Usable
A/D conversion interrupt Usable in one-shot mode (Do not use)
Comparator 0 interrupt Usable Can be used if there is no filter
Comparator 1 interrupt Usable Can be used if there is no filter
Timer RA interrupt Usable in all modes Can be used if there is no filter in
event counter mode.
Usable by selectin g fOCO as count
source.
Timer RB interrupt Usable in all modes (Do not use)
Timer RC interrupt Usable in a ll modes (Do not use)
Timer RE interrupt Usable in all modes (Do not use)
INT interrupt Usable Usable (INT0, INT1, INT3 can be used
if there is no filter.)
Voltage monitor 1 interrupt Usable Usable
Voltage monitor 2 interrupt Usable Usable
Oscillation stop detection
interrupt Usable (Do not use)
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Figure 10.10 shows Time from Wait Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit wait mode, set up the following before executing the WAIT
instruction.
(1) Set the interru pt priority level in bits ILV L2 to ILVL0 in the in terrupt cont rol regi st ers of the peripheral
function interrupts to be used for exiting wait mode. Set bits ILVL2 to ILVL0 of the peripheral function
interrupts that are not to be used for exiting wait mod e to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operate the peripheral function to be used for exiting wait mode.
When exiting by a peripheral function interrupt, the time (number of cycles) between interrupt request
generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 register,
as described in Figure 10.10.
The CPU clock, when exiting wait mode by a peripheral function interrupt, is the same clock as the CPU clock
when the WAIT instruction is executed.
Figure 10.10 Time from Wait Mode to Interrupt Routine Execution
Period of CPU clock
× 20 cycles
Same as above
Following total time is
the time from wait
mode until an interrupt
routine is executed.
Wait mode Flash memory
activation sequence
T1
CPU clock restart sequence
T2
Interrupt sequence
T3
Interrupt request generated
Time for Interrupt
Sequence (T3) Remarks
Period of XIN clock
× 12 cycles + 30 µs (max.)
Period of XIN clock
× 12 cycles
Time until Flash Memor y
is Activated (T1)
Period of CPU c lock
× 6 cycles
Same as above
Time until CPU Clock
is Supplied (T2)
0
(flash memory operates)
1
(flash memory stops)
FMSTP Bit
FMR0 Register
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10.4.2.5 Reducing Internal Power Consumption
Internal power consumption can b e reduced by usin g low-speed on-chip oscillator mode. Figure 10.11 shows
the Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit.
When enabling reduced internal power consumpti on using the VCA 20 bit, follow Figure 10.11 Procedure for
Enabling Reduced Internal Power Consumption Using VCA20 bit.
Figure 10.11 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit
NOTES:
1. Execute this routine to handle all interrupts generated in wait mode.
However, this does no t apply if it is not nec essary to start the high-s pe ed c lock or high-speed on-chip osc illator during the interrupt routine.
2. Do not set the VCA2 0 bit to 0 with the instruction immediately aft er s etting the VCA20 bit to 1. Also, do not do the oppos ite.
3. When the VCA20 bit is set to 1, do not set the CM10 bit to 1 (stop mode).
4. When entering wait mode, follow 10.6.2 Wait Mode.
Handling procedure of in te rn al power
low consumptio n enabled by VCA20 bit
Enter low-speed on-chip os c illator mode
Stop XIN clo c k and high-spe ed on-chip
oscillator clock
VCA20 ← 1 (internal power low consumption
enabled)(2, 3)
Enter wait mode(4)
VCA20 ← 0 (internal power low consumption
disabled)(2)
Start XIN clock or high-speed on-chip
oscillator clock
(Wait until XIN clock oscillation stabilizes)
Enter high-speed clock mode or
high-speed on-ch ip os c illator mode
In inter rupt routine
VCA20 ← 0 (internal power low consumpti on
disabled)(2)
Start XIN clock or high-speed on-ch ip
oscillator clock
Enter high-speed c lo c k mode or
high-speed on-chip oscillator mode
Enter low-speed on-chi p osc illator mode
Exit wait mode by interrupt
Stop XIN cloc k and high-speed on-c h ip
oscillator clock
VCA20 ← 1 (internal power low consumpti on
enabled)(2 , 3 )
Interrupt handling c ompleted
Step (1)
Step (2)
Step (3)
Step (4)
Step (5)
Step (6)
Step (7)
Step (8)
Step (5)
Step (6)
Step (7)
Step (8)
(Wait until XIN clock oscillation stabilizes)
Step (1)
Step (2)
Step (3)
If it is necessary to start
the high-speed clock or
the high-speed on-c hip
oscillator in the interrupt
routine, ex ec ute steps (5)
to (7) in the interrupt
routine.
If the high-s peed clock or
high-speed on-ch ip
oscillat or is s tarted in the
interrupt routine, execute
steps (1) to (3) at the last of
the interrupt rout ine .
(Note 1)
Interrupt handling
VCA20: Bit in VCA2 register
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10.4.3 Stop Mode
Since the oscillator circuits stop in stop mode, the CPU clock and peripheral function clock stop and the CPU
and peripheral functions that use these clocks stop operating. The least power required to operate the MCU is in
stop mode. If the voltage applied to the VCC pin is VRAM or more, the contents of internal RAM is
maintained.
The peripheral functions clocked by external signals conti nue operating.
Ta ble 10.4 li sts Interrupts to Exit Stop Mode and Usage Conditions.
10.4.3.1 Entering Stop Mode
The MCU enters stop mode when the CM10 bit in the CM1 register is set to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM1 register is
set to 1 (XIN clock oscillator circuit drive capacity high).
When using stop mode, set bits OCD1 to OCD0 to 00b before entering stop mode.
10.4.3.2 Pin Status in Stop Mode
The status before wait mode was entered is maintained.
However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held
“H”. When the CM13 bit is set to 0 (input ports P4_6 and P4_7), the P4_7(XOUT pin) is held in input status.
Table 10.4 Interrupts to Exit Stop Mode and Usage Conditions
Interrupt Usage Conditions
Key input interrupt −
INT0, INT1, INT3 interrupt Can be used if there is no filter
Timer RA interrupt When there is no filter and external pulse is counted in event counter
mode
Serial interface interrupt When external clock is selected
Voltage monitor 1 interrupt Usable in digital filter disabled mod e (VW1C1 bit in VW1C register is set
to 1)
Voltage monitor 2 interrupt Usable in digital filter disabled mod e (VW2C1 bit in VW2C register is set
to 1)
Comparator 0 interrupt,
Comparator 1 interrupt Can be used if there is no filter
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10.4.3.3 Exiting Stop Mode
The MCU exits stop mode by a reset or peripheral function interrupt.
Figure 10.12 shows the Time from Stop Mode to Interrupt Ro utine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setti ng the CM10 bit
to 1.
(1) Set the interrupt priority level in bits ILVL2 to ILVL0 of the peripheral function interrupts to be used for
exiting stop mode . Set bit s ILVL2 to ILVL0 of th e peripheral functio n interrupts th at are not to b e used
for exiting stop mode to 000b (interrupt disabled).
(2) Set the I flag to 1.
(3) Operates the peripheral function to be used for exiting stop mode.
When exiting by a peripheral fun ction in terrup t, the in terrupt sequence is executed when an interrupt request is
generated and the CPU clock supply is started.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the prev ious system clock divided by 8.
Figure 10.12 Time from Stop Mode to Interrupt Routine Execution
Time until Flash Memory
is Activated (T2)
T2
Time until CPU Clock
is Supplied (T3) Time for Interrupt
Sequence (T4) Remarks
Flash memory
activation sequence CPU clock restart
sequence Interrupt sequence
Oscillation time of
CPU clock source
used immediately
before stop mode
Stop
mode
T3 T4
Internal
power
stability time
T1T0
Interrupt
request
generated
150 µs
(max.)
FMSTP Bit
FMR0 Register
0
(flash mem o ry
operates)
1
(flash memory stops)
Peri od of CPU c lock
× 6 cycles Period of CPU clock
× 20 cycles Following to ta l
time of T0 to T4
is the time from
stop mode until
an interrupt
handling is
executed.
Period of XIN clock
× 12 cycles + 30 µs (max.)
Period of XIN clock
× 12 cycles Same as above Same as above
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Figure 10.13 shows the State Transitions in Power Control Mode.
Figure 10.13 State Transitions in Power Control Mode
CM10 = 1
CPU operation stops
Stop mode
State Transitions in Power Control Mode
Reset
Wait mode
Low-speed on-chip oscillator mode
CM14 = 0
OCD2 = 1
FRA01 = 0
High-speed on-chip oscillator mode
OCD2 = 1
FRA00 = 1
FRA01 = 1
High-speed clock mode
CM05 = 0
CM13 = 1
OCD2 = 0
Standard oper ating mode
CM14 = 0
OCD2 = 1
FRA01 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
CM05 = 0
CM13 = 1
OCD2 = 0
OCD2 = 1
FRA00 = 1
FRA01 = 1
FRA00 = 1
FRA01 = 1
CM14 = 0
FRA01 = 0
All oscillators stop
InterruptWAIT instructionInterrupt
CM05: Bit in CM0 register
CM13, CM14: Bits in CM1 register
OCD2: Bit in OCD register
FRA00, FRA01: Bits in FRA0 regis t er
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10.5 Oscillation Stop Detection Function
The oscillation stop detection function detects the stop of the XIN clock oscillating circuit. The oscillation stop
detection function can be enabled and disabled by the OCD0 bit in the OCD register.
Table 10.5 lists the Specifications of Oscillation Stop Detection Function.
When the XIN clock is the CPU clock source and bits OCD1 to OCD0 are set to 11b, the system is placed in the
following state if the XIN clock stops.
•OCD2 bit in OCD register = 1 (on-chip oscillator clock selected)
•OCD3 bit in OCD register = 1 (XIN clock stops)
•CM14 bit in CM1 register = 0 (low-speed on-chip oscillator oscillates)
•Oscillation stop detection interrupt request is generated.
10.5.1 How to Use Oscillation Stop Detection Function
•The oscillation stop detection interrupt shares a vector with the voltage monitor 1 interrupt, the voltage
monitor 2 interrupt, and the watchdog timer interrupt. When using the oscillation stop detection interrupt
and watchdog timer interrupt, the interrupt source needs to be determined.
Ta ble 10.6 lists Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer, Voltage
Monitor 1, and Voltage Monitor 2 Interrupts. Figure 10.15 shows the Example of Determining Interrupt
Source for Oscillation Stop Detection, Watchdog Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt.
•When the XIN clock restarts after oscillation stop, switch the XIN clock to the clock source of the CPU
clock and peripheral functions by a program.
Figure 10.14 shows the Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to
XIN Clock.
•To enter wait mode while using the oscillation stop detection function, set the CM02 bit to 0 (peripheral
function clock does no t stop in wait mode).
•Since the oscillation stop detection functi on is a function for cases where the XIN clock is stopped by an
external cause, set bits OCD1 to OCD0 t o 00b when the XIN clock stops or is started by a program, (stop
mode is selected or the CM05 bit is changed).
•This function cannot be used when the XIN clock frequency is 2 MHz or below. In this case, set bits OCD1
to OCD0 to 00b.
•To use the low-speed on-chip oscillator cloc k for the CPU clock an d clock sources of peripheral funct ions
after detecting the oscillation stop, set the FRA01 bit in the FRA0 register to 0 (low-speed on-chip
oscillator selected) and bits OCD1 to OCD0 to 11b.
To use the high-speed on-chip oscillato r clo c k fo r the CPU clock and clock sources of peripheral functions
after detecting the oscillation stop, set the FRA00 bit to 1 (high-speed on-chip oscillator on) and the FRA01
bit to 1 (high-speed on-chip oscillator selected) and then set bits OCD1 to OCD0 to 11b.
Table 10.5 Specifications of Oscillation Stop Detection Function
Item Specification
Oscillation stop detection clock and
frequency bandwidth f(XIN) ≥ 2 MHz
Enabled condition for oscillation stop
detection function Set bits OCD1 to OCD0 to 11b
Operation at oscillation stop detection Oscillation stop detection interrupt is generated
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Figure 10.14 Procedure for Switching Clock Source from Low-Speed On-Chip Oscillator to XIN
Clock
Table 10.6 Determining Interrupt Source for Oscillation Stop Detection, Watchdog Timer,
Voltage Monitor 1, and Voltage Monitor 2 Interrupts
Generated Interrupt Source Bit Showing Interr upt Cause
Oscillation stop detection
((a) or (b)) (a) OCD3 bit in OCD register = 1
(b) OCD1 to OCD0 bits in OCD register = 11b and OCD2 bit = 1
Watchdog timer VW2C3 bit in VW2C register = 1
Voltage moni tor 1 VW1C2 bit in VW1C register = 1
Voltage moni tor 2 VW2C2 bit in VW2C register = 1
OCD3 to OCD0: Bits in OCD register
Switch to XIN clock
Multiple confirmations
that OCD3 bit is set to 0 (XIN
clock oscillates) ?
Set OCD1 to OCD0 bits to 00b
Set OCD2 bit to 0
(select XIN clock)
End
YES
NO
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Figure 10.15 Example of Determining Interrupt Source for Oscillation Stop Detection, Watchdog
Timer, Voltage Monitor 1, or Voltage Monitor 2 Interrupt
Interrupt source s ju dgm ent
OCD3 = 1 ?
(XIN clock stopped)
OCD1 = 1
(oscillation stop detection
interrupt enabled) and OCD2 = 1
(on-chip oscillator clock selected
as system clock) ?
VW2C3 = 1 ?
(Watchdog timer
underflow)
VW2C2 = 1 ?
(passing Vdet2)
To oscillation st op detection
interrupt rout i ne To voltage monitor 1
interrupt rou t i ne
To voltage monitor 2
interrupt rout i ne
To watchdog timer
interrupt rout i ne
NO
YES
NO
YES
NO
YES
NO
YES
NOTE:
1. This disables multiple oscillation stop detection interrupts.
OCD1 to OCD3: Bits in OCD register
VW2C2, VW2C3: Bits in VW2C register
Set OCD1 bit to 0 (oscillation stop
detection interrupt disabled).(1)
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10.6 Notes on Clock Generation Circuit
10.6.1 Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instr uction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets th e CM10 b it
to 1.
• Program example to enter stop mode
BCLR 1,FMR0 ; CPU rewrite mode disabled
BSET 0,PRCR ; Protect disabled
FSET I ; Enable interrupt
BSET 0,CM1 ; Stop mode
JMP.B LABEL_001
LABEL_001 :
NOP
NOP
NOP
NOP
10.6.2 Wait Mode
When entering wait m ode, set the FMR01 bit in the FMR0 regist er to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruct ion queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instru ction
BCLR 1,FMR0 ; CPU rewrite mode disabled
FSET I ; Enable interrupt
WAIT ; Wa it mode
NOP
NOP
NOP
NOP
10.6.3 Oscillation Stop Detection Function
Since the oscillation stop detectio n function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
10.6.4 Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
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11. Protection
The protection function protects important registers from being easily overwritten when a program runs out of control.
Figure 11.1 shows the PRCR Register. The registers protected by the PRCR register are listed below.
• Registers protected by PRC0 bit: Registers CM0, CM1, OCD, FRA0, FRA1, and FRA2
• Registers protected by PRC1 bit: Registers PM0 and PM1
• Registers protected by PRC2 bit: PD0 register
• Registers protected by PRC3 bit: Registers VCA2, VW1C, and VW2C
Figure 11.1 PRCR Register
P rotect Regi s te
r
Symbol Address After Reset
PRCR 000Ah 00h
Bit Symbol Bit Name F unction RW
NOTE:
1. This bit is set to 0 after writi ng 1 to the PRC2 bi t and executing a write to any address. Since the other bi ts are not
set to 0, set them to 0 by a program.
PRC2 Protect bit 2 Writing to the PD0 register is enabled.
0 : Disables w riti ng
1 : Enables writi ng(1) RW
RW
—
(b5-b4) Reserved bits Set to 0. RW
PRC0 RW
PRC1 RW
Protect bit 0 Writing to regi sters CM0, CM1, OCD, FRA0, FRA1,
and FRA2 is enabl ed.
0 : Disables w riti ng
1 : Enables writi ng
Protect bit 1 Writing to regi sters PM0 and PM1 is enabled.
0 : Disables w riti ng
1 : Enables writi ng
00b3 b2 b1 b0b7 b6 b5 b4
RO
PRC3
Protect bit 3 Writing to registers VCA2, VW1C, and VW2C is
enabled.
0 : Disables w riti ng
1 : Enables writi ng
—
(b7-b6) Reserved bits When read, the content is 0.
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12. Interrupts
12.1 Interrupt Overview
12.1.1 Types of Interrupts
Figure 12.1 sh ow s th e ty pes of Interrupts.
Figure 12.1 Interrupts
•Maskable Interrupts: The interrupt enable flag (I flag) enables or disables these interrupts. The
interrupt priority order can be changed based on the interrupt priority level.
•Non-Maskable Interrupts: The interrupt en able flag (I flag) does not enable or disable these interrupts.
The interrupt priority order cannot be changed based on interrupt priority
level.
Interrupts
(non-maskable interrupts)
Hardware
Software
(non-maskable interrupts)
(maskable interrupts)
Special
Peripheral functions(1)
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
Single step(2)
Address break(2)
Address match
NOTES:
1. Peripheral function interrupts in the MCU are used to generate peripheral interrupts.
2. Do not use this int errupt. This is for use with development tools only.
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12.1.2 Software Interrupts
A software interrupt is generated when an instructio n is executed. Software interrupts are non-maskable.
12.1.2.1 Undefined Instruction Interrupt
The undefined instruction interrup t is generat e d when the UND instruction is executed.
12.1.2.2 Overflow Interrupt
The overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX,
NEG, RMPA, SBB, SHA, and SUB.
12.1.2.3 BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
12.1.2.4 INT Instruction Interrupt
An INT instruction int errupt is generated when the INT instruction is executed. The INT instruction can select
software interrupt numbers 0 to 63. Software interrupt numbers 3 to 31 are assigned to the peripheral function
interrupt. Therefore, the M CU executes the same interrupt routine when the INT instruction is executed as
when a peripheral function interrupt is generated. For software interrupt numbers 0 to 31, the U flag is saved to
the stack during instruction execution and the U flag is set to 0 (ISP selected) before the interrupt sequence is
executed. The U flag is restored from the stack when returning from the interrupt routine. For software interrupt
numbers 32 to 63, the U flag does not change state during instruction execution, and the selected SP is used.
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12.1.3 Special Interrupts
Special interru pts are non-maskable.
12.1.3.1 Watchdog Timer Interrupt
The watchdog timer in terrupt is gen erated by the watchdog timer. For details, refer to 13. Watchdog Timer.
12.1.3.2 Oscillation Stop Detection Interrupt
The oscillation stop detection interru pt is gen erated by the oscillat ion stop detect ion function . For de tails of the
oscillation stop detection function, refer to 10. Clock Generation Circuit.
12.1.3.3 Voltage Monitor 1 Interrupt
The voltage monitor 1 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.4 Voltage Monitor 2 Interrupt
The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage detection
circuit, refer to 6. Voltage Detection Circuit.
12.1.3.5 Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are for use by develo pm ent tools only.
12.1.3.6 Address Match Interrupt
The address match interrupt is generat ed immediately before executing an instruction that is stored at an
address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER 1 bit in the AIER reg ister is set to
1 (address match interrupt enable). For details of the address match in terrupt, refer to 12.4 Address Match
Interrupt.
12.1.4 Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function o f the MCU and is a maskable
interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral function interrupt. For
details of peripheral functions, refer to th e descript ions of individual peripheral functions.
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12.1.5 Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 12.2 shows an Interrupt Vector.
Figure 12.2 Interrupt Vector
12.1.5.1 Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 12.1 lists the Fixed Vector Tables. The vector address es (H) of fixed vectors are used by the ID code
check function. For details, refer to 20.3 Functions to Prevent Rewriting of Flash Memory .
•
NOTE:
1. Do not use these interrupts. They are for use by development tools only.
Table 12.1 Fixed Vector Tables
Interrupt Source Vector Addresses
Address (L) to (H) Remarks Reference
Undefined instruction 0FFDCh to 0FFDFh Interrupt on UND
instruction R8C/Tiny Series Software
Manual
Overflow 0FFE0h to 0FFE3h Interrupt on INTO
instruction
BRK instruction 0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
Address match 0FFE8h to 0FFEBh 12.4 Address Match
Interrupt
Single step(1) 0FFECh to 0FFEFh
Watchdog timer,
Oscillation stop detection,
Voltage monitor 1,
Voltage monitor 2
0FFF0h to 0FFF3h 13. Watchdog Timer
10. Clock Generation Circuit
6. Voltage Detection Circuit
Address break(1) 0FFF4h to 0FFF7h
(Reserved) 0FFF8h to 0FFFBh
Reset 0FFFCh to 0FFFFh 5. Resets
Vector address (L)
Vector address (H)
MSB LSB
Low address
Mid address
High address0 0 0 0
0 0 0 0 0 0 0 0
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12.1.5.2 Relocatable Vector Tables
The relocatable vector tables occupy 256 bytes beginning from the starting address set in the INTB register.
Table 12.2 lists the Relocatable Vector Tables.
NOTES:
1. These addresses are relative to those in the INTB register.
2. The I flag does not disab l e these interrupts.
Ta b le 12 .2 Relocatable Vector Tables
Interrupt Source Vector Addresse s(1)
Address (L) to Address (H)
Software
Interrupt
Number
Interrupt Control
Register Reference
BRK instruction(2) +0 to +3 (0000h to 0003h) 0 −R8C/Tiny Series Software
Manual
(Reserved) 1 to 2 −−
(Reserved) 3 to 6 −−
Timer RC +28 to +31 (001Ch to 001Fh) 7 TRCIC 14.3 Timer RC
(Reserved) 8 to 9 −−
Timer RE +40 to +43 (0028h to 002Bh) 10 TREIC 14.4 Timer RE
(Reserved) 11 to 12 −−
Key input +52 to +55 (0034h to 0037h) 13 KUPIC 12.3 Key Input Interrupt
A/D + 56 to +59 (0038h to 003Bh) 14 ADIC 17. A/D Converter
(Reserved) 15 to 16 −−
UART0 transmit +68 to +71 (0044h to 0047h) 17 S0TIC 15. Serial Interface
UART0 receive +72 to +75 (0048h to 004Bh) 18 S0RIC
(Reserved) 19 to 21 −−
Timer RA +88 to +91 (0058h to 005Bh) 22 TRAIC 14.1 Timer RA
(Reserved) 23 −−
Timer RB +96 to +99 (0060h to 0063h) 24 TRBIC 14.2 Timer RB
INT1 +100 to +103 (0064h to 0067h) 25 INT1IC 12.2 INT Interrupt
INT3 +104 to +107 (0068h to 006Bh) 26 INT3IC
Comparator 0 +108 to +111 (006 Ch to 006Fh) 27 CM0IC 19. Comparator
Comparator 1 +112 to +115 (0070h to 0073h) 28 CM1IC
INT0 +116 to +119 (0074h to 0077 h) 29 INT0IC 12.2 INT Interrupt
(Reserved) 30 −−
(Reserved) 31 −−
Software interrupt(2) +128 to +131 (0080h to 0083h) to
+252 to +255 (00FCh to 00FFh) 32 to 63 −R8C/Tiny Series Software
Manual
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12.1.6 Interrupt Control
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IP L, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRCIC, CM0IC, and CM1IC
and Figure 12.5 shows the INTiIC Register (i=0, 1, 3).
Figure 12.3 Interrupt Control Register
Int errupt Cont rol Regist er(2)
Address After Reset
004Ah XXXXX000b
004Dh XXXXX000b
004Eh XXXXX000b
0051h XXXXX000b
0052h XXXXX000b
0056h XXXXX000b
TRBIC 0058h XXXXX000b
Bit Symbol Functi o n RW
NOTES:
1.
2.
Symbol
Bit Name
Interrupt priority level select bits
TRAIC
TREIC
KUPIC
ADIC
S0TIC
S0RIC
Rewrite the interrupt control register w hen the interrupt request which is applicable for its register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
b7 b6 b5 b4 b3 b2 b1 b0
RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1 RW
ILVL2 RW
ILVL0
Only 0 can be written to the IR bit. Do not write 1.
IR 0 : Requests no interrupt
1 : Requests interrupt RW(1)
—
(b7-b4) —
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Interrupt request bit
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Figure 12.4 Registers TRCIC, CM0IC, and CM1IC
Int errupt Cont rol Regist er(1)
Address After Reset
0047h XXXXX000b
005Bh XXXXX000b
005Ch XXXXX000b
Bit Symbol Functi o n RW
NOTE:
1.
Symbol
TRCIC
CM0IC
Bit Name
CM1IC
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Rewrite the interrupt control register w hen the interrupt request which is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
ILVL0 RW
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1 RW
—
(b7-b4) —
ILVL2
b7 b6 b5 b4 b3 b2 b1 b0
RW
IR 0 : Requests no interrupt
1 : Requests interrupt RO
Interrupt priority level select bits
Interrupt request bit
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Figure 12.5 INTiIC Register (i=0, 1, 3)
INTi Int errup t Control Regi ster (i =0, 1, 3)(2)
Symbol Address After Reset
INT1IC 0059h XX00X000b
INT3IC 005Ah XX00X000b
INT0IC 005Dh XX00X000b
Bit Symbol Bi t Name Function RW
NOTES:
1.
2.
3.
4.
—
(b7-b6) —
Nothing is assigne d. If nece ssary, set to 0 .
When read, the content is undefined.
Only 0 can be written to the IR bi t. (Do not write 1.)
—
(b5) Reserved bi t Set to 0. RW
POL Polarity sw itch bit(4) 0 : Selects falling edge
1 : Sel e cts rising edge(3) RW
IR Interrupt request bit 0 : Requests no interrupt
1 : Requests interrupt RW(1)
ILVL0 RW
Interrupt priority level select bits b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1 RW
ILVL2 RW
b0
0
Rewrite the interrupt control register w hen the interrupt request w hi ch is applicable for the register i s not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
If the INTiPL bit i n the INTEN register is set to 1 (both edges), set the POL bit to 0 (selects falling edge).
The IR bit may be set to 1 (requests interrupt) when the POL bit is rewritten. Refer to 12.6.4 Changi ng Interrupt
Sources.
b7 b6 b5 b4 b3 b2 b1
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12.1.6.1 I Flag
The I flag enables or disables maskable interrupts. Setting the I flag to 1 (enabl ed) enables maskable interrupt s.
Setting the I flag to 0 (disabled) disables all maskable interrupts.
12.1.6.2 IR Bit
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the interrupt
request is acknowledged and the CPU branches to the corresponding interrupt vector, the IR bit is set to 0 (=
interrupt not request ed).
The IR bit can be set to 0 by a program. Do not write 1 to this bit.
However, the IR bit operations of the timer RC interrupt, comparator 0 interrupt, and comparator 1 interrupt are
different. Refer to 12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt.
12.1.6.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 12.3 lists the Settings of Interrupt Priority Levels and Table 12.4 lists the Interrupt Priority Levels
Enabled by IPL.
The following are conditions under which an interrup t is acknowledged:
•I flag = 1
•IR bit = 1
•Interrupt priority level > IPL
The I flag, IR bit, bits ILVL2 to ILVL0, and IPL are independent of each other. They do not affect one another.
Table 12.3 Settings of Interrupt Priority
Levels
ILVL2 to ILVL0 Bits Interrupt Priority Level Priority Order
000b Level 0 (interrupt disabled) −
001b Level 1 Low
010b Level 2
011b Level 3
100b Level 4
101b Level 5
110b Level 6
111b Level 7 High
T able 12.4 Interrupt Priority Levels Enabled by
IPL
IPL Enabled Interrupt Priority Levels
000b Interrupt level 1 and above
001b Interrupt level 2 and above
010b Interrupt level 3 and above
011b Interrupt level 4 and above
100b Interrupt level 5 and above
101b Interrupt level 6 and above
110b Interrupt level 7 and above
111b All maskable interrupts are disabled
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12.1.6.4 Interrupt Sequence
An interrupt sequence is p erformed between an interrupt request acknowled gement and interrupt routine
execution.
When an interrupt request is generated while an instruction is being executed, the CPU det ermines it s interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instructions, if an interrupt request is generated while the
instruction is being executed, the MCU su spends the instruction to start the inter rupt sequence. The interrup t
sequence is performed as indicated below.
Figure 12.6 show s th e Time Required for Executing Interrupt Sequence.
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading address
00000h. The IR bit for the corresponding interru pt is set to 0 (interrupt not requested).(2)
(2) The FLG register is saved to a temporary register(1) in the CPU immediately before entering the
interrupt sequence.
(3) The I, D and U flags in the FLG register are set as follows:
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt n umber 32 to 63
is executed.
(4) The CPU’s internal temporary regi st er(1) is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt prio rity level of the acknowledged interrupt is set in the IPL.
(7) The starting address of th e interrupt routine set in the interrupt vector is stored in the PC.
After the inte rrupt sequence is compl eted, instructions are executed from the starting address of the interrupt
routine.
Figure 12.6 Time Required for Executing Interrupt Sequence
NOTES:
1. This register cannot be used by user.
2. Refer to 12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt for the
IR bit operations of the timer RC interrupt, comparat or 0 in terrupt, and comparator 1 interrupt.
1234567891011 12 13 14 15 16 17 18 19 20
CPU Clock
Address Bus
Data Bus
RD
WR
Address
0000h Undefined
Undefined
Undefined
Interrupt
information
SP-2 SP-1 SP-4 SP-3 VEC VEC+1 VEC+2 PC
SP-2
contents SP-1
contents SP-4
contents SP-3
contents VEC
contents VEC+1
contents VEC+2
contents
The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue buffer is
ready to acknowledge instructions.
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12.1.6.5 Interrupt Response Time
Figure 12.7 shows the Interrupt Respo nse Time. The interr upt response time is the period between an interrupt
request generation and the execution of the first i nstructio n in the int errupt routine. The int errupt response ti me
includes the period between interrupt request generation and the completion of execution of the instruction
(refer to (a) in Figure 12.7) and the period required to perform the interrupt sequence (20 cycles, refer to (b) in
Figure 12.7).
Figure 12.7 Interrupt Response Time
12.1.6.6 IPL Change when Interrupt Request is Acknowledged
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 12.5 is set in the
IPL.
Ta ble 12.5 lists the IPL Value When Software or Special Interrupt Is Acknowledged.
Table 12.5 IPL Value When Software or Special Interrupt Is Acknowledged
Interrupt Source Value Set in IPL
Watchdog timer, oscillation stop detection, voltage monitor 1,
voltage monitor 2, addr e ss br ea k 7
Software, address match, single-step Not changed
Interrupt request i s generated. Interrupt request is acknowledged.
Instruct i on Interrupt sequence Instruction i n
interrupt routine
Time
(a) 20 cycles (b)
Interrupt response time
(a) Period between interrupt request generation and the completion of execution of an
instruction. The length of time varies depending on the instruction being executed. The
DIVX instruction requires t he longest time, 30 cycles (no wait and whe n the register is set
as the divisor)
(b) 21 cycles for address match and single-step interrupts.
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12.1.6.7 Saving a Register
In the interrupt sequence, the FLG register and PC are saved to the stack.
After an extended 16 bits, 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG
register, are saved to the stack, the 16 low-ord e r bits in the PC are saved.
Figure 12.8 shows the Stack State Before and After Acknowledg e ment of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM
instruction can save several registers in the register bank being currently used(1) with a single instruction.
NOTE:
1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and F B .
Figure 12.8 Stack State Before and After Acknowledgement of Interrupt Request
The register saving operation, wh ich is performed as part o f the interrupt sequence, saved in 8 bits at a time in
four steps.
Figure 12.9 shows the Register Saving Operation.
Figure 12.9 Register Saving Operation
Stack
[SP]
SP valu e before
interru pt is ge ne r at ed
Previous stack contents
LSBMSB
Address
Previous stack contents
m−4
m−3
m−2
m−1
m
m+1
Stack stat e before interrupt request
is acknowledged
[SP]
New SP value
Previous stack contents
LSBMSB
Previous stack contents
m
m+1
Stack state after interrupt request
is acknowledged
PCL
PCM
FLGL
FLGH PCH
m−4
m−3
m−2
m−1
Stack
Address
PCH : 4 High-order bits of PC
PCM : 8 Middle-order bits of PC
PCL : 8 Low-order bits of PC
FLGH : 4 High-order bits of FLG
FLGL : 8 Low-order bits of FLG
NOTE:
1.When executing software number 32 to 63 INT instructions,
this SP is specified by the U flag. Otherwise it is ISP.
Stack
Compl eted savi ng
registers in four
operations.
Address
[SP]−5
[SP]
PCL
PCM
FLGL
FLGH PCH
(3)
(4)
(1)
(2)
Saved, 8 bits at a time
Sequence in which
order registers are
saved
NOTE:
1.[SP] indicates the initial value of the SP when an interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4. When executing
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
[SP]−4
[SP]−3
[SP]−2
[SP]−1PCH : 4 High-order bits of PC
PCM : 8 Middle-order bits of PC
PCL : 8 Low-order bits of PC
FLGH : 4 High-order bits of FLG
FLGL : 8 Low-order bits of FLG
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12.1.6.8 Returning from an Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the FLG register and PC, which have
been saved to the stack, are automatically restored. The program, that was running before the i nterrupt request
was acknowledged, starts running again.
Restore registers saved by a program in an interrupt routine using the POPM instruction or others before
executing the REIT instruction.
12.1.6.9 Interrupt Priority
If two or more interrupt requests are generated while a single instruction is being executed, the interrupt with
the higher priority is acknowledged.
Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts (peripheral functions).
However, if two or more maskable interrupts have the same priority level, th eir interrupt priori ty is resolv ed by
hardware, and the higher priority interrupts acknowledged.
The priority levels of special interrupts, such as reset (reset has the highest priority) and watchdog timer, are set
by hardware.
Figure 12.10 shows the Priority Levels of Hardware Interrupts.
The interrupt priori ty does not affect software interrupts. The MCU jumps to the interrup t routine when the
instruction is executed.
Figure 12.10 Priority Levels of Hardware Interrupts
Address break
Watchdog timer
Oscillation stop detection
Voltage monitor 1
Voltage monitor 2
Peripheral function
Single step
Address match
High
Low
Reset
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12.1.6.10 Interrupt Priority Judgement Circuit
The interrupt priority ju dgem e nt circuit selects the highest priority interrupt, as shown in Figure 12.11.
Figure 12.11 Interrupt Priority Level Judgement Circuit
UART0 receive
A/D conversion
Key input
IPL Lowest
Highest
Priority of peripheral function interrupts
(if priority levels are same)
Interrupt request level
judgment output signal
Interrupt request
acknowledged
I flag
Address match
Watchdog timer
Oscillation stop detection
Voltage monitor 1
UART0 transmit
Timer RE
INT0
INT1
INT3
Timer RB
Timer RA
Priority level of interrupt
Level 0 (default value)
Voltage monitor 2
Timer RC
Comparator 0
Comparator 1
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12.2 INT Interrupt
12.2.1 INTi Interrupt (i = 0, 1, 3)
The INTi interrupt is generated by an INTi input. When using the INTi interrupt, t he INTiEN bit in the INTEN
register is set to 1 (enable). The edge polarity is selected using the INTiPL bit in the INTEN register and the
POL bit in the INTiIC register.
Inputs can be passed through a digital filter wit h three di fferent sampling clocks.
The INT0 pin is shared with the pulse output forced cutoff of timer RC and is shared with the external trigger
input of timer RB.
Figure 12.12 shows the INTEN Register. Fi gure 12.13 shows the INTF Regi ster.
Figure 12.12 INTEN Register
E xtern al Input E nabl e Regi st er
Symbol Address After Reset
INTEN 00F9h 00h
Bit Symbol Bi t Name Function RW
INT0
_
____ input enable bit
INT0
_
____ input polarity sel ect bit(1,2)
INT1
_
____ input enable bit
INT1
_
____ input polarity sel ect bit(1,2)
INT3
_
____ input enable bit
INT3
_
____ input polarity sel ect bit(1,2)
NOTES:
1.
2.
INT3PL
b3 b2 b1 b0b7 b6 b5 b4
00
RW
INT0EN
RW
INT1PL 0 : One edge
1 : Both edges RW
INT3EN
When setting the INTiPL bit (i = 0 to 3) to 1 (both edges), set the POL bit in the INTiIC register to 0 (selects falling
edge).
The IR bit in the INT iIC register may be set to 1 (requests interrupt) wh en the INTi PL bit is rewritten. Refer to 12.6.4
Changing Interrupt Sources.
0 : Disable
1 : Enable
0 : O ne edge
1 : Both edges
0 : O ne edge
1 : Both edges
RW
INT0PL RW
INT1EN 0 : Di sable
1 : Enable
0 : Disable
1 : Enable RW
—
(b5-b4) S e t to 0 . RW
Reserved bits
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Figure 12.1 3 INTF Regi st er
INT0
_
______
Input Filt er S elec t Regis ter
Symbol Address After Reset
INTF 00FAh 00h
Bit Symbol Bit Name Function RW
INT0
_____ input fi lter sel ect bi ts
INT1
_____ input fi lter sel ect bi ts
INT3
_____ input fi lter sel ect bi ts
—
(b5-b4) RW
Reserved bits
INT1F0 b3 b2
0 0 : No fil ter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Fil ter w ith f32 sampling
RW
INT1F1 RW
INT3F1
INT3F0
00
RW
b1 b0
0 0 : No fil ter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Fil ter w ith f32 sampling
RW
b7 b6
0 0 : No fil ter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Fil ter w ith f32 sampling
S e t to 0.
b3 b2 b1 b0b7 b6 b5 b4
INT0F0 RW
INT0F1 RW
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12.2.2 INTi Input Filter (i = 0, 1, 3)
The INTi input cont ains a digital filter. The sampling clock is selected by bits INTiF1 to INTiF0 in the INTF
register. The IR bit in the INTiIC register is set to 1 (interrupt requested) when the INTi level is sampled for
every sampling clock and the sampled input level matches three times.
Figure 12.14 sh ows the Configuration of INTi Input Filter. Figure 12.15 shows an Operating Example of INTi
Input Filter.
Figure 12.14 C onfiguration of INTi Input Filter
Figure 12.15 Operating Example of INTi Input Filter
INTiF0, INTiF1: Bits in INTF register
INTiEN, INTiPL: Bits in INTEN register
i = 0, 1, 3
= 01b
INTi
Port direction
register(1)
Sampling clock
Digital filter
(input level
matches 3x)
INTi interrupt
= 10b
= 11b
f32
f8
f1
INTiF1 to INTiF0
INTiEN
Other than
INTiF1 to INTiF0
= 00b
= 00b INTiPL = 0
INTiPL = 1
NOTE:
1. INT0: Port P4_5 direction register
INT1: Port P1_5 direction register when using the P1_5 pin
Port P1_7 direction register when using the P1_7 pin
INT3: Port P3_3 direction register
Both edges
detection
circuit
INTi input
Sampling
timing
IR bit in
INTiIC register
Set to 0 in program
This is an operatio n example when bits INTiF1 to INTiF0 in the
INTiF register are set to 01b, 10b, or 11b (passing digital filter).
i = 0, 1, 3
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12.3 Key Input Interrupt
A key input interrupt request is generated by one of the input edges of the K10 to K13 pins. The key input interrupt
can be used as a key-on wake-up function to exit wait or stop mode.
The KIiEN (i = 0 to 3) bit in the KIEN register can select whether the pins are used as KIi input. The KIiPL bit in
the KIEN register can select the input polarity.
When inputting “L” to the KIi pin which sets the KIiPL bit to 0 (falling edge), the input of the other pins K10 to
K13 is not detected as interrupts. Also, when inputting “H” to the KIi pin, which sets the KIiPL bit to 1 (rising
edge), the input of the other pins K10 to K13 is not detected as interrupts.
Figure 12.16 shows a Block Diag ram of Key Input Interrupt.
Figure 12.16 Block Diagram of Key Input Interrupt
KI3
Pull-up
transistor
KI2
Pull-up
transistor
KI3PL = 0
KI3PL = 1
PD1_3 bit
KI3EN bit
PU02 bit in PUR0 register
PD1_3 bit in PD1 regis ter KUPIC re gister
Interrupt control
circuit Key input inter r upt
request
KI2PL = 0
KI2PL = 1
PD1_2 bit
KI2EN bit
KI1
Pull-up
transistor KI1PL = 0
KI1PL = 1
PD1_1 bit
KI1EN bit
KI0
Pull-up
transistor KI0PL = 0
KI0PL = 1
PD1_0 bit
KI0EN bit KI0EN, KI1EN, KI2EN, KI3EN,
KI0PL, KI1 PL, KI2PL, KI3PL: Bi ts in KIEN register
PD1_0, PD1_1, PD1_2, PD1_3: Bits in PD1 regis ter
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Figure 12.1 7 KIEN Regist er
K ey Input E n abl e Register(1)
Symbol Address After Reset
KIEN 00FBh 00h
Bit Symbol Bit Name Functi on RW
NOTE:
1.
RW
KI0 input polarity select bit 0 : Falling edge
1 : Rising edge
KI1 input enable bit 0 : Disabl e
1 : Enable
b3 b2
RW
KI2EN RW
KI1PL KI1 i np ut polarity select bit 0 : Falling edge
1 : Rising edge
KI2 input enable bit 0 : Disabl e
1 : Enable
b7 b6 b5 b4 b1 b0
The IR bit in the KUPIC register may be set to 1 (requests i n terrupt) w hen the KIEN register is rewritten.
Refer to 12.6.4 Changing Interrupt Sources.
KI1EN RW
KI3EN KI3 i np ut enable bit
KI3PL RW
KI2PL KI2 i np ut polarity select bit 0 : Falling edge
1 : Rising edge
KI3 input polarity select bit 0 : Falling edge
1 : Rising edge
KI0EN RW
KI0PL RW
KI0 input enable bit 0 : Disabl e
1 : Enable
RW
0 : Disable
1 : Enable
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12.4 Address Match Interrupt
An address ma tch interrupt reques t is generated imme diately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When
using the on-chip debugger, do not set an address match interrupt (registers of AIER, RMAD0, and RMAD1 and
fixed vector tables) in a user system.
Set the starting address of any instruction in the RMADi register. Bits AIER0 and AIER1 in the AIER0 register can
be used to select enable or disable of the interrupt. The I flag and IPL do not affect the address match interrupt.
The value of the PC (Refer to 12.1.6.7 Saving a Register for the value of the PC) which is saved to the stack when
an address match inter rupt is acknowledged varies depending on the instruction at the address indicated by the
RMADi register. (The appropriate return address is not saved on the stack.) When returning from the address match
interrupt, return by one of the following means:
•Change the content of the stack and use the REIT instruction.
•Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowl edged.
Then use a jump instruction.
Table 12.6 lists the Val ues of PC Saved to Stack when Address Match Interrupt is Acknowledged , Tab le 12.7 lists
the Correspondence Between Address Match Interrupt Sources and Associated Registers.
Figure 12.18 shows Registers AIER and RMAD0 to RMAD1.
NOTES:
1. Refer to the 12.1.6.7 Savi n g a Re gi st er for the PC value saved.
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
Table 12.6 Values of PC Saved to Stack when Address Match Interrupt is Acknowledged
Address Indicate d by RM ADi Reg ist er (i = 0 or 1) PC Value Saved (1)
• Instruction with 2-byte operation code(2)
• Instruction with 1-byte operation code(2)
ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest
OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ #IMM8,dest
STNZ #IMM8,dest STZX #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest PUSHM src POPM dest
JMPS #IMM8 JSRS #IMM8
MOV.B:S #IMM,dest (however, dest = A0 or A1)
Address indicated by
RMADi register + 2
• Instructions other than the above Address indicated by
RMADi register + 1
Ta b le 12 .7
Correspondence Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
Address match inte rrupt 0 AIER0 RMAD0
Address match inte rrupt 1 AIER1 RMAD1
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Figure 12.1 8 Registers AI ER and RMAD0 to RMAD1
A
ddres s M atch Int e rrupt E nab le Regist e
r
Symbol Address After Reset
AIER 0013h 00h
Bit Symbol Bi t Name Function RW
—
(b7-b2) —
Nothing is assigne d. If n ecessary, set to 0.
When read, the content is 0.
b7 b6 b5 b4
0 : Disable
1 : Enable RW
b3 b2 b1 b0
Address match interrupt 0 enable bit 0 : Disable
1 : Enable RW
AIER1 Address match interrupt 1 enable bit
AIER0
A ddress M at ch Int errupt Regi st er i (i = 0 or 1)
b0
Symbol Address After Reset
RMAD0 0012h-0010h 000000h
RMAD1 0016h-0014h 000000h
Setting Range RWFunction
RW
(b19)
b3 (b15)
b7 (b8)
b0 b7
(b16)
b0
—
—
(b7-b4) Nothi ng is assigned. If necessary, set to 0.
When read, the content is 0.
Address setting register for address match interrupt 00000h to FFFFFh
(b23)
b7
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12.5 Timer RC Interrupt, Comparator 0 Interrupt, and Comparator 1 Interrupt
As with other maskable interrupts, the timer RC inter rupt, comparator 0 interrupt, and comparator 1 interrupt are
controlled by the combination of the I flag, IR bit, bits ILVL0 t o ILVL2, and IPL. However, some differences from
other maskable interrupts apply.
Refer to chapters of the individual peripheral functions (14.3 Timer RC and 19.4 Comparator 0 Interrupt and
Comparator 1 Interrupt) for the status register and enable register.
Refer to 12.1.6 Interrupt Control for the interrupt control register.
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12.6 Notes on Interrupts
12.6.1 Reading Address 00000h
Do not read address 0000 0h by a program. When a maskable interrupt requ est is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
12.6.2 SP Setting
Set any value in the SP before an interrupt is acknowl edged. The SP i s set to 000 0h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program ma y ru n out of control.
12.6.3 External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is ne cessary for the signal input
to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, re fer to Table 21.19 (VCC = 5V), Table 21 .25 (VCC = 3V) External Interrupt INTi (i = 0, 1, 3)
Input.
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12.6.4 Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripher al
function involve s interrupt so urces, edge polarities, an d timing, set t he IR bit to 0 (no i nterrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 12.19 shows an Examp le of Procedure for Changing Interrupt Sources.
Figure 12.19 Example of Procedure for Changing Interrupt Sources
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated, disable
the peripheral function before changing the interrupt
source. In this case, use the I flag if all maskable interrupts
can be disabled. If all maskable interrupts cannot be
disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register
Contents for the instructions to be used and usage notes.
Interrupt source change
Disable in terrupts(2, 3)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Change interrupt source (including mode
of peripheral function)
Enable interrupts(2, 3)
Change completed
IR bit: The interrupt control register bit of an
interrupt whose source is changed.
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12.6.5 Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are gen erated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt req uested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When di sabling interrupts using the I flag, set the I flag as shown in the sample programs b elow. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
NOP ;
NOP
FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
MOV.W MEM,R0 ; Dummy read
FSET I ; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
POPC FLG ; Enable interrupts
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13. Watchdog Timer
The watchdog timer is a function that detects when a program is out of control. Use of the watchdog timer is
recommended to improve the reliability of the system. The watchdog timer contains a 15-bit counter and allows
selection of count source protection mode enable or disable.
Table 13.1 lists the Specifications for Watchdog Timer.
Refer to 5.5 Watchdog Timer Reset for details on the watchdog timer.
Figure 13.1 shows the Block Diagram of Watchdog T imer, Figure 13.2 shows the Registers WDTR, WDTS, and WDC
and Figure 13.3 shows the Registers CSPR and OFS.
Figure 13.1 Block Diagram of Watchdog Timer
Table 13.1 Specifications for Watchdog Timer
Item Count Source Protection Mode Disabled Count Source Protection Mode Enabled
Count source CPU clock Low-speed on-chip oscillator clock
Count operation Decrement
Count start condition Either of the following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS re gist er
Count stop condition Stop mode, wait mode None
Reset condition of
watchdog timer • Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Operation at the time
of underflow Watchdog timer interrupt or watchdog
timer reset Watchdog timer reset
Select functions • Division ratio of prescaler
Selected by the WDC7 bit in th e WDC re gis te r
• Count source protection mode
Whether count source protection mode is enabled or disabled after a reset can
be selected by the CSPROINI bit in the OFS register (flash memory). If count
source protection mode is disabled after a reset, it can be enabled or disabled
by the CSPRO bit in the CSPR register (program).
• Starts or stops of the watchdog timer after a reset
Selected by the WDTON bit in the OFS register (flash memory).
CPU clock
1/16
1/128 Watchdog timer
Internal reset signal
Write to WDTR register
WDC7 = 0
WDC7 = 1
Set to
7FFFh(1)
PM12 = 1
Watchdog
timer reset
PM12 = 0
Watchdog timer
interrupt request
Prescaler
CSPRO = 0
fOCO-S CSPRO = 1
CSPRO: Bit in CSPR register
WDC7: Bit in WDC register
PM12: Bit in PM1 register
NOTE:
1. When the CSPRO bit is set to 1 (count source protection mode enabled), 0FFFh is set.
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Figure 13.2 Registers WDTR, WDTS, and WDC
Watc h dog Ti m er Cont rol Regi st er
Symbol Address After Reset
WDC 000Fh 00X11111b
Bit Symbol Bit Name Functi on RW
b3 b2 b1 b0
RW
Hi gh-order bits of w atchdog timer—
(b4-b0)
RW
—
(b5) RW
00
b7 b6 b5 b4
Reserved bit S e t to 0. Whe n read, the content is undefined.
RO
WDC7
—
(b6) Reserved bit S e t to 0.
Prescaler select bit 0 : Divide-by-16
1 : Divide-by-128
Watc h dog Ti m er Res e t Regi st er
Symbol Address After Reset
WDTR 000Dh Undefined RW
NOTES:
1.
2.
When 00h is w ritten before w riting FFh, the watchdog timer is reset.(1)
The default value of the w atchdog timer i s 7FFFh w hen count source protection
mode is disabled and 0FFFh w hen count source protection mode is enabled.(2)
Function
Do not generate an interrupt between w hen 00h and FFh are written.
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode enabled ),
0FFFh is set in the w atchdog timer.
WO
b7 b0
Wat chdog Ti m er Start Regi s t er
Symbol Address After Reset
WDTS 000Eh Undefined RW
WO
Function
The w atchdog timer starts counting after a w rite i nstruction to this regi ster.
b0b7
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Figure 13.3 Registers CSPR and OFS
Count Sourc e Prot ection M od e Regi s ter
Symbol Address After Reset(1)
CSPR 001Ch 00h
Bit Symbol B it Name Function RW
NOTES:
1.
2.
000
b7 b6 b5 b4 b3 b2 b1 b0
Write 0 before writing 1 to set the CSPRO bit to 1.
0 cannot be set by a program.
When 0 is written to the CSPROINI bit i n the OF S register, the val ue after reset is 10000000b.
0
Reserved Bits Set to 0.
RW
0
CSPRO Count Source Protection Mode
Select Bit(2) 0 : Count source protection mode disabled
1 : Count source protection mode enabled
—
(b6-b0) RW
00
Opti on Fu nct i on S elect Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(2)
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2.
—
(b5) Reserved bit Set to 0. RW
—
(b4) Reserved bit Set to 1. RW
b3 b2 b1 b0b7 b6 b5 b4
101
WDTON RW
Wa tchdog timer start
select bit 0 : Starts w atchdog timer automatical ly after reset
1 : W a tchdog timer i s inactive after reset
1
—
(b1) RW
Reserved bit Set to 1.
ROMCR ROM code protect
di sabled bi t 0 : ROM code protect disabl ed
1 : RO MCP1 enabled RW
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : RO M code protect disabled RW
If the block includi ng the OFS register is erased, F Fh is set to the O FS register.
—
(b6) Reserved bit Set to 1. RW
CSPROINI Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
The OFS register is on the flash memory. W rite to the O FS register with a program. After writi ng is completed, do not
write additions to the OFS register.
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13.1 Count Source Protection Mode Disabled
The count source of the watchdog timer is the CPU clock when count source protection mode is disabled.
Table 13.2 lists the Watchdog Timer Specifications (with Count Source Protection Mode Disabled).
NOTES:
1. The watchdog timer is reset when 00h is written to th e WDT R re gist er befor e FF h . Th e presca ler is
reset after the MCU is r eset. Some erro rs in the per iod of the watch dog timer may be caused by the
prescaler.
2. The WDTON bit cannot be chan ged by a prog ram. To set the WDT ON bit, write 0 to bit 0 of addres s
0FFFFh with a flash programmer.
Table 13.2 Watchdog Timer Specifications (with Count Source Protection Mode Disabled)
Item Specification
Count source CPU clock
Count operation Decrement
Period
Division r at io of prescaler (n) × count va lu e of watchdog timer (3 27 68 )
(1)
CPU clock
n: 16 or 128 (selected by WDC7 bit in WDC register)
Example: When the CPU clock frequency is 16 MHz and prescaler
divides by 16, the period is approximately 32.8 ms
Reset condition of watchdog
timer • Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Count start condition The WDTON bit(2) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset
• When the WDTON bit is set to 1 (watchdog timer is in stop state after
reset)
The watchdog timer an d prescaler stop after a r eset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts automatically
after exiting)
• The watchdo g timer and pres ca ler start counting automatically after a
reset
Count stop condition S top and wait modes (inherit the count from the held value after exiting
modes)
Operation at time of underflow •When the PM12 bit in the PM1 register is set to 0
Watchdog timer interrupt
• When the PM12 bit in the PM1 register is set to 1
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)
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13.2 Count Source Protection Mode Enabled
The count source of the watchdog timer is the low-speed on-chip oscillator clock when count source protection
mode is enabled. If the CPU clock stops when a program is out of control, the clock can still be supplied to the
watchdog timer.
Table 13.3 lists the Watchdog Timer Specifications (with Count Source Protection Mode Enabled).
NOTES:
1. The WDTON bit cannot be chan ged by a prog ram. To set the WDT ON bit, write 0 to bit 0 of addres s
0FFFFh with a flash programmer.
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The
CSPROINI bit cannot be changed by a prog ram. To set the CSPROINI bit, write 0 to bit 7 of address
0FFFFh with a flash programmer.
Table 13.3 Watchdog Timer Specifications (with Count Source Protection Mode Enabled)
Item Specification
Count source Low-speed on-chip oscillator clock
Count operation Decrement
Period Count value of watchdog timer (409 6)
Low-speed on-chip oscillator clock
Example: Period is approxima tely 32.8 ms when the low-speed on-
chip oscillator clock frequency is 125 kHz
Reset condition of watchdog
timer • Reset
• Write 00h to the WDTR register before writing FFh
• Underflow
Count start condition The WDTON bit(1) in the OFS register (0FFFFh) selects the operation
of the watchdog timer after a reset.
• When the WDTON bit is set to 1 (watchdog timer is in stop state
after reset)
The watchdog timer and prescaler stop after a reset and the count
starts when the WDTS register is written to
• When the WDTON bit is set to 0 (watchdog timer starts
automatically after reset)
The watchdog timer and prescaler start counting automatically after
a reset
Count stop condition None (The count does not stop in wait mode after the cou nt starts.
The MCU does not enter stop mode.)
Operation at time of underflow Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset .)
Registers, bits • When setting the CSPPRO bit in the CSPR register to 1 (count
source protection mode is enabled)(2), the following are set
automatically
- Set 0FFFh to the watchdog timer
- Set the CM14 bit in the CM1 register to 0 (low- speed on-chip
oscillator on)
- Set the PM12 bit in the PM1 register to 1 (The watchdog timer is
reset when watchdog timer underflows)
• The following conditions ap ply in co un t sou rc e pr ot ec tion mo de
- Writing to the CM10 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The MCU does not enter stop
mode.)
- Writing to the CM14 bit in the CM1 register is disabled (It remains
unchanged even if it is set to 1. The low-speed on-chip oscillator
does not stop.)
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14. Timers
The MCU has two 8-bit t imers with 8-bit prescalers, a 16-bit timer, and a timer with a 4-bit counter and an 8-bit
counter. The two 8-bit timers with 8-bit prescalers are timer RA and timer RB. These timers contain a reload register to
store the default value of the counter. The 16-bit timer is timer RC, and has input capture and output compare
functions. The 4-bit and 8-bit counters are timer RE, and has an output compare function. All the timers operate
independently.
Table 14.1 lists Functional Comparison of Timers.
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Table 14.1 Functional Comparison of Timers
Item Timer RA Timer RB Timer RC Timer RE
Configuration 8-bit timer with 8-
bit prescaler (with
reload register)
8-bit timer with 8-
bit prescaler (with
reload register)
16-bit free-run timer (with
input capture and output
compare)
4-bit counter
8-bit counter
Count Decrement Decrement Increment Increment
Count source • f1
•f2
•f8
•fOCO
•f1
•f2
•f8
•Timer RA
underflow
•f1
•f2
•f4
•f8
•f32
• fOCO40M
• TRCCLK
•f4
•f8
•f32
Function Timer Mode provided provided provided
(input capture funct ion,
output compare function)
not provided
Pulse Output Mode provided not provided not provided not provided
Event Counter
Mode provided not provided not provided not provided
Pulse Width
Measurement Mode provided not provided not provided not provided
Pulse Period
Measurement Mode provided not provided not provided not provided
Programmable
Waveform
Generation Mode
not provided provided not provided not provided
Programmable
One-Shot
generation Mode
not provided provided not provided not provided
Programmable W ait
One-Shot
Generation Mode
not provided provided not provided not provided
Input Capture Mode not provide d not provided provided not provided
Output Compare
Mode not provided not provided provided provided
PWM Mode not provided not provided provided not provided
PWM2 Mode not provide d not provided provided not provided
Input Pin TRAIO INT0 INT0, TRCCLK, TRCTRG
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
−
Output Pin TRAO
TRAIO TRBO TRCIOA, TRCIOB,
TRCIOC, TRCIOD TREO
Related Interrupt Timer RA interrupt
INT1 interrupt Timer RB interrupt
INT0 interrupt Compare Match / Input
Capture A to D interrupt
Overflow interrupt
INT0 interrupt
Timer RE
interrupt
Timer Stop provided provided provided provided
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14.1 Timer RA
Timer RA is an 8-bit timer with an 8-bit prescaler .
The prescaler and timer each consist of a reload register and counter. The reload register and counter are allocated
at the same address, and can be accessed when accessing registers TRAPRE and TRA (refer to Tables 14.2 to 14.6
the Specification of Each Modes).
The count source for t im er RA is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.1 shows a Blo ck Diagram of Timer RA. Figures 14.2 and 14.3 show the registers associat ed with Timer
RA.
Timer RA contains the following five operating modes:
•Timer mode: The timer counts the internal count source.
•Pulse output mode: The timer counts the internal count source and outputs pulses which
invert the polarity by underflow of the timer.
•Event counter mode: The timer counts external pulses.
•Pulse width measurement mode: The timer measures the pulse width of an external pulse.
•Pulse period measurement mode: The timer measures the pulse period of an external pulse.
Figure 14.1 Block Diagram of Ti mer RA
= 000b
= 001b
= 011b
f2
f8
f1
= 010b
fOCO
TCK2 to TCK0 bit TMOD2 to TMOD0
= other than 010b
Counter
Reload
register
TRAPRE register
(prescaler)
Data bus
Timer RA interrupt
Write to TRAMR register
Write 1 to TSTOP bit
TCSTF, TSTOP: TRACR register
TEDGSEL, TOPCR, TOENA, TIOSEL, TIPF1, TIPF 0: TRAIOC register
TMOD2 to TMOD0, TCK2 to TCK0, TCKCUT: TRAMR register
Toggle
flip-flop
Q
QCLR
CK
TOENA bit
TRAO pin
INT1/TRAIO (P1_5) pin
TCSTF bit
TCKCUT bit
TMOD2 to TMOD0
= 011b or 100b
TMOD2 to TMOD0
= 010b
Polarity
switching
Digital
filter
Counter
Reload
register
TRA register
(timer)
TIPF1 to TIPF0 bits
= 01b
= 10b
f8
f1
= 11b
f32
TIOSEL = 0
TIOSEL = 1
Count control
circle
TMOD2 to TMOD0 = 001b
TOPCR bit
Underflow signal
Measurement completion
signal
TIPF1 to TIPF0 bits
= other than
000b
= 00b
INT1/TRAIO (P1_7) pin
TEDGSEL = 1
TEDGSEL = 0
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Figure 14.2 Registers TRACR and TRAIOC
Ti me r RA Contro l Re
g
iste
r
(4)
Symbol Address After Reset
TRACR 0100h 00h
B it Symbol Bit Name Functi o n RW
NOTES:
1.
2.
3.
4.
5.
RW
TCSTF
RW
RW
RO
TSTART
0 : Count stops
1 : During count
0 : Count stops
1 : Count starts
Timer RA count status flag(1)
TSTOP
Active edge j udgment
flag(3, 5)
Timer RA underflow flag(3, 5) 0 : No underflow
1 : Underflow
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
b3 b2
When this bit is set to 1, the count is forcibly
stopped. When read, its content is 0.
—
(b3)
b1 b0b7 b6 b5 b4
Timer RA count start bit(1)
Timer RA count forcible stop
bit(2)
Bits TEDGF and TUNDF can be set to 0 by writing 0 to these bits by a program. However, their value remai n s
unchanged when 1 is w ritten.
In pulse w idth measurement mode and pulse period measurement mode, use the MOV instruction to set the TRACR
register. If it is necessary to avoid changing the values of bits TEDGF and T UNDF, write 1 to them.
—
(b7-b6) —
—
RW
TEDGF 0 : Active edge not received
1 : Active edge received
(end of measurement period)
Set to 0 i n timer mode, pulse output mode, and event counter mode.
TUNDF
When the TSTOP bi t is set to 1, bi ts TSTART and T CSTF and registers TPRAPRE and TRA are set to the values after
a reset.
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
Refer to 14.1.6 Notes on Timer RA for precautions regarding bits TSTART and TCSTF.
Ti m er RA I/ O Contro l Regi st e
r
Symbol Address After Reset
TRAIOC 0101h 00h
B it Symbol Bit Name Functi o n RW
INT1
_
____/TRAIO select bit
b3 b2
TIOSEL
b1 b0b7 b6 b5 b4
—
TEDGSEL RW
TOPCR RW
TRAIO p olarity switch b it
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
—
(b7-b6)
RW
TIPF0 RW
TOENA RW
TRAIO input filter select bits
TIPF1
Function varies depending on operating mode.
TRAIO output control bit
TRAO output enable bit
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Figure 14.3 R egisters TRAMR, TRAPRE, and TRA
Ti me r RA M o de Reg i ste
r
Symbol Address After Reset
TRAMR 0102h 00h
B it Symbol Bit Name Functi o n RW
NOTE:
1.
TCK0
b3 b2
—
(b3)
b1 b0
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
RW
—
RW
b7 b6 b5 b4
RW
TMOD1 RW
TMOD0 Timer RA operating mode
select bits(1) b2 b1 b0
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : Event counter mode
0 1 1 : Pulse width measurement mode
1 0 0 : Pulse period measurement mode
1 0 1 :
1 1 0 : Do not set.
1 1 1 :
TMOD2 RW
When both the TSTART and TCSTF bits in the TRACR regi ster are set to 0 (count stops), rew ri te this register.
RW
Timer RA count source
cutoff bit 0 : Provides count source
1 : Cuts off count source
TCK2
RW
Timer RA count source
select bits b6 b5 b4
0 0 0 : f1
0 0 1 : f8
0 1 0 : fOCO
0 1 1 : f2
1 0 0 :
1 0 1 : Do not set.
1 1 0 :
1 1 1 :
TCKCUT
TCK1
Ti mer RA Prescal er Reg i st e
r
Symbol Address After Reset
TRAPRE 0103h FFh(1)
Mode Function Setting Range RW
NOTE:
1.
00h to FFh RW
Pulse w idth
measurement mode
b0
Timer mode
b7
Pulse output mode RW00h to FFh
Counts an internal count source RW00h to FFh
When the TSTOP bit in the TRACR register is set to 1, the TRAPRE register is set to FFh.
Event counter mode Counts an external count source 00h to FF h RW
Measure pulse width of input pulses from
external (counts internal count source) 00h to FFh RW
Pulse period
measurement mode Measure pulse period of input pulses from
external (counts internal count source)
Ti m er RA Regi st e r
Symbol Address After Reset
TRA 0104h FFh(1)
Mode Function Setting Range RW
NOTE:
1. When the TSTO P bit in the TRACR register i s set to 1, the TRA register i s set to F Fh.
b0
All modes Counts on underflow of ti mer RA prescaler
register RW
b7
00h to FFh
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14.1.1 Timer Mode
In this mode, the timer counts an internally generated count source (refer to Table 14.2 Timer Mode
Specifications).
Figure 14.4 sh ow s TRAIOC Register in Timer Mode.
Figure 14.4 TRAIOC Register in Timer Mode
Tab le 14.2 Timer Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO
Count operations •Decrement
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Divide ratio 1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function Programmable I/O port, or INT1 interrupt input
TRAO pin function Programmable I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer •When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Ti mer RA I/ O Con t ro l Reg i st e r
Symbol Address After Reset
TRAIOC 0101h 00h
Bit Symbol Bi t Name Function RW
INT1
_
____/TRAIO select bit 0 : INT1
_
____/T RAIO pin (P1_7)
1 : INT1
_
____/T RAIO pin (P1_5)
b3 b2
TIOSEL
b1 b0
00
TEDGSEL
b7 b6 b5 b4
00
—
(b7-b6) —
TOPCR RW
TOENA RW
RW
TIPF0 RW
TIPF1
RW
TRAIO polarity switch bit
0
S e t t o 0 in ti mer mode.
TRAIO output control bit
Nothing is assigne d. If nece ssary, set to 0 .
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select bits Set to 0 in timer mode.
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14.1.1.1 Timer Write Control during Count Operation
Timer RA has a pre scaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. When writing to the prescaler or timer, values are written to both the
reload register and counter.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, if the prescaler or timer is written to when count
operation is in progress, the counter value is not updated immediately after the WR ITE instruction is executed.
Figure 14.5 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation.
Figure 14.5 Operating Example of Timer RA when Counter Value is Rewritten during Count
Operation
Count source
Reloads register of
timer RA prescaler
IR bit in TRAIC
register 0
Counter of
timer RA prescaler
Reloads register of
timer RA
Counter of timer RA
Set 01h to the TRAPRE register and 25h to
the TRA register by a program.
After writing, the reload register is
written to at the first count source.
Reload at
second count
source Reload at
underflow
After writing, the reload register is
written to at the f i rst underflow.
Reload at the second underflow
The IR bit remains unchanged until underflow is
generated by a new value.
05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h
New value (01h)Previous value
New value (25h)Previous value
03h 24h02h 25h
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRACR register are set to 1 (During count).
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14.1.2 Pulse Output Mode
In pulse output mode, the internally generated count source is counted, and a pulse with i nverted polarity is
output from the TRAIO pin each time the timer underflows (refer to Table 14.3 Pulse Output Mode
Specifications).
Figure 14.6 shows TRAIOC Register in Pulse Output Mode.
NOTE:
1. The level of the output pulse becomes the level when the pulse output start s when the TRAMR
register is written to.
Ta ble 14 .3 Pulse Output Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO
Count operations • Decrement
• When the timer underflows, the con tents in the reload reg ister is reloaded and
the count is continued.
Divide ratio 1/(n+1)(m+1)
n: Value set in TRAPRE register, m: Value set in TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function Pulse output, programmable output port, or INT1 interrupt(1)
TRAO pin function Programmable I/O port or inverted output of TRAIO(1)
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE a nd TRA are written while the count is stopped, values
are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reloa d register and counter (r efer to 14.1.1.1 Timer W ri te Control
during Count Operation).
Select functions • TRAIO signal polarity switch function
The TEDGSEL bit in th e TR AIO C registe r selects the level at the start of pulse
output.(1)
• TRAO output function
Pulses inverted from the TRAIO output polarity can be output from the TRAO
pin (selectable by the TOENA bit in the TRAIOC register).
• Pulse output stop function
Output from the TRAIO pin is stopp ed by the T OPCR bit in the TRAIOC register.
•INT1
/TRAIO pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
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Figure 14.6 TRAIOC Register in Pulse Output Mode
Ti mer RA I/ O Control Regi ste
r
Symbol Address After Reset
TRAIOC 0101h 00h
Bit Symbol Bi t Name Function RW
INT1
_
____/TRAIO select bit 0 : INT1
_
____/TRAIO pin (P1_7)
1 : INT1
_
____/TRAIO pin (P1_5) RW
RW
0 : TRAIO output
1 : Port P1_7 or P1_5
Nothing is a ssigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select bits Set to 0 in pulse output mode.
TEDGSEL RW
TRAIO pol arity sw itch bit
TIPF1
—
(b7-b6) —
TOPCR RW
TOENA RW
RW
TIPF0
TRAIO output control bit
00
b7 b6 b5 b4 b3 b2
0 : Port P3_7
1 : TRAO output (inverted TRAIO output from P3_7)
TIOSEL
b1 b0
0 : TRAIO output starts at “H”
1 : TRAIO output starts at “L”
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14.1.3 Event Counter Mode
In event counter mode, external signal inputs to the INT1/TRAIO pin are cou nted (refer to Table 14.4 Event
Counter Mode Specifications).
Figure 14.7 show s TRAIOC Register in Event Counter Mode.
NOTE:
1. The level of the output pulse becomes the level when the pulse output start s when the TRAMR
register is written to.
Table 14.4 Event Counter Mode Specifications
Item Specification
Count source External signal which is input to TRAIO pin (active edge selectable by a program)
Count operations • Decrement
• When the timer underflows, the contents of the reload register are reloaded and
the count is continued.
Divide ratio 1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
Count start condition 1 (count starts) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stops) is written to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing •When timer RA underflows [timer RA interrupt].
INT1/TRAIO pin
function Count source input (INT1 interrupt input)
TRAO pin function Programmable I/O port or pulse output(1)
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped, values
are written to both the reload reg ister and counter.
• When reg isters TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer W rite Control
during Count Operation).
Select functions •INT1
input polarity switch function
The TEDGSEL bit in the TRAIOC register selects the active edge of the count
source.
• Count source input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Pulse output function
Pulses of inverted polarity can be output from the TRAO pin each time the timer
underflows (selectable by the TOENA bit in the TRAIOC register).(1)
• Digital filter function
Bits TIPF0 and TIPF1 in the TRA IO C regi ster enable or disable the digital filter
and select the sampling frequency.
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Figure 14.7 TRAIOC Register in Event Counter Mode
Ti me r RA I/ O Con t rol Registe
r
Symbol Address After Reset
TRAIOC 0101h 00h
Bit Symbol Bi t Name Function RW
INT1
_
____/TRAIO select bit 0 : INT1
_
____/TRAIO pin (P1_7)
1 : INT1
_
____/TRAIO pin (P1_5)
NOTE:
1.
—
When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
TRAIO output control bit Set to 0 in event counter mode.
Nothing is a ssigned. If necessary, set to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO i nput fi lter sel ect
bits(1) b5 b4
0 0 : No fi lter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
TIPF1
—
(b7-b6)
RW
TEDGSEL RW
TRAIO pol arity sw itch bit
RW
TIPF0
RW
TOPCR RW
b3 b2b7 b6 b5 b4
0 : Port P3_0
1 : TRAO output
TIOSEL
b1 b0
0 : Starts counting at rising edge of the TRAIO
input or TRAIO starts output at “L”
1 : Starts counting at fall ing edge of the TRAIO
input or TRAIO starts output at “H”
0
TOENA
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14.1.4 Pulse Width Measurement Mode
In pulse width measurement mode, the pulse width of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.5 Pulse Width Measurement Mode Specifications).
Figure 14.8 shows TRAIOC Reg ister in Pulse Width Measurement Mode and Figure 14.9 shows an Operating
Example of Pulse Width Measurement Mode.
Table 14.5 Pulse Width Measurement Mode Specifications
Item Specification
Count sources f1, f2, f8, fOCO
Count operations • Decrement
• Continuou sly counts the selected signal on ly when measurement pulse is “H”
level, or conversely only “L” level.
• When the timer underflows, the contents of the reload register are reloaded
and the count is continued.
Count start condition 1 (coun t starts) is written to the TS TART bit in the TRACR register.
Count stop conditions • 0 (count stops) is writte n to the TSTART bit in the TRACR register.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing • When timer RA underflows [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input (INT1 interrupt input)
TRAO pin function Programmabl e I/O port
Read from timer The count value can be read by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When reg isters TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Select functions • Measurement level select
The TEDGSEL bit in the TRAIOC register selects the “H” or “L” level period.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIO C reg iste r en a ble or disa b le th e dig ital
filter and select the sampling freq uency.
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Figure 14.8 TRAIOC Register in Pulse Width Measurement Mode
Ti mer RA I/ O Control Regi ste
r
Symbol Address After Reset
TRAIOC 0101h 00h
Bit Symbol Bi t Name Function RW
INT1
_
____/TRAIO select bit 0 : INT1
_
____/T RAIO pin (P1_7)
1 : INT1
_
____/T RAIO pin (P1_5)
NOTE:
1. When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
b3 b2
TIOSEL
b1 b0
0 : TRAIO input starts at “L”
1 : TRAIO input starts at “H”
00
b7 b6 b5 b4
—
TOPCR RW
TOENA RW
RW
TIPF0
RW
TRAIO output control bit
TIPF1
TEDGSEL RW
TRAIO pol arity sw i tch bi t
—
(b7-b6) Nothin g is a ssign ed . If necessary, se t to 0.
When read, the content is 0.
TRAO output enable bit
TRAIO input filter select
bits(1) b5 b4
0 0 : No fi lter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
Set to 0 in pulse w i dth measurement mode.
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Figure 14.9 Operating Example of Pulse Width Measurement Mode
FFFFh
n
0000h
Content of counter (hex)
n = high level: the contents of TRA register, low level: the contents of TRAPRE register
Count start
Count stop
Underflow
Period
TSTART bit in
TRACR register 1
0
Measured pulse
(TRAIO pin input) 1
0
TEDGF bit in
TRACR register 1
0
TUNDF bit in
TRACR register 1
0
• “H” level width of measur e d pulse is measu red . (TE DGS E L = 1)
• TRAPRE = FFh
Set to 1 by a program
IR bit in
TRAIC register 1
0
Set to 0 by a program
Count stop
Count start
Set to 0 when interrupt request is acknowledged, or set by a program
Count start
Set to 0 by a program
The above applies under the following conditions.
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14.1.5 Pulse Period Measurement Mode
In pulse period measurement mode, the pulse period of an external signal input to the INT1/TRAIO pin is
measured (refer to Table 14.6 Pulse Period Measurement Mode Specifications).
Figure 14.10 shows TRAIOC Register in Pulse Period Measurement Mode and Figure 14.11 shows an
Operating Example of Pulse Period Measurement Mode.
NOTE:
1. Input a pulse with a period longer than twice the timer RA prescaler period. Input a pulse with a
longer “H” and “ L” width than the timer RA prescaler period . If a pulse with a shorte r period is input to
the TRAIO pin, the input may be ignored.
Table 14.6 Pulse Period Measurement Mode S pecifications
Item Specification
Count sources f1, f2, f8, fOCO
Count operations • Decrement
• After the active edge of the m easured pu lse is input, the content s of the rea d-
out buffer are retained at the first underflow of timer RA prescaler . Then timer
RA reloads the contents in the reload register at the second underflow of
timer RA prescaler and continues counting.
Count start condition 1 (count start) is written to the TSTART bit in the TRACR register.
Count stop conditions • 0 (count stop) is written to TSTART bit in the TRACR re gister.
• 1 (count forcibly stops) is written to the TSTOP bit in the TRACR register.
Interrupt request
generation timing • When timer RA underflows or reloads [timer RA interrupt].
• Rising or falling of the TRAIO input (end of measurement period) [timer RA
interrupt]
INT1/TRAIO pin function Measured pulse input(1) (INT1 interrupt input)
TRAO pin function Programmab le I/O port
Read from timer The count value can be rea d by reading registers TRA and TRAPRE.
Write to timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Select functions • Measurement period select
The TEDGSEL bit in the TRAIOC register selects the measuremen t period of
the input pulse.
• Measured pulse input pin select function
P1_7 or P1_5 is selected by the TIOSEL bit in the TRAIOC register.
• Digital filter function
Bits TIPF0 and TIPF1 in the TRAIOC register enable or disable the digital
filter and select the sampling frequency.
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Figure 14.10 TRAIOC Register in Pulse Period Measurement Mode
Ti mer RA I/ O Control Regi ste
r
Symbol Address After Reset
TRAIOC 0101h 00h
Bit Symbol Bit Name Function RW
INT1
_
____/TRAIO select bit 0 : INT1
_
____/TRAIO pin (P1_7)
1 : INT1
_
____/TRAIO pin (P1_5)
NOTE:
1.
—
(b7-b6) Nothing is assigned. If necessary, set to 0.
W hen read, the content is 0.
TRAO output enable bi t
TRAIO input filter select
bits(1) b5 b4
0 0 : No fil ter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Fil ter w i th f32 sampling
Set to 0 in pulse period measurement mode.
TEDGSEL RW
TRAIO p olarity switch bit
—
TOPCR RW
TOENA RW
RW
TIPF0
RW
TRAIO output control bit
TIPF1
b7 b6 b5 b4
When the same value from the TRAIO pin is sampled three times continuously, the input is determined.
b3 b2
TIOSEL
b1 b0
0 : Measures measurement pul se from one
rising edge to next rising edge
1 : Measures measurement pul se from one
fall ing edge to next falling edge
00
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Figure 14.11 Operating Example of Pulse Period Measurement Mode
Underflow signal of
timer RA prescaler
NOTES:
1. The contents of the read-out buffer can be read by reading t he TRA register in pulse period measurement mode.
2. After an active edge of the measured pulse is input, the TEDGF bit in the TRACR register is set to 1 (active edge found) when the timer
RA prescaler underflows for the secon d t ime.
3. The TRA register should be read before the next active edge is in put after the TEDGF bit is set to 1 (active edge found).
The contents in the read-out buffer are retained until the TRA register is read. If the TRA register is not read before the next ac tive edge
is input, the measured result of the previous period is retained.
4. To set to 0 by a program, use a MOV instruction to write 0 to the TEDGF bit in the TRACR register. At the same time, write 1 to the
TUNDF bit in the TRACR register.
5. To set to 0 by a program, use a MOV instruction to write 0 to the TUNDF bit. At the same time, write 1 to the TEDGF bit.
6. Bits TUNDF and TEDG F are both set to 1 if timer RA underf l ows and reloads on an active edge simultaneously.
0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 0Fh 0Eh 0Dh 01h 00h 0Fh 0Eh0Fh
0Dh
0Fh 0Bh 0Ah 0Dh 01h 00h 0Fh 0Eh09h
TSTART bit in
TRACR register 1
0
1
0
1
0
TEDGF bit in
TRACR register 1
0
Measurement pulse
(TRAIO pin input)
Contents of TRA
1
0
Contents of read-out
buffer(1)
IR bit in TRAIC
register
TUNDF bit in
TRACR register
Set to 1 by a program
Starts co unt i ng
TRA reloads
TRA read(3)
Retained
Set to 0 by a program
Conditions: The period from one ri sing edge to the next rising edge of the measured pulse is measured (TEDGSEL = 0) with
the default value of the TRA register as 0Fh.
0Eh
TRA reloads
Retained
Set to 0 when interrupt request is acknowledged, or set by a program
Set to 0 by a program
Underflow
(Note 2) (Note 2)
(Note 4) (Note 6)
(Note 5)
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14.1.6 Notes on Timer RA
• Timer RA stops co unting after a reset. Set the values in the timer RA and timer RA prescalers before the
count starts.
• Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
• In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain un changed if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instru ction.
• When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
• The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
• When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
• The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTAR T bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with tim er RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (duri ng count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
• When the TRAPRE register is continuously written during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
• When the TRA register is continuously written during count operatio n (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
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14.2 Timer RB
Timer RB is an 8-bit timer with an 8-bit prescaler.
The prescaler and timer each consist of a reload register and counter (refer to Tables 14.7 to 14.10 the
Specifications of Each Mode).
Timer RB has timer RB primary and timer RB secondary as reload registers.
The count source for timer RB is the operating clock that regulates the timing of timer operations such as counting
and reloading.
Figure 14.12 shows a Block Diagram of Timer RB. Figures 14.13 and 14.15 show the registers associated with
timer RB.
Timer RB has four operation modes listed as follows:
•Timer mode: The timer counts an internal count source (peripheral
function clock or timer RA underflows ).
•Programmable waveform generation mode: The timer outputs pulses of a given width successively.
•Programmable one-shot generation mode: The timer outputs a one-shot pulse.
•Programmable wait one-shot generation mode: The timer ou tpu ts a delayed one-shot pulse.
Figure 14.12 Block Diagram of Timer RB
INT0PL bit
= 00b
= 01b
= 11b
f8
f1
= 10b
Timer RA underflow
TCK1 to TCK0 bits
TSTRAT bit
TRBPRE register
(prescaler)
Timer RB interrupt
INT0 interrupt
TCSTF bit
Toggle
flip-flop
Q
QCLR
CK
TOPL = 1
TOPL = 0
TRBO pin
TOCNT = 0
TOCNT = 1 P3_1 bit in P3 register
f2 TMOD1 to TMOD0 bits
= 10b or 11b
TOSSTF bit
Polarity
select
INOSEG bit
Input polarity
selected to be one
edge or both edges
Digital filter
INT0 pin
INT0EN bit
TMOD1 to TMOD0 bits
= 01b, 10b, 11b
TMOD1 to TMOD0 bits
= 01b, 10b, 11b
Counter
Reload
register
Counter (timer RB)
Reload
register
TRBPR
register
Data bus
TRBSC
register Reload
register
TCKCUT bit
INOSTG bit
TSTART, TCSTF: Bits in TRBCR register
TOSSTF: Bi t in TRBOCR register
TOPL, TOCNT, INOSTG, INOSEG: Bits in TRBIOC register
TMOD1 to TMOD0, TCK1 to TCK0, TCKCUT: Bits in TRBMR register
(Timer)
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Figure 14.13 Registers TRBCR and TRBOCR
Ti m er RB Control Regi st e
r
Symbol Address After Reset
TRBCR 0108h 00h
B it Symbol B it Name Functi o n RW
NOTES:
1.
2.
3. Indi cates that count operati on is in progress in timer mode or programmable waveform mode. In programmabl e one-
shot generation mode or programmable wait one-shot generation mode, indicates that a one-shot pul se trigger has
been acknowledged.
Timer RB count start bit(1)
Timer RB count forcible stop
bit(1, 2)
Refer to 14.2.5 Notes on Timer RB for precautions regarding bits TSTART, TCSTF and TSTOP.
TSTART RW
b7 b6 b5 b4 b3 b2
When this bit is set to 1, the count is forcibly
stopped. When read, its content is 0.
b1 b0
0 : Count stops
1 : Count starts
When the TSTOP bit is set to 1, registers TRBPRE, TRBSC, TRBPR, and bits TSTART and TCSTF, and the TOSSTF bit
in the TRBOCR register are set to values after a reset.
0 : Count stops
1 : During count(3)
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
RO
—
(b7-b3) —
TCSTF Timer RB count status flag(1)
TSTOP RW
Ti m er RB One-Shot Cont rol Regist er(2)
Symbol Address After Reset
TRBOCR 0109h 00h
B it Symbol B it Name Functio n RW
NOTES:
1.
2.
b2
0 : One-shot stopped
1 : One-shot operating (Including w ait period)
b1 b0
TOSSP
TOSSTF
TOSST
b7 b6 b5 b4 b3
RW
RW
Timer RB one-shot start bit When this bit is set to 1, one-shot trigger
generated. When read, its content is 0.
Timer RB one-shot stop bit When this bit is set to 1, counting of one-shot
pul ses (including programmable wait one-shot
pulses) stops. When read, i ts content is 0.
Nothi ng is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RB one-shot status
flag(1)
When 1 is set to the TSTOP bit in the TRBCR register, the TOSS TF bit is set to 0.
This register i s enabl ed when bits TMOD1 to TMOD0 i n the TRBMR register is set to 10b (programmable one-shot
generation mode) or 11b (programmable wait one-shot generation mode).
RO
—
(b7-b3) —
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Figure 14.14 R egisters TRBIOC and TRBMR
Ti mer RB I/ O Control Regi ste
r
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bi t Name Function RW
Nothing is a ssigned. If necessary, set to 0.
When read, the content is 0.
One-shot tri g ger polarity
select bit
—
(b7-b4) —
Functi on varies depending on operating mode. RW
RW
RW
RW
One-shot trigger control bit
b3 b2
INOSEG
b1 b0
INOSTG
TOCNT
b7 b6 b5 b4
TOPL Timer RB output l evel select
bit
Timer RB output sw itch bit
Ti me r RB M o de Reg i ste
r
Symbol Address After Reset
TRBMR 010Bh 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
—
Timer RB count source
select bits(1) b5 b4
0 0 : f1
0 1 : f8
1 0 : Timer RA underflow
1 1 : f2
TCK1
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
The TWRC bit can be set to either 0 or 1 in timer mode. In programmable waveform generation mode, programmable
one-shot generation mode, or programmable wait one-shot generation mode, the TWRC bit must be set to 1 (w rite to
reload register only).
TCK0 RW
Change bi ts TMOD1 and TMOD0; TCK1 and TCK0; and TCKCUT w hen both the TSTART and TCSTF bi ts in the TRBCR
register set to 0 (count stops).
RW
Timer RB count source
cutoff bit(1) 0 : Provides count source
1 : Cuts off count source RWTCKCUT
—
(b6)
RW
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RB write control bit(2) 0 : Write to reload register and counter
1 : Write to reload register only
—
b7 b6 b5 b4
RW
TMOD1 RW
Timer RB operating mode
select bits(1) b1 b0
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generati on mode
1 1 : Programmable wait one-shot generation mode
b3 b2
TWRC
b1 b0
—
(b2)
TMOD0
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Figure 14.1 5 Registe rs T RBPRE, TRBSC, and TRBPR
Ti mer RB Prescal er Reg i s ter(1)
Symbol Address After Reset
TRBPRE 010Ch FFh
Mode F unction Setting Range RW
NOTE:
1.
Timer mode
b0b7
RW
00h to FFhCounts an internal count source or timer RA
underflows
00h to FFh RW
When the TSTOP bit in the TRBCR register is set to 1, the TRBPRE register is set to FFh.
Programmable waveform
generati on mode RW
00h to FFh
Programmable one-shot
generati on mode 00h to FFh RW
Programmable wait one-shot
generati on mode
Ti m er RB S econdary Regi st er(3 , 4)
Symbol Address After Reset
TRBSC 010Dh FFh
Mode F unction Setting Range RW
NOTES:
1.
2.
3.
4. To write to the TRBSC register, perform the followi ng steps.
(1) Write the value to the TRBSC register.
(2) Write the value to the TRBPR register. (If the value does not change, w ri te the same val ue second time.)
The count value can be read out by reading the TRBPR register even w hen the secondary period is bei ng counted.
Programmable wait one-shot
generati on mode Counts timer RB prescaler underflows
(one-shot w idth is counted) 00h to F Fh WO(2)
The val ues of registers TRBPR and T RBSC are reloaded to the counter alternately and counted.
When the TSTOP bit in the TRBCR register is set to 1, the TRBSC register is set to FFh.
WO(2)
Counts timer RB prescaler underflows(1) 00h to FF h
Programmable one-shot
generati on mode Disabled 00h to FFh —
Programmable waveform
generati on mode
b7 b0
Timer mode —
Disabled 00h to FF h
Ti m e r RB Pri m a ry Reg i ster (2)
Symbol Address After Reset
TRBPR 010Eh FFh
Mode F unction Setting Range RW
NOTES:
1.
2. When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
Programmable waveform
generati on mode RW
Counts timer RB prescaler underflows(1) 00h to FF h
Programmable one-shot
generati on mode Counts timer RB prescal er underflows
(one-shot w idth is counted) 00h to F Fh RW
The val ues of registers TRBPR and T RBSC are reloaded to the counter alternately and counted.
Timer mode RW
Counts timer RB prescaler underflows 00h to FFh
b7 b0
Programmable wait one-shot
generati on mode Counts timer RB prescal er underflows
(wait period width is counted) 00h to FFh RW
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14.2.1 Timer Mode
In timer mode, a count source which is internally generated or timer RA underflows are counted (refer to Table
14.7 Timer Mode Specifications). Registers TRBOCR and TRBSC are not used in timer mode.
Figure 14.16 shows TRBIOC Register in Timer Mode.
Figure 14.16 TRBIOC Register in Timer Mode
Tab le 14.7 Timer Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement
• When the timer underflows, it reloads the reload register contents before the
count continues (when timer RB u nderflows, the content s of timer RB pr imary
reload register is reloaded).
Divide ratio 1/(n+ 1) (m +1 )
n: setting value in TRBPRE register, m: setting value in TRBPR register
Count start condition 1 (count starts) is written to the TSTART bit in the TRBCR register.
Count stop conditions •0 (count stops) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
Interrupt request
generation timing When timer RB underflows [timer RB interrupt].
TRBO pin function Programmable I/O port
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value ca n be rea d out by readin g re gis te rs T RBPR an d T RBPRE.
Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the r eload register and counter.
• When re gisters TRBPRE and TRBPR are writte n to while count operation is in
progress:
If the TWRC bit in the TRBMR register is set to 0, the value is written to both
the reload register and the counter.
If the TWRC bit is set to 1, the value is written to the reload register only.
(Refer to 14.2.1.1 Timer Write Control during Count Operation.)
Ti mer RB I/ O Control Regi ste
r
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bi t Name Function RW
RW
RW
One-shot trigger control bit
S e t t o 0 in ti mer mode. RW
RW
00
TOPL Timer RB output l evel select
bit
Timer RB output sw itch bit
b7 b6 b5 b4 b3 b2
INOSEG
b1 b0
00
INOSTG
TOCNT
Noth ing is assign ed . If ne cessary, set to 0.
When read, the content is 0.
One-shot tri g ger polarity
select bit
—
(b7-b4) —
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14.2.1.1 Timer Write Control during Count Operation
Timer RB has a prescaler and a timer (which counts the prescaler underflows). The prescaler and timer each
consist of a reload register and a counter. In timer mode, the TWRC bit in the TRBMR register can be used to
select whether writing to the prescaler or timer during count operation is performed to both the reload register
and counter or only to the reload regist er.
However, values are transferred from the reload register to the counter of the prescaler in synchronization with
the count source. In addition, values are transferred from the reload register to the counter of the timer in
synchronization with prescaler underflows. Therefore, even if the TWRC bit is set for writing to both the reload
register and counter, the counter value is not updated immediately after the WRITE instruction is executed. In
addition, if the TWRC bit is set for writing to the reload register only, the synchronization of the writing will be
shifted if the prescaler value changes. Figure 1 4.17 shows an Operating Example of Timer RB when Counter
Value is Rewritten durin g Count Operation.
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Figure 14.17 Operating Example of Timer RB when Counter Value is Rewritten during Count
Operation
Count sour c e
Reloads register of
timer RB prescaler
IR bit in TRBIC
register 0
Counter of
timer RB prescaler
Reloads register of
timer RB
Counter of timer RB
Set 01h to t he T R BP R E r eg ister and 25h to
the TRBPR register by a program.
After writing, the reload register is
written with the first count source.
Reload wi t h
the second
count source
Reload on
underflow
After writing, the reload register is
written on the fi rst underflow.
Reload on the secon d
underflow
The IR bit remains unchanged unt i l und erfl o w
is generated by a ne w val ue .
When the TWRC bit is set to 0 (write to reload register and counter)
Count source
Reloads register of
timer RB prescaler
IR bit in TRBIC
register
Counter of
timer RB prescaler
Reloads register of
timer RB
Counter of timer RB
Set 01h to th e TRBPRE regist er and 25h to
the TRBPR register by a program.
After writi n g, the reload register is
written with the first count source.
Reload on
underflow
After writing, the reload register is
written on the first underf l ow .
Reload on
underflow
Only the prescale r val ue s are up da te d,
extending th e duration unti l timer RB underflow.
When the TWRC bit is set to 1 (write to reload register only)
05h 04h 03h 02h 01h 00h 01h 00h 01h 00h06h 01h 00h 01h
03h 00h02h 01h 25h
New valu e (25h)Previous value
New value (01h)Previous value
New value (01h)Previous value
05h 04h 01h 00h 01h 00h 01h 00h 01h 00h06h
New value (25h)Previous value
03h 24h02h 25h
The above applies under the following conditions.
Both bits TSTART and TCSTF in the TRBCR register are set to 1 (During count).
0
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14.2.2 Programmable Waveform Generation Mode
In programmable waveform generation mode, the signal output from the TRBO pin is inverted each time the
counter underflows, while the values in registers TRBPR and TRBSC are counted alternately (refer to Table
14.8 Programmable Waveform Generation Mode Speci fications). Counting st arts by counting the setting value
in the TRBPR register. The TRBOCR register is unused in this mode.
Figure 14.18 shows TRBIOC Register in Programmable Waveform Generation Mode. Figure 14.19 shows an
Operating Example of Timer RB in Programmable Waveform Generation Mode.
NOTES:
1. Even when counting the secondary period, the TRBPR register may be read.
2. The set values are reflected in th e waveform output beginning with the following primary p eriod after
writing to the TRBPR register.
3. The value written to the TOCNT bit is enabled by the following.
•When counting starts.
•When a timer RB interrupt request is generated.
The contents after the TOCNT bit is changed are reflected from the output of the following
primary period.
Table 14.8 Programmable Waveform Generation Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement
• When the timer underflows, it reloads the contents of the primary reload and
secondary reload registers alternately before the count continues.
Width and period of
output waveform Primary period: (n+1)(m+1)/fi
Secondary period: (n+1)(p+1)/fi
Period: (n+1){(m+1)+(p+1)}/fi
fi: Count source frequency
n: Value set in TRBPRE register
m: Value set in TRBPR register
p: Value set in TRBSC register
Count start condition 1 (count start) is written to the TSTART bit in the TRBCR register.
Count stop conditions •0 (count stop) is written to the TSTART bit in the TRBCR register.
• 1 (count forcibly stop) is written to the TSTOP bit in the TRBCR register.
Interrupt request
generation timing In half a cycle of the count source, after timer RB underflows during the
secondary period (at the same time as the TRBO output change) [timer RB
interrupt]
TRBO pin function Programmable output port or pulse output
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value ca n be rea d out by readin g re gis te rs T RBPR an d T RBPRE(1).
Write to timer • When registers TRBPRE, TRBSC, and TRBPR are written while the count is
stopped, values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only.(2)
Select functions • Output level select function
The T OPL bit in th e TRBIOC registe r select s the outp ut level dur ing primar y and
secondary periods.
• TRBO pin output switch function
Ti m er RB puls e ou tp ut or P3_ 1 lat ch outp u t is selec te d by th e TOCNT bit in the
TRBIOC register.(3)
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Figure 14.18 TRBIOC Register in Programmable Waveform Generation Mode
Ti mer RB I/ O Control Regi ste
r
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bi t Name Function RW
b3 b2
INOSEG
b1 b0
INOSTG
b7 b6 b5 b4
RW
TOCNT RW
00
TOPL
Timer RB output l evel select
bit 0 : Outputs “H” for primary period
Outputs “L” for secondary period
Outputs “L” when the timer is stopped
1 : O utputs “L” for primary peri od
Outputs “H” for secondary period
Outputs “H” w hen the timer is stopped
Timer RB output switch bit 0 : Outputs ti mer RB waveform
1 : O utputs value in P3_1 (P1_3) port register
—
(b7-b4) —
RW
RW
One-shot trigger control bit
Nothing is a ssigned. If nece ssary, set to 0.
When read, the content is 0.
One-shot tri g ger polarity
select bit
Set to 0 in programmabl e waveform generation
mode.
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Figure 14.19 Operating Example of Timer RB in Programmable Waveform Generation Mode
1
0
1
0
IR bit in TRBIC
register 1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBO pin output
TOPL bit in TRBIO
register
Set to 1 by a program
Set to 0 when interrupt
request i s acknowledged,
or set by a program.
The above applies under the following conditions.
TSTART bit in TRBCR
register 1
0
01h 00h 02h
Timer RB secondary reloads Timer RB primary reloads
Set to 0 by a pr ogram
TRBPRE = 01h, TRBPR = 01h, TRBSC = 02h
TRBIOC register TOCNT = 0 (timer RB waveform is output from the TRBO pin)
02h 01h 00h 01h 00h
Primary period Primary periodSecondary period
Waveform
output starts Waveform output inverted Waveform output starts
Initial output is the same level
as during secondary period.
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14.2.3 Programmable One-shot Generation Mode
In programmable o ne-shot generat ion mode, a on e-shot pulse is o utput from the TRBO pin by a p rogram or an
external trigger input (input to the INT0 pin) (refer to Table 14.9 Programmable One-Shot Generation Mode
Specifications). When a trigger is generated, the timer starts operating from the point only once for a given
period equal to the set value in the TRBPR register. The TRBSC register is not used in this mo de.
Figure 14.20 shows TRBIO C Register in Programmabl e One-Shot Generation Mode. Figure 14.21 sho ws an
Operating Example of Programmable One-Shot Generation Mode.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to the TRBPR register.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
Table 14.9 Programmable One-Shot Generation Mode Specifications
Item Specification
Count sources f1, f2, f8, timer RA underflow
Count operations • Decrement the setting value in the TRBPR register
• When the timer underflows, it reloads the contents of the reload register before
the count completes and the TOSSTF bit is set to 0 (one-shot stops).
• When the count stops, the timer reloads the contents of the reload register
before it stops.
One-shot pulse
output time (n+1)(m+1)/fi
fi: Count source frequency,
n: Setting value in TRBPRE register, m: Setting value in TRBPR register(2)
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next
trigger is generated
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts)
• Input trigger to the INT0 pin
Count stop conditions • When reloading completes after timer RB underflows during primary period
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops)
• When the TSTART bit in the TRBCR register is set to 0 (stops counting)
• When the TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting)
Interrupt request
generation timing In half a cycle of the count source , af ter the tim er underflows (at the sam e time as
the TRBO output ends) [timer RB interrupt]
TRBP pin function Pulse output
INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigg e r
disabled): programmable I/O port or INT0 interrupt input
• When the INOSTG bit in the TRBIOC register is set to 1 (INT0 one-shot trigg e r
enabled): external trigger (INT0 interrupt input)
Read from timer The count value can be read out by reading registers TRBPR and TRBPRE.
Write to timer • When registers TRBPRE and TRBPR are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRBPRE and TRBPR are written during the count, values are
written to the reload register only (the data is transferred to the counter at the
following reload)(1).
Select functions •Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot
pulse wavefo rm.
• One-shot trigger select function
Refer to 14.2.3.1 One-Shot Trigger Selection.
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Figure 14.20 TRBIOC Register in Programmable One-Shot Generation Mode
Ti mer RB I/ O Control Regi ste
r
Symbol Address After Reset
TRBIOC 010Ah 00h
Bit Symbol Bi t Name Function RW
0 : INT0
_
____ pin one-shot trigger disabled
1 : INT0
_
____ pin one-shot trigger enabled
NOTE:
1. Refer to 14.2.3.1 One-Shot Trigger Selection.
Nothing is a ssigned. If nece ssary, set to 0.
When read, its content i s 0.
One-Shot Trigger Polarity
Select Bit(1)
—
(b7-b4) —
b3 b2
INOSEG
b1 b0
0
INOSTG
b7 b6 b5 b4
RW
TOCNT RW
TOPL
Timer RB Output Level
Select Bit 0 : O utputs one-shot pulse “H”
Outputs “L” when the timer is stopped
1 : O utputs one-shot pulse “L”
Outputs “H” w hen the timer is stopped
Timer RB Output Switch Bit Set to 0 in programmable one-shot generation
mode.
RW
RW
One-Shot Trigger Control
Bit(1)
0 : Fall ing edge trigger
1 : Rising edge trigger
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Figure 14.21 Operating Example of Pr ogrammable One-Shot Generation Mode
TOSSTF bit in TRBOCR
register
INT0 pin input
1
0
1
0
IR bit in TRBIC
register 1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBIO pin output
TOPL bit in
TRBIOC register
Set to 1 by a program
Set to 1 by a program
Set to 0 when interrupt request is
acknowle dg ed , or set by a pro g ram
The above applies under the following conditions.
TSTART bit in TRBCR
register 1
0
1
0
01h 00h 01h 00h 01h
Count starts Timer RB primary reloads Count starts Timer RB primary reloads
Set to 0 by a progra m
Waveform output starts Waveform output ends Waveform output starts Waveform output ends
Set to 0 when
counting ends Set to 1 by INT0 pin
input trigger
TRBPRE = 01h, TRBPR = 01h
TRBIOC register TOPL = 0, TOCNT = 0
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
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14.2.3.1 One-Shot Trigger Selection
In programmable one-shot generation mode and programmable wait one-shot generation mode, operation starts
when a one-shot trigger is generated while the TCSTF bit in the TRBCR register is set to 1 (count starts).
A one-shot trigger can be generated by either of the following causes:
•1 is written to the TOSST bit in the TRBOCR register by a program.
•Trigger input from the IN T0 pin.
When a one-shot trigger occurs, the TOSSTF bit in the TRBOCR register is set to 1 (one-shot operation in
progress) after one or two cycles of the count source have elapsed. Then, in programmable one-shot gen erati on
mode, count operation begins and one-shot waveform output starts. (In programmable wait one-shot generation
mode, count operation starts for the wait period.) If a one-shot trigger occurs w hile the TOSSTF bit is set to 1,
no retriggering occurs.
To use trigger input from the INT0 pin, input the trigger after making the following set tings:
•Set the PD4_5 bit in the PD4 register to 0 (input port).
•Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register.
•Select both edges or one edge with the INT0PL bit in INTEN register. If one edge is selected, further select
falling or rising edge with the INOSEG bit in TRBIOC register.
•Set the INT0EN bit in the INTEN register to 0 (enabled).
•After completing the above, set the INOSTG bit in the TRBIOC register to 1 (INT pin one-shot trigger
enabled).
Note the following points with regard to generating interrupt requests by trigger input from the INT0 pin.
•Processing to handle the interrupts is required. Refer to 12. Interrupts, for details.
•If one edge is selected, use the POL bit in the INT0IC register to select falling or rising edge. (The
INOSEG bit in the TRBIOC register does not affect INT0 interrupts).
•If a one-shot trigger occurs while the TOSSTF bit is set to 1, timer RB operation is not affected, but the
value of the IR bit in the INT0IC register changes.
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14.2.4 Programmable Wait One-Shot Generation Mode
In programmable wait one-shot generation mode, a one-shot pulse is output from the TRBO pin by a program
or an external trigger input (input to the INT0 pin) (refer to Table 14.10 Programmable Wait One-Shot
Generation Mode Specifications). When a trigge r is generated from that point, t he timer outp uts a pulse on ly
once for a given length of time equal to the setting value in the TRBSC register after waiting for a gi ven leng th
of time equal to the setting value in the TRBPR register.
Figure 14.22 shows TRBIOC Register in Pro grammable Wait One-Shot Ge neration Mode. Fig ure 14 .2 3 shows
an Operating Example of Programmable Wait One-Shot Generation Mode.
NOTES:
1. The set value is reflected at the following one-shot pulse after writing to registers TRBSC and TRBPR.
2. Do not set both the TRBPRE and TRBPR registers to 00h.
Table 14.10 Programmable Wait One-Shot Generation Mode Specifications
Item Specification
Count sources f1 , f2, f8, timer RA underflow
Count operations • Decrement the timer RB primary setting value.
• When a count of the timer RB primary underflows, the timer reloads the contents of
timer RB secondary before the count continues.
• When a count of the timer RB secondary underflows, the timer reloads the contents
of timer RB primary before the count completes and the TOSSTF bit is set to 0
(one-shot stops).
• When the count stops, the timer reloads the contents of the reload register before it
stops.
Wait time (n+1)(m+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, m Value set in the TRBPR register
(2)
One-shot pulse output time (n+1)(p+1)/fi
fi: Count source frequency
n: Value set in the TRBPRE register, p: Value set in the TRBSC register
Count start conditions • The TSTART bit in the TRBCR register is set to 1 (count starts) and the next trigger
is generated.
• Set the TOSST bit in the TRBOCR register to 1 (one-shot starts).
• Input trigger to the INT0 pin
Count stop conditions
• When reloading completes after timer RB underflows during secondary period.
• When the TOSSP bit in the TRBOCR register is set to 1 (one-shot stops).
• When the TSTA RT bit in the TRBCR register is set to 0 (starts counting).
• When t he TSTOP bit in the TRBCR register is set to 1 (forcibly stops counting).
Interrupt req uest generation
timing In half a cycle of the count source after timer RB underflows during secondary period
(complete at the same time as waveform output from the TRBO pin) [timer RB
interrupt].
TRBO pin function Pulse ou tput
INT0 pin functions • When the INOSTG bit in the TRBIOC register is set to 0 (INT0 one-shot trigger
disabled): programmable I/O port or INT0 interrupt input
• When t he INOSTG bit in the TRBIOC register i s set to 1 (INT0 one-shot trigger
enabled): external trigger (INT0 interrupt input)
Read from timer The count value can be read out by reading regi sters TRBPR and TRBPRE.
Write to timer • When registers TRBPRE, TR BSC, and TRBPR are written while the count stops,
values are written to both the reload register and counter.
• When registers TRBPRE, TRBSC, and TRBPR are written to during count
operation, values are written to the reload registers only. (1)
Select functions • Output level select function
The TOPL bit in the TRBIOC register selects the output level of the one-shot pulse
waveform.
• One-shot trigger select functi on
Refer to 14.2.3.1 On e-Sho t Trigger Selection.
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Figure 14.22 TRBIOC Register in Programmable Wait One-Shot Generation Mode
Ti m e r RB I/ O Control Registe
r
Symbol Address After Reset
TRBIOC 010Ah 00h
B it Symbol B it Name Functio n RW
0 : INT0
_
____ pin one-shot trigger disabled
1 : INT0
_
____ pin one-shot trigger enabled
NOTE:
1.
RW
RW
One-shot trigger control bit(1)
0 : Falling edge trigger
1 : Rising edge trigger
RW
TOCNT RW
TOPL
Timer RB output level select
bit 0 : Outputs one-shot pulse “H”.
Outputs “L” when the timer stops or during
wait.
1 : O utputs one-shot pulse “L”.
Outputs “H” w hen the timer stops or during
wait.
Timer RB output sw itch bit Set to 0 in programmable wait one-shot generation
mode.
b7 b6 b5 b4 b3 b2
INOSEG
b1 b0
0
INOSTG
Refer to 14.2.3.1 One-Shot Trigger Selection.
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
One-shot trigger polarity
select bit(1)
—
(b7-b4) —
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Figure 14.23 Operating Example of Pr ogrammable Wait One-Shot Generation Mode
TOSSTF bit in TRBOCR
register
INT0 pin input
1
0
1
0
IR bit in TRBIC
register 1
0
Count source
Timer RB prescaler
underflow signal
Counter of timer RB
TRBIO pin output
TOPL bit in
TRBIOC register
Set to 1 by a program
Set to 1 by setting 1 to TOSST bit in TRBOCR
register, or INT0 pin input trigger.
Set to 0 when interrupt request is
acknowledged, or set by a program.
The above applies under the following conditions.
TSTART bit in TRBCR
register 1
0
1
0
01h 00h 00h 01h
Count starts Timer RB secondary reloads Timer RB primary reload s
Set to 0 by a program
Wait starts Waveform output starts Waveform output ends
Set to 0 when
counting ends
TRBPRE = 01h, TRBPR = 01h, TRBSC = 04h
INOSTG = 1 (INT0 one-shot trigger enabled)
INOSEG = 1 (edge trigger at rising edge)
04h 03h 02h 01h
Wait
(primary period ) One-shot pulse
(secondary period)
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14.2.5 Notes on Timer RB
•Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
•Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the perio d when these two reg isters are being
read.
•In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the
TRBOCR register to 1 (stops one-sh ot), th e timer rel oads the value of reload register and stops. Therefore,
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the
timer count value before the timer stop s.
•The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bi t is set to 0.
During this time, do not access registers associated with timer RB(1) othe r than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
•If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
•If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elap sed. If th e TOSSP bit is written to 1 d uring the peri od
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
14.2.5.1 Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
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14.2.5.2 Programmable waveform generation mode
The following three workarounds should be performe d in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR duri ng count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 14.24 and 14.25.
The following shows the detailed workaround examp les.
•Workaround example (a):
As shown in Figure 14.24, write to registers TRBSC and TRBPR in the timer RB interru pt routine. These
write operations must be completed by the beginni ng of period A.
Figure 14.24 Workaround Example (a) When Timer RB interrupt is Used
TRBO pin output
Count source/
prescaler
underflow si gn al
Primary period
Period A
IR bit in
TRBIC register
Secondary period
(b)
Interrupt
sequence Instruction in
interrupt routine
Interrupt request is
acknowledged
(a)
Interrupt request
is generated
Ensure sufficient time
Set the secondary and then
the primary register immediately
(a) Period between interrupt req uest generation and the completion of execution of an ins truction. T he length of time
varies depend ing on th e ins tru ct io n be ing exe cut ed.
The DIVX instruction requires the longest time, 30 cycles (assuming no wait states and that a register is set as
the divisor).
(b) 20 cycles. 21 cycles for address match and single-step interrupts.
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•Workaround example (b):
As shown in Figure 14.25 detect the start of the primary period by th e TRBO pin output level and w rite to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’ s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicat es the TRBO pin output value.
Figure 14.25 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
14.2.5.3 Programmable one-shot generation mode
The following two workarounds should be performe d in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuousl y during count operatio n (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
•When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
(i)
The TRBO output inversion
is detected at the end of the
secondary period.
Ensure sufficient time
Upon detecting (i), set the secondary and
then th e primary regis ter immediately.
(ii) (iii)
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14.2.5.4 Programmable wait one-shot generation mode
The following three workarounds should be performe d in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or m ore cycles of the count source before writing to the
TOSST bit.
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14.3 Timer RC
14.3.1 Overview
Timer RC is a 16-bit timer with four I/O pins.
Timer RC uses either f1 or fOCO40M as its operation clock. Table 14.11 lists the Timer RC Operation Clock.
Ta ble 14.12 lists the Timer RC I/O Pins, and Figure 14.26 shows a Block Diagram of Timer RC.
Timer RC has three modes.
•Timer mode
- Input capture function The counter value is captured to a register, using an external signal as the trigger.
- Output compare function Matches between the counter and register values are det ected. (Pin output state
changes when a match is detected.)
The following two modes use the output compare function.
•PWM mode Pulses of a given width are output continuously.
•PWM2 mode A one-shot waveform or PWM waveform is output following the trigger after
the wait time has elapsed.
Input capture function, output compare function, and PWM mode settings may be specified independently for
each pin.
In PWM2 mode waveforms are output based on a combination of the counter or the regi ster.
Table 14.11 Timer RC Operation Clock
Condition Timer RC Operation Clock
Count source is f1, f2, f4, f8, f32, or TRCCLK input (bits TCK2 to TCK0 in
TRCCR1 register are set to a value from 000b to 101b) f1
Count source is fOCO40M (bits TCK2 to TCK0 in TRCCR1 register are set
to 110b) fOCO40M
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Figure 14.26 Block Diagram of Timer RC
NOTE:
1. The pins used for TRCIOC and TRCIOD are selectable. Refer to the description of the bits
TRCIOCSEL and TRCIODSEL in the PINSR3 register in Figure 7.9 Registers PINSR2 and
PINSR3 for details.
Table 14.12 Timer RC I/O Pins
Pin Name I/ O Function
TRCIOA(P1_1)
TRCIOB(P1_2)
TRCIOC(P5_3 or P3_4)(1)
TRCIOD(P5_4 or P3_5)(1)
I/O Function dif fers according to the mode. Refer to descriptions
of individual modes for deta ils
TRCCLK(P3_3) Input External clock input
TRCTRG(P1_1 ) Input PWM 2 mo d e ex ter n al trigge r inpu t
TRCMR regi ster
Data bus
TRCCR1 reg ister
TRCIER register
TRCSR register
TRCIOR0 register
TRC register
TRCGRA register
TRCGRB register
TRCGRC register
TRCGRD register
TRCCR2 reg ister
TRCDF regi ster
TRCOER register
Timer RC control circuit
INT0
TRCCLK
Count source
select circuit
f1, f2, f4 , f8, f32,
fOCO40M
Timer RC interrupt
request
TRCIOR1 register TRCIOB
TRCIOC
TRCIOD
TRCIOA/TRCTRG
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14.3.2 Registers Associated with Timer RC
Table 14.13 lists the Registers Associated with Timer RC. Figures 14.27 t o 14.36 show details of th e registers
associated with timer RC.
− : Invalid
Tab le 14 .1 3 Registe rs As soc ia te d with Timer RC
Address Symbol
Mode
Related Info rmatio n
Timer
PWM PWM2
Input
Capture
Function
Output
Compare
Function
0120h TRCMR Valid Valid Valid Valid Timer RC mode register
Figure 14.27 TRCMR Register
0121h TRCCR1 Valid Valid Valid Valid Timer RC control register 1
Figure 14.28 TRCCR1 Register
Figure 14.49 TRCCR1 Register in Output
Compare Function
Figure 14.52 TRCCR1 Register in PWM Mode
Figure 14.56 TRCCR1 Register in PWM2 Mode
0122h TRCIER Val i d Valid Valid Valid Timer RC interrupt enable register
Figure 14.29 TRCIER Register
0123h TRCSR Valid Valid Valid Valid Timer RC status register
Figure 14.30 TRCSR Register
0124h TRCIOR0 Valid Valid −−Timer RC I/O control register 0, timer RC I/O
control regist er 1
Figure 14.36 Registers TRCIOR0 and TRCIOR1
Figure 14.43 TRCIOR0 Register in Input Capture
Function
Figure 14.44 TRCIOR1 Register in Input Capture
Function
Figure 14.47 TRCIOR0 Register in Output
Compare Function
Figure 14.48 TRCIOR1 Register in Output
Compare Function
0125h TRCIOR1
0126h
0127h TRC Valid Valid Valid Valid Timer RC counter
Figure 14.31 TRC Register
0128h
0129h TRCGRA Valid Valid Valid Valid Timer RC general registers A, B, C, and D
Figure 14.32 Registers TRCGRA, TRCGRB,
TRCGRC, and TRCGRD
012Ah
012Bh TRCGRB
012Ch
012Dh TRCGRC
012Eh
012Fh TRCGRD
0130h TRCCR2 −−−Valid Timer RC control register 2
Figure 14.33 TRCCR2 Register
0131h TRCDF Valid −−Valid Timer RC digital filter function select register
Figure 14.34 TRCDF Regist er
0132h TRCOER −Valid Vali d Valid Timer RC output mask enable register
Figure 14.35 TRCOER Register
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Figure 14.27 TRCMR Register
Ti m e r RC Mode Reg i ster (1)
Symbol Address After Reset
TRCMR 0120h 01001000b
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2. These bits are enabled when the PWM2 bit is set to 1 (timer mode or PWM mode).
3. Set the BFC bit to 0 (general register) in PWM2 mode.
0 : Timer mode
1 : PWM mode RW
PWM2 PWM2 mode select bit 0 : PWM 2 mode
1 : Timer mode or PWM mode RW
For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 Mode.
b3 b2
BFD
b1 b0
PWMC
RW
RW
PWMB
0 : General register
1 : Buffer register of TRCG RA register
TRCGRD register function select
bit 0 : General register
1 : Buffer register of TRCG RB regi ster
0 : Timer mode
1 : PWM mode RW
PWMD PWM mode of TRCIOD select bit(2)
b7 b6 b5 b4
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
—
(b6)
BFC
—
RW
TSTART RW
TRC count start bit 0 : Count stops
1 : Count starts
PWM mode of TRCIOB sel ect bit(2) 0 : Timer mode
1 : PWM mode
TRCGRC register function select
bit(3)
PWM mode of TRCIOC select bi t(2)
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Figure 14.28 TRCCR1 Register
Ti m er RC Cont rol Register 1
Symbol Address After Reset
TRCCR1 0121h 00h
B it Symbol Bit Name Function RW
NOTES:
1.
2.
3. The TRC counter performs free-running operation for the i nput capture functi on of the timer mode independent of the
CCLR bit setting.
Count source select bits(1) b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Disable clear (free-running
operation)
1 : Clear by compare match in the
TRCGRA register
Bits CCLR, TOA, T OB, TOC and T OD are disabled for the input capture function of the timer mode.
TCK0
TCK1 RW
TRC coun ter clear selec t bit(2, 3)
TCK2
Set to these bits when the TSTART bit i n the TRCMR register is set to 0 (count stops).
TOC RW
RW
RW
RW
TRCIOD output level select bit(1)
CCLR RW
TRCIOC output level select bit(1)
RW
TOB RW
TRCIO A output level select bit(1)
TRCIOB output level select bit(1)
Function varies according to the
operating mode (function).(2)
b7 b6 b5 b4 b3 b2
TOD
b1 b0
TOA
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Figure 14.2 9 TRCIER Regist er
Ti m er RC Int errupt E nabl e Regi st er
Symbol Address After Reset
TRCIER 0122h 01110000b
B it Symbol Bit Name Function RW
b3 b2
IMIED
b1 b0b7 b6 b5 b4
RW
IMIEB RW
Input capture / compare match
i nterrupt enable bit A 0 : Disable interrupt (IMIA) by the
IMFA bi t
1 : Enable interrupt (IMIA) by the
IMFA bi t
Input capture / compare match
i nterrupt enable bit B 0 : Disable interrupt (IMIB) by the
IMFB bit
1 : Enable interrupt (IMIB) by the
IMFB bit
IMIEA
IMIEC RW
Overflow interrupt enable bit 0 : Disable interrupt (OVI) by the
OVF bit
1 : Enable interrupt (OVI) by the
OVF bit
—
(b6-b4) —
RWOVIE
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
RW
Input capture / compare match
i nterrupt enable bit D 0 : Disable interrupt (IMID) by the
IMFD bit
1 : Enable interrupt (IMID) by the
IMFD bit
Input capture / compare match
i nterrupt enable bit C 0 : Disable interrupt (IMIC) by the
IMFC bit
1 : Enable interrupt (IMIC) by the
IMFC bit
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Figure 14.30 TRCSR Register
Ti m er RC S tatus Register
Symbol Address After Reset
TRCSR 0123h 01110000b
Bit Symbol Bit Name Function RW
NOTE:
1. The writing results are as fol lows:
• This bit is set to 0 when the read result is 1 and 0 is written to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1
even if it is set to 1 from 0 after reading, and writing 0.)
• This bit remains unchanged if 1 is written to it.
b3 b2
IMFD
b1 b0
Input capture / compare match flag
B
IMFA
b7 b6 b5 b4
Input capture / compare match flag
C
IMFC RW
[Source for setti ng this bi t to 0]
W rite 0 after read(1).
[Source for setti ng this bi t to 1]
Refer to the table bel o w.
RW
Input capture / compare match flag
D
RW
IMFB RW
Input capture / compare match flag
A
—
(b6-b4) —
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
RWOVF
Overfl ow flag [S ource for setti ng this bi t to 0]
W rite 0 after read(1).
[Source for setti ng this bi t to 1]
Refer to the table bel o w.
Input capture Function Output Compare Function
TRCIOA pi n input edge(1)
TRCIOB pin i nput edge(1)
TRCIOC pin input edge(1)
TRCIOD pin input edge(1)
NOTES:
1.
2. Edge selected by bits IOj1 to IOj 0 (j = A, B, C, or D).
Incl udes the condition that bits BFC and BFD are set to 1 (buffer registers of regi sters TRCGRA and
TRCGRB).
Bit Symbol
IMFA
IMFB
IMFC
IMFD
OVF
When the values of the registers TRC and TRCGRC match.(2)
When the values of the registers TRC and TRCGRD match.(2)
PWM2 Mode
When the TRC regi ster overflows.
When the values of the registers TRC and TRCGRA match.
When the values of the registers TRC and TRCGRB match.
Timer Mode PWM Mode
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Figure 14.31 TRC Register
Figure 14.32 Registers T RCG RA, TRCGRB, TRCGRC, and TRCGRD
Ti m e r RC Co un ter(1)
Symbol Address After Reset
TRC 0127h-0126h 0000h
Setting Range RW
NOTE:
1.
Function
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRCSR register is set to 1. 0000h to FFFFh RW
Access the T RC register in 16-bit units. Do not access it in 8-bit units.
b0b7
(b8)
b0
(b15)
b7
Ti m e r RC G en era l Re gi st e r A, B , C a nd D (1)
Symbol Address After Reset
TRCGRA
TRCGRB
TRCGRC
TRCGRD
0129h-0128h
012Bh-012Ah
012Dh-012Ch
012Fh-012Eh
FFFFh
FFFFh
FFFFh
FFFFh
RW
NOTE:
1.
(b8)
b0
(b15)
b7 b0b7
RW
Function
Function varies according to the operating mode.
Access registers TRCGRA to TRCGRD in 16-bit units. Do not access them in 8-bit units.
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Figure 14.33 TRCCR2 Register
Ti m er RC Cont rol Register 2
Symbol Address After Reset
TRCCR2 0130h 00011111b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
RW
RW
TRCTRG input edge sel ect bits(3) b7 b6
0 0 : Disable the trigger input from the
T RCTRG pin
0 1 : Rising edge selected
1 0 : Fall ing edge selected
1 1 : Both edges selected
b7 b6 b5 b4 b3 b2
TCEG0
b1 b0
CSEL
In timer mode and PWM mode these bits are disabled.
In timer mode and PWM mode this bit is disabled (the count operation continues independent of the CSEL bit setting).
TCEG1
For notes on PWM2 mode, refer to 14.3.9.5 TRCMR Register in PWM2 Mode.
—
(b4-b0) Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1. —
TRC count operati on sel ect
bit(1, 2) 0 : Count continues at compare match with
the TRCGRA register
1 : Count stops at compare match with
the TRCGRA register
RW
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Figure 14.34 TRCDF Register
Ti m er RC Digi tal F i l t er F un c ti on S e l ect Regi ster
Symbol Address After Reset
TRCDF 0131h 00h
B it Symbol Bit Name Function RW
NOTES:
1.
2. These bi ts are enabl ed for the i nput capture functi on .
These bi ts are enabl ed when in PWM2 mode and bits T CEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or
11b (TRCT RG trigger input enabl ed).
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
Clock select bits for digital filter
function(1, 2)
—
(b5)
DFCK0 RW
—
b7 b6
0 0 : f32
0 1 : f8
1 0 : f1
1 1 : Count source (clock selected by
bits TCK2 to TCK0 in the
TRCCR1 regi ster)
b3 b2
DFD
b1 b0
DFC
b7 b6 b5 b4
RW
DFB RW
DFA T RCIOA pin digital filter function
select bit(1)
TRCIOB pin digi tal fi lter function
select bit(1)
0 : Function is not used
1 : Function is used
RW
RW
TRCIOD pin digital filter functi on
select bit(1)
TRCIOC pin digital filter functi on
select bit(1)
DFCK1 RW
DFTRG TRCTRG pin digi tal fi lter function
select bit(2) RW
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Figure 14.35 TRCOER Register
Ti m er RC Output Ma st er En abl e Regi st er
Symbol Address After Reset
TRCOER 0132h 01111111b
Bit Symbol Bit Name Function RW
INT0
_
____ of pulse output forced 0 : Pulse output forced cutoff i n put disabl ed
cutoff signal input enabled 1 : Pulse output forced cutoff input enabled
bi t (Bi ts EA, EB , EC, and ED are set to 1
(disable output) when “L” is applied to the
INT0
_
____ pin)
NOTE:
1.
—
(b6-b4)
These bi ts are di sabled for input pins set to the input capture functio n.
RW
—
TRCIOD output disable bit(1) 0 : Enable output
1 : Disable output (The TRCIO D pin is
used as a programmable I/O port.)
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
PTO RW
TRCIOC output disable bit(1) 0 : Enable output
1 : Disable output (The TRCIO C pin is
used as a programmable I/O port.)
EC RW
RW
EB RW
TRCIOA output disable bi t(1) 0 : Enable output
1 : Disable output (The TRCIO A pin is
used as a programmable I/O port.)
TRCIOB output disable bit(1) 0 : Enabl e output
1 : Disable output (The TRCIO B pin is
used as a programmable I/O port.)
b7 b6 b5 b4 b3 b2
ED
b1 b0
EA
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Figure 14.3 6 Registers T RCIOR0 and TRCIOR 1
Ti m er RC I/ O Cont rol Regi ster 0(1)
Symbol Address After Reset
TRCIOR0 0124h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4. The IOA3 bit i s enabled when the IOA2 bit is set to 1 (input capture functi on).
TRCGRB control bits Function varies according to the operating mode
(function).
When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 regi ster.
—
IOB0
IOB1 RW
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIO R1 register to the same value as the IO A2 bit in the TRCIOR0 register.
TRCGRB mode select bit(3)
The T RCIOR0 regi ster i s enabl ed in timer mode. It is disabled in modes PWM and PWM2.
—
(b7)
b3 b2
IOA3
b1 b0
IOA2
b7 b6 b5 b4
RW
RW
IOA1
IOA0 TRCG RA control bi ts Function varies according to the operating mode
(function).
IOB2 RW
TRCGRA mode select bit(2) 0 : Output compare function
1 : Input capture function RW
TRCGRA inpu t capture input
switch b it(4) 0 : fO CO 128 si gnal
1 : TRCIOA pin input RW
0 : O utput compare function
1 : Input capture function
RW
Ti m er RC I/ O Cont rol Regi ster 1(1)
Symbol Address After Reset
TRCIOR1 0125h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
The T RCIOR1 regi ster i s enabl ed in timer mode. It is disabled in modes PWM and PWM2.
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
TRCGRC mode select bit(2) 0 : Output compare function
1 : Input capture function RW
—
—
(b7)
IOD2 RW
TRCGRD control bi ts
RW
RW
IOC1
IOC0 TRCG RC control bi ts Function varies accordi ng to the operati ng mode
(function).
b7 b6 b5 b4
IOC2
0 : O utput compare function
1 : Input capture function
b3 b2
—
(b3)
b1 b0
RWFunction varies according to the operating mode
(function).
When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 regi ster.
—
IOD0
IOD1 RW
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIO R1 register to the same value as the IO A2 bit in the TRCIOR0 register.
TRCGRD mode select bit(3)
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14.3.3 Common Items for Multiple Modes
14.3.3.1 Count Source
The method of selecting the count source is common to all modes.
Ta ble 14.14 lists the Coun t Source Selection, and Figure 14.37 shows a Count Source Block Diagram.
Figure 14.37 C ount Source Block Diagram
The pulse width of the external clock input to the TRCCLK pin should be three cycles or more of the timer RC
operation clock (see Table 14.11 Timer RC Operation Clock).
To select fOCO40M as the count source, set the FRA00 bit in the FR A0 register set to 1 (high-speed on-chip
oscillator on), and then set bits TCK2 to TCK0 in the TRCCR1 register to 110b (fOCO40M).
Table 14.14 Count Source Selection
Count Source Selection Method
f1, f2, f4, f8, f32 Count source selected using bits TCK2 to TCK0 in TRCCR1 register
fOCO40M FRA00 bit in FRA0 register set to 1 (high-speed on-chip oscillator on) and bits
TCK2 to TCK0 in TRCCR1 register are set to 110b (fOCO40M)
External signal input
to TRCCLK pin Bits TCK2 to TCK0 in TRCCR1 register are set to 101b (count source is rising edge
of external clock) and PD3_3 bit in PD3 register is set to 0 (input mode)
TCK2 to TCK0
TRC regist e r
TCK2 to TCK0: Bits in TRCCR1 register
f1
f2
f4
f8
f32
= 001b
= 010b
= 011b
= 000b
= 110b
= 100b
Count source
TRCCLK = 101b
fOCO40M
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14.3.3.2 Buffer Operation
Bits BFC and BFD in the TRCM R register are used to select the TRCGRC or TRC GRD register as the buffer
register for the TRCGRA or TRCGRB register.
•Buffer register for TRCGRA register: TRCGRC register
•Buffer register for TRCGRB register: TRCGRD register
Buffer operation differs depending on the mod e .
Table 14.15 list s the Buffer Operation in Each Mode, Figure 14.38 shows the Buffer Operation for Input
Capture Function, and Figure 14 .39 shows the Buffer Operation for Output Compare Function.
Figure 14.38 Buffer Operation for Input Capture Function
Table 14.15 Buffer Operation in Each Mode
Function, Mode Transfer Timing Transfer Destination Register
Input capture function Input capture signal input Contents of TRCGRA (TRCGRB)
register are transferred to buffer register
Output compare function Compare match betwee n TR C
register and TRCGRA (TRCGRB)
register
Content s of buffer registe r are
transferred to TRCGRA (TRCGRB)
register
PWM mode
PWM2 mode • Compar e match between TRC
register and TRCGRA register
• TRCTRG pin trigger input
Contents of buffer register (TRCGRD)
are transferred to TRCGRB register
m
Transfer
n
n-1 n+1
TRCIOA input
TRC register
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 100b (input capture at the rising edge).
m
Transfer
n
TRCGRC
register TRCGRA
register TRC
TRCIOA input
(input capture signal)
TRCGRA reg i ster
TRCGRC register
(buffer)
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Figure 14.39 Buffer Operation for Output Compare Function
Make the following settings in timer mod e .
•To use the TRCGRC register as the buffer register for the TRCGRA register:
Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
•To use the TRCGRD register as the buffer register for the TRCGRB register:
Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is
functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare
match with the TRC register occurs.
The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,
the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin
or TRCIOD pin.
mnTRCGRA register
m-1 m+1
TRC register
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).
n
Transfer
TRCGRC register
(buffer)
m
TRCIOA output
TRCGRC
register TRCGRA
register Comparator TRC
Compare match signal
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14.3.3.3 Digital Filter
The input to TRCTRG or TRCIOj (j = A, B, C, or D) is sampled, and the level is considered to be determined
when three matches occur. The digital filter function and sampling clock are selected using the TRCDF register.
Figure 14.40 shows a Block Diagram of Dig ital Filter.
Figure 14.40 Block Diagram of Digital Filter
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
Match detect
circuit Edge detect
circuit
DFj (or DFTRG)
Sampling clock
IOA2 to IOA0
IOB2 to IOB0
IOC2 to IOC0
IOD2 to IOD0
(or TCEG1 to TCEG0)
DFCK1 to DFCK0
TRCIOj in put signal
(or TRCTRG input
signal)
Clock cycle selected by
TCK2 to TCK0
(or DFCK1 to DFCK0)
Sampling clock
TRCIOj in put signal
(or TRCTRG input signal)
Input sign al after passing
through digital filter
If fewer than three matches occur,
the matches are treated as noise
and no transmission is performed.
Maximum signal transmission
delay is five sampling clock
pulses.
Three matches occur and a
signal change is co nf irmed.
f32
f8
f1
j = A, B, C, or D
TCK0 to TCK2: Bits in TRCCR1 register
DFTRG, DF CK0 t o DFCK1, DFj: Bit s in TRCDF register
IOA0 to IOA2, IOB0 to IOB2: Bits in TRCIOR0 register
IOC0 to IOC2, IOD0 to IOD2: Bits in TRCIOR1 register
TCEG1 to TCEG0 : Bits in TRCCR2 register
C
DQ
Latch
C
DQ
Latch
Timer RC operation clock
f1 or fOCO40M
Count source
= 00b
= 01b
= 10b
= 11b
TCK2 to TCK0
1
0
= 001b
= 010b
= 011b
= 000b
= 100b
= 101b
f1
f32
TRCCLK
f8
f4
f2
fOCO40M = 110b
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14.3.3.4 Forced Cutoff of Pulse Output
When using the timer mode’s output compare function, the PWM mode, or the PWM2 mode, pulse output from
the TRCIOj (j = A, B, C, or D) output pin can be forcibly cut off and the TRCIOj pin set to function as a
programmable I/O port by means of input to the INT0 pin.
A pin used for output by the timer mode’s output compare function, the PWM mode, or the PWM2 mode can be
set to function as the timer RC output pin by setting the Ej bit in the TRCOER register to 0 (timer RC output
enabled). If “L” is input to the INT0 pin while the PTO bit in the TRCOER register is set to 1 (pulse output
forced cutoff signal input INT0 enabled), bits EA, EB, EC, and ED in the TRCOER register are all set to 1
(timer RC output disabled, TRCIOj outp ut pin functions as the programmable I/O port). When one or two
cycles of the timer RC operation clock after “L” input to the INT0 pin (refer to Table 14.11 Timer RC
Operation Clock) has elapsed, the TRCIOj output pin becomes a programmable I/O port.
Make the following settings to use this function.
•Set the pin state following forced cutoff of pulse output (high impedance (input), “L” output, or “H”
output). (Refer to 7. Programmable I/O Ports.)
•Set the INT0EN bit to 1 (INT0 input enabled) and the INT0PL bit to 0 (one edge) in the INTEN register.
•Set the PD4_5 bit in the PD4 register to 0 (input mode).
•Select the INT0 digital filter by means of bi ts INT0F1 to INT0F0 in the INTF register.
•Set the PTO bit in the TRCOER register to 1 (pulse output forced cutoff signal input INT0 enabled).
The IR bit in the INT0IC register is set to 1 (interrupt request) in accordance with the setting of the POL bit and
a change in the INT0 pin input (refer to 12.6 Notes on Interrupts).
For details on interrupts, refer to 12. Interrupts.
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Figure 14.41 Forced Cutoff of Pulse Output
INT0 input TRCIOA
PTO bit
D
S
Q
EA bit
EA bit
write value
TRCIOB
D
S
Q
EB bit
EB bit
write value
TRCIOC
D
S
Q
EC bit
EC bit
write value
TRCIOD
D
S
Q
ED bit
ED bit
write value
EA, EB, EC, ED, PTO: Bits in TRCOER register
Timer RC
output data
Port P1_1
output data
Port P1_1
input data
Timer RC
output data
Port P1_2
output data
Port P1_2
input data
Timer RC
output data
Port P5_3 (P3_4)(1)
output data
Port P5_3 (P3_4)(1)
input data
Timer RC
output data
Port P5_4 (P3_5)(1)
output data
Port P5_4 (P3_5)(1)
input data
NOTE:
1. The pin in par en t h es e s ( ) ca n be as signed by a program .
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14.3.4 Timer Mode (Input Capture Function)
This functi on measur es the wi dt h or peri od of an exter nal signal. An external signal input to the TRCIOj (j = A,
B, C, or D) pin acts as a trigger for transferring the contents of the TRC register (counter) to the TRCGRj
register (input capture). The input capture function, or any other mode or function, can be selected for each
individual pin.
The TRCGRA register can also select fOC O128 signal as input-capture trigger input.
Ta ble 14.16 lists the Specifications of Input Capture Function, Figure 14.42 shows a Block Diagram of Input
Capture Function, Figures 14.43 and 14.4 4 show registers associated with the input capture fu nction, Tab le
14.17 lists the Functions of TRCGRj Regist er when Using Inpu t Capture Functio n, and Figure 14.45 shows an
Operating Example of Input Capture Function.
j = A, B, C, or D
Table 14.16 Specifications of Input Capture Function
Item Specification
Count source f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Count operation Increment
Count period 1/fk × 65,536 fk: Count source frequency
Count start condition 1 (count start s) is written to the TSTART bit in the TRCMR register.
Count stop condition 0 (count stops) is written to the TSTART bit in the TRCMR register.
The TRC register retains a value before count stops.
Interrupt request generation
timing • Input capture (valid edge of TRCIOj input or fOCO128 signal edge)
• The TRC register overflows.
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions Programmable I/O port or input capture input (selectable individually by
pin)
INT0 pin function Programmable I/O port or INT0 interrupt input
Read from timer The count value can be read by reading TRC register.
Write to timer The TRC register can be written to.
Select functions • Input ca pture input pin select
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Input capture input valid edge selected
Rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 14.3. 3. 2 Bu ff er Op era ti on .)
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
• Input-capture trigger selected
fOCO128 can be selected for input-capture trigger input of the
TRCGRA register.
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Figure 14.42 Block Diagram of Input Capture Function
NOTES:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
3. The trigger input of the TRCGRA register can select the TRCIOA pin input or fOCO128 signal.
TRCGRA
register TRC register
Input capture signal(3)
TRCGRC
register
TRCGRB
register
TRCGRD
register
TRCIOB
(Note 1)
(Note 2)
TRCIOC
TRCIOD
Input capture signal
Input capture signal
Input capture signal
Divided
by 128 IOA3 = 0
IOA3 = 1
fOCO fOCO128
TRCIOA
IOA3: Bit in TRCIOR0 register
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Figure 14.43 TRCIOR0 Register in Input Capture Function
Ti m e r RC I/O Control Register 0
Symbol Address After Reset
TRCIOR0 0124h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. The IOA3 bit i s enabled when the IOA2 bit is set to 1 (input capture functi on).
TRCGRA mode select bit(1) Set to 1 (input capture) in the input capture
function. RW
TRCGRA inpu t capture input
switch b it(3) 0 : fO CO128 signal
1 : TRCIOA pin input RW
—
(b7)
IOB2 RW
RW
RW
IOA1
IOA0
TRCGRA control bits b1 b0
0 0 : Input capture to the TRCGRA regi ster
at the rising edge
0 1 : Input capture to the TRCGRA regi ster
at the falling edge
1 0 : Input capture to the TRCGRA regi ster
at both edges
1 1 : Do not set.
b7 b6 b5 b4
1b3 b2
IOA3
b1 b0
1
IOA2
When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
—
IOB0
IOB1 RW
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIO R1 register to the same value as the IO A2 bit in the TRCIOR0 register.
TRCGRB mode select bit(2) S et to 1 (i nput capture) in the input capture
function.
RW
TRCGRB control bits b5 b4
0 0 : Input capture to the TRCGRB register
at the rising edge
0 1 : Input capture to the TRCGRB register
at the falling edge
1 0 : Input capture to the TRCGRB register
at both edges
1 1 : Do not set.
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Figure 14.44 TRCIOR1 Register in Input Capture Function
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Table 14.17 Functions of TRCGRj Register when Using Input Ca pture Function
Register Setting Regi ster Function Input Ca pture
Input Pin
TRCGRA −General register. Can be used to read the TRC registe r value
at input capture. TRCIOA
TRCGRB TRCIOB
TRCGRC BFC = 0 General register. Can be used to read the TRC registe r value
at input capture. TRCIOC
TRCGRD BFD = 0 TRCIOD
TRCGRC BFC = 1 Buffer registers. Can be used to hold transferred value from
the general register. (Refer to 14.3.3.2 Buffer Operation.) TRCIOA
TRCGRD BFD = 1 TRCIOB
Ti me r RC I/O Co ntro l Re gi ste r 1
Symbol Address After Reset
TRCIOR1 0125h 10001000b
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2.
TRCGRC mode select bit(1) Set to 1 (input capture) in the input capture
function. RW
—
RW
RW
IOC1
IOC0
TRCGRC control bits b1 b0
0 0 : Input capture to the TRCGRC register
at the rising edge
0 1 : Input capture to the TRCGRC register
at the falling edge
1 0 : Input capture to the TRCGRC register
at both edges
1 1 : Do not set.
b7 b6 b5 b4
1b3 b2
—
(b3)
b1 b0
1
IOC2
RW
—
(b7)
IOD2 RW
TRCGRD control bits b5 b4
0 0 : Input capture to the TRCGRD register
at the rising edge
0 1 : Input capture to the TRCGRD register
at the falling edge
1 0 : Input capture to the TRCGRD register
at both edges
1 1 : Do not set.
When the BFD bit in the TRCMR register is set to 1 (buffer regi ster of TRCGRB register), set the IOD2 bi t in the
TRCIO R1 register to the same value as the IOB2 bit in the TRCIOR0 register.
Nothing is assigne d. If nece ssary, set to 0.
When read, the content is 1.
—
IOD0
IOD1 RW
Nothing is assigne d. If nece ssary, set to 0.
When read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
TRCGRD mode select bit(2) Set to 1 (input capture) in the input capture
function.
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Figure 14.45 Operating Example of Input Capture Function
TRC register
count valu e
FFFFh
0006h
TSTART bi t in
TRCMR register
65536
TRCGRA register
0000h
1
0
TRCIOA input
TRCGRC register
IMFA bit in
TRCSR register
OVF bit in
TRCSR register
Set to 0 by a program
Transfer
0003h0006h
0006h
Transfer
1
0
1
0
TRCCLK input
count source
The above applie s under the following conditions:
• Bits TCK2 to TCK0 in the TRCCR1 register are set to 101b (the count source is TRCCLK input).
• Bits IOA2 to IOA0 in the TRCIORA regist er ar e se t t o 101b (inp ut capture at t h e f a lling edge of the TRC I OA in p ut ) .
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
0003h
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14.3.5 Timer Mode (Output Compare Function)
This function detects when the contents of the TRC regist er (counter) and t he TRCGRj register (j = A, B, C, or
D) match (compare match). When a match occurs a signal is output from the TRCIOj pin at a given level. The
output compare function, or other mode or function, can be selected for each individual pin.
Table 14.18 lists the Specifications of Output Compare Function, Figure 14.46 shows a Block Diagram of
Output Compare Fu nction, Figures 14.4 7 to 14.49 sho w registers associated with the outp ut compare function ,
Ta ble 14.19 lists the Func tions of TR CGRj Regi ster when U sing Output Compare Fu nction, an d Figure 14.5 0
shows an Operating Example of Output Compare Function.
j = A, B, C, or D
Table 14.18 Specifications of Output Compare Function
Item Specification
Count source f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Count operation Increment
Count period • The CCLR bit in the TRCCR1 register is set to 0 (free running
operation): 1/fk × 65,536
fk: Count source frequency
• The CCLR bit in the TRCCR1 register is set to 1 (TRC register set to
0000h at TRCGRA compare match):
1/fk × (n + 1)
n: TRCGRA register setting value
Waveform output timing Compare match
Count start condition 1 (count start s) is written to the TSTART bit in the TRCMR register.
Count stop condition 0 (count stops) is written to the TSTART bit in the TRCMR register.
The output compare output pin retains output level before count stops,
the TRC register retains a value before count stops.
Interrupt request generation
timing • Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
TRCIOA, TRCIOB, TRCIOC,
and TRCIOD pin functions Programmable I/O port or output compare output (selectable in dividually
by pin)
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Read from timer The count value can be read by reading the TRC register.
Write to timer The TRC register can be written to.
Select functions • Output compare output pin selected
One or more of pins TRCIOA, TRCIOB, TRCIOC, and TRCIOD
• Compare match output level select
“L” output, “H” output, or output level inverted
• Initial output level select
Sets output level for period from count start to compare match
• Timing for clearing the TRC register to 0000h
Overflow or compare match with the TRCGRA register
• Buffer operation (Refer to 14.3. 3. 2 Bu ff er Op era ti on .)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff
of Pulse Output.)
• Can be u sed as an internal timer by disabling timer RC output
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Figure 14.46 Block Diagram of Output Compare Function
TRCIOA Output
control Comparator TRCGRA
TRC
TRCIOC TRCGRC
TRCIOB TRCGRB
TRCIOD TRCGRD
Output
control
Output
control
Output
control
Compare match signal
Compare match signal
Compare match signal
Compare match signal
Comparator
Comparator
Comparator
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Figure 14.4 7 TRCIOR0 Regi st er in Out put Compare Function
Ti m e r RC I/O Control Regi st er 0
Symbol Address After Reset
TRCIOR0 0124h 10001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2. When the BFD bit in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit in the
TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
—
IOB0
IOB1 RW
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIO R1 register to the same value as the IO A2 bit in the TRCIOR0 register.
TRCGRB mode select bit(2) S et to 0 (output compare) in the output compare
function.
RW
—
(b7)
IOB2 RW
TRCGRB control bits b5 b4
0 0 : Disable pin output by compare
match (TRCIOB pin functions as the
programmable I/O port)
0 1 : “L” output by compare match in
the TRCGRB register
1 0 : “H” output by compare match in
the TRCGRB register
1 1 : Toggle output by compare match
in the TRCGRB register
b3 b2
IOA3
b1 b0
10
IOA2
0
b7 b6 b5 b4
RW
RW
IOA1
IOA0
TRCGRA control bits b1 b0
0 0 : Disable pin output by compare
match (TRCIOA pin functions as the
programmable I/O port)
0 1 : “L” output by compare match in
the TRCGRA regi ster
1 0 : “H” output by compare match in
the TRCGRA regi ster
1 1 : Toggle output by compare match
in the TRCGRA regi ster
TRCGRA mode select bit(1) Set to 0 (output compare) in the output compare
function. RW
TRCGRA inpu t capture input
switch b it Set to 1 . RW
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Figure 14.4 8 TRCIOR1 Regi st er in Out put Compare Function
Ti me r RC I/O Co ntro l Re gi ste r 1
Symbol Address After Reset
TRCIOR1 0125h 10001000b
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2. When the B FD bi t in the TRCMR register is set to 1 (buffer register of TRCGRB register), set the IOD2 bit i n the
TRCIO R1 register to the same value as the IOB2 bit in the TRCIOR0 register.
—
IOD0
IOD1 RW
Nothing is assigne d. If nece ssary, set to 0.
When read, the content is 1.
When the BFC bit in the TRCMR register is set to 1 (buffer register of TRCGRA register), set the IOC2 bit in the
TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
TRCGRD mode select bit(2) Set to 0 (output compare) in the output compare
function.
RW
—
(b7)
IOD2 RW
TRCGRD control bits b5 b4
0 0 : Disabl e pin output by compare
match
0 1 : “L” output by compare match in
the TRCGRD register
1 0 : “H” output by compare match in
the TRCGRD register
1 1 : Toggle output by compare match
in the TRCGRD register
b3 b2
—
(b3)
b1 b0
0
IOC2
0
b7 b6 b5 b4
RW
RW
IOC1
IOC0
TRCGRC control bits b1 b0
0 0 : Disabl e pin output by compare
match
0 1 : “L” output by compare match in
the TRCGRC register
1 0 : “H” output by compare match in
the TRCGRC register
1 1 : Toggle output by compare match
in the TRCGRC register
TRCGRC mode select bit(1) Set to 0 (output compare) in the output compare
function. RW
—
Nothing is assigne d. If nece ssary, set to 0.
When read, the content is 1.
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Figure 14.49 TRCCR1 Register in Output Compare Function
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
Table 14.19 Functions of TRCGRj Register when Using Outpu t Compare Function
Register Setting Register Function Output Compare
Output Pin
TRCGRA −General register. Write a compare value to one of these
registers. TRCIOA
TRCGRB TRCIOB
TRCGRC BFC = 0 General register. Write a compare value to one of these
registers. TRCIOC
TRCGRD BFD = 0 TRCIOD
TRCGRC BFC = 1 Buffer register. Write the next compare value to one of
these registers. (Refer to 14.3.3.2 Buffer Operation.) TRCIOA
TRCGRD BFD = 1 TRCIOB
Ti m e r RC Control Regi st er 1
Symbol Address After Reset
TRCCR1 0121h 00h
B it Symbol Bit Name Function RW
NOTES:
1.
2. If the pin function is set for w aveform output (refer to Tables 7.13 to 7.16, Tables 7.26 to 7.29, and Tables 7.36 to
7.39), the initi al output level is output when the TRCCR1 register is set.
b3 b2
TOD
b1 b0b7 b6 b5 b4
TRCIOC output level select bit(1, 2)
b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Disable clear (free-running
operation)
1 : Clear by compare match in the
TRCGRA register
TCK0
TCK1
RW
TOB RW
TRCIO A output level select bit(1, 2)
TRCIOB output level select bit(1, 2)
TOA
Set to these bits when the TSTART bit i n the TRCMR register is set to 0 (count stops).
TOC RW
RW
RW
RW
TRCIOD output level select bit(1, 2)
CCLR
0 : Initial output “L”
1 : Initial output “H”
Count source select bits(1)
RW
TRC coun ter clear select bit
TCK2
RW
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Figure 14.50 Operating Example of Output Compare Function
Output level held
m
n
p
TRC register value
Count source
m+1 m+1
TSTART bit in
TRCMR register 1
0
TRCIOA output
IMFA bit in
TRCSR register 1
0
n+1
TRCIOB output “H” output at
compare match
Set to 0 by a program
IMFB bit in
TRCSR register 1
0
Initial outp ut “L”
Initial outp ut “L”
TRCIOC output
Set to 0 by a prog ram
IMFC bit in
TRCSR register 1
0
Initial output “H”
“L” output at com pa re match
P+1
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
The above applies under the following conditions:
Count
restarts
Count
stops
Output level held
Set to 0 by a program
• Bits BFC and BFD in the TRCMR regist er are set to 0 (TRCGRC and TRCGRD do not operate as buffers).
• Bits EA, EB, and EC in the TRCOER register are set to 0 (output from TRCIOA, TRCIOB, and TRCIOC enabled).
• The CCLR bit in the TRCCR1 register is set to 1 (set the TRC register to 0000h by TRCGRA compare match).
• In the TRCCR1 register, bits TOA a nd TOB are set to 0 (“L” initial output un til compare match) and the TOC bit is set t o 1 (“H” initial output until
compare match).
• Bits IOA2 to IO A0 in the TRCIOR0 register are set to 011b (T RCIO A out p ut in ve rte d at TRCG RA co m pare ma t ch).
• Bits IOB2 to IOB0 in the TRCIOR0 register are set to 010b (“H” TRCIOB output at TRCGRB compare match).
• Bits IOC2 to IOC2 in the TRCIOR1 register are set to 001b (“L” TRCIOC o utput at TRCGRC compare match).
Output level held
Output inverted at
compare match
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14.3.6 PWM Mode
This mode outputs PWM waveforms. A maximum of three PWM waveforms with the same period are output.
The PWM mode, or the timer mode, can be selected for each individual pin. (However, since the TRCGRA
register is used when using any pin for the PWM mode, the TRCGRA register cannot be used for the timer
mode.)
Ta ble 14.20 lists the Specifications of PWM Mode, Figure 14.51 shows a Block Diagram of PWM Mode,
Figure 14.52 shows the registers associated with the PWM mode, Ta ble 14.21 lists the Functions of TRCGRj
Register in PWM Mode, and Figures 14.53 and 14.54 show Operating Examples of PWM Mode.
j = B, C, or D
Table 14.20 Specifications of PWM Mode
Item Specification
Count source f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) input to
TRCCLK pin
Count operation Increment
PWM waveform PWM period: 1/fk × (m + 1)
Active level width: 1/fk × (m - n)
Inactive width: 1/fk × (n + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRj register setting value
Count start condition 1 (count starts) is written to the TSTART bit in the TRCMR register.
Count stop condition 0 (count stops) is written to the TSTART bit in the TRCMR register.
PWM output pin retains output level before count stops, TRC register
retains value before count stops.
Interrupt request generation
timing • Compare match (contents of registers TRC and TRCGRj match)
• The TRC register overflows.
TRCIOA pin function Programmable I/O port
TRCIOB, TRCIOC, and
TRCIOD pin functions Programmable I/O port or PWM output (selectable individually by pin)
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0
interrupt input
Read from timer The count value can be rea d by rea ding the TRC register.
Write to timer The TRC register can be written to.
Select functions • One to three pins selectable as PWM output pins per channel
One or more of pins TRCIOB, TRCIOC, and TRCIOD
• Active level selectable by individual pin
• Buffer operation (Refer to 14.3.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced
Cutoff of Pulse Output.)
m+1
n+1 m-n (“L” is active level)
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Figure 14.51 Block Diagram of PWM Mode
TRCIOB
Output
control
Comparator TRCGRA
TRC
Compare match signal
TRCGRB
TRCIOC
TRCGRC
TRCGRD
TRCIOD
NOTES:
1. The BFC bit in the TRCMR register is set to 1 (TRCGRC register functions as the buffer register for the TRCGRA register)
2. The BFD bit in the TRCMR register is set to 1 (TRCGRD register functions as the buffer register for the TRCGRB register)
(Note 1)
(Note 2)
Compare match signal
Compare match signal
Compare match signal
Comparator
Comparator
Comparator
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Figure 14.52 TRCCR1 Register in PWM Mode
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
NOTE:
1. The output level does not change even when a compare match occurs if the TRCGRA register value (PWM
period) is the same as the TRCGRB, TRCGRC, or TRCGRD register value.
Table 14.21 Functions of TRCGRj Register in PWM Mode
Register Setting Register Function PWM Output Pin
TRCGRA −General register. Set the PWM period. −
TRCGRB −General register . Set the PWM output change point. TRCIOB
TRCGRC BFC = 0 General register. Set the PWM output change point. TRCIOC
TRCGRD BFD = 0 TRCIOD
TRCGRC BFC = 1 Buffer register. Set the next PWM period. (Refer to 14.3.3.2
Buffer Operation.) −
TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to
14.3.3.2 Buffer Operation.) TRCIOB
Ti m e r RC Control Regi st er 1
Symbol Address After Reset
TRCCR1 0121h 00h
Bit Symbol Bit Name F uncti on RW
j
= B, C or
D
NOTES:
1.
2.
RW
TRC coun ter clear selec t bit
TCK2
Count source select bits(1) b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Disable clear (free-running operation)
1 : Clear by compare match i n the
TRCGRA register
TCK0
TCK1
Set to these bits when the TSTART bit i n the TRCMR register is set to 0 (count stops).
TOC RW
RW
RW
RW
TRCIOD output level select bit(1, 2)
CCLR
0 : Active le vel “H”
(Initial output “L”
“H” output by compare match in
the TRCGRj register
“L” output by compare match i n
the TRCGRA register
1 : Active le vel “L”
(Initial output “H”
“L” output by compare match i n
the TRCGRj register
“H” output by compare match in
the TRCGRA register
RW
RW
TOB RW
TRCIOA o utp ut leve l select bit (1)
TRCIOB output level select bit(1, 2)
TRCIOC output level select bit(1, 2)
Di sabled in PWM mode
TOA
b7 b6 b5 b4
If the pin function is set for waveform output (refer to T able 7.15, Table 7.16, Tables 7.26 to 7.29, and Tables 7.36 to
7.39), the initi al output level is output when the TRCCR1 regi ster i s set.
b3 b2
TOD
b1 b0
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Figure 14.53 Operating Example of PWM Mode
m
n
p
TRC register value
Count source
m+1
n+1
TRCIOC output
q
m-n
p+1 m-p
m-qq+1
TRCIOD out put
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
q: TRCGRD register setting value
Inactive level is “L”Active level is “H”
Active level is “L”
“L” initial output until
compare match
“H” initial output until
compare match
Set to 0 by a progr am
Set to 0 by a program Set to 0 by a program
TRCIOB output
IMFA bit in
TRCSR register 1
0
IMFB bit in
TRCSR register 1
0
IMFC bit in
TRCSR register 1
0
IMFD bit in
TRCSR register 1
0
The above applies under the following conditions:
• Bits BFC and BFD in the TRCMR register are set to 0 (registers TRCGRC and TRCGRD do not operate as buffers).
• Bits EB, EC, and ED in the TRCOER register are set to 0 (output from TRCIOB, TRCIOC, and TRCIOD enabled).
• In the TRCCR1 register, bits TOB and TOC are set to 0 (active level is “H”) and the TOD bit is set to 1 (active level is “L”).
Set to 0 by a program
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Figure 14.54 Operating Example of PWM Mode (Dut y 0% and Duty 100%)
Rewritten by
a program
m
p
q
TRC register value
n
m: TRCG RA register setting value
Set to 0 by a program
Rewritten by a program
0000h
q
Duty 0%
TRCGRB register
IMFA bit in
TRCSR register
1
0
IMFB bit in
TRCSR register 1
0
TSTART bit in
TRCMR register
TRCIOB output
p (p>m)n
1
0
m
p
TRC register value
n
0000h
TRCGRB register
IMFA bit in
TRCSR register
1
0
IMFB bit in
TRCSR register 1
0
TSTART bit in
TRCMR register
TRCIOB output
pn
1
0
m
The above applies un der the following conditions:
• The EB bit in the T RCOER register is set to 0 (output from TRCIOB enabled).
• The TOB bit in the TRCCR1 register is set to 1 (active level is “L”).
TRCIOB output does not switch to “L” because
no compare m atch with the T RCGRB register
has occurred
If compare matches occur simultaneously with registers TRCGRA and
TRCGRB, the compare match with the TRCGRB register has priority.
TRCIOB output switches to “L”. (In other words, no change).
TRCIOB out put swi tc hes to “L” at compare mat ch wit h t he
TRCGRB register. (In other words, no change).
Set to 0 by a program
Set to 0 by a program
Duty 100%
Set to 0 by a program
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14.3.7 PWM2 Mode
This mode outputs a sin gle PWM waveform. After a given wait duration has elapsed followi ng the trigger, the
pin output switches to active level. Then, after a given duration, the output switches back to inactive level.
Furthermore, the counter stops at the same time the output returns to inactive level, maki ng it possible to use
PWM2 mode to output a programmable wait one-shot waveform.
Since timer RC uses multiple general registers in PWM2 mode, other modes cannot be used in conjunction with
it.
Figure 14.55 shows a Block Diagram of PWM2 Mode, Table 14.22 lists the Specifications of PWM2 Mode,
Figure 14.56 shows the register associated with PWM2 mode, Table 14.23 lists the Functio ns of TRCGRj
Register in PWM2 Mode, and Figures 14.57 to 14.59 show Operating Examples of PWM2 Mode.
Figure 14.55 B lock Diagram of PWM2 Mode
TRCTRG Input
control
TRCIOB Output
control
Comparator TRCGRATRC
TRCGRD
register
Compare match signal
Comparator TRCGRB
Comparator TRCGRC
NOTE:
1. The BFD bit in the TRCMR register is set to 1 (the TRCGRD register functions as the buffer register for the TRCGRB regi ster).
Count clear signal
Trigger signal
(Note 1)
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j = A, B, C, or D
Table 14.22 Specifications of PWM2 Mode
Item Specification
Count source f1, f2, f4, f8, f32, fOCO40M, or external signal (rising edge) inpu t to TRCCLK pin
Count operation Increment TRC register
PWM waveform PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
Count start conditions • Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
1 (count starts) is written to the TSTART bit in the TRCMR register.
• B its TCEG1 to TCEG0 in t he TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG
trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts).
A trigger is input to the TRCTRG pin
Count stop conditions • 0 (count stops) is written to the TST AR T bit in the TRCMR register while the CSEL bit in
the TRCCR2 register is set to 0 or 1.
The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in
the TRCCR1 register. The TRC register retains the value before count stops.
• The count stops due to a compare match with TRCGRA whi l e the CSEL bit in the
TRCCR2 register is set to 1
The TRCIOB pin outputs the initial level. The TRC register retains the value before
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set
to 0000h if the CCLR bit in the TRCCR1 register is set to 1.
Interrupt request
generation timing • Compare match (contents of TRC and TRCGRj registers match)
• Th e TRC register overflows
TRCIOA/TRCTRG pin
function Programmable I/O port or TRCTRG input
TRCIOB pin function PWM output
TRCIOC and TRCIOD pin
functions Programmable I/O port
INT0 pin function Programmable I/O port, pulse output forced cutoff signal input, or INT0 interru pt input
Read from timer The count value can be read by reading the TRC register.
Write to timer The TRC register can be written to.
Select functions • External trigger and valid edge sele cted
The edge or edges of the signal input to the TRCTRG pin can be used as th e PWM
output trigger: rising edge, falling edge, or both rising and falling edges
• Buffer operation (Refer to 14.3.3.2 Buffe r Operation .)
• Pulse output forced cutoff signal input (Refer to 14.3.3.4 Forced Cutoff of Pulse
Output.)
• Digital filter (Refer to 14.3.3.3 Digital Filter.)
m+1
TRCTRG input
TRCIOB output
(TRCTRG: Rising edge, active level is “H”)
n-p
n+1
p+1 p+1
n+1
n-p
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Figure 14.56 TRCCR1 Register in PWM2 Mode
j = A, B, C, or D
BFC, BFD: Bits in TRCMR register
NOTE:
1. Do not set the TRCGRB and TRCGR C registers to the same value.
Table 14.23 Functions of TRCGRj Register in PWM2 Mode
Register Setti ng Register Fun ction PWM2 Output Pin
TRCGRA −General register. Set the PWM period. TRCIOB pin
TRCGRB −General register . Set the PWM output change point.
TRCGRC BFC = 0 General register. Set the PWM output change point (wait time
after trigger).
TRCGRD BFD = 0 (Not used in PWM2 mode) −
TRCGRD BFD = 1 Buffer register. Set the next PWM output change point. (Refer to
14.3.3.2 Buffer Operation.) TRCIOB pin
Ti m e r RC Control Regi st er 1
Symbol Address After Reset
TRCCR1 0121h 00h
Bit Symbol Bit Name F uncti on RW
NOTES:
1.
2. If the pin function i s set for waveform output (refer to Table 7.15 and Table 7.16), the ini tial output l evel i s output
when the TRCCR1 register is set.
TRC coun ter clear selec t bit
TCK2
Set to these bits when the TSTART bit i n the TRCMR register is set to 0 (count stops).
CCLR
Count source select bits(1) b6 b5 b4
0 0 0 : f1
0 0 1 : f2
0 1 0 : f4
0 1 1 : f8
1 0 0 : f32
1 0 1 : TRCCLK input rising edge
1 1 0 : fOCO40M
1 1 1 : Do not set.
0 : Disable clear (free-running operation)
1 : Clear by compare match i n the
TRCGRA register
TCK0
TCK1
TOC RW
RW
RW
RW
TRCIOD output level select bit(1)
RW
0 : Active le vel “H”
(Initial output “L”
“H” output by compare match i n the
TRCGRC register
“L” output by compare match in the
TRCGRB register)
1 : Active le vel “L”
(Initial output “H”
“L” output by compare match in the
TRCGRC register
“H” output by compare match i n the
TRCGRB register)
RW
RW
TOB RW
TRCIOA o utp ut leve l select bit (1)
TRCIOB output level select bit(1, 2)
TRCIOC output level select bit(1)
Di sabled i n the PWM2 mode
Di sabled i n the PWM2 mode
b7 b6 b5 b4 b3 b2
TOD
b1 b0
TOA
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Figure 14.57 Operating Example of PWM2 Mode (TRCTRG Trigger Input Disabled)
Set to 0 by a program Set to 0 by a program
TRC register value
Count source
m+1
n+1
0000h
FFFFh
p+1
TRCIOB output
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
m
n
p
TSTART bit in
TRCMR register 1
0
Count stops
because t h e
CSEL bit is
set to 1
“L” initia l output
“H” output at TRCGRC
register compare match “L” output at TRCGRB
register compare match
IMFA bit in
TRCSR register 1
0
Set to 0 by a program
IMFB bit in
TRCSR register
CSEL bit in
TRCCR2 register 1
0
Set to 1 by
a program
1
0
IMFC bit in
TRCSR register 1
0
Transfer
TRCGRB register
TRCGRD register nNext data
Transfer
n
Transfer from buffer register to general register
The above appl ie s und er th e fol lo w ing co nd it i ons :
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” out pu t at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 0 0b (TRCTRG trigger input disabled).
Set to 0000h
by a program
Previous value held if the
TSTRAT bit is set to 0
TSTART bit
is set to 0
TRC register cleared
at TRCGRA register
compare match
p+1
“H” output at TRCGRC register
compar e ma t c h
No change
No change
Return to initial output
if the TSTART bit is
set to 0
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Figure 14.58 Operating Example of PWM2 Mode (TRCTRG Trigger Input Enabled)
Set to 0 by
a program
TRC register value
Count source
m+1
n+1
0000h
FFFFh
p+1
TRCIOB output
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
m
n
p
TSTART bit in
TRCMR register 1
0
Count stops
because th e
CSEL bit is
set to 1
“L” initia l output
“H” output at
TRCGRC register
compare match
IMFA bit in
TRCSR register 1
0
Set to 0 by
a program
IMFB bit in
TRCSR register
CSEL bit in
TRCCR2 register 1
0
1
0
IMFC bit in
TRCSR register 1
0
Transfer
TRCGRB register
TRCGRD register Next data
Transfer
n
Transfer from buffer register to general register
The above appl ies under t h e fol l ow ing co nd iti on s:
• The TOB bit in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match wi th the TRCGRC register, “L” output at compare match with the
TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 11b (trigger at both rising and falling edges of TRCTRG input).
Set to 0000h
by a program
Previous value
held if the
TSTART bit is
set to 0
The TSTART
bit is set to 0
TRC register cl eared
at TRCGRA register
compar e ma t c h
Return to initial value if the
TSTART bit is set to 0
TRC register (counter)
cleared at TRCTRG pin
trigger input
TRCTRG input Count starts
TSTART bit
is set to 1
n+1
p+1 p+1
“L” output at
TRCGRB register
compare match
Inactive level so
TRCTRG input is
enabled
Active level so TRCTRG
input is disabled
Set to 0 by
a program Set to 0 by
a program
n
Transfer
n
n
Transfer
Transfer from buffer register to general register
n
Set to 1 by
a program
Changed by a program
Count start s at
TRCTRG pin
trigger input
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Figure 14.59 Operating Example of PWM2 Mode (Duty 0% and Duty 100%)
• TRCGRC register setting value greater than TRCGRA
register setting value
m
n
TRC register value
p
Set to 0 by a
program
0000h
IMFB bit in
TRCSR regist er
1
0
IMFC bit in
TRCSR regist er 1
0
TSTART bit in
TRCMR regi ster
TRCIOB outp ut
1
0
The above applies under the following conditions:
• The TOB bi t in the TRCCR1 register is set to 0 (initial level is “L”, “H” output at compare match with the TRCGRC register, “L” output at compare
match with the TRCGRB register).
• Bits TCEG1 and TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger input disab led).
p+1
IMFA bit in
TRCSR regist er 1
0
“L” initial
output
No compare match with
TRCGRB register, so
“H” output continues
“H” output at TRCGRC register
compar e ma t c h
m+1
• TRCGRB register setting value greater than TRCGRA
register setting value
m
p
TRC register value
n
0000h
IMFB bit in
TRCSR regist er
1
0
IMFC bit in
TRCSR regist er 1
0
TSTART bit in
TRCMR regi ster
TRCIOB outp ut
1
0
n+1
IMFA bit in
TRCSR regist er 1
0
“L” initial
output
“L” output at
TRCGRB register
compare match
with no change.
No compare match
with TRCGRC register,
so “L” output continues
m+1
m: TRCG RA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
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14.3.8 Timer RC Interrupt
Timer RC generates a timer RC interrupt request from five sources. The timer RC interrupt uses the single
TRCIC register (bits IR and ILVL0 to ILVL2) and a single vector.
Table 14.24 lists the Registers Associated with Timer RC Interrupt, and Figure 14.60 is a Timer RC Interrupt
Block Diagram.
Figure 14.60 Timer RC Interrupt Block Diagram
Like other maskable interrupts, the timer RC interru pt is controlled by the combination of the I flag, IR bit, bits
ILVL0 to ILVL2, and IPL. However, it differs from other maskable interrupts in the following respects because
a single interrupt source (timer RC interrupt) is generated from multiple interrupt request sources.
•The IR bit in the TRCIC register is set to 1 (interrupt requested) when a bit in the TRCSR register is set to
1 and the corresponding bit in the TRCIER register is also set to 1 (interrupt enabled).
•The IR bit is set to 0 (no interrup t request) when the bit in the TRCSR reg ister or the corresponding bit in
the TRCIER register is set to 0, or both are set to 0. In other words, the i nterrupt request is not maintai ned
if the IR bit is once set to 1 but the interrupt is not acknowledged.
•If after the IR bit is set to 1 another interrup t source is triggered, the IR bi t remains set to 1 and does not
change.
•If multiple bits in the TRCIER register are set to 1, use the TRCSR register to determine the source of the
interrupt request.
•The bits in the TRCSR register are not automatically set to 0 when an interrupt is ackn owledged. Set th em
to 0 within the interrupt r outine. Refer to Figure 14.30 TRCSR Register, for the procedure for setting
these bits to 0.
Refer to Figure 14.29 TRCIER Register, for details of the TRCIER register.
Refer to 12.1.6 Interrupt Control, for details of the TRCIC register and 12.1.5 .2 Relocata ble Vector Tables,
for information on interrupt vectors.
Ta bl e 14 .24 Regis te rs As so c ia ted with Timer RC Interrupt
Timer RC Status Register Timer RC Interrupt Enable Register Timer RC Interrupt Control Register
TRCSR TRCIER TRCIC
Timer RC interrupt request
(IR bit in TRCIC register)
IMFA bit
IMIEA bit
IMFB bit
IMIEB bit
IMFC bit
IMIEC bit
IMFD bit
IMIED bit
OVF bit
OVIE bit
IMFA, IMFB, IMFC, IMFD, OVF: Bits in TRCSR register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRCIER register
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14.3.9 Notes on Timer RC
14.3.9.1 TRC Register
•The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTAR T bit in the TRCMR register is
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is
set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
•Reading from the TRC register immediat ely after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example MOV.W #XXXXh, TRC ;Write
JMP.B L1 ;JMP.B instruction
L1: MOV.W TRC,DATA ;Read
14.3.9.2 TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the writ e instructions.
Program Example MOV.B #XXh, TRCSR ;Write
JMP.B L1 ;JMP.B instruction
L1: MOV.B TRCSR,DATA ;Read
14.3.9.3 Count Source Switching
•Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the setti ngs of bits TCK2 to TCK0 in the TRCCR1 register.
•After switching the count source from fOCO40M to another clock, allow a m ini mum of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the setti ngs of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in th e FRA0 register to 0 (high-speed on-chip oscillator off).
14.3.9.4 Input Capture Function
•The pulse width of the input capture sign al shoul d be three cycles or more of the timer RC operation clock
(refer to Table 14.11 Timer RC Operation Clock).
•The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
14.3.9.5 TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
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14.4 Timer RE
Timer RE has the 4-bit counter and 8-bit counter.
Timer RE has the following modes:
•Output compare mode Count a count source and detect compare matches.
The count source for timer RE is the operating clo ck that regulates the timing of timer operatio ns.
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14.4.1 Output Compare Mode
In output com pare mode, the inte rnal count so urce divided by 2 is counted using t he 4-bit or 8-bit count er and
compare value match is detected with the 8-bit counter. Figure 14.61 shows a Block Diagram of Output
Compare Mode and Table 14.25 lists the Output Compare Mode Specifications. Figures 14.62 to 14.66 show
the Registers Associated with Output Compare Mode, and Figure 14.67 shows the Operating Example in
Output Compare Mode.
Figure 14.61 Block Diagram of Output Compare Mode
Table 14.25 Output Compare Mode Specifications
Item Specification
Count sources f4, f8, f32
Count operations • Increment
• When the 8-bit counter content matches with the TREMIN register content, the
value returns to 00h and count continues.
The count value is held while count stops.
Count period • When RCS2 = 0 (4-bit counter is not used)
1/fi x 2 x (n+1)
• Whe n RCS2 = 1 (4-bit counter is used)
1/fi x 32 x (n+1)
fi: Frequency of count source
n: Setting value of TREMIN register
Count start condition 1 (count starts) is written to the TSTART bit in the TRECR1 register
Count stop condition 0 (count stops) is written to the TSTART bit in the TRECR1 register
Interrupt req uest generation ti ming When the 8-bit counter content matches with the TREMIN register content
TREO pin function Select any one of the following:
• Programmable I/O ports
• Output f2, f4, or f8
• Compare output
Read from timer When reading the TRESEC register, the 8-bit counter value can be read.
When reading the TREMIN register, the compare value can be read.
Write to timer Writing to the TRESEC register is disabled.
When bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer
stops), writing to the TREMIN register is enabled.
Select functions • Select use of 4-bit counter
• Compare output function
Every time the 8-bit counter value matches the TREMIN register value, TREO
output polarity is reversed. The TREO pin outputs “L” after reset is deasserted
and the timer RE is reset by the TRERST bit in the TRECR1 register. Output
level is held by setting the TSTART bit to 0 (count stops).
TOENA
TREO pin
f32
f4
f8
4-bit
counter 8-bit
counter
TRESEC TREMIN
1/2 RCS2 = 1
RCS2 = 0
COMIE Timer RE interrupt
f2
Match
signal
= 00b
= 01b
= 10b
RCS1 to RCS0
RCS6 to RCS5
= 00b
= 01b
= 10b
= 11b
TRERST, TOENA: Bits in TRECR1 register
COMIE: Bit in TRECR2 register
RCS0 to RCS2, RCS5 to RCS6: Bits in TRECSR register
TQ
RReset
TRERST
Data bus
Comparison
circuit
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Figure 14.62 TRESEC Register in Output Compare Mode
Figure 14.63 TREMIN Register in Output Compare Mode
Figure 14.64 TRECR1 Register in Output Compare Mode
Ti m er RE Counter Dat a Regi st er
Symbol Address After Reset
TRESEC 0118h 00h RW
b7 b6 b5 b4
RO
Function
8-bit counter data can be read.
Although Timer RE stops counting, the count value is held.
The T RESEC register is set to 00h at the compare match.
b3 b2 b1 b0
Ti m er RE Com pare Data Regi s ter
Symbol Address After Reset
TREMIN 0119h 00h RW
b3 b2 b1 b0
RW
Function
8-bit compare data is stored.
b7 b6 b5 b4
Ti m e r RE Cont ro l Register 1
Symbol Address After Reset
TRECR1 011Ch 00h
Bit Symbol Bit Name Function RW
Timer RE reset bit When setting this bit to 0, after setting i t to 1, the
following will occur.
• Registers TRESEC, TREMIN, and TRECR2
are set to 00h.
• Bits TCSTF, INT, and TSTART in the
TRECR1 register are set to 0.
• The 8-bit counter is set to 00h and the 4-bi t
counter is set to 0h.
RW
RW
Set to 0.
TREO pin output enabl e bit 0 : Disable clock output
1 : Enable cl ock output
TOENA RW
RW
TSTART Timer RE count start bit 0 : Count stops
1 : Count starts RW
Interrupt request timing bit Set to 0 in output compare mode.
—
(b6-b5) Reserved bits
TRERST
—
TCSTF RO
Nothi ng is assigned. If necessary, set to 0.
When read, the content is 0.
Timer RE count status flag 0 : Count stopped
1 : Counting
00
b7 b6 b5 b4 b3 b2
INT
b1 b0
0
—
(b0)
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Figure 14.65 TRECR2 Register in Output Compare Mode
Figure 14.66 TRECSR Register in Output Compare Mode
Ti m er RE Control Regi st er 2
Symbol Address After Reset
TRECR2 011Dh 00h
Bit Symbol Bit Name Functi o n RW
Set to 0.
b3 b2 b1 b0
00000
b7 b6 b5 b4
RW
Reserved bits
COMIE Compare match interrupt enable bit RW
—
(b4-b0)
—
(b7-b6) —
Nothi ng is assigned. If necessary, set to 0.
When read, the content is 0.
0 : Disable compare match interrupt
1 : Enable compare match interrupt
Ti m er RE Coun t Source S el ect Register
Symbol Address After Reset
TRECSR 011Eh 00001000b
Bit Symbol Bi t Name Function RW
NOTE:
1.
Nothing is assigne d. If nece ssary, set to 0 .
When read, the content is 0.
—
RW
RCS6 RW
RCS5
—
(b4) Nothing is a ssign ed . If necessary, se t to 0.
When read, the content is 0.
Cl ock output select bits(1) b6 b5
0 0 : f2
0 1 : f4
1 0 : f8
1 1 : Compare output
4-bit counter select bit 0 : Not used
1 : Used
Write to bits RCS5 to RCS6 when the TOENA bit in the TRECR1 register is set to 0 (di sable clock output).
RCS2 RW
RW
—
(b7) —
Reserved bit S et to 0.
RW
RCS1 RW
Count source select bits b1 b0
0 0 : f4
0 1 : f8
1 0 : f32
1 1 : Do not set.
b7 b6 b5 b4 b3 b2
—
(b3)
b1 b0
0
RCS0
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Figure 14.67 Operating Example in Output Compare Mode
00h
8-bit counter content
(hexadecimal number)
Count starts
Time
TSTART bit in
TRECR1 register 1
0
IR bit in
TREIC register 1
0
The above appli es und er th e following conditions .
TOENA bit in TRECR 1 register = 1 (enable clock output)
COMIE bit in TR ECR2 register = 1 (enable compare m at c h interrupt)
RCS6 to RCS5 bits in TRECSR register = 11b (compare output)
Set to 1 by a program
TREMIN register
setting value
Matched
TREO output 1
0
TCSTF bit in
TRECR1 register 1
0
Output polarit y is inv e rted
when the compare m atches
Matched Matched
Set to 0 by acknowledgement of interrupt request
or a program
2 cycles of maximum count source
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14.4.2 Notes on Timer RE
14.4.2.1 Starting and Stopping Count
Timer RE has the TSTART bit for instru cting the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register .
Timer RE starts coun ting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTA RT bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the tim e for up to 2 cycles of the count source unti l the TCSTF bit is set to 0 afte r setting
the TSTART bit to 0. During this ti me, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TRECR1, TRECR2, and TRECSR.
14.4.2.2 Register Setting
Write to the following registers or bits when timer RE is stopped.
•Registers TRESEC, TREMIN, and TRECR2
•INT bit in TRECR1 register
•Bits RCS0 to RCS2 and b3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
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15. Serial Interface
The serial interface consists of one channel (UAR T0). UART0 has an exclusive timer to generate the transfer clock and
operates.
Figure 15.1 shows a UART0 Block Diagram. Figure 15.2 shows a UART0 Transmit/Receive Unit.
UARTi has two modes: clock synchronous serial I/O mode and clock asynchronous serial I/O mode (UART mode).
Figures 15.3 to 15.7 show the Registers Associated with UART0.
Figure 15.1 UART0 Block Diagram
= 01b
f8
f1
= 10b
CLK1 to CLK0 = 00b
RXD0
f32
1/16
1/16
1/2
1/(n0+1)
UART reception
UART transmission
Clock synchronous type
(when internal clock is selected)
Clock
synchronous type Recept io n co n t rol
circuit
Transmission
control circuit
CKDIR = 0
CKDIR = 1
Receive
clock
Transmit
clock
Transmit/
receive
unit
U0BRG register
CKDIR = 0
Internal
External
CKDIR = 1
(UART0)
TXD0
CLK
polarity
switch
circuit
CLK0
Clock
synchronous type
Clock synchronous type
(when external clock is selected)
Clock synchronous type
(when internal clock is selected)
CLK1 to CLK0: Bits in U0C0 register
CKDIR: Bit in U0MR register
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Figure 15.2 UART0 Transmit/Receive Unit
RXD0
1SP
2SP
SP SP PAR
PRYE = 0
PAR
disabled
PAR
enabled
PRYE = 1 UART UART (9 bits)
D7 D6 D5 D4 D3 D2 D1 D0
UART0 receive register
U0RB register
0000000D8
MSB/LSB conversion ci rcu it
Data bus high-order bits
Data bus low-order bits
D7 D6 D5 D4 D3 D2 D1 D0 U0TB register
D8
TXD0
1SP
2SP
SP SP PAR
UART0 transmit register
0SP: Stop bit
PAR: Parity bit
PRYE: Bit in U0MR register
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
Clock
synchronous
type UART (7 bits)
Clock
synchronous
type
UART (7 bits)
Clock
synchronous
type
UART (8 bits)
UART (9 bits)
UART (7 bits)
UART (8 bits)
Clock
synchronous
type
UART (9 bits)
UART
PRYE = 1
PAR
enabled
PAR
disabled
PRYE = 0
Clock
synchronous
type
MSB/LSB conversion ci rcu it
UART (8 bits)
UART (9 bits)
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Figure 15.3 Registers U0TB and U0RB
UA RT0 Trans m i t B uffer Regis ter(1, 2 )
Symbol Address After Reset
U0TB 00A3h-00A2h Undefined RW
NOTES:
1.
2.
(b15)
b7 (b8)
b0 b0b7
When the transfer data length i s 9 bits, w rite data to high byte first, then low byte.
Use the MOV instruction to write to this register.
Function
WO
—
Transmit data
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
—
(b8-b0)
—
(b15-b9)
UART0 Rec ei ve Buffer Regi s ter(1)
Symbol Address After Reset
U0RB 00A7h-00A6h Undefined RW
NOTES:
1.
2.
—
—
(b7-b0) —
Function
Receive data (D7 to D0) RO
Receive data (D8) RO
—
(b8) —
b0b7
(b15)
b7 (b8)
b0
Bit Symbol Bit Name
OER Overrun erro r flag (2) 0 : No overrun error
1 : Overrun error RO
0 : No parity error
1 : Parity error RO
FER F rami ng error fl ag(2) 0 : No framing error
1 : Framing error RO
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
—
(b11-b9)
Read out the U0RB register in 16-bit units.
Bits SUM, PER, F ER, and OER are set to 0 (no error) when bits SMD2 to SMD0 in the U0MR regi ster are set to 000b
(serial interface disabled) or the RE bit in the U0C1 regi ster i s set to 0 (receive disabled). The SUM bit is set to 0 (no
error) when bits PER, FER, and O ER are set to 0 (no error). Bits PER and FER are set to 0 even w hen the higher byte
of the U0RB register i s read out.
Also, bits PER and FER are set to 0 when reading the high-order byte of the U0RB register.
ROSUM Erro r sum flag(2) 0 : No error
1 : Erro r
PER Parity error flag(2)
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Figure 15.4 Registers U0BRG and U0MR
UART0 B it Rate Re gi ste r(1, 2, 3)
Symbol Address After Reset
U0BRG 00A1h Undefined
Setting Range RW
NOTES:
1.
2.
3.
b7
00h to FFh
Function
Assumi ng the set value is n, U0BRG divides the count source by
n+1
After setting the CLK0 to CLK1 bits of the U0C0 register, w rite to the U0BRG register.
b0
Use the MOV instruction to write to this register.
WO
Write to this register while the serial I/O is neither transmitting nor receiving.
UART0 Trans m i t /Rec eive M ode Regist er
Symbol Address After Reset
U0MR 00A0h 00h
Bit Symbol Bit Name Functi on RW
NOTE:
1.
Internal/external clock select bit 0 : Internal cl ock
1 : External clock (1)
Stop bit length select bit
—
(b7) Reserved bit RW
Odd/even parity select bit Enabl e when PRYE = 1
0 : O dd parity
1 : Even parity
PRYE Parity enable bit 0 : Parity disabled
1 : Parity enabl ed RW
S e t to 0.
When the CLK0 pi n is used, set the PD1_6 bit in the PD1 register to 0 (input).
SMD2 RW
RW
STPS RW
0 : 1 stop bi t
1 : 2 stop bi ts
CKDIR
PRY RW
Seria l I/O mode select bits b2 b1 b0
0 0 0 : Serial interface disabled
0 0 1 : Clock synchronous seri al I/O mode
1 0 0 : UART mode transfer data 7 bits l ong
1 0 1 : UART mode transfer data 8 bits l ong
1 1 0 : UART mode transfer data 9 bits l ong
Other than above : Do not set
SMD1
b7 b6 b5 b4
0
RW
b3 b2 b1 b0
SMD0 RW
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Figure 15.5 U0C0 Register
UA RT0 Transm i t/ Recei ve Cont rol Register 0
Symbol Address After Reset
U0C0 00A4h 00001000b
Bit Symbol Bi t Name Function RW
NOTE:
1.
RW
RW
If the BRG count source i s switched, set the U0BRG register agai n.
RW
Data output select bit 0 : TXDi pin is for CMOS output
1 : TXDi pin is for N-channel open drain output
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
NCH
CLK polarity select bit 0 : Transmit data is output at fal ling edge of transfer
clock and recei ve data is input at risi ng edge
1 : Transmit data i s output at risi ng edge of transfer
clock and recei ve data is input at falling edge
Set to 0.
Transmit register empty
flag 0 : Data in transmit register (during transmit)
1 : No data in transmit regi ster (transmit compl eted)
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
—
(b2)
CKPOL
CLK1 RW
BRG count source select
bits(1) b1 b0
0 0 : S e lects f1
0 1 : S e lects f8
1 0 : S e lects f32
1 1 : Do not set.
RW
RW
RO
—
(b4) —
Reserved bit
b7 b6 b5 b4 b3 b2
TXEPT
b1 b0
0
CLK0
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Figure 15.6 U0C1 Register
Figure 15.7 PMR Regist er
UA RT0 Transm i t/ Recei ve Cont rol Register 1
Symbol Address After Reset
U0C1 00A5h 00000010b
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2.
b0
Nothi ng is assigned. If necessary, set to 0.
Wh en read, the content is 0.
Transmit enable bit(1) 0 : Di sables transmission
1 : Enables transmission
Transmit buffer empty flag
0 : Disables reception
1 : Enables reception
U0IRS
b3 b2 b1
—
Receive enable bit
b7 b6 b5 b4
RW
TI RO
0 : Data in U0TB register
1 : No data in U0TB register
TE
RO
RW
RI Receive complete flag(1) 0 : No data in U0RB regi ster
1 : Data in U0RB register
RE
Set the U0RRM bit to 0 (disables continuous receive mode) in UART mode.
UART 0 transmi t interrupt cause
select bit 0 : T ransmission buffer empty (TI=1)
1 : Transmission completed (TXEPT=1) RW
U0RRM UART0 conti n uous receive mode
enable bit(2) 0 : Disables continuous receive mode
1 : Enables continuous receive mode RW
The RI bit is set to 0 when the hi gher byte of the U0RB register is read out.
—
(b7-b6)
P ort M ode Regi s te
r
Symbol Address After Reset
PMR 00F8h 00h
Bit Symbol Bi t Name Function RW
INT1
_
___ pin select bit
000
b7 b6 b5 b4 b0b3 b2 b1
INT1SEL 0 : P1_5, P1_7
1 : P3_6 RW
—
(b3-b1) —
Nothing is a ssigned. If necessary, set to 0.
When read, the content is 0.
—
(b7) —
Nothing is a ssigned. If necessary, set to 0.
When read, the content is 0.
—
(b6-b4) Reserved bits Set to 0. RW
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15.1 Clock Synchronous Serial I/O Mode
In the clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Table 15.1 lists the Spec ifications of Clock Syn chronous Serial I/O Mode. Tabl e 15.2 lists the Regist ers Used and
Settings in Clock Synchronous Serial I/O Mode.
NOTES:
1. If an external clock is selected, ensure that the external clock is “H” when the CKPOL bit in the
U0C0 register is set to 0 (transmit data output at falling edge and receive data input at rising edge of
transfer clock), and that the e xternal clock is “L” when the CKPOL bit is set to 1 (transmit data output
at rising edge and receive data input at falling edge of transfer clock).
2. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR
bit in the S0RIC register remains unchang ed.
Table 15.1 Specifications of Clock Synchronous Serial I/O Mode
Item Specification
Transfer data format • Transfer data length: 8 bits
Transfer clocks • CKDIR bit in U0MR register is set to 0 (internal clock): fi/(2(n+1))
fi = f1, f8, f32 n = value set in U0BRG register: 00h to FFh
• The CKDIR bit is set to 1 (external clock): input from CLK0 pin
Tr ansmit start conditions • Before transmit starts, the following requirements must be met(1)
- The TE bit in the U0C1 register is set to 1 (transmission enabled)
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register)
Receive start conditions • Before receive sta rts, the following requirements must be met(1)
- The RE bit in the U0C1 register is set to 1 (reception enabled)
- The TE bit in the U0C1 register is set to 1 (transmission enabled)
- The TI bit in the U0C1 register is set to 0 (data in the U0TB register)
Interrupt request
generation timing • When transmitting, one of the following conditions can be selected
- The U0IRS bit is set to 0 (transmit buf fer empty):
When transferring data from the U0TB register to UART0 transmit
register (when transmission starts).
- The U0IRS bit is set to 1 (transmission completes):
When completing data transmission from UART0 transmit register.
• When receiving
When data transfer from the UART0 receive register to the U0RB register
(when reception completes).
Error detectio n • Overrun error(2)
This error occurs if the serial interface starts receiving the next data item
before reading the U0RB register and receives the 7th bit of the next data.
Select functions • CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the
rising or the falling edge of the transfer clock.
• LSB first, MSB first selection
Whether transmitting or rece ivin g da ta begins with bit 0 or be gins with bit 7
can be selected.
• Continuous receive mode selection
Receive is enable d immediately by reading the U0RB register.
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NOTE:
1. Set bits which are not in this table to 0 when writing to the above registers in clock synchronous
serial I/O mode.
Table 15.3 lists the I/O Pin Functions in Clock Synchronous Serial I/O Mode. The TXD0 pin outputs “H” level
between the operating mode selection of UART0 and transfer start. (If the NCH bit is set to 1 (N-channel open-
drain outpu t ), this pin is in a high-impedance state.)
Table 15.2 Registers Used and Settings in Clock Synchronous Serial I/O Mode(1)
Register Bit Function
U0TB 0 to 7 Set data transmission
U0RB 0 to 7 Data reception can be read
OER Overrun error flag
U0BRG 0 to 7 Set bit rate
U0MR SMD2 to SMD0 Set to 001b
CKDIR Select the internal clock or external clock
U0C0 CLK1 to CLK0 Select the count source in the U0BRG register
TXEPT Transmit register empty flag
NCH Se lect TXD0 pin output mode
CKPOL Select the transfer clock polarity
UFORM Select the LSB first or MSB first
U0C1 TE Set this bit to 1 to enable transmission/reception
TI Tran sm it bu ffer empty flag
RE Set this bit to 1 to enable reception
RI Reception complete flag
U0IRS Select the UART0 transmit interrupt source
U0RRM Set this bit to 1 to use continuous receive mode
Table 15.3 I/O Pin Functions in Clock Synchronous Serial I/O Mode
Pin Name Function Selection Method
TXD0 (P1_4) Output serial data (Outputs dummy data when performing reception only)
RXD0 (P1_5) Input serial data PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6) Output transfer clock CKDIR bit in U0MR register = 0
Input transfer clock CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
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Figure 15.8 Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
Transfer clock
D0
TE bit in U0C1
register
TXD0
• Example of transmit timing (when internal clock is selected)
Set data in U0TB register
Transfer fr om U 0T B re gi s te r to UAR T 0 t ran s m it re gis t er
TC
CLK0
TCLK Stop pulsin g be ca use th e T E bi t is set to 0
D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
TC = TCLK = 2(n+1)/fi
fi: Frequency of U0BRG count source (f1, f8, f32)
n: Setting value to U0BRG register
The above applies under the following settings:
• CKDIR bit in U0MR register = 0 (internal clock)
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• U0IRS bit in U0C1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
D0
Set to 0 when interrup t request is acknowl edg ed , or set by a pr ogr am
Write dum m y data to U0TB register
Transfer fr om U 0T B re gi s te r to UAR T 0 t ran s m it re gis t er
1/fEXT
D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5
Receive data is taken in
Read out from U0RB register
Transfer fr om U ART 0 recei v e re gi ster to
U0RB register
TI bit in U0C1
register
1
0
1
0
1
0
1
0
TXEPT bit in
U0C0 register
IR bit in S0TIC
register
Set to 0 when interrupt request is acknowledged, or set by a program
• Example of receive timing (when external clock is selected)
RE bit in U0C1
register
TE bit in U0C1
register
TI bit in U0C1
register
1
0
1
0
1
0
RI bit in U0C1
register
IR bit in S0RIC
register
1
0
1
0
CLK0
RXD0
The above applies under the following settings:
• CKDIR bit in U0MR register = 1 (external clock)
• CKPOL bit in U0C0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfe r cloc k)
The following conditions are met when “H” is applied to the CLK0 pin before receiving data:
• TE bit in U0C1 register = 1 (enables transmit)
• RE bit in U0C1 register = 1 (enables receive)
• Write dummy data to the U0TB register
fEXT: Frequency of external clock
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15.1.1 Polarity Select Function
Figure 15.9 shows the Transfer Clock Polarity. Use the CKPOL bit in the U0C0 register to select the transfer
clock polarity.
Figure 15.9 Transfer Clock Polarity
15.1.2 LSB First/MSB First Select Function
Figure 15.10 shows the Transfer Format. Use the UFORM bit in the U0C0 register to select the transfer format.
Figure 15.10 Transfer Format
CLK0(1)
D0TXD0
• When the CKPOL bit in th e U0C0 re gister = 0 (output transmit data at the falling
edge and input receive data at the risi ng edge of the transfer clock)
D1 D2
NOTES:
1. When not transferring, the CLK0 pin level is “H”.
2. When not transferring, the CLK0 pin level is “L”.
D3 D4 D5 D6 D7
D0RXD0 D1 D2 D3 D4 D5 D6 D7
CLK0(2)
D0TXD0 D1 D2 D3 D4 D5 D6 D7
D0RXD0 D1 D2 D3 D4 D5 D6 D7
• When the CKPOL bit in th e U0C0 re gister = 1 (output transmit data at the ri sing
edge and input receive data at the falling edge of the transfer clock)
CLK0
D0
TXD0
• When UFORM bit in U0C0 register = 0 (LSB first)(1)
D1 D2 D3 D4 D5 D6 D7
D0RXD0 D1 D2 D3 D4 D5 D6 D7
CLK0
D7TXD0 D6 D5 D4 D3 D2 D1 D0
RXD0
• When UFORM bit in U0C0 register = 1 (MSB first)(1)
NOTE:
1. The above applies whe n th e CKPOL bit in the U0C0 register is
set to 0 (output transmit data at the falling edge and input receive
data at the rising edge of the transfer clock).
D7 D6 D5 D4 D3 D2 D1 D0
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15.1.3 Continuous Receive Mode
Continuous receive mode is selected by setting the U0RRM bit in the U0C1 register to 1 (enables continuous
receive mode). In this mode, reading the U0RB register sets the TI bit in the U0C1 register to 0 (data in the
U0TB register). When the U0RRM bit is set to 1, do not write dum my data to the U0TB register by a program.
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15.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allo ws data transmission and rec eption after setting the desired bit rate and transfer data form at.
Table 15.4 lists the Specifications of UART Mode. Table 15.5 lists the Registers Used and Settings for UART
Mode.
NOTE:
1. If an overrun error occurs, the receive data (b0 to b8) of the U0RB register will be undefined. The IR
bit in the S0RIC register remains unchang ed.
Table 15.4 Specifications of UART Mode
Item Specification
Transfer data formats • Character bit (transfer data): Selectable among 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable among odd, even, or none
• Stop bit: Selectable among 1 or 2 bits
Transfer clocks • C KD IR b i t i n U 0M R re g is t e r is set to 0 (internal clock) : fj/(16(n+1))
fj = f1, f8, f32 n = value set in U0BRG register: 00h to FFh
•CKDIR bit is set to 1 (external clock): fEXT/(16(n+1))
fEXT: Input from CLK0 pin, n = value set in U0BRG register: 00h to FFh
Transmit start conditions • Before transmission starts, the following are required
- TE bit in U0C1 register is set to 1 (transmission enabled)
- TI bit in U0C1 register is set to 0 (data in U0TB register)
Receive start conditions • Before reception st arts, the following are required
- RE bit in U0C1 register is set to 1 (reception enabled)
- Start bit detected
Interrupt request
generation timing • When transmitting, one of the following conditions can be selected
- U0IRS bit is set to 0 (transmit buffer empty):
When transferring data from the U0TB register to UART0 transmit
register (when transmit starts).
- U0IRS bit is set to 1 (transfer ends):
When serial interfac.e completes transmitting data from the UART0
transmit regis te r
• When receiving
When transferring dat a fr om the UAR T0 rece ive registe r to U0RB register
(when receive ends).
Error detectio n •Overrun error(1)
This error occurs if the serial interface starts receiving the next data item
before reading the U0RB register and receive the bit preceding the final
stop bit of the next data item.
• Framing error
This error occurs when the set number of stop bits is not detected.
• Parity error
This error occurs when parity is enabled, and the number of 1’s in parity
and character bits do not match the number of 1’s set.
• Error sum flag
This flag is set is set to 1 when an overrun, fram in g, or parity error is
generated.
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NOTES:
1. The bits used for transmit/receive data are as follows: Bits 0 to 6 when transfer data is 7 bits long;
bits 0 to 7 when transfer data is 8 bit s long; bits 0 to 8 when transfer da ta is 9 bits long.
2. The following bits are un defined: Bits 7 and 8 when transfer data is 7 bits long; bit 8 when transfer
data is 8 bits long.
Table 15.6 lists the I/O Pin Functions in UART Mode. After the UA RT0 operating mode i s selected, the TXD0 pin
outputs “H” level (If the NCH bit is set to 1 (N-channel open-drain output), this pin is in a high-impedance state)
until transfer starts.
Table 15.5 Registers Used and Settings for UART Mode
Register Bit Function
U0TB 0 to 8 Set transmit data(1)
U0RB 0 to 8 Re ce ive da ta can be read(1, 2)
OER,FER,PER,SUM Error flag
U0BRG 0 to 7 Set a bit rate
U0MR SMD2 to SMD0 Set to 100b when transfer data is 7 bits long.
Set to 101b when transfer data is 8 bits long.
Set to 110b when transfer data is 9 bits long.
CKDIR Select the internal clock or external clock
STPS Select the stop bit
PRY, PRYE Select whether parity is included and whether odd or even
U0C0 CLK0, CLK1 Select the count source for the U0BRG register
TXEPT Transmit register empty flag
NCH Select TXD0 pin output mode
CKPOL Set to 0
UFORM LSB first or MSB first can be selected when transfer data is 8 bits
long. Set to 0 when transfer data is 7 or 9 bits long.
U0C1 TE Set to 1 to enable transm it
TI Transmit buffer empty flag
RE Set to 1 to enable receive
RI Receive complete flag
U0IRS Select the factor of UART0 transmit interrupt
U0RRM Set to 0
Table 15.6 I/O Pin Functions in UART Mode
Pin name Function Selection Method
TXD0 (P1_4) Output serial data (Cannot be used as a port when performing reception only)
RXD0 (P1_5) Input serial data PD1_5 bit in PD1 register = 0
(P1_5 can be used as an input port when performing
transmission only)
CLK0 (P1_6) Programmable I/O Port CKDIR bit in U0MR register = 0
Input transfer clock CKDIR bit in U0MR register = 1
PD1_6 bit in PD1 register = 0
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Figure 15.11 Transmit Timing in UART Mode
D0
TC
D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SPST D0 D1ST
D0
TC
D1 D2 D3 D4 D5 D6 D7 D8 SP SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST D0 D1ST
Transfer clock
TE bit in U0C1
register
TXD0
Set to 0 w hen interrup t request is ack nowledged , or set by a program
• Transmit timing when transfer data is 8 bits long (parity enabled, 1 stop bit)
Write data to U 0T B re gi st e r
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Fr equency of U0 B RG count source (f1, f8, f32)
fEXT: Frequency of U0BRG count source (external clock)
n: Settin g v alue to U0BRG regist e r
The above timing diagram applies under the following conditi ons:
• PRYE bit in U0MR register = 1 (parity enabled)
• STPS bit in U0MR register = 0 (1 stop bit)
• U0IRS bit in U0C1 register = 1 (an interrupt request is generated when transmit completes)
Start
bit Parity
bit
Stop pulsing
because the TE bit is set to 0
TXD0
Write data to U0TB regist er
Transfer from U0TB register to UART0 transmit register
TI bit in U0C1
register
1
0
1
0
1
0
1
0
TXEPT bit
U0C0 register
IR bit in
S0TIC register
Stop
bit
• Transmit timing when transfer data is 9 bits long (parity disabled, 2 stop bits)
1
0
Stop
bit
Stop
bit
Start
bit
Transfer clock
TE bit in U0C1
register
TI bit in U0C1
register
TXEPT bit in
U0C0 register
IR bit in
S0TIC register
1
0
1
0
1
0
Transfer fr om U 0T B re gi s te r to UAR T 0 t ran s m i t re gi ster
TC=16 (n + 1) / fj or 16 (n + 1) / fEXT
fj: Frequency of U0BRG count source (f1, f8, f32)
fEXT: Frequency of U0BRG count source (external clock)
n: Setting value to U0BRG register
Set to 0 when interrupt request is acknowledged, or set by a program
The above timing diagram applies under the following conditions:
• PRYE bit in U0MR register = 0 (parity disabled)
• STPS bit in U0MR register = 1 (2 stop bits)
• U0IRS bit in U0C1 register = 0 (an interrupt request is generated when transmit buffer is empty)
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Figure 15.12 Receive Timing Example in UART Mode
U0BRG output
Set to 0 when interrupt request is accepted, or set by a program
• Example of receive timi ng when transfer data is 8 bits long (parity disabled, one stop bit)
The above tim in g diagram applies when the regis ter bits are set as f ollows:
• PRYE bit in U0MR regis te r = 0 (parity di s abled)
• STPS bit in U0MR regist er = 0 (1 st op bit )
RE bit in
U0C1 register
Start bit Stop bit
D0 D1 D7
RXD0
Transfer clock
Determined to be “L” Receive data taken in
Reception triggered when transfer clock
is generated by falling edge of start bit Transferred from UART0 receive
register to U0RB register
RI bit in
U0C1 register
IR bit in
S0RIC regis t er
1
0
1
0
1
0
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15.2.1 Bit Rate
In UART mode, the bit rate is the frequency divided by the U0BRG register.
Figure 15.13 shows a Calculation Formula of U0BRG Register Setting Value. Ta ble 15.7 lists the Bit Rate
Setting Example in UART Mode (Internal Clock Sel ected).
Figure 15.13 C alculation Formula of U0BRG Register Setting Va lue
Table 15.7 Bit Rate Setting Example in UART Mode (Internal Clock Selected)
Bit Rate
(bps)
BRG
Count
Source
System Clock = 20 MHz System Clock = 8 MHz
U0BRG
Setting Value Actual T ime
(bps) Error (%) U0BRG
Setting Value Actual
Time (bp s) Error (%)
1200 f8 129 (81h) 1201.92 0.16 51 (33h) 1201.92 0.16
2400 f8 64 (40h) 2403.85 0.16 25 (19h) 2403.85 0.16
4800 f8 32 (20h) 4734.85 -1.36 12 (0Ch) 4807.69 0.16
9600 f1 129 (81h) 9615.38 0.16 51 (33h) 9615.38 0.16
14400 f1 86 (56h) 14367.82 -0.22 34 (22h) 14285.71 -0.79
19200 f1 64 (40h) 19230.77 0.16 25 (19h) 19230.77 0.16
28800 f1 42 (2Ah) 29069.77 0.94 16 (10h) 29411.76 2.12
31250 f1 39 (27h) 31250.00 0.00 15 (0Fh) 31250.00 0.00
38400 f1 32 (20h) 37878.79 -1.36 12 (0Ch) 38461.54 0.16
51200 f1 23 (17h) 52083.33 1.73 9 (09h ) 50000.00 -2.34
UART mode
• Internal cl ock select ed
U0BRG register setting value = fj
Bit Rate × 16 - 1
fj: Count source frequency of the U0BRG register (f1, f8, or f32)
• External clock selected fEXT
Bit Rate × 16 - 1
fEXT: Count source frequency of the U0BRG register (external clock)
U0BRG register setting value =
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15.3 Notes on Serial Interface
•When reading data from the U0RB register either in the clock synchronous serial I/O mode or in the clock
asynchronous serial I/O mode, ensure the data is read in 16-bit units. When the high-order byte of the U0RB
register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0.
The check receive errors, read the U0RB register and then use the read data.
Example (when reading receive buffer register):
MOV.W 00A6H,R0 ; Read the U0RB register
•When writing data to the U0TB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
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16. Hardware LIN
The hardware LIN performs LIN communication in cooperation with timer RA and UART0.
16.1 Features
The hardware LIN has the features listed below.
Figure 16.1 shows a Block Diagram of Hardware LIN.
Master mode
•Generates Synch Break
•Detects bus collision
Slave mode
•Detects Synch Break
•Measures Synch Field
•Controls Synch Break and Synch Field signal inpu ts to UART0
•Detects bus collision
NOTE:
1. The WakeUp function is detected by INT1.
Figure 16.1 Block Diagram of Hardware LIN
Timer RA
UART0
Interrupt
control
circuit
Bus collision
detection
circuit
Synch Field
control
circuit
RXD0 input
control
circuit
RXD0 pin
TXD0 pin
LSTART bit
SBE bit
LINE bit Timer RA
interrupt
TIOSEL = 0
Hardware LIN
TIOSEL = 1
RXD data
Timer RA
underflow signal
Bits BCIE,
SBIE, and SFIE UART0 transfer clock
UART0 TE bit
Timer RA output pulse
UART0 TX D data
MST bit
LINE, MST, SBE, LSTART, BCIE, SBIE, SFIE: Bits in LINCR register
TIOSEL: Bit in TRAIOC register
TE: Bit in U0C1 register
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16.2 Input/Output Pins
The pin configuration of the hardware LIN is listed in Table 16.1.
Table 16.1 Pin Configuration
Name Abbreviation Input/Output Function
Receive data input RXD0 Input Receiv e da ta input pin of the ha rd wa re LIN
Tr an sm it da ta outpu t TX D0 Output Transmit data output pin of the hardwa re LIN
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16.3 Register Configuration
The hardware LIN contains the registers listed below.
These registers are detailed in Figures 16.2 and 16.3.
•LIN Control Register (LINCR)
•LIN Status Register (LINST)
Figure 16.2 LINCR Register
LIN Contro l Re gi ster
Symbol Address After Reset
LINCR 0106h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. Inputs to ti mer RA and UART0 are prohibi ted immediately after this bit is set to 1. (Refer to Figure 16.5 Example of
Header Field Transmission Flowchart (1) and Figure 16.9 Example of Header F ield Reception Flowchart
(2).)
Before changing LIN operation modes, temporarily stop the LIN operation (LINE bit = 0).
SBE
After setting the LS TART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
0 : Unmasked after S ynch Break is detected
1 : Unmasked after S ynch Fi eld measurement
is completed RW
RXD0 input unmasking timing
select bit (effective only in slave
mode)
MST RW
LINE
SBIE
BCIE
RXDSF
LSTART
Synch Break detection interrupt
enable bit
Bus collision detection interrupt
enable bit
0 : Disables Synch Break detection interrupt
1 : Enables Synch Break detection interrupt
0 : Disables bus collision detection interrupt
1 : Enables bus collision detection interrupt
0 : RXD0 input enable d
1 : RXD0 input disabled
W h e n this bit is set to 1, timer RA in p ut i s
enabled and RXD0 input is disabled.
When read, the content is 0.
RW
RW
RO
RW
RW
RXD0 input status flag
Synch Break detection start bit(1)
b3 b2 b1 b0b7 b6 b5 b4
0 : Disables Synch Field measurement-
completed interrupt
1 : Enables Synch Fiel d measurement-
completed interrupt
SFIE
Synch Field measurement-
completed interrupt enable bit
LIN operation start bit 0 : Causes LIN to stop
1 : Causes LIN to start operating(3) RW
LIN operation mode setting bit(2) 0 : Slave mode
(Synch Break detecti on circuit actuated)
1 : Master mode
(timer RA output O R’ed with TXD0)
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Figure 16.3 LINST Register
LIN S tatus Regist er
Symbol Address After Reset
LINST 0107h 00h
Bit Symbol Bit Name Functi on RW
—
(b7-b6) —
1 show s Synch F ield measurement compl eted.
SFDCT Synch Field measurement-
completed flag RO
RW
RW
RW
RO
b3 b2 b1 b0b7 b6 b5 b4
RO
SBDCT bit clear bit
BCDCT bit clear bit
1 show s Synch Break detected or Synch Break
generation compl e ted.
1 show s Bus collision detected.
Whe n this bit is set to 1, the SFDCT bit is set to 0.
When read, the content is 0.
When this bit is set to 1, the SBDCT bit is set to 0.
When read, the content is 0.
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
B2CLR
SBDCT
BCDCT
B0CLR
B1CLR
When this bit is set to 1, the BCDCT bit is set to 0.
When read, the content is 0.
Synch Break detection fl ag
Bus collision detection flag
SFDCT bit clear bit
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16.4 Functional Description
16.4.1 Master Mode
Figure 16.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.
Figures 16.5 and 16.6 show an Example of Header Field Transmission Flowchart.
When transmitting a header field, the hardware LIN operates as described below.
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for
timer RA.
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
(3) The hardware LIN transmit s 55h via UART0.
(4) The hardware LIN transmit s an ID field via UART0 after it finishes sending 55h .
(5) The hardware LIN performs comm unication for a response field after it finishes sending the ID field.
Figure 16.4 Typical Operation when Sending a Header Field
TXD0 pin
Synch Break
1
0
SBDCT flag in
LINST register 1
0
IR bit in
TRAIC register 1
0
Sync h Field IDENTIFIER
(1) (2) (3) (4) (5)
Set by writing 1 to the
B1CLR bit in the LINST
register
Cleared to 0 upon
acceptance of interrupt
request or by a program
The above applies under the following conditions.
LINE = 1, MST = 1, SBIE = 1
LINE, MST, SBIE: Bits in LINCR register
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Figure 16.5 Example of Header Field Transmission Flowchart (1)
Timer RA Set to timer mode
Bits TMOD0 to TMOD2 in TRAMR register ← 000b
Timer RA Set the pulse output level from low to start
TEDGSEL bit in TRAIOC register ← 1
Timer RA Set the INT1/TRAIO pin to P1_5
TIOSEL bit in TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set to master mode
MST bit in LINCR register ← 1
Hardware LIN Set the LIN operation to start
LINE bit in LINCR register ← 1
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in LINCR register
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in LINST register ← 1
Set the count source and
registers TRA and TRAPRE
as suitable for the Synch
Break per iod.
During master mode, the
Synch Field measurement-
completed interrupt cannot be
used.
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
UART0 Set to transmit/receive mode
(Transfer data length: 8 bits, Internal clock, 1 stop bit,
Parity disabled)
U0MR register
UART0 Set the BRG count source (f1, f8, f32)
Bits CLK0 to CLK2 in U0C0 register
UART0 Set the bit rate
U0BRG register
Hardware LIN Set the LIN operation to stop
LINCR register LINE bit ← 0
Set the BRG count source
and U0BRG register as
appropriate for the bit rate.
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Figure 16.6 Example of Header Field Transmission Flowchart (2)
Timer RA Set the timer to start counting
TSTART bit in TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
Hardware LIN Read the Synch Break detection flag
SBDCT flag in LINST register
Timer RA Set the timer to stop cou nting
TSTART bit in TRACR register ← 0
Timer RA Read the count status flag
TCSTF flag in TRACR register
UART0 Communication via UART0
TE bit in U0C1 register ← 1
U0TB register ← 0055h
The timer RA interrupt may be used
to terminate generation of Synch
Break.
Three to five cycles of the CPU clock
are required after Synch Break
generation completes befo re the
SBDCT flag is set to 1.
Transmit the ID field.
A
TCSTF = 1 ?
SBDCT = 1 ?
YES
TCSTF = 0 ?
YES
UART0 Communication via UART0
U0TB register ← ID field
NO
YES
NO
NO
If registers TRAPRE and TRA for timer
RA do not need to be read or the
register settings do not need to be
changed after writing 0 to the TSTART
bit, the procedure for reading TCSTF
flag = 0 can be omitted.
Zero to one cycle of the timer RA count
source is required after timer RA stops
counting before the TCSTF flag is set
to 0.
Transmit the Synch Field.
After timer RA Synch Break is
generated, the timer should be made
to stop counting.
If registers TRAPRE and TRA for
timer RA do not need to be re ad or
the register settings do not need to be
changed after writing 1 to the
TSTART bit, the procedure for reading
TCSTF flag = 1 can be omitted.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
Timer RA generates Synch Break.
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16.4.2 Slave Mode
Figure 16.7 shows typical operation of the hardware LIN when receiving a header field in slave mode. Figure
16.8 through Figure 16.10 show an Example of Header Field Transmission Flowchart.
When receiving a header field, the hardware LIN operates as described below.
(1) Synch Break detection is enabled by writing 1 to the LSTART bit in the LINCR register of the hardware
LIN.
(2) When “L” level is input for a durat ion equal to or greater than the period set in timer RA, the hardware
LIN detects it as Synch Break. At this time, the SBDCT flag in the LINST register is set to 1.
Furthermore, if the SBIE bit in the LINCR register is set to 1, the hardware LIN generates a timer RA
interrupt. Then it goes to Synch Field measurement.
(3) The hardware LIN receives a Synch Field (55h). At this time, it measures the period of the start bit and
bits 0 to 6 by using timer RA. In this case, it is possible to select whether to input the Synch Field signal
to RXD0 of UART0 by setting the SBE bit in the LINCR register accordingly.
(4) The hardware LIN sets the SFDCT flag in the LINST register to 1 when it finishes measuring the Synch
Field. Furthermore, if the SFIE bit in the LINCR register is set to 1, it generates a timer RA interrupt.
(5) After it finishes measuring the Synch Field, calculate a transfer rate from the count value of timer RA
and set to UART0 and registers TRAPRE and TRA of timer RA again. Then it receives an ID field via
UART0.
(6) The hardware LIN performs communication for a response field after it finishes receiving the ID field.
Figure 16.7 Typical Op era ti on wh en Rec e iv in g a He ad e r Field
RXD0 pin
Synch Break
1
0
RXD0 input f o r
UART0 1
0
RXDSF flag in
LINCR register 1
0
Synch Field IDENTIFIER
(2) (3) (5) (6)
The above applies under the following conditions.
LINE = 1, MST = 0, SBE = 1, SBIE = 1, SFIE = 1
LINE, MST , SBE, SBIE, SFI E : Bits in LINCR register
(4)(1)
SBDCT flag in
LINST register 1
0
SFDCT flag in
LINST register 1
0
IR bit in
TRAIC register 1
0
Set by writing 1 to the
B0CLR bit in the LINST
register
Cleared to 0 when Synch
Field mea surement
finishes
Measure this period
Set by writing 1 to
the B1CLR bit in
the LINST register
Cleared to 0 upon
acceptance of
interrupt request or
by a program
Set by writing 1 to
the LSTA RT bit in
the LINCR reg i ster
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Figure 16.8 Example of Header Field Reception Flowchart (1)
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Timer RA Set to pulse width measu rement m ode
Bits TMO D0 to T M O D2 in the TR A M R register ← 011b
Timer RA Set the pulse width measurement level low
TEDGSEL bit in the TRAIOC register ← 0
Timer RA Set the INT1/TR AIO pin to P1_5
TIOSEL bit in the TRAIOC register ← 1
Timer RA Set the count source (f1, f2, f8, fOCO)
Bits TCK0 to TCK2 in the TRAMR register
Timer RA Set the Synch Break width
TRAPRE register
TRA register
Hardware LIN Set the LIN operation to stop
LINE bit in the LINCR register ← 0
Hardware LIN Set to slave mode
MST bit in the LINCR register ← 0
Hardware LIN Set the RXD0 input unmasking timing
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
Hardware LIN Set the register to enable interrupts
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
Hardware LIN Set the LIN operation to start
LINE bit in the LINCR register ← 1
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Figure 16.9 Example of Header Field Reception Flowchart (2)
Timer RA Set to start a pulse width measurement
TSTART bit in the TRACR register ← 1
Timer RA Read the count status flag
TCSTF flag in the TRACR register
Hardware LIN Set to start Synch Break detection
LSTART bit in the LINCR register ← 1
Hardware LIN Read the RXD0 input status flag
RXDSF flag in the LINCR register
A
TCSTF = 1 ?
YES
RXDSF = 1 ?
YES
NO
NO
Timer RA waits until the timer starts
counting.
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break
detection, Synch Field measurement)
Bits B2CLR, B1CLR, B0CLR in the LINST
register ← 1
Hardware LIN Read the Synch Break detection flag
SBDCT flag in the LINST register
SBDCT = 1 ?
YES
NO
B
Do not apply “L” level to the RXD pin
until the RXDSF flag reads 1 after
writing 1 to the LSTART bit. This is
because the signal applied during this
time is input directly to UART0.
Three to five cycles of the CPU clock
are required after the LSTART bit is
set to 1 before the RXDSF flag is set
to 1. After this, input to timer RA and
UART0 is enabled.
Hardware LIN detects a Synch Break.
The interrupt of the timer RA may be
used.
Hardware LIN waits until the RXD0
input for UART0 is masked.
When Synch Break is detected, timer
RA is reloaded with the initially set
count value.
Even if the duration of the input “L”
level is shorter than the set period,
timer RA is reloaded with the initially
set count value and waits until the
next “L” level is input.
Three to five cycles of the CPU clock
are required after Synch Break
detection before the SBDCT flag is
set to 1.
When the SBE bit in the LINCR
register is set to 0 (unmasked after
Synch Break is detected), timer RA
can be used in timer mode after the
SBDCT flag in the LINST register is
set to 1 and the RXDSF flag is set to
0.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the TCSTF
flag is set to 1.
R8C/2E Group, R8C/2F Group 16. Hardware LIN
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Figure 16.10 Example of Header Field Reception Flowchart (3)
Hardware LIN Read the Synch Field measurement-
completed flag
SFDCT flag in the LINST register
UART0 Set the UART0 communication rate
U0BRG register
Communication via UART0
(The SBDCT flag is set when the
timer RA counter underflows upon
reaching the terminal count.)
B
SFDCT = 1 ?
YES
UART0 Communication via UART0
Clock asynchronous serial interface (UART) mode
Transmit ID field
NO
Hardware LIN measures the Synch
Field.
The interrupt of timer RA may be
used (the SBDCT flag is set when
the timer RA counter underflows
upon reaching the terminal count).
When the SBE bit in the LINCR
register is set to 1 (unmasked after
Synch Field measurement is
completed), timer RA may be used
in timer mode after the SFDCT bit
in the LINST register is set to 1.
Set a communication rate based on
the Synch Field measurement
result.
YES
Timer RA Set the Synch Break width again
TRAPRE register
TRA register
R8C/2E Group, R8C/2F Group 16. Hardware LIN
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16.4.3 Bus Collision Detection Function
The bus collision detection functio n can be us ed when UART0 i s enabled for transmi ssion (TE bi t in the U 0C1
register = 1).
Figure 16.11 shows Typical Operation when a Bus Collision is Detected.
Figure 16.11 Typical Operation when a Bus Collision is Detected
TXD0 pin 1
0
RXD0 pin 1
0
Transfer clock 1
0
LINE bit in the
LINCR register 1
0
TE bit in the U0C1
register 1
0
BCDCT flag in the
LINST register 1
0
IR bit in the TRAIC
register 1
0
Cleared to 0 upon
acceptance of interrupt
request or by a program
Set by writing 1 to
the B2CLR bit in the
LINST register
Set to 1 by a program
Set to 1 by a program
R8C/2E Group, R8C/2F Group 16. Hardware LIN
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16.4.4 Hardware LIN End Processing
Figure 16.12 shows an Examp le of Hardware LIN Communication Completion Flowchart .
Use the following timing for hardware LIN end processing:
•If the hardware bus collision detection fun c tion is used
Perform hardware LIN end processing after checksum tran smission completes.
•If the bus collision detection function is not used
Perform hardware LIN end processing after header field transmission and reception complete.
Figure 16.12 Example of Hardware LIN Commun ication Completion Flowchart
Hardware LIN Clear the status flags
(Bus collision detection, Synch Break detection, Synch
Field m easurement)
Bits B2CLR, B1CLR, B0CLR in the LINST register ← 1
Timer RA Read the count status flag
TCSTF flag in TRACR register
UART0 Complete transmission via UART0 W hen the bus collisio n d e tectio n
function is not used, end
processing for the U AR T0
transmission is not required.
TCSTF = 0 ?
YES
NO
Set the tim er to stop counting.
Zero to one cycle of the timer RA
count source is required after timer
RA starts counting before the
TCSTF flag is set to 1.
After clearing hardware LIN
status flag, stop the hardware
LIN operation.
Timer RA Set the timer to stop counting
TSTART bit in TRACR register ← 0
Hardware LIN Set the LIN operation to stop
LIN E bit in the LINC R register ← 0
R8C/2E Group, R8C/2F Group 16. Hardware LIN
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16.5 Interrupt Requests
There are four interrupt requests that are generated by the hardware LIN: Synch Break detection, Synch Break
generation completed, Synch Field measurement completed, and bus collision detection. These interrupts are
shared with timer RA.
Table 16.2 lists the Interrupt Requests of Hardware LIN.
Table 16.2 Interrupt Requests of Hardware LIN
Interrupt Request Status Flag Cause of Interrupt
Synch Break detection
SBDCT
Generated when timer RA has underflowed after measuring
the “L” level duration of RXD0 input, or when a “L” level is
input for a duration longer than the Synch Break period du ring
communication.
Synch Break generation
completed Generated when “L” level output to TXD0 for the duration set
by timer RA completes.
Synch Field measurement
completed SFDCT Generated when m easurement for 6 bits of the Synch Field by
timer RA is completed.
Bus collision detection BCDCT Generated when the RXD0 input and TXD0 output values
differed at data latch timing while UART0 is enabled for
transmission.
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17. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive coupling
amplifier. The analog input shares pins P0_0 to P0_7, and P1_0 to P1_3. Therefore, when using these pins, ensure that
the corresponding port direction bits are set to 0 (input mode).
When not using the A/D converter, set the VCUT bit in the ADCON1 register to 0 (Vref unconnected) so that no
current will flow from the VREF pin into the resisto r ladder. This helps to reduce the power consumption of the chip.
The result of A/D conversion is stored in the AD register.
Table 17.1 lists the Performance of A/D converter. Figure 17.1 shows a Block Diagram of A/D Converter.
Figures 17.2 and 17.3 show the A/D converter-related registers.
NOTES:
1. The analog input voltage does not depend on use of a sample and hold function.
When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh
in 10-bit mode and FFh in 8-bit mode.
2. When 2.7 V ≤ AVCC ≤ 5.5 V, the frequency of φAD must be 10 MHz or below.
Without a sample and hold function, the φAD frequency should be 250 kHz or above.
With a sample and hold function, the φAD frequency should be 1 MHz or above.
3. In repeat mode, only 8-bit mode can be used.
Table 17.1 Performance of A/D converter
Item Performance
A/D conversion meth od Success ive ap p roxim ation (with capacitive coupling amplifier)
Analog input voltage(1) 0 V to AVCC
Operating clock φAD(2) 4.2 V ≤ AVCC ≤ 5.5 V f1, f2, f4, fOCO-F
2.7 V ≤ AVCC < 4.2 V f2, f4, fOCO-F
Resolution 8 bits or 10 bits selectable
Absolute accuracy AVCC = Vref = 5 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±3 LSB
AVCC = Vref = 3.3 V, φAD = 10 MHz
• 8-bit resolution ±2 LSB
• 10-bit resolution ±5 LSB
Operating mode One-shot and repeat(3)
Analog input pin 12 pins (AN0 to AN11)
A/D conversion start condition Software trigger
Set the ADST bit in the ADCON0 register to 1 (A/D conversion starts)
Conversion rate per pin •Without sample and hold function
8-bit resolution: 49φAD cycles, 10-bit resolution: 59φAD cycles
• With sample and hold function
8-bit resolution: 28φAD cycles, 10-bit resolution: 33φAD cycles
R8C/2E Group, R8C/2F Group 17. A/D Converter
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Figure 17.1 Block Diagram of A/D Converter
Comparator
AVSS
Data bus
Resistor ladder
VCUT = 0
VCUT = 1
VREF
Successive conversion register
AD register
ADCON0
Vcom
VIN
P1_0/AN8
P1_1/AN9
P1_2/AN10
P1_3/AN11
ADGSEL0 = 1
CH0 to CH2, ADGSEL0, CKS0: Bits in ADCON0 register
CKS1, VCUT: Bits in ADCON1 register
ADGSEL0 = 0
P0_7/AN0 CH2 to CH0 = 000b
P0_6/AN1
P0_5/AN2
P0_4/AN3
P0_3/AN4
P0_2/AN5
P0_1/AN6
P0_0/AN7
Decoder
CKS0 = 1 CKS1 = 1
CKS1 = 0
φAD
A/D conversion rate selection
CKS0 = 0
f2
f4
fOCO-F
f1
CKS0 = 1
CKS0 = 0
CH2 to CH0 = 001b
CH2 to CH0 = 010b
CH2 to CH0 = 011b
CH2 to CH0 = 100b
CH2 to CH0 = 101b
CH2 to CH0 = 110b
CH2 to CH0 = 111b
CH2 to CH0 = 100b
CH2 to CH0 = 101b
CH2 to CH0 = 110b
CH2 to CH0 = 111b
R8C/2E Group, R8C/2F Group 17. A/D Converter
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Figure 17.2 ADCON0 Register
A/ D Co ntr ol Re giste r 0 (1)
Symbol Address After Reset
ADCON0 00D6h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4. ADGSEL0 = 0 ADGSEL0 = 1
AN0
AN1
AN2
AN3
AN4 AN8
AN5 AN9
AN6 AN10
AN7 AN11
b0b3 b2 b1
MD A/D operati ng mode select
bit(2)
b7 b6 b5 b4
0
CH2 RW
Analog input pin sele ct bi ts (Note 4)
0 : O ne-shot mode
1 : Repeat mode RW
RW
ADGSEL0 RW
A/D input group select bit(4) 0 : Sele cts port P0 group (AN0 to AN7)
1 : Selects port P1 group (AN8 to AN11)
CH1 RW
CH0
—
(b5) Reserved bi t Set to 0. RW
ADST A/D conversion start flag 0 : Stops A/D conversion
1 : Starts A/D conversion RW
Set øAD frequency to 10 MHz or below.
The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit.
CKS0
Frequency select bit 0 [When CKS1 in ADCON1 register = 0]
0 : Select f4
1 : Select f2
[When CKS1 in ADCON1 register = 1]
0 : Select f1(3)
1 : Select fOCO-F
RW
If the ADCO N0 register i s rewritten during A/D conversion, the conversion resul t is undefined.
When changing A/D operation mode, set the analog input pin again.
CH2 to CH0
000b Do not set.
001b
010b
011b
100b
101b
110b
111b
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Figure 17.3 Registers ADC ON1, ADCON2, and AD
A/ D Co ntr ol Re gist e r 1 (1)
Symbol Address After Reset
ADCON1 00D7h 00h
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2.
3. Set the B ITS bit to 0 (8-bit mode) in repeat mode.
Reserved bits Set to 0.
8/10-bit mode select bit(2) 0 : 8-bi t mode
1 : 10-bit mode
RW
S e t to 0 .
Frequency select bit 1
BITS RW
If the ADCO N1 register is rewritten during A/D conversion, the conversion resul t is undefined.
CKS1 RW
RW
RW
—
(b6-b7) Reserved bits
VREF connect bit(3) 0 : VREF not connected
1 : VREF connected
—
(b2-b0)
00 0
b7 b6 b5 b4
When the VCUT bi t is set to 1 (connected) from 0 (not connected), wait for 1 µs or more before starti n g
A/D conversion.
b3 b2
VCUT
b1 b0
00
Refer to the description of the CKS0 bit in the
ADCON0 register function.
A/ D Co ntro l Reg i ster 2(1)
Symbol Address After Reset
ADCON2 00D4h 00h
Bit Symbol Bi t Name Function RW
NOTE:
1.
0 : Without sampl e and hold
1 : With sample and hold RW
If the ADCO N2 register is rew ri tten during A/D conversi on , the conversion result i s undefined.
SMP A/D conversion method select bit
Nothing is a ssigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b4) —
—
(b3-b1) RW
Reserved bits Set to 0.
b7 b6 b5 b4 0
b3 b2 b1 b0
00
A
/D Regis te
r
Symbol Address After Reset
AD 00C1h-00C0h Undefined
Function
RO
When BITS bit in ADCON1 register is
set to 1 (10-bit mode). When BITS bit in ADCO N1 register is
set to 0 (8-bi t mode).
8 l ow-order bits i n A/D conversion result A/D conversion result
RW
RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0. —
2 hi gh-order bits in A/D conversion result When read, the content is undefined.
b0b7
(b8)
b0
(b15)
b7
R8C/2E Group, R8C/2F Group 17. A/D Converter
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17.1 One-Shot Mode
In one-shot mode, the input voltage of one selected pin is A/D converted once.
Table 17.2 lists the Specification of One-Shot Mode. Figure 17.4 shows the ADCON0 Register in One-Shot Mode
and Figure 17.5 shows the ADCON1 Register in One-Shot Mod e.
Ta b le 17 .2 Specification of On e- Sh ot Mo de
Item Specification
Function The input voltage of one pi n selected by bit s CH2 to CH0 and ADGSEL0 is
A/D converted on ce
Start condition Set the ADST bit to 1 (A/D conversion starts)
Stop condition • A/D conversion completes (ADST bit is set to 0)
• Set the ADST bit to 0
Interrupt request generation
timing A/D conversion completes
Input pin Select one of AN0 to AN11
Reading of A/D conversion
result Read AD register
R8C/2E Group, R8C/2F Group 17. A/D Converter
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Figure 17.4 ADCON0 Register in One-Shot Mode
A/ D Co ntr ol Re giste r 0 (1)
Symbol Address After Reset
ADCON0 00D6h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4. ADGSEL0 = 0 ADGSEL0 = 1
AN0
AN1
AN2
AN3
AN4 AN8
AN5 AN9
AN6 AN10
AN7 AN11
100b
101b
110b
111b
CH2 to CH0
000b Do not set.
001b
010b
011b
b0
0
b3 b2 b1
MD A/D operati ng mode select
bit(2)
b7 b6 b5 b4
0
CH2 RW
Analog input pin select bits (Note 4)
0 : O ne-shot mode RW
RW
ADGSEL0 RW
A/D input group select bit(4) 0 : Sele cts port P0 group (AN0 to AN7)
1 : Selects port P1 group (AN8 to AN11)
CH1 RW
CH0
—
(b5) Reserved bi t Set to 0. RW
ADST A/D conversion start flag 0 : Stops A/D conversion
1 : Starts A/D conversion RW
Set øAD frequency to 10 MHz or below.
The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit.
CKS0
Frequency select bit 0 [When CKS1 in ADCON1 register = 0]
0 : Select f4
1 : Select f2
[When CKS1 in ADCON1 register = 1]
0 : Select f1(3)
1 : Select fOCO-F
RW
If the ADCO N0 register i s rewritten during A/D conversion, the conversion resul t is undefined.
After changing the A/D operating mode, select the anal og input pin agai n .
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Figure 17.5 ADCON1 Register in One-Shot Mode
A/ D Co ntro l Re gi st e r 1(1)
Symbol Address After Reset
ADCON1 00D7h 00h
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2. When the VCUT bit is set to 1 (connected) from 0 (not connected), wait for 1 µs or more before starti n g
A/D conversion.
b3 b2
VCUT
b1 b0
00
Refer to the description of the CKS0 bit in the
ADCON0 register function.
b7 b6 b5 b4
—
(b2-b0)
001 0
BITS RW
If the ADCO N1 register is rewritten duri ng A/D conversion, the conversion result is undefined.
CKS1 RW
RW
RW
—
(b6-b7) Reserved bits
VREF connect bit(2)
RW
S e t to 0 .
Frequency select bit 1
1 : VREF connected
Reserved bits Set to 0.
8/10-bit mode sele ct bi t 0 : 8-bi t mode
1 : 10-bit mode
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17.2 Repeat Mode
In repeat mode, the input voltage of one selected pin is A/D converted repeatedly.
Table 17.3 lists the Repeat Mode Specifications. Figure 17.6 shows the ADCON0 Register in Repeat Mode and
Figure 17.7 shows ADCON1 Register in Repeat Mode.
Table 17.3 Repeat Mode Specifications
Item Specification
Function The Input voltage of one pin select ed by bit s CH2 to CH0 and ADGSEL0 is
A/D converted re pe at ed ly
Start conditions Set the ADST bit to 1 (A/D conversion starts)
Stop condition Set the ADST bit to 0
Interrupt request generation
timing Not generated
Input pin S elect one of AN0 to AN11
Reading of result of A/D
converter Read AD register
R8C/2E Group, R8C/2F Group 17. A/D Converter
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Figure 17.6 ADCON0 Register in Repeat Mode
A/ D Co ntr ol Re gist e r 0 (1)
Symbol Address After Reset
ADCON0 00D6h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4. ADGSEL0 = 0 ADGSEL0 = 1
AN0
AN1
AN2
AN3
AN4 AN8
AN5 AN9
AN6 AN10
AN7 AN11
b0
1
b3 b2 b1
MD A/D operati ng mode select
bit(2)
b7 b6 b5 b4
0
CH2 RW
Analog input pin sele ct bi ts (Note 4)
1 : Repeat mode RW
RW
ADGSEL0 RW
A/D input group select bit(4) 0 : Sele cts port P0 group (AN0 to AN7)
1 : Selects port P1 group (AN8 to AN11)
CH1 RW
CH0
—
(b5) Reserved bi t Set to 0. RW
ADST A/D conversion start flag 0 : Stops A/D conversion
1 : Starts A/D conversion RW
Set øAD frequency to 10 MHz or below.
The analog input pin can be selected according to a combination of bits CH0 to CH2 and the ADGSEL0 bit.
CKS0
Frequency select bit 0 [When CKS1 in ADCON1 register = 0]
0 : Select f4
1 : Select f2
[When CKS1 in ADCON1 register = 1]
0 : Select f1(3)
1 : Do not set.
RW
If the ADCO N0 register i s rewritten during A/D conversion, the conversion resul t is undefined.
After changing A/D operati on mode, select the analog input pin agai n.
CH2 to CH0
000b Do not set.
001b
010b
011b
100b
101b
110b
111b
R8C/2E Group, R8C/2F Group 17. A/D Converter
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Figure 17.7 ADCON1 Register in Repeat Mode
A/ D Co ntro l Re gi st e r 1 (1)
Symbol Address After Reset
ADCON1 00D7h 00h
Bit Symbol Bit Name Functi on RW
NOTES:
1.
2.
3. Set the B ITS bit to 0 (8-bit mode) in repeat mode.
VREF connect bit(3) 1 : VREF connected
Reserved bits Set to 0.
8/10-bit mode select bit(2) 0 : 8-bi t mode
RW
S e t to 0 .
Frequency select bit 1
BITS RW
If the ADCO N1 register is rewritten duri ng A/D conversion, the conversion result is undefined.
CKS1 RW
RW
RW
—
(b6-b7) Reserved bits
—
(b2-b0)
001 0
b7 b6 b5 b4
When the VCUT bi t is set to 1 (connected) from 0 (not connected), wait for 1 µs or more b efore startin g
A/D conversion.
b3 b2
VCUT
b1 b0
000
Refer to the de scription of the CKS0 bit in the
ADCON0 register function.
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17.3 Sample and Hold
When the SMP bit in the ADCON2 register is set to 1 (sample and hold function enabled), the A/D conversion rate
per pin increases. The sample and hold function is available in all oper ating modes. Start A/D conversion after
selecting whether the sample and hol d cir c uit is to be used or not.
Figure 17.8 shows a Timing Diagram of A/D Conversion .
Figure 17.8 Timing Diagram of A/D Conversion
17.4 A/D Conversion Cycles
Figure 17.9 shows the A/D Conversion Cycles.
Figure 17.9 A/D Conversion Cycles
Sampling time
4ø AD cycles
Sample and hold
disabled Conversion time of 1st bit 2nd bit
Comparison
time Sampling time
2.5ø AD cycles Comparison
time Sampling time
2.5ø AD cycles Comparison
time
* Repeat until conversion ends
Sampling time
4ø AD cycles
Sample and hold
enabled Conversion time of 1st bit 2nd bit
Comparison
time Comparison
time Comparison
time
* Repeat until conversion ends
Comparison
time
A/D Conversion Mode
Without Sample & Hold
Without Sample & Hold
With Sample & Hold
With Sample & Hold
8 bits
10 bits
8 bits
10 bits
Conversion
Time Comparison
Time Comparison
Time End process
Sampling
Time
End processConversion time at the 1st bit
Sampling
Time
Conversi on t i me at t he 2nd
bit and the follows
49φAD 4φAD 2.0φAD 2.5φAD 2.5φAD 8.0φAD
59φAD 4φAD 2.0φAD 2.5φAD 2.5φAD 8.0φAD
28φAD 4φAD 2.5φAD 0.0φAD 2.5φAD 4.0φAD
33φAD 4φAD 2.5φAD 0.0φAD 2.5φAD 4.0φAD
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17.5 Internal Equivalent Circuit of Analog Input
Figure 17.10 shows the Intern al Equival e nt Circuit of Anal og Input.
Figure 17.10 Internal Equivalent Circuit of Analog Input
VCC
Parasitic Diode
Chopper-type
Amplifier
A/D Successive
Conversion Register
Comparison
voltage
b1b2 b0
VCC VSS
AN0
VSS
i=12
AN11
VREF
AVSS
Vref
Comparison reference voltage
(Vref) generator
SW1 SW2
AVCC
AMP
SW3
AVSS
VIN
SW4
SW5
SW1
Parasitic Diode ON Re sistor
Approx. 2kΩWiring Resistor
Approx. 0.2kΩ
ON Resistor
Approx. 0.6kΩ
ON R e sistor
Approx. 2kΩWiring Resistor
Approx. 0.2kΩ
i Ladder-type
Switches
A/D Control Reg is ter 0
ON Resistor
Approx. 0.6k f
Analog Input
Voltage
Sampling
Control Signal
ON Resistor
Approx. 5kΩ
C = Approx.1.5pF
A/D Conversion
Interrupt Request
SW1 conducts only on the ports selected for analog input.
SW2 and SW3 are open when A/D conversion is not in progress;
their st atus varies as shown by t h e wav e f o rm s i n t h e di ag ra m s on t h e le f t.
SW4 conducts only when A/D conversion is not in progress.
SW5 conducts when compare operation is in progress.
Control signal
for SW2
Control signal
for SW3
Sampling Comparison
Connect to
C onnect to
Connect to
Connect to
NOTE:
1. Use only as a standard for designing this data.
Mass production may cause some changes in device characteristics.
i Ladder-type
W iring Resistors
Resistor
ladder
Reference
Control Signal
b4
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17.6 Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 17.11 has to be completed
within a specified period of time. T (sampling time) as the specified time. Let output impedance of sensor
equivalent circuit be R0, internal resistance of microcomputer be R, precision (error) of the A/D converter be X,
and the resolution of A/D converter be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit m ode).
VC is generally
And when t = T,
Hence,
Figure 17.11 shows Analog Input Pin and External Sensor Equivalent Circuit. When the difference between VIN
and VC becomes 0.1LSB, we find impedance R0 when voltage between pins VC changes from 0 to VIN-
(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision drop due to insufficient capacitor charge is held to
0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is the value of absolute precision
added to 0.1LSB.
When f(XIN) = 10 MHz, T = 0.25 µs in the A/D conversion mode without sample and hold. Output impedance R0
for sufficiently charging capacitor C within time T is determined as follows.
T = 0.25 µs, R = 2.8 kΩ, C = 6.0 pF, X = 0.1, and Y = 1024. Hence,
Thus, the allowable output impedance of the sensor equivalent circuit, making the precision (error) 0.1LSB or less,
is approximately 1.7 kΩ. maximum.
Figure 17.11 Analog Input Pin and External Sensor Equivalent Circuit
R0 R ( 2.8 kΩ)
C (6.0 pF)
VIN
VC
MCU
Sensor equivalent
circuit
NOTE:
1. The capacity of the terminal is assumed to be 4.5 pF.
R0 T
CX
Y
----ln•
-------------------–R–=
1
CR0 R+()
--------------------------–T
X
Y
----ln=
e 1
CR0 R+()
-------------------------- T–X
Y
----=
VC VIN X
Y
---- VIN VIN 1 X
Y
----–
=–=
VC VIN 1e 1
CR0 R+()
--------------------------– t
–
=
R0 0.25 10 6–
×
6.0 10 12–0.1
1024
------------ln•×
---------------------------------------------------–=2.8
3
×10–1.7 3
×10≈
R8C/2E Group, R8C/2F Group 17. A/D Converter
Rev.1.00 Dec 14, 2007 Page 252 of 332
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17.7 Notes on A/D Converter
•Write to each bit (other than bit 6) in the ADCON0 register, each b it in the ADCON1 register, or the SMP bit
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
•After changing the A/D operatin g mode, select an analog input pin again.
•When using the one-shot mode, ensure that A/D conversion is com pleted before reading the AD register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
•When using the repeat mode, select t he frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion .
Do not select the fOCO-F for the φAD.
•If the ADST bit in the ADCON0 register is set to 0 (A/D conv ersion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.
•Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.
•Do not enter stop mode during A/D conversion.
•Do not enter wait mode when the CM02 bi t in the CM0 regi ster is set to 1 (peripheral function clock stops in
wait mode) during A/D conversi on.
R8C/2E Group, R8C/2F Group 18. D/A Converter
Rev.1.00 Dec 14, 2007 Page 253 of 332
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18. D/A Converter
The D/A converters are 8-bit R-2R type uni ts. The D/A converter 0 and D/A converter 1 are two independent D/A
converters.
D/A conversion is performed by writing to the DAi register (i = 0 or 1). To out put the conversion result, set the DAiE
bit in the DACON register to 1 (output enabled) and set the VRiSEL bit in the ACCRi register to 0 (AVREFi pin
input). Before using D/A conversion, the corresponding port direction bit must be set to 0 (input mode). Setting the
DAiE bit to 1 removes the pull-up from the corresponding port.
The output analog voltage (V) is determined by the setting value n (n: decimal) of the DAi register.
V = Vref × n/256 (n = 0 to 255)
Vref: Reference voltage
Table 18.1 lists the D/A Converter Specificati ons. Figure 18.1 shows the Block Diagram of D/A Converter. Fi gures
18.2 and 18.3 show the D/A converter related registers. Figure 18.4 shows the D/A Converter Equivalent Circuit.
Figure 18.1 Block Diagram of D/A Converter
Tab le 18 .1 D/A Converter Specificat io n s
Item Performance
D/A conversion method R-2R method
Resolution 8 bits
Analog output pins 2 (DA0 and DA1)
DA0 register
R-2R resistor ladder DA0
DA1 register
R-2R resistor ladder DA1
DA0E bit
DA1E bit
0
1
0
1
D a ta b u s
VR0SEL bit
VR1SEL bit
1
0
1
0
DA0E, DA1E: Bits in DACON register
VR0SEL: Bit in ACCR0 register
VR1SEL: Bit in ACCR1 register
R8C/2E Group, R8C/2F Group 18. D/A Converter
Rev.1.00 Dec 14, 2007 Page 254 of 332
REJ09B0349-0100
Figure 18.2 R egisters DA0 to DA1 and DACON
D/ A i Regi st er (i = 0 or 1)(1)
Symbol
DA0
DA1 Setting Range RW
NOTE:
1.
00h
When not using the D/A converter, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to
prevent current from flowing into the R-2R resistor ladder to reduce unnecessary current consumption.
Function
Output value of D/A conversion 00h to FFh RW
After Reset
00h
Address
00DAh
00D8h
b7 b0
D/A Co ntro l Reg i ster (1)
Symbol
DACON
Bit Symbol RW
NOTE:
1.
b3 b2 b1 b0b7 b6 b5 b4
RWDA0E
After Reset
00h
—
(b7-b2) —
When not using the D/A converter, set the DAiE bit (i = 0 or 1) to 0 (output disabled) and set the DAi register to 00h to
prevent current from flowing into the R-2R resistor ladder to reduce unnecessary current consumption.
Bit Name Function
0 : Output disabled
1 : Output enabled
D/A0 output enable bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
DA1E RW
0 : Output disabled
1 : Output enabled
Address
00DCh
D/A1 output enable bit
R8C/2E Group, R8C/2F Group 18. D/A Converter
Rev.1.00 Dec 14, 2007 Page 255 of 332
REJ09B0349-0100
Figure 18.3 Registers ACCR0 to ACCR1
Figure 18.4 D/A Converter Equivalent Circuit
Com parat or i Cont rol Regi st er (i = 0 or 1)
Symbol Address After Reset
ACCR0 0174h 00001000b
ACCR1 0175h 00001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
b3 b2
FLTi1
b1 b0
VRiSEL
b7 b6 b5 b4
CMiE
CMiLV RO
When setting the VRiSEL bit to 1 (D/A converter i output), set the DAiE bit in the DACON register to 1 (output
enabl e d). How ever, at this time, the D/A conversion result is not output from DAi pin.
FLTi0 RW
RW
RWCMiF
Comparator i interrupt fl ag
RW
0 : Disable i nterrupt by CMiF bit
1 : Enable interrupt by CMiF bit
CMiOE ACOUT i output enable bit 0 : Disabl e output
1 : Enable output
b5 b4
0 0 : No fi lter
0 1 : F ilter w ith f2 sampling
1 0 : F ilter w ith f8 sampling
1 1 : Filter w i th f32 sampli ng
Comparator i reference input
select bit 0 : AVREFi pin input
1 : D/A converter i o u tput(1)
Comparison result monitor flag 0 : ACMPi input < reference input
1 : AC MPi input > reference input
The w ri ting resul ts are as fol lows:
• T his bi t is set to 0 when the read result is 1 and 0 is written to the same bit.
• T his bi t remains unchanged even if the read result i s 0 and 0 i s written to the same bit. (This bit remains 1
even if it is set to 1 from 0 after reading, and writing 0.)
• T his bi t remains unchanged i f 1 i s written to it.
CMiIE
Comparator i enable operation bit 0 : Disable operation
1 : Enable operation RW
RW
RW
[Source for setti ng this bi t to 0]
Write 0 after read(2)
[Source for setti ng this bi t to 1]
When the comparison result is changed
Comparator i digital fi lter sel ect
bits
Comparator i interrupt enable bit
VREF(2)
AVSS
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
2R
DAi
MSB LSB
DAiE bit
DAi register
NOTES:
1. The above diagram applies when the value of the DAi register is 2Ah.
2. VREF is not affected by the setting of the VCUT bit in the ADCON1 register.
r
i = 0 to 1
0
0
1
1
R8C/2E Group, R8C/2F Group 19. Comparator
Rev.1.00 Dec 14, 2007 Page 256 of 332
REJ09B0349-0100
19. Comparator
The comparators compare a reference input voltage and an analog input voltage. Comparator 0 and comparator 1 are
two independent comparators.
19.1 Overview
The comparison result of the reference input voltage and analog input voltage can be read by software. The result
also can be output from the ACO UTi (i = 0 or 1) pin. An input to the AVR EFi pin or output from D/A conv erter i
can be selected as the reference input voltage.
Table 19.1 lists the Specifications for Comparator, Figure 19.1 shows the Block Diagram of Comparator, and Table
19.2 lists the I/O Pins.
i = 0 or 1
Figure 19.1 Block Diagram of Comparator
Tab le 19 .1 Specifications for Comparator
Item Specification
Analog input voltage Input voltage to ACMPi pin
Reference input voltage Input voltage to AVREFi pin or output voltage of D/A converter i
Comparison result Read the CMiLV bit in the ACCRi register
Interrupt request
generation timing When the comparison result changes
Select functions • The comparison result can be output from the ACOUTi pin.
• ACOUTi pin output polarity
Whether the comparison result output is inverted or not inverted can be
selected.
• Digital filter function
For the CMACOUTi signal (comparison result), whether the digital filter is
applied or not and the sampling frequency can be selected.
+
-
FLT01 to FLT00
= 01b
= 10b
= 11b
Pin output
select circuit
CM0E, CM0OE, VR0SEL, CM0LV, FLT00 to FLT01: Bits in ACCR0 register
CM1E, CM1OE, VR1SEL, CM1LV, FLT10 to FLT11: Bits in ACCR1 register
CM0POR, CM1POR: Bits in ACMR register
DA0E, DA1E: Bits in DACON register
CMACOUT0 signal, CMACOUT1 signal: Internal signal
f2
f8
f32
AVREF0
VR0SEL
ACMP0 0
1
CM0E
Digital filter ACOUT0
+
-
FLT11 to FLT10
= 01b
= 10b
= 11b
f2
f8
f32
AVREF1
VR1SEL
ACMP1 0
1
CM1E
Digital filter ACOUT1
CM0POR
CM1POR
0
1
DA0E
0
1DA1E
VR1SEL
DA1
DA0 D/A Converter 0
D/A Converter 1
VR0SEL
Interrupt control
circuit
Comparator 0
interrupt request
0
1
CM0OE
0
1
CM1OE
Comparator 1
interrupt request
0
1
0
1
= other than 00b
= 00b
= other than 00b
= 00b
Sampling clock
CM0LV
CMACOUT0
signal
CMACOUT1
signal
1
0
1
0
CM1LV
Sampling clock
R8C/2E Group, R8C/2F Group 19. Comparator
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REJ09B0349-0100
Ta ble 19 .2 I/O Pins
Pin Name I/O Function
ACMP0 Input Comparator 0 analog pin
AVREF0 Input Comparator 0 reference voltage pin
ACOUT0 Output Comparator 0 comparison result output pin
ACMP1 Input Comparator 1 analog pin
AVREF1 Input Comparator 1 reference voltage pin
ACOUT1 Output Comparator 1 comparison result output pin
R8C/2E Group, R8C/2F Group 19. Comparator
Rev.1.00 Dec 14, 2007 Page 258 of 332
REJ09B0349-0100
19.2 Register Functions
Figure 19.2 shows the Registers ACCR0 to ACCR1 and Figure 19.3 shows the ACMR Register.
Figure 19.2 R egisters ACCR0 to ACCR1
Com parat or i Cont rol Regi st er (i = 0 or 1)
Symbol Address After Reset
ACCR0 0174h 00001000b
ACCR1 0175h 00001000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
b3 b2
FLTi1
b1 b0
VRiSEL
b7 b6 b5 b4
CMiE
CMiLV RO
When setting the VRiSEL bit to 1 (D/A converter i output), set the DAiE bit in the DACON register to 1 (output
enabl e d). How ever, at this time, the D/A conversion result is not output from DAi pin.
FLTi0 RW
RW
RWCMiF
Comparator i interrupt fl ag
RW
0 : Disable i nterrupt by CMiF bit
1 : Enable interrupt by CMiF bit
CMiOE ACOUT i output enable bi t 0 : Disable output
1 : Enable output
b5 b4
0 0 : No fi lter
0 1 : F ilter w ith f2 sampling
1 0 : F ilter w ith f8 sampling
1 1 : F ilter w ith f32 sampling
Comparator i reference input
select bit 0 : AVREFi pin input
1 : D/A converter i o u tput(1)
Comparison result monitor flag 0 : ACMPi input < reference input
1 : AC MPi input > reference input
The w ri ting resul ts are as fol lows:
• T his bi t is set to 0 when the read result is 1 and 0 is written to the same bit.
• T his bi t remains unchanged even if the read result i s 0 and 0 i s written to the same bit. (This bit remains 1
even if it is set to 1 from 0 after reading, and writing 0.)
• T his bi t remains unchanged i f 1 i s written to it.
CMiIE
Comparator i enable operation bit 0 : Di sable operati on
1 : Enable operation RW
RW
RW
[Source for setti ng this bi t to 0]
Write 0 after read(2)
[Source for setti ng this bi t to 1]
When the comparison result is changed
Comparator i digital fi lter sel ect
bits
Comparator i interrupt enable bit
R8C/2E Group, R8C/2F Group 19. Comparator
Rev.1.00 Dec 14, 2007 Page 259 of 332
REJ09B0349-0100
Figure 19.3 ACMR Register
Com parat or M ode Regi ster
Symbol Address After Reset
ACMR 0177h 00h
Bit Symbol Bit Name Function RW
Nothin g is assi gn ed. If necessary, set to 0.
When read, the content is 0.
Nothin g is assi gn ed. If necessary, set to 0.
When read, the content is 0.
Reserved bits Set to 0.
Set to 0. RW
ACOUT0 output polarity select bit 0 : Output the non-inverted comparator 0
comparison result to ACOUT 0
1 : O utput the inverted comparator 0
comparison result to ACOUT 0
ACOUT1 output polarity select bit 0 : Output the non-inverted comparator 1
comparison result to ACOUT 1
1 : O utput the inverted comparator 1
comparison result to ACOUT 1
CM0POR RW
RW
—
-
(b3) —
-
(b6-b4) RW
CM1POR
Reserved bi t
000
b7 b6 b5 b4 b3 b2
-
(b7)
b1 b0
0
-
(b2)
R8C/2E Group, R8C/2F Group 19. Comparator
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19.3 Functional Description
Comparator 0 and comparator 1 operate independently. Their operations are the same.
Table 19.3 lists the Procedure for Setting Registers Associated with Comparator
i = 0 or 1
Table 19.3 Procedure for Setting Registers Associated with Comparator
Step Register Bit Setting Value
1 Function selection of ACMPi, AVREFi, and ACOUTi pin. Refer to 7.4 Port Setting.
Set registers and bits other than listed in step 2 and the following steps.
2 ACMR CMiPOR When using the ACOUTi output: Select the ACOUTi output polarity.
3 ACCRi FLTi1 to FLTi0 Select to en able or disable the filter, and select the sampling clock
frequency.
VRiSEL Select the reference inpu t.
4 DACON DAiE When setting the D/A converter i output voltage to refer ence
voltage: 1 (D/A output enabled )
5 ACCRi CMiE 1 (operation enabled)
6 Wait until comparator stability time (max. 10 µs)
7 ACCRi CMiF Read (dummy read to initialize the interrupt flag)
8 ACCRi CMiOE When using the ACOUTi output: 1 (ACOUTi output enabled)
CMiIE When using interrupts: 1 (interrupt enab led)
CMiF When using interrupts: 0 (no interrupt requested: Initialization)
9 CMiIC ILVL2 to ILVL0 When using interrupts: Select the interrupt priority level.
IR When using interrupts: 0 (no inter rupt requested: Initialization)
R8C/2E Group, R8C/2F Group 19. Comparator
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Figure 19.4 shows an Operating Example of Comparato r i (i = 0 or 1).
If the analog input voltage is higher than the reference input voltage, the CMiLV bit in the ACCRi register is set
to 1. If the analog input voltage is lower than the reference input voltage, the CMiLV bit is set to 0. When the
comparison result changes, the CMiF bit in the ACCRi register is set to 1. If the value of the CMiIE bit in the
ACCRi register is 1 (interrupt by CMiF bit enabled) at this time, a comparator i interrupt request is generated.
Refer to 19.4 Comparator 0 Interrupt and Com parator 1 Interrupt for information of interrupts.
Figure 19.4 Operating Example of Comparator i (i = 0 or 1)
19.3.1 Comparison Result Output
When the CMiOE bit in the ACCRi register is set to 1 (output enabled), the comparison result can be output
from the ACOUT i pin. Also, the CMiPOR bit in the ACMR register can be used to select whether the ACOUTi
pin output polarity is inverted or not inverted.
0
Analog input voltage (V)
CMiLV bit in
ACCRi register 1
0
ACOUTi output
(when CMiPOR bit
in ACMR register
is set to 0)
1
0
The above applies under the following conditions:
CMiOE bit in the ACCRi register = 1 (output enabled)
Bits FLTi1 to FLTi0 in the ACCRi register = 00b (no filter)
CMiPOR bit in the ACMR register = 0 (non-inverted comparator i compare result output to ACOUTi)
CMiPOR bit in the ACMR register = 1 (inverted comparator i comp are result output to ACOUTi)
i = 0 or 1
Reference input voltage
1
0
CMiF bit in
ACCRi register
Set to 0 by a program
ACOUTi output
(when CMiPOR bit
in ACMR register
is set to 1)
1
0
R8C/2E Group, R8C/2F Group 19. Comparator
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19.3.2 Digital Filter
The digital filter can be applied to the CMACOU Ti (i = 0 or1) signal.
The CMACOUTi signal is sampled, and the level is considered to be determined when two matches occur. The
digital filter function and sampling frequ e ncy are selected usin g bits FLTi0 to FLTi1 in the ACCRi register.
Figure 19.5 shows a Block Diagram of Digital Filter.
Figure 19.5 Block Diagram of Digital Filter
C
DQ
Latch
C
DQ
Latch
Match
detect
circuit
Sampling clock
FLTi1 to FLT i 0
CMACOUTi
signal
Clock cycle selected by
FLTi1 to FLTi0
Sampling clock
CMACOUTi
signal
Input signal after passing
through digital filter
If fewer than two matches
occur, t h e m at ches are
treated as noise and no
transmission is performed.
Maximum signal
transmission
delay is 2.5
sampling clock
pulses.
Two matches
occur and a
signal change
is confirmed.
f2
f8
f32
FLTi0 to FLTi1: Bits in ACCRi register
i = 0 or 1
= 01b
= 10b
= 11b
= 01b, 10b, 11b
= 00b
FLTi1 to FLTi 0
C
DQ
Latch
R8C/2E Group, R8C/2F Group 19. Comparator
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19.4 Comparator 0 Interrupt and Comparator 1 Interrupt
Comparator 0 and Comparator 1 generate interrupt request from two source s. The comparator i (i = 0 or 1)
interrupt uses the corresponding CMiIC register (bits IR and ILVL0 to ILVL2) and vector. When the
comparison result changes, the CMiF bit in the ACCRi register is set to 1. If the value of the CMiIE bit in the
ACCRi register is 1 (interrupt by CMiF bit enabled) at this time, a comparator i interrupt request is generated.
Table 19.4 lists the Registers and Bits Associated with Comparator Interrupt, and Figure 19.6 is a Block
Diagram of Comparator Interrupt.
i = 0 or 1
Figure 19.6 Block Diagram of Comparator Interrupt
Like other maskab le interrupts, the comparator i int errupt is controlled by the com bination of the I flag, IR bit,
bits ILVL0 to ILVL2, and IPL.
However, the exi stence of the bits CMiF and CMiIE results in the following differences from other maskable
interrupts.
•The IR bit in the CMiIC register is set to 1 (interrupt requested) when the CMiF bit in the ACCRi register
is set to 1 and the CMiIE bit in the ACCRi register is set to 1 (interrupt enabled).
•The IR bit is set to 0 (no interrupt requested) when the CMiF bit or CMiIE bit is set to 0, or both are set to
0. In other words, the interrupt request is not maintained if the IR bit is once set to 1 but the interrupt is not
acknowledged.
•The CMiF bit is not automatically set to 0 when an interrupt is acknowledged. Set it to 0 within the
interrupt routine. Refer to Figure 19.2 Registers ACCR0 to ACCR1, for the procedure for setting these
bits to 0.
Refer to 12.1.6 Interrupt Control, for deta ils of the CMiIC register and 12.1.5.2 Relocatable Vector Tables,
for information on interrupt vectors.
Tab le 19 .4 Registers an d Bi ts Associated with Comparator Interru p t
Comparator i Control Register,
Comparator i Interrupt Flag Comparator i Inte rrupt Control Register ,
Comparator i Interrupt Enable Bit Comparator i Interrupt
Control Register
CMiF bit in ACCRi register CMiE bit in ACCRi register CMiIC
Comparator 0 interrupt request
(IR bit in CM0IC register)
CM0F bit
CM0IE bit
CM0F, CM0IE: Bits in ACCR0 register
CM1F, CM1IE: Bits in ACCR1 register
CM1F bit
CM1IE bit Comparator 1 interrupt request
(IR bit in CM1IC regist er)
R8C/2E Group, R8C/2F Group 20. Flash Memory Version
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REJ09B0349-0100
20. Flash Memory Version
20.1 Overview
In the flash memory, rewrite operations to the flash memory can be performed in three modes: CPU rewrite,
standard serial I/O, and parallel I/O.
Table 20.1 lists the Flash Memory Performance (refer to Ta ble 1. 1, Table 1.2, Table 1.3, and Ta ble 1. 4
Specifications for items not listed in Table 20.1).
NOTES:
1. Definition of programming and erasure endurance
The programming and erasure endurance is defined on a per-block basis. If the programming and erasure
endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are
performed to block A, a 1-Kbyte block, and then the block is erased, the erase count stands at one. When
performing 100 or more rewrites, the actual erase count can be reduced by executing programming operations
in such a way that all blank areas are used before performing an erase operation. Avoid rewriting only particular
blocks and try to average out the programming and erasure endurance of the blocks. It is also advisable to
retain data on the erase count of each block and limit the number of eras e operations to a certain number.
2. Blocks A and B are implemented only in the R8C/2F group.
3. To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
Ta b le 20 .1 Flash Memory Performance
Item Specification
Flash memory operating mode 3 modes (CPU rewrite, standa rd seria l I/O, and p a rallel I/O)
Division of erase block Refer to Figure 20.1 and Figure 20.2
Programming method Byte unit
Erase method Block er ase
Programming and erasure control method
(3) Program and erase control by software co mmand
Rewrite control method Rewrite control for blocks 0 and 1 by FMR02 bit in FMR0
register
Rewrite control fo r block 0 by FMR15 bit and block 1 by
FMR16 bit in FMR1 register
Number of commands 5 commands
Programming
and erasure
endurance(1)
Blocks 0 and 1 (program
ROM) R8C/2E Group: 100 times; R8C/2F Group: 1,000 times
Blocks A and B (dat a flash)(2) 10,000 times
ID code check function Standard serial I/O mode supported
ROM code protect Parallel I/O mode supported
Table 20.2 Flash Memory Rewrite Modes
Flash memory
Rewrite mode CPU Rewrite Mode S tandard Serial I/O
Mode Parallel I/O Mode
Function User ROM area is rewritten by executing
software commands from the CPU.
EW0 mode: Rewritable in the RAM
EW1 mode: Rewritable in flash memory
User ROM area is
rewritten by a
dedicated serial
programmer.
User ROM area is
rewritten by a
dedicated parallel
programmer.
Areas which can
be rewritten User ROM area User ROM area User ROM area
Operating mode Single chip mode Boot mode Parallel I/O mode
ROM Programmer None Serial programmer Parallel programmer
R8C/2E Group, R8C/2F Group 20. Flash Memory Version
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20.2 Memory Map
The flash memory contains a user ROM area and a boot ROM area (reserved area). Figure 20.1 shows the Flash
Memory Block Diagram for R8C/2E Group. Figure 20.2 shows a Flash Memory Block Diagram for R8C/2F
Group.
The user ROM area of the R8C/2F Group contains an area (program ROM) which stores MCU operating programs
and blocks A and B (data flash) each 1 Kbyte in size.
The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite mode and
standard serial I/O and parallel I/O modes.
When rewriting blocks 0 and 1 in CPU rewrite mode, set the FMR02 bit in the FMR0 register to 1 (rewrite
enabled). When the FMR15 bit in the FMR1 regist er is set to 0 (rewrite enab led), block 0 is rewri table. When the
FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. The boot
ROM area and the user ROM area share the same address, but have separate memory areas.
Figure 20.1 Flash Memory Block Diagram for R8C/2E Group
Boot ROM area
(reserved area)(2)
8 Kbytes
0E000h
0FFFFh
User ROM area
User ROM area
Block 0: 8 Kbytes(1)
0E000h
0FFFFh
Block 0: 8 Kbytes(1)
0C000h
0FFFFh
16 Kbyte ROM product
Program ROM
8 Kbyte ROM product
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0
(rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for
CPU rewrite mode).
2. This area is for storing the boot program provided by Renesas Technology.
0E000h
0DFFFh Block 1: 8 Kbytes(1)
R8C/2E Group, R8C/2F Group 20. Flash Memory Version
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REJ09B0349-0100
Figure 20.2 Flash Memory Block Diagram for R8C/2F Group
Boot ROM area
(reserved area)(2)
8 Kbytes
0E000h
0FFFFh
User ROM area
Block 0: 8 Kbytes(1)
0E000h
0FFFFh
User ROM area
Block 0: 8 Kbytes(1)
Block 0: 16 Kbytes(1)
0C000h
0FFFFh
Block B: 1 Kbyte
Block A: 1 Kbyte
02400h
02BFFh
16 Kbytes ROM product
Program ROM
Data flash
Block B: 1 Kbyte
Block A: 1 Kbyte
02400h
02BFFh
8 Kbytes ROM product
NOTES:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled) and the FMR15 bit in the FMR1 register is set to 0
(rewrite enabled), block 0 is rewritable. When the FMR16 bit is set to 0 (rewrite enabled), block 1 is rewritable (only for CPU
rewrite mode).
2. This area is for storing the boot program provided by Renesas Technology.
Block 1: 8 Kbytes(1)
0E000h
0DFFFh
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20.3 Functions to Prevent Rewriting of Flash Memory
Standard serial I/O mode has an ID code check function, and parallel I/O mode has a ROM code protect function to
prevent the flash memory from being read or rewritten easily.
20.3.1 ID Code Check Function
This function is used in standard serial I/O mode. Unless the flash memory is blank, the ID codes sent from the
programmer and the ID codes written in the flash memory are checked to see if they match. If the ID codes do
not match, the commands sent from the programmer are not acknowledged. The ID codes consist of 8 bits of
data each, the areas of which, beginning with the first byte, are 00FFDFh, 00FFE3h, 00FFEBh, 00FFEFh,
00FFF3h, 00FFF7h, and 00FFFBh. Write programs in which the ID codes are set at these addresses and write
them to the flash memory.
Figure 20.3 Address for Stored ID Code
4 bytes
Address
NOTE:
1. The OFS register is assigned to 00FFFFh.
Refer to Figure 20.4 OFS Register for OFS register details.
ID1
ID2
ID3
ID4
ID5
ID6
ID7
(Note 1)
Undefined instruction vector
Overflow vector
BRK instruction vector
Address match vector
Osc illatio n s top d e t e c tion/watc h do g
timer/voltage monitor 1 and voltage
monitor 2 vector
Address break
Reset vector
(Reserved)
Single step vector
00FFDFh to 00FFDCh
00FFE3h to 00FFE0h
00FFE7h to 00FFE4h
00FFEBh to 00FFE8h
00FFEFh to 00FFECh
00FFF3h to 00FFF0h
00FFF7h to 00FFF4h
00FFFBh to 00FFF8h
00FFFFh to 00FFFCh
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20.3.2 ROM Code Protect Function
The ROM code protect function disables reading or changing the contents of the on-chip flash memory by the
OFS register in parallel I/O mode. Figure 20.4 shows the OFS Register.
The ROM code protect function is enabled by writing 0 to the ROMCP1 bit and 1 to the ROMCR bit. It disables
reading or changing the contents of the on-chip flash memory.
Once ROM code protect is enabled, the content in the i nternal flash memory cannot be rewritten in parallel I/O
mode. To disable ROM code protect, erase the block including the OFS register with CPU rewrite mode or
standard serial I/O mode.
Figure 20.4 OFS Register
Opti on Fu nct i on S el ect Register(1)
Symbol Address When Shipping
OFS 0FFFFh FFh(2)
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
—
(b5) Reserved bit Set to 0. RW
—
(b4) Reserved bit Set to 1. RW
b3 b2 b1 b0b7 b6 b5 b4
101
WDTON RW
Wa tchdog timer start
select bit 0 : Starts w atchdog timer automatical ly after reset
1 : W a tchdog timer i s inactive after reset
1
—
(b1) RW
Reserved bit Set to 1.
ROMCR ROM code protect
di sabled bi t 0 : ROM code protect disabled
1 : RO MCP1 enabled RW
ROMCP1 ROM code protect bit 0 : ROM code protect enabled
1 : RO M code protect disabled RW
If the block includi ng the OFS register is erased, F Fh is set to the O FS register.
—
(b6) Reserved bit Set to 1. RW
CSPROINI Count source protect
mode after reset select
bit
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset RW
The OFS register is on the flash memory. Write to the OFS register w ith a program. After writi ng is completed, do not
write additions to the OFS register.
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20.4 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the program and block erase commands onl y to blo c ks in the user ROM area.
The flash module has an erase-suspend function when an interrupt request is generated during an erase operation in
CPU rewrite mode. It performs an inter rupt process after the erase operation is halted temporarily. During erase-
suspend, the user ROM area can be read by a program.
In case an interrupt request is generated during an auto-program operation in CPU rewrite mode, the flash m odule
contains a program-suspend function which performs the interrupt process after the auto-program operation is
suspended. During program-suspend, the user ROM area can be read by a program.
CPU rewrite mode has an erase write 0 mode (EW0 mode) and an erase write 1 mode (EW1 mode). Table 20.3 lists
the Differences between EW0 Mode and EW1 Mode.
NOTE:
1. When the FMR02 bit in the FMR0 register is set to 1 (rewrite enabled), rewriting block 0 is enable d
by setting the FMR15 bit in the FMR1 register to 0 (rewrite enabled), and rewriting block 1 is
enabled by setting the FMR16 bit to 0 (rewrite enabled).
Table 20.3 Differences between EW0 Mode and EW1 Mode
Item EW0 Mo de EW1 Mode
Operating mode Single-chip mo de Single-chip mode
Areas in which a rewrite
control program can be
located
User ROM area User ROM area
Areas in which a rewrite
control program can be
executed
Necessary to transfer to any area other
than the flash memory (e.g., RAM) before
executing
Executing directly in user ROM or RAM
area possible
Areas which can be
rewritten User ROM area User ROM area
However, blocks which contain a rewrite
control program are excluded(1)
Software command
restrictions None • Program and block erase commands
Cannot be run on any block which
contains a rewrite control program
• Read status register command
Cannot be execute d
Modes after program or
erase Read status register mode Read array mode
Modes after read status
register Read status register mode Do not execute this command
CPU status during auto-
write and auto-erase Operating Hold state (I/O ports hold state before the
command is executed)
Flash memory status
detection • Read bits FMR00, FMR06, and FMR07
in the FMR0 register by a program
• Execute the read status register
command and read bits SR7, SR5, and
SR4 in the status register.
Read bits FMR00, FMR06, and FMR07 in
the FMR0 register by a program
Conditions for transition to
erase-suspend Set bits FMR40 and FMR41 in the FMR4
register to 1 by a program. The FMR40 bit in the FMR4 register is set
to 1 and the interrupt reque st of the
enabled maskable interrupt is generated
Conditions for transiti ons to
program-suspend Set bits FMR40 and FMR42 in the FMR4
register to 1 by a program. The FMR40 bit in the FMR4 register is set
to 1 and the interrupt reque st of the
enabled maskable interrupt is generated
CPU clock 5 MHz or below No restriction (on clock frequency to be
used)
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20.4.1 EW0 Mode
The MCU enters CPU rewrite mode and software commands can be acknowledged by setting the FMR01 bit in
the FMR0 register to 1 (CPU rewrite mode enabled). In this case, since the FMR11 bit in the FMR1 register is
set to 0, EW0 mode is selected.
Use software commands to control program and erase operations. The FMR0 register or the status register can
be used to determine when program and erase operations complete.
During auto-erasure, set the FMR40 bit to 1 (erase-s uspend enabled) an d the FMR41 bit to 1 (request erase -
suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read enabled) before accessing the
user ROM area. The auto-erase operation can be restarted by setting the FMR41 bit to 0 (erase restarts).
To enter program-suspend during the auto-program operation, set the FMR40 bit to 1 (suspend enabled) and the
FMR42 bit to 1 (request program-suspend). Wait for td(SR-SUS) and ensure that the FMR46 bit is set to 1 (read
enabled) before accessing the use r ROM area. The auto-pro gram operation can be restarted by settin g the
FMR42 bit to 0 (program restarts).
20.4.2 EW1 Mode
The MCU is switched to EW1 mode by settin g the FMR11 bit to 1 (EW1 mode) after set ting the FMR01 bit to
1 (CPU rewrite mode enabled).
The FMR0 register can be used to determine wh en program and erase operations complete. Do not execute
commands that use the read status register in EW1 mode.
To enable the erase-suspend function during auto-erasure, execute the block erase command after setting the
FMR40 bit to 1 (erase-suspend enabled). The interrupt to enter erase-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the block erase command is executed, the interrupt request is
acknowledged.
When an interrupt request is generated, the FMR41 bit is automatically s et to 1 (requests erase-sus pend) and the
auto-erase operation suspends. If an auto-erase operation does not complete (FMR00 bit is 0) after an interrupt
process completes, the auto-erase op erati on restarts by settin g the FMR41 bit to 0 (erasure restarts)
To enable the program-suspend function during auto-programming, execute the program command after setting
the FMR40 bit to 1 (suspend enabled). The interrupt to enter program-suspend should be in interrupt enabled
status. After waiting for td(SR-SUS) after the program command is executed, an interrupt request is
acknowledged.
When an interrupt request is generated, the FMR42 bit is automatically set to 1 (request program -suspend) and
the auto-program operation suspends. When the auto-pr ogram operatio n does not comp lete (FMR00 bit is 0)
after the interrupt process completes, the auto-program operation can be restarted by setting the FMR42 bit to 0
(programming restarts).
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Figure 20.5 shows the FMR0 Register. Figure 20.6 shows the FMR1 Re gister. Figure 20.7 shows the FMR4
Register.
20.4.2.1 FMR00 Bit
This bit indicates the operating status of the flash memory. The bits val ue is 0 during programmin g, erasure
(including suspend periods), or erase-suspend mode; otherwise, it is 1.
20.4.2.2 FMR01 Bit
The MCU is made ready to accept commands by setting the FMR01 bit to 1 (CPU rewrite mode).
20.4.2.3 FMR02 Bit
Rewriting of blocks 0 and 1 does not accept program or block erase commands if the FMR02 bit is set to 0
(rewrite disabled).
Rewriting of blocks 0 and 1 are controlled by bits FMR15 and FMR16 if the FMR02 bit is set to 1 (rewr ite
enabled).
20.4.2.4 FMSTP Bit
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Therefore, the FMSTP bit must be written to by a program transferred to the RAM.
In the following cases, set the FMSTP bit to 1:
•When flash memory access resulted in an error while erasing or programming in EW0 mode (FMR00 bit
not reset to 1 (ready))
•To provide lower consumption in high-speed on-chip oscillator mode and low-speed on-chip oscillator
mode (XIN clock stops).
Figure 20.11 shows the handling to provid e lower consum ption in high-speed on-chip oscillator mod e and low-
speed on-chip oscillator mode (XIN clock stops). Handle according to this flowchart. Note that when going to
stop or wait mode while the CPU rewrite mode is disabled, the FMR0 register does not need to be set because
the power for the flash memory is automatically turned off and is turned back on again after returning from stop
or wait mode.
20.4.2.5 FMR06 Bit
This is a read-only bit indicating the status of an auto-program operation. The bit is set to 1 when a program
error occurs; otherwise, it is cleared to 0. For details, refer to the description in 20.4.5 Full Status Check.
20.4.2.6 FMR07 Bit
This is a read-only bit indicating the status of an auto-erase operation. The bit is set to 1 when an erase error
occurs; otherwise, it is set to 0. Refer to 20.4.5 Full Status Check for details.
20.4.2.7 FMR11 Bit
Setting this bit to 1 (EW1 mode) places the MCU in EW1 mode.
20.4.2.8 FMR15 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR15 bit is set to 0 (rewrite enabled), block 0
accepts program and block erase commands.
20.4.2.9 FMR16 Bit
When the FMR02 bit is set to 1 (rewrite enabled) and the FMR16 bit is set to 0 (rewrite enabled), block 1
accepts program and block erase commands.
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20.4.2.10 FMR40 Bit
The suspend function is enabled by setting the FMR40 bit to 1 (enable).
20.4.2.11 FMR41 Bit
In EW0 mode, the MCU enters erase-suspend mode when the FMR41 bit is set to 1 by a program. The FMR41
bit is automatically set to 1 (request erase-suspend) when an interrupt request of an enabled interrupt is
generated in EW1 mode, and then the MCU enters erase-suspend mode.
Set the FMR41 bit to 0 (erase restarts) when the auto-erase operation restarts.
20.4.2.12 FMR42 Bit
In EW0 mode, the MCU enters program-suspend mode when the FMR42 bit is set to 1 by a program. The
FMR42 bit is automatically set to 1 (request program-suspend) when an interrupt request of an enabled
interrupt is generated in EW1 mode, and then the MCU enters program-suspend mode.
Set the FMR42 bit to 0 (program restart) when the auto-program operation restarts.
20.4.2.13 FMR43 Bit
When the auto-erase operation starts, the FMR43 bit is set to 1 (erase execution in progress). The FMR43 bit
remains set to 1 (erase execution in progress) during erase-suspend operation.
When the auto-erase operation ends, the FMR43 bit is set to 0 (erase not executed).
20.4.2.14 FMR44 Bit
When the auto-program operation starts, the FMR44 bit is set to 1 (program execution in progress). The FMR44
bit remains set to 1 (program execution in progress) during program-suspend operation.
When the auto-program operation ends, the FMR44 bit is set to 0 (program not executed).
20.4.2.15 FMR46 Bit
The FMR46 bit is set to 0 (reading disabled) d uring auto -prog ram or auto- erase execution and set to 1 (reading
enabled) in suspend mode. Do not access the fl ash memory while this bit is set to 0.
20.4.2.16 FMR47 Bit
Power consumption wh en reading the flash memory can be reduced by setting the FMR47 bit to 1 (enabled) in
low-speed on-chip oscillator mode (XIN clock stops).
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Figure 20.5 FMR0 Register
F l ash M em ory Control Regi ster 0
Symbol Address After Reset
FMR0 01B7h 00000001b
Bit Symbol Bit Name Function RW
RY/BY
_
___ status flag
NOTES:
1.
2.
3.
4.
5.
6. When setting the FMR01 bit to 0 (CPU rewrite mode disabl ed), the F MR02 bit i s set to 0 (disables rewrite).
FMR07
b3 b2 b1 b0
0 : Disables rew rite
1 : Enables rewrite
Flash memory stop bit(3, 5) 0 : Enables flash memory operation
1 : S tops flash memory
(enters l ow-power consumption state
and flash memory is reset)
FMR01
Blocks 0, 1 rewrite enable bit(2, 6)
0 : B u sy (writing or erasing in progress)
1 : Ready
CPU rewrite mode select bit(1) 0 : CPU rewrite mode disabl ed
1 : CPU rewrite mode enabled
00
b7 b6 b5 b4
Reserved bits Set to 0.
RW
FMR02 RW
RW
—
(b5-b4)
FMR00
FMSTP
RW
RO
RO
RO
This bit is set to 0 by executing the clear status command.
This bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled). When the FMR01 bit is set to 0,
writing 1 to the FMSTP bit causes the FMSTP bit to be set to 1. The fl ash memory does not enter low-power
consumption state nor is it reset.
FMR06
To set this bit to 1, set i t to 1 i mmediately after setti ng it first to 0. Do not generate an interrupt between setting the bit
to 0 and setting it to 1. Enter read array mode and set this bit to 0.
Set this bit to 1 immediately after setting it first to 0 while the FMR01 bit is set to 1.
Do not generate an interrupt between setting the bit to 0 and setting it to 1.
Set this bit by a program transferred to the RAM.
Program status fl ag(4) 0 : Complet ed successfully
1 : Terminated by error
Erase status flag(4) 0 : Comp let ed success fully
1 : Terminated by error
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Figure 20.6 FMR1 Register
F l ash M em ory Cont ro l Register 1
Symbol Address After Reset
FMR1 01B5h 1000000Xb
Bit Symbol Bi t Name Function RW
NOTES:
1.
2.
3.
FMR16 Block 1 rewrite disable bit(2,3)
To set this bi t to 1, set it to 1 i mmedi ately after setting it first to 0 while the FMR01 bit is set to 1 (CPU rewrite mode
enabl e) . Do not generate an interrupt between setting the bit to 0 and setting it to 1.
This bit is set to 0 by setting the FMR01 bit in the FMR0 register to 0 (CPU rew ri te mode di sabled).
Reserved bit S et to 1.
When the FMR01 bit is set to 1 (CPU rewrite mode enabled), bits FMR15 and FMR16 can be written to.
To set this bit to 0, set it to 0 immediately after setti n g it first to 1.
To set this bi t to 1, set it to 1.
—
(b7)
0
RW
RW
RW
RO
RW
Reserved bi t
0 : Enables rewrite
1 : Disables rew ri te
RW
FMR15
—
(b0)
Reserved bits
When read, the content is undefined.
EW1 mode select bit(1, 2) 0 : EW0 mode
1 : EW1 mode
Block 0 rew rite disable bi t(2,3) 0 : Enabl es rew rite
1 : Disables rew ri te
b7 b6 b5 b4
10
b3 b2
S e t to 0 .
0b1 b0
FMR11
—
(b4-b2)
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Figure 20.7 FMR4 Register
F l ash M em ory Control Regi ster 4
Symbol Address After Reset
FMR4 01B3h 01000000b
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3.
4.
5. Set the FMR01 bi t in the FMR0 regi ster to 0 (CPU rewrite mode disabl ed) in low-power consumption read mode.
To set this bit to 1, set i t to 1 i mmediately after setti ng it first to 0. Do not generate an interrupt between setting the bit
to 0 and setti ng it to 1.
This bi t is enabled w hen the FMR40 bit is set to 1 (enable) and it can be written to during the period between issuing
an erase command and completing the erase. (This bit is set to 0 during periods other than the above.)
In EW0 mode, it can be set to 0 or 1 by a program.
In EW1 mode, i t is automatically set to 1 if a maskable interrupt i s generated duri ng an erase
operation while the F MR40 bit i s set to 1. Do not set this bit to 1 by a program (0 can be written).
b3 b2
S e t to 0 .
b1 b0
FMR41
—
(b5)
0
FMR40
FMR42
b7 b6 b5 b4
RW
RW
Erase-suspend function
enable bit(1)
0 : Disabl es reading
1 : Enables readi ng
Reserved bit
0 : Disabl e
1 : Enable
Erase-suspend request bit(2) 0 : Erase restart
1 : Erase-suspend request
RO
ROFMR46
Program-suspend request bit(3) 0 : Program restart
1 : Program-suspend request RW
FMR43 Erase command flag 0 : Erase not executed
1 : Erase execution i n progress RO
FMR44
In high-speed cl o ck mode and high-speed on-chip oscillator mode, set the FMR47 bit to 0 (disabled).
Program command flag 0 : Program not executed
1 : Program executi on in progress RO
The F MR42 bit i s enabl ed only when the FMR40 bit i s set to 1 (enable) and programming to the FMR42 bit is enabl ed
unti l auto-programming ends after a program command is generated. (T his bi t is set to 0 duri ng periods other than the
above.)
In EW0 mode, 0 or 1 can be programmed to the FMR42 bit by a program.
In EW1 mode, the FMR42 bit is automatically set to 1 by generating a maskable interrupt during auto-programming
when the FMR40 bit is set to 1. 1 cannot be written to the FMR42 bit by a program.
FMR47
Read status flag
RW
Low-pow er consumption read
mode enable bit (1, 4, 5) 0 : Disabl e
1 : Enable
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Figure 20.8 shows the Timing of Suspend Operation.
Figure 20.8 Timing of Suspend Operation
FMR00 bit in
FMR0 register
FMR46 bit in
FMR4 register
FMR44 bit in
FMR4 register
FMR43 bit in
FMR4 register
1
0
1
0
1
0
1
0
Erasure
starts Erasure
suspends Programming
starts Programming
suspends Programming
restarts Programming
ends
During erasure During programm ing During programm ing
Erasure
restarts Erasure
ends
During erasure
Check that the
FMR43 bit is set to 1
(during erase
execution), and that
the erase-operati on
has not ended.
Check that the
FMR44 bit is se t t o 1
(during program
execution), and that
the program has not
ended.
Check the status,
and that the
programming ends
normally.
Check the status,
and that the
erasure ends
normally.
Remains 0 during su s pend
Remains 1 during su s pend
NOTE:
1. If program-suspend is entered during erase-suspend, always restart programming.
The above figure shows an example of the use of program-suspend during programming following erase-suspend.
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Figure 20.9 shows How to Set and Exit EW0 Mode. Figure 20.10 shows How to Set and Exit EW1 Mode.
Figure 20.9 How to Set and Exit EW0 Mode
Figure 20.10 How to Set and Exit EW1 Mode
Set registers(1) CM0 and CM1
Transfer a rewrite control program which uses CPU
rewrite mode to the RAM.
Jump to the rewrite control program which has been
transferred to the RAM.
(The subsequent process is executed by the rewrite
control program in the RAM.)
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)(2)
Execute the read array command(3)
Execute software commands
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Jump to a s pe c ified address in the flash memory
Rewrite control program
NOTES:
1. Select 5 MHz or below for the CPU clock by the CM06 bit in the CM0 register and bits CM16 to CM17 in the CM1 register.
2. To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1. Do not generate an interrupt between writing 0 and 1.
Write to the FMR01 bit in the RAM.
3. Disable the CPU rewri te mode after executing the read array command.
EW0 Mode Operating Procedure
Write 0 to the FMR01 bit before writing 1 (CPU
rewrite mode enabled)(1)
Write 0 to the FMR11 bit before writing 1 (EW1
mode)
Execute software co mm a nds
Write 0 to the FMR01 bit
(CPU rew rite mode disabled)
NOTE:
1.To set the FMR01 bit to 1, write 0 to the FMR01 bit before writing 1.
Do not generate an interrupt between writing 0 and 1.
EW1 Mode Operating Procedure
Program in ROM
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Figure 20.11 Process to Reduce Power Consumption in High -Speed On-Chip Oscillator Mode and
Low-Speed On-Chip Oscillator Mode (XIN Clock Stops)
Transfer a high-spee d on -c hip oscill ator mode and
low-speed on-chip oscillator mode (XIN clock stops)
program to the RAM.
Jump to the high-speed on-chip oscillator mode and
low-speed on-chip oscillator mode (XIN clock stops)
program which has been transferred to the RAM.
(The subsequent processing is executed by the
program in the RAM.)
Write 0 to the FMR01 bit before writing 1
(CPU rewrite mode enabled)
Switch the clock source for the CPU clock.
Turn XIN off
Process in high-speed on-chip oscillator
mode and low-speed on-chip oscillator
mode (XIN clock stops)
Write 0 to the FMR01 bit
(CPU rewrite mode disabled)
Jump to a s pe c ified address in the flash memory
High-spe e d on-chip osci lla t o r m ode
and low-speed on-chip oscillator
mode (XIN clock stops) program
NOTES:
1. Set the FMR01 bit to 1 (CPU rewrite mode enabled) before setting the
FMSTP bit to 1.
2. Before switching to a diff erent clock source for the CPU, make sure
the designated clock is stable.
3. Insert a 30 µs wait time in a program. Do not access to the flash
memory during this wait time.
Write 1 to the FMSTP bit (flash memory stops.
Low power consumption mode )(1)
Wait until the flash memory circuit stabilizes
(30 µs)(3)
Write 0 to the FMS TP bit
(flash memory operation)
Turn XIN clock on → wait until oscillation
stabilizes → switch the clock source for CPU
clock(2)
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20.4.3 Software Commands
The software commands are described below. Read or write commands and data in 8-bit units.
SRD: Status register data (D7 to D0)
W A: Write addre ss (Ensure the add ress specified in the first bus cycle is the same address as the wr ite
address specified in the second bus cycle.)
WD: Write data (8 bits)
BA: Given block address
×: Any specified address in the user ROM area
20.4.3.1 Read Array Command
The read array command reads the flash memory.
The MCU enters read array mode when FFh is written in the first bus cycle. When the read address is entered in
the following bus cycles, the content of the specified address can be read in 8-bit units.
Since the MCU remains in read array mode until another command is written, the contents of multiple
addresses can be read continuously.
In addition, the MCU enters read array mode after a reset.
20.4.3.2 Read Status Register Command
The read status register command is used to read the status register.
When 70h is written in the first bus cycle, the status register can be read in the second bus cycle (refer to 20.4.4
Status Registers). When reading the status register, specify an address in the user ROM area.
Do not execute this command in EW1 mode.
The MCU remains in read status register mode until the next read array command is written.
20.4.3.3 Clear Status Register Command
The clear status register command sets the status register to 0.
When 50h is written in the first bus cycle, bits FMR0 6 to FMR07 in the FMR0 register and SR4 to SR5 in the
status register are set to 0.
Tab le 20 .4 Software Com m and s
Command First Bus Cycle Second Bus Cycle
Mode Address Data
(D7 to D0) Mode Address Data
(D7 to D0)
Read array Write × FFh
Read status register Write × 70h Read × SRD
Clear status register Write × 50h
Program Write WA 40h Write WA WD
Block erase Write × 20h Write BA D0h
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20.4.3.4 Program Command
The program command writes data to the flash memory in 1-byte units.
By writing 40h in the first bus cycle and data in the second bus cycle to the write address, an auto-program
operation (data program and verify) will start. Make sure the address value specified in the first bus cycle is the
same address as the write address specified in the second bus cycle.
The FMR00 bit in the FMR0 r egister can be used to determine whether auto- programming has completed.
When suspend function disabled, the FMR00 bit is set to 0 during auto-programming and set to 1 when auto-
programming completes.
When suspend function enabled, the FMR44 bit is set to 1 during auto -programming and set to 0 when auto-
programming completes.
The FMR06 bit in the FMR0 register can be used to determine the result of auto-programming after it has been
finished (refer to 20.4.5 Full Status Check).
Do not write additions to the already programmed addresses.
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled), or the FMR0 2 b it is set t o 1 (rewrite
enabled) and the FMR15 bit in the FMR1 regi ster i s set to 1 (rew riting disabled), p rogram comman ds targeting
block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled ), program commands
targeting block 1 are not ackn owledged.
Figure 20.12 shows Program Command (When Suspe nd Function Disabled). Figure 20.13 shows Program
Command (When Suspend Function Enabled).
In EW1 mode, do not execute this command for any address which a rewrite control program is allocated.
In EW0 mode, the MCU enters read status register mode at the same time auto-programming starts and the
status register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-programming starts
and set back to 1 when auto-programming completes. In this case, the MCU remains in read status register
mode until the next read array command is written. The status register can be read to de termine th e result of
auto-programming after auto-programming has completed.
Figure 20.12 Program Command (When Suspend Function Disabled)
Start
Write the command code 40h to
the write address
Write data to the write address
FMR00 = 1?
Full status check
Program completed
No
Yes
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Figure 20.13 Program Command (When Suspend Function Enabled)
Start
Write the command code 40h
to the write address
Write data to the write addres s
FMR44 = 0 ?
Full status chec k
Program complete d
No
Yes
EW0 Mode
FMR40 = 1
Start
Write the command code 40h
Write data to the write addres s
FMR44 = 0 ?
Full status chec k
Program complete d
No
Yes
EW1 Mode
FMR40 = 1
Maskable interrupt (2)
REIT
Access flash memory
FMR42 = 0
NOTES:
1.In EW0 mode, the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2.td(SR-SUS) is needed until the interrupt request is ack nowledged afte r it is generated. The interrupt to enter suspend
should be in interrupt enabled status.
3.When no interrupt is used, the instruction to enable interrupts is not needed.
4. td(SR-SUS) is needed until program is suspended after the FMR42 bit in the FMR4 register is set to 1.
Maskable interrupt(1)
FMR46 = 1 ?
REIT
Yes
FMR42 = 1(4)
FMR42 = 0
Access fl as h memory
FMR44 = 1 ?
Yes
No
Access flash memory
No
I = 1 (enable interrupt)
I = 1 (enable interrupt)(3)
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20.4.3.5 Block Erase
When 20h is written in the first bus cycle and D0h is written to a given address of a block in the second bus
cycle, an auto-erase operation (erase and verify) of th e specified block starts.
The FMR00 bit in the FMR0 register can determine whether auto-erasure has completed.
The FMR00 bit is set to 0 during auto-erasure and set to 1 when auto-erasure completes.
The FMR07 bit in the FMR0 register can be used to determine the result of auto-erasure after auto-erasure has
completed (refer to 20.4.5 Full St atus Check).
When the FMR02 bit in the FMR0 register is set to 0 (rewriting disabled) or the FMR02 bit is set to 1 (rewriting
enabled) and the FMR15 bit in the FMR1 register is set to 1 (rewriting disabled), the block erase commands
targeting block 0 are not acknowledged. When the FMR16 bit is set to 1 (rewriting disabled), block erase
commands targeting block 1 are not acknowledged.
Do not use the block erase command during program-suspend.
Figure 20.14 shows the Block Erase Command (When Erase-Suspend Functio n Disabled). Figure 20.15 shows
the Block Erase Command (When Erase-Suspend Function Enabled).
In EW1 mode, do not execute this command for any address to which a rewrite control pro gram is allocated .
In EW0 mode, the MCU enters read status register mode at the same time auto-erasure starts and the status
register can be read. The status register bit 7 (SR7) is set to 0 at the same time auto-erasure starts and set back to
1 when auto-erasure completes. In this case, the MCU remains in read status register mode until the next read
array command is written.
Figure 20.14 Block Erase Comma nd (When Erase-Suspend Function Disabled)
Start
Write the command code 20h
Write D0h to a given block
address
FMR00 = 1?
Full status check
Block erase co m pleted
No
Yes
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Figure 20.15 Block Erase Command (When Erase-Suspend Function Enabled)
Start
Write the command code 20h
Write D0h to any block
address
FMR00 = 1 ?
Full status check
Block erase completed
No
Yes
EW0 Mode
FMR40 = 1
Start
Write the command code 20h
Write D0h to any block
address
FMR00 = 1 ?
Full status check
Block erase completed
No
Yes
EW1 Mode
I = 1 (enable interrupt)
Maskable interrupt(2)
REIT
Access flash memory
FMR41 = 0
NOTES:
1.In EW0 mode, the interrupt ve c tor table and interrupt routine for interrupts to be used should be allocated to the RAM area.
2.td(SR-SUS) is needed until the interrupt request is ac k no wle dged after it is generated . The interrupt to ent er s us pe nd
should be in interrupt enabled status.
3.When no interrupt is used, th e ins truction to enable int errupts is not needed.
4. td(SR-SUS) is needed until erase is susp ended after the FMR41 bi t in the FMR4 register is set to 1.
Maskable interrupt(1)
FMR46 = 1 ?
REIT
Yes
FMR41 = 1(4)
FMR41 = 0
Access flash memory
FMR43 = 1 ?
Yes
No
Acces s f l as h memor y
No
I = 1 (enable interrupt) (3)
FMR40 = 1
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20.4.4 Status Registers
The status register indicates the operating status of the flash memory and whether an erase or program operation
has completed normally or in error. Status of the status register can be read by bits FMR00, FMR06, and
FMR07 in the FMR0 register.
Table 20.5 lists the Status Register Bits.
In EW0 mode, the status register can be read in the following cases:
•When a given address in the user ROM area is read after writing the read status register command
•When a given address in the user ROM area is read after executing the program or block erase command
but before executing the read array command.
20.4.4.1 Sequencer Status (SR7 and FMR00 Bits)
The sequencer status bits indicate the operating status of the flash memory. SR7 is set to 0 (busy ) during auto-
programming and auto-erasure, and is set to 1 (ready) at the same time the operation comp let e s.
20.4.4.2 Erase Status (SR5 and FMR07 Bits)
Refer to 20.4.5 Full Status Check.
20.4.4.3 Program Status (SR4 and FMR06 Bits)
Refer to 20.4.5 Full Status Check.
D0 to D7:Indicate the data bus which is read when the read status register command is executed.
Bits FMR07 (SR5) to FMR06 (SR4) are set to 0 by executing the clear status register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to 1, the progra m and block erase commands ca nnot
be accepted.
Table 20.5 Status Register Bits
Status Register
Bit FMR0 Register
Bit Status Name Description Value after
Reset
01
SR0 (D0) −Reserved −−−
SR1 (D1) −Reserved −−−
SR2 (D2) −Reserved −−−
SR3 (D3) −Reserved −−−
SR4 (D4) FMR06 Program status Completed normally Error 0
SR5 (D5) FMR07 Erase status Completed no rmally Error 0
SR6 (D6) −Reserved −−−
SR7 (D7) FMR00 Sequencer
status Busy Ready 1
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20.4.5 Full Status Check
When an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating the occurrence of an
error. Therefore, checking these status bits (full status check) can be used to determine the execution result.
Table 20.6 lists the Errors and FMR0 Register Status. Figure 20.16 shows the Full Status Check and Handling
Procedure for Individual Errors.
NOTE:
1. The MCU enters read array mo de wh en FFh is wr it te n in the second bu s cycle of th ese co mmands.
At the same time, the command code written in the first bus cycle is disabled.
Tab le 20 .6 Errors and FMR0 Regist er Status
FRM0 Register (Status
Register) Status Error Error Occurrence Condition
FMR07(SR5) FMR06(SR4)
1 1 Command
sequence
error
• When a command is not written correctly
• When invalid data other than that which can be written
in the second bus cycle of the bl ock er ase command is
written (i.e., other than D0h or FF h)(1)
• When th e prog ram co mmand o r block erase com mand
is executed while rewriting is disabled by the FMR02 bit
in the FMR0 register, or the FMR15 or FMR16 bit in the
FMR1 register.
• When an address not allocated in flash memory is input
during erase command input
• When attempting to eras e th e blo ck fo r w hic h re writ ing
is disabled during erase command input.
• When an address not allocated in flash memory is input
during write command input.
• When attempting to write to a block for which rewriting
is disabled during the wr ite command input.
1 0 Erase error • When the block erase command is executed but auto-
erasure does not complete correctly
0 1 Program error •When the program command is executed but not auto-
programming doe s not complete.
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Figure 20.16 Full Status Check and Handling Procedure for Individual Errors
NOTE:
1. To rewrite to the address where the program error occurs, check if the full
status check is complete normally and write to the address after the block
erase command is executed.
Full status check
FMR06 = 1
and
FMR07 = 1?
FMR07 = 1?
FMR06 = 1?
Full status check completed
No
Yes
Yes
No
Yes
No
Command sequence error
Erase error
Program error
Command sequence error
Execute the clear status register command
(set these status flags to 0)
Check if command is properly input
Re-execute the command
Erase error
Execute the clear status register command
(set these status flags to 0)
Erase command
re-execution times ≤ 3 times?
Re-execute block erase command
Program error
Execute the clear status register
command
(set these status flags to 0)
Specify the other address besides the
write address where the error occurs for
the program address(1)
Re-execute program command
Block targeting for erasure
cannot be used
No
Yes
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20.5 Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be rewritten while the MCU is mounted on-board by using a
serial programmer which is suitable for the MCU.
There are three types of Standard serial I/O modes:
•Standard serial I/O mode 1 ............Clock synchronous serial I/O used to connect with a serial programmer
•Standard serial I/O mode 2 ............Clock asynchronous serial I/O used to connect with a serial programmer
•Standard serial I/O mode 3 ............Special clock asynchronous serial I/O used to connect with a serial
programmer
This MCU uses Standard serial I/O mode 2 and Standard serial I/O mode 3.
Refer t o Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator.
Contact the manufacturer of your serial programmer for details. Refer to the user ’s manual of your serial
programmer for instructions on how to use it.
Table 20.7 lists the Pin Functions (Flash Memory Standard Serial I/O Mode 2), Table 20.8 lists the Pin Functions
(Flash Memory Standard Serial I/O Mode 3). Figure 20.17 shows Pin Connection s for Standard Serial I/O Mode 3.
After processing the pins sh own in Table 20.8 and rewriting the flash memory using the programmer, apply “H” to
the MODE pin and reset the hardware to run a program in the flash memory in single-chip mode.
20.5.1 ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer and those written
in the flash memory match (refer to 20.3 Functions to Prevent Rewriting of Flash Memory).
Table 20.7 Pin Functions (Flash Memory Standard Serial I/O Mode 2)
Pin Name I/O Description
VCC,VSS Power input Apply the voltage guaranteed for pr ogramming and
erasure to the VCC pin and 0 V to the VSS pin.
RESET Reset input I Reset input pin.
P4_6/XIN P4_6 input/clock input I Connect a ceramic resonator or crystal oscillator
between the XIN and XOUT pins.
P4_7/XOUT P4_7 input/clock output I/O
P0_0 to P0_7 Input port P0 I Input “H” or “L” level signal or leave the pin open.
P1_0 to P1_7 Input port P1 I
P3_0, P3_1, P3_3 to
P3_6 Input port P3 I
P4_2/VREF Input port P4 I
P5_3, P5_4 Input port P5 I
MODE MODE I/O Input “L”.
P3_7 TXD output O Serial data output pin.
P4_5 RXD input I Serial dat a input pin.
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Figure 20.17 Pin Connections for Standard Serial I/O Mode 3
Table 20.8 Pin Functions (Flash Memory Standard Serial I/O Mode 3)
Pin Name I/O Description
VCC,VSS Power input Apply the voltage guara nteed for p rog rammin g and
erasure to the VCC pin and 0 V to the VSS pin.
RESET Reset input I Reset input pin.
P4_6/XIN P4_6 input/clock input I Connect a ceramic resonator or crystal oscillator
between the XIN and XOUT pins when connecting
external oscillator . Apply “H” and “L” or leave the pin
open when using as input port.
P4_7/XOUT P4_7 input/clock output I/O
P0_0 to P0_7 Input port P0 I Input “H” or “L” level signal or leave the pin open.
P1_0 to P1_7 Input port P1 I
P3_0, P3_1, P3_3 to
P3_7 Input port P3 I
P4_2/VREF, P4_5 Input port P4 I
P5_3, P5_4 Input port P5 I
MODE MODE I/O Serial data I/O pin. Connect to the flash
programmer.
NOTE:
1. It is not necessary to connect an oscillating circuit
when operating wi th the on-chip oscillator clock.
Package: PLQP0032G B-A
Mode setting
Signal Value
MODE
RESET
Voltage from programmer
VSS → VCC
Connect oscillator circuit(1)
VCC
MODE
VSS
R8C/2E Group, R8C/2F Group
29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
24 23 22 21 20 19 18 17
5781234 6
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20.5.1.1 Example of Circuit Application in the Standard Serial I/O Mode
Figure 20.18 shows an example of Pin Processing in Standard Serial I/O Mode 2, Figure 20.19 shows an
example of Pin Processing in Standard Serial I/O Mode 3. Since the controlled pins vary depending on the
programmer, refer to the manual of your serial programmer for details.
Figure 20.18 Pin Processing in Standard Serial I/O Mode 2
Figure 20.19 Pin Processing in Standard Serial I/O Mode 3
NOTES:
1. In this example, modes are switched between single-chip mode and
standard serial I/O mode by controlling the MODE input with a switch.
2. Connecting the oscillation is necessary. Set the main clock frequency 1
MHz to 20 MHz. Refer to Appendix Figure 2.1 Connecting examples
with M16C Flash Starter (M3A-0806).
MCU
TXD
RXD
Data Output
Data Input
MODE
NOTES:
1. Controlled pins and external circuits vary depending on the programmer.
Refer to the programmer manual for details.
2. In this example, modes are switched between single-chip mode and
standard serial I/O mode by connecting a programmer.
3. When operating with the on-chip oscillator clock, it is not necessary to
connect an oscillating circuit .
MCU
MODE
RESET
User reset signal
MODE I/O
Reset input
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20.6 Parallel I/O Mode
Parallel I/O mode is used to input and output software commands, addresses and data necessary to control (read,
program, and erase) the on-chip flash memory. Use a parallel programmer which supports this MCU. Contact the
manufacturer of the parallel programmer for more information, and refer to the user ’s manual of the parallel
programmer for details on how to use it.
ROM areas shown in Figures 20.1 and 20.2 can be rewritten in parallel I/O mode.
20.6.1 ROM Code Protect Function
The ROM code protect function disables the reading and rewriting of the flash memory. (Refer to the 20.3
Functions to Prevent Rewriting of Flash Memory.)
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20.7 Notes on Flash Memory Version
20.7.1 CPU Rewrite Mode
20.7.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
20.7.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference internal data in flash memory:
UND, INTO, and BRK.
20.7.1.3 Interrupts
Ta ble 20.9 lists the EW0 Mode Interrupts and Table 20.10 lists the EW1 Mode Interrupt.
NOTES:
1. Do not use the address match interrupt while a command is being executed because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in blo ck 0.
Table 20.9 EW0 Mode Interrupts
Mode Status When Maskable
Interrupt Requ est is
Acknowledged
When Watchdog Timer, Oscillation Stop
Detection, V olt age Monitor 1, or Voltage Mo nitor
2 Interrupt Request is Acknowledged
EW0 During auto-erasure Any interrupt can be used
by allocating a vector in
RAM
Once an interrupt request is acknowledged, the
auto-programming or auto-erasure is forcibly
stopped immediately and th e flash memory is
reset. Interrupt handling starts after the fixed
period and the fla sh memory restarts. Since the
block during auto-erasure o r the addr ess during
auto-programming is forcibly stopped, the
normal value may not be read. Execute auto-
erasure again and ensure it completes normally.
Since the watchdog timer does not stop during
the command operation, inter rupt re que sts may
be generated. Rese t the watchdog timer
regularly.
Auto-programming
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NOTES:
1. Do not use the address match interrupt while a command is executing because the vector of the
address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in blo ck 0.
Table 20.10 EW1 Mode Interrupt
Mode Status When Maskable Interrupt
Request is Acknowledged
When W atchdog Timer , Oscillation S top
Detection, V olt age Monitor 1, or V oltage
Monitor 2 Interrupt Request is
Acknowledged
EW1 During auto-erasure
(erase-suspend
function enabled)
Auto-erasure is suspended after
td(SR-SUS) and interrupt
handling is executed. Auto-
erasure can be restarted by
setting the FMR41 bit in the
FMR4 register to 0 (erase rest ar t)
after interrupt handling
completes.
Once an interrupt request is
acknowledged, auto-programming or
auto-erasure is forcibly stopped
immediately and the flash memory is
reset. Interrup t handling starts after the
fixed period and the flash memor y
restarts. Since the block during aut o-
erasure or the ad d re ss du rin g auto -
programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensure it
completes normally.
Since the watchdog timer does not stop
during the command operation,
interrupt requests may be generated.
Reset the watchdog timer regularly
using the erase-suspend function.
During auto-erasure
(erase-suspend
function disabled)
Auto-erasure has priority and the
interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-erasure
completes.
During auto-
programming
(program su spend
function enabled)
Auto-programming is suspended
after td(SR-SUS) and interrupt
handling is executed.
Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) af ter interrupt
handling completes.
During auto-
programming
(program su spend
function disabled)
Auto-programming has priority
and the interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-programming
completes.
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20.7.1.4 How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
20.7.1.5 Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
20.7.1.6 Program
Do not write additions to the already programmed address.
20.7.1.7 Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
20.7.1.8 Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
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21. Electrical Characteristics
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Table 21.1 Absolute Maximum Ratings
Symbol Parameter Condition Rated Value Unit
VCC/AVCC Supply voltage −0.3 to 6.5 V
VIInput voltage −0.3 to VCC + 0.3 V
VOOutput voltage −0.3 to VCC + 0.3 V
PdPower dissipation Topr = 25°C500mW
Topr Operating ambient temperature −20 to 85 (N version) /
−40 to 85 (D version) °C
Tstg Storage temperature −65 to 150 °C
Table 21.2 Recommended Operating Conditions
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
VCC/AVCC Supply voltage 2.7 −5.5 V
VSS/AVSS Supply voltage −0−V
VIH Input “H” voltage 0.8 VCC −VCC V
VIL Input “L” voltage 0 −0.2 VCC V
IOH(sum) Peak sum output
“H” cu rrent Sum of all pins IOH(peak) −−−160 mA
IOH(sum) Average sum
output “H” current Sum of all pins IOH(avg) −−−80 mA
IOH(peak) Peak output “H”
current Except P1_0 to P1_7 −−−10 mA
P1_0 to P1_7 −−−20 mA
IOH(avg) Average output
“H” cu rrent Except P1_0 to P1_7 −−−5mA
P1_0 to P1_7 −−−10 mA
IOL(sum) Peak sum output
“L” currents Sum of all pins IOL(peak) −−160 mA
IOL(sum) Average sum
output “L” currents Sum of all pins IOL(avg) −−80 mA
IOL(peak) Peak output “L”
currents Except P1_0 to P1_7 −−10 mA
P1_0 to P1_7 −−20 mA
IOL(avg) Average output
“L” current Except P1_0 to P1_7 −−5mA
P1_0 to P1_7 −−10 mA
f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
−System clock OCD2 = 0
XlN clock selected 3.0 V ≤ VCC ≤ 5.5 V 0 −20 MHz
2.7 V ≤ VCC < 3.0 V 0 −10 MHz
OCD2 = 1
On-chip oscillator clock
selected
FRA01 = 0
Low-speed on-chip
oscillator clock sele cted
−125 −kHz
FRA01 = 1
High-speed on-chip
oscillator clock sele cted
3.0 V ≤ VCC ≤ 5.5 V
−−20 MHz
FRA01 = 1
High-speed on-chip
oscillator clock sele cted
2.7 V ≤ VCC ≤ 5.5 V
−−10 MHz
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Figure 21.1 Ports P0, P1, and P3 to P5 Timing Measurement Circuit
NOTES:
1. AVCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
NOTES:
1. AVCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF
not connected), IVref flows into the D/A converters.
Table 21.3 A/D Converter Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution Vref = AVCC −−10 Bits
−Absolute
accuracy 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±3 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V −−±2 LSB
10-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±5 LSB
8-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V −−±2 LSB
Rladder Resistor ladder Vref = AVCC 10 −40 kΩ
tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 −−µs
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 −−µs
Vref Reference voltage 2.7 −AVCC V
VIA Analog input voltage(2) 0−AVCC V
−A/D operating
clock frequency Without sample and hold Vref = AVCC = 2.7 to 5.5 V 0.25 −10 MHz
With sample and hold Vref = AVCC = 2.7 to 5.5 V 1 −10 MHz
Table 21.4 D/A Converter Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Resolution −−8Bit
−Absolute accuracy −−1.0 %
tsu Setup time −−3µs
ROOutput resistor 4 10 20 kΩ
IVref Reference power input current (NOTE 2) −−1.5 mA
P0
P1
P3
P4
P5
30pF
R8C/2E Group, R8C/2F Group 21. Electrical Characteristics
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NOTE:
1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 21.5 Comparator Characteristics(1)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
Vcref Comparator reference voltage 0 −VCC−1.2 V
Vcin Comparator input voltage −0.3 −VCC+0.3 V
Vofs Input offset voltage −− ±100 mV
Tcrsp Response time −− 200 ns
Table 21.6 Flash Memory (Program ROM) Electrical Characteristics
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) R8C/2E Group 100(3) −−times
R8C/2F Group 1,000(3) −−times
−Byte program time −50 400 µs
−Block erase time −0.4 9 s
td(SR-SUS) Time delay from suspend request until
suspend −−97+CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−T ime from suspend until program/erase
restart −−3+CPU cl o ck
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.7 −5.5 V
−Program, erase temperature 0 −60 °C
−Data hold time(7) Ambient temperature = 55°C20 −−year
R8C/2E Group, R8C/2F Group 21. Electrical Characteristics
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NOTES:
1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. −40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
Table 21.7 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Symbol Parameter Conditions Standard Unit
Min. Typ. Max.
−Program/erase endurance(2) 10,000(3) −−times
−Byte program time
(program/erase endurance ≤ 1,000 times) −50 400 µs
−Byte program time
(program/erase endurance > 1,000 times) −65 −µs
−Block erase time
(program/erase endurance ≤ 1,000 times) −0.2 9 s
−Block erase time
(program/erase endurance > 1,000 times) −0.3 −s
td(SR-SUS) Time delay from suspend request until
suspend −−97+CPU clock
× 6 cycles µs
−Interval from erase start/restart until
following suspend request 650 −−µs
−Interval from program start/restart until
following suspend request 0−−ns
−Time from suspend until program/erase
restart −−3+CPU clock
× 4 cycles µs
−Program, erase voltage 2.7 −5.5 V
−Read voltage 2.7 −5.5 V
−Program, erase temperature −20(8) −85 °C
−Data hold time(9) Ambient temperature = 55 °C20 −−year
R8C/2E Group, R8C/2F Group 21. Electrical Characteristics
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Figure 21.2 Time delay until Suspend
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
NOTES:
1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 21.8 Voltage Detection 1 Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet1 Voltage detection level(4) 2.7 2.85 3.00 V
−Voltage monitor 1 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA26 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3) −−100 µs
Vccmin MCU operating voltage minimum value 2.7 −−V
Table 21.9 Voltage Detection 2 Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vdet2 Voltage detection level 3.3 3.6 3.9 V
−Voltage monitor 2 interrupt request generation time(2) −40 −µs
−Voltage detection circuit self power consumption VCA27 = 1, VCC = 5.0 V −0.6 −µA
td(E-A) Waiting time until voltage detection circuit operation
starts(3) −−100 µs
FMR46
Suspend request
(maskable in terrupt request)
Fixed time
td(SR-SUS)
Clock-dependent
time Access restart
R8C/2E Group, R8C/2F Group 21. Electrical Characteristics
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REJ09B0349-0100
NOTES:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. tw(por1) indicates the dur ation the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if −20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if −40°C ≤ Topr < −20°C.
Figure 21.3 Reset Circuit Electrical Characteristics
Table 21.10 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(3) −−0.1 V
Vpor2 Power-on reset valid voltage 0 −2.6 V
trth External power VCC rise gradient(2) 20 −−mV/msec
NOTES:
1. E nsure that the voltage is 2.2 V or above during the samp ling time.
2. The sampling time is fOCO-S divided by 1 × 4 cycles .
max. 2.6 V
Vpor1
Internal
reset si gnal
(“L” valid)
tw(por1) Sampling time(1, 2)
max. 2.6 V
1
fOCO-S × 32 1
fOCO-S × 32
Vpor2
2.2 V
External
Power VCC trth trth
R8C/2E Group, R8C/2F Group 21. Electrical Characteristics
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REJ09B0349-0100
NOTES:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
NOTE:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Table 21.11 High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO40M High-speed on-chip oscillator frequency
temperature • supply voltage dependence VCC = 4.75 V to 5.25 V
0°C ≤ Topr ≤ 60°C(2) 39.2 40 40.8 MHz
VCC = 3.0 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(2) 38.8 40 41.2 MHz
VCC = 3.0 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(2) 38.4 40 41.6 MHz
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C(2) 38 40 42 MHz
VCC = 2.7 V to 5.5 V
−40°C ≤ Topr ≤ 85°C(2) 37.6 40 42.4 MHz
VCC = 5.0 V ±10%
−20°C ≤ Topr ≤ 85°C(2) 38.8 40 40.8 MHz
VCC = 5.0 V ±10%
−40°C ≤ Topr ≤ 85°C(2) 38.4 40 40.8 MHz
High-speed on-chip oscillator frequency when
correction value in FRA7 register is written to
FRA1 register
VCC = 5.0 V, Topr = 25°C−36.864 −MHz
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C−3% −3% %
−Value in FRA1 register after reset 08h −F7h −
−Oscillation frequency adjustment unit of high-
speed on-chip oscillator Adjust FRA1 register
(value after reset) to −1−+0.3 −MHz
−Oscillation stability time −10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−400 −µA
Table 21.12 Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 30 125 250 kHz
−Oscillation stability time −10 100 µs
−Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C−15 −µA
Table 21.13 Power Supply Circuit Timing Characteristics
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during
power-on(2) 1−2000 µs
td(R-S) STOP exit time(3) −−150 µs
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NOTE:
1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Table 21.14 Electrical Characteristics (1) [VCC = 5 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P1_0 to P1_7,
XOUT IOH = −5 mA VCC − 2.0 −VCC V
IOH = −200 µAVCC − 0.5 −VCC V
P1_0 to P1_7 Drive capacity HIGH IOH = −10 mA VCC − 2.0 −VCC V
Drive capacity LOW IOH = −5 mA VCC − 2.0 −VCC V
XOUT Drive capacity HIGH IOH = −1 mA VCC − 2.0 −VCC V
Drive capacity LOW IOH = −500 µAVCC − 2.0 −VCC V
VOL Output “L” voltage Except P1_0 to P1_7,
XOUT IOL = 5 mA −−2.0 V
IOL = 200 µA−−0.45 V
P1_0 to P1_7 Drive capacity HIGH IOL = 10 mA −−2.0 V
Drive capacity LOW IOL = 5 mA −−2.0 V
XOUT Drive capacity HIGH IOL = 1 mA −−2.0 V
Drive capacity LOW IOL = 500 µA−−2.0 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, CLK0
0.1 0.5 −V
RESET 0.1 1.0 −V
IIH Input “H” current VI = 5 V, VCC = 5 V −−5.0 µA
IIL Input “L” current VI = 0 V, VCC = 5 V −−−5.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 5 V 30 50 167 kΩ
RfXIN Feedback
resistance XIN −1.0 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
R8C/2E Group, R8C/2F Group 21. Electrical Characteristics
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REJ09B0349-0100
Table 21.15 Electric al Characteristics (2) [Vcc = 5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply
current
(V
CC
= 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
High-speed
clock mode XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−10 17 mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−915mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−6−mA
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−5−mA
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4−mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
High-speed
on-chip
oscillator mode
XIN clock off
High-speed on-chip oscillator on fO CO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−10 15 mA
XIN clock off
High-speed on-chip oscillator on fO CO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−4−mA
XIN clock off
High-speed on-chip oscillator on fO CO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−5.5 10 mA
XIN clock off
High-speed on-chip oscillator on fO CO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2.5 −mA
Low-speed
on-chip
oscillator mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−130 300 µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = 0
VCA20 = 1
−25 75 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Periphe r al clock off
VCA27 = VCA26 = 0
VCA20 = 1
−23 60 µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Periphe r al clock off
VCA27 = VCA26 = 0
−0.8 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Periphe r al clock off
VCA27 = VCA26 = 0
−1.2 −µA
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REJ09B0349-0100
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Figure 21.4 XIN Input Timing Diagram when VCC = 5 V
Figure 21.5 TRAIO Input Timing Diagram when VCC = 5 V
Ta b le 21 .1 6 XIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 50 −ns
tWH(XIN) XIN input “H” width 25 −ns
tWL(XIN) XIN input “L” width 25 −ns
Table 21.17 TRAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 100 −ns
tWH(TRAIO) TRAIO input “H” width 40 −ns
tWL(TRAIO) TRAIO input “L” width 40 −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 5 V
TRAIO input
VCC = 5 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
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REJ09B0349-0100
Figure 21.6 Serial Interface Timing Diagram when VCC = 5 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 21.7 External Interrupt INTi Input T iming Diagram when VCC = 5 V
Table 21.18 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLK0 input cycle time 200 −ns
tW(CKH) CLK0 input “H” width 100 −ns
tW(CKL) CLK0 input “L” width 100 −ns
td(C-Q) TXD0 output delay time −50 ns
th(C-Q) TXD0 hold time 0 −ns
tsu(D-C) RXD0 input setup time 50 −ns
th(C-D) RXD0 input hold time 90 −ns
Table 21.19 External Interrupt INTi (i = 0, 1, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 250(1) −ns
tW(INL) INTi input “L” width 250(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLK0
TXD0
RXD0
VCC = 5 V
INTi input
tW(INL)
tW(INH)
i = 0, 1, 3
VCC = 5 V
R8C/2E Group, R8C/2F Group 21. Electrical Characteristics
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REJ09B0349-0100
NOTE:
1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Table 21.20 Electrical Characteristics (3) [VCC = 3 V]
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
VOH Output “H” voltage Except P1_0 to P1_7,
XOUT IOH = −1 mA VCC − 0.5 −VCC V
P1_0 to P1_7 Drive capacity
HIGH IOH = −2 mA VCC − 0.5 −VCC V
Drive capacity
LOW IOH = −1 mA VCC − 0.5 −VCC V
XOUT Drive capacity
HIGH IOH = −0.1 mA VCC − 0.5 −VCC V
Drive capacity
LOW IOH = −50 µAVCC − 0.5 −VCC V
VOL Output “L” voltage Except P1_0 to P1_7,
XOUT IOL = 1 mA −−0.5 V
P1_0 to P1_7 Drive capacity
HIGH IOL = 2 mA −−0.5 V
Drive capacity
LOW IOL = 1 mA −−0.5 V
XOUT Drive capacity
HIGH IOL = 0.1 mA −−0.5 V
Drive capacity
LOW IOL = 50 µA−−0.5 V
VT+-VT- Hysteresis INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, CLK0
0.1 0.3 −V
RESET 0.1 0.4 −V
IIH Input “H” current VI = 3 V, VCC = 3 V −−4.0 µA
IIL Input “L” current VI = 0 V, VCC = 3 V −−−4.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 3 V 66 160 500 kΩ
RfXIN Feedback resistance XIN −3.0 −MΩ
VRAM RAM hold voltage During stop mode 1.8 −−V
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REJ09B0349-0100
Table 21.21 Electric al Characteristics (4) [Vcc = 3 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Symbol Parameter Condition Standard Unit
Min. Typ. Max.
ICC Power supply current
(VCC = 2.7 to 3.3 V)
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
clock mode XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
−6−mA
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
High-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
−59mA
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
−2−mA
Low-speed
on-chip
oscillator
mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR47 = 1
−130 300 µA
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = 0
VCA20 = 1
−25 70 µA
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = 0
VCA20 = 1
−23 55 µA
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = 0
−0.7 3.0 µA
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = 0
−1.1 −µA
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REJ09B0349-0100
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
Figure 21.8 XIN Input Timing Diagram when VCC = 3 V
Figure 21.9 TRAIO Input Timing Diagram when VCC = 3 V
Ta b le 21 .2 2 XIN Input
Symbol Parameter Standard Unit
Min. Max.
tc(XIN) XIN input cycle time 100 −ns
tWH(XIN) XIN input “H” width 40 −ns
tWL(XIN) XIN input “L” width 40 −ns
Table 21.23 TRAIO Input
Symbol Parameter Standard Unit
Min. Max.
tc(TRAIO) TRAIO input cycle time 300 −ns
tWH(TRAIO) TRAIO input “H” width 120 −ns
tWL(TRAIO) TRAIO input “L” width 120 −ns
XIN input
tWH(XIN)
tC(XIN)
tWL(XIN)
VCC = 3 V
TRAIO in pu t
VCC = 3 V
tC(TRAIO)
tWL(TRAIO)
tWH(TRAIO)
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Figure 21.10 Serial Interface Timing Diagram when VCC = 3 V
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
Figure 21.11 External Interrupt INTi Input Timing Diagram when VCC = 3 V
Table 21.24 Serial Interface
Symbol Parameter Standard Unit
Min. Max.
tc(CK) CLK0 input cycle time 300 −ns
tW(CKH) CLK0 input “H” width 150 −ns
tW(CKL) CLK0 Input “L” width 150 −ns
td(C-Q) TXD0 output delay time −80 ns
th(C-Q) TXD0 hold time 0 −ns
tsu(D-C) RXD0 input setup time 70 −ns
th(C-D) RXD0 input hold time 90 −ns
Table 21.25 External Interrupt INTi (i = 0, 1, 3) Input
Symbol Parameter Standard Unit
Min. Max.
tW(INH) INTi input “H” width 380(1) −ns
tW(INL) INTi input “L” width 380(2) −ns
tW(CKH)
tC(CK)
tW(CKL) th(C-Q)
th(C-D)
tsu(D-C)td(C-Q)
CLK0
TXD0
RXD0
VCC = 3 V
INTi input
tW(INL)
tW(INH)
VCC = 3 V
i = 0, 1, 3
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22. Usage Notes
22.1 Notes on Clock Generation Circuit
22.1.1 Stop Mode
When entering stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instr uction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least 4 NOP instructions following the JMP.B instruction after the instruction which sets th e CM10 b it
to 1.
• Program example to enter stop mode
BCLR 1,FMR0 ; CPU rewrite mode disabled
BSET 0,PRCR ; Protect disabled
FSET I ; Enable interrupt
BSET 0,CM1 ; Stop mode
JMP.B LABEL_001
LABEL_001 :
NOP
NOP
NOP
NOP
22.1.2 Wait Mode
When entering wait m ode, set the FMR01 bit in the FMR0 regist er to 0 (CPU rewrite mode disabled) and
execute the WAIT instruction. An instruct ion queue pre-reads 4 bytes from the WAIT instruction and the
program stops. Insert at least 4 NOP instructions after the WAIT instruction.
• Program example to execute the WAIT instru ction
BCLR 1,FMR0 ; CPU rewrite mode disabled
FSET I ; Enable interrupt
WAIT ; Wa it mode
NOP
NOP
NOP
NOP
22.1.3 Oscillation Stop Detection Function
Since the oscillation stop detectio n function cannot be used if the XIN clock frequency is 2 MHz or below, set
bits OCD1 to OCD0 to 00b.
22.1.4 Oscillation Circuit Constants
Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system.
To use this MCU with supply voltage below VCC = 2.7 V, it is recommended to set the CM11 bit in the CM1
register to 1 (on-chip feedback resistor disabled), the CM15 bit to 1 (high drive capacity), and connect the
feedback resistor to the chip externally.
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22.2 Notes on Interrupts
22.2.1 Reading Address 00000h
Do not read address 0000 0h by a program. When a maskable interrupt requ est is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
22.2.2 SP Setting
Set any value in the SP before an interrupt is acknowl edged. The SP i s set to 000 0h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program ma y ru n out of control.
22.2.3 External Interrupt and Key Input Interrupt
Either “L” level or an “H” level of width shown in the Electrical Characteristics is ne cessary for the signal input
to pins INT0, INT1, INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, re fer to Table 21.19 (VCC = 5V), Table 21 .25 (VCC = 3V) External Interrupt INTi (i = 0, 1, 3)
Input.
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22.2.4 Changing Interrupt Sources
The IR bit in the interrupt control register may be set to 1 (interrupt requested) when the interrupt source
changes. When using an interrupt, set the IR bit to 0 (no interrupt requested) after changing the interrupt source.
In addition, changes of interrupt sources include all factors that change the interrupt sources assigned to
individual software interrupt numbers, polarities, and timing. Therefore, if a mode change of a peripher al
function involve s interrupt so urces, edge polarities, an d timing, set t he IR bit to 0 (no i nterrupt requested) after
the change. Refer to the individual peripheral function for its related interrupts.
Figure 22.1 shows an Example of Procedure for Changing In terrup t Sources.
Figure 22.1 Example of Procedure for Changing Interrupt Sources
NOTES:
1. Execute the above settings individually. Do not execute two
or more settings at once (by one instruction).
2. To prevent interrupt requests from being generated, disable
the peripheral function before changing the interrupt
source. In this case, use the I flag if all maskable interrupts
can be disabled. If all maskable interrupts cannot be
disabled, use bits ILVL0 to ILVL2 of the interrupt whose
source is changed.
3. Refer to 12.6.5 Changing Interrupt Control Register for
the instructions to be used and usage notes.
Interrupt source change
Disable in terrupts(2, 3)
Set the IR bit to 0 (interrupt not requested)
using the MOV instruction(3)
Change interrupt source (including mode
of peripheral function)
Enable interrupts(2, 3)
Change completed
IR bit: The interrupt control register bit of an
interrupt whose source is changed.
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22.2.5 Changing Interrupt Control Register Contents
(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are gen erated. If interrupt requests may be generated, disable interrupts
before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be careful to
choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction, the IR bit
may not be set to 1 (interrupt req uested), and the interrupt request may be ignored. If this causes a
problem, use the following instructions to change the register: AND, OR, BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the instruction used.
Therefore, use the MOV instruction to set the IR bit to 0.
(c) When di sabling interrupts using the I flag, set the I flag as shown in the sample programs b elow. Refer
to (b) regarding changing the contents of interrupt control registers by the sample programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before the interrupt
control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control register
is changed
INT_SWITCH1:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
NOP ;
NOP
FSET I ; Enable interrupts
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
MOV.W MEM,R0 ; Dummy read
FSET I ; Enable interrupts
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR I ; Disable interrupts
AND.B #00H,0056H ; Set TRAIC register to 00h
POPC FLG ; Enable interrupts
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22.3 Notes on Timers
22.3.1 Notes on Timer RA
•Timer RA stops counting after a reset. Set th e values in the timer RA and timer RA prescalers before the
count starts.
•Even if the prescaler and timer RA are read out in 16-bit units, these registers are read 1 byte at a time by
the MCU. Consequently, the timer value may be updated during the period when these two registers are
being read.
•In pulse period measurement mode, bits TEDGF and TUNDF in the TRACR register can be set to 0 by
writing 0 to these bits by a program. However, these bits remain un changed if 1 is written. When using the
READ-MODIFY-WRITE instruction for the TRACR register, the TEDGF or TUNDF bit may be set to 0
although these bits are set to 1 while the instruction is being executed. In this case, write 1 to the TEDGF or
TUNDF bit which is not supposed to be set to 0 with the MOV instru ction.
•When changing to pulse period measurement mode from another mode, the contents of bits TEDGF and
TUNDF are undefined. Write 0 to bits TEDGF and TUNDF before the count starts.
•The TEDGF bit may be set to 1 by the first timer RA prescaler underflow generated after the count starts.
•When using the pulse period measurement mode, leave two or more periods of the timer RA prescaler
immediately after the count starts, then set the TEDGF bit to 0.
•The TCSTF bit retains 0 (count stops) for 0 to 1 cycle of the count source after setting the TSTART bit to 1
(count starts) while the count is stopped.
During this time, do not access registers associated with tim er RA(1) other than the TCSTF bit. Timer RA
starts counting at the first valid edge of the count source after The TCSTF bit is set to 1 (duri ng count).
The TCSTF bit remains 1 for 0 to 1 cycle of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RA counting is stopped when the TCSTF bit is set to 0.
During this time, do not access registers associated with timer RA(1) other than the TCSTF bit.
NOTE:
1. Registers associated with timer RA: TRACR, TRAIOC, TRAMR, TRAPRE, and TRA.
•When the TRAPRE register is continuously wri tten during count operation (TCSTF bit is set to 1), allow
three or more cycles of the count source clock for each write interval.
•When the TRA register is continuously written during count operation (TCSTF bit is set to 1), allow three
or more cycles of the prescaler underflow for each write interval.
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22.3.2 Notes on Timer RB
•Timer RB stops counting after a reset. Set the values in the timer RB and timer RB prescalers before the
count starts.
•Even if the prescaler and timer RB is read out in 16-bit units, these registers are read 1 byte at a time by the
MCU. Consequently, the timer value may be updated during the perio d when these two reg isters are being
read.
•In programmable one-shot generation mode and programmable wait one-shot generation mode, when
setting the TSTART bit in the TRBCR register to 0, 0 (stops counting) or setting the TOSSP bit in the
TRBOCR register to 1 (stops one-sh ot), th e timer rel oads the value of reload register and stops. Therefore,
in programmable one-shot generation mode and programmable wait one-shot generation mode, read the
timer count value before the timer stop s.
•The TCSTF bit remains 0 (count stops) for 1 to 2 cycles of the count source after setting the TSTART bit to
1 (count starts) while the count is stopped.
During this time, do not access registers associated with timer RB(1)other than the TCSTF bit. Timer RB
starts counting at the first valid edge of the count source after the TCSTF bit is set to 1 (during count).
The TCSTF bit remains 1 for 1 to 2 cycles of the count source after setting the TSTART bit to 0 (count
stops) while the count is in progress. Timer RB counting is stopped when the TCSTF bi t is set to 0.
During this time, do not access registers associated with timer RB(1) othe r than the TCSTF bit.
NOTE:
1. Registers associated with timer RB: TRBCR, TRBOCR, TRBIOC, TRBMR, TRBPRE, TRBSC, and
TRBPR.
•If the TSTOP bit in the TRBCR register is set to 1 during timer operation, timer RB stops immediately.
•If 1 is written to the TOSST or TOSSP bit in the TRBOCR register, the value of the TOSSTF bit changes
after one or two cycles of the count source have elap sed. If th e TOSSP bit is written to 1 d uring the peri od
between when the TOSST bit is written to 1 and when the TOSSTF bit is set to 1, the TOSSTF bit may be
set to either 0 or 1 depending on the content state. Likewise, if the TOSST bit is written to 1 during the
period between when the TOSSP bit is written to 1 and when the TOSSTF bit is set to 0, the TOSSTF bit
may be set to either 0 or 1.
22.3.2.1 Timer mode
The following workaround should be performed in timer mode.
To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the following
points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
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22.3.2.2 Programmable waveform generation mode
The following three workarounds should be performe d in programmable waveform generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) To change registers TRBPRE and TRBPR duri ng count operation (TCSTF bit is set to 1), synchronize
the TRBO output cycle using a timer RB interrupt, etc. This operation should be preformed only once in
the same output cycle. Also, make sure that writing to the TRBPR register does not occur during period
A shown in Figures 22.2 and 22.3.
The following shows the detailed workaround examp les.
•Workaround example (a):
As shown in Figure 22.2, writ e to registers TRBSC and TRBPR in the timer RB interrupt routine. These
write operations must be completed by the beginni ng of period A.
Figure 22.2 Workaround Example (a) When Timer RB interrupt is Used
TRBO pin output
Count source/
prescaler
underflow si gn al
Primary period
Period A
IR bit in
TRBIC register
Secondary period
(b)
Interrupt
sequence Instruction in
interrupt routine
Interrupt request is
acknowledged
(a)
Interrupt request
is generated
Ensure suffici ent time
Set the secondary and then
the primary register immediately
(a) Peri od between i nterrupt reque st generation and the co mpletion of execution of an instruc tion. The length of t ime
varies depend ing on th e inst ru ct io n being exec ute d.
The DIVX instruction requires the longest time, 30 c ycles (assuming no wait states and that a register is se t as
the divisor).
(b) 20 cycles. 21 c yc l es for address match and single-step interrupts.
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•Workaround example (b):
As shown in Figure 22.3 detect the start of the primary period by the TRBO pin output level and write to
registers TRBSC and TRBPR. These write operations must be completed by the beginning of period A.
If the port register’ s bit value is read after the port direction register’s bit corresponding to the TRBO pin is
set to 0 (input mode), the read value indicat es the TRBO pin output value.
Figure 22.3 Workaround Example (b) When TRBO Pin Output Value is Read
(3) To stop the timer counting in the primary period, use the TSTOP bit in the TRBCR register. In this case,
registers TRBPRE and TRBPR are initialized and their values are set to the values after reset.
22.3.2.3 Programmable one-shot generation mode
The following two workarounds should be performe d in programmable one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuousl y during count operatio n (TCSTF bit is set to 1), allow
three or more cycles of the count source for each write interval.
•When the TRBPR register is written continuously during count operation (TCSTF bit is set to 1), allow
three or more cycles of the prescaler underflow for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
TRBO pin output
Count source/
prescaler
underflow signal
Primary period
Period A
Read value of the port register’s
bit corresponding to the TRBO pin
(when the bit in the port direction
register is set to 0)
Secondary period
(i)
The TRBO output inversion
is detected at the end of the
secondary period.
Ensure sufficient time
Upon detecting (i), set the secondary and
then the primary register immediately.
(ii) (iii)
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22.3.2.4 Programmable wait one-shot generation mode
The following three workarounds should be performe d in programmable wait one-shot generation mode.
(1) To write to registers TRBPRE and TRBPR during count operation (TCSTF bit is set to 1), note the
following points:
•When the TRBPRE register is written continuously, allow three or more cycles of the count source for each
write interval.
•When the TRBPR register is written continuously, allow three or more cycles of the prescaler underflow
for each write interval.
(2) Do not set both the TRBPRE and TRBPR registers to 00h.
(3) Set registers TRBSC and TRBPR using the following procedure.
(a) To use “INT0 pin one-shot trigger enabled” as the count start condition
Set the TRBSC register and then the TRBPR register. At this time, after writing to the TRBPR
register, allow an interval of 0.5 or more cycles of the count source before trigger input from the
INT0 pin.
(b) To use “writing 1 to TOSST bit” as the start condition
Set the TRBSC register, the TRBPR register, and then TOSST bit. At this time, after writing to the
TRBPR register, allow an interval of 0.5 or m ore cycles of the count source before writing to the
TOSST bit.
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22.3.3 Notes on Timer RC
22.3.3.1 TRC Register
•The following note applies when the CCLR bit in the TRCCR1 register is set to 1 (clear TRC register at
compare match with TRCGRA register).
When using a program to write a value to the TRC register while the TSTAR T bit in the TRCMR register is
set to 1 (count starts), ensure that the write does not overlap with the timing with which the TRC register is
set to 0000h.
If the timing of the write to the TRC register and the setting of the TRC register to 0000h coincide, the
write value will not be written to the TRC register and the TRC register will be set to 0000h.
•Reading from the TRC register immediat ely after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the write instructions.
Program Example MOV.W #XXXXh, TRC ;Write
JMP.B L1 ;JMP.B instruction
L1: MOV.W TRC,DATA ;Read
22.3.3.2 TRCSR Register
Reading from the TRCSR register immediately after writing to it can result in the value previous to the write
being read out. To prevent this, execute the JMP.B instruction between the read and the writ e instructions.
Program Example MOV.B #XXh, TRCSR ;Write
JMP.B L1 ;JMP.B instruction
L1: MOV.B TRCSR,DATA ;Read
22.3.3.3 Count Source Switching
•Stop the count before switching the count source.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the setti ngs of bits TCK2 to TCK0 in the TRCCR1 register.
•After switching the count source from fOCO40M to another clock, allow a m ini mum of two cycles of f1 to
elapse after changing the clock setting before stopping fOCO40M.
Switching procedure
(1) Set the TSTART bit in the TRCMR register to 0 (count stops).
(2) Change the setti ngs of bits TCK2 to TCK0 in the TRCCR1 register.
(3) Wait for a minimum of two cycles of f1.
(4) Set the FRA00 bit in th e FRA0 register to 0 (high-speed on-chip oscillator off).
22.3.3.4 Input Capture Function
•The pulse width of the input capture sign al shoul d be three cycles or more of the timer RC operation clock
(refer to Table 14.11 Timer RC Operation Clock).
•The value of the TRC register is transferred to the TRCGRj register one or two cycles of the timer RC
operation clock after the input capture signal is input to the TRCIOj (j = A, B, C, or D) pin (when the
digital filter function is not used).
22.3.3.5 TRCMR Register in PWM2 Mode
When the CSEL bit in the TRCCR2 register is set to 1 (count stops at compare match with the TRCGRA
register), do not set the TRCMR register at compare match timing of registers TRC and TRCGRA.
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22.3.4 Notes on Timer RE
22.3.4.1 Starting and Stopping Count
Timer RE has the TSTART bit for instru cting the count to start or stop, and the TCSTF bit, which indicates
count start or stop. Bits TSTART and TCSTF are in the TRECR1 register .
Timer RE starts coun ting and the TCSTF bit is set to 1 (count starts) when the TSTART bit is set to 1 (count
starts). It takes up to 2 cycles of the count source until the TCSTF bit is set to 1 after setting the TSTART bit to
1. During this time, do not access registers associated with timer RE(1) other than the TCSTF bit.
Also, timer RE stops counting when setting the TSTA RT bit to 0 (count stops) and the TCSTF bit is set to 0
(count stops). It takes the tim e for up to 2 cycles of the count source unti l the TCSTF bit is set to 0 afte r setting
the TSTART bit to 0. During this ti me, do not access registers associated with timer RE other than the TCSTF
bit.
NOTE:
1. Registers associated with timer RE: TRESEC, TREMIN, TRECR1, TRECR2, and TRECSR.
22.3.4.2 Register Setting
Write to the following registers or bits when timer RE is stopped.
•Registers TRESEC, TREMIN, and TRECR2
•INT bit in TRECR1 register
•Bits RCS0 to RCS2 and b3 in TRECSR register
Timer RE is stopped when bits TSTART and TCSTF in the TRECR1 register are set to 0 (timer RE stopped).
Also, set all above-mentioned registers and bits (immediately before timer RE count starts) before setting the
TRECR2 register.
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22.4 Notes on Serial Interface
•When reading data from the U0RB register either in the clock synchronous serial I/O mode or in the clock
asynchronous serial I/O mode, ensure the data is read in 16-bit units. When the high-order byte of the U0RB
register is read, bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0.
The check receive errors, read the U0RB register and then use the read data.
Example (when reading receive buffer register):
MOV.W 00A6H,R0 ; Read the U0RB register
•When writing data to the U0TB register in the clock asynchronous serial I/O mode with 9-bit transfer data
length, write data to the high-order byte first then the low-order byte, in 8-bit units.
Example (when reading transmit buffer register):
MOV.B #XXH,00A3H ; Write the high-order byte of U0TB register
MOV.B #XXH,00A2H ; Write the low-order byte of U0TB register
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22.6 Notes on A/D Converter
•Write to each bit (other than bit 6) in the ADCON0 register, each b it in the ADCON1 register, or the SMP bit
in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
•After changing the A/D operatin g mode, select an analog input pin again.
•When using the one-shot mode, ensure that A/D conversion is com pleted before reading the AD register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
•When using the repeat mode, select t he frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion .
Do not select the fOCO-F for the φAD.
•If the ADST bit in the ADCON0 register is set to 0 (A/D conv ersion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD register.
•Connect 0.1 µF capacitor between the P4_2/VREF pin and AVSS pin.
•Do not enter stop mode during A/D conversion.
•Do not enter wait mode when the CM02 bi t in the CM0 regi ster is set to 1 (peripheral function clock stops in
wait mode) during A/D conversi on.
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22.7 Notes on Flash Memory Version
22.7.1 CPU Rewrite Mode
22.7.1.1 Operating Speed
Before entering CPU rewrite mode (EW0 mode), select 5 MHz or below for the CPU clock using the CM06 bit
in the CM0 register and bits CM16 to CM17 in the CM1 register. This does not apply to EW1 mode.
22.7.1.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because they reference internal data in flash memory:
UND, INTO, and BRK.
22.7.1.3 Interrupts
Ta ble 22.1 li sts the EW0 Mode Interrupts and Table 22.2 lists the EW1 Mode Interrupt.
NOTES:
1. Do not use the address match interrupt while a command is being exec uted because the vector of
the address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Table 22.1 EW0 Mode Interrupts
Mode Status When Maskable
Interrupt Request is
Acknowledged
When Watchdog Timer, Oscillation Stop
Detection, V olt age Monitor 1, or V olt age Monitor
2 Interrupt Request is Acknowledged
EW0 During auto-erasure Any interrupt can be used
by allocating a vector in
RAM
Once an interrup t re qu e st is acknowledged, the
auto-programming or auto-erasure is forcibly
stopped immediately and th e flash memory is
reset. Interrupt handling starts after the fixe d
period and the flash memory restarts. Since the
block during auto-erasure or the address during
auto-programming is forcibly stopped, the
normal value may not be read. Execute auto-
erasure again and ensure it completes normally.
Since the watchdog timer does not stop during
the command operation, interrupt reque st s may
be generated. Rese t the watchdog timer
regularly.
Auto-programming
R8C/2E Group, R8C/2F Group 22. Usage Notes
Rev.1.00 Dec 14, 2007 Page 324 of 332
REJ09B0349-0100
NOTES:
1. Do not use the address match interrupt while a command is execu tin g because the vector of the
address match interrupt is allocated in ROM.
2. Do not use a non-maskable interrupt while block 0 is being automatically erased because the fixed
vector is allocated in block 0.
Table 22.2 EW1 Mode Interrupt
Mode Status When Maskable Interrupt
Request is Acknowledged
When W atchdog Timer , Oscillation S top
Detection, V olt age Monitor 1, or V oltage
Monitor 2 Interrupt Request is
Acknowledged
EW1 During auto-erasure
(erase-suspend
function enabled)
Auto-erasure is suspended after
td(SR-SUS) and interrupt
handling is executed. Auto-
erasure can be restarted by
setting the FMR41 bit in the
FMR4 register to 0 (era se rest art)
after interrupt handling
completes.
Once an interrupt request is
acknowledged, auto-programming or
auto-erasure is forcibly stopped
immediately and the flash memory is
reset. Interrupt ha ndling starts after the
fixed period and the flash memory
restarts. Since the block during auto-
erasure or the ad d r e ss du rin g auto-
programming is forcibly stopped, the
normal value may not be read. Execute
auto-erasure again and ensu re it
completes normally.
Since the watchdog timer does not stop
during the command operation,
interrupt requests may be generated.
Reset the watchdog timer regularly
using the erase-suspend function.
During auto -erasure
(erase-suspend
function disabled )
Auto-erasure has priority and the
interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-erasure
completes.
During auto-
programming
(program suspend
function enabled)
Auto-programming is suspended
after td(SR-SUS) and interrupt
handling is executed.
Auto-programming can be
restarted by setting the FMR42 bit
in the FMR4 register to 0
(program restart) after interrupt
handling completes.
During auto-
programming
(program suspend
function disabled )
Auto-programming has priority
and the interrupt request
acknowledgement is put on
standby. Interrupt handling is
executed after auto-programming
completes.
R8C/2E Group, R8C/2F Group 22. Usage Notes
Rev.1.00 Dec 14, 2007 Page 325 of 332
REJ09B0349-0100
22.7.1.4 How to Access
Write 0 before writing 1 when setting the FMR01, FMR02, or FMR11 bit to 1. Do not generate an interrupt
between writing 0 and 1.
22.7.1.5 Rewriting User ROM Area
In EW0 Mode, if the supply voltage drops while rewriting any block in which a rewrite control program is
stored, it may not be possible to rewrite the flash memory because the rewrite control program cannot be
rewritten correctly. In this case, use standard serial I/O mode.
22.7.1.6 Program
Do not write additions to the already programmed address.
22.7.1.7 Entering Stop Mode or Wait Mode
Do not enter stop mode or wait mode during erase-suspend.
22.7.1.8 Program and Erase Voltage for Flash Memory
To perform programming and erasure, use VCC = 2.7 V to 5.5 V as the supply voltage. Do not perform
programming and erasure at less than 2.7 V.
R8C/2E Group, R8C/2F Group 22. Usage Notes
Rev.1.00 Dec 14, 2007 Page 326 of 332
REJ09B0349-0100
22.8 Notes on Noise
22.8.1
Inserting a Byp ass Cap acitor between VCC and VSS Pins as a Countermeasure
against Noise and Latch-up
Connect a bypass capacitor (at least 0.1 µF) using the shortest and thickest write possible.
22.8.2 Countermeasures against Noise Error of Port Control Registers
During rigorous noise testing or the like, external noise (mainly power supply system noise) can exceed the
capacity of the MCU's internal noise control circuitry. In such cases the contents of the port related registers
may be changed.
As a firmware countermeasure, it is recommended that the port registers, port direction registers, and p ull-up
control registers be reset periodically. However, examine the control processing fully before introducing the
reset routine as conflicts may be created between the reset routine and interrupt routines.
R8C/2E Group, R8C/2F Group 23. Notes for On-Chip Debugger
Rev.1.00 Dec 14, 2007 Page 327 of 332
REJ09B0349-0100
23. Notes for On-Chip Debugger
When using the on-chip debugger to develop and debug programs for the R8C/2E Group and R8C/2F Group take note
of the following.
(1) Some of the user flash memory and RAM areas are used by the on-ship debugger. These areas cannot be
accessed by the user.
Refer to the on-chip debugger manual for which areas are used.
(2) Do not set the address match interrupt (registers AIER, RMAD0, and RMAD1 and fixed vector tables) in a
user system.
(3) Do not use the BRK instruction in a user system.
(4) Debugging is available under the condition of supply voltage VCC = 2.7 to 5.5 V. Debugging with the on-chip
debugger under less than 2.7 V is not allowed.
Connecting and usin g the on-chip debugger has so me special restrictions. Refer to the on-chip deb ugger manual for
details.
R8C/2E Group, R8C/2F Group Appendix 1. Package Dimensions
Rev.1.00 Dec 14, 2007 Page 328 of 332
REJ09B0349-0100
Appendix 1. Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
y
Index mark
*3
F
32
25
24 17
16
9
81
*1
*2
x
b
p
e
H
E
E
D
H
D
Z
D
Z
E
Detail F
L
1
L
A
c
A
2
A
1
Previous CodeJEITA Package Code RENESAS Code
PLQP0032GB-A 32P6U-A
MASS[Typ.]
0.2gP-LQFP32-7x7-0.80
1.0
0.125
0.35
0.7
0.7
0.20
0.20
0.145
0.09
0.420.370.32
MaxNomMin
Dimension in Millimeters
Symbol
Reference
7.17.06.9
D
7.17.06.9
E
1.4
A
2
9.29.08.8
9.29.08.8
1.7
A
0.20.1
0
0.70.50.3
L
x
8°0°
c
0.8
e
0.10
y
H
D
H
E
A
1
b
p
b
1
c
1
Z
D
Z
E
L
1
Terminal cross section
b
1
c
1
bp
c
R8C/2E Group, R8C/2F GroupAppendix 2. Connection Examples between Serial Writer and On-Chip Debugging
Rev.1.00 Dec 14, 2007 Page 329 of 332
REJ09B0349-0100
Appendix 2. Connection Examples between Serial Writer and On-Chip
Debugging Emulator
Appendix Figure 2.1 shows a Connection Example with M16C Flash Starter (M3A-0806) and Appendix Figure 2.2
shows a Connection Example with E8 Emulator (R0E000080KCE00).
Appendix Figure 2.1 Connection Example with M16C Flash Starter (M3A-0806)
Appendix Figure 2.2 Connection Example with E8 Emulator (R0E000080KCE00)
NOTES:
1. An oscillation circ uit must be connected, even when operating with t he on-chip oscillator cl ock.
2. For devel opment too ls only.
RXD 4
7 VSS
1 VCC
10
M16C Flash Starter
(M3A-0806)
RXD
TXD
VSS
VCC
TXD
RESET
MODE
Connect osc illation circuit(1)
29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
5
7
8
1
2
3
4
6
24
23
22
21
20
19
18
17
R8C /2E Group,
R8C/2F Group
(2)
(2)
NOTE:
1. It is not nece ss ar y to connect an osci llation circuit when
operating with the on-c hip os cillator clock.
MODE
4.7kΩ ±10%
E8 emulator
(R0E000080KCE00)
RESET
12
10
8
6
4
2
VSS
13
7 MODE
VCC
14
VSS
VCC
Connect oscillation circuit(1)
29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
5
7
8
1
2
3
4
6
24
23
22
21
20
19
18
17
R8C/2E Group,
R8C/2F Group
4.7kΩ or more
Open collector buffer
User logic
R8C/2E Group, R8C/2F Group Appendix 3. Example of Oscillation Evaluation Circuit
Rev.1.00 Dec 14, 2007 Page 330 of 332
REJ09B0349-0100
Appendix 3. Example of Oscillation Evaluation Circuit
Appendix Figure 3.1 shows an Example of Oscillation Evaluation Circuit.
Appendix Figure 3.1 Example of Oscillation Evaluation Circuit
Connect
oscillation
circuit
NOTE:
1. After reset, t he XIN clock stops.
Write a program to oscillate the XIN clock.
VSS
VCC
RESET
29
28
27
26
25
32
31
30
9
10
11
12
13
14
15
16
5
7
8
1
2
3
4
6
24
23
22
21
20
19
18
17
R8C/2E G roup,
R8C/2F Group
Rev.1.00 Dec 14, 2007 Page 331 of 332
REJ09B0349-0100
R8C/2E Group, R8C/2F Group Index
[ A ]
ACCR0 to ACCR1 ....................................................... 255, 258
ACMR .................................................................................. 259
AD ....................................................................................... 242
ADCON0 ............................................................................. 241
ADCON1 ............................................................................. 242
ADCON2 ............................................................................. 242
ADIC ...................................................................................... 95
AIER .................................................................................... 110
[ C ]
CM0 ....................................................................................... 67
CM0IC ................................................................................... 96
CM1 ....................................................................................... 68
CM1IC ................................................................................... 96
CSPR .................................................................................. 117
[ D ]
DA0 to DA1 ......................................................................... 254
DACON ............................................................................... 254
[ F ]
FMR0 .................................................................................. 273
FMR1 .................................................................................. 274
FMR4 .................................................................................. 275
FRA0 ..................................................................................... 70
FRA1 ..................................................................................... 70
FRA2 ..................................................................................... 70
FRA7 ..................................................................................... 71
[ I ]
INT0IC ................................................................................... 97
INT1IC ................................................................................... 97
INT3IC ................................................................................... 97
INTEN ................................................................................. 104
INTF .................................................................................... 105
[ K ]
KIEN .................................................................................... 108
KUPIC ................................................................................... 95
[ L ]
LINCR ................................................................................. 226
LINST .................................................................................. 227
[ O ]
OCD ...................................................................................... 69
OFS ....................................................................... 26, 117, 268
[ P ]
P1DRR .................................................................................. 51
PDi (i = 0, 1, and 3 to 5) ........................................................ 48
Pi (i = 0, 1, and 3 to 5) ........................................................... 49
PINSR2 ................................................................................. 50
PINSR3 ................................................................................. 50
PM0 ....................................................................................... 63
PM1 ....................................................................................... 63
PMR .............................................................................. 50, 212
PRCR .................................................................................... 89
PUR0 ..................................................................................... 51
PUR1 .....................................................................................51
[ R ]
RMAD0 ................................................................................110
RMAD1 ................................................................................110
[ S ]
S0RIC .................................................................................... 95
S0TIC .................................................................................... 95
[ T ]
TRA ..................................................................................... 124
TRACR ................................................................................ 123
TRAIC .................................................................................... 95
TRAIOC ....................................... 123, 125, 128, 130, 132, 135
TRAMR ................................................................................ 124
TRAPRE ..............................................................................124
TRBCR ................................................................................ 139
TRBIC .................................................................................... 95
TRBIOC ............................................... 140, 142, 146, 149, 153
TRBMR ................................................................................ 140
TRBOCR ............................................................................. 139
TRBPR ................................................................................ 141
TRBPRE ..............................................................................141
TRBSC ................................................................................ 141
TRC ..................................................................................... 166
TRCCR1 ...................................................... 163, 186, 190, 195
TRCCR2 ..............................................................................167
TRCDF ................................................................................ 168
TRCGRA ............................................................................. 166
TRCGRB ............................................................................. 166
TRCGRC ............................................................................. 166
TRCGRD ............................................................................. 166
TRCIC .................................................................................... 96
TRCIER ............................................................................... 164
TRCIOR0 ............................................................. 170, 179, 184
TRCIOR1 ............................................................. 170, 180, 185
TRCMR ................................................................................ 162
TRCOER ............................................................................. 169
TRCSR ................................................................................ 165
TRECR1 ..............................................................................203
TRECR2 ..............................................................................204
TRECSR .............................................................................. 204
TREIC .................................................................................... 95
TREMIN ............................................................................... 203
TRESEC .............................................................................. 203
[ U ]
U0BRG ................................................................................210
U0C0 ................................................................................... 211
U0C1 ................................................................................... 212
U0MR .................................................................................. 210
U0RB ...................................................................................209
U0TB ................................................................................... 209
[ V ]
VCA1 .....................................................................................33
VCA2 ...............................................................................33, 71
VW1C .................................................................................... 34
VW2C .................................................................................... 35
Index
Rev.1.00 Dec 14, 2007 Page 332 of 332
REJ09B0349-0100
R8C/2E Group, R8C/2F Group Index
[ W ]
WDC .................................................................................... 116
WDTR ................................................................................. 116
WDTS .................................................................................. 116
C - 1
REVISION HISTORY R8C/2E Group, R8C/2F Group Hardware Manual
Rev. Date Description
Page Summary
0.01 Nov 17, 2006 −First Edition issued
0.03a May 31, 2007 −“RENESAS TECHNICAL UPDATE” reflected:
TN-16C-A16 4A/E, TN-16C-A167 A /E
25 Figure 5.3 re vise d
26 Figure 5. 4 NOT E 1 revised
29 5.2 and Figure 5.7 revised
33 Figure 6.4; VCA2 register NOTE5 revised
56 Table 7.18 revised
67 10 revised
68 Figure 10.1 rev ised
72 Figure 10.5 FRA1 register revised
73 Figure 10.6 NOTE5 revised
74 Figure 10.7 added
79 10.4.1.3 revised
83 10.4.2.5 and Figure 10.10 revised
85 Figure 10.11 revised
87 10.5.1 revised
94 12.1.3.1 revised
106 12.2.1 revised
111 Table 12.6 revised
114 1 2.6.4 deleted
115 Figure 12.19 NOTE 2 re vise d
119 Figure 13.3 OFS register NOTE1 revised
128 Figure 14.5; “Following conditions” revised
139 14.1.6 revised
142 Fig ur e 14.14 TRBMR register revised
143 Figure 14.15 TRBPR register; NOTE2 revised
146 Figure 14.17; “Following conditions” revised
154 Table 14.10 revised
157 to 160 14.2.5.1 to 14.2.5.4 added
212 Figure 15.4 U0MR to U1MR Register NOTE2 deleted
222 Table 15.5 NOTE2 added
233 Figure 16.6 revised
234 Figure 16.7; “B0CLR“bit name revised
236 Figure 16.9 revised
238 Figure 16.11; “BCDCT” flag name revised.
255 17.7 revised
267 Table 20.2 revised
R8C/2E Group, R8C/2F Group Hardware Manual
REVISION HISTORY
C - 2
REVISION HISTORY R8C/2E Group, R8C/2F Group Hardware Manual
0.03a May 31, 2007 271 Figure 20.4 NOTE1 revised
272 Table 20.3 revised
274 20.4.2.4 revised
275 20.4.2.1 5 revised
276 Figure 20.5 revised
278 Figure 20.7 NOTE5 revised
280 Figure 20.9 revised
281 Figure 20.11 revised
283 20.4.3.4 revised
284 Figure 20.13 revised
286 Figure 20.15 revised
288 Table 20.6; “FRM00 Register” → “FRM0 Register” revised
303 Table 21.11 revised
313 22.2.4 deleted
314 Figure 22.1 NOTE2 revised
316 22.3.1 revised
317 to 320 21.3.2.1 to 21.3.2.4 added
325 22.6 revised
332 Appendix Figure 2.1 NOTE2 deleted
333 Appendix Figure 3.1 NOTE1 revised
0.10 Aug 01, 2007 2, 4 Table 1.1 and Table 1.3; “Serial Interface” revised
3, 5 Table 1.2 and Table 1.4; revised specifications of “Operating Frequency/
Supply Voltage” and “Current consumption”
6 Table 1.5 and Figure 1.1; “factory programming product” added
7 Table 1.6 and Figure 1.2; “factory programming product” added
8 Figure 1.3 “UART or clock synchronous ser i a l I/O (8 bits × 1)” revised
9 Figure 1.4 revised
10 Table 1.7 revised
11 Table 1. 8 revised
15 Figure 3.1 re vise d
16 Figure 3.2 re vise d
18 Table 4. 2; - 0053h “S1TIC register” de le te d,
- 0054h “S1RIC register” deleted
19 Table 4.3; - 00A8h “U1MR register” delet ed,
- 00A9h “U1BRG register” deleted,
- 00AAh to 00ABh “U1TB register” deleted,
- 00ACh “U1C0 regist e r” deleted,
- 00ADh “U1C1 regist e r” deleted,
- 00AEh to 00AFh “U1RB register” deleted
20 Table 4. 4; - 00F5h “PINSR1 regis te r” deleted
Rev. Date Description
Page Summary
C - 3
REVISION HISTORY R8C/2E Group, R8C/2F Group Hardware Manual
0.10 Aug 01, 2007 29 Figure 5.7 revised
43 Figure 7.1 P1_0 to P1_3 and P1_4 revised
44 Figure 7.2 re vise d
50 Figure 7.9 PINSR1 register deleted, Figur e 7. 10 PMR register revised
52 Table 7.4 revised
53 Table 7.9 revised
59 Table 7.30 and Table 7.31 revised, Table 7.32 revised
60 Table 7.33 revised
65 Table 10.1 NOTE2 revised
66 Figure 10.1 rev ised
77 10.4.1.3 “low-speed clock mode” → “low-speed on-chip oscillator mode”
revised
94 Table 12 .2 revised
95 Figure 12.3 Registers S1TIC and S1RIC deleted
103 Figure 12.11 revised
138 14.2 “The reload register and counter are allocated at the same
address.” deleted
141 Figure 14.15
“Programmable one-shot generation mode” mode name revised
203 Figure 14.64 revised
207 to 223 15. Serial Interface; “UART1” deleted
(“UARTi (i = 0 or 1)” → “UART0” and “i (i = 0 or 1)” → “0” revised)
207 Figure 15.1 revised
208 Figure 15.2 revised
209 Figure 15.3 U1TB register and U1RB register deleted
210 Figure 15.4 U1BRG register and U1MR register deleted, U0MR register
NOTE1 revised
211 Figure 15.5 U1C0 register deleted
212 Figure 15.6 U1C1 register deleted, Figure 15.7 PMR register revised
213 Table 15.1 revised
214 Table 15.2 and Table 15.3 revised
215 Figure 15.8 revised
216 Figure 15.9 and Figure 15.10 revised
218 Table 15.4 revised
219 Table 15.5 and Table 15.6 revised
220 Figure 15.11 revised
221 Figure 15.12 revised
222 Figure 15.13 revised
223 15.3 revised
224 Figure 16.1 revised
Rev. Date Description
Page Summary
C - 4
REVISION HISTORY R8C/2E Group, R8 C/2F Group Hardware Manual
0.10 Aug 01, 2007 229 Figure 16.5 revised
230 Figure 16.6 “Zero to one cycle of” revised
233 Figure 16.9 revised
236 Figure 16.12 revised
294 Table 21.2 revised
296 Table 21.5 and Table 21.6 revised
297 Table 21.7 revised
298 Table 21.8 NOTE4 added
299 Table 21.10 and Figure 21.3 revised
301 Table 21.14 re vise d
304 Table 21.18 and Figure 21.6 “i (i = 0 or 1)” → “0” revised
305 Table 21.20 re vise d
308 Table 21.24 and Figure 21.10 “i (i = 0 or 1)” → “0” rev i se d
320 22.4 “i (i = 0 or 1)” → “0” revised
327 23 (1) deleted
329 Appendix Figure 2.1 NOTE2 added, Appendix Figure 2.2 revised
1.00 Dec 14, 2007 All pages “Under development” deleted
2, 4 Table 1.1 and Table 1.3 “Int er ru p ts” revised
6, 7 Table 1.5 and Table 1.6 “(D) ” de let ed
15, 16 Figure 3.1 and Figure 3. 2 “Expande d ar ea” deleted
17 Table 4. 1 “002Ch” added
29 5.2 “2.5 V” → “2.6 V” revised
66 Figure 10.1 rev is ed
71 Figure 10.6 “FR A 7 Re gist er ” ad d ed
74 10.2.2 revised
75 10.3.8 added
79 Table 10 .3 rev ised
94 Table 12 .2 rev ised
122 Figure 14.1 “TSTART” → “TCSTF” revised
170 Figure 14.36 TRCIOR0: b3 revised, NOTE4 added
177 14.3.4 and Table 14.16 revised
178 Figure 14.42 revised
179 Fig ur e 14 .4 3 b3 rev ise d, NOTE3 added
184 Fig ur e 14 .4 7 b3 rev ise d
233 Figure 16.9 revised
250 Figure 17.10 revised
294 Table 21.2 IOH(sum) and NOTE2 revised
300 Table 21.11 Symbol “fOCO40M”: Parameter added
Rev. Date Description
Page Summary
R8C/2E Group, R8C/2F Group Ha rdware Manual
Publication Date: Rev.0.01 Nov 17, 2006
Rev.1.00 Dec 14, 2007
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
© 2007. Renesas Technology Corp., All rights reserved. Printed in Japan
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
R8C/2E Group, R8C/2F Group
REJ09B0349-0100
Hardware Manual
