True 3.0V to 5.5V RS-232 Transceivers
SP3222E / SP3232E
1/21
REV 1.0.3
FEATURES
■ Meets true EIA/TIA-232-F standards from
a 3.0V to 5.5V power supply
■ Minimum 120kbps data rate under full load
■ 1μA low power shutdown with receivers
active (SP3222E)
■ Interoperable with RS-232 down to a 2.7V
power source
■ Enhanced ESD specifications:
■ ±15kV Human Body Model
■ ±15kV IEC61000-4-2 Air Discharge
■ ±8kV IEC61000-4-2 Contact
Discharge
Description
The SP3222E and SP3232E series are RS-232 transceiver solutions
intended for portable or hand-held applications such as notebook
or palmtop computers. The SP3222E / SP3232E series has a high-
efficiency, charge-pump power supply that requires only 0.1µF
capacitors in 3.3V operation. This charge pump allows the SP3222E
/ SP3232E series to deliver true RS-232 performance from a single
power supply ranging from 3.0V to 5.5V. The SP3222E / SP3232E
are 2-driver / 2-receiver devices. This series is ideal for portable or
hand-held applications such as notebook or palmtop computers. The
ESD tolerance of the SP3222E / SP3232E devices are over ±15kV
for both Human Body Model and IEC61000-4-2 Air discharge test
methods. The SP3222E device has a low-power shutdown mode
where the devices’ driver outputs and charge pumps are disabled.
During shutdown, the supply current falls to less than 1µA.
Typical Applications
Ordering Information - Page 21
SP3222E
2
4
6
5
3
7
19
GND
T1IN
T2IN
T1OUT
T2OUT
C1+
C1-
C2+
C2-
V+
V-
VCC
13
12
0.1µF
0.1µ F
0.1µF
+
C2
C5
C1
+
+
*C3
C4
+
+
0.1µF
0.1µF
8
17
RS-232
OUTPUTS
RS-232
INPUTS
LOGIC
INPUTS
V
CC
18
1
5kΩ
R1IN
R1OUT
15
9
5kΩ
R2IN
R2OUT
10
16
LOGIC
OUTPUTS
EN 20
SHDN
*can be retur
ned to
either VCC
or GND
SSOP
TSSOP
SP3222E
2
4
6
5
3
7
17
GND
T1IN
T2IN
T1OUT
T2OUT
C1+
C1-
C2+
C2-
V+
V-
VCC
12
11
0.1µF
0.1µF
0.1µF
+
C2
C5
C1
+
+
*C3
C4
+
+
0.1µF
0.1µF
8
15
RS-232
OUTPUTS
RS-232
INPUTS
LOGIC
INPUTS
V
CC
16
1
5kΩ
R1IN
R1OUT
13
9
5kΩ
R2IN
R2OUT
10
14
LOGIC
OUTPUTS
EN 18
SHDN
*can be retur
ned to
either VCC
or GND
SOIC
SP3232E
1
3
5
4
2
6
16
GND
T1IN
T2IN
T1OUT
T2OUT
C1+
C1-
C2+
C2-
V+
V-
VCC
11
10
0.1µF
+
C2
C5
C1
+
+*C3
C4
+
+
14
7RS-232
OUTPUTS
RS-232
INPUTS
LOGIC
INPUTS
V
CC
15
5kΩ
R1IN
R1OUT
12 13
5kΩ
R2IN
R2OUT
98
LOGIC
OUTPUTS
*can be retur
ned to
either VCC or GND
0.1µF
0.1µF
0.1µF
0.1µF
SP3222E / SP3232E
2/21
REV 1.0.3
Absolute Maximum Ratings
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may affect
reliability and cause permanent damage to the device.
VCC..................................................................-0.3V to 6.0V
V+(1).................................................................-0.3V to 7.0V
V-(1)..................................................................0.3V to -7.0V
V+ + |V-|(1).......................................................................13V
ICC (DC VCC or GND current).................................±100mA
Input Voltages
TxIN, EN, SHDN.................................-0.3V to (VCC + 0.3V)
RxIN.............................................................................±25V
Output Voltages
TxOUT......................................................................±13.2V
RxOUT...............................................-0.3V to (VCC + 0.3V)
Electrical Characteristics
Unless otherwise noted, the following specifications apply for VCC = 3.0V to 5.5V with TAMB = TMIN to TMAX, typical values
apply at VCC = 3.3V or 5.0V and TAMB = 25°C.
PARAMETERS MIN. TYP. MAX. UNITS CONDITIONS
DC Characteristics
Supply current 0.3 1.0 mA no load, VCC = 3.3V,
TAMB = 25oC, TxIN = GND or VCC
Shutdown supply current 1.0 10 µA SHDN = GND, VCC = 3.3V,
TAMB = 25oC, TxIN = Vcc or GND
Logic Inputs and Receiver Outputs
Input logic threshold LOW 0.8 V TxIN, EN, SHDN(2)
Input logic threshold HIGH 2.0 VCC V VCC = 3.3V(2)
Input logic threshold HIGH 2.4 VCC V VCC = 5.0V(2)
Input leakage current +0.01 +1.0 µA TxIN, EN, SHDN,
TAMB = 25oC, VIN = 0V to VCC
Output leakage current +0.05 +10 µA Receivers disabled, VOUT = 0V to VCC
Output voltage LOW 0.4 V IOUT = 1.6mA
Output voltage HIGH VCC - 0.6 VCC - 0.1 V IOUT = -1.0mA
Driver Outputs
Output voltage swing +5.0 +5.4 V All driver outputs loaded with 3kΩ to GND,
TAMB = 25oC
Output resistance 300 ΩVCC = V+ = V- = 0V, TOUT = +2V
Output short-circuit current +35 +60 mA VOUT = 0V
Output leakage current +25 µA VCC = 0V or 3.0V to 5.5V,
VOUT = +12V, drivers disabled
Short-Circuit Duration
TxOUT................................................................Continuous
Storage Temperature.................. ...............-65˚C to +150˚C
Power Dissipation per package
20-pin SSOP (derate 9.25mW/°C above 70°C).......750mW
18-pin SOIC (derate 15.7mW/°C above 70°C).......1260mW
20-pin TSSOP (derate 11.1mW/°C above 70°C).....890mW
16-pin SSOP (derate 9.69mW/°C above 70°C).......775mW
16-pin PDIP (derate 14.3mW/°C above 70°C).......1150mW
16-pin WSOIC (derate 11.2mW/°C above 70°C).....900mW
16-pin TSSOP (derate 10.5mW/°C above 70°C).....850mW
16-pin NSOIC (derate 13.57mW/°C above 70°C)..1086mW
NOTE:
1. V+ and V- can have maximum magnitudes of 7V, but their absolute dier-
ence cannot exceed 13V.
SP3222E / SP3232E
3/21
REV 1.0.3
Electrical Characteristics (Continued)
Unless otherwise noted, the following specifications apply for VCC = 3.0V to 5.5V with TAMB = TMIN to TMAX, typical values
apply at VCC = 3.3V or 5.0V and TAMB = 25°C.
PARAMETERS MIN. TYP. MAX. UNITS CONDITIONS
Receiver Inputs
Input voltage range -15 15 V
Input threshold LOW 0.6 1.2 V VCC = 3.3V
Input threshold LOW 0.8 1.5 V VCC = 5.0V
Input threshold HIGH 1.5 2.4 V VCC = 3.3V
Input threshold HIGH 1.8 2.4 V VCC = 5.0V
Input hysteresis 0.3 V
Input resistance 3 5 7 kΩ
Timing Characteristics
Maximum data rate 120 235 kbps RL = 3kΩ, CL = 1000pF, one driver switching
Driver propagation delay, tPHL 1.0 µs RL = 3kΩ, CL = 1000pF
Driver propagation delay, tPLH 1.0 µs RL = 3kΩ, CL = 1000pF
Receiver propagation delay, tPHL 0.3 µs Receiver input to receiver output, CL = 150pF
Receiver propagation delay, tPLH 0.3 µs Receiver input to receiver output, CL = 150pF
Receiver output enable time 200 ns
Receiver output disable time 200 ns
Driver skew 100 500 ns | tPHL - tPLH |, TAMB = 25°C
Receiver skew 200 1000 ns | tPHL - tPLH |
Transition-region slew rate 30 V/µs
VCC = 3.3V, RL = 3kΩ, CL = 1000pF,
TAMB = 25°C, measurements taken from
-3.0V to 3.0V or 3.0V to -3.0V
NOTE:
2. Driver input hysteresis is typically 250mV.
SP3222E / SP3232E
4/21
REV 1.0.3
Typical Performance Characteristics
Unless otherwise noted, the following performance characteristics apply for VCC = 3.3V, 120kbps data rate, all drivers
loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = 25°C.
Figure 1: Transmitter Output Voltage vs Load Capacitance
for the SP3222E and SP3232E
Figure 2: Slew Rate vs Load Capacitance
for the SP3222E and SP3232E
Figure 3: Supply Current VS. Load Capacitance
when Transmitting Data
6
4
2
0
-2
-4
-6
Transmitter Output Voltage [V]
Load Capacitance [pF]
Vout+
Vout-
500 1000 1500 2000
0
14
12
10
8
6
4
2
0
Slew Rate [V /µs ]
Load Capacitance [pF]
+Slew
-Slew
0 500 1000 1500 2000
2330
50
45
40
35
30
25
20
15
10
5
0
Suppl y Current [mA]
Load Capacitance [pF]
118KHz
60KHz
10KHz
0 500 1000 1500 2000 2330
SP3222E / SP3232E
5/21
REV 1.0.3
Pin Functions
Pin Name Pin Function / Description
Pin Number
SP3222E
SP3232E
SOIC SSOP
TSSOP
EN Receiver Enable. Apply logic LOW for normal operation.
Apply logic HIGH to disable the receiver outputs (high-Z state). 1 1 -
C1+ Positive terminal of the voltage doubler charge-pump capacitor 2 2 1
V+ 5.5V output generated by the charge pump 3 3 2
C1- Negative terminal of the voltage doubler charge-pump capacitor 4 4 3
C2+ Positive terminal of the inverting charge-pump capacitor 5 5 4
C2- Negative terminal of the inverting charge-pump capacitor 6 6 5
V- -5.5V output generated by the charge pump 7 7 6
T1OUT RS-232 driver output 15 17 14
T2OUT RS-232 driver output 8 8 7
R1IN RS-232 receiver input 14 16 13
R2IN RS-232 receiver input 9 9 8
R1OUT TTL/CMOS receiver output 13 15 12
R2OUT TTL/CMOS receiver output 10 10 9
T1IN TTL/CMOS driver input 12 13 11
T2IN TTL/CMOS driver input 11 12 10
GND Ground 16 18 15
VCC 3.0V to 5.5V supply voltage 17 19 16
SHDN Shutdown Control Input. Drive HIGH for normal device operation.
Drive LOW to shutdown the drivers (high-Z output) and the on-board power supply. 18 20 -
N.C. No connect - 11, 14 -
Table 1: Device Pin Description
SP3222E / SP3232E
6/21
REV 1.0.3
Pinouts
V-
1
2
3
417
18
19
20
5
6
7
16
15
14
SHDN
C1+
V+
C1-
C2+
C2-
N.C.
EN
R1IN
GND
V
CC
T1OUT
N.C.
8
9
10 11
12
13
R2IN
R2OUT
SP3222E
T2OUT T1IN
T2IN
R1OUT
SSOP/TSSOP
V-
1
2
3
415
16
17
18
5
6
7
14
13
12
SHDN
C1+
V+
C1-
C2+
C2-
EN
R1IN
GND
V
CC
T1OUT
8
910
11
R2IN
SP3222E
T2OUT T2IN
T1IN
R1OUT
SOIC
R2OUT
Figure 4: Pinout Configurations for the SP3222E
V-
1
2
3
413
14
15
16
5
6
7
12
11
10
C1+
V+
C1-
C2+
C2-
R1IN
R2IN
GND
VCC
T1OUT
T2IN
89
SP3232E
T1IN
R1OUT
R2OUT
T2OUT
Figure 5: Pinout Configurations for the SP3232E
SP3222E / SP3232E
7/21
REV 1.0.3
Typical Operating Circuits
Figure 6: SP3222E Typical Operating Circuits
Figure 7: SP3232E Typical Operating Circuit
SP3222E
2
4
6
5
3
7
19
GND
T1IN
T2IN
T1OUT
T2OUT
C1+
C1-
C2+
C2-
V+
V-
VCC
13
12
0.1µF
0.1µ F
0.1µF
+
C2
C5
C1
+
+
*C3
C4
+
+
0.1µF
0.1µF
8
17
RS-232
OUTPUTS
RS-232
INPUTS
LOGIC
INPUTS
V
CC
18
1
5kΩ
R1IN
R1OUT
15
9
5kΩ
R2IN
R2OUT
10
16
LOGIC
OUTPUTS
EN 20
SHDN
*can be retur
ned to
either VCC
or GND
SSOP
TSSOP
SP3222E
2
4
6
5
3
7
17
GND
T1IN
T2IN
T1OUT
T2OUT
C1+
C1-
C2+
C2-
V+
V-
VCC
12
11
0.1µF
0.1µF
0.1µF
+
C2
C5
C1
+
+
*C3
C4
+
+
0.1µF
0.1µF
8
15
RS-232
OUTPUTS
RS-232
INPUTS
LOGIC
INPUTS
V
CC
16
1
5kΩ
R1IN
R1OUT
13
9
5kΩ
R2IN
R2OUT
10
14
LOGIC
OUTPUTS
EN 18
SHDN
*can be retur
ned to
either VCC
or GND
SOIC
SP3232E
1
3
5
4
2
6
16
GND
T1IN
T2IN
T1OUT
T2OUT
C1+
C1-
C2+
C2-
V+
V-
VCC
11
10
0.1µF
+
C2
C5
C1
+
+*C3
C4
+
+
14
7RS-232
OUTPUTS
RS-232
INPUTS
LOGIC
INPUTS
V
CC
15
5kΩ
R1IN
R1OUT
12 13
5kΩ
R2IN
R2OUT
98
LOGIC
OUTPUTS
*can be retur
ned to
either V
CC
or GND
0.1µF
0.1µF
0.1µF
0.1µF
SP3222E / SP3232E
8/21
REV 1.0.3
Applications Information
The SP3222E / SP3232E transceivers meet the
EIA/TIA-232 and ITU-T V.28/V.24 communication protocols
and can be implemented in battery-powered, portable,
or hand-held applications such as notebook or palmtop
computers. The SP3222E / SP3232E devices feature
MaxLinear’s proprietary on-board charge pump circuitry
that generates 5.5V for RS-232 voltage levels from a single
3.0V to 5.5V power supply. This series is ideal for 3.3V-only
systems, mixed 3.3V to 5.5V systems, or 5.0V-only systems
that require true RS-232 performance. The SP3222E
/ SP3232E devices can operate at a typical data rate of
235kbps when fully loaded.
The SP3222E and SP3232E are 2-driver / 2-receiver
devices ideal for portable or hand-held applications. The
SP3222E features a 1µA shutdown mode that reduces
power consumption and extends battery life in portable
systems. Its receivers remain active in shutdown mode,
allowing external devices such as modems to be monitored
using only 1µA supply current.
Theory of Operation
The SP3222E/SP3232E series is made up of three basic
circuit blocks:
1. Drivers
2. Receivers
3. The MaxLinear proprietary charge pump
Drivers
The drivers are inverting level transmitters that convert
TTL or CMOS logic levels to 5.0V EIA/TIA-232 levels
with an inverted sense relative to the input logic levels.
Typically, the RS-232 output voltage swing is 5.4V with
no load and 5V minimum fully loaded. The driver outputs
are protected against infinite short-circuits to ground
without degradation in reliability. Driver outputs will meet
EIA/TIA-562 levels of ±3.7V with supply voltages as low
as 2.7V.
The drivers can guarantee a data rate of 120kbps fully
loaded with 3kΩ in parallel with 1000pF, ensuring
compatability with PC-to-PC communication software.
The slew rate of the driver is internally limited to a maximum
of 30V/µs in order to meet the EIA standards (EIA
RS-232D 2.1.7, Paragraph 5). The transition of the loaded
output from HIGH to LOW also meet the monotonicity
requirements of the standard.
Figure 8 shows a loopback test circuit used to test the
RS-232 Drivers. Figure 9 shows the test results of the
loopback circuit with all drivers active at 120kbps with
RS-232 loads in parallel with a 1000pF capacitor.
Figure 10 shows the test results where one driver
was active at 235kbps and all drivers loaded with an
RS-232 receiver in parallel with 1000pF capacitors. A
solid RS-232 data transmission rate of 120kbps provides
compatibility with many designs in personal computer
peripherals and LAN applications.
SP3222E
SP3232E
GND
TxIN TxOUT
C1+
C1-
C2+
C2-
V+
V-
VCC
0.1µF
0.1µF
0.1µF
+
C2
C5
C1
+
+
C3
C4
+
+
0.1µF
0.1µ
F
LOGIC
INPUTS
V
CC
5kΩ
RxIN
RxOUT
LOGIC
OUTPUTS
EN* *SHDN
1000pF
VCC
* SP3222E only
Figure 8: SP3222E/SP3232E Driver Loopback Test Circuit
3
1
2
T
T
T
T[]
T1 IN
T1 OUT
R1 OUT
Ch1
Ch3
5.00V Ch2 5.00V M 5.00µs Ch1 0V
5.00V
Figure 9: Loopback Test results at 120kbps
SP3222E / SP3232E
9/21
REV 1.0.3
The SP3222E driver’s output stages are turned off (tri-
state) when the device is in shutdown mode. When the
power is off, the SP3222E device permits the outputs to
be driven up to ±12V. The driver’s inputs do not have pull-
up resistors. Designers should connect unused inputs to
VCC or GND.
In the shutdown mode, the supply current falls to less than
1µA, where SHDN = LOW. When the SP3222E device is
shut down, the device’s driver outputs are disabled (tri-
stated) and the charge pumps are turned off with V+ pulled
down to VCC and V- pulled to GND. The time required to
exit shutdown is typically 100µs. Connect SHDN to VCC if
the shutdown mode is not used.
Receivers
The Receivers convert EIA/TIA-232 levels to TTL or
CMOS logic output levels. The SP3222E receivers have
an inverting tri-state output. These receiver outputs
(RxOUT) are tri-stated when the enable control EN =
HIGH. In the shutdown mode, the receivers can be active
or inactive. EN has no effect on TxOUT. The truth table
logic of the SP3222E driver and receiver outputs can be
found in Table 2.
SHDN EN TxOUT RxOUT
0 0 Tri-state Active
0 1 Tri-state Tri-state
1 0 Active Active
1 1 Active Tri-state
Table 2: SP3222E Truth Table Logic
for Shutdown and Enable Control
3
1
2
T
T
T
T[]
T1 IN
T1 OUT
R1 OUT
Ch1
Ch3
5.00V Ch2 5.00V M 2.50µs Ch1 0V
5.00V
Figure 10: Loopback Test results at 235kbps
Applications Information (Continued)
Since receiver input is usually from a transmission line
where long cable lengths and system interference can
degrade the signal, the inputs have a typical hysteresis
margin of 300mV. This ensures that the receiver is
virtually immune to noisy transmission lines. Should
an input be left unconnected, an internal 5kΩ pulldown
resistor to ground will commit the output of the receiver to
a HIGH state.
Charge Pump
The charge pump is an MaxLinear-patended design (U.S.
5,306,954) and uses a unique approach compared to older
less-efficient designs. The charge pump still requires four
external capacitors, but uses a four-phase voltage shifting
technique to attain symmetrical 5.5V power supplies. The
internal power supply consists of a regulated dual charge
pump that provides output voltages of ±5.5V regardless
of the input voltage (VCC) over the 3.0V to 5.5V range.
In most circumstances, decoupling the power supply can
be achieved adequately using a 0.1µF bypass capacitor
at C5 (refer to figures 6 and 7). In applications that are
sensitive to power-supply noise, decouple Vcc to ground
with a capacitor of the same value as charge-pump
capacitor C1. Physically connect bypass capcitors as
close to the IC as possible.
The charge pump operates in a discontinuous mode
using an internal oscillator. If the output voltages are less
than a magnitude of 5.5V, the charge pump is enabled.
If the output voltages exceed a magnitude of 5.5V, the
charge pump is disabled. This oscillator controls the
four phases of the voltage shifting. A description of each
phase follows.
Phase 1: VSS charge storage
During this phase of the clock cycle, the positive side of
capacitors C1 and C2 are initially charged to VCC. Cl+ is
then switched to GND and the charge in C1– is transferred
to C2–. Since C2+ is connected to VCC, the voltage
potential across capacitor C2 is now 2 times VCC.
Phase 2: VSS transfer
Phase two of the clock connects the negative terminal
of C2 to the VSS storage capacitor and the positive
terminal of C2 to GND. This transfers a negative
generated voltage to C3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to C3, the
positive side of capacitor C1 is switched to VCC and the
negative side is connected to GND.
SP3222E / SP3232E
10/21
REV 1.0.3
Phase 3: VDD charge storage
The third phase of the clock is identical to the first phase;
the charge transferred in C1 produces –VCC in the
negative terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at VCC, the voltage
potential across C2 is 2 times VCC.
Phase 4: VDD transfer
The fourth phase of the clock connects the negative
terminal of C2 to GND, and transfers this positive
generated voltage across C2 to C4, the VDD storage
capacitor. This voltage is regulated to 5.5V. At
this voltage, the internal oscillator is disabled.
Simultaneous with the transfer of the voltage to C4, the
positive side of capacitor C1 is switched to VCC and the
negative side is connected to GND, allowing the charge pump
cycle to begin again. The charge pump cycle will continue
as long as the operational conditions for the internal
oscillator are present.
Since both V+ and V– are separately generated from VCC,
in a no–load condition V+ and V– will be symmetrical.
Older charge pump approaches that generate V– from V+
will show a decrease in the magnitude of V– compared to
V+ due to the inherent inefficiencies in the design.
The clock rate for the charge pump typically operates at
greater than 250kHz. The external capacitors can be as
low as 0.1µF with a 16V breakdown voltage rating.
Applications Information (Continued)
V
CC
= +5V
–5V –5V
+5V
VSS
Storage Capacitor
VDD
Storage Capacitor
C1C2
C3
C4
+
+
++
–
–
––
Figure 11: Charge Pump - Phase 1
V
CC
= +5V
VSS
Storage Capacitor
VDD Storage Capacito
r
C1C2
C3
C4
+
+
++
–
–
––
-5.5V
Figure 12: Charge Pump - Phase 2
Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V
2
1T
T[]
T
+6V
a) C2+
b) C2-
GND
GND
-6V
Figure 13: Charge Pump Waveforms
V
CC
= +5V
–5V –5V
+5V
VSS Storage Capacitor
VDD
Storage Capacitor
C1C2
C3
C4
+
+
++
–
–
––
Figure 14: Charge Pump - Phase 3
V
CC
= +5V
VSS Storage Capacitor
VDD Storage Capacito
r
C1C2
C3
C4
+
+
++
–
–
––
+5.5V
Figure 15: Charge Pump - Phase 4
SP3222E / SP3232E
11/21
REV 1.0.3
ESD Tolerance
The SP3222E / SP3232E Series incorporates ruggedized
ESD cells on all driver output and receiver input pins. The
ESD structure is improved over our previous family for more
rugged applications and environments sensitive to electro-
static discharges and associated transients. The improved
ESD tolerance is at least ±15kV without damage or latch-
up.
There are different methods of ESD testing applied:
a) MIL-STD-883, Method 3015.7
b) IEC61000-4-2 Air-Discharge
c) IEC61000-4-2 Direct Contact
The Human Body Model has been the generally accepted
ESD testing method for semiconductors. This method is
also specified in MIL-STD-883, Method 3015.7 for ESD
testing. The premise of this ESD test is to simulate the
human body’s potential to store electro-static energy and
discharge it to an integrated circuit. The simulation is
performed by using a test model as shown in Figure 16.
This method will test the IC’s capability to withstand an ESD
transient during normal handling such as in manufacturing
areas where the IC’s tend to be handled frequently.
The IEC61000-4-2, formerly IEC801-2, is generally used
for testing ESD on equipment and systems. For system
manufacturers, they must guarantee a certain amount of
ESD protection since the system itself is exposed to the
outside environment and human presence. The premise
with IEC61000-4-2 is that the system is required to withstand
an amount of static electricity when ESD is applied to
points and surfaces of the equipment that are accessible
to personnel during normal usage. The transceiver IC
receives most of the ESD current when the ESD source
is applied to the connector pins. The test circuit for
IEC61000-4-2 is shown on Figure 17. There are two
methods within IEC61000-4-2, the Air Discharge method
and the Contact Discharge method.
Figure 17: ESD Test Circuit for IEC61000-4-2
Figure 16: ESD Test Circuit for Human Body Model
R
S
and
R
V
add up to 330Ω for IEC61000-4-2.
R
C
Device
Under
Test
DC Power
Source
C
S
R
S
SW1 SW2
R
V
Contact-Discharge Model
R
C
Device
Under
Test
DC Power
Source
C
S
R
S
SW1 SW2
SP3222E / SP3232E
12/21
REV 1.0.3
ESD Tolerance (Continued)
With the Air Discharge Method, an ESD voltage is applied to
the equipment under test (EUT) through air. This simulates
an electrically charged person ready to connect a cable onto
the rear of the system only to find an unpleasant zap just
before the person touches the back panel. The high energy
potential on the person discharges through an arcing path to
the rear panel of the system before he or she even touches
the system. This energy, whether discharged directly or
through air, is predominantly a function of the discharge
current rather than the discharge voltage. Variables with an
air discharge such as approach speed of the object carrying
the ESD potential to the system and humidity will tend to
change the discharge current. For example, the rise time of
the discharge current varies with the approach speed.
The Contact Discharge Method applies the ESD current
directly to the EUT. This method was devised to reduce
the unpredictability of the ESD arc. The discharge current
rise time is constant since the energy is directly transferred
without the air-gap arc. In situations such as hand held
systems, the ESD charge can be directly discharged to the
equipment from a person already holding the equipment.
The current is transferred on to the keypad or the serial port
of the equipment directly and then travels through the PCB
and finally to the IC.
The circuit model in Figures 16 and 17 represent the typical
ESD testing circuit used for all three methods. The CS is
initially charged with the DC power supply when the first
switch (SW1) is on. Now that the capacitor is charged,
the second switch (SW2) is on while SW1 switches off.
The voltage stored in the capacitor is then applied through
RS, the current limiting resistor, onto the device under test
(DUT). In ESD tests, the SW2 switch is pulsed so that the
device under test receives a duration of voltage.
t = 0ns t = 30ns
0A
15A
30A
I →
t →
Figure 18: ESD Test Waveform for IEC61000-4-2
For the Human Body Model, the current limiting resistor
(RS) and the source capacitor (CS) are 1.5kΩ an 100pF,
respectively. For IEC-61000-4-2, the current limiting
resistor (RS) and the source capacitor (CS) are 330Ω an
150pF, respectively.
The higher CS value and lower RS value in the IEC61000-
4-2 model are more stringent than the Human Body Model.
The larger storage capacitor injects a higher voltage to the
test point when SW2 is switched on. The lower current
limiting resistor increases the current charge onto the test
point.
DEVICE PIN TESTED HUMAN BODY MODEL IEC61000-4-2
Air Discharge Direct Contact Level
Driver Outputs ±15kV ±15kV ±8kV 4
Receiver Inputs ±15kV ±15kV ±8kV 4
Table 3: Transceiver ESD Tolerance Levels
SP3222E / SP3232E
13/21
REV 1.0.3
Mechanical Dimensions
SSOP20
Drawing No:
Revision: A
Side View
Top View
Front View
POD-00000119
SP3222E / SP3232E
14/21
REV 1.0.3
Mechanical Dimensions
SSOP16
Drawing No:
Revision: A
Side View
Top View
Front View
POD-00000116
SP3222E / SP3232E
15/21
REV 1.0.3
Mechanical Dimensions
WSOIC16
Drawing No: POD-00000115
Revision: B
Side View
Top View
Front View
SP3222E / SP3232E
16/21
REV 1.0.3
Mechanical Dimensions
WSOIC18
Drawing No: POD-00000118
Revision: B
Side View
Top View
Front View
SP3222E / SP3232E
17/21
REV 1.0.3
Mechanical Dimensions
NSOIC16
Drawing No:
Revision: A
Side View
Top View
Front View
POD-00000114
SP3222E / SP3232E
18/21
REV 1.0.3
Mechanical Dimensions
TSSOP16
Drawing No:
Revision: A
Side View
Top View
Front View
POD-00000117
SP3222E / SP3232E
19/21
REV 1.0.3
Mechanical Dimensions
TSSOP20
Drawing No:
Revision: A
Side View
Top View
Front View
POD-00000120
SP3222E / SP3232E
20/21
REV 1.0.3
Ordering Information(1)
Part Number Operating Temperature Range Package Packaging Method Lead-Free(2)
SP3222E
SP3222ECA-L/TR 0°C to +70°C 20 Pin SSOP Reel Yes
SP3222ECT-L/TR 0°C to +70°C 18 Pin WSOIC Reel Yes
SP3222ECY-L/TR 0°C to +70°C 20 Pin TSSOP Reel Yes
SP3222EEA-L/TR -40°C to +85°C 20 Pin SSOP Reel Yes
SP3222EEY-L/TR -40°C to +85°C 20 Pin TSSOP Reel Yes
SP3232E
SP3232ECA-L 0°C to +70°C 16 Pin SSOP Tube Yes
SP3232ECA-L/TR 0°C to +70°C 16 Pin SSOP Reel Yes
SP3232ECN-L 0°C to +70°C 16 Pin NSOIC Tube Yes
SP3232ECN-L/TR 0°C to +70°C 16 Pin NSOIC Reel Yes
SP3232ECT-L/TR 0°C to +70°C 16 Pin WSOIC Reel Yes
SP3232ECY-L 0°C to +70°C 16 Pin TSSOP Tube Yes
SP3232ECY-L/TR 0°C to +70°C 16 Pin TSSOP Reel Yes
SP3232EEA-L -40°C to +85°C 16 Pin SSOP Tube Yes
SP3232EEA-L/TR -40°C to +85°C 16 Pin SSOP Reel Yes
SP3232EEN-L -40°C to +85°C 16 Pin NSOIC Tube Yes
SP3232EEN-L/TR -40°C to +85°C 16 Pin NSOIC Reel Yes
SP3232EET-L -40°C to +85°C 16 Pin WSOIC Tube Yes
SP3232EET-L/TR -40°C to +85°C 16 Pin WSOIC Reel Yes
SP3232EEY-L -40°C to +85°C 16 Pin TSSOP Tube Yes
SP3232EEY-L/TR -40°C to +85°C 16 Pin TSSOP Reel Yes
NOTE:
1. Refer to www.maxlinear.com/SP3222E and www.maxlinear.com/SP3232E for most up-to-date Ordering Information.
2. Visit www.maxlinear.com for additional information on Environmental Rating.
Selection Table
MODEL Power Supplies RS-232
Drivers
RS-232
Receivers
External
Components Shutdown TTL 3-State # of Pins
SP3222E +3.0V to +5.5V 2 2 4 Capacitors Yes Yes 18, 20
SP3232E +3.0V to +5.5V 2 2 4 Capacitors No No 16
SP3222E / SP3232E
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© 2013 - 2020 MaxLinear, Inc. All rights reserved
SP3222E_SP3232E_DS_042220 21/21
REV 1.0.3
Corporate Headquarters:
5966 La Place Court
Suite 100
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Tel.:+1 (760) 692-0711
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Revision History
Revision Date Description
08/22/05 -- Legacy Sipex Datasheet
12/08/10 1.0.0 Convert to Exar Format and update ordering information.
03/14/13 1.0.1 Correct type error to driver Transition-Region Slew Rate
conditions.
10/16/17 1.0.2 Correct SP3222E nSOIC pinout to SOIC. Updated to MaxLinear logo. Up-
dated format and ordering information table.
04/22/20 1.0.3 Change RxIN absolute maximum from ±15V to ±25V. Update Ordering
Information.
