DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT166
8-bit parallel-in/serial-out shift
register
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
FEATURES
•Synchronous parallel-to-serial applications
•Synchronous serial data input for easy expansion
•Clock enable for “do nothing” mode
•Asynchronous master reset
•For asynchronous parallel data load see “165”
•Output capability: standard
•ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
an active LOW parallel enable (PE) input. When PE is
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q0
from serial data input (Ds), and the remaining bits are
shifted one place to the right (Q0→ Q1→ Q2, etc.) with
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q7 output to the Ds input of the succeeding
stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of inputCE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+ ∑ (CL× VCC2 × fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× VCC2× fo) = sum of outputs
CL= output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC − 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/ tPLH propagation delay
CP to Q7
MR to Q7
CL= 15 pF; VCC =5 V 15
14 20
19 ns
ns
fmax maximum clock frequency 63 50 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 41 41 pF
December 1990 3
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1D
s
serial data input
2, 3, 4, 5, 10, 11, 12, 14 D0 to D7parallel data inputs
6CE clock enable input (active LOW)
7 CP clock input (LOW-to-HIGH edge-triggered)
8 GND ground (0 V)
9MR asynchronous master reset (active LOW)
13 Q7serial output from the last stage
15 PE parallel enable input (active LOW)
16 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 4
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑= LOW-to-HIGH CP transition
OPERATING MODES INPUTS Qn REGISTER OUTPUT
PE CE CP DSD0-D7Q0Q1-Q6Q7
parallel load I
II
I↑
↑X
XI- I
h - h L
HL - L
H - H L
H
serial shift h
hI
I↑
↑I
hX - X
X-X L
Hq
0- q5
q0- q5
q6
q6
hold “do nothing” X h X X X - X q0q1 - q6q7
Fig.4 Functional diagram.
December 1990 5
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
Fig.5 Logic diagram.
Fig.6 Typical clear, shift, load, inhibit, and shift sequences.
December 1990 6
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HC VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q7
50
18
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.7
tPHL propagation delay
MR to Q7
47
17
14
160
32
27
200
40
34
240
48
41
ns 2.0
4.5
6.0
Fig.8
tTHL/ tTLH output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.7
tWclock pulse width
HIGH or LOW 80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
tWmaster reset pulse width
LOW 100
20
17
25
9
7
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.8
trem removal time
MR to CP 0
0
0
−19
−7
−6
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.8
tsu set-up time
Dn, CE to CP 80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.9
tsu set-up time
PE to CP 100
20
17
33
12
10
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.8
thhold time
Dn, CE to CP 2
2
2
−8
−3
−2
2
2
2
2
2
2
ns 2.0
4.5
6.0
Fig.8
thhold time
PE to CP 0
0
0
−28
−10
−8
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.9
fmax maximum clock pulse
frequency 6.0
30
35
19
57
68
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7
December 1990 7
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
D0 to D7
Ds
CP
CE
MR
PE
0.35
0.35
0.80
0.80
0.40
0.60
December 1990 8
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q7
23 40 50 60 ns 4.5 Fig.7
tPHL propagation delay
MR to Q7
22 40 50 60 ns 4.5 Fig.8
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.7
tWclock pulse width
HIGH or LOW 20 9 25 30 ns 4.5 Fig.7
tWmaster reset pulse width
LOW 25 11 31 38 ns 4.5 Fig.8
trem removal time
MR to CP 0−7 0 0 ns 4.5 Fig.8
tsu set-up time
Dn, CE to CP 16 8 20 24 ns 4.5 Fig.9
tsu set-up time
PE to CP 30 15 38 45 ns 4.5 Fig.8
thhold time
Dn, CE to CP 0−3 0 0 ns 4.5 Fig.9
thhold time
PE to CP 0−13 0 0 ns 4.5 Fig.9
fmax maximum clock pulse
width 25 45 20 17 MHz 4.5 Fig.7
December 1990 9
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
AC WAVEFORMS
Fig.7 Waveforms showing the clock (CP) to output (Q7) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.
The changing to output assumes internal Q6 opposite state from Q7.
The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3V; VI= GND to 3V.
Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7) propagation delay
and the master reset to clock (CP) removal time.
The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3V; VI= GND to 3V.
December 1990 10
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT166
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds), the data inputs (Dn), the
clock enable input (LOW CE), the clock enable input CE and the parallel enable input to the clock (CP).
The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
CE may change only from HIGH-to-LOW while CP is LOW.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: VM= 1.3V; VI= GND to 3V.
