SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 623 The MC14534B is composed of five BCD ripple counters that have their respective outputs multiplexed using an internal scanner. Outputs of each counter are selected by the scanner and appear on four (BCD) pins. Selection is indicated by a logic high on the appropriate digit select pin. Both BCD and digit select outputs have three-state controls providing an "open-circuit" when these controls are high and allowing multiplexing. Cascading may be accomplished by using the carry-out pin. The counters and scanner can be independently reset by applying a high to the counter master reset (MR) and the scanner reset (SR). The MC14534B was specifically designed for application in real time or event counters where continual updating and multiplexed displays are used. * * * * * * P SUFFIX PLASTIC CASE 709 DW SUFFIX SOIC CASE 751E Four Operating Modes (See truth table) Input Error Detection Circuit Clock Conditioning Circuits for Slow Transition Inputs Counter Sequences on Positive Transition of Clock A Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = - 55 to 125C for all packages. BLOCK DIAGRAM TO CAPACITORS 22 1 VDD = PIN 24 VSS = PIN 12 23 CLOCK B PULSE SHAPER CLOCK A 4 MASTER 2 RESET TENS Cn+4 Q0 ERROR OUT TEST CONTROL UNITS C / 10 3 PULSE ERROR DETECTOR CARRY CONTROL C / 10 Q3 HUNDREDS C / 10 Cn+4 Q0 Q3 THOUSANDS Cn+4 Q0 Q3 C / 10 Cn+4 Q0 Q3 TEN THOUSANDS C / 10 Cn+4 Q0 13 CARRY OUT Q3 5 MODE A OUTPUT CONTROL MODE B MUX MUX MUX 17 MUX Q3 6 MUX 18 Q2 BCD OUT 19 SCANNER RESET 9 Q1 R 20 SCANNER 10 CLOCK Q0 SCANNER 21 7 8 DS1 NOTE: = 3-STATE OUTPUT BUFFER 14 DS2 16 DS3 DIGIT SELECT DS4 11 DS5 15 3-STATE DIGIT CONTROL 3-STATE BCD CONTROL 3-State Control Out 0 1 Q or DS High Impedance REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14534B 1 IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS (Voltages referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit - 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) - 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin 10 mA PD Power Dissipation, per Package Tstg Storage Temperature TL 500 mW - 65 to + 150 _C 260 _C Lead Temperature (8-Second Soldering) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: - 12 mW/_C From 100_C To 125_C ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc "0" Level VIL 5.0 10 15 -- -- -- 1.0 2.0 3.0 -- -- -- 1.5 3.0 4.5 1.0 2.0 3.0 -- -- -- 1.0 2.0 3.0 5.0 10 15 4.0 8.0 12 -- -- -- 4.0 8.0 12 3.5 7.0 11 -- -- -- 4.0 8.0 12 -- -- -- 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 0.88 2.25 8.8 -- -- -- 0.36 0.9 2.4 -- -- -- 5.0 10 15 - 0.31 - 0.31 - 0.9 -- -- - 0.25 - 0.25 - 0.75 - 0.8 - 0.4 - 1.6 -- -- - 0.17 - 0.17 - 0.51 -- -- IOL 5.0 10 15 0.024 0.06 1.3 -- -- -- 0.02 0.05 0.25 0.03 0.09 1.63 -- -- -- 0.014 0.035 0.175 -- -- -- mAdc Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "1" Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc IOH Source Sink IOL Output Drive Current -- Pins 1 and 22 (VOH = 2.5 Vdc) (VOH = 9.5 Vdc) Source (VOH = 13.5 Vdc) IOH (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Sink mAdc mAdc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. MC14534B 2 mAdc (continued) MOTOROLA CMOS LOGIC DATA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) (continued) - 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit IDD 5.0 10 15 -- -- -- 5.0 10 20 -- -- -- 0.010 0.020 0.030 5.0 10 20 -- -- -- 150 300 600 Adc Total Supply Current** (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Three-State Leakage Current ITL Characteristic Symbol Quiescent Current (Per Package) 15 IT = (0.5 A/kHz) f + IDD IT = (1.0 A/kHz) f + IDD IT = (1.5 A/kHz) f + IDD -- 0.1 -- 0.0001 Adc Scan Oscillator Frequency = 1.0 kHz 0.1 -- 3.0 Adc #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. ** The formulas given are for the typical characteristics only at 25_C. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. MOTOROLA CMOS LOGIC DATA MC14534B 3 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C, see Figure 1) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL Propagation Delay Time, Clock to Q tPLH, tPHL = (1.8 ns/pF) CL + 4.0 s tPLH, tPHL = (0.8 ns/pF) CL + 1.5 s tPLH, tPHL = (0.6 ns/pF) CL + 1.0 s tPLH, tPHL 3.3 1.1 0.8 6.6 2.2 1.7 5.0 10 15 -- -- -- 1.8 0.6 0.5 3.6 1.2 0.9 5.0 10 15 -- -- -- 0.6 0.2 0.12 1.5 .5 0.38 5.0 10 15 -- -- -- 1.8 0.6 0.5 3.6 1.2 0.9 5.0 10 15 -- -- -- 1.5 0.5 0.4 3.0 1.0 0.75 tPHZ 5.0 10 15 -- -- -- 75 45 40 150 90 80 ns tPZH 5.0 10 15 -- -- -- 120 55 40 240 110 80 ns tPLZ 5.0 10 15 -- -- -- 120 55 45 240 110 90 ns tPZL 5.0 10 15 -- -- -- 160 70 45 320 140 90 ns fcl 5.0 10 15 -- -- -- 1.0 3.0 5.0 0.5 1.0 1.2 MHz tWH 5.0 10 15 1000 500 375 500 190 125 -- -- -- ns tw 5.0 10 15 320 130 80 160 65 40 -- -- -- ns trem 5.0 10 15 900 150 100 270 80 50 -- -- -- ns tWH(R) 5.0 10 15 2000 600 450 900 300 250 -- -- -- ns trem 5.0 10 15 1060 350 250 550 205 140 -- -- -- ns Scanner Clock to Q tPLH, tPHL = (1.8 ns/pF) CL + 1.8 s tPLH, tPHL = (0.8 ns/pF) CL + 0.6 s tPLH, tPHL = (0.6 ns/pF) CL + 0.5 s tPLH, tPHL Scanner Clock to Digit Select tPHL, tPLH = (1.8 ns/pF) CL + 1.5 s tPHL, tPLH = (0.8 ns/pF) CL + 0.5 s tPHL, tPLH = (0.6 ns/pF) CL + 0.4 s tPLH, tPLH Master Reset Removal Time s -- -- -- tPHL Master Reset Pulse Width ns 5.0 10 15 Master Reset to Error Out tPHL = (1.8 ns/pF) CL + 0.57 s tPHL = (0.8 ns/pF) CL + 0.19 s tPHL = (0.6 ns/pF) CL + 0.11 s Scanner Reset Removal Time Unit 200 100 80 8.0 3.0 2.25 tPHL Scanner Reset Pulse Width Max 100 50 40 4.0 1.5 1.0 Master Reset to Q tPHL = (1.8 ns/pF) CL + 1.8 s tPHL = (0.8 ns/pF) CL + 0.6 s tPHL = (0.6 ns/pF) CL + 0.5 s Clock or Scanner Clock Pulse Width Typ # -- -- -- -- -- -- tPLH Clock Pulse Frequency Min 5.0 10 15 5.0 10 15 Clock to Carry Out tPLH = (1.8 ns/pF) CL + 3.3 s tPLH = (0.8 ns/pF) CL + 1.1 s tPLH = (0.6 ns/pF) CL + 0.8 s Propagation Delay Time 3-State Control to Q VDD Vdc s s s s s * The formulas given are for the typical characteristics only at 25_C. #Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. MC14534B 4 MOTOROLA CMOS LOGIC DATA COUNTER TIMING DIAGRAM 1 2 3 4 5 6 7 8 9 10 102 103 104 105 106 CLOCK A UNITS Q0 UNITS Q1 UNITS Q2 UNITS Q3 UNITS Cn + 4 TENS Q0 TENS Q3 TENS Cn + 4 HUNDREDS Q0 HUNDREDS Q3 HUNDREDS Cn + 4 THOUSANDS Q0 THOUSANDS Q3 THOUSANDS Cn + 4 TEN THOUSANDS Q0 TEN THOUSANDS Q3 CARRY OUT MASTER RESET MODE CONTROL TRUTH TABLE Mode A Mode B First Stage Output Carry to Second Stage Application 0 0 Normal Count and Display At 9 to 0 transition of first stage 5-digit Counter 0 1 Inhibited Input Clock Test Mode: Clock directly into stages 1, 2, and 4. 1 1 Inhibited At 4 to 5 transition of first stage 4-digit counter with / 10 and roundoff at front end. 1 0 Counts 3, 4, 5, 6, 7 = 5 Counts 8, 9, 0, 1, 2 = 0 At 7 to 8 transition of first stage 4-digit counter with 1/2 pence capability. MOTOROLA CMOS LOGIC DATA MC14534B 5 SCANNER TIMING DIAGRAM SCANNER CLOCK SCANNER RESET DS1 UNITS DS2 TENS DS3 HUNDREDS DS4 THOUSANDS DS5 TEN THOUSANDS NOTE: If Mode B = 1, the first decade is inhibited and S1 will not go high, and the cycle will be shortened to four stages. DS5 is selected automatically when Scanner Reset goes high. ERROR DETECTION TIMING DIAGRAM RESET CLOCK A CLOCK B ERROR OUT GOOD PULSE ERROR 1 ERROR 2 GOOD PULSE ERROR 3 ERROR 4 NOTE: Error detector looks for inverted pulse on Clock B. Whenever a positive edge at Clock A is not accompanied by a negative pulse at Clock B (or vice-versa) within a time period of the one-shots an error is counted. Three errors result in Error Out to go to a "1". If error detection is not needed, tie Clock B high or low and leave Pins 1 and 22 unconnected. CLOCK SKEW RANGE ALLOWABLE CLOCK SKEW (ns/pF) 1000 500 300 100 SKEW IN THIS RANGE RESULTS IN COUNTED ERROR. 50 30 MAX SKEW IN THIS RANGE MAY OR MAY NOT RESULT IN COUNTED ERROR. 10 5.0 3.0 1.0 3.0 TYP SKEW IN THIS RANGE RESULTS IN NO ERROR COUNTED. MC14534B 6 5.0 7.0 MIN 9.0 11 VDD (Vdc) 13 15 NOTES: 1. The skew is the time difference between the low-to-high transition of CA to the high-to- low transition of CB or vice-versa. Capacitors C1 = C22 tied from pins 1 and 22 to VSS. 2. This graph is accurate for C1 = C22 100 pF. 3. When the error detection circuitry in not used, pins 1 and 22 are left open. 17 MOTOROLA CMOS LOGIC DATA APPLICATIONS INFORMATION VDD En CLOCK MC14534B 1/2 MC14518B Q4 CLOCK A MC14534B Cout* CLOCK A C * Carry Out is high for a single clock period when all five BCD stages go to zero. (Carry Out also goes high when MR is applied.) Figure 1. Cascade Operation CLOCK Q0 CLOCK A Q1 MC14534B Q2 SC BCD FOR SELECTED STAGE Q3 DS1 DS2 DS3 DS4 DS5 When the Q outputs of a given stage are required, this configuration will lock up the selected stage within four clock cycles. The select line feedback may be hardwired or switched. Figure 2. Forcing a BCD Stage to the Q Outputs PIN ASSIGNMENT MOTOROLA CMOS LOGIC DATA Cext 1 24 VDD MR 2 23 CLOCK B Eout 3 22 Cext CLOCK A 4 21 3-ST BCD MODE A 5 20 Q0 MODE B 6 19 Q1 DS1 7 18 Q2 DS2 8 17 Q3 SR 9 16 DS4 SC 10 15 3-ST DIG DS5 11 14 DS3 VSS 12 13 Cout MC14534B 7 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 623-05 ISSUE M 24 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). 13 B 1 12 DIM A B C D F G J K L M N A F SEATING PLANE C L N D G INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050 J M K MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 P SUFFIX PLASTIC DIP PACKAGE CASE 709-02 ISSUE C 24 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 13 B 1 12 A L C N K H F G MC14534B 8 D SEATING PLANE M J DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 31.37 32.13 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.03 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 1.235 1.265 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.080 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E-04 ISSUE E -A- 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 -B- 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.010 (0.25) M T A S B S F R C -T- SEATING PLANE M 22X G K X 45 _ DIM A B C D F G J K M P R MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0_ 8_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0_ 8_ 0.395 0.415 0.010 0.029 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CMOS LOGIC DATA *MC14534B/D* MC14534B MC14534B/D 9