MC14534BCP - ON Semiconductor

MOTOROLA CMOS LOGIC DATA 1

MC14534B

   

The MC14534B is composed of five BCD ripple counters that have their

respective outputs multiplexed using an internal scanner. Outputs of each

counter are selected by the scanner and appear on four (BCD) pins.

Selection is indicated by a logic high on the appropriate digit select pin. Both

BCD and digit select outputs have three–state controls providing an

“open–circuit” when these controls are high and allowing multiplexing.

Cascading may be accomplished by using the carry–out pin. The counters

and scanner can be independently reset by applying a high to the counter

master reset (MR) and the scanner reset (SR). The MC14534B was

specifically designed for application in real time or event counters where

continual updating and multiplexed displays are used.

•Four Operating Modes (See truth table)

•Input Error Detection Circuit

•Clock Conditioning Circuits for Slow Transition Inputs

•Counter Sequences on Positive Transition of Clock A

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

BLOCK DIAGRAM

PULSE ERROR

DETECTOR

PULSE

SHAPER TEST

CONTROL

OUTPUT

CONTROL

MUX

MUX MUX MUX MUX

UNITS CARRY

CONTROL

TENS HUNDREDS THOUSANDS TEN

THOUSANDS

C

÷

10 C

÷

10 C

÷

10 C

÷

10 C

÷

10

Q0 Q3 Q0 Q3 Q0 Q3 Q0 Q3 Q0 Q3

Cn+4 Cn+4 Cn+4 Cn+4 Cn+4

22

7 8 14 16 11

1

23

4

2

5

6

9

10

CLOCK B

CLOCK A

MASTER

RESET

MODE A

MODE B

SCANNER

RESET

SCANNER

CLOCK

ERROR OUT

3

R

SCANNER

13

17

18

19

20

Q3

Q2

Q1

Q0

21 3–STATE BCD

CONTROL

CARRY OUT

3–STATE DIGIT

CONTROL

15

DS1 DS2 DS3 DS4 DS5

DIGIT SELECT

3–STATE

OUTPUT BUFFER

NOTE:

BCD

OUT

VDD = PIN 24

VSS = PIN 12

TO CAPACITORS

3–State Control Out

Q or DS

High Impedance

0

1

=



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94



L SUFFIX

CERAMIC

CASE 623

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBDW SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 709

DW SUFFIX

SOIC

CASE 751E

MOTOROLA CMOS LOGIC DATAMC14534B

2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS (Voltages referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage – 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current (DC or Transient),

per Pin ± 10 mA

PDPower Dissipation, per Package† 500 mW

Tstg Storage Temperature – 65 to + 150

_

C

TLLead Temperature (8–Second Soldering) 260

_

C

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

_

C From 65

_

C To 125

_

C

Ceramic “L” Packages: – 12 mW/

_

C From 100

_

C To 125

_

C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

– 55

_

C 25

_

C 125

_

C

Unit

Characteristic

Symbol

VDD

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage “0” Level

Vin = VDD or 0

VOL 5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

“1” Level

Vin = 0 or VDD

VOH 5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

VIL 5.0

10

15

—

1.0

2.0

3.0

—

1.5

3.0

4.5

1.0

2.0

3.0

—

1.0

2.0

3.0

Vdc

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

10

15

4.0

8.0

12

—

4.0

8.0

12

3.5

7.0

11

—

4.0

8.0

12

—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH 5.0

5.0

10

15

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

mAdc

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

Output Drive Current — Pins 1 and 22

(VOH = 2.5 Vdc)

(VOH = 9.5 Vdc) Source

(VOH = 13.5 Vdc)

IOH 5.0

10

15

– 0.31

– 0.9 —

—

– 0.25

– 0.75

– 0.8

– 0.4

– 1.6 —

—

– 0.17

– 0.51 —

—

mAdc

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

10

15

0.024

0.06

1.3

—

0.02

0.05

0.25

0.03

0.09

1.63

—

0.014

0.035

0.175

—

mAdc

Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(Vin = 0) Cin — — — — 5.0 7.5 — — pF

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. (continued)

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, Vin and Vout should be constrained

to the range VSS

v

(Vin or Vout)

v

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

MOTOROLA CMOS LOGIC DATA 3

MC14534B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) (continued)

Characteristic

Symbol

VDD

Vdc

– 55

_

C 25

_

C 125

_

C

Unit

Characteristic

Symbol

VDD

Vdc

Min Max Min Typ # Max Min Max

Unit

Quiescent Current

(Per Package) IDD 5.0

10

15

—

5.0

10

20

—

0.010

0.020

0.030

5.0

10

20

—

150

300

600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

IT5.0

10

15 IT = (0.5 µA/kHz) f + IDD Scan Oscillator

IT = (1.0 µA/kHz) f + IDD Frequency = 1.0 kHz

IT = (1.5 µA/kHz) f + IDD

µAdc

Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

**The formulas given are for the typical characteristics only at 25

_

C.

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MOTOROLA CMOS LOGIC DATAMC14534B

4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25

_

C, see Figure 1)

Characteristic Symbol VDD

Vdc Min Typ # Max Unit

Output Rise and Fall Time tTLH,

tTHL 5.0

10

15

—

100

50

40

200

100

80

ns

Propagation Delay Time,

Clock to Q

tPLH, tPHL = (1.8 ns/pF) CL + 4.0 µs

tPLH, tPHL = (0.8 ns/pF) CL + 1.5 µs

tPLH, tPHL = (0.6 ns/pF) CL + 1.0 µs

tPLH,

tPHL 5.0

10

15

—

4.0

1.5

1.0

8.0

3.0

2.25

µs

Clock to Carry Out

tPLH = (1.8 ns/pF) CL + 3.3 µs

tPLH = (0.8 ns/pF) CL + 1.1 µs

tPLH = (0.6 ns/pF) CL + 0.8 µs

tPLH 5.0

10

15

—

3.3

1.1

0.8

6.6

2.2

1.7

µs

Master Reset to Q

tPHL = (1.8 ns/pF) CL + 1.8 µs

tPHL = (0.8 ns/pF) CL + 0.6 µs

tPHL = (0.6 ns/pF) CL + 0.5 µs

tPHL 5.0

10

15

—

1.8

0.6

0.5

3.6

1.2

0.9

µs

Master Reset to Error Out

tPHL = (1.8 ns/pF) CL + 0.57 µs

tPHL = (0.8 ns/pF) CL + 0.19 µs

tPHL = (0.6 ns/pF) CL + 0.11 µs

tPHL 5.0

10

15

—

0.6

0.2

0.12

1.5

.5

0.38

µs

Scanner Clock to Q

tPLH, tPHL = (1.8 ns/pF) CL + 1.8 µs

tPLH, tPHL = (0.8 ns/pF) CL + 0.6 µs

tPLH, tPHL = (0.6 ns/pF) CL + 0.5 µs

tPLH,

tPHL 5.0

10

15

—

1.8

0.6

0.5

3.6

1.2

0.9

µs

Scanner Clock to Digit Select

tPHL, tPLH = (1.8 ns/pF) CL + 1.5 µs

tPHL, tPLH = (0.8 ns/pF) CL + 0.5 µs

tPHL, tPLH = (0.6 ns/pF) CL + 0.4 µs

tPLH,

tPLH 5.0

10

15

—

1.5

0.5

0.4

3.0

1.0

0.75

µs

Propagation Delay Time

3–State Control to Q

tPHZ 5.0

10

15

—

75

45

40

150

90

80

ns

tPZH 5.0

10

15

—

120

55

40

240

110

80

ns

tPLZ 5.0

10

15

—

120

55

45

240

110

90

ns

tPZL 5.0

10

15

—

160

70

45

320

140

90

ns

Clock Pulse Frequency fcl 5.0

10

15

—

1.0

3.0

5.0

0.5

1.0

1.2

MHz

Clock or Scanner Clock Pulse Width tWH 5.0

10

15

1000

500

375

500

190

125

—

ns

Scanner Reset Pulse Width tw5.0

10

15

320

130

80

160

65

40

—

ns

Scanner Reset Removal Time trem 5.0

10

15

900

150

100

270

80

50

—

ns

Master Reset Pulse Width tWH(R) 5.0

10

15

2000

600

450

900

300

250

—

ns

Master Reset Removal Time trem 5.0

10

15

1060

350

250

550

205

140

—

ns

*The formulas given are for the typical characteristics only at 25

_

C.

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA 5

MC14534B

COUNTER TIMING DIAGRAM

106

105

104

103

102

10987654321

CLOCK A

UNITS Q0

UNITS Q1

UNITS Q2

UNITS Q3

UNITS Cn+4

TENS Q0

TENS Q3

TENS Cn+4

HUNDREDS Q0

HUNDREDS Q3

HUNDREDS Cn+4

THOUSANDS Q0

THOUSANDS Q3

THOUSANDS Cn+4

TEN THOUSANDS Q0

TEN THOUSANDS Q3

CARRY OUT

MASTER RESET

MODE CONTROL TRUTH TABLE

Mode A Mode B First Stage Output Carry to Second Stage Application

0 0 Normal Count and Display At 9 to 0 transition of first stage 5–digit Counter

0 1 Inhibited Input Clock Test Mode: Clock directly into stages 1, 2, and 4.

1 1 Inhibited At 4 to 5 transition of first stage 4–digit counter with ÷ 10 and roundoff at front end.

1 0 Counts 3, 4, 5, 6, 7 = 5

Counts 8, 9, 0, 1, 2 = 0 At 7 to 8 transition of first stage 4–digit counter with 1/2 pence capability.

MOTOROLA CMOS LOGIC DATAMC14534B

6

SCANNER TIMING DIAGRAM

NOTE: If Mode B = 1, the first decade is inhibited and S1 will not go high, and the cycle will be

shortened to four stages.

DS5 is selected automatically when Scanner Reset goes high.

TEN

THOUSANDS

HUNDREDS

TENS

UNITS

SCANNER

CLOCK

SCANNER

RESET

DS1

DS2

DS3

DS4

DS5

ERROR DETECTION TIMING DIAGRAM

NOTE: Error detector looks for inverted pulse on Clock B. Whenever a positive edge at

Clock A is not accompanied by a negative pulse at Clock B (or vice–versa) within

a time period of the one–shots an error is counted. Three errors result in Error Out

to go to a “1”. If error detection is not needed, tie Clock B high or low and leave

Pins 1 and 22 unconnected.

CLOCK A

CLOCK B

RESET

ERROR

OUT GOOD PULSE ERROR

1ERROR

2ERROR

3ERROR

4

GOOD PULSE

CLOCK SKEW RANGE

NOTES:

1. The skew is the time difference between the

low–to–high transition of CA to the high–to–

low transition of CB or vice–versa. Capacitors

C1 = C22 tied from pins 1 and 22 to VSS.

2. This graph is accurate for C1 = C22 ≥ 100 pF.

3. When the error detection circuitry in not used,

pins 1 and 22 are left open.

1000

500

300

100

50

30

10

5.0

3.0

1.0

3.0 5.0 7.0 9.0 11 13 15 17

VDD (Vdc)

SKEW IN THIS RANGE

RESULTS IN COUNTED

ERROR.

MAX

SKEW IN THIS RANGE

RESULTS IN NO ERROR

COUNTED.

TYP

MIN

SKEW IN THIS RANGE

MAY OR MAY NOT

RESULT IN COUNTED

ERROR.

ALLOWABLE CLOCK SKEW (ns/pF)

MOTOROLA CMOS LOGIC DATA 7

MC14534B

APPLICATIONS INFORMATION

Figure 1. Cascade Operation

*Carry Out is high for a single clock period when all five BCD stages go to zero.

(Carry Out also goes high when MR is applied.)

VDD

CLOCK CLOCK A CLOCK A

En

CQ4 Cout*

1/2

MC14518B

MC14534B MC14534B

Figure 2. Forcing a BCD Stage to the Q Outputs

When the Q outputs of a given stage are required, this configuration will

lock up the selected stage within four clock cycles. The select line feedback

may be hardwired or switched.

CLOCK BCD FOR

SELECTED

STAGE

Q0

CLOCK A Q1

Q2

Q3

SC

DS5DS4DS3DS2DS1

MC14534B

MODE B

CLOCK A

Eout

MR

Cext

DS2

DS1

MODE A Q0

3–ST BCD

Cext

CLOCK B

VDD

3–ST DIG

DS4

Q3

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

13

11

12

21

22

23

24

Cout

DS3

Q2

Q1

DS5

VSS

SC

SR

PIN ASSIGNMENT

MOTOROLA CMOS LOGIC DATAMC14534B

8

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 709–02

ISSUE C

L SUFFIX

CERAMIC DIP PACKAGE

CASE 623–05

ISSUE M

NOTES:

1. POSITIONAL TOLERANCE OF LEADS (D),

SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM

MATERIAL CONDITION, IN RELATION TO

SEATING PLANE AND EACH OTHER.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A31.37 32.13 1.235 1.265

B13.72 14.22 0.540 0.560

C3.94 5.08 0.155 0.200

D0.36 0.56 0.014 0.022

F1.02 1.52 0.040 0.060

G2.54 BSC 0.100 BSC

H1.65 2.03 0.065 0.080

J0.20 0.38 0.008 0.015

K2.92 3.43 0.115 0.135

L15.24 BSC 0.600 BSC

M0 15 0 15

N0.51 1.02 0.020 0.040

_ _ _ _

1 12

1324

B

H

A

FD

G

K

SEATING

PLANE

N

C

MJ

L

NOTES:

1. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION (WHEN FORMED

PARALLEL).

1 12

24 13

B

A

SEATING

PLANE

F

D

GK

N

C

MJ

L

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A31.24 32.77 1.230 1.290

B12.70 15.49 0.500 0.610

C4.06 5.59 0.160 0.220

D0.41 0.51 0.016 0.020

F1.27 1.52 0.050 0.060

G2.54 BSC 0.100 BSC

J0.20 0.30 0.008 0.012

K3.18 4.06 0.125 0.160

L15.24 BSC 0.600 BSC

M0 15 0 15

N0.51 1.27 0.020 0.050

_ _ _ _

MOTOROLA CMOS LOGIC DATA 9

MC14534B

OUTLINE DIMENSIONS

DW SUFFIX

PLASTIC SOIC PACKAGE

CASE 751E–04

ISSUE E

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN

EXCESS OF D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

–A–

–B– P12X

D24X

12

1324

1

M

0.010 (0.25) B M

S

A

M

0.010 (0.25) B S

T

–T–

G

22X

SEATING

PLANE

K

C

RX 45

_

M

F

J

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A15.25 15.54 0.601 0.612

B7.40 7.60 0.292 0.299

C2.35 2.65 0.093 0.104

D0.35 0.49 0.014 0.019

F0.41 0.90 0.016 0.035

G1.27 BSC 0.050 BSC

J0.23 0.32 0.009 0.013

K0.13 0.29 0.005 0.011

M0 8 0 8

P10.05 10.55 0.395 0.415

R0.25 0.75 0.010 0.029

____

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided

in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,

including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent

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MC14534B/D

*MC14534B/D*

◊