February 1999 - Linear Technology

LINEAR TECHNOLOGY

IN THIS ISSUE…

COVER ARTICLE

Third-Generation DC/DC Controller

Reduces Size and Cost .................. 1

Randy G. Flatness

Issue Highlights ............................ 2

LTC

in the News........................... 2

DESIGN FEATURES

New Universal Continuous-Time Filter

with Extended Frequency Range ... 7

Max W. Hauser

SOT-23 Switching Regulators

Deliver Low Noise Outputs

in a Small Footprint ................... 11

Steve Pietkiewicz

Versatile New Switching Regulator

Fits in SO-8 ................................. 14

Craig Varga

16-Bit Parallel DAC Has 1LSB

Linearity, Ultralow Glitch and

Accurate 4-Quadrant Resistors ... 18

Patrick Copley

Fast Rate Li-Ion Battery Charger

................................................... 24

Goran Perica

DESIGN IDEAS

No R

SENSE

Controller Delivers 12V and

100W at 97% Efﬁciency .............. 26

Christopher B. Umminger

Generating Low Cost, Low Noise,

Dual-Voltage Supplies ................. 27

Ajmal Godil

Switched Capacitor Voltage Regulator

Provides Current Gain ................. 28

Jeff Witt

High Current Step-Down Conversion

from Low Input Voltages ............. 30

Dave Dwelley

How to Design High Order Filters with

Stopband Notches Using the LTC1562

Operational Filter (Part 2) ........... 31

Nello Sevastopoulos

DESIGN INFORMATION

The LTC1658 and LTC1655: Smallest

Rail-to-Rail 14-Bit and 16-Bit DACs

................................................... 36

Hassan Malik

New Device Cameos ..................... 37

Design Tools................................ 39

Sales Offices ............................... 40

FEBRUARY 1999 VOLUME IX NUMBER 1

, LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load,

FilterCAD, Hot Swap, Linear View, Micropower SwitcherCAD, No R

SENSE

, Operational Filter, OPTI-LOOP, PolyPhase,

SwitcherCAD and UltraFast are trademarks of Linear Technology Corporation. Other product names may be trademarks

of the companies that manufacture the products.

Thir d-Generation DC/DC

Controllers Reduce

Size and Cost

Introduction

The LTC1735 and LTC1736 are the

newest members of Linear Tech-

nology’s third generation of DC/DC

controllers. These controllers use the

same constant frequency, current

mode architecture and Burst Mode™

operation as the previous generation

LTC1435–LTC1437 controllers but

with improved features. With

OPTI-LOOP™ compensation, new

protection circuitry, tighter load regu-

lation and strong MOSFET drivers,

these controllers are ideal for the

current and future generations of CPU

power applications.

The LTC1735 is pin compatible with

the previous generation LTC1435/

LTC1435A controllers with only mi-

nor external component changes.

Protection features include internal

foldback current limiting, output ov-

ervoltage crowbar and optional

short-circuit shutdown. The 0.8V ±1%

reference allows the low output volt-

ages and 1% accuracy that will be

demanded by future microprocessors.

The operating frequency (synchroniz-

able up to 500kHz) is set by an external

capacitor , allowing maximum ﬂexibil-

ity in optimizing efﬁciency.

The LTC1736 has all of the fea-

tures of the LTC1735, plus voltage

programming for CPU power , in a 24-

lead SSOP package. The output voltage

in LTC1736 applications is pro-

grammed by a 5-bit digital-to-analog

converter (DAC) that adjusts the out-

continued on page 3

Figure 1. LTC1736 evaluation circuit: a complete 5V–24V to 0.9V–2V/12A converter

in 2.15in

of PC board space

by Randy G. Flatness

Linear Technology Magazine • February 1999

EDITOR’S PAGE

Issue Highlights

Happy New Year and welcome to

the ninth volume of Linear Technol-

ogy magazine.

This issue is heavy on power prod-

ucts: our cover article introduces the

LTC1735 and LTC1736, the newest

members of Linear Technology’s third

generation of DC/DC controllers.

These controllers use the same cur -

rent mode architecture with constant

frequency and Burst Mode operation

as the LTC1435–LTC1437 controllers

but with improved features. With

OPTI-LOOP compensation, new

protection circuitry, tighter load regu-

lation and strong MOSFET drivers,

these controllers are ideal for the cur-

rent and future generations of CPU

power applications.

This issue debuts the L TC1530, a

synchronous buck regulator control-

ler in the SO-8 package. The LTC1530

is a small, versatile controller that is

usable in numerous topologies and

over a wide range of power levels. In

basic buck applications, the LTC1530

permits the designer to realize very

simple, low parts count designs that

require minimal real estate. With a

little ingenuity, it is possible to de-

velop circuits different than those that

the part’s designers intended, but

which give excellent performance

nonetheless.

The LT

1505 is a constant-cur-

rent, constant-voltage, current mode

switching battery charger using the

synchronous buck topology. Its out-

put voltage is preset for 3–4 Li-Ion

cells, but can be programmed from 1V

to 21V. It features a 0.5% voltage

reference, low dropout operation, pro-

grammable wall adapter current

limiting and ef ficiencies to 94%.

Rounding out our selection of

switchers are the LT1611 and LT1613.

These current mode, constant fre-

quency devices contain inter nal 36V

switches capable of generating out-

put power in the range of 400mW to

2W , in a 5-lead SOT-23 package. The

LT1613 has a standard positive feed-

back pin and is designed to regulate

positive voltages. The LT1611 has a

novel feedback scheme designed to

directly regulate negative output volt-

ages without the use of level-shifting

circuitry.

In the filter arena, we premier the

LTC1562-2, an extended-frequency

version of the LTC1562 quadruple

2nd order, universal, continuous-time

ﬁlter , described in the February 1998

issue. The LTC1562 introduced

Operational Filter™ building blocks,

which satisfy diverse ﬁlter

requirements and applications

compactly

. The

LTC1562-2 has the

same block diagram, pinout and pack-

aging as the original LTC1562, but is

optimized for higher ﬁlter frequen-

cies: 20kHz to 300kHz. Besides

covering a full octave of frequencies

(150kHz–300kHz) above the range of

the LTC1562, the LTC1562-2 also

overlaps the LTC1562’s utility in the

range 20kHz to 150kHz. In this

frequency range, the LTC1562-2 typi-

cally shows reduced large-signal

distortion at a cost of slightly more

noise than with the L TC1562.

We also introduce a new data con-

verter: the LTC1597 16-bit parallel,

current output, low glitch, multiplying

DAC. The LTC1597 has outstanding

1LSB linearity over temperature,

ultralow glitch impulse, on-chip 4-

quadrant feedback resistors, low power

consumption, asynchronous clear and

a versatile parallel interface. For 14-

bit systems, its pin compatible

counterpart, the LTC1591, is an ideal

solution. Combined with the LT1468

op amp (introduced in the November

1998 issue), the LTC1597 provides the

best in its class, 1.7µs settling time to

0.0015%, while maintaining superb

DC linearity speciﬁcations. Two rail-

to-rail, voltage output DACs can be

found in the Design Information sec-

tion: the 14-bit LTC1658 and the 16-bit

LTC1655; these DACs have a ﬂexible

3-wire serial interface that is SPI/

QSPI and MICROWIRE™ compatible.

They provide a convenient upgrade

path for users of LTC’s 12-bit voltage

output

DAC family.

This issue features a rich selection

of Design Ideas, including four dif-

ferent power conversion circuits and

the second in a series of articles on

designing high order filters with stop-

band notches using the LTC1562

filter ICs.

The issue concludes with six New

Device Cameos.

LTC in the News…

On January 12, 1999, Linear Tech-

nology announced its financial

results for the second quarter of FY

1999, reporting increased sales and

profits compared to the second

quarter of the previous year. Net

sales and net income for the quar-

ter ended December 27, 1998, were

$120,020,000 and $45,904,000,

respectively.

Reporting the results, Linear

Technology President and CEO Rob-

ert H. Swanson said, “This quarter

proved to be stronger than we

initially expected, as the general

worldwide economic climate

improved. We grew sales and prof-

its 3% sequentially from the

previous quarter and added $35.6

million to our cash balance. Our

return on sales is an industry

leading 38.2%.”

Prior to the announcement, Lin-

ear Technology was named a top

stock pick for 1999 in a December

17, 1998 article in USA Today. Jim

Craig, manager of the $21 billion

Janus fund and one of several

financial analysts surveyed inter-

viewed by USA Today, listed Linear

Technology among his top picks for

the coming year.

The December 28 issue of EE

Times named Linear Technology

Staf f Scientist Jim Williams one of

nineteen “Times People 98.” The

issue included a full-page profile on

Jim, emphasizing the changes he

has seen in analog design over the

past two decades.

The December 7 issues of both

Electronic News and Electronic

Buyers’ News reported Linear

Technology’s December announce-

ment of the addition of Wyle

Electronics as an authorized

distributor.

MICROWIRE is a trademark of National Semiconductor Corp.

Linear Technology Magazine • February 1999

DESIGN FEATURES

put voltage from 0.925V to 2.00V,

according to Intel mobile VID

speciﬁcations.

Details

The LTC1735 and LTC1736 are syn-

chronous step-down switching

regulator controllers that drive exter-

nal N-Channel power MOSFETs using

a programmable ﬁxed frequency OPTI-

LOOP architecture. OPTI-LOOP

compensation effectively removes the

constraints placed on C

OUT

by other

controllers for proper operation (such

as limits on low ESRs). A maximum

duty cycle limit of 99% provides low

dropout operation, which extends

operating time in battery operated

systems. A forced-continuous con-

trol pin reduces noise and RF

interference and can assist second-

ary winding regulation by disabling

Burst Mode when the main output is

lightly loaded. Soft-start is provided

by an exter nal capacitor that can be

used to properly sequence supplies.

The operating current level is user-

programmable via an external current

sense resistor. A wide input-supply

range allows operation from 3.5V to

30V (36V maximum).

Protection

New internal protection features in

the LTC1735 and LTC1736 control-

lers include foldback current limiting,

short circuit detection, short-circuit

latch-off and overvoltage protection.

These features protect the PC board,

the MOSFETs and the load itself (the

CPU) against faults.

Fault Protection:

Overcurrent Latch-Off

The RUN/SS pin, in addition to pro-

viding soft-start capability, also

provides the ability to shut off the

controller and latch off when an over-

current condition is detected. The

RUN/SS capacitor, C

(refer to Fig-

ure 5) is used initially to turn on and

limit the inrush current of the con-

troller. After the controller has been

started and given adequate time to

charge the output capacitor and pro-

vide full load current, C

is used as

a short-circuit timer. If the output

voltage falls to less than 70% of its

nominal output voltage after C

reaches 4.2V, it is assumed that the

output is in a severe overcurrent

and/or short-circuit condition and

begins discharging. If the condi-

tion lasts for a long enough period, as

determined by the size of C

, the

controller will be shut down until the

RUN/SS pin voltage is recycled.

This built-in latch-off can be over-

ridden by providing >5µA at a

compliance of 4V to the RUN/SS pin

(refer to the LTC1735/LTC1736 Data

Sheet for details). This exter nal cur-

rent shortens the soft-start period

but also prevents net discharge of the

RUN/SS capacitor during a severe

overcurrent and/or short-circuit

condition.

Why should you defeat overcur-

rent latch-off? During the prototyping

stage of a design, there may be a

problem with noise pickup or poor

layout causing the protection circuit

to latch off. Defeating this feature will

allow easy troubleshooting of the cir-

cuit and PC layout. The internal

short-circuit detection and foldback

current limiting still remain active,

thereby protecting the power supply

system from failure. After the design

is complete, you can decide whether

to enable the latch-of f feature.

Fault Protection: Current Limit

and Current Foldback

The LTC1735/LTC1736 current com-

parator has a maximum sense voltage

of 75mV, resulting in a maximum

MOSFET current of 75mV/R

SENSE

The LTC1735/LTC1736 includes cur-

rent foldback to help further limit

load current when the output is

shorted to ground. If the output falls

by more than one-half, the maximum

sense voltage is progressively lowered

from 75mV to 30mV. Under short-

circuit conditions with very low duty

cycle, the LTC1735/LTC1736 will

begin cycle skipping in order to limit

the short-circuit current. In this situ-

ation, the bottom MOSFET will be on

most of the time, conducting the cur-

rent. The average short-circuit current

will be approximately 30mV/ R

SENSE.

Note that this function is always active

and is independent of the short cir -

cuit latch-off.

Fault Protection: Output

Overvoltage Protection (OVP)

An output overvoltage crowbar turns

on the synchronous MOSFET to blow

a system fuse in the input lead when

noitidnoCgnitarepOhctaLtfoShctaLdraH

stneisnarTtsaFtoohsrevOslortnoCffOsehctaL

V5otdetrohStuptuOPVOtadepmalCtuptuOffOsehctaL

esaerceDegatloVDIVegatloVweNsetalugeRffOsehctaL

esioNtuptuOslortnoCffOsehctaL

TEFSOMpoTdetrohSsdaolrevOTEFSOMmottoBsdaolrevOTEFSOMmottoB

naCegatloVtuptuO

esreveR

oNseY

devomeRsidaolrevOnehWnoitarepOlamroNsemuseRffOdehctaLsniameR

stluaFgnitoohselbuorTstnemerusaeMCDysaE

eriuqeRyaM;tluciffiD

sepocsollicsOlatigiD

Table 1. Overvoltage protection comparison

OPERATING FREQUENCY (kHz)

0 100 200 300 400 500 600

OSC

VALUE (pF)

100.0

87.5

75.0

62.5

50.0

37.5

25.0

12.5

LTC1735/

LTC1736

LTC1435/

LTC1436

Figure 2. C

OSC

value vs frequency for the

LTC1435/36 and the LTC1735/36

LTC1735/LTC1736, continued from page 1

Linear Technology Magazine • February 1999

DESIGN FEATURES

the output of the regulator rises much

higher than nominal levels. The crow-

bar can cause huge currents to ﬂow,

greater than in normal operation. This

feature is designed to protect against

a shorted top MOSFET or short cir -

cuits to higher supply rails; it does

not protect against a failure of the

controller itself.

Previous latching crowbar schemes

for overvoltage protection have a num-

ber of problems (see T able 1). One of

the most obvious, not to mention

most annoying, is nuisance trips

caused by noise or transients

momentarily exceeding the OVP

threshold. Each time that this occurs

with latching OVP, a manual reset is

required to restart the regulator. Far

more subtle is the resulting output

voltage reversal. When the synchro-

nous MOSFET latches on, a large

reverse current is loaded into the

inductor while the output capacitor is

discharging. When the output voltage

reaches zero, it does not stop there,

but rather continues to go negative

until the reverse inductor current is

depleted. This requires a sizable

Schottky diode across the output to

prevent excessive negative voltage on

the output capacitor and load.

A further problem on the horizon

for latching OVP circuits is their

incompatibility with on-the-ﬂy CPU

core voltage changes. If an output

voltage is reprogrammed from a higher

voltage to a lower voltage, the OVP

will temporarily indicate a fault, since

the output capacitor will momentarily

hold the previous, higher output volt-

age. With latching OVP, the result will

be another latch-off, with a manual

reset required to attain the new out-

put voltage. To prevent this problem,

the OVP threshold must be set above

the maximum programmable output

voltage, which would do little good

when the output voltage was pro-

grammed near the bottom of its range.

In order to avoid these problems

with traditional latching OVP circuits,

the LTC1735 and LTC1736 use a new

“soft latch” OVP circuit. Regardless of

operating mode, the synchronous

MOSFET is forced on whenever the

output voltage exceeds the regulation

point by more than 7.5%. However , if

the voltage then returns to a safe

level, nor mal operation is allowed to

resume, thereby preventing latch-off

caused by noise or voltage repro-

gramming. Only in the case of a true

fault, such as a shorted top MOSFET,

will the synchronous MOSFET remain

latched on until the input voltage

collapses or the system fuse blows.

The new soft latch OVP also pro-

vides protection and easy diagnosis

of other overvoltage faults, such as a

lower supply rail shorted to a higher

voltage. In this scenario, the output

voltage of the higher regulator is pulled

down to the OVP voltage of the

soft-latched regulator, allowing the

problem to be easily diagnosed with

DC measurements. On the other

hand, latching OVP provides only a

millisecond glimpse of the fault as it

latches off, forcing the use of expensive

digital oscilloscopes for trouble-

shooting.

Three Operating Modes/One

Pin: Sync, Burst Disable and

Secondary Regulation

The FCB pin is a multifunction pin

that controls the operation of the

synchronous MOSFET and is an input

for external clock synchronization.

When the FCB pin drops below its

0.8V threshold, continuous mode

operation is forced. In this case, the

top and bottom MOSFETs continue

to be driven synchronously regard-

less of the load on the main output.

Burst Mode operation is disabled and

current reversal is allowed in the

inductor.

In addition to providing a logic

input to force continuous syn-

chronous operation and external

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Table 2. FCB possible states

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esneStnerruCxaMVm57Vm051

emiT-nOmuminiMsn002sn003

elbazinorhcnySseYylnOLLP-A6341CTL

VtnI

egatloV)xaMV7(V2.5)xaMV01(V5

tuptuOdooGrewoPylnO6371CTLylnOLLP-6A3/6A341CTL

kcabdloFtnerruClanretnIlanretxE

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ffO-hctaLIOtuptuOlanoitpOoN

segakcaP42G/61NG,61OS42NG/61G,61OS

srevirDTEFSOM3×1×

Table 3. Comparison of LTC1735/36 controllers with LTC1435A/36A-PLL controllers

BURST

SYNC

CONTINUOUS

100%

90%

80%

70%

60%

50%

40%

30%

20%

0.001 0.01 0.1 1.0 10.0

LOAD CURRENT (A)

EFFICIENCY (%)

Figure 3. Efﬁciency vs load current for three

modes of operation

Linear Technology Magazine • February 1999

DESIGN FEATURES

synchronization, the FCB pin pro-

vides a means to regulate a ﬂyback

winding output. It can force continu-

ous synchronous operation when

needed by the ﬂyback winding,

regardless of the primary output load.

In order to prevent erratic operation if

Table 4. VID output voltage programming

4B3B2B1B0BV

TUO

)V(

00000 V000.2

00001 V059.1

00010 V009.1

00011 V058.1

00100 V008.1

00101 V057.1

00110 V007.1

00111 V056.1

01000 V006.1

01001 V055.1

01010 V005.1

01011 V054.1

01100 V004.1

01101 V053.1

01110 V003.1

01111 *

10000 V572.1

10001 V052.1

10010 V522.1

10011 V002.1

10100 V571.1

10101 V051.1

10110 V521.1

10111 V001.1

11000 V570.1

11001 V050.1

11010 V520.1

11011 V000.1

11100 V579.0

11101 V059.0

11110 V529.0

11111 **

denifedatuohtiwsedoctneserpe r**,*:etoN .snoitacificepsletnInideificepssaegatlovtuptuo dilavasasedocesehtsterpretni6371CTLehT :swollofsaegatlovtuptuosecudorpdnastupni .V009.0=]11111[,V052.1=]11110[

no external connections are made,

the FCB pin is pulled high by a 0.25µA

inter nal current source.

The LTC1735 internal oscillator

can be synchronized to an external

oscillator by applying a clock signal of

at least 1.5V

P-P

to the FCB pin. When

synchronized to an external fre-

quency, Burst Mode operation is

disabled but cycle skipping occurs at

low load currents since current

reversal is inhibited. The bottom gate

will come on every 10 clock cycles to

ensure that the bootstrap cap is kept

refreshed and to keep the frequency

above the audio range. The rising

edge of an external clock applied to

the FCB pin starts a new cycle.

The range of synchronization is

from 0.9 × f

to 1.3 × f

, with f

set by

OSC

. Attempting to synchronize to a

higher frequency than 1.3 × f

can

result in inadequate slope compensa-

tion and cause loop instability with

high duty cycles. If loop instability is

observed while synchronized, addi-

tional slope compensation can be

obtained by simply decreasing C

OSC

A plot of operating frequency versus

OSC

value is shown in Figure 2.

Table 2 summarizes the possible

states available on the FCB pin.

Figure 3 gives a comparison of efﬁ-

ciencies in a regulator for the three

operating modes: forced continuous

operation, pulse skipping mode (syn-

chronized at f = f

) and Burst Mode

operation.

Converting to the LTC1735

The LTC1735 is pin compatible with

the LTC1435/LTC1435A, with minor

component changes. Table 3 shows

the differences between the two con-

trollers. The important items to note

are:

1. The L TC1735 has a 0.8V refer-

ence (versus 1.19V for the

L TC1435) that allows lower

output voltage operation (down to

0.8V). Thus, the output feedback

divider will have to be recalcu-

lated for the same output voltage.

2. The L TC1735’s maximum

current sense voltage is half that

of the LTC1435. This r educes the

power lost in the sense resistor

by half. Hence, for the same

maximum output current, the

current sense resistor must be

cut in half.

0.005Ω

FDS6680A

0.22µF

4.7µF

2µH

MBRS340T3

22µF

30V

OUT

1.6V/9A

IN1

CS1

O3*

820µF

180µF

FDS6680A

10k

†

BOOST

PGND

INT V

RUN/SS

OSC

SGND

SENSE

EXT V

FCB

OSENSE

SENSE

–

LTC1735

OSC1

47pF

100pF

, 1000pF

0.1µF

33k

330pF D1

CMDSH-3

R5 10Ω

R2 10Ω

47pF

EXT V

4.7Ω

0.1µF

JP2

LATCH-OFF

(DISABLED)

R6, 1M

INT V

JP1

BURST MODE FCB/SYNCRUN

10Ω

22µF

30V

IN3

GND

1µF

PANASONIC ETQP6F2R0HFA (201) 348-7522

SANYO OSCON 4SP820M (619) 661-6835

†

OFF

100 200 300 400 500 600

FREQUENCY (kHz)

GATE-CHARGE CURRENT (mA)

TOP AND BOTTOM MOSFETS

= FAIRCHILD NDS6680A

Figure 4. MOSFET gate-charge current vs

frequency

Figure 5. High efﬁciency 1.6V/9A CPU power supply

Linear Technology Magazine • February 1999

DESIGN FEATURES

3. The gate drivers of the L TC1735

are 3× the strength of those in

the L TC1435. This equates to

faster rise and fall times for

driving the same MOSFETs plus

the capability to drive larger

MOSFET s with less efﬁciency

loss due to transition losses.

Speed

The LTC1735/LTC1736 are designed

to be used in higher current applica-

tions than the LTC1435 family.

Stronger gate drives allow paralleling

multiple MOSFETs or higher operat-

ing frequencies. The LTC1735 has

been optimized for low output voltage

operation by reducing the minimum

on-time to less than 200ns. Remem-

ber, though, that transition losses

can still impose signiﬁcant efﬁciency

penalties at high input voltages and

high frequencies. Just because the

LTC1735 can operate at frequencies

above 300kHz doesn’t mean it should.

Figure 4 shows a plot of MOSFET

charge current versus frequency.

Linear Current

Comparator Operation

Since the trend in the marketplace

has forced output voltages to lower

and lower values, the current sense

inputs have been optimized for low

voltage operation. The current sense

comparator has a linear response

characteristic, without discon-

tinuities, from 0V to 6V output

voltages. In the LTC1435/LTC1435A,

two input stages are used to cover

this range, so an overlap exists

together with a transition region. The

LTC1735/LTC1736 uses only one

input stage and includes slope com-

pensation that operates over the full

output voltage range. This allows the

LTC1735/LTC1736 to be operated in

grounded R

SENSE

applications as well.

LTC1736 Additional Features

The LTC1736 includes all the fea-

tures of the LTC1735, plus 5-bit

mobile VID control and a power-good

comparator in a 24-lead SSOP pack-

age. The window comparator monitors

the output voltage and its open-drain

output is pulled low when the divided

voltage is not within ±7.5% of the 0.8V

reference voltage.

The output voltage is digitally set

to levels between 0.925V and 2.00V

using the voltage identiﬁcation (VID)

inputs B0–B4. The internal 5-bit DAC

conﬁgured as a precision resistive

voltage divider sets the output volt-

age in 50mV or 25mV increments

according to Table 4. The VID codes

(00000–11110) are compatible with

the Intel mobile Pentium

proces-

sor. The LSB (B0) represents 50mV

increments in the upper voltage range

(2.00V–1.30V) and 25mV increments

in the lower voltage range (1.275V–

0.925V). The MSB is B4. When all bits

are low or grounded, the output volt-

age is 2.00V.

The LTC1736 also has remote sense

capability. The top of the internal

resistive divider is connected to

OSENSE

and is referenced to the SGND

pin. This allows a Kelvin connection

for remotely sensing the output voltage

directly across the load, eliminating

any PC board trace resistance errors.

Applications

Figure 5 shows a 1.6V/9A applica-

tion using the LTC1735. The input

voltage can range from 6V to 26V.

Figure 6 shows a VID application

using the LTC1736 optimized for out-

put voltages of 1.6V to 1.3V with a 5V

to 24V input voltage range.

0.004Ω

0.22µF

4.7µF

D2 MBRS-

340T3

OUT

0.9V–2.0V

/12A

IN1

22µF

30V

CS1

820µF

FDS6680A

M1, M3

FDS6680A

×2

†

1.2µH

BOOST

PGND

INT V

RUN/SS

OSC

SGND

SENSE

EXT V

FCB

OSENSE

SENSE

–

LTC1736

OSC1

47pF

330pF

47pF

, 1000pF

33k

100pF D1

CMDSH-3

R5 10Ω

R2 10Ω

EXT V

4.7Ω

0.1µF

JP2

LATCH-OFF

(DISABLED)

R6, 680k

INT V

OFF

JP1

BURST MODE FCB/SYNCRUN

10Ω

IN3

22µF

30V

PGOOD

B1 B2

VID V

47pF

100k

INT V

PGOOD C4

1µF

JP4 ABCDE

LSB MSB

PANASONIC ETQP6F2R0HFA (201) 348-7522

PANASONIC EEFVEOG181R

†

Figure 6. High efﬁciency, VID programmable, 0.9V–2.0V/12A CPU power supply

Authors can be contacted

at (408) 432-1900

Pentium is a registered trademark of Intel Corp.

continued on page 35

Linear Technology Magazine • February 1999

DESIGN FEATURES

New Universal Continuous-Time Filter

with Extended Frequency Range

by Max W. Hauser

Introduction

The original LTC1562, described in

the February 1998 issue of this maga-

zine, is a compact, quadruple 2nd

order , universal, continuous-time ﬁl-

ter that is DC accurate and user

programmable for the 10kHz–150kHz

frequency range. The LTC1562 intro-

duced Operational Filter building

blocks, whose virtual-ground input,

rail-to-rail outputs and precision

internal R and C components satisfy

diverse ﬁlter requirements and appli-

cations compactly.

1, 2, 3

The design of the LTC1562 entailed

choices in the internal R and C values

and internal ampliﬁers, and these

elements were optimized to minimize

wideband noise. The LTC1562-2 is a

new product with the same block

diagram, pinout and packaging, but

optimized for higher ﬁlter frequen-

cies: 20kHz to 300kHz. The inter nal

precision R and C components and

ampliﬁers are different in the

LTC1562-2. Besides covering a full

octave of frequencies (150kHz–

300kHz) above the range of the

LTC1562, the LTC1562-2 also over -

laps the LTC1562’s utility in the range

20kHz to 150kHz. In this frequency

range, the LTC1562-2 typically shows

reduced large-signal distortion at a

cost of slightly more noise than with

the LTC1562. For example, a 100kHz

dual 4th order Butterworth lowpass

ﬁlter with a ±5V supply, built with the

LTC1562-2 and lightly loaded, exhib-

ited 2nd-harmonic distortion of

–103dB and 3rd-harmonic distortion

of –112dB at 20kHz with an output of

RMS

(2.8V

P-P

), and maintained low

distortion even with output swings

approaching the full supply voltage

(–83dB total harmonic distortion, or

THD, at 9.7V

P-P

output).

The LTC1562-2 is, therefore, the

product of choice for applications

above 150kHz as well as for applica-

tions in the 20kHz–150kHz range that

are especially distortion sensitive.

Both the LTC1562 and the LTC1562-2

can replace LC ﬁlters or ﬁlters built

from high performance op amps and

precision capacitors and resistors,

with a total surface mount board area

of 155mm

(0.24in

)—smaller than a

dime (the smallest US coin).

Comparison to the LTC1562

The LTC1562-2 both resembles and

differs fr om the L TC1562 as follows:

❏ The parts have identical pin

conﬁgurations and block

diagrams (four independently

programmable 2nd order

Operational Filter blocks with

virtual-ground inputs and rail-to-

rail outputs).

❏ In both products, the user can

program the ﬁlter’s center-

frequency parameter (f

) over a

wide range, using resistor values

that vary as the desired f

changes up or down from a

design-center value. In the

L TC1562, this design-center f

100kHz; for the LTC1562-2, the

value is 200kHz.

❏ The L TC1562 is optimized for

lower noise, the LTC1562-2 for

higher frequencies. Thus, a

single LTC1562 section can

deliver 103dB SNR in 200kHz

bandwidth (Q = 1), whereas a

single L TC1562-2 section

supports 99dB SNR in 400kHz.

–

SHDN

1562 F02

2ND ORDER SECTIONS

INV V1 V2

INV V1 V2 INV V1 V2

SHUTDOWN

SWITCH

SHUTDOWN

SWITCH AGND

–

R2 R

V2 INV V1

1562 F01

sR1C*

*R1 AND C ARE PRECISION

INTERNAL COMPONENTS

Figure 1. LTC1562-2 block diagram

Figure 2. Single 2nd order Operational Filter section (inside

dashed line) with external components added: resistor for

gives lowpass at V2, bandpass at V1; capacitor for Z

gives bandpass at V2, highpass at V1.

Linear Technology Magazine • February 1999

DESIGN FEATURES

❏ Each chip contains precision R

and C components equivalent to

eight 0.25% tolerance capacitors

and four 0.5% tolerance

resistors, as well as twelve op

amps with rail-to-rail outputs

and excellent high frequency

linearity.

❏ Both circuits operate from

nominal 5V to 10V total supplies

(single or split). Single-supply

applications can use a half-

supply, ground-reference voltage

generated on the chip.

❏ Both chips feature a power-down

mode that drops the power

supply current to zero, except for

reverse junction leakages (on the

order of 1µA total).

What the LTC1562-2 Can Do

Figure 1 is an overall diagram and

Figure 2 a per-section diagram for the

LTC1562-2. These are identical to the

diagrams for the LTC1562, except for

the values of the internal precision

components in Figure 2. In the

LTC1562-2, R1 is 7958Ω and C is

100pF. External resistors can be com-

bined with an LTC1562-2 section, as

shown in Figure 2, to deﬁne a second

order ﬁlter response with standard-

ized parameters f

, Q and gain. Design

equations and procedures appear in

the LTC1562-2 data sheet. For

example, in Figure 2, R2 sets f

; R

, a

multiple of R2, sets Q; and Z

sets

both the gain and the block’s func-

tion. The 3-terminal blocks minimize

the number of external parts neces-

sary for complete 2nd order sections

with programmable f

, Q and gain.

A resistor for Z

in Figure 2 gives

simultaneous lowpass (at V3) and

bandpass (at V1) responses. The data

sheet describes other ways to exploit

the virtual ground INV input. For

example, because the V1 output in

Figure 2 shows a phase shift of 180°

at the user-set center frequency, f

summing a V1 output with a feedfor-

ward path from the signal source

yields a notch response,

or with dif-

ferent weighting, allpass (phase

equalization), as used in Figure 5

later in this article. Using capacitors

together with the INV input’s sum-

ming capability provides further

powerful techniques for zero and

notch responses (which, in turn,

enable elliptic highpass and lowpass

ﬁltering). For example, the two out-

puts of each 2nd order section have a

90° phase difference, so summing V1

through a capacitor and V2 through a

resistor, into another section’s vir-

tual-ground input, gives the same

notch or allpass option mentioned

above but without devoting an addi-

tional section for phase shift.

Figures

5 and 9, described later, use this RC

notch method. Moreover, a capacitor

for Z

in Figure 2 yields simulta-

neous highpass and bandpass

responses; the capacitor sets voltage

gain, not critical frequencies, with a

relationship of the for m Gain = C

100pF in the LTC1562-2. Low level

signals can exploit the built-in gain

capability, which raises ﬁlter SNR

with low input voltage amplitudes.

Such abilities to tailor the use of each

block and its built-in time constants

are reminiscent of an operational

ampliﬁer—whence the term “opera-

tional ﬁlter.”

DC performance includes a typical

lowpass input-to-output offset of 3mV

and outputs that swing (under load)

to within approximately 100mV of

each supply rail. An internal half-

supply reference point (the AGND pin)

generates a reference voltage for the

inputs and outputs in single-supply

applications. The shutdown (SHDN)

pin accepts CMOS logic levels and in

20µs puts the LTC1562-2 into a

“sleep” mode, in which the chip con-

sumes approximately 1µA (the part

will default to this state if the pin is

left open). The 16-pin dies is pack-

aged in a 20-pin SSOP (the extra pins

in the SSOP are substrate connec-

tions, to be retur ned to the negative

supply for best per for mance).

The following application examples

are tailored for speciﬁc corner fre-

quencies, which can be modiﬁed by

properly scaling the external com-

ponents, as described in the data

sheet and in LTC1562 application

articles.

2, 3

Expert application assis-

tance can be obtained by calling us at

408-954-8400, x3761. Pin numbers

in the ﬁgures that follow are for the

20-pin SSOP package, where pins 4,

7, 14 and 17 (not shown) are always

tied to the negative power supply rail.

As with other ﬁlters, achieving low

noise and distortion levels requires

electrically clean construction (as well

as equipment that can measure such

performance).

Dual 4th Order 200kHz

Butterworth Lowpass Filter

Each half of the circuit in Figure 3

provides a classic 4th order lowpass

gain roll-off (24dB per octave) with a

maximally ﬂat passband. This schematic

includes power supply connections for a

split ±5V supply, one of the options

available for any LTC1562-2

INV C

V1 C

V2 C

–

AGND

V2 D

V1 D

INV D

INV B

V1 B

V2 B

SHDN

V2 A

V1 A

INV A

IN2

7.87k

10.2k

R22 7.87k

R24 7.87k

10.2k

IN4

7.87k

4.22k

R23 7.87k

IN3

7.87k

4.22k

R21 7.87k

IN1

7.87k

IN2

IN1

5V 0.1µF0.1µF–5V*

OUT1

OUT2

–

ALSO AT PINS 4, 7, 14 & 17

ALL RESISTORS 1% METAL FILM

LTC1562-2

20-PIN

SSOP

Figure 3. Dual 4th order 200kHz Butterworth lowpass ﬁlter

Linear Technology Magazine • February 1999

DESIGN FEATURES

application (Figure 5, in a different

application, illustrates connections

for a single 5V supply). The circuit of

Figure 3 is a higher frequency varia-

tion of a 100kHz dual 4th order

Butterworth lowpass ﬁlter using the

LTC1562, which appeared in the

February 1998 Linear Technology

magazine,

as well as in the LTC1562

data sheet. Figure 4 shows the mea-

sured frequency response for one of

the two ﬁlters in Figure 3. This ±5V

circuit supports rail-to-rail inputs and

outputs, with output noise of

approximately 60µV

RMS

, for a maxi-

mum SNR of 95dB (compared to

100dB with the L TC1562 equivalent

at half as much bandwidth). THD in a

RMS

output (2.8V

P-P

) was measured

as –87dB at 50kHz and –72dB at

100kHz.

256kHz Phase-Linearized

6th Order Lowpass Filter

Data communication and some sig-

nal antialiasing and reconstruction

applications demand ﬁlters with con-

trolled phase (or time-domain)

responses. The circuit in Figure 5

realizes a root-raised-cosine lowpass

gain response (Figure 6). For data

communications, this ﬁlter’s time-

domain pulse response (Figure 7)

approximates, in continuous time, the

ideal Nyquist-type property of cross-

ing zero at a time interval that is

equal to 1/(2f

). When used as a

pulse-shaping ﬁlter, this response has

the special property of producing mini-

mal intersymbol interference (ISI)

among successive data pulses at a

data rate of 2f

(512 kbits/second or

ksymbols/second for Figure 5) while

simultaneously limiting the trans-

mitted spectrum to a bandwidth

approaching the theoretical mini-

mum, which is f

Also, data or signal

acquisition (before A/D conversion)

or reconstruction (after D/A conver-

sion) can beneﬁt from the linear-phase

(that is, constant-group-delay)

response (typically ±300ns group

delay variation over the passband from

0 to f

, evident in Figure 8).

The ﬁlter in Figure 5 achieves these

properties by preceding a 6th order

lowpass section (the C, A, and D quar-

ters of the LTC1562-2 chip, in that

sequence) with a 2nd order allpass

response to linearize the phase. This

combination illustrates two practical

uses of the virtual-ground inputs in

the LTC1562-2. Combining two feed-

forward paths (R

FF1

from the input

and R

from a bandpass section in

the “B” quarter of the LTC1562-2)

yields the allpass equalization. Sub-

sequently, R

IN4

and C

IN4

sum together

two signals with 90° phase difference

from the two outputs of the “A” quar-

ter, with an additional 90° phase

difference caused by the capacitor , to

achieve a stopband notch at a desired

frequency.

Figure 5 operates from a

single supply voltage from 5V to 10V

(the AGND pin furnishes a built-in

GAIN (dB)

–10

–20

–30

–40

–50

–60

–70

–8050k 1.5M

FREQUENCY (Hz)

100k

16*

INV C

V1 C

V2 C

–

AGND

V2 D

V1 D

INV D

INV B

V1 B

V2 B

SHDN

V2 A

V1 A

INV A

LTC1562-2

20-PIN

SSOP

1.54k

FF1

6.19k

4.12k

R22 6.19k

R24 4.12k

7.32k

IN4

4.12k

7.32k

R23 4.12k

IN3

4.12k

IN1

7.5k

3.24k

R21 6.81k

5V 0.1µF1µF

OUT

–

ALSO AT PINS 4, 7, 14 & 17

ALL RESISTORS 1% METAL FILM

IN4

22pF 5%

GAIN (dB)

–10

–20

–30

–40

–50

–60

–70

–80

10k 1M

FREQUENCY (Hz)

100k

INPUT

1V/DIV

OUTPUT

(INVERTED)

200mV/DIV

1.953µs/DIV (= 1/512kHz)

DELAY (µs)

FREQUENCY (kHz)

50 100 150 200 250 300 350 400

Figure 4. Frequency response of one of the

two ﬁlters in Figure 3

Figure 5. 256kHz linear-phase 6th order lowpass ﬁlter

Figure 6. Gain response of Figure 5’s circuit Figure 7. Time-domain response of Figure 5’s

circuit Figure 8. Group delay response of Figure 5’s

circuit

Linear Technology Magazine • February 1999

DESIGN FEATURES

half-supply ground reference) and

exhibits –80dB THD at 50kHz for a

500mV

RMS

output with a 5V supply.

175kHz 8th Order

Elliptic Highpass Filter

In Figure 9, three response notches

below the cutoff frequency suppress

the stopband and permit a narrow

transition band in a 175kHz high-

pass ﬁlter, whose measured frequency

response appears in Figure 10. Each

notch is produced by summing two

180°-different currents into a virtual-

ground “INV” summing input, one

current passing through an R

and

the other (from a voltage 90° different

from the ﬁrst) through a C

This

circuit exhibits only 44µV

RMS

of out-

put noise over a 1MHz bandwidth and

THD of –70dB with a 200kHz signal,

0.5V

P-P

output, operating from a 5V

total supply.

400kHz Dual

6th Order Lowpass Filter

Although it is outside the 300kHz f

limit recommended for best accuracy,

this dual 6th order 400kHz Butter-

worth lowpass ﬁlter (Figure 11)

illustrates an extreme of bandwidth

available from the LTC1562-2 with

some compromises. The high f

requires unusually small resistor val-

ues, resulting in heavier loading and

an increase in distortion from the

L TC1562-2; it was also necessary to

adjust the R

resistors in Figure 11

downwards to correct for Q enhance-

ment encountered when the designed

is very high.

The circuit of Figure 11 supple-

ments the eight poles of ﬁltering in

the L TC1562-2 by driving all four of

the virtual-ground INV inputs from

R-C-R “T” networks (in place of resis-

tors) and thus obtaining additional

real poles (a method described in the

original LTC1562 application article

and data sheet). Two such real poles

replace the Q = 0.518 pole pair of a

conventional 6th order Butterworth

pole conﬁguration, to good accuracy.

The measured frequency response of

one 6th order section appears in Fig-

ure 12. With ±5V power, this circuit

permits rail-to-rail inputs and out-

puts and exhibits THD, at 1V

RMS

(2.8V

P-P

) output, of –92dB at 50kHz

and –79dB at 100kHz. Output noise

INV C

V1 C

V2 C

–

AGND

V2 D

V1 D

INV D

INV B

V1 B

V2 B

SHDN

V2 A

V1 A

INV A

IN2

20.5k

26.7k

R22 10k

R24 4.02k

3.24k

IN4

40.2k

59k

R23 11.3k

9.09k

R21 7.15k

5V 0.1µF0.1µF–5V*

OUT

–

ALSO AT PINS 4, 7, 14 AND 17

ALL RESISTORS 1% METAL FILM

ALL CAPACITORS 5% STANDARD VALUES

LTC1562-2

20-PIN

SSOP

IN1

220pF

IN2

82pF

IN3

47pF

IN3

45.3k

IN4

100pF

GAIN (dB)

–10

–20

–30

–40

–50

–60

–70

–80

–9050k 900k

FREQUENCY (Hz)

200k

INV C

V1 C

V2 C

–

AGND

V2 D

V1 D

INV D

INV B

V1 B

V2 B

SHDN

V2 A

V1 A

INV A

LTC1562-2

20-PIN

SSOP

IN2A

1.43k R

IN2B

576Ω

2.26k

R22 2k

R24 2k

2.26k

IN4A

1.43k R

IN4B

576Ω

6.19k

R23 2k

IN3B

576Ω

IN1B

576Ω

IN3A

1.43k

IN1A

1.43k

6.19k

R21 2k

IN2

IN1

5V 0.1µF0.1µF–5V*

OUT1

OUT2

–

ALSO AT PINS 4, 7, 14 & 17

ALL RESISTORS 1% METAL FILM

1000pF

5% C2

1000pF

5% C4

1000pF

Figure 9. 175kHz 8th order elliptic highpass ﬁlter

Figure 10. Frequency response of Figure 9’s

circuit

Figure 11. 400kHz dual 6th order Butterworth lowpass ﬁlter

GAIN (dB)

–10

–20

–30

–40

–50

–60

FREQUENCY (Hz)

100k

Figure 12. Frequency response of

Figure 11’s circuit

continued on page 35

Linear Technology Magazine • February 1999

DESIGN FEATURES

SOT-23 Switching Regulators Deliver

Low Noise Out puts in a Small Footprint

by Steve Pietkiewicz

Introduction

As portable electronics designers con-

tinue to press for reduction in

component sizes, Linear Technology

introduces the LT1611 and LT1613

SOT -23 switching regulators. These

current mode, constant frequency

devices contain internal 36V switches

capable of generating output power

in the range of 400mW to 2W , in a 5-

lead SOT-23 package. The LT1613

has a standard positive feedback pin

and is designed to regulate positive

voltages. The LT1611 has a novel

feedback scheme designed to directly

regulate negative output voltages

without the use of level-shifting cir -

cuitry. Boost, single-ended primary

inductance converters (SEPIC) and

inverting conﬁgurations are possible

with the LT1613 and LT1611. The

high voltage switch allows hard-to-

do, yet popular DC/DC converter

functions like four cells to 5V, 5V to

–5V, 5V to –15V or 5V to 15V to be

easily realized.

Both devices switch at a frequency

of 1.4MHz, allowing the use of tiny

inductors and capacitors. Many of

the components speciﬁed for use with

the L T1613 and LT1611 are 2mm or

less in height, providing a low proﬁle

solution. The input voltage range is

1V to 10V, with 2mA quiescent

current. In shutdown mode, the qui-

escent current drops to 0.5µA. The

constant frequency switching pro-

duces low amplitude output ripple

that is easy to ﬁlter, unlike the low

frequency ripple typical of pulse-

skipping or PFM type converters.

Internally compensated current mode

control provides good transient

response.

LT1613 Boost Converter

Provides a 5V Output

Figure 1’s circuit details a boost con-

verter that delivers 5V at 200mA from

a 3.3V input. The input can range

from 1.5V to 4.5V, making the circuit

usable from a variety of input sources,

such as a 2- or 3-cell battery, single

Li-Ion cell or 3.3V supply. Efﬁciency,

shown in Figure 2, reaches 88% from

a 4.2V input. Start-up waveforms from

a 3.3V input into a 47Ω load are

pictured in Figure 3; the converter

reaches regulation in approximately

250µs. The device requires some bulk

capacitance due to the internal com-

pensation network used. A 10µF

ceramic output capacitor can be used

with the addition of a phase-lead

capacitor paralleled with R1; this

capacitor is typically in the 10pF–

100pF range.

LT1613 5V to 15V

Boost Converter

By changing the value of the resistive

divider, a 15V supply can be gener-

ated in a similar manner to the 5V

converter shown in Figure 1. Figure 4

depicts the converter. L1’s value has

been changed to 10µH to provide the

same di/dt slope with a higher input

voltage. The converter delivers 15V at

60mA from a 5V input, at efﬁciencies

up to 85%, as shown in the efﬁciency

graph of Figure 5.

LT1613 4-Cell to 5V SEPIC

A 4-cell battery presents a unique

challenge to the DC/DC converter

designer. A fresh battery measures

about 6.5V, above the 5V output,

while at end of life the battery voltage

will measure 3.5V, below the 5V out-

put. Simple switching regulator

topologies like boost or buck can only

increase or decrease an input voltage,

3.3V

OUT

5V/200mA

1613 • TA01

4.7µHD1

GND

LT1613

L1: MURATA LQH3C4R7M24 (814) 237-1431

OR SUMIDA CD43-4R7 (847) 956-0666

C1, C2: AVX TAJA156M010R (803) 946-0362

D1: MOTOROLA MBR0520 (800) 441-2447

15µFC2

15µF

121k

374k

FBSHDN SHDN

+ +

LOAD CURRENT (mA)

0 50 100 150 200 250 300 350 400

EFFICIENCY (%)

1613 TA01a

100

VIN = 4.2V

VIN = 3.5V

VIN = 2.8V

VIN = 1.5V

OUT

1V/DIV

500mA/DIV

SHDN

5V/DIV

100µs/DIV

Figure 1. This boost converter steps up a 1.5V to 4.2V input to 5V.

It can deliver 250mA from a 3.3V input.

Figure 2. Efﬁciency of Figure 1’s boost

converter

Figure 3. Boost converter start-up with 3.3V input into a 50Ω load

Linear Technology Magazine • February 1999

DESIGN FEATURES

which will not do the trick in this

situation. The solution is a SEPIC. A

dual-winding inductor or two sepa-

rate inductors are required to make

this converter. Figure 6 details the

circuit. A Sumida CLS62-150 15µH

dual inductor is speciﬁed in the appli-

cation, although two 15µH units can

be used instead. Up to 125mA can be

generated from a 3.6V input. Figure

7’s graph shows converter efﬁciency,

which peaks at 77%. Transient

response with a 5mA to 105mA load

step is pictured in Figure 8. The con-

verter settles to ﬁnal value inside

200µs, with a maximum perturba-

tion under 200mV. The double trace

of V

OUT

under load in Figure 8 is

actually switching ripple at 1.4MHz

caused by the ESR of output capaci-

tor C2. A better (lower ESR) output

capacitor will decrease the output

ripple.

LT1611 5V to –5V

Inverting Converter

A low noise –5V output can be gener-

ated using an inverting topology with

the LT1611. This circuit, shown in

Figure 9, bears some similarity to the

SEPIC described above, but the out-

put is in series with the second

inductor. This results in a very low

noise output. The circuit can deliver

–5V at up to 150mA from a 5V input,

or up to 100mA from a 3V input.

Efﬁciency, described in Figure 10,

peaks at 75%. Figure 11 illustrates

the start-up waveforms. During start-

up, the switch-current increases to

approximately 1A. At this current,

the inductance of the Sumida unit

decreases, resulting in the increased

3V–7V V

OUT

15V/50mA

1613 • TA01

10µHD1

GND

LT1613

L1: MURATA LQH3C100 (814) 237-1431

C1: AVX TAJB226M016 (803) 946-0362

C2: AVX TAJA475M025

D1: MOTOROLA MBR0520 (800) 441-2447

15µFC2

22µF

121k

1.37M

FBSHDN SHDN

+ +

1nF

LOAD CURRENT (mA)

EFFICIENCY (%)

1611 TA02

0 102030405060

= 3.6V

= 6.5V

= 5V

70 10080 90

VIN

4V–7V

VOUT

5V/175mA

1613 • TA01

L1A

15µH

GND

LT1613

L1: SUMIDA CLS62-150 15µH (847) 956-0666

C1, C2: AVX TAJA156M016 (803) 946-0362

C3: X7R CERAMIC

D1: MOTOROLA MBR0520 (800) 441-2447

15µF

324k

FBSHDN SHDN

L1B

15µH

0.22µF

LOAD CURRENT (mA)

EFFICIENCY (%)

1611 TA02

0 25 50 75 100 125 150

= 3.6V V

= 5V

= 6.5V

175 200 225 250

ripple current noticeable in the switch-

current trace of Figure 11. After the

circuit has reached regulation, the

ripple current decreases by about a

factor of two. Switching waveforms

with a 100mA load are shown in Fig-

ure 12. Output voltage ripple is caused

by ripple current in the inductor mul-

tiplied by output capacitor ESR.

Although the 20mV

P-P

ripple pic-

tured in Figure 12 is low, signiﬁcant

improvement can be obtained by

judicious component selection. Fig-

ure 13 details the same 5 to –5V

OUT

100mV/DIV

AC COUPLED

105mA

5mA

LOAD

200µs/DIV

OUT

–5V/150mA

1613 • TA01

L1A

22µH

GND

LT1611

L1: SUMIDA CLS62-220 22µH (847) 956-0666

C1, C2: AVX TAJB226010 (803) 946-0362

C3: X7R CERAMIC

D1: MOTOROLA MBR0520 (800) 441-2447

22µF

10k

NFBSHDN SHDN

L1B

22µH

29.4k

0.22µF

Figure 4. This 4-cell to 15V boost converter can deliver 50mA

from a 3V input.

Figure 5. Efﬁciency of Figure 4’s circuit

Figure 6. This single-ended primary inductance converter (SEPIC)

generates 5V from an input voltage above or below 5V.

Figure 7. Efﬁciency of Figure 6’s SEPIC

reaches 77%.

Figure 9. This inverting converter delivers –5V at 150mA from

a 5V input.

Figure 8. SEPIC transient response at 5V input with a 5mA to 105mA

load step

Linear Technology Magazine • February 1999

DESIGN FEATURES

converter function with better output

capacitors. Now, output ripple mea-

sures just 4mV

P-P

. Additionally,

transient response is improved by the

addition of phase lead capacitor C5.

Figure 14 depicts load transient

response of a 25mA to 125mA load

step. Maximum perturbation is under

30mV and the converter reaches ﬁnal

value in approximately 250µs.

It is important to take notice of how

Figures 9 and 13 are drawn. D1’s

cathode is returned to the LT1611’s

GND pin before both connect to the

ground plane. This connection com-

bines the current of the switch and

diode, which conduct on alternate

phases. The summation of both cur-

rents equals a current with no abrupt

changes, minimizing di/dt induced

voltages caused by the few nanohen-

ries of inductance in the ground plane.

This summed current is then depos-

ited into the ground plane. If this

technique is not followed, 100mV

spikes can appear at the converter

output (I speak from experience: my

ﬁrst several breadboards had this

problem).

Many systems, such as personal

computers, have a 12V supply avail-

able. Although the LT1611 V

OUT

2V/DIV

500mA/DIV

SHDN

5V/DIV

OUT

200mV/DIV

AC COUPLED

100mA/DIV

10V/DIV

100ns/DIV

OUT

20mV/DIV

AC COUPLED

125mA

25mA

LOAD

has a 10V maximum, the 36V switch

allows a 12V supply to be used for the

inductor while the LT1611’s V

pin is

still driven from 5V, as indicated in

Figure 13. Signiﬁcantly more output

power can be obtained in this man-

ner, as illustrated in the efﬁciency

graph of Figure 15.

Figure 10. 5V to –5V inverting converter

efﬁciency reaches 76%.

Figure 11. 5V to –5V inverting converter start-up into a 47Ω load

Figure 12. Switching waveforms of inverting converter with 100mA load

Figure 13. Low noise inverting converter; component selection and

feedforward capacitor C5 reduce noise to 4mV

P-P

Figure 14. Transient response of low noise inverting converter is

under 30mV for a 25mA to 125mA load step. Steady-state output

ripple is 4mV

P-P

200µs/DIV

LOAD CURRENT (mA)

EFFICIENCY (%)

1611 TA02

0 25 50 75 100 125 150

= 3V

= 5V

OUT

–5V/150mA

1613 • TA01

L1A

22µH

GND

LT1611

L1: SUMIDA CLS62-220 22µH (847) 956-0666

C1: AVX TAJB226010 (803) 946-0362

C2: X7R CERAMIC

C3: Y5V CERAMIC

C4: SANYO POSCAP 10TPC68M (619) 661-6835

D1: MOTOROLA MBR0520 (800) 441-2447

22µF

4.7µF

68µF

10k

NFBSHDN SHDN

L1B

22µH

29.4k

0.22µF

2.2nF

5V OR 12V

(SEE TEXT)

continued on page 23

Linear Technology Magazine • February 1999

DESIGN FEATURES

Versatile New Switching Regulator

Fits in SO-8 by Craig Varga

Introduction

Linear Technology recently introduced

the LTC1530 synchronous buck

regulator controller. Although pack-

aged in an 8-pin SO, it has proven to

be remarkably capable and versatile.

The part is loosely based on the

popular LTC1430, but with numerous

enhancements. Features include

current limiting that senses the volt-

age across the R

DS(ON)

of the high-side

MOSFET (no sense resistor required),

built in soft-start, 1% accurate refer-

ence, gate drivers capable of handling

large MOSFETs, and micropower

shutdown. The error ampliﬁer trans-

conductance is higher than that of

previous generation parts and is

trimmed for accuracy and stabilized

over temperature. The I

MAX

current,

which programs current limit, has a

positive temperature coefﬁcient to

help cancel the positive temperature

coefﬁcient of the MOSFET’s R

DS(ON)

This allows for more consistent cur-

rent limit over temperature. Although

intended primarily for buck regulator

designs, the part has been successfully

designed into boost, positive-to-

negative and negative-to-positive

converters.

A Quick Look at the Insides

Figure 1 is the basic block diagram.

The L TC1530 is a voltage mode con-

trol, synchronous buck regulator

controller. An on-chip oscillator gen-

erates a 300kHz ramp waveform. The

output of the error ampliﬁer is com-

pared to this ramp by the PWM

comparator. So far, nothing extraor -

dinary. Current-limit circuitry,

however, is a little more unusual.

Instead of the traditional current

sense resistor , the LTC1530 relies on

the R

DS(ON)

of the high-side MOSFET

as its source of load current informa-

tion. This saves the space, cost and

the power dissipation of an additional

resistor in the power path. The pro-

gramming current (I

MAX

) has a positive

temperature coefﬁcient that approxi-

mates the positive TC of a MOSFET’s

DS(ON)

. This tends to ﬂatten the cur-

rent-limit trip point as a function of

temperature. In a slight overload, the

LTC1530 provides “square current

limiting.” In other words, the regula-

tor starts to look like a current source.

In the event of a signiﬁcant overload,

should the output fall to less than

one-half of the nominal output volt-

age, the soft-start capacitor will be

discharged very quickly. This forces

–

COMP

DISDR

INTERNAL

OSCILLATOR

LOGIC AND

THERMAL SHUTDOWN

POWER DOWN

–

REF

– 3%

REF

+ 3%

ERR MIN

= 2m

PWM

–

MAX

–

SENSE

FOR FIXED

VOLTAGE

VERSIONS

OUT

REF

– 3%

REF

+ 3%

REF

1530 BD

LVC

MAX

HCL*

MONO

HCL

*HCL = HARD CURRENT LIMIT

Ω

Figure 1. LTC1530 block diagram

Linear Technology Magazine • February 1999

DESIGN FEATURES

the regulator into shutdown for a

period of time, typically a few milli-

seconds. After the time delay, the

supply attempts to restart. If the over-

load still exists, the hiccup mode

operation will continue. Once the short

is removed, the regulator will start

normally.

Unlike its predecessor, the

LTC1530’s soft-start capacitor is

internal. The start-up rise time was

chosen to satisfy the vast majority of

application requirements. Turn on is

clean, well controlled and monotonic.

Since dynamic performance is of

extreme importance in many of today’s

systems, the LTC1530 incorporates

several features to provide improved

response times to load transients.

First are the min/max comparators.

These are a pair of comparators that

continuously monitor the output volt-

age. If the output is more than 3% on

either side of nominal, the appropri-

ate comparator forces the duty factor

to maximum or zero in an attempt to

restore the output to the correct level

as quickly as possible. Eventually,

the error ampliﬁer and main feed-

back loop will catch up and force the

output to settle nicely. The error am-

pliﬁer is also an improvement over

earlier designs. The transconduct-

ance and output impedance have both

been increased substantially from the

LTC1430 values. This has the effect

of raising the DC open-loop gain of

the ampliﬁer, resulting in better line

and load regulation. Transconduct-

ance is also trimmed to ensure

accuracy. The result is more predict-

able and repeatable loop response.

The ampliﬁer g

is temperature com-

pensated so loop gain stays nearly

constant over temperature extremes.

The LTC1530 also has a low power

shutdown mode. If the Comp pin is

pulled to ground with an open collec-

tor or open drain transistor, the

LTC1530’s quiescent current will drop

to approximately 45µA.

Virtually all integrated circuits have

some quirks that will get you in trouble

if you don’t pay attention. The

LTC1530 is no exception. Care must

be taken in choosing the power MOS-

FETs used in circuits that depend on

a charge pump to supply gate-drive

power. It is essential to select a FET

for the upper device that will be almost

fully enhanced before the PV

sup-

ply voltage reaches 8V with whatever

main input voltage happens to be

available. Failure to heed this

requirement can lead to a circuit that

may not start up properly at all times.

Standard logic-level FETs work ﬁne.

Be sure V

is less than 2V in the

worst case.

The cause of this start-up phe-

nomenon is related to the way the

current limit circuit behaves. Below a

level of 8V, current limit is dis-

abled. Assume for the sake of this

discussion that the main input sup-

ply is derived from 5V . At turn on, as

the charge pump gradually pushes

the PV

supply upward, the current-

limit circuit wakes up at 8V on PV

If the 5V supply is exactly 5V, the gate

drive available for the FET is only 3V

(8V – 5V). If the FET’s R

DS(ON)

is very

high relative to its nominal value at

this point, the current-limit circuit

may activate in a misguided attempt

to maintain control of the output cur-

rent. If, at the same time, the output

voltage has come up to less than one-

half of its ﬁnal value, the LTC1530

will respond by discharging the soft-

COMP

GND

MAX

LTC1530S8

12V

ON/OFF

1µF

16V

1µF

16V

C11

4.7µF, 16V

KEMET Ta

C2–C3

330µF, 6.3V

KEMET Ta

×2

2N7002

R10

10k

68pF

1800pF

10k

R4 750Ω

IRF7805

R3 100Ω

3.5µH

ETQP6F3R5SFA

C13

2200pF

1.0Ω

MBRS-

130T3

C12

0.22µF

D2 BAT54S

OPTIONAL, INSTALL IF NO 12V

JP1 JP2 JP3

75k

1.5V

68.1k

1.8V

20.5k

2.5V

11.3k

3.3V

OUT

1.5V, 1.8V,

2.5V OR 3.3V

AT 6A

270pF R1

16.5k

C8–C10

330µF

6.3V

KEMET Ta

×3

REF

= 1.233V

Figure 2. 6A buck regulator; output voltage is jumper selectable for 1.5V, 1.8V, 2.5V or 3.3V.

Figure 3. Output voltage at turn-on for Figure

2’s circuit

Linear Technology Magazine • February 1999

DESIGN FEATURES

start capacitor and trying to initiate a

restart.

As long as the output voltage has

reached a level of greater than one-

half of its ﬁnal value before the PV

voltage reaches 8V, the output will

continue to rise in current limit. If the

output is below this level, start-up is

not ensured. If the PV

supply is

derived from a 12V source instead of

charge pumped from the 5V supply,

this problem cannot occur.

A Few Circuit Examples

The LTC1530 turns out to be a rather

versatile device. Although intended

as a buck regulator, the part has been

successfully used in boost and buck-

boost designs. Figure 2 is a classic

buck topology. The circuit was

designed to handle approximately 6A

while maintaining a low proﬁle. Input

and output capacitors are tantalum

devices. The inductor is a very low DC

resistance design for high efﬁciency.

The input is 5V, while the output

voltage can be jumper selected for

3.3V, 2.5V, 1.8V or 1.5V. The photo

in Figure 3 shows the output voltage

rise at turn on. A clean, monotonic

rise is evident.

Figure 4 is a 3A design that has a

total height of less than 2.4mm. The

inductor is a Gowanda part #50-324,

which mounts through a hole in the

PCB for a total height above the board

of approximately 1.5mm. Output

ripple voltage is approximately

10mV

P-P

at a 3A load with the speciﬁed

Panasonic SP series output capaci-

tors. There are several options for the

main inductor. The overall smallest

size available is an IHLP-2525 by

Dale Electronics. It’s 3mm tall but

only 6.4mm on a side. Output ripple

is about 50% higher with this inductor.

Figure 5 is an example of a syn-

chronous boost regulator. The input

is 3.3V and the output is 5V. The

circuit is rated for a maximum output

current of 6A. Since the output cur-

COMP

GND

MAX

LTC1530S8

C12

1µF

16V

1µF

10V

C11

4.7µF

16V

C2–C3

47µF, 6.3V

×2

68pF

4700pF

10k

R4 750Ω

Q1A

Si4936DY

Q1B

Si4936DY

R5 100Ω

4.7µH

C11

0.1µF

D1 BAT54S

OUT

3.3V/3A

C8–C10

56µF

×3

REF

= 1.233V

470pF

16.9k

10k

C2, C3, C8–C10: PANASONIC SP TYPE

(201) 348-7522

L1: GOWANDA 50-324 (716) 532-2234

OR DALE IHLP2525 (605) 665-1627

(SEE TEXT)

IMAX

COMP

VFB

GND

PVCC

IFB

LTC1530S8

1µF

16V

C1–C2

470µF

16V

×2

C15

100pF C14

0.022µF

12k

IRF7801

L2**

10µHVOUT

5V/6A

C7, C8,

C11

470µF

6.3V

×3

C10

470µF

6.3V

VREF =

1.233V

71.5k

23.2k

L1*

2.5µH

LTC1517-5

VIN

GND

VOUT

C1–

C1+

FMM914

0.22µF

C12

10µF

16V

C13

1µF

16V

1µF X7R

1µF

X7R

VIN

3.3V

MBR0530

MBR0530 C5

0.22µF

L1: PULSE PE-53681 (619) 674-8100

L2: COILCRAFT DS3316P-102 (847) 639-6400

RS1

(OPTIONAL,

SEE TEXT)

Figure 4. 3.3V/3A regulator

Figure 5. 5V/6A synchronous boost regulator

Linear Technology Magazine • February 1999

DESIGN FEATURES

rent wavefor m is discontinuous, the

output ripple is inherently large in

any boost regulator. The second stage

LC ﬁlter is added to clean things up a

bit. The feedback divider connects to

the output before the LC ﬁlter for a

reason. If the divider is connected

after the LC ﬁlter, the extra 180° of

phase shift above the LC cor ner fre-

quency will make the regulator’s

feedback loop unstable. The DC re-

sistance of the inductor is small, so

the ef fect on load regulation is mini-

mal.

The LTC1517 charge pump is used

to generate a sufﬁciently high voltage

for the LTC1530 to function correctly

and also to ensure adequate gate

drive for the power MOSFETs. It runs

from the 3.3V input and delivers a

regulated 5V output. Once the main

output comes into regulation, charge

pump power is derived through D2.

This causes the LTC1517’s regulated

output voltage set-point to be exceeded

and D3 back biases, shutting the

LTC1517 down. Note that current

limit is disabled in this design by

grounding I

MAX

and connecting I

. Since in the boost topology there

is a direct DC path from input to

output, there is no point in using the

current limit feature except to protect

against inductor saturation. It is also

worth mentioning that the FET R

DS(ON)

cannot be used as the current sense

resistor in this application because

FET Q2’s drain is not common to V

If inductor saturation protection is

desirable, it is possible to install a

small value current sense resistor

between C2 and L1. Install an appro-

priate value resistor (R

) between C2

and L1; connect the I

MAX

pin to the C2

side of R

(instead of ground) and

connect I

directly to the input side

of L1. Just don’t expect the circuit to

limit current in the event of a short

circuit.

Figure 6 is a positive input to nega-

tive 5V output design. Since the

LTC1530 needs to be referenced to

the –5V output, the design requires

exter nal gate-drive circuitry for both

the main and synchronous FETs. The

absolute maximum voltage rating of

the LTC1530’s gate drive would be

exceeded if the high-side gate were

driven directly. Q3 and the associated

parts at the input to the LTC1693

gate driver provide the required level-

shift function. The synchronous FET

is driven by the other half of the

LTC1693. The driver is only required

at this location to match the propaga-

tion delay of the high-side drive.

Failure to pay attention to these details

will result in severely degraded efﬁ-

ciency. Output currents of up to 4A

can be obtained from this circuit.

Like the boost regulator, the output

currents are discontinuous, so ripple

on the output is somewhat high. A

small, second-stage LC ﬁlter can eas-

ily remedy this if desired.

Conclusion

The LTC1530 is a small, versatile

controller that is usable in numerous

topologies and over a wide range of

power levels. In the basic buck appli-

cations for which it was designed, the

LTC1530 permits the designer to

realize very simple, low parts count

designs that require minimal real

estate. The part provides clean turn-

on and current-limit characteristics.

With a little ingenuity, it is possible to

develop circuits dif ferent than those

that the part’s designers intended,

but which give excellent performance

nonetheless.

COMP

SENSE

GND

MAX

LTC1530-ADJ

1.3k

27µFR4

2.0k

10µFC4

0.1µF

2N3906

1000pF R

4.7k

0.22µF

2.7k

470Ω

1/4W

R9 1k

MBR0530T1

2N7002

4.7µFC6

0.1µF

365

4Q1

CIN

OUT

–5V/5A

OUT

2.5µH

4.7µF

1/2 LTC1693-2

1/2

LTC1693-2

R10

47Ω

1N4148

6.8µF

100Ω

1N4148

2.96k

VIN 5V

PANASONIC ETQP6F2R5FA

(201) 348-7522

3× SANYO 10MV1200GX

4× SANYO 6MV1500GX

(619) 661-6835

SUD50N03-10

L1:

OUT

Q1, Q2:

R7 3.3Ω

Figure 6. 5V to –5V/4A synchronous switching, inverting polarity converter

Linear Technology Magazine • February 1999

DESIGN FEATURES

16-Bit Parallel DAC Has 1LSB Linearity,

Ultralow Glitch and Accurate

4-Quadrant Resistors by Patrick Copley

Today’s fast paced marketplace has

developed a major appetite for high

resolution, high accuracy, fast digi-

tal-to-analog converters. System

requirements in instrumentation,

automatic test equipment, communi-

cations, waveform generation, data

acquisition and feedback control sys-

tems, among many other applications,

have fueled the need for 16-bit digital-

to-analog converters. Not only does

the converter need to meet the strin-

gent speed and accuracy requirements

of the system, it needs to do so in both

unipolar (0V to 10V) and bipolar (±10V)

modes of operation without degrada-

tion. To meet and exceed these

requirements, Linear Technology

introduces its LTC1597 16-bit paral-

lel, current output, low glitch,

multiplying DAC with 4-quadrant

resistors. Key features of the new

DAC include:

❏±1LSB maximum INL and DNL

over the industrial temperature

range

❏On-chip 4-quadrant resistors

allow precise 0V to 10V, 0V to

–10V or ±10V outputs

❏Ultralow, < 1nV-s midscale glitch

impulse

❏Small 28-pin SSOP package

❏Low supply power consumption:

10µW typical

❏Pin-compatible with the L TC1591

14-bit parallel, current output,

low glitch, multiplying DAC with

4-quadrant resistors.

Unique Features

of the LTC1597

The L TC1597 operates from a single

5V supply and provides both unipolar

0V to –10V or 0V to 10V and bipolar

±10V output ranges from a 10V or

–10V reference input using a single or

dual external op amp. The device

achieves bipolar operation using three

additional on-chip precision resistors.

The DAC consists of a precision thin-

ﬁlm R/2R ladder for the thirteen LSBs.

The three MSBs are decoded into

seven segments of resistor value R, as

shown in Figure 1. R is nominally

48k. Each of these segments and the

R/2R ladder carry an equally weighted

current of one-eight of full-scale. The

feedback resistor, R

, and 4-quad-

rant resistor , R

OFS

have a value of R/

4. 4-quadrant resistors R1 and R2

have a magnitude of R/4.

The reference pin presents a constant

input impedance of R/8 in unipolar

mode and R/12 in bipolar mode. The

output impedance of the current out-

put pin, I

OUT1

varies with DAC code.

96k 12k 12k

96k

48k

96k

48k

96k

DECODER

D15

(MSB) D13

D14

D15

D12 D11 D0

(LSB)

LOAD

REF

OUT1

AGND

CLR

DGND

1597 BD

DAC REGISTER

48k 48k 48k 48k 48k 48k 48k

12k

R1 3

COM

10 D14

11 D4

21 D3

24 D2

25 D0

OFS

• • •

12k

WR INPUT REGISTER

• • • •

RST

Figure 1. The LTC1597 16-bit CMOS DAC uses a precision thin-ﬁlm modiﬁed R/2R architecture to provide unsurpassed accuracy and stability.

Accurate 4-quadrant multiplication applications are now possible with on-chip resistors R1, R2 and R

OFS

. A built-in deglitcher reduces glitch

impulse to 1nV-s.

Linear Technology Magazine • February 1999

DESIGN FEATURES

An added feature of the LTC1597 is

a proprietary deglitcher that reduces

the glitch energy to below 1nV-s over

the DAC’s output voltage range.

The LTC1597 has a 16-bit parallel

input data bus and is double buffered

with two 16-bit registers. The double

buffered feature permits the updat-

ing of several DACs simultaneously.

The WR signal updates the input reg-

ister and the LD signal loads the DAC

on the rising edge of the LD signal.

The versatility of the interface also

allows the use of the input and DAC

registers in a master/slave or edge-

triggered conﬁguration. This mode of

operation occurs when WR and LD

are tied together to act as a clock

signal.

The asynchronous clear pin (CLR)

resets the LTC1597 to zero scale and

the LTC1597-1 to midscale. CLR re-

sets both the input and DAC registers.

The L TC1597 also features a power-

on reset.

16-Bit Accuracy

Over Temperature

The LTC1597 has ultralow linearity

drift of well below ±0.2LSB from

–45°C to 85°C. This allows the

LTC1597 to hold its accuracy of 1LSB

integral nonlinearity (INL) and differ-

ential nonlinearity (DNL) over time

and temperature. In the past, the

only DACs that approached this

accuracy over temperature were of

the autocalibrated type. These DACs

were very large, very expensive and

therefore not very practical for most

applications.

Figures 2a and 2b show the typical

INL and DNL curves of the LTC1597.

The outstanding 0.25LSB INL, 0.15

LSB DNL (typical) and very low drift

allow a maximum 1LSB speciﬁcation

over the extended industrial tempera-

ture range. For optimum performance,

the REF pin of the LTC1597 should be

driven by a source impedance of less

than 1kΩ. However, the DAC has been

designed to minimize source

impedance effects. An 8kΩ source

impedance degrades both INL and

DNL by a mere 0.2LSB.

Fast Settling:

Less than 2

s to within

0.0015% of Full-Scale

Now system designers no longer have

to make tough decisions in the trade-

off between accuracy and speed. The

solution is here. The combination of

the LTC1597 DAC and the LT1468 op

amp provides an industry ﬁrst: superb

16-bit settling of less than 2µs for a

10V step while maintaining 1LSB DC

accuracy.

Figure 3 shows the application cir-

cuit for unipolar mode. Figure 4 shows

the resulting full-scale 10V step set-

tling time of the LTC1597/LT1468

combination. With a 20pF feedback

capacitor , the optimized settling time

to 0.0015% is an amazing ≈1.7µs. A

DIGITAL INPUT CODE

–1.0

INTEGRAL NONLINEARITY (LSB)

–0.8

–0.4

–0.2

1.0

0.4

16384 32768

1597 G01

–0.6

0.6

0.8

0.2

49152 65535

DIGITAL INPUT CODE

–1.0

DIFFERENTIAL NONLINEARITY (LSB)

–0.8

–0.4

–0.2

1.0

0.4

16384 32768

1597 G02

–0.6

0.6

0.8

0.2

49152 65535

LTC1597

OFS

9828

R1 R

COM

REF 45

0.1µF

OUT1

20pF

OUT

0V TO

–V

REF

1591/97 F01b

AGND

DGND

10 TO 21,

24 TO 27

CLR

REF

–

LT1468

16-BIT DAC

R1 R2

DATA

INPUTS

Unipolar Binary Code Table

DIGITAL INPUT

BINARY NUMBER

IN DAC REGISTER

–V

REF

(65,535/65,536)

–V

REF

(32,768/65,536) = –V

REF

–V

REF

(1/65,536)

LSB

1111 1111 1111

0000 0000 0000

0000 0000 0001

0000 0000 0000

ANALOG OUTPUT

VOUT

MSB

1111

1000

0000

Figure 2. The outstanding INL and DNL

(typically less than 0.25LSB) and very low

linearity drift allow a maximum 1LSB spec to

be guaranteed over the industrial tempera-

ture range.

Figure 3. With a single external op amp, the LTC1597 performs 2-quadrant multiplication with

±10V input and 0V to –V

REF

output. With a ﬁxed –10V reference, it provides a precision 0V to

10V unipolar output.

500ns/DIV

GATED

SETTLING

WAVEFORM

500µV/DIV

LD PULSE

5V/DIV

Figure 4. When used with the LT1468 and a

20pF feedback capacitor (see Figure 3), the

LTC1597 can settle in an amazing 1.7µs to

within 0.0015%. The top trace shows the LD

pulse; the bottom trace shows the gated

settling waveform settling to 1LSB in 1.7µs.

2a.

2b.

Linear Technology Magazine • February 1999

DESIGN FEATURES

detailed discussion of 16-bit settling

time can be found in Linear Technol-

ogy Application Note 74, “Component

and Measurement Advances Ensure

16-Bit DAC Settling T ime.”

The ability to minimize settling time

is limited by the need to null the DAC

output capacitance, which varies from

70pF to 115pF, depending on code.

This capacitance at the ampliﬁer input

combines with the feedback resistor

to for m a zero in the closed-loop fre-

quency response in the vicinity of

200kHz–400kHz. Without a feedback

capacitor, the circuit will oscillate.

The choice of 20pF stabilizes the cir-

cuit by adding a pole at 1.3MHz to

limit the frequency peaking and also

optimizes settling time. The settling

time to 16-bit accuracy is theoreti-

cally bounded by 11.1 time constants

set by the feedback resistance and

capacitance.

Ultralow 1nV-s Glitch

Glitches in a DAC’s output when it

updates can be a big problem in pre-

cision applications. Usually, the

worst-case glitch occurs when the

DAC output crosses midscale. The

LTC1597’s new proprietary deglitcher

reduces the output glitch impulse to

1nV-s, which is at least ten times

lower than any of the competition’s

16-bit voltage output DACs. In addi-

tion, the deglitcher makes the glitch

impulse uniform for any code. Figure

5 shows the output glitch for a mid-

scale transition with a 0V to 10V

output range.

Unipolar 0V to 10V Outputs

with a Single Op Amp

Figure 3 shows the circuit for a 0V to

10V output range. The DAC uses an

external reference and a single op

amp in this conﬁguration. This cir-

cuit can also perform 2-quadrant

multiplication where the REF pin is

driven by a ±10V AC input signal and

OUT

swings from 0V to –V

REF

TIME (µs)

01234

OUTPUT VOLTAGE (mV)

1595 03 .eps

–10

+10 COMPETITOR’S DAC

LTC1597

1nV-s TYP

FREQUENCY (Hz)

–90

SIGNAL/(NOISE + DISTORTION) (dB)

–70

–50

–40

10 1k 10k 100k

1591/97 G03

–110 100

–60

–80

–100

= 5V USING AN LT1468

FEEDBACK

= 30pF

REFERENCE = 6V

RMS

500kHz FILTER

80kHz FILTER

30kHz FILTER

FREQUENCY (Hz)

–90

SIGNAL/(NOISE + DISTORTION) (dB)

–70

–50

–40

10 1k 10k 100k

1591/97 G04

–110 100

–60

–80

–100

= 5V USING TWO LT1468s

FEEDBACK

= 15pF

REFERENCE = 6V

RMS

500kHz FILTER

80kHz FILTER 30kHz

FILTER

FREQUENCY (Hz)

–90

SIGNAL/(NOISE + DISTORTION) (dB)

–70

–50

–40

10 1k 10k 100k

1591/97 G05

–110 100

–60

–80

–100

= 5V USING TWO LT1468s

FEEDBACK

= 15pF

REFERENCE = 6V

RMS

500kHz FILTER

80kHz FILTER

30kHz FILTER

LTC1597-1

OFS

9828

R1 R

COM

REF 45

0.1µF

OUT1

33pF

OUT

–V

REF

TO V

REF

1591/97 F02b

AGND

DGND

–

1/2 LT1112

10 TO 21,

24 TO 27

CLR

REF

–

1/2 LT1112

16-BIT DAC

R1 R2

DATA

INPUTS

Bipolar Offset Binary Code Table

DIGITAL INPUT

BINARY NUMBER

IN DAC REGISTER

REF

(32,767/32,768)

REF

(1/32,768)

–V

REF

(1/32,768)

–V

REF

LSB

1111 1111 1111

0000 0000 0001

0000 0000 0000

1111 1111 1111

0000 0000 0000

ANALOG OUTPUT

OUT

MSB

1111

1000

0111

0000

Figure 5. The proprietary deglitcher reduces

the output glitch to less than 1nV-s, which is

ten times less than any other 16-bit, voltage-

output DAC. Further, the deglitcher makes

the glitch uniform, independent of code.

Figure 6. LTC1597 multiplying-mode signal-to-noise vs frequency

6a. Unipolar-mode full-scale: the noise and

distortion (N + D) is less than –96dB for signal

frequencies up to 30kHz. Out to 100kHz, the

N + D is less than –78dB.

6b. Bipolar-mode zero-scale: the N + D is less

than –96dB for signal frequencies up to

30kHz. Out to 100kHz, the N + D is less than

–82dB.

6c. Bipolar-mode full-scale: the (N + D) is less

than –96dB for signal frequencies up to

30kHz. Out to 100kHz, the N + D is less than

–79dB.

Figure 7. With a dual op amp, the LTC1597 performs 4-quadrant multiplication. With a ﬁxed

10V reference, it provides a ±10V bipolar output. For fast bipolar settling applications, an

LT1468 can be used for the output ampliﬁer.

Linear Technology Magazine • February 1999

DESIGN FEATURES

0.92LSB (140µV) at 17 bits for room

temperature. The circuit uses the

LTC1597 in its unipolar mode with

the reference input inverted (–V

REF

by means of R1 and R2 and an exter-

nal op amp) for the output voltage

range 0V to V

REF

. When the sign bit

changes, the analog switch changes

the reference input polarity to nonin-

verting (V

REF

) for the output range 0V

to –V

REF

94dB SFDR

Digital Sine Wave Generator

Figure 9 shows the circuit diagram

for a variable frequency digital wave-

form generator. The circuit shows the

bipolar conﬁguration for the LTC1597

but the unipolar conﬁguration will

work just as well. For a sampling

frequency of 50kHz and an output

sine wave frequency of 1kHz, the sec-

ond harmonic distortion is –94dB and

the third harmonic is –101dB. The

on-chip deglitcher circuit minimizes

the code-dependent glitch (which

–

LTC203AC

LTC1236A-10

LT1468

16 15 14

123

15pF

R1 R2

R1 R

COM

REF

321

23 4 5

OFS

SIGN BIT

16 DATA

INPUTS

10 T0 21

24 TO 27

LTC1597

0.1µF

16-BIT DAC LT1468

0UT

AGND

DGND 22

20pF

OUT

9828

CLR

REF

Bipolar Sign Magnitude Code Table

DIGITAL INPUT

BINARY NUMBER

IN DAC REGISTER

REF

(65,535/65,536)

REF

(1/65,536)

–V

REF

(1/65,536)

–V

REF

(65,535/65,536)

LSB

1111 1111 1111

0000 0000 0001

0000 0000 0000

0000 0000 0001

1111 1111 1111

ANALOG OUTPUT

OUT

MSB

1111

0000

1111

SIGN

15V

Bipolar ±10V Output

with Two Op Amps

The LTC1597 contains all the 4-quad-

rant resistors necessary for bipolar

operation. For a ﬁxed 10V reference,

the circuit shown in Figure 7 gives a

precision –10V to 10V output swing,

with a minimum of external compo-

nents: a feedback capacitor and a

dual op amp. The bipolar zero error is

8LSB maximum over temperature. If

two LT1468 op amps are used instead

of the LT1112, the circuit can per-

form wider bandwidth 4-quadrant

multiplication, where the reference

input is driven by a ±10V AC input

signal and V

OUT

swings ±10V

Figure 6 shows a graph of the multiply-

ing mode total harmonic distortion and

noise of the L TC1597/LT1468 combi-

nation in both unipolar and bipolar

modes of operation. For AC signals less

than 40kHz, the THD+noise is superb

(better than 90dB) and is still very good

out to 100kHz (78dB). Filtering at the

output of the LT1468 is necessary to

reduce the noise bandwidth to accept-

able levels. The wider the bandwidth,

the higher the noise ﬂoor.

17-Bit Sign Magnitude DAC

Gives Perfect Bipolar Zero

Figure 8 shows a novel application of

the LTC1597, a 17-bit sign magni-

tude DAC, and the resulting output

coding. This circuit has an extremely

accurate bipolar zero error, which is

the offset voltage of the current-to-

voltage op amp plus the bias current

times the DAC feedback resistor. For

the LT1468, this corresponds to a

maximum bipolar zero error of

Figure 8. This 17-bit sign-magnitude DAC uses the LTC1597 in its unipolar mode with the reference bit inverted (–V

REF

) for the output range 0V

to V

REF

. When the sign bit changes, the analog switch changes the reference input polarity to noninverting (V

REF

) for the output range 0V to

–V

REF

. The resulting circuit produces an impressive bipolar zero error of 140µV (0.92LSB) max at room temperature—less than 1LSB at 17 bits.

Linear Technology Magazine • February 1999

DESIGN FEATURES

–

LTC1236A-10

R1 R2

R1 RCOM REF

321

23 4 5

ROFS

RFB

16 DATA

INPUTS

10 T0 21

24 TO 27

LTC1597

0.1µF

16-BIT DAC LT1468

I0UT

AGND

DGND 22

15pF

9828

WR CLR

CLR

10V

15V

LOWPASS

FILTER

–

LT1001

SINE ROM

LOOKUP

TABLE

PHASE

CLOCK

PHASE

TRUNCATION

16 BITS

PARALLEL

DELTA

PHASE

SERIAL

OR BYTE

LOAD

FREQUENCY CONTROL

PHASE ACCUMULATORn = 24–32 BITS

nnn

SERIAL OR

PARALLEL

DATA INPUT

M • fC

fO =

CODE

DAC OUTPUT ERROR

32,768

1720 G01

65,535

DAC TRANSFER CURVE

WITH IDEAL OP AMP

DAC TRANSFER CURVE WITH VOS IN CURRENT-TO-VOLTAGE OP AMP

OFFSET ERROR =

VOSI-to-V

GAIN ERROR =

VOSI-to-V

UNIPOLAR MODE

CODE

DAC OUTPUT ERROR

32,768

1720 G01

65,535

GAIN ERROR =

I-to-V

+ 4V

INV

BIPOLAR ZERO ERROR =

I-to-V

+ 2V

INV

DAC TRANSFER CURVE

WITH IDEAL OP AMP

NEGATIVE FULL-SCALE

ERROR = 2V

I-to-V

DAC TRANSFER CURVE WITH V

IN CURRENT-TO-VOLTAGE

OP AMP AND REF INVERTING OP AMP

BIPOLAR MODE

Figure 9. This digital waveform generator produces a 1kHz sine wave with a second harmonic distortion of –94dB. The sampling frequency is 50kHz.

Figure 10. The effect of op amp offset on the LTC1597 gain and offset errors in unipolar mode (left) and bipolar mode (right); op amp offset

has virtually no effect on DAC linearity; it merely shifts the end points.

reifilpmA

snoitacificepSreifilpmA

VµI

An A

Vm/V

egatloV esioN/Vn zH esioNtnerruC /ApzH etaRwelSsµ/V

htdiwdnaBniaG tcudorP

zHM

rewoP noitapissiD

1001TL522 01

7901TL0553.041800.0

)laud(2111TL0652.041800.0

)laud(4211TL07027.23.0

8641TL570156.0

Table 1. Amplifiers recommended for use with the LTC1597, with relevant specifications

008 0001 0051 0004 0005

21.0 52.0 2.0 61.0 5.422

8.0 7.0 57.0 5.21 09

6411 pmapo/5.01 pmapo/96 711

Linear Technology Magazine • February 1999

DESIGN FEATURES

LOAD CURRENT (mA)

EFFICIENCY (%)

1611 TA02

0 50 100 150 200 250 300 350

VIN

3.6V–7V

VOUT

–10V/60mA

1613 • TA01

L1A

15µH

GND

LT1611

L1: SUMIDA CL562-150 (847) 956-0666

C1: AVX TAJB226M010 (803) 946-0362

C2: X7R CERAMIC

C3: AVX TAJA685M016

D1: MOTOROLA MBR0520 (800) 441-2447

22µF

6.8µF

10k

NFBSHDN SHDN

L1B

15µH

68.1k

0.22µF

LOAD CURRENT (mA)

EFFICIENCY (%)

1611 TA02

0 25 50 75 100 125 150

= 3.6V V

= 5V

= 6.5V

LT1611 4-Cell to –10V

Inverting Converter

A –10V low noise output can be gen-

erated in a similar manner as the –5V

circuit described above. Figure 16’s

circuit can deliver –10V at up to 60mA

from a 3.6V input. Efﬁciency, graphed

in Figure 17, reaches a high of 78%.

Conclusion

The ﬂexibility of individually controlled

outputs in multiple-supply applica-

tions can make several LT1611/

LT1613 converters attractive com-

pared to a multiple-output ﬂyback

Figure 15. 12V supply at L1A increases

efﬁciency to 81% and output current to

350mA.

Figure 16. 4-Cell to –10V inverting converter delivers 75mA from a 4V input.

Figure 17. 4-cell to –10V converter efﬁciency

design with one large switching regu-

lator and a custom transformer.

Changing an output voltage on a

multiple output ﬂyback requires

changing the transformer turns ratio,

hardly a simple task. Conversely,

individual control of each output, us-

ing the multiple LT1611/LT1613

approach, provides for complete con-

trol of each output voltage as well as

supply sequencing. The LT1611 and

LT1613 SOT-23 switchers provide

small, low noise solutions to power

generation needs in tight spaces.

LT1611/LT1613, continued from page 13

causes distortion) by making the glitch

impulse both ultralow and uniform

with code.

Op Amp Selection

Considerations

A signiﬁcant advantage of the

L TC1597 is the ability to choose the

I-to-V output op amp to optimize sys-

tem accuracy, speed, power and cost.

Table 1 shows a sampling of op amps

and their relevant speciﬁcations for

this application.

The LTC1597 is designed to mini-

mize the sensitivity of INL and DNL to

op amp offset; this sensitivity has

been greatly reduced compared to that

of competing multiplying DACs. Fig-

ure 10 summarizes the effects of op

amp offset for both modes of opera-

tion. Note that the bipolar LSB size is

twice its unipolar counterpart. As Fig-

ure 10 shows, op amp offset has a

minimal effect on DAC linearity; it

merely shifts the end points.

The ampliﬁer’s input bias current,

which ﬂows through the feedback

resistor, adds to the output offset

voltage. The ampliﬁer’s ﬁnite DC open-

loop gain also degrades accuracy. The

DAC gain error is inversely propor-

tional to the open-loop gain and

feedback factor of the op amp. In

unipolar mode at full-scale the feed-

back factor is 0.5; for a 0.2LSB of gain

error (REF = 10V) at 16 bits, the open-

loop ampliﬁer gain should be greater

than 650,000.

The op amp’s input voltage and

current noise also limit DC accuracy.

Noise effects accuracy similarly to

voltage and current offsets and adds

in an RMS fashion. As with any pre-

cision application, and with wide

bandwidth ampliﬁers in particular,

the noise bandwidth should be mini-

mized with a ﬁlter on the output of the

op amp to maximize resolution.

Referring to Table 1, the LT1001

provides excellent DC precision, low

noise and low power dissipation. The

LT1468 provides the optimum solu-

tion for applications requiring DC

precision, low noise and fast 16-bit

settling.

Conclusion:

Wherever system requirements

demand true 16-bit accuracy over

temperature, the LTC1597 provides

the best solution. The LTC1597 has

outstanding 1LSB linearity over

temperature, ultralow glitch impulse,

on-chip 4-quadrant resistors, low

power consumption, asynchronous

clear and a versatile parallel

interface.Combined with the LT1468

op amp, the LTC1597 provides the

best in its class, 1.7µs settling time to

0.0015%, while maintaining superb

DC linearity speciﬁcations.

Linear Technology Magazine • February 1999

DESIGN FEATURES

Fast Rate Li-Ion Battery Charger

by Goran Perica

Introduction

The recent trend in notebook com-

puters has been toward increasing

battery operating time and faster

processor speeds. These two require-

ments, in conjunction with a need for

faster battery recharging (1–2 hours)

have placed a strain on battery charg-

ing circuits and wall adapters. A

typical notebook computer system

conﬁguration is shown in Figure 1.

W all adapters are typically AC/DC

converters with a 20V output at

3A–4A of load current. When a note-

book computer is running, all of the

available current from the wall adapter

may be consumed by the system,

with no power left for charging the

battery. However, as soon as the

system’s power requirements drop

below the wall adapter’s current limit,

the battery charging can resume. In

order to recharge the battery in the

shortest time possible, the recharg-

ing should start as soon as there is

any current left over from the system.

The ideal situation is when the sum of

battery charging current and the sys-

tem current is just below the wall

adapter’s current limit:

IIN_MAX > ISYS + ICHARGER

where I

IN_MAX

is the wall adapter cur-

rent limit, I

SYS

is the system load

current and I

CHARGER

is the battery

charger current.

To achieve this objective, it is nec-

essary to adjust the battery charger

current so that the sum of the two

currents is just below the maximum

available input current, I

IN_MAX

. The

LT1505 incorporates a patented bat-

tery charger input current limiting

function along with other functions

necessary to provide a complete,

single-chip battery charging circuit

solution.

LT1505 Features

The LT1505 is a constant-current

(CC), constant-voltage (CV) current

mode switching battery charger cir-

cuit with the following features:

❏ 0.5% voltage reference

❏ 5% output current regulation

❏ Output voltage is preset for 3 or 4

Li-Ion cells (12.3V, 12.6V, 16.4V

and 16.8V)

❏ Output voltage is programmable

from 1V to 21V

❏ Low V

-to-V

OUT

operation

(dropout <0.5V)

❏ Programmable AC wall adapter

current limiting

❏ Programmable peak battery

charging current

❏ Battery drain <10µA in shutdown

❏ 94% efﬁciency

Circuit Description

The LT1505 is a synchronous buck

converter using N-channel MOSFETs.

The LT1505 operates at 200kHz and

can be synchronized to an external

clock with a frequency higher than

240kHz. The LT1505 IC has an

undervoltage lockout circuit that

detects the presence of an input power

source and enables the battery charg-

ing. Once the undervoltage lockout

has been exceeded, the PWM will start

running and the input MOSFET M3 is

turned ON, thus reducing the voltage

drop across its internal body diode

BODY

(see Figure 2).

The LT1505 monitors the current

from the wall adapter and controls

the battery charger current. For

example, if a 3A, 20V wall adapter is

used along with a 12.6V Li-Ion bat-

tery pack, the peak battery charging

current, when the system is of f, can

be set to:

IBATT MAX = η × IIN_MAX × VIN/VBATT

where I

BATT MAX

is the maximum bat-

tery charging current when the system

is idle, η is the efﬁciency of battery

charger, V

is the wall adapter out-

put voltage and V

BATT

is the battery

charging voltage.

Assuming an efﬁciency of 90%, the

above example could provide battery

charging current in excess of 4A. The

LT1505 will reduce the battery charg-

ing current as soon as the system

current exceeds (I

IN_MAX

– I

CHARGER

For example, if a 20V, 3A wall adapter

is used and the system draws 2A from

the adapter, the available current for

charging the battery will be I

CHARGER

1A. The resulting battery charging

current I

BATT

will be:

IBATT = η × ICHARGER × VIN/VBATT

IBATT = 0.9 × 1A × 20V/12.6V = 1.428A

The input current from the wall

adapter passes through a current

sense resistor, R

. One part of the

input current goes to the system load

and the remaining part goes to the

LT1505 battery charger. The voltage

drop across R

is monitored by a

current comparator with a 90mV

threshold. Once the threshold of 90mV

is reached, the LT1505 will reduce

the programmed battery charging cur-

rent so that the peak input current

does not exceed the preset limit. Thus,

the maximum input current (I

IN_MAX

)

will be:

IIN_MAX = ISYSTEM + ICHARGER = 0.090V/RS4

INPUT FROM

WALL ADAPTER

INPUT

CURRENT

SENSE

Li-Ion

BATTERY

SYSTEM

LOAD

LT1505

BATTERY

CHARGER

Figure 1. Typical notebook computer power supply

Linear Technology Magazine • February 1999

DESIGN FEATURES

where I

SYSTEM

is the system load cur-

rent, I

CHARGER

is the LT1505 battery

charger current and R

is the cur-

rent sense resistor. With the r esistor

value of 0.025Ω in Figure 2, the input

current limit I

IN_MAX

will be set to

3.6A.

The battery charging current limit

is set by R

PROG

, R

and R

and is:

IBAT_MAX = (VPROG/RPROG) × (RS2/RS1)

where V

PROG

is the reference voltage

of 2.465V. The values in Figure 2 have

been selected for a current limit

BAT_MAX

) of 4A. Changing R

0.050Ω will set the I

BAT_MAX

to 2A.

Also, the peak battery charging

current (I

BAT_MAX

) can be programmed

by the host computer. The I

BAT_MAX

can be set in increments of 0.25A if

PROG

is replaced by a network of

resistors, as shown in Figure 3.

The battery charger in Figure 2

achieves high efﬁciency thanks to

synchronous operation and input

power FET. The efﬁciency is as high

as 94%, as can be seen in Figure 4.

PCB Layout

When laying out the PCB, a multilayer

layout with one of the inner layers as a

solid ground plane is recommended.

The LT1505 and low power compo-

nents associated with it should be kept

as close together as possible. Addition-

ally, all power components should be

kept together and next to LT1505 con-

trol circuitry. The goal is to keep all

high power switching currents as lo-

calized as possible. Components that

connect to the ground plane should

have vias placed as close as possible to

the pins connected to the ground plane.

Also, power components should have

larger or multiple vias connecting to

the ground plane. Avoid placing the

power components in such a way that

input and output currents ﬂow by the

LT1505 IC. Also, to keep the compo-

nent temperature rise low, use as much

copper as possible. The use of polygon

planes for high power nets such as the

ones connecting to V

, V

BAT2 BAT SENSE

LT1505

4.7Ω

BOOST BOOSTC

SPIN

PGND

AGND

4.1V

4.2V C

1µF

0.68µF

0.1µF

4.7µF

220pF

OUT

22µF

25V

×2

1µF

BAT

12.6V

BATTERY

NOTE: D

BODY

IS THE BODY DIODE OF M3

: SANYO OS-CON (619) 661-6835

L1: SUMIDA CDRH127 (847) 956-0666

Si4412

Si4412 D4

MBRS140

1N4148

475Ω

100k

4.75k

0.025Ω

Si4435

BODY

SYSTEM POWER

(FROM

ADAPTER)

22Ω

0.025Ω

10µH

330Ω

1505 F01

PROG

4.93k

0.33µF

200Ω

3 CELL

PROG

BGATE

COMP1

CAP

FLAG

SHDN

SYNC

INFET

TGATE

GBIAS

CLP

CLN

47µF

35V

1µF

0.1µF

LT1505

PROG

2A 1A 0.5A 0.25A

10k 20k 40.2k 80.6k R

330Ω

1µF

FROM

µP

{

4× 2N3904

OUTPUT CURRENT (A)

EFFICIENCY (%)

1611 TA02

01234

100

LIMITED

INPUT

POWER BATTERY

CHARGE

CURRENT

SENSE

BATTERY SUPPLIES

ADDITIONAL PEAK POWER

SYSTEM

LOAD

LT1505

BASED

CONVERTER

Figure 2. 4A Li-Ion battery charger

Figure 3. Programming of battery-charge current Figure 5. Typical telecom application

Figure 4. Efﬁciency of 4A, 12.6V battery

charger at 20V input

continued on page 35

Linear Technology Magazine • February 1999

DESIGN IDEAS

No R

SENSE

Controller Delivers 12V

and 100W at 97% Efﬁciency by Christopher B.

Umminger

Heat removal presents a thorny

problem in many of today’s compact

systems. This is especially the case

when power converters deliver high

output voltages with several amperes

of current and are processing tens to

hundreds of watts. In this regime, a

converter with only moderate efﬁ-

ciency will have a signiﬁcant amount

of waste heat and may require heat

sinks and additional air ﬂow. A very

high efﬁciency converter can reduce

the wasted power , which saves space

and lowers costs.

The circuit shown in Figure 1 is a

power converter that produces a 12V

output at up to 8.5A from an input

that can range between 12V and 28V.

The 100W of output power is con-

verted at 97% efﬁciency with only 3W

dissipated on the board. No special

heat sinks were used other than a

widened V

trace connected to the

drain of M1. This point reached a

maximum temperature of 75°C in a

25°C environment. L1 is a custom-

wound inductor using fourteen turns

of 15 gauge wire on a Magnetics, Inc.

Kool Mµ

77206-A7 core. The entire

converter takes up a volume of only

0.65in

and processes an impressive

150W per cubic inch.

The circuit uses the LTC1625 No

SENSE

™ controller to deliver the high

output voltage with excellent efﬁ-

ciency. This controller provides true

current mode control without using a

sense resistor by monitoring the volt-

age drop across the power MOSFET

switches. Eliminating the sense

resistor saves board space and

improves efﬁciency. In this applica-

tion, a 0.01Ω sense resistor would

dissipate about 0.7W at full load.

Many current mode controllers use

a sense resistor in series with the

inductor. Unfortunately, they must

restrict the maximum output voltage

due to limits on the input range of the

current comparator. However, the

LTC1625 has no such constraint. The

circuit in Figure 1 uses the LTC1625

in its adjustable mode, with the V

PROG

pin left open. The internal error

ampliﬁer compares the voltage at the

OSENSE

pin to a 1.19V reference and

an exter nal resistive divider sets the

output voltage.

Figure 2 shows that 97% efﬁciency

is achieved over a wide range of load

current. The application uses the FCB

pin to disable Burst Mode operation

and force continuous, synchronous

operation down to no load. Enabling

Burst Mode would keep the efﬁciency

above 90% down to a load of only

50mA. The current mode control of

the LTC1625 incorporates foldback

current limiting that reduces the out-

put current to 6A when the output is

shorted.

Kool Mµ is a registered trademark of Magnetics, Inc.

Figure 1. 100W, 12V, 8.5A supply Figure 2. Efﬁciency vs load current for

Figure 1’s circuit

EXTV

SYNC

RUN/SS

FCB

SGND

OSENSE

PROG

BOOST

INTV

PGND

LTC1625CS

FDS6670A

L1 15µHV

OUT

12V/8.5A

OUT

150µF

16V

×2

MBRS-

140T3

FDS6670A

4.7µF

CMDSH-3 C

0.22µF

R2 35.7k

R1 3.92k

100pF

20k

2200pF

0.1µF

1Ω

10µF

30V

×4

12V–28V

SANYO OS-CON 30SC10M (619) 661-6835

SANYO OS-CON 16SA150M

OUT

EFFICIENCY (%)

100

80 10

LOAD CURRENT (A)

24 8

= 24V

OUT

= 12V

Linear Technology Magazine • February 1999

DESIGN IDEAS

Generating Low Cost, Low Noise,

Dual-Voltage Supplies by Ajmal Godil

Some sensitive electronic applica-

tions, such as telecommunication and

data acquisition, require both 5V and

–5V low noise supplies, which may

have to be generated from a single

high voltage positive supply. The cir-

cuit in Figure 1 shows a cost-effective

way to generate 5V and –5V from a

single 10V–28V supply by using the

low noise LT1777 and a few off-the-

shelf components.

The LT1777 is a step-down regula-

tor specially designed for low noise

applications. In order to achieve low

noise, the LT1777 is equipped with

dI/dt limiting circuitry, which is pro-

grammed via a small external inductor

in the power path. It also contains

internal circuitry to limit the dV/dt

turn-on and turn-off ramp rates. Fig-

ure 2 shows the V

node voltage and

the V

node current for the low noise

LT1777. Figure 3 shows the V

node

voltage and V

node current for the

high voltage LT1676 buck regulator

under the same test conditions. It can

be seen from Figures 2 and 3 that the

IV5

DAOL

)Am(

dewollamumixaM ehtnotnerruc )Am(ylppusV5–

V01=

0504

00107

002011

003031

053041

V81=

0509

001051

002002

003032

053002

V82=

05031

001081

002062

003072

053032

Table 1. Allowable load current on the –5V

supply vs input voltage and 5V load current

SHDN

SYNC

SGND

GND

LT1777

10V–28V C6

100µF

63V

100pF

2200pF

22k

SENSE

0.47µHL1B

200µH

MBRS-

1100

D2 MBRS1100

L1A

200µH

100µF

10V

100µF

10V

1µF

10V

1µF

10V

36.5k

12.1k

OUT

5V*

–V

OUT

–5V*

C2**

4.7µF

L1A/B:

SENSE

C3, C7:

C6:

C2:

COILTRONICS CTX200-4

(561) 241-7876

GOWANDA SML32-470K

(716) 532-2234

AVX TPSD107M010R0065

(803) 946-0362

63CV1D0BS

AVX 1206YG475

SEE TABLE 1 FOR RELATIONSHIP BETWEEN LOAD

ON +V

OUT

AND MAXIMUM CURRENT ON –V

OUT

THIS IS A CERAMIC CAP, BUT A

TANTALUM CAP COULD ALSO BE USED

NODE

VOLTAGE

10V/DIV

NODE

CURRENT

200mA/DIV

500ns/DIV

NODE

VOLTAGE

10V/DIV

NODE

CURRENT

200mA/DIV

500ns/DIV

Figure 1. This cost-effective supply generates ±5V from a 10V–28V input.

Figure 2. V

node voltage and node current for the

LT1777 Figure 3. V

node voltage and node current for the

LT1676

continued on page 29

Linear Technology Magazine • February 1999

DESIGN IDEAS

Switched Capacitor Voltage Regulator

Provides Current Gain by Jeff Witt

A switched capacitor voltage

inverter is normally used to generate

a negative supply voltage from a posi-

tive input supply. The negative supply

current is equal in magnitude to the

current drawn from the input. This

design idea describes two circuits that

use an inverter to double the current

between the input and output,

increasing efﬁciency and eliminating

heat dissipation problems.

More Efﬁcient than a Linear

If the roles of the ground and output

pins are swapped (Figure 1), an

inverter will divide the input voltage

by two. This circuit can be used in

place of a linear regulator when the

input voltage is more than twice the

desired output, for example, regula-

tion of 12V to 5V or 3.3V.

The circuit’s operation is illustrated

in Figure 2. An internal oscillator

alternately closes and opens four

switches. In the ﬁrst half cycle,

switches 1 and 2 are closed and cur-

rent ﬂows from the input to the output,

charging C1. In the second half cycle,

switches 3 and 4 are closed, dis-

charging C1 into the output. The cur-

rent delivered to the output is

continuous and equal to twice the

average input current. Because the

output current is continuous, the

output voltage ripple is low. Note that

C1 and C

OUT

do not need to be

matched, as their voltages are equal-

ized on each cycle.

Figure 3 shows the actual circuit.

Instead of halving the input voltage,

the LT1054 modulates the input cur-

rent (through switch 1 of Figure 2) to

regulate the output voltage. This cir-

cuit can deliver 200mA at 5V from an

input of 11.2V to 13V. Typical efﬁ-

ciency is 74%, compared to 42% for a

linear regulator. More importantly,

dissipation is decreased from 1.4W

for the linear regulator to 0.35W, eas-

ily managed by the LT1054’s 8-pin

sur face mount package. For a 3.3V/

200mA output, the circuit is 49%

efﬁcient, compared to a linear

regulator’s 27%, with power dissipa-

tion reduced from 1.8W to 0.7W. A

6.2Ω resistor in series with C1 shares

the dissipated power with the LT1054;

no heat sink is needed.

Three Diodes

Improve the Inverter

The same advantages can be realized

while generating a negative output.

However, a switched capacitor inverter

does not have the right compliment of

switches. By adding three diodes (see

Figure 4), the inverter can charge two

capacitors in series and then dis-

charge them in parallel to an output

capacitor. The absolute value of the

output voltage will equal half of the

input voltage, minus some loss due to

the switches and diodes.

Figure 5 shows a practical circuit,

which converts 12V to –4V. The

LT1054’s servo loop keeps the output

regulated to –4V over an input range

of 11V to 15V and a load current up to

Figure 1. Rewiring a switched capacitor inverter for step-down regulation results in

a current gain of 2.

Figure 2. The LT1054’s internal switches alternately charge and discharge C1, delivering

a continuous current to the output.

OUT

CAP

–

GND

–V

OUT

CAP

–

GND

V/2

COUT

VOUT

VIN

COUT

VOUT

VIN

CURRENT FLOW

Linear Technology Magazine • February 1999

DESIGN IDEAS

OUT

CAP

CAP–

GND

C1*

10µF

39.2k

R3*

200k 330pF

R4*

33k

12V

OUT

5V/200mA

REF

FB/SHDN

*FOR 3.3V/200mA, SET R4 = 147k, PUT 6.2Ω IN SERIES

WITH C1 AND PRELOAD WITH R4 = 2.2k

LT1054CS8

OUT

CURRENT FLOW

OUT

D2 D3

33µF

6.8µF

33µF

20.0k

86.6k

11V–15V

OUT

–4V/100mA

CAP

–

CAP

OUT

REF

FB/SHDN

GND

U1 LT1054CS8

AVX TAJB336M010R

AVX TAJB685M025R

MOTOROLA MBR0520LT1

IR IRLML2402

C1, C2, C3:

C4:

D1, D2, D3:

Q1:

100mA. (Unfortunately, there is too

much voltage loss to regulate to –5V

from a 12V source.) Note that many

negative supplies will power loads

that can pull the output above ground

(op amp circuits in particular); Q1

prevents such a load from pulling

U1’s V

OUT

pin above its ground pin.

Because most of U1’s operating

current ﬂows out of its ground pin,

the input current to this circuit is a

bit more than one-half of the output

current. While delivering 100mA, the

input from 12V was measured at

64mA, resulting in 53% efﬁciency.

One alternative, a switched capacitor

inverter followed by a linear regula-

tor, would be 33% efﬁcient at best and

power dissipation would be 0.8W. This

circuit dissipates only 0.35W, allow-

ing this all–surface mount circuit to

run cool.

Figure 3. This switched capacitor regulator doubles the current

between the input and the output, increasing efﬁciency and

eliminating the need for a heat sink.

Figure 4. Adding three diodes to a switched capacitor inverter doubles the current between the input and the output.

Figure 5. This circuit converts 12V to –4V. Only 63mA of input current

is required for 100mA of output current.

switch node voltage and current wave-

forms for the LT1777 are more

controlled and rise and fall more slowly

than those of the LT1676 regulator.

By slowing down the sharp edges

during turn-on and turn-off for the

power switch, conducted and radi-

ated EMI are reduced.

The circuit in Figure 1 shows three

inductors: L1A, L1B and L

SENSE

. L1A

and L1B are two windings on a single

core to generate ±5V. C2 has been

added to minimize coupling mis-

matches between the two windings

(L1A and L1B); this forces the wind-

ing potentials to be equal and improves

cross-regulation. This creates the dual

SEPIC (single-ended primary induc-

tance converter) topology. L

SENSE

is a

user-selectable sense inductor to pro-

gram the dI/dt ramp rate (see the

LT1777 Data Sheet for more informa-

tion). Table 1 summarizes the

allowable load current on the –5V

supply as a function of input supply

voltage and the load current on the

5V supply. Note that 5V and –5V

supplies are allowed to droop by 0.25V,

which corresponds to 5% load

regulation.

LT1777, continued from page 27

Linear Technology Magazine • February 1999

DESIGN IDEAS

High Current Step-Down Conversion

from Low Input Voltages by Dave Dwelley

Many modern logic systems run

with 3.3V as the sole power source. At

the same time, some modern micro-

processors and ASICs require supply

voltages of 2.5V or less. Traditional

step-down switching regulators can

have difﬁculty running from the 3.3V

supply, because affordable power

MOSFETs generally require 5V gate

drive to work efﬁciently. Two attractive

solutions to generating 2.5V or less

from a 3.3V supply are possible using

the L TC1649 and the L TC1430A.

The L TC1649 is a switching regu-

lator controller designed to use 5V

MOSFETs while running from an input

supply as low as 2.7V. No 5V supply

is required. The LTC1649 includes an

A typical circuit is shown in Figure

1. The 3.3V supply voltage at V

converted to a regulated 5V output at

OUT

. This 5V supply powers the

CC2

and V

pins to provide gate

drive to Q3. Q1 and Q2 require an

additional charge-pump stage to drive

their gates above the V

supply volt-

age. D1 and C2 provide this boosted

supply at PV

CC1

. The voltage feedback

loop is closed through R1 and R2,

with loop compensation provided by

an RC network at the COMP pin. Soft-

start time is programmed by the value

of C

. Maximum output current is

set by R

IMAX

at the I

MAX

pin and is

sensed across the R

DS(ON)

of the Q1/Q2

pair, eliminating the need for a high

current external resistor to monitor

current. The circuit boasts efﬁciency

approaching 95% at 5A (Figure 2).

Some applications have a small 5V

supply available, but need to draw

the load current from the 3.3V sup-

ply. Such an application can use the

circuit shown in Figure 3, with the

OUT

2.5V/15A

MAX

SHDN

1µF

3.3V

LTC1649

VCC2

VCC1

COMP

SS C

–

GND CP

OUT

C2 1µF

10µF

MBR0530

0.1µF

0.01µF

IRF7801 = INTERNATIONAL RECTIFIER (310) 322-3331

MBR0530 = MOTOROLA (800) 441-2447

7.5k

EXT

1.2µH

220pF

10µF

MBR0530

MAX

51k

R3 22ΩR4 1k

IRF7801

Q1, Q2

IRF7801

TWO IN

PARALLEL

OUT

4400µF

3300µF

SHDN

12.7k

12.4k

1649 TA01

0.33µF

LOAD CURRENT (A)

0.1 1 10 100

EFFICIENCY (%)

1649 TA02

100

OUT

2.5V/15A

MAX

SHDN

3.3V

LTC1430A

VCC2

VCC1

COMP

GND

C2 1µF

0.1µF

0.01µF

7.5k

EXT

1.2µH

220pF

10µF

MBR0530

MAX

51k

R3 22ΩR4 1k

IRF7801

Q1, Q2

IRF7801

TWO IN

PARALLEL

OUT

4400µF

3300µF

SHDN

12.7k

12.4k

1649 TA01

SENSE

–

FREQSET

PGND

IRF7801 = INTERNATIONAL RECTIFIER (310) 322-3331

MBR0530 = MOTOROLA (800) 441-2447

Figure 1. 3.3V to 2.5V/15A converter using the LTC1649

Figure 3. 3.3V to 2.5V/15A converter using a 5V auxiliary supply and the LTC1430A

Figure 2. Efﬁciency of Figure 1’s circuit

continued on page 35

onboard charge pump to generate the

5V gate drive that the external power

MOSFETs require. It also features an

architecture designed to use all

N-channel external MOSFETs and a

high performance voltage mode feed-

back loop to ensure excellent transient

response for use with high speed

microprocessors and logic.

Linear Technology Magazine • February 1999

DESIGN IDEAS

How to Design High Order Filters with

Stopband Notches Using the LTC1562

Operational Filter (Part 2) by Nello Sevastopoulos

This is the second in a series of

articles describing applications of the

LTC1562 connected as a lowpass,

highpass or bandpass ﬁlter with added

stopband notches to increase selec-

tivity. Part 1 (Linear Technology VIII:2,

May 1998, pp. 28–31) described one

method of coupling the four Opera-

tional Filter™ building blocks of the

LTC1562 to design an 8th order low-

pass ﬁlter with two stopband notches.

Part 2 expands the technique of Part

1 to design an 8th order bandpass

ﬁlter with two stopband notches.

Throughout this series of articles,

notches will be generated by ﬁrst sum-

ming the input signal with a 180

degree out-of-phase signal appearing

at the output(s) of the LTC1562

Operational Filter and second, by ad-

justing the summation gains to yield

a zero sum.

Part 1 showed one proprietary

method of creating notches in the

stopband of a lowpass ﬁlter. The

essence of this method is brieﬂy

revisited in Figure 1, where two of

four Operational Filter sections are

coupled to for m a 4th order lowpass

ﬁlter with one stopband notch. The

notch is obtained by summing the

input signal, V

, with the output,

V1A, into the inverting node of the

next section of the IC. The two sig-

nals, V

and V1A, will tend to cancel

each other at a frequency where they

are 180 degrees out of phase. The

cancellation will be complete if the

amplitudes of V

and V

yield equal

(and opposite) currents at the sum-

ming junction of the op amp of Figure

1, that is if:

RIN2 = RFF2 • (RQ1/RIN1) (1)

In Figure 1, the lead capacitor C

IN1

raises the frequency where a 180

degree phase shift occurs above the

center frequency of the 2nd order

section (f

). The resulting notch fre-

quency is then higher than the cutoff

frequency of the 4th order ﬁlter.

Figure 1 can be easily modiﬁed to

make the frequency of the notch lower

than the center frequency of the 2nd

order section from which it is derived.

This is useful in bandpass ﬁlters where

an unwanted frequency lower than

the center frequency of the ﬁlter must

be rejected. This is shown in Figure 2,

where the input signal is summed

with output V2A instead of output

V1A. The frequency of the resulting

notch is:

= f

• R1

IN1

R21

IN1

1–

••(2)

(R1 = 10k; C = 159.15pF)

and the gain conditions dictating

Equation 1 now translate to:

R1 C

IN1

•(3)

IN2

= R

FF2

•

(

The circuit of Figure 2 can be used

to build a 4th order bandpass ﬁlter

with one notch below its center

frequency. Such a ﬁlter can simulta-

neously detect a tone and reject an

unwanted frequency located in the

vicinity of the passband.

–

sCR1

–

sCR1

R22

FF2

IN2

R21

IN1

1/2 LTC1562

R1, C ARE PRECISION INTERNAL COMPONENTS

R1 = 10k; C = 159.15pF

V2A

V1B

V2B

R21

IN1

LTC1562

V1A

V2A

(OTHER CONNECTIONS

AS SHOWN IN FIGURE 1)

Figure 1. Two out of four Operational Filter sections are coupled to form a 4th order lowpass

ﬁlter with one stopband notch.

Figure 2. Figure 1’s circuit modiﬁed to make

the frequency of the notch lower than the

center frequency of the 2nd order section

from which it is derived.

Linear Technology Magazine • February 1999

DESIGN IDEAS

The notch techniques of Figures 1

and 2 will be referred as “feedfor-

ward.” This is necessary to separate

these techniques from others to be

shown later , in Part 3 of this series of

articles.

The feedforward notch technique

of Figure 2 can be advantageously

combined with Figure 1 to realize

sharp bandpass ﬁlters with two stop-

band notches: one notch below and

one above the center frequency. Fil-

ters of this type can be very selective,

although they are quite cumbersome

to design. A step-by-step design pro-

cedure is illustrated below.

A Practical Example

An 8th order 100kHz bandpass ﬁlter

is realized, through FilterCAD™ for

Windows

(available at no charge from

Linear Technology—see the “Design

Tools” page in this issue), by cas-

cading four 2nd order sections of

equal Q. The –3dB band-edges are

arithmetrically symmetric with

respect to the ﬁlter’s 100kHz center

frequency and signals below 80kHz

and above 125kHz are attenuated by

60dB or more. Figure 3 shows the

theoretical amplitude response and

Table 1 shows the desired ﬁlter

parameters, namely, the center fre-

quencies, Qs and notch frequencies.

The ﬁlter of Figure 3/T able 1 can be

realized by decomposing the 8th order

realization into two independent 4th

order ﬁlter sections and then cascad-

ing these two 4th order sections, which

is an easier task than designing an

8th order elliptic bandpass ﬁlter all at

once. FilterCAD, in custom mode,

should be used to perform this opera-

tion. Figure 4 and Table 2 show the

ﬁlter decomposition and the cascad-

ing sequence; note the left and right

notches. Figure 5 uses the L TC1562

Operational Filter to realize the ﬁlter

of Figure 3 as decomposed in Figure

4. The design is split into two 4th

order sections. The algorithm to

calculate the external passive com-

ponents is outlined below.

In order to obtain a practical real-

ization that closely approximates the

theoretical one, the Q of each 2nd

order section will be lowered by 15%.

(Please consult the LTC1562 ﬁnal data

sheet.)

In order to follow the long and

tedious algorithm below, consider the

intuitive outline: We need to calculate

the following set of passive compo-

nents for the ﬁrst 4th order section:

IN1

, C

IN1

, R21, R

, and R

IN2

, R

FF2

R22 and R

. The resistors R21, R

R22 and R

are easily calculated via

the expression for the center fre-

quency, f

, and Q

for the 2nd order

section “i.” The expression for the

notch, equation (2), involves the prod-

uct of R

IN1

• C

IN1

, so neither component

can be calculated separately. Instead,

IN1

is calculated by considering the

maximum gain (which occurs around

the center frequency f

) at either

node V1A or V2A. This controls pre-

mature internal clipping. Once R

IN1

set, C

IN1

is easily calculated via equa-

tion (2) for the lower band notch.

Similarly, equation (3) deﬁnes the ra-

tio of R

IN2

to R

FF2

, so neither of these

components can be calculated inde-

pendently of the other. R

FF2

calculated by considering the gain

factor (“GAIN”) of the 4th order ﬁlter

section at the V1B output (Figure 1/

Table 2)). Once R

FF2

is set, R

IN2

calculated via equation (3).

epyT

3e7869.990000.01——————PB

3e4699.690000.013e4182.921———NPL

3e2230.3010000.013e3203.77———NPH

3e0000.0010000.01——————PB

Table 1. Parameters of the four sections of an 8th order, 100kHz bandpass filter

–20

–40

–60

–80

–100

–12050 60 70 80 90 100 120 130110 140 150

FREQUENCY (kHz)

GAIN (dB)

–65dB

BANDWIDTH

–20

–40

–60

–80

–100 50 60 70 80 90 100 120 130110 140 150

FREQUENCY

(

kHz

)

GAIN (dB)

50 60 70 80 90 100 120 130110 140 150

FREQUENCY

(

kHz

)

k4699.69=01=1Q

k7869.99=01=2Qf

k3.77=

M)s(D/)s(N•NIAG=)s(H

M3282.0=NIAG

Ms(s1A=)s(N

01•2709•532+

)

M01•2218.26=1A

k001=01=3Q

k2230.301=01=4Qf

k4182.921=

M)s(D/)s(N•NIAG=)s(H

M8871.0=NIAG

Ms(s1A=)s(N

01•38•956+

)

M01•9138.26=1A

Table 2. Filter decomposition and cascading sequence

Figure 3. Theoretical amplitude response of

8th order, 100kHz bandpass ﬁlter

Figure 4. Cascading two 4th order bandpass sections to realize the ﬁlter of Figure 3.

Linear Technology Magazine • February 1999

DESIGN IDEAS

The same design method is later

repeated to derive the passive compo-

nents for the second 4th order section:

I. Calculate the passive components

of the of the ﬁrst 4th order

section

= 96.9964kHz, Q = 8.5, f

99.9687kHz, Q = 8.5, f

77.3kHz)

1. Calculate the center frequency-

setting resistor, R21:

(For details, please refer to the

L TC1562 data sheet.)

R21 = (100kHz/f

)

• 10k =

10.629k

(choose the closest 1% value,

R21 = 10.7k (1%))

2. Calculate the Q-setting resistor,

(For details, please refer to the

L TC1562 data sheet)

= Q1 √R21 • 10k = 87.925k

(choose the closest 1% value,

= 86.6k (1%))

3. Calculate the input resistor R

IN1

from the following expression(s):

3a. if f

≤100kHz (for L TC1562)

(4)

IN1

•

R21

•

(

N22

O12

–

•

1 +

IN1

= 95.56k

Although not applicable for this

example, thoroughness dictates men-

tioning the case below:

3b. if f

≥ 100kHz (for L TC1562)

(5)

IN1

= RQ1 •

(

N22

O12

1 –

•

1 +

Make sure, in either case 3a or 3b,

that R

IN1

is greater than R21, that is,

the DC gain at pin 3 in Figure 5 is less

than unity; if not set R

IN1

= R21 and

proceed to step 4a.

The expression for R

IN1

sets the

gain at f

equal to unity at the node

of maximum swing (V1A or V2A). Note

that, for high Qs, the gain at f

is the

maximum gain. If you know the spec-

trum of the signals that will be applied

to the ﬁlter input and if internal gains

higher than unity will be allowed, the

value of R

IN1

can be reduced to improve

the input signal-to-noise ratio.

4a. Use the value of R

IN1

, calcu-

lated above, and calculate the

value for the input capacitor

IN1

from the notch equation (2).

(6)

IN1

(

N22

O12

1 –

R21

IN1

••C

< f

; C = 159.15pF)

CIN1 = 5.639pF.

Use the commercially available NPO

type 0402 surface mount capacitor

with the value nearest the ideal value

of C

IN1

calculated above. For instance,

for C

IN1

, choose an off-the-shelf 5.6pF

capacitor.

4b. Recalculate the value of R

IN1

after C

IN1

is chosen.

IN1

= (C

IN1(ideal)

IN1(NPO,0402)

= 96.22k

Choose the closest 1% value:

IN1

= 95.3k (1%)

5. Calculate the frequency- and Q-

setting resistors R22, R

, as

done in steps 1 and 2, above.

Choose the closest 1% standard

resistor values.

R22 = 10k (1%);

= 84.5k(1%)

6. Calculate the feedforward

resistor, R

FF2

1/(R

FF2

C) = Gain • A1;

C = 159.15pF

The values for parameter (Gain •

A1) are provided by FilterCAD; they

relate to the coefﬁcients of the nu-

merator of the transfer function (V1B/

in Figure 1); a passband AC gain of

unity is assumed (see Table 2). Please

note that, for a lowpass case, as in

Part 1 of this article series, the value

of (Gain • A1) is the DC gain of the

ﬁlter and its value can be easily set

without software assistance.

Equating the numerator of the ﬁl-

ter transfer function with the values

provided by FilterCAD:

s(s

+ ω

N22

)

FF2

• C) • D(s) GAIN (A1s)(s

+ A2)

D(s)

GAIN = 0.2823

A1 = 62.8122 • 10

A2 = (2πf

)

= 235.9 • 10

(7)

RFF2 = 1/((Gain A1) C) = 354.35k;

C = 159.15pF

RFF2 = 357k(1%)

INV B

V1 B

V2 B

SHDN

V2 A

V1 A

INV A

INV C

V1 C

V2 C

–

AGND

V2 D

V1 D

INV D

LTC1562

FF2

357k

IN2

110k

IN4

95.3k

FF4

332k

IN1,

10.7k

IN1,

5.6pF

OUT

1562 TA03

IN3

, 294k

–5V

, 86.6k

R21,10.7k

R23, 10k

0.1µF

, 84.5k

R24, 9.53k

, 82.5k

, 84.5k

R22, 10k

IN3,

18pF

0.1µF

–20

–40

–60

–80

–100

–12050 60 70 80 90 100 120 130110 140 150

FREQUENCY (kHz)

GAIN (dB)

–65dB

BANDWIDTH

Figure 5. Hardware realization of the ﬁlter in Figure 3, using all four sections of an LTC1562

Figure 6. Measured amplitude response of

Figure 5’s ﬁlter

Linear Technology Magazine • February 1999

DESIGN IDEAS

7. Solve for R

IN2

by using Equation

(3), which dictates the gain

condition for the occurrence of

the notch:

IN2

= (R

FF2

IN1

)/(R1 C) =

108.785k; (R1,C) = (10k, 159.15pF)

IN2

= 110k (1%)

II. Calculate the passive

components of the second 4th

order section

= 100kHz, Q3 = 8.5, f

103.0322kHz, Q4 = 8.5, f

129.2814kHz)

Except for the bandpass gain

calculations, the algorithm will

be the same as the lowpass

design of Part 1 of this article.

1. R23 = (100kHz/f

)

• 10k =

10k (1%)

2. R

= Q3 √R23 • 10k = 85k,

= 84.5k (1%)

3. Calculate the input resistor R

IN3

from the following expression(s):

3a. if f

≤ 100kHz (for L TC1562)

(8)

RIN3 = Q3 • R23 •

(

fO32

fN42

1 –

1 + 2

• Q32

RIN3 = 302.41k

3b. if f

≥ 100kHz (for L TC1562)

(9)

IN3

= R

•

(

O32

N42

1 –

1 +

• Q3

For f

= 100kHz, as in the example

above, either expression can be used.

Note that the expression for R

IN3

3b, above, is the same as expression

for R

IN1

shown in Part 1 of this article.

4a. Use the theoretical value for

IN3

, calculated above, and

calculate the value of the input

capacitor C

IN3

from the notch

equation (2) of part 1 of this

article; for convenience this is

repeated below:

(10)

CIN3 = C •

(

fO32

fN42

1 –

RQ3

RIN3 •

CIN3 = 17.86pF;

Use a commercially available NPO-

type 0402 surface mount capacitor

with the value nearest the ideal value

of C

IN3

calculated above. For instance,

IN3

= 18pF.

4b. Recalculate the value for R

IN3

calculated in step 3a after C

IN3

is chosen.

IN3

= (C

IN3(ideal)

)/C

IN3(NPO,0402)

= 300.058k

RIN3 = 294k (1%)

5. Calculate the frequency- and

Q-setting resistors, R24 and

, as done in steps 1 and 2,

above. Choose the nearest 1%

standard value.

R24 = 9.42k; R24 = 9.53k (1%)

RQ4 = 82.97k; RQ4 = 82.5k (1%)

6. Calculate the feedforward

resistor, RFF4. First equate the

numerator of the 4th order ﬁlter

transfer function with the

values provided by FilterCAD

(see Table 2):

OUT

FF4

•

Cω

O32

O42

N42

D(s)

GAIN • A1s • (s

+ ω

N42

)

D(s)

=••

••

O32

2N4

THEN R

FF4

= 1

GAIN • A1 1

GAIN = 0.1788

A1 = 62.8319 • 10

(11)

RFF4 = 334.64k, choose RFF4 = 332k

(1%).

7. Solve for R

IN4

by using equation

(1) of Part 1 of this article,

which dictates the gain

condition for the occurrence of

a notch. For convenience, this

gain condition is repeated

below.

IN4

= R

FF4

• R

IN3

(12)

RIN4 = 95.422k; RIN4 = 95.3k(1%)

Experimental Results

Figure 6 shows the measured ampli-

tude response of the ﬁlter of Figure 5.

The values of the passive component

are as calculated above and as shown

in Figure 5. The measured amplitude

response closely approximates the

ideal response as synthesized by Fil-

terCAD. The peak frequency with

standard 1% resistor values and 5%

capacitor values is 100.65kHz (0.65%

off). The higher frequency notch,

although it shows a respectable depth

of 70dB, is not as well deﬁned as the

notch below the ﬁlter’s center fre-

quency, yet the –65dB bandwidth is

as predicted by FilterCAD. The 10dB

lack of the upper band notch depth is

due to the ﬁnite speed of the internal

op amps; they cause the practical 180

degree phase shift frequency and the

gain at V1A’s output to depart slightly

from the theoretical calculations.

For the sake of perfection, the notch

depth can be easily restored by tweak-

ing the value of R

; the new R

will

be 75k. This is shown with dashed

lines in Figure 6. This, however, low-

ers the passband gain by the ratio of

the new to the old R

value, that is,

by about –1.0dB (you cannot fool

mother nature). Depending on the

application, the 10dB of additional

notch depth for 1.5dB of passband

gain loss may be a reasonable trade.

The passband gain can also be cor -

rected by lowering the values of either

pair , (R

FF2

, R

IN2

) or (R

FF4

, R

IN4

), by the

same amount (1.5dB). In Figure 6,

the gain was restored to 0dB by chang-

ing the values of R

IN2

, R

FF2

to 93.1k

and 300.1k respectively.

The total integrated noise was an

impressively low 69µV

RMS

, allowing a

signal-to-noise ratio well in excess of

80dB. The input signal-to-noise ratio

can be further increased if the pass-

= ±5V

OUT(RMS)

, f

OUT

= 100kHz

IN(RMS)

, f

OUT

= 100kHz

0.1

50.1 1

Figure 7. Gain linearity of Figure 5’s ﬁlter,

measured at the 100kHz theoretical center

frequency

Linear Technology Magazine • February 1999

Step-Down Conversion, continued from page 30

lower cost LTC1430A replacing the

LTC1649. The LTC1430A does not

include the 3.3V to 5V charge pump

and requires a 5V supply to drive the

external MOSFET gates. The current

drawn from the 5V supply depends

on the gate charge of the external

MOSFETs but is typically below 50mA,

regardless of the load current on the

2.5V output. The drains of the Q1/Q2

pair draw the main load current from

the 3.3V supply. The remaining cir -

cuitry works in the same manner as

in Figure 1. Efﬁciency and perfor-

mance are virtually the same as the

LTC1649 solution, but parts count

and system cost are lower.

In a 3.3V to 2.5V application, the

steady-state, no-load duty cycle is

76%. If the input supply drops to

3.135V (3.3V – 5%), the duty cycle

requirement rises to 80% at no load,

and even higher under heavy or

transient load conditions. Both the

LTC1649 and the LTC1430A guar-

antee a maximum duty cycle of greater

than 90% to provide acceptable load

regulation and transient response.

The standard LTC1430 (not the

LTC1430A) can max out as low as

83%—not high enough for 3.3V to

2.5V circuits. Applications with larger

step-down ratios, such as 3.3V to

2.0V, can use the circuit in Figur e 3

successfully with a standard

LTC1430.

band gain can be higher than 0dB or

if inter nal nodes are allowed to have

gains higher than 0dB. Please con-

tact the LTC Filter Design and

Applications Group for further details.

The low noise behavior of the ﬁlter

makes it useful in applications where

the input signal has a wide voltage

range. This is true provided the ﬁlter

magnitude response does not change

with varying input signal levels, that

is, the ﬁlter gain is linear. The gain

linearity measured at the 100kHz

theoretical center frequency of the

ﬁlter is shown in Figure 7. The gain is

per fectly linear for input amplitudes

up to 1.25V

RMS

(3.5V

P-P

) so an 84dB

dynamic range can be claimed. The

input signal, however , can reach am-

plitudes up to 3V

RMS

(8.4V

P-P

, 92dB

SNR) with some reduction in gain

linearity.

SW, V

BAT

and GND in Figure 2 will

help in spreading the heat and will

reduce the power dissipation in con-

ductors and MOSFETs.

Other Applications

The LT1505 can also be used in other

system topologies, such as the tele-

com application shown in Figure 5.

The circuit in Figure 5 uses the bat-

tery to supply peak power demands.

By doing so, the required peak power

from the wall adapter can be much

lower than the peak power required

by the load. The wall adapter has to

supply the average power only.

Conclusion

The LT1505 is a complete, single-

chip battery charger solution for

today’s demanding charging require-

ments in high performance laptop

applications. The device requires a

small number of external components

and provides all necessary functions

for battery charging and power man-

agement. High efﬁciency and small

size allow for easy integration with

the laptop circuits. Also, by adding a

simple external circuit, charging can

be easily controlled by the host com-

puter, allowing for more sophisticated

charging schemes.

LTC1735/LTC1736, continued from page 6

level is 44µV

RMS

over a bandwidth of

800kHz or 98dB below the maximum

unclipped output.

Acknowledgments

Philip Karantzalis and Nello Sev-

astopoulos of LTC’s Monolithic Filter

Design and Applications Group con-

tributed to the application examples.

References

1. Hauser, Max. “Universal Continu-

ous-Time Filter Challenges Discrete

Designs.” Linear Technology VIII:1

(February 1998), pp. 1–5 and 32.

2. Sevastopoulos, Nello. “How to De-

sign High Order Filters with Stopband

Notches Using the LTC1562 Quad

Operational Filter, Part 1.” Linear

Technology VIII:2 (May 1998), pp.

28-31.

3. Sevastopoulos, Nello. “How to De-

sign High Order Filters with Stopband

Notches Using the LTC1562 Quad

Operational Filter, Part 2.” in the De-

sign Ideas section of this issue of

Linear Technology.

4. L TC1562 Final Data Sheet.

5. For example: Schwartz, Mischa.

Information Transmission, Modula-

tion, and Noise, fourth edition, pp.

180–192. McGraw-Hill 1990.

LTC1562-2, continued from page 10

Conclusion

The LTC1735 and LTC1736 are the

latest members of Linear Technology’s

family of constant frequency, N-chan-

nel high efﬁciency controllers. With

new protection features, improved cir-

cuit operation and strong MOSFET

drivers, the L TC1735 is an ideal up-

grade to the LTC1435/LTC1435A for

higher current applications. With the

integrated VID control, the L TC1736

is ideal for CPU power applications.

The high performance of these con-

trollers with wide input range, 1%

reference and tight load regulation

makes them ideal for next generation

designs.

LT1505, continued from page 25

CONTINUATIONS

Linear Technology Magazine • February 1999

DESIGN INFORMATION

The LTC1658 and LT C1655: Smallest

Rail-to-Rail 14-Bit and 16-Bit DACs

by Hassan Malik

Expanding the rail-to-rail, voltage

output

DAC family, Linear Technol-

ogy introduces two new voltage output

DACs that break the size/bits bar-

rier. The LTC1658 is a 14-bit

rail-to-rail voltage output

DAC in a

tiny MSOP-8 package and the

LTC1655 is a 16-bit voltage output

DAC in an SO-8 package. Both of

these DACs also provide a convenient

upgrade path for users of LTC’s 12-

bit voltage output

DAC family. The

LTC1658 draws only 270µA from a

3V or 5V supply and is 14-bit mono-

tonic over temperature. The LTC1655

draws 600µA from a 5V supply and is

16-bit monotonic over temperature.

These DACs have a ﬂexible 3-wire

serial inter face that is SPI/QSPI and

MICROWIRE compatible.

Figures 1 demonstrates the ease of

using the LTC1658. The output swings

from 0V to V

REF

at full-scale. V

REF

should be less than or equal to V

prevent the loss of codes and degrada-

tion of PSRR near full-scale. The input

serial data is loaded as one 16-bit

word with two dummy bits. The digital

inputs are TTL/CMOS level compat-

ible and the CLK input has an internal

Schmitt trigger for noise immunity.

This allows direct optocoupler inter-

facing to the part. Figure 2 plots the

part’s 0.25LSB typical DNL.

A typical application for the

LTC1655 is shown in Figure 3. The

LTC1655 has the same interface as

the LTC1658 and is also capable of

being daisy chained. There is an

onboard 2.048V bandgap reference

connected internally to the 16-bit

DAC. The rail-to-rail output nomi-

nally swings from 0V to 4.096V, since

there is a gain of two in the output

ampliﬁer. The reference pin can be

overdriven to a value higher than

2.048V if a larger output swing is

desired. Since there is a gain of 2 from

the reference pin to the output at full-

scale, the voltage on the REF pin

must always be less than V

/2.

Figure 4 plots the typical DNL of the

LTC1655.

Figure 1. LTC1658 block diagram Figure 2. The LTC1658 14-bit rail-to-rail

DAC in MSOP has 0.25LSB typical DNL.

Figure 3. LTC1655 block diagram Figure 4. LTC1655 typical DNL plot

CODE

–1.0

–0.2

–0.4

–0.6

–0.8

0.2

0.4

0.6

0.8

1.0

DNL ERROR (LSB)

16384 32768

1658 TA02

49152 65535

–

14-BIT

DAC

2.7V TO 5.5V

GND

POWER-ON

RESET

OTHER

DACS

16-BIT

SHIFT

REG

AND

DAC

LATCH

µP

REF

OUT

1658 TA01

CLK1

CS/LD3

7RAIL-TO-RAIL

VOLTAGE

OUTPUT

OUT

CODE

–1.0

–0.2

–0.4

–0.6

–0.8

0.2

0.4

0.6

0.8

1.0

DNL ERROR (LSB)

4096 8192

1658 TA02

12288 16383

–

16-BIT

DAC

4.5V TO 5.5V

GND

POWER-ON

RESET

OTHER

DACS

16-BIT

SHIFT

REG

AND

DAC

LATCH

µP

OUT

1658 TA01

CLK1

CS/LD3

7RAIL-TO-RAIL

VOLTAGE

OUTPUT

OUT

2.048V

REF REF

Linear Technology Magazine • February 1999

NEW DEVICE CAMEOS

LTC1502-3.3

Single Cell to 3.3V

Inductorless DC/DC Converter

The LTC1502-3.3 is LTC’s latest

offering in the regulated charge pump

arena. This new charge pump is the

only inductorless single-cell boost

converter in the industry. The part

employs a quadrupler switched

capacitor architecture to generate a

regulated 3.3V supply from a single

NiCd or alkaline cell. Start-up

enhancement circuitry enables the

LTC1502-3.3 to power up with V

low as 0.8V. Only ﬁve small ceramic

capacitors are required to make a

complete 3.3V single-cell power sup-

ply with 10mA of output load

capability.

The part also has a shutdown fea-

ture that disconnects the load from

and reduces quiescent current to

only 5µA. The LTC1502-3.3 is short-

circuit protected and can survive an

indeﬁnite V

OUT

short to GND. Small

size (8-pin MSOP package) and low

quiescent current (40µA typical) make

the LTC1502-3.3 ideal for space con-

scious, low power applications such

as pagers and PDAs. Since the V

OUT

pin is high impedance during shut-

down, the part is also well suited for

single-cell battery backup applica-

tions.

LTC1661 Micropower Dual

10-Bit DAC with Sleep Mode

Available in MS-8

The LTC1661 is a micr opower, dual,

10-bit voltage-output DAC that is

available in a tiny 8-pin MSOP pack-

age. Required board area is only

0.01in

per DAC.

Operating on a single 2.7–5.5V

supply, the LTC1661 draws just 60µA

per DAC (120µA total for the part) for

true micropower per for mance. Sleep

mode further reduces total supply-

plus-reference current to just 1µA.

The LTC1661 is guaranteed mono-

tonic over temperature—differential

nonlinearity error is typically ±0.2LSB

(±0.75LSB Max). Each DAC has a

gain of 1 from reference to output; the

Reference pin can be tied to V

for

full rail-to-rail operation. The output

ampliﬁers are stable driving capaci-

tive loads of up to 1000pF and can

source or sink up to 5mA. The out-

puts swing to within a few millivolts of

either supply rail when unloaded and

have an equivalent output resistance

of 85Ω when driving a load to the

rails.

The 3-wire serial interface uses a

16-bit input word comprising 4 con-

trol bits, 10 input-code bits, and 2

don’t-care bits. Power-on reset is also

provided. The input logic is double

buffered for additional ﬂexibility in

interfacing with the microprocessor

and for more effective control of mul-

tiple chips that share clock and data

lines.

Low supply current, power-saving

Sleep mode and extremely compact

size make the LTC1661 ideal for bat-

tery-powered applications, while its

straightforward usability, high per-

formance and wide supply range make

it an excellent choice as a general-

purpose converter.

LTC1841/LTC1842/LTC1843

Dual Micropower Comparator

with Built-In Reference

The LTC1841/LTC1842/LTC1843

are dual micropower comparators

with built-in references (LTC1842/

LTC1843). These parts feature less

than 5.7µA supply current over tem-

perature, a 1.182V ±1% reference

(L TC1842/L TC1843), pr ogrammable

hysteresis (LTC1842/LTC1843) and

open-drain output comparators that

can sink greater than 20mA. The ref-

erence output can drive a bypass

capacitor of up to 0.01µF without

oscillation.

The comparators operate from

single 2V to 11V supplies or ±1V to

±5.5V supplies (LTC1841). Compara-

tor hysteresis is easily programmed

using two resistors and the HYST pin.

The comparator’s input operates from

the negative supply to within 1.3V of

the positive supply. The comparator

output stage can typically sink greater

than 20mA. By eliminating the cross-

conduction current that normally

occurs when the comparator changes

logic states, power supply glitches

are eliminated.

The LTC1841/LTC1842/LTC1843

are available in 8-pin SO packages.

LTC1605-1/-2: 100ksps

16-Bit ADC Now Available

with 0V to 4V and ±4V

Analog Input Ranges

The LTC1605-1 and LTC1605-2 are

the newest members of Linear

Technology’s family of 16-bit ADCs.

The two new ADCs offer the user a

choice of analog input ranges to help

make full use of the wide dynamic

range offered by these converters.

These 100ksps sampling ADCs fea-

ture 16-bit resolution with no missing

codes and ±2LSB INL. They operate

from a single 5V supply with typical

power dissipation of only 55mW. They

are offered in both 28-pin PDIP and

SSOP packages.

The LTC1605-1 has an analog input

range of 0V to 4V with ±20V overvolt-

age protection. This 16-bit ADC is

ideally suited for single-supply sys-

tems. It is a complete data acquisition

system containing a differential, suc-

cessive-approximation A/D that uses

switched capacitor technology to per-

form a 16-bit conversion. The analog

front end consists of a resistor divider

network followed by a sample-and-

hold that allows fast moving signals

to be digitized. The LTC1605-1 also

has a trimmed bandgap reference that

can be overdriven with an external

reference if greater accuracy is needed.

It also features a simple parallel I/O

where the digital output word can be

read as a 16-bit word or as two 8-bit

bytes. The digital output word format

for the LTC1605-1 is straight binary.

The LTC1605-2 has a bipolar ana-

log input range of ±4V with ±20V

overvoltage protection (±15V overdrive

recoverable) operating on a single 5V

supply. It is also a complete data

acquisition system with the same fea-

tures and parallel I/O as the

New Device Cameos

Linear Technology Magazine • February 1999

NEW DEVICE CAMEOS

LTC1605-1. The LTC1605-2 digital

output word format is two’s

complement.

LTC1754-5 Regulated Charge

Pump Delivers 50mA in an

SOT-23 Package

The LTC1754-5 is the newest addi-

tion to Linear Technology’s industry

leading family of switched capacitor

regulated charge pumps. Combining

the best features of its predecessors,

it delivers a full 50mA from a tiny

SOT-23 package while stepping up

from 3V to a regulated 5V . The 6-pin

package provides additional fun-

ctionality by including shutdown

capability. Finally, it has built-in ther-

mal shutdown circuitry that allows it

to survive a continuous short circuit

to ground at its output.

The quiescent supply current of

the LTC1754-5 is only 13µA. This low

supply current means very low power

consumption in light load

applications. Furthermore, because

it uses Burst Mode operation, its

efﬁciency is typically 82.7% when

delivering moderate to high load cur-

rent. This efficiency is very close to

the ideal 83.3% for a 3V to 5V regulat-

ing charge pump. In shutdown, the

supply current is guaranteed to be

less than 1µA.

With no inductors and only three

small capacitors, the LTC1754-5 regu-

lated charge pump delivers signiﬁcant

power from a small amount of real

estate.

LTC1569-7: Unique 10th

Order, Linear-Phase, DC

Accurate Lowpass Filter is

Tunable by a Single Resistor

The LTC1569-7 is a self-contained

10th order linear-phase ﬁlter featur-

ing cutoff frequencies up to 256kHz

while operating on supplies from 3.3V

(3V minimum) up to ±5V. Cutof f fre-

quencies up to 128kHz can also be

obtained with a 3V (2.7V minimum)

supply. Unlike other monolithic ﬁl-

ters, the LTC1569-7’s precision

on-chip oscillator allows the cutoff

frequency to be set accurately (within

2%) by a single resistor. Alternatively,

for swept cutoff frequency applica-

tions, an external clock can be used.

The amplitude response of the

LTC1569-7 approximates a root raised

cosine, with an alpha of 0.5, for phase

linearity with excellent attenuation.

The attenuation of the LTC1569-7 at

1.5 times the cutoff frequency is 55dB,

whereas attenuation is in excess of

60dB at 2.1 times the cutoff frequency.

The DC offset of the LTC1569-7 is

typically 2mV. Its DC gain linearity

and SINAD are suitable for 12-bit

systems. The input of the ﬁlter can be

conﬁgured as single ended or

differential.

When operated at full bandwidth,

the LTC1569-7 consumes 20mA on a

single 5V supply but, when slower

sampling rates are required (that is,

at lower cutoff frequencies), the device

automatically switches to a reduced

supply current, which can be as low

as 5mA. The LTC1569-7 is available

in an 8-pin SO package.

For further information on any

of the devices mentioned in this

issue of Linear Technology, use

the reader service card or call

the LTC literature service

number:

1-800-4-LINEAR

Ask for the pertinent data sheets

and Application Notes.

Authors can be contacted

at (408) 432-1900

for

the latest information

on LTC products,

visit

www.linear-tech.com

Linear Technology Magazine • February 1999

DESIGN TOOLS

Applications on Disk

FilterCAD™

2.0 CD-ROM — This CD is a powerful ﬁlter

design tool that supports all of Linear Technology’s high

performance switched capacitor ﬁlters. Included is Fil-

terView™, a document navigator that allows you to

quickly ﬁnd Linear Technology monolithic ﬁlter data

sheets, the FilterCAD manual, application notes, design

notes and

Linear Technology

magazine articles. It

does

not

have to be installed to run FilterCAD. It is not

necessary to use FilterView to view the documents, as

they are standard .PDF ﬁles, readable with any version

of Adobe Acrobat™. FilterCAD runs on Windows

3.1 or

Windows 95. FilterView requires Windows 95. The

FilterCAD program itself is also available on the web and

will be included on the new LinearView™ CD.

Available at no charge.

Noise Disk — This IBM-PC (or compatible) program

allows the user to calculate circuit noise using LTC op

amps, determine the best LTC op amp for a low noise

application, display the noise data for LTC op amps,

calculate resistor noise and calculate noise using specs

for any op amp. Available at no charge

SPICE Macromodel Disk — This IBM-PC (or compat-

ible) high density diskette contains the library of LTC op

amp SPICE macromodels. The models can be used with

any version of SPICE for general analog circuit simula-

tions. The diskette also contains working circuit examples

using the models and a demonstration copy of PSPICE™

by MicroSim. Available at no charge

SwitcherCAD™ — The SwitcherCAD program is a pow-

erful PC software tool that aids in the design and

optimization of switching regulators. The program can

cut days off the design cycle by selecting topologies,

calculating operating points and specifying component

values and manufacturer’s part numbers. 144 page

manual included. $20.00

SwitcherCAD supports the following parts: LT1070 se-

ries: LT1070, LT1071, LT1072, LT1074 and LT1076.

LT1082. LT1170 series: LT1170, LT1171, LT1172 and

LT1176. It also supports: LT1268, LT1269 and LT1507.

LT1270 series: LT1270 and LT1271. LT1371 series:

LT1371, LT1372, LT1373, LT1375, LT1376 and LT1377.

Micropower SwitcherCAD™ — The MicropowerSCAD

program is a powerful tool for designing DC/DC convert-

ers based on Linear Technology’s micropower switching

regulator ICs. Given basic design parameters,

MicropowerSCAD selects a circuit topology and offers

you a selection of appropriate Linear Technology switch-

ing regulator ICs. MicropowerSCAD also performs circuit

simulations to select the other components which sur-

round the DC/DC converter. In the case of a battery

supply, MicropowerSCAD can perform a battery life

simulation. 44 page manual included. $20.00

MicropowerSCAD supports the following LTC micro-

power DC/DC converters: LT1073, LT1107, LT1108,

LT1109, LT1109A, LT1110, LT1111, LT1173, LTC1174,

LT1300, LT1301 and LT1303.

Technical Books

1990 Linear Databook, Vol I —This 1440 page collec-

tion of data sheets covers op amps, voltage regulators,

references, comparators, ﬁlters, PWMs, data conver-

sion and interface products (bipolar and CMOS), in both

commercial and military grades. The catalog features

well over 300 devices. $10.00

1992 Linear Databook, Vol II — This 1248 page supple-

ment to the 1990 Linear Databook is a collection of all

products introduced in 1991 and 1992. The catalog

contains full data sheets for over 140 devices. The 1992

Linear Databook, Vol II is a companion to the 1990

Linear Databook, which should not be discarded.

$10.00

1994 Linear Databook, Vol III —This 1826 page supple-

ment to the 1990 and 1992 Linear Databooks is a

collection of all products introduced since 1992. A total

of 152 product data sheets are included with updated

selection guides. The 1994 Linear Databook Vol III is a

companion to the 1990 and 1992 Linear Databooks,

which should not be discarded. $10.00

1995 Linear Databook, Vol IV —This 1152 page supple-

ment to the 1990, 1992 and 1994 Linear Databooks is a

collection of all products introduced since 1994. A total

of 80 product data sheets are included with updated

selection guides. The 1995 Linear Databook Vol IV is a

companion to the 1990, 1992 and 1994 Linear Databooks,

which should not be discarded. $10.00

1996 Linear Databook, Vol V —This 1152 page supple-

ment to the 1990, 1992, 1994 and 1995 Linear Databooks

is a collection of all products introduced since 1995. A

total of 65 product data sheets are included with updated

selection guides. The 1996 Linear Databook Vol V is a

companion to the 1990, 1992, 1994 and 1995 Linear

Databooks, which should not be discarded. $10.00

1997 Linear Databook, Vol VI —This 1360 page supple-

ment to the 1990, 1992, 1994, 1995 and 1996 Linear

Databooks is a collection of all products introduced

since 1996. A total of 79 product data sheets are in-

cluded with updated selection guides. The 1997 Linear

Databook Vol VI is a companion to the 1990, 1992, 1994,

1995 and 1996 Linear Databooks, which should not be

discarded. $10.00

1990 Linear Applications Handbook, Volume I —

928 pages full of application ideas covered in depth by

40 Application Notes and 33 Design Notes. This catalog

covers a broad range of “real world” linear circuitry. In

addition to detailed, systems-oriented circuits, this hand-

book contains broad tutorial content together with liberal

use of schematics and scope photography. A special

feature in this edition includes a 22-page section on

SPICE macromodels. $20.00

1993 Linear Applications Handbook, Volume II —

Continues the stream of “real world” linear circuitry

initiated by the 1990 Handbook. Similar in scope to the

1990 edition, the new book covers Application Notes 40

through 54 and Design Notes 33 through 69. References

and articles from non-LTC publications that we have

found useful are also included. $20.00

1997 Linear Applications Handbook, Volume III —

This 976 page handbook maintains the practical outlook

and tutorial nature of previous efforts, while broadening

topic selection. This new book includes Application

Notes 55 through 69 and Design Notes 70 through 144.

Subjects include switching regulators, measurement

and control circuits, ﬁlters, video designs, interface,

data converters, power products, battery chargers and

CCFL inverters. An extensive subject index references

circuits in LTC data sheets, design notes, application

notes and

Linear Technology

magazines. $20.00

1998 Data Converter Handbook — This impressive

1360 page handbook includes all of the data sheets,

application notes and design notes for Linear

Technology’s family of high performance data converter

products. Products include A/D converters (ADCs), D/A

converters (DACs) and multiplexers—including the fast-

est monolithic 16-bit ADC, the 3Msps, 12-bit ADC with

the best dynamic performance and the ﬁrst dual 12-bit

DAC in an SO-8 package. Also included are selection

guides for references, op amps and ﬁlters and a glossary

of data converter terms. $10.00

Interface Product Handbook — This 424 page hand-

book features LTC’s complete line of line driver and

receiver products for RS232, RS485, RS423, RS422,

V.35 and AppleTalk

applications. Linear’s particular

expertise in this area involves low power consumption,

high numbers of drivers and receivers in one package,

mixed RS232 and RS485 devices, 10kV ESD protection

of RS232 devices and surface mount packages.

Available at no charge

Power Solutions Brochure — This collection of cir-

cuits contains real-life solutions for common power

supply design problems. There are over 70 circuits,

including descriptions, graphs and performance

speciﬁcations. Topics covered include battery chargers,

power supplies for desktop and portable computers,

supplies for portable electronics, telecommunications

supplies, offline supplies and various other power man-

agement techniques, including Hot Swap™ circuits.

Available at no charge

Data Conversion Solutions Brochure — This 64 page

collection of data conversion circuits, products and

selection guides serves as excellent reference for the

data acquisition system designer. Over 60 products are

showcased, solving problems in low power, small size

and high performance data conversion applications—

with performance graphs and speciﬁcations. Topics

covered include ADCs, DACs, voltage references and

analog multiplexers. A complete glossary deﬁnes data

conversion speciﬁcations; a list of selected application

and design notes is also included.

Available at no charge

Telecommunications Solutions Brochure — This col-

lection of circuits, new products and selection guides

covers a wide variety of products targeted for the

telecommunications industry. Circuits solving real life

problems are shown for central ofﬁce switching, cellular

phone, base station and other telecom applications.

New products introduced include high speed ampliﬁers,

A/D converters, power products, interface transceivers

and ﬁlters. Reference material includes a telecommuni-

cations glossary, serial interface standards, protocol

information and a complete list of key application notes

and design notes. Available at no charge

DESIGN TOOLS

Information furnished by Linear Technology Corporation

is believed to be accurate and reliable. However, Linear

Technology makes no representation that the circuits

described herein will not infringe on existing patent rights.

continued on page 40

Linear Technology Magazine • February 1999

LINEAR TECHNOLOGY CORPORATION

1630 McCarthy Boulevard

Milpitas, CA 95035-7417

(408) 432-1900 FAX (408) 434-0507

www.linear-tech.com

For Literature Only: 1-800-4-LINEAR

Acrobat is a trademark of Adobe Systems, Inc.; Windows

is a registered trademark of Microsoft Corp.; Macintosh

and AppleTalk are registered trademarks of Apple Com-

puter, Inc. PSPICE is a trademark of MicroSim Corp.

CD-ROM Catalog

LinearView — LinearView™ CD-ROM version 3.0 is

Linear Technology’s latest interactive CD-ROM. It al-

lows you to instantly access thousands of pages of

product and applications information, covering Linear

Technology’s complete line of high performance analog

products, with easy-to-use search tools.

The LinearView CD-ROM includes the complete product

speciﬁcations from Linear Technology’s Databook li-

brary (Volumes I–VI) and the complete Applications

Handbook collection (Volumes I–III). Our extensive

collection of Design Notes and the complete collection

Linear Technology

magazine are also included.

A powerful search engine built into the LinearView CD-

ROM enables you to select parts by various criteria,

such as device parameters, keywords or part numbers.

All product categories are represented: data conversion,

references, ampliﬁers, power products, ﬁlters and inter-

face circuits. Up-to-date versions of Linear Technology’s

DESIGN TOOLS, continued from page 39

software design tools, SwitcherCAD, Micropower Switch-

erCAD, FilterCAD, Noise Disk and Spice Macromodel

library, are also included. Everything you need to know

about Linear Technology’s products and applications is

readily accessible via LinearView. LinearView runs un-

der Windows 95 and Macintosh

System 8.0 or later.

Available at no charge.

World Wide Web Site

Linear Technology Corporation’s customers can now

quickly and conveniently ﬁnd and retrieve the latest

technical information covering the Company’s products

on LTC’s internet web site. Located at www.linear-

tech.com, this site allows anyone with internet access

and a web browser to search through all of LTC’s

technical publications, including data sheets, applica-

tion notes, design notes,

Linear Technology

magazine

issues and other LTC publications, to ﬁnd information

on LTC parts and applications circuits. Other areas

within the site include help, news and information about

Linear Technology and its sales ofﬁces.

Other web sites usually require the visitor to download

large document ﬁles to see if they contain the desired

information. This is cumbersome and inconvenient. To

save you time and ensure that you receive the correct

information the ﬁrst time, the ﬁrst page of each data

sheet, application note and

Linear Technology

maga-

zine is recreated in a fast, download-friendly format.

This allows you to determine whether the document is

what you need, before downloading the entire ﬁle.

The site is searchable by criteria such as part numbers,

functions, topics and applications. The search is per-

formed on a user-deﬁned combination of data sheets,

application notes, design notes and

Linear Technology

magazine articles. Any data sheet, application note,

design note or magazine article can be downloaded or

faxed back. (ﬁles are downloaded in Adobe Acrobat PDF

format; you will need a copy of Acrobat Reader to view

or print them. The site includes a link from which you

can download this program.)

International

Sales Ofﬁces

FRANCE

Linear Technology S.A.R.L.

Immeuble “Le Quartz”

58 Chemin de la Justice

92290 Chatenay Malabry

France

Phone: 33-1-41079555

FAX: 33-1-46314613

GERMANY

Linear Technology GmbH

Oskar-Messter-Str. 24

D-85737 Ismaning

Germany

Phone: 49-89-962455-0

FAX: 49-89-963147

JAPAN

Linear Technology KK

5F NAO Bldg.

1-14 Shin-Ogawa-cho Shinjuku-ku

Tokyo, 162

Japan

Phone: 81-3-3267-7891

FAX: 81-3-3267-8510

KOREA

Linear Technology Korea Co., Ltd

Namsong Building, #403

Itaewon-Dong 260-199

Yongsan-Ku, Seoul 140-200

Korea

Phone: 82-2-792-1617

FAX: 82-2-792-1619

SINGAPORE

Linear Technology Pte. Ltd.

507 Yishun Industrial Park A

Singapore 768734

Phone: 65-753-2692

FAX: 65-752-0108

SWEDEN

Linear Technology AB

Sollentunavägen 63

S-191 40 Sollentuna

Sweden

Phone: (08)-623-1600

FAX: (08)-623-1650

TAIWAN

Linear Technology Corporation

Rm. 602, No. 46, Sec. 2

Chung Shan N. Rd.

Taipei, Taiwan, R.O.C.

Phone: 886-2-521-7575

FAX: 886-2-562-2285

UNITED KINGDOM

Linear Technology (UK) Ltd.

The Coliseum, Riverside Way

Camberley, Surrey GU15 3YL

United Kingdom

Phone: 44-1276-677676

FAX: 44-1276-64851

World Headquarters

Linear Technology Corporation

1630 McCarthy Boulevard

Milpitas, CA 95035-7417

Phone: (408) 432-1900

FAX: (408) 434-0507

U.S. Area

Sales Ofﬁces

NORTHEAST REGION

Linear Technology Corporation

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Phone: (215) 638-9667

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Phone: (978) 658-3881

FAX: (978) 658-2701

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Phone: (512) 343-3679

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Houston, TX 77043

Phone: (713) 463-5001

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Phone: (949) 453-4650

FAX: (949) 453-4765

41K