ALTERA CORP 24E cf ~ See ee ees) High density logic replacement for TTL and Funetional and pin compatible with the Altera EP600. High speed, tpd = 45 ns, @ Asynchronous clocking of all registers or banked register operation from 2 synchronous clocks. @ 16 Macrocells with configurable I/O architecture allowlng 20 Inputs and 16 outputs. @ "Zero Power" (typically 20uA standby). @ Programmable registers providing D,T,SR or JK flipflops with individual Asynchronous Clear control, 100% generically testable-provides 100% pro- gramming yield. @ Programmable Security Bit" allows total pro- tection of proprietary designs. Package options Include both a 24 pin, 300 mil DIP and a 28 pin J-leaded chip carrier. @ Full software support featuring Schematic Capture, Netlist, Boolean Equation and State Machine design entry methods. CONNECTION DIAGRAM D @@ 0595372 0001113 5 @ go -13-47 rn ios GENERAL DESCRIPTION The Altera EP600 Is a pin-compatible version of the popular EP610 Erasable Programmable Logic Device (EPLD), Available in 24-pin DIP and 28-pin J-leaded chip carrier packages, the EP600 contains 16 Macrocells with user-configurable I/O architec- ture, allowing up to 20 inputs and 16 outputs. Each of the 16 Macrocells contains a program- mable AND and fixed OR PLA structure, see Figure 1, with a maximum eight product terms for logic implementation. In addition, single product terms control Output Enable/Asynchronous Clock and Asynchronous Clear functions. The Altera proprietary programmable |/O archi- tecture allows the EP600 user to program output and feedback paths for both combinatorial or registered operation, active high or active low. For increased flexibility, the EP600 also includes programmable registers. Each of the 16 internal registers may be programmed to be D, T, SR or JK flipflop. In addition, each register may be clocked asynchronously on an individual basis or syn- chronously on a banked register basis. For proper operation, standard high performance design practices should be followed. It is recom- mended that opaque labels be placed over device window. Input and output pins must be constrained to the range GND < (Vy or Vout) S Voc. Unused inputs must always be tied to an appropriate logic level (e.g. either Vog or GND). Each set of Voc and GND pins must be shorted together directly at the device. Power supply decoupling capacitors of at least 1F must be connected between each Voc pin and GND. For the most effective decoupling, connect one capacitor between each set of Voc and GND pins, directly at the device. Programming the EP600 is accomplished by using the Altera AtPLUS PC-based development software which supports schematic capture, net- list, state machine and Boolean equation design entry methods. Once the design is entered, A+PLUS automatically performs translation Into logical equations, Boolean minimization, and de- sign fitting directly to an EP600. The device may then be programmed to achieve customized work- ing silicon within minutes at the designer's own desktop. For full EP600 functional description please consult the EP610 datasheet. REV 5.0et ~ ALTERA CORP P4E D Mgm@ 0595372 0001114 7 Figure 1 Logic Array Macrocell j2 14 16 18 20 24 OE/CLK , PRODUCT TERMS ~~ Oe Onr na Oo 2 2 3 a 23 4 6 6 7 8 8 10 11 14 15 16 17 18 19 20 21 22 2 Note: i: I/O pin, in which Logic Array input is from feedback path. T= Yb-13-41 SYNCHRONOUS OE/CLK CLOCK SELECT Veo EP600 1/0 ARCHITECTURE CONTROL FEED- 3 BACK Figure 2. log v8 Frequency Figu WOrtA lec ACTIVE (mA) Typ. i NON-TUARBO MODE {lo] Output Current (mA) Typ. J J j i ff 0H {KHz WKHr =f00KHz = Iz 10H SOM: MAXIMUM FREQUENCY re 3, Output Drive Currents 60 50 40 30 20 = a a AA NHOO vec = 5.0V TA = 26C Ld 1 L i 1 j 0 1 2 3 4 Vo Output Voltage (V)i ALTERA CORP 24E D MM 0595372 0001115 7 eB. at - a ete COMMERCIAL, INDUSTRIAL, MILITARY Note: See Design Recommendations OPERATING RANGE 7-46-13 - 47 wn respect GND not DC to note (3) DC Veo or current RECOMMENDED OPERATING CONDITIONS PARAMETER hote For For Case time note note eRe) ALEC Ren irae batter: (Veo = BV 5%, Ta = 0C to 70C for Commercial) (Voc = SV + 10%, Ta = -40C to 85C for Industrial) (Veg = BV 10%, To = -55C to 125C for Military)* Note (4) and (6) TTL current off-state current Veo supply current (standby) Vv, = No load, f = 1.0 MHz note = Voc or Veo supply current (turbo) No f= 10 MHz note Veo supply current (non-turbo) MAX + 150 10 (15) 50 (60) Note (4) ; SYMBOL PARAMETER CONDITIONS MIN . MAX UNIT Cn Input Capacitance Ho Wiz 20 pF Cour Output Capacitance jo 20 pF Coxk Clock Pin Capacitance f v " 0 te 20 pF 48 ATERAALTERA CORP CYE D M@ 0595372 OOOLLIL O : EPO0, EP600-3 (Voc = SV + 5%, Ta = 0C to 70C for Commercial) T-6-/3- (Veo = SV + 10%, Ta = 40C to 85C for Industrial) / zorh 7 (Vee S 5V & 10%, Te 5 65C to 125C for Military)* EP600-3 EPGOO ADDER SYMBOL PARAMETER CONDITIONS MIK MAX MIN _ MAX note (5) UNIT tony Anput to non-registered output 4a 53 25 ns tone 1/0 input to non-registered output C; = 50pF 45 55 5 ns tezx Input or {/0 input to output enable 45 5 25 ns texz | Input or 1/0 Input to output disable oe 45 55 25 ns tea Asynchronous output clear time C; = 50pF 45 55 25 ns | to 1/0 input buffer delay 2 2 0 ns BR Tieieiticnemeren ae) 2 EP600-3 26.3 0 17.5 to four output feedback fo register + Internat maxknum four note (7) 22.2 ASYNCHRONOUS CLOCK MODE EP600-3 to tacar | output feedback to register Internal facar note (7) : 18.2 1. Typical values are for Ts = 25C, Veo = SV 2, Sample tested only for an output change of 500mV. GRADE AVAILABILITY 3. Minimum DC input is -0.3V, During transitions, the inputs may Commercial . EPS00-3 EP600 4 iniderstont to -2.0V for periods less than atns. Wy. Clock o (0C to 70C) . Capacitance measured at 25C. Sample tested only. Clock pin Industrial capacitance for dedicated clock inputs only. Pin 13, (high (-40C to 85C) EPGOO-3 EPGOO voltage pin during programming), has capacitance of 50 pF max. Military 5. See TURBO-BIT, page 44. (-B5C to 125C) EP600 6. Figures in ( ) pertain to military and industrlal temperature "Tho specitations noted uhove applyto mary operating range devices MIL-$T083 7. Measured with device programmed as a 16 bit counter, compllant product specifications are provide nm Hitary product drawings available 8. EPLD automatically goes into standby mode if logic transitions srawlage shouldbe vied for paparaie aaereecanel envy do not occur when In non-turbo mode (approximately 100 ns after fast transition). 9, Clock tp, te = 250ns (100ns). 10, The fyay values shown represent the highest frequency for pipelined data. (NU fe RYAN EP600 49