+
-
191:
9.95k
10k,
0.1%
10k, 0.1%
10k,
0.1%
50:
A2
A1
+
-
VOUT = 100VD
VCM - 1/2VD
10:
Gain
Trim
VCM + 1/2VD
CMRR
Trim
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LMC6462 Dual/LMC6464 Quad Micropower, Rail-to-Rail Input and Output CMOS
Operational Amplifier
Check for Samples: LMC6462,LMC6464
1FEATURES DESCRIPTION
The LMC6462/4 is a micropower version of the
2• (Typical Unless Otherwise Noted) popular LMC6482/4, combining Rail-to-Rail Input and
• Ultra Low Supply Current 20 μA/Amplifier Output Range with very low power consumption.
• Ensured Characteristics at 3V and 5V The LMC6462/4 provides an input common-mode
• Rail-to-Rail Input Common-Mode Voltage voltage range that exceeds both rails. The rail-to-rail
Range output swing of the amplifier, ensured for loads down
to 25 kΩ, assures maximum dynamic signal range.
• Rail-to-Rail Output Swing This rail-to-rail performance of the amplifier,
– (within 10 mV of rail, VS= 5V and RL= 25 combined with its high voltage gain makes it unique
kΩ)among rail-to-rail amplifiers. The LMC6462/4 is an
• Low Input Current 150 fA excellent upgrade for circuits using limited common-
mode range amplifiers.
• Low Input Offset Voltage 0.25 mV The LMC6462/4, with ensured specifications at 3V
APPLICATIONS and 5V, is especially well-suited for low voltage
applications. A quiescent power consumption of 60
• Battery Operated Circuits μW per amplifier (at VS= 3V) can extend the useful
• Transducer Interface Circuits life of battery operated systems. The amplifier's 150
• Portable Communication Devices fA input current, low offset voltage of 0.25 mV, and
85 dB CMRR maintain accuracy in battery-powered
• Medical Applications systems.
• Battery Monitoring
Figure 1. 8-Pin PDIP/SOIC – Top View Figure 2. 14-Pin PDIP/SOIC – Top View
(See Package Number P or D) (See Package Number NFF0014A or D)
Figure 3. Low-Power Two-Op-Amp Instrumentation Amplifier
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
ESD Tolerance(4) 2.0 kV
Differential Input Voltage ±Supply Voltage
Voltage at Input/Output Pin (V+) + 0.3V, (V−)−0.3V
Supply Voltage (V+−V−) 16V
Current at Input Pin(5) ±5 mA
Current at Output Pin(6)(7) ±30 mA
Current at Power Supply Pin 40 mA
Lead Temp. (Soldering, 10 sec.) 260°C
Storage Temperature Range −65°C to +150°C
Junction Temperature(8) 150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) For specified Military Temperature Range parameters see RETSMC6462/4X.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) Human body model, 1.5 kΩin series with 100 pF. All pins rated per method 3015.6 of MIL-STD-883. This is a class 2 device rating.
(5) Limiting input pin current is only necessary for input voltages that exceed absolute maximum input voltage ratings.
(6) Applies to both single supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
(7) Do not short circuit output to V+, when V+is greater than 13V or reliability will be adversely affected.
(8) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/θJA. All numbers apply for packages soldered directly into a PC board.
Operating Ratings
Supply Voltage 3.0V ≤V+≤15.5V
Junction Temperature LMC6462AM, LMC6464AM −55°C ≤TJ≤+125°C
Range LMC6462AI, LMC6464AI −40°C ≤TJ≤+85°C
LMC6462BI, LMC6464BI −40°C ≤TJ≤+85°C
Thermal Resistance (θJA) P Package, 8-Pin PDIP 115°C/W
D Package, 8-Pin SOIC 193°C/W
NFF Package, 14-Pin PDIP 81°C/W
D Package, 14-Pin SOIC 126°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
5V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2 and RL> 1M. Boldface limits
apply at the temperature extremes. Typ(1) LMC6462AI LMC6462BI LMC6462AM
Symbol Parameter Conditions LMC6464AI LMC6464BI LMC6464AM Units
Limit(2) Limit(2) Limit(2)
VOS Input Offset Voltage 0.25 0.5 3.0 0.5 mV
1.2 3.7 1.5 max
TCVOS Input Offset Voltage 1.5 μV/°C
Average Drift
IBInput Current See(3) 0.15 10 10 200 pA max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) Specified limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
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5V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2 and RL> 1M. Boldface limits
apply at the temperature extremes. Typ(1) LMC6462AI LMC6462BI LMC6462AM
Symbol Parameter Conditions LMC6464AI LMC6464BI LMC6464AM Units
Limit(2) Limit(2) Limit(2)
IOS Input Offset Current See(3) 0.075 5 5 100 pA max
CIN Common-Mode 3 pF
Input Capacitance
RIN Input Resistance >10 Tera Ω
CMRR Common Mode 0V ≤VCM ≤15.0V, 85 70 65 70 dB
Rejection Ratio V+= 15V min
67 62 65
0V ≤VCM ≤5.0V 85 70 65 70
V+= 5V 67 62 65
+PSRR Positive Power Supply 5V ≤V+≤15V, 85 70 65 70 dB
Rejection Ratio V−= 0V, VO= 2.5V min
67 62 65
−PSRR Negative Power Supply −5V ≤V−≤ −15V, 85 70 65 70 dB
Rejection Ratio V+= 0V, VO=−2.5V min
67 62 65
VCM Input Common-Mode V+= 5V −0.2 −0.10 −0.10 −0.10 V
Voltage Range For CMRR ≥50 dB max
0.00 0.00 0.00
5.30 5.25 5.25 5.25 V
min
5.00 5.00 5.00
V+= 15V −0.2 −0.15 −0.15 −0.15 V
For CMRR ≥50 dB max
0.00 0.00 0.00
15.30 15.25 15.25 15.25 V
min
15.00 15.00 15.00
AVLarge Signal RL= 100 kΩ(4) Sourcing V/mV
3000
Voltage Gain min
Sinking V/mV
400 min
RL= 25 kΩ(4) Sourcing V/mV
2500 min
Sinking V/mV
200 min
VOOutput Swing V+= 5V 4.995 4.990 4.950 4.990 V
RL= 100 kΩto V+/2 min
4.980 4.925 4.970
0.005 0.010 0.050 0.010 V
max
0.020 0.075 0.030
V+= 5V 4.990 4.975 4.950 4.975 V
RL= 25 kΩto V+/2 min
4.965 4.850 4.955
0.010 0.020 0.050 0.020 V
max
0.035 0.150 0.045
V+= 15V 14.990 14.975 14.950 14.975 V
RL= 100 kΩto V+/2 min
14.965 14.925 14.955
0.010 0.025 0.050 0.025 V
max
0.035 0.075 0.050
V+= 15V 14.965 14.900 14.850 14.900 V
RL= 25 kΩto V+/2 min
14.850 14.800 14.800
0.025 0.050 0.100 0.050 V
max
0.150 0.200 0.200
(4) V+= 15V, VCM = 7.5V and RLconnected to 7.5V. For Sourcing tests, 7.5V ≤VO≤11.5V. For Sinking tests, 3.5V ≤VO≤7.5V.
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5V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2 and RL> 1M. Boldface limits
apply at the temperature extremes. Typ(1) LMC6462AI LMC6462BI LMC6462AM
Symbol Parameter Conditions LMC6464AI LMC6464BI LMC6464AM Units
Limit(2) Limit(2) Limit(2)
ISC Output Short Circuit Sourcing, VO= 0V 27 19 19 19 mA
Current min
15 15 15
V+ = 5V Sinking, VO= 5V 27 22 22 22 mA
min
17 17 17
ISC Output Short Circuit Sourcing, VO= 0V 38 24 24 24 mA
Current min
17 17 17
V+= 15V Sinking, VO= 12V(5) 75 55 55 55 mA
min
45 45 45
ISSupply Current Dual, LMC6462 40 55 55 55 μA
V+= +5V, VO= V+/2 max
70 70 75
Quad, LMC6464 80 110 110 110 μA
V+= +5V, VO= V+/2 max
140 140 150
Dual, LMC6462 50 60 60 60 μA
V+= +15V, VO= V+/2 max
70 70 75
Quad, LMC6464 90 120 120 120 μA
V+= +15V, VO= V+/2 max
140 140 150
(5) Do not short circuit output to V+, when V+is greater than 13V or reliability will be adversely affected.
5V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5V, V−= 0V, VCM = VO= V+/2 and RL> 1M. Boldface limits
apply at the temperature extremes. Typ(1) LMC6462AI LMC6462BI LMC6462AM
Symbol Parameter Conditions LMC6464AI LMC6464BI LMC6464AM Units
Limit(2) Limit(2) Limit(2)
SR Slew Rate See(3) 15 15 15 V/ms
28 min
888
GBW Gain-Bandwidth Product V+= 15V 50 kHz
φmPhase Margin 50 Deg
GmGain Margin 15 dB
Amp-to-Amp Isolation See(4) 130 dB
enInput-Referred f = 1 kHz 80 nV/√Hz
Voltage Noise VCM = 1V
inInput-Referred Current Noise f = 1 kHz 0.03 pA/√Hz
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) V+= 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of either the positive or negative slew
rates.
(4) Input referred, V+= 15V and RL= 100 kΩconnected to 7.5V. Each amp excited in turn with 1 kHz to produce VO= 12 VPP.
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3V DC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 3V, V−= 0V, VCM = VO= V+/2 and RL> 1M. Boldface limits
apply at the temperature extremes. Typ(1) LMC6462AI LMC6462BI LMC6462AM
Symbol Parameter Conditions LMC6464AI LMC6464BI LMC6464AM Units
Limit(2) Limit(2) Limit(2)
VOS Input Offset Voltage 2.0 3.0 2.0 mV
0.9 max
2.7 3.7 3.0
TCVOS Input Offset Voltage 2.0 μV/°C
Average Drift
IBInput Current See(3) 0.15 10 10 200 pA
IOS Input Offset Current See(3) 0.075 5 5 100 pA
CMRR Common Mode 0V ≤VCM ≤3V dB
74 60 60 60
Rejection Ratio min
PSRR Power Supply 3V ≤V+≤15V, V−= 0V dB
80 60 60 60
Rejection Ratio min
VCM Input Common-Mode For CMRR ≥50 dB V
−0.10 0.0 0.0 0.0
Voltage Range max
3.0 3.0 3.0 3.0 V
min
VOOutput Swing RL= 25 kΩto V+/2 V
2.95 2.9 2.9 2.9 min
V
0.15 0.1 0.1 0.1 max
ISSupply Current Dual, LMC6462 40 55 55 55 μA
VO= V+/2 70 70 70
Quad, LMC6464 80 110 110 110 μA
VO= V+/2 max
140 140 140
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) Specified limits are dictated by tester limitations and not device performance. Actual performance is reflected in the typical value.
3V AC Electrical Characteristics
Unless otherwise specified, V+= 3V, V−= 0V, VCM = VO= V+/2 and RL> 1M. Boldface limits apply at the temperature
extremes. Typ(1) LMC6462AI LMC6462BI LMC6462AM
Symbol Parameter Conditions LMC6464AI LMC6464BI LMC6464AM Units
Limit(2) Limit(2) Limit(2)
SR Slew Rate See(3) 23 V/ms
GBW Gain-Bandwidth Product 50 kHz
(1) Typical Values represent the most likely parametric norm.
(2) All limits are specified by testing or statistical analysis.
(3) Connected as Voltage Follower with 2V step input. Number specified is the slower of either the positive or negative slew rates.
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Typical Performance Characteristics
VS= +5V, Single Supply, TA= 25°C unless otherwise specified
Supply Current Sourcing Current
vs. vs.
Supply Voltage Output Voltage
Figure 4. Figure 5.
Sourcing Current Sourcing Current
vs. vs.
Output Voltage Output Voltage
Figure 6. Figure 7.
Sinking Current Sinking Current
vs. vs.
Output Voltage Output Voltage
Figure 8. Figure 9.
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Typical Performance Characteristics (continued)
VS= +5V, Single Supply, TA= 25°C unless otherwise specified
Sinking Current Input Voltage Noise
vs. vs
Output Voltage Frequency
Figure 10. Figure 11.
Input Voltage Noise Input Voltage Noise
vs. vs.
Input Voltage Input Voltage
Figure 12. Figure 13.
Input Voltage Noise ΔVOS
vs. vs
Input Voltage CMR
Figure 14. Figure 15.
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Typical Performance Characteristics (continued)
VS= +5V, Single Supply, TA= 25°C unless otherwise specified
Input Voltage
vs.
Output Voltage Open Loop Frequency Response
Figure 16. Figure 17.
Open Loop Frequency Response Gain and Phase
vs. vs.
Temperature Capacitive Load
Figure 18. Figure 19.
Slew Rate
vs.
Supply Voltage Non-Inverting Large Signal Pulse Response
Figure 20. Figure 21.
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Typical Performance Characteristics (continued)
VS= +5V, Single Supply, TA= 25°C unless otherwise specified
Non-Inverting Large Signal Pulse Response Non-Inverting Large Signal Pulse Response
Figure 22. Figure 23.
Non-Inverting Small Signal Pulse Response Non-Inverting Small Signal Pulse Response
Figure 24. Figure 25.
Non-Inverting Small Signal Pulse Response Inverting Large Signal Pulse Response
Figure 26. Figure 27.
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Typical Performance Characteristics (continued)
VS= +5V, Single Supply, TA= 25°C unless otherwise specified
Inverting Large Signal Pulse Response Inverting Large Signal Pulse Response
Figure 28. Figure 29.
Inverting Small Signal Pulse Response Inverting Small Signal Pulse Response
Figure 30. Figure 31.
Inverting Small Signal Pulse Response
Figure 32.
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APPLICATION INFORMATION
Input Common-Mode Voltage Range
The LMC6462/4 has a rail-to-rail input common-mode voltage range. Figure 33 shows an input voltage
exceeding both supplies with no resulting phase inversion on the output.
Figure 33. An Input Voltage Signal Exceeds the LMC6462/4 Power Supply Voltage with No Output Phase
Inversion
The absolute maximum input voltage at V+= 3V is 300 mV beyond either supply rail at room temperature.
Voltages greatly exceeding this absolute maximum rating, as in Figure 34, can cause excessive current to flow in
or out of the input pins, possibly affecting reliability. The input current can be externally limited to ±5 mA, with an
input resistor, as shown in Figure 35.
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Figure 34. A ±7.5V Input Signal Greatly Exceeds the 3V Supply in Figure 35 Causing No Phase Inversion
Due to RI
Figure 35. Input Current Protection for Voltages Exceeding the Supply Voltage
Rail-to-Rail Output
The approximated output resistance of the LMC6462/4 is 180Ωsourcing, and 130Ωsinking at VS= 3V, and
110Ωsourcing and 83Ωsinking at VS= 5V. The maximum output swing can be estimated as a function of load
using the calculated output resistance.
Capacitive Load Tolerance
The LMC6462/4 can typically drive a 200 pF load with VS= 5V at unity gain without oscillating. The unity gain
follower is the most sensitive configuration to capacitive load. Direct capacitive loading reduces the phase margin
of op-amps. The combination of the op-amp's output impedance and the capacitive load induces phase lag. This
results in either an underdamped pulse response or oscillation.
Capacitive load compensation can be accomplished using resistive isolation as shown in Figure 36. If there is a
resistive component of the load in parallel to the capacitive component, the isolation resistor and the resistive
load create a voltage divider at the output. This introduces a DC error at the output.
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Figure 36. Resistive Isolation of a 300 pF Capacitive Load
Figure 37. Pulse Response of the LMC6462 Circuit Shown in Figure 36
Figure 37 displays the pulse response of the LMC6462/4 circuit in Figure 36.
Another circuit, shown in Figure 38, is also used to indirectly drive capacitive loads. This circuit is an
improvement to the circuit shown in Figure 36 because it provides DC accuracy as well as AC stability. R1 and
C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal
back to the amplifiers inverting input, thereby preserving phase margin in the overall feedback loop. The values
of R1 and C1 should be experimentally determined by the system designer for the desired pulse response.
Increased capacitive drive is possible by increasing the value of the capacitor in the feedback loop.
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Figure 38. LMC6462 Non-Inverting Amplifier, Compensated to Handle a 300 pF Capacitive and 100 kΩ
Resistive Load
Figure 39. Pulse Response of LMC6462 Circuit in Figure 38
The pulse response of the circuit shown in Figure 38 is shown in Figure 39
Compensating for Input Capacitance
It is quite common to use large values of feedback resistance with amplifiers that have ultra-low input current,
like the LMC6462/4. Large feedback resistors can react with small values of input capacitance due to
transducers, photodiodes, and circuits board parasitics to reduce phase margins.
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Figure 40. Canceling the Effect of Input Capacitance
The effect of input capacitance can be compensated for by adding a feedback capacitor. The feedback capacitor
(as in Figure 40 ), CF, is first estimated by:
(1)
or R1CIN ≤R2CF(2)
which typically provides significant overcompensation.
Printed circuit board stray capacitance may be larger or smaller than that of a breadboard, so the actual optimum
value for CFmay be different. The values of CFshould be checked on the actual circuit. (Refer to the LMC660
quad CMOS amplifier data sheet for a more detailed discussion.)
Offset Voltage Adjustment
Offset voltage adjustment circuits are illustrated in Figure 41 and Figure 42. Large value resistances and
potentiometers are used to reduce power consumption while providing typically ±2.5 mV of adjustment range,
referred to the input, for both configurations with VS= ±5V.
Figure 41. Inverting Configuration Offset Voltage Adjustment
Figure 42. Non-Inverting Configuration Offset Voltage Adjustment
SPICE Macromodel
A Spice macromodel is available for the LMC6462/4. This model includes a simulation of:
• Input common-mode voltage range
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• Frequency and transient response
• GBW dependence on loading conditions
• Quiescent and dynamic supply current
• Output swing dependence on loading conditions
and many more characteristics as listed on the macromodel disk.
Contact the Texas Instruments Customer Response Center to obtain an operational amplifier Spice model library
disk
Printed-Circuit-Board Layout for High-Impedance Work
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low input current of the
LMC6462/4, typically 150 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining
low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though
it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination,
the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6462's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs, as in Figure 43. To have a significant effect, guard rings should be placed in both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of the input. This would cause a 30 times degradation from the
LMC6462/4's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ωwould cause only 0.05 pA of leakage current. See Figure 44 through Figure 46 for typical
connections of guard rings for standard op-amp configurations.
Figure 43. Example of Guard Ring in P.C. Board Layout
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Figure 44. Typical Connections of Guard Rings – Inverting Amplifier
Figure 45. Typical Connections of Guard Rings – Non-Inverting Amplifier
Figure 46. Typical Connections of Guard Rings – Follower
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 47.
(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 47. Air Wiring
Instrumentation Circuits
The LMC6464 has the high input impedance, large common-mode range and high CMRR needed for designing
instrumentation circuits. Instrumentation circuits designed with the LMC6464 can reject a larger range of
common-mode signals than most in-amps. This makes instrumentation circuits designed with the LMC6464 an
excellent choice for noisy or industrial environments. Other applications that benefit from these features include
analytic medical instruments, magnetic field detectors, gas detectors, and silicon-based transducers.
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+
-
191:
9.95k
10k,
0.1%
10k, 0.1%
10k,
0.1%
50:
A2
A1
+
-
VOUT = 100VD
VCM - 1/2VD
10:
Gain
Trim
VCM + 1/2VD
CMRR
Trim
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A small valued potentiometer is used in series with RGto set the differential gain of the three op-amp
instrumentation circuit in Figure 48. This combination is used instead of one large valued potentiometer to
increase gain trim accuracy and reduce error due to vibration.
Figure 48. Low Power Three Op-Amp Instrumentation Amplifier
A two op-amp instrumentation amplifier designed for a gain of 100 is shown in Figure 49. Low sensitivity
trimming is made for offset voltage, CMRR and gain. Low cost and low power consumption are the main
advantages of this two op-amp circuit.
Higher frequency and larger common-mode range applications are best facilitated by a three op-amp
instrumentation amplifier.
Figure 49. Low-Power Two-Op-Amp Instrumentation Amplifier
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TYPICAL SINGLE-SUPPLY APPLICATIONS
Transducer Interface Circuits
Figure 50. Photo Detector Circuit
Photocells can be used in portable light measuring instruments. The LMC6462, which can be operated off a
battery, is an excellent choice for this circuit because of its very low input current and offset voltage.
LMC6462 as a Comparator
Figure 51. Comparator with Hysteresis
Figure 51 shows the application of the LMC6462 as a comparator. The hysteresis is determined by the ratio of
the two resistors. The LMC6462 can thus be used as a micropower comparator, in applications where the
quiescent current is an important parameter.
Half-Wave and Full-Wave Rectifiers
Figure 52. Half-Wave Rectifier with Input Current Protection (RI)
Figure 53. Full-Wave Rectifier with Input Current Protection (RI)
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMC6462 LMC6464
LMC6462, LMC6464
SNOS725D –MAY 1999–REVISED MARCH 2013
www.ti.com
In Figure 52 Figure 53, RIlimits current into the amplifier since excess current can be caused by the input
voltage exceeding the supply voltage.
Precision Current Source
Figure 54. Precision Current Source
The output current IOUT is given by:
(3)
Oscillators
Figure 55. 1 Hz Square-Wave Oscillator
For single supply 5V operation, the output of the circuit will swing from 0V to 5V. The voltage divider set up R2,
R3and R4will cause the non-inverting input of the LMC6462 to move from 1.67V (⅓of 5V) to 3.33V (⅔of 5V).
This voltage behaves as the threshold voltage.
R1and C1determine the time constant of the circuit. The frequency of oscillation, fOSC is
(4)
where Δt is the time the amplifier input takes to move from 1.67V to 3.33V. The calculations are shown below.
(5)
where τ= RC = 0.68 seconds
→t1= 0.27 seconds.
and
(6)
→t2= 0.75 seconds
20 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LMC6462 LMC6464
LMC6462, LMC6464
www.ti.com
SNOS725D –MAY 1999–REVISED MARCH 2013
Then,
(7)
(8)
= 1 Hz
Low Frequency Null
Figure 56. High Gain Amplifier with Low Frequency Null
Output offset voltage is the error introduced in the output voltage due to the inherent input offset voltage VOS, of
an amplifier.
Output Offset Voltage = (Input Offset Voltage) (Gain)
In the above configuration, the resistors R5and R6determine the nominal voltage around which the input signal,
VIN should be symmetrical. The high frequency component of the input signal VIN will be unaffected while the low
frequency component will be nulled since the DC level of the output will be the input offset voltage of the
LMC6462 plus the bias voltage. This implies that the output offset voltage due to the top amplifier will be
eliminated.
Copyright © 1999–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMC6462 LMC6464
LMC6462, LMC6464
SNOS725D –MAY 1999–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 21
22 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: LMC6462 LMC6464
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMC6462AIM NRND SOIC D 8 95 Non-RoHS &
Non-Green Call TI Call TI -40 to 85 LMC64
62AIM
LMC6462AIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC64
62AIM
LMC6462AIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC64
62AIM
LMC6462AIN/NOPB ACTIVE PDIP P 8 40 RoHS & Green SN Level-1-NA-UNLIM -40 to 85 LMC6462
AIN
LMC6462B-MDC ACTIVE DIESALE Y 0 324 RoHS & Green Call TI Level-1-NA-UNLIM -40 to 85
LMC6462BIM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC64
62BIM
LMC6462BIMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC64
62BIM
LMC6462BIN/NOPB ACTIVE PDIP P 8 40 RoHS & Green SN Level-1-NA-UNLIM -40 to 85 LMC6462
BIN
LMC6464AIM NRND SOIC D 14 55 Non-RoHS &
Non-Green Call TI Call TI -40 to 85 LMC6464
AIM
LMC6464AIM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6464
AIM
LMC6464AIMX NRND SOIC D 14 2500 Non-RoHS &
Non-Green Call TI Call TI -40 to 85 LMC6464
AIM
LMC6464AIMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6464
AIM
LMC6464BIM NRND SOIC D 14 55 Non-RoHS &
Non-Green Call TI Call TI -40 to 85 LMC6464
BIM
LMC6464BIM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6464
BIM
LMC6464BIMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6464
BIM
LMC6464BIN/NOPB ACTIVE PDIP NFF 14 25 RoHS & Green SN Level-1-NA-UNLIM -40 to 85 LMC6464BIN
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMC6462AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC6462BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC6464AIMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMC6464AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMC6464BIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMC6462AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC6462BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC6464AIMX SOIC D 14 2500 367.0 367.0 35.0
LMC6464AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMC6464BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA
N0014A
www.ti.com
N14A (Rev G)
NFF0014A
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