Semiconductor Components Industries, LLC, 2002
May, 2002 – Rev. 3 1Publication Order Number:
MMBT2369LT1/D
MMBT2369LT1,
MMBT2369ALT1
MMBT2369ALT1 is a Preferred Device
Switching Transistors
NPN Silicon
MAXIMUM RATINGS
Rating Symbol Value Unit
Collector–Emitter Voltage VCEO 15 Vdc
Collector–Emitter Voltage VCES 40 Vdc
Collector–Base Voltage VCBO 40 Vdc
Emitter–Base V oltage VEBO 4.5 Vdc
Collector Current – Continuous IC200 mAdc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board
(Note 1) TA = 25°C
Derate above 25°C
PD225
1.8
mW
mW/°C
Thermal Resistance,
Junction to Ambient RJA 556 °C/W
Total Device Dissipation Alumina
Substrate, (Note 2) TA = 25°C
Derate above 25°C
PD300
2.4
mW
mW/°C
Thermal Resistance,
Junction to Ambient RJA 417 °C/W
Junction and Storage Temperature TJ, Tstg –55 to
+150 °C
1. FR–5 = 1.0 0.75 0.062 in.
2. Alumina = 0.4 0.3 0.024 in. 99.5% alumina.
Device Package Shipping
ORDERING INFORMATION
MMBT2369LT1 SOT–23
SOT–23
CASE 318
STYLE 6
3000/Tape & Reel
2
3
1
Preferred devices are recommended choices for future use
and best overall value.
MARKING DIAGRAMS
M1J X
MMBT2369LT1
COLLECTOR
3
1
BASE
2
EMITTER
1JA X
MMBT2369ALT1
MMBT2369ALT1 SOT–23 3000/Tape & Reel
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M1J, 1JA = Specific Device Code
X = Date Code
MMBT2369LT1, MMBT2369ALT1
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ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector–Emitter Breakdown Voltage (Note 3)
(IC = 10 mAdc, IB = 0) V(BR)CEO 15 – – Vdc
Collector–Emitter Breakdown Voltage
(IC = 10 µAdc, VBE = 0) V(BR)CES 40 – – Vdc
Collector–Base Breakdown Voltage
(IC = 10 Adc, IE = 0) V(BR)CBO 40 – – Vdc
Emitter–Base Breakdown Voltage
(IE = 10 Adc, IC = 0) V(BR)EBO 4.5 – – Vdc
Collector Cutoff Current
(VCB = 20 Vdc, IE = 0)
(VCB = 20 Vdc, IE = 0, TA = 150°C)
ICBO –
––
–0.4
30
µAdc
Collector Cutoff Current
(VCE = 20 Vdc, VBE = 0) MMBT2369A ICES – – 0.4 µAdc
ON CHARACTERISTICS
DC Current Gain (Note 3)
(IC = 10 mAdc, VCE = 1.0 Vdc) MMBT2369
(IC = 10 mAdc, VCE = 1.0 Vdc) MMBT2369A
(IC = 10 mAdc, VCE = 0.35 Vdc) MMBT2369A
(IC = 10 mAdc, VCE = 0.35 Vdc, TA = –55°C) MMBT2369A
(IC = 30 mAdc, VCE = 0.4 Vdc) MMBT2369A
(IC = 100 mAdc, VCE = 2.0 Vdc) MMBT2369
(IC = 100 mAdc, VCE = 1.0 Vdc) MMBT2369A
hFE 40
–
40
20
30
20
20
–
–
–
–
–
–
–
120
120
–
–
–
–
–
–
Collector–Emitter Saturation Voltage (Note 3)
(IC = 10 mAdc, IB = 1.0 mAdc) MMBT2369
(IC = 10 mAdc, IB = 1.0 mAdc) MMBT2369A
(IC = 10 mAdc, IB = 1.0 mAdc, TA = +125°C) MMBT2369A
(IC = 30 mAdc, IB = 3.0 mAdc) MMBT2369A
(IC = 100 mAdc, IB = 10 mAdc) MMBT2369A
VCE(sat) –
–
–
–
–
–
–
–
–
–
0.25
0.20
0.30
0.25
0.50
Vdc
Base–Emitter Saturation Voltage (Note 3)
(IC = 10 mAdc, IB = 1.0 mAdc) MMBT2369A
(IC = 10 mAdc, IB = 1.0 mAdc, TA = –55°C) MMBT2369A
(IC = 30 mAdc, IB = 3.0 mAdc) MMBT2369A
(IC = 100 mAdc, IB = 10 mAdc) MMBT2369A
VBE(sat) 0.7
–
–
–
–
–
–
–
0.85
1.02
1.15
1.60
Vdc
SMALL–SIGNAL CHARACTERISTICS
Output Capacitance
(VCB = 5.0 Vdc, IE = 0, f = 1.0 MHz) Cobo – – 4.0 pF
Small Signal CurrentGain
(IC = 10 mAdc, VCE = 10 Vdc, f = 100 MHz) hfe 5.0 – – –
SWITCHING CHARACTERISTICS
Storage Time
(IB1 = IB2 = IC = 10 mAdc) ts– 5.0 13 ns
Turn–On Time
(VCC = 3.0 Vdc, IC = 10 mAdc, IB1 = 3.0 mAdc) ton – 8.0 12 ns
Turn–Off Time
(VCC = 3.0 Vdc, IC = 10 mAdc, IB1 = 3.0 mAdc, IB2 = 1.5 mAdc) toff – 10 18 ns
3. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
MMBT2369LT1, MMBT2369ALT1
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Figure 1. ton Circuit – 10 mA
Figure 2. ton Circuit – 100 mA
Figure 3. toff Circuit – 10 mA
Figure 4. toff Circuit – 100 mA
Figure 5. Turn–On and Turn–Off Time Test Circuit
+10.6 V
-1.5 V
0
t1
< 1 ns
PULSE WIDTH (t1) = 300 ns
DUTY CYCLE = 2%
3 V 270 Ω
3.3 k Cs* < 4 pF
10 V 95 Ω
1 k Cs* < 12 pF
+10.8 V
-2 V 0
t1
< 1 ns
PULSE WIDTH (t1) = 300 ns
DUTY CYCLE = 2%
+10.75 V
0
-9.15 V
t1
< 1 ns
PULSE WIDTH (t1) = 300 ns
DUTY CYCLE = 2%
< 1 ns
-8.6 V
+11.4 V t1
0
PULSE WIDTH (t1) BETWEEN
10 AND 500 µs
DUTY CYCLE = 2%
270 Ω
3.3 k Cs* < 4 pF
95 Ω
1 k Cs* < 12 pF
10 V
1N916
SWITCHING TIME EQUIVALENT TEST CIRCUITS FOR 2N2369, 2N3227
Vout 90%
10%
Vin
0
ton
Vin
3.3 kΩ
50 Ω
220 Ω
50 Ω
0.1 µF
Vout
3.3 k
0.0023 µF 0.0023 µF
0.005 µF 0.005 µF
0.1 µF 0.1 µF
VBB +
-+
-VCC = 3 V
Vin
0
90%
10%
toff
Vout
VBB = +12 V
Vin = -15 V
TO OSCILLOSCOPE
INPUT IMPEDANCE = 50 Ω
RISE TIME = 1 ns
TURN-OFF WAVEFORMS
PULSE GENERATOR
Vin RISE TIME < 1 ns
SOURCE IMPEDANCE = 50 Ω
PW ≥ 300 ns
DUTY CYCLE < 2%
TURN-ON WAVEFORMS
*Total shunt capacitance of test jig and connectors.
*Total shunt capacitance of test jig and connectors.
6
5
4
3
2
1
100.1 0.2 0.5 1.0 2.0 5.0
REVERSE BIAS (VOLTS)
CAPACITANCE (pF)
SWITCHING TIMES (nsec)
LIMIT
TYPICAL
Cob
Cib
TJ = 25°C
Figure 6. Junction Capacitance Variations
100
2
5
10
20
50
1 2 5 10 20 50 100
IC, COLLECTOR CURRENT (mA)
Figure 7. Typical Switching Times
βF = 10
VCC = 10 V
VOB = 2 V
tr (VCC = 3 V)
VCC = 10 V
td
ts
tr
tf
MMBT2369LT1, MMBT2369ALT1
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25°C
100°C
QT, βF = 10
500
1
IC, COLLECTOR CURRENT (mA)
Figure 8. Maximum Charge Data
10
20
50
100
200
2 5 10 20 50 100
VCC = 10 V
QT, βF = 40
QA, VCC = 10 V
QA, VCC = 3 V
CHARGE (pC)
+5 V
0
t1
< 1 ns
PULSE WIDTH (t1) = 5 µs
DUTY CYCLE = 2%
3 V 270
4.3 k
Cs* < 4 pF
∆V10 pF MAX
VALUES REFER TO
IC = 10 mA TEST
Figure 9. QT Test Circuit
+6 V
-4 V
0
t1
< 1 ns
PULSE WIDTH (t1) = 300 ns
DUTY CYCLE = 2%
10 V 980
500 Cs* < 3 pF
C COPT
TIME
C < COPT C = 0
Figure 10. Turn–Off Waveform Figure 11. Storage Time Equivalent Test Circuit
VCE, MAXIMUM COLLECTOR-EMITTER VOLTAGE (VOLTS)
1.0
0.8
0.6
0.4
0.2
0.02 0.05 0.1 0.2 0.5 1 2 5 10 20
IC = 3 mA IC = 10 mA IC = 30 mA IC = 50 mA IC = 100 mA
TJ = 25°C
IB, BASE CURRENT (mA)
Figure 12. Maximum Collector Saturation Voltage Characteristics
MMBT2369LT1, MMBT2369ALT1
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hFE, MINIMUM DC CURRENT GAIN
V(sat), SATURATION VOLTAGE (VOLTS)
COEFFICIENT (mV/ C)°
200
100
20
50
1 2 5 10 20 50 100
IC, COLLECTOR CURRENT (mA)
Figure 13. Minimum Current Gain Characteristics
VCE = 1 V
TJ = 125°C
75°C
25°C
-15°C
-55°C
TJ = 25°C and 75°C
1.4
1.2
1.0
0.8
0.6
0.4
0.2 1 2 5 10 20 50 100
IC, COLLECTOR CURRENT (mA)
Figure 14. Saturation Voltage Limits
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5 0 102030405060708090100
IC, COLLECTOR CURRENT (mA)
Figure 15. Typical Temperature Coefficients
βF = 10
TJ = 25°C
MAX VBE(sat)
MIN VBE(sat)
MAX VCE(sat)
(25°C to 125°C)
(-55°C to +25°C)
(-55°C to +25°C)
(25°C to 125°C)
θVC for VCE(sat)
θVB for VBE(sat)
-55°C to +25°C25°C to 125°C
θVC ±0.15 mV/°C±0.15 mV/°C
θVB ±0.4 mV/°C±0.3 mV/°C
APPROXIMATE DEVIATION
FROM NOMINAL
MMBT2369LT1, MMBT2369ALT1
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6
INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
SOT–23
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature o f the die, RθJA, the thermal resistance from t h e
device junction to ambient, and the operating temperature,
TA. Using the values provided on the data sheet for the
SOT–23 package, PD can be calculated as follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this
case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 225 milliwatts.
There are other alternatives to achieving higher power
dissipation from the SOT–23 package. Another alternative
would be to use a ceramic substrate or an aluminum core
board such as Thermal Clad. Using a board material such
as Thermal Clad, an aluminum core board, the power
dissipation can be doubled using the same footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and soldering
should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied during
cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
MMBT2369LT1, MMBT2369ALT1
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7
PACKAGE DIMENSIONS
CASE 318–08
ISSUE AH
SOT–23 (TO–236)
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
4. 318-03 AND -07 OBSOLETE, NEW STANDARD
318-08.
STYLE 6:
PIN 1. BASE
2. EMITTER
3. COLLECTOR
MMBT2369LT1, MMBT2369ALT1
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changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
For additional information, please contact your local
Sales Representative.
MMBT2369LT1/D
Thermal Clad is a registered trademark of the Bergquist Company.
Literature Fulfillment:
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Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
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