MC14512BD - Motorola / Freescale Semiconductor

MOTOROLA CMOS LOGIC DATAMC14512B

370

  

The MC14512B is an 8–channel data selector constructed with MOS

P–channel and N–channel enhancement mode devices in a single

monolithic structure. This data selector finds primary application in signal

multiplexing functions. It may also be used for data routing, digital signal

switching, signal gating, and number sequence generation.

•Diode Protection on All Inputs

•Single Supply Operation

•3–State Output (Logic “1”, Logic “0”, High Impedance)

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS* (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage – 0.5 to + 18.0 V

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current (DC or Transient),

per Pin ± 10 mA

PDPower Dissipation, per Package† 500 mW

Tstg Storage Temperature – 65 to + 150

TLLead Temperature (8–Second Soldering) 260

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages: – 12 mW/

C From 100

C To 125

TRUTH TABLE

C B A Inhibit Disable Z

0 0 0 0 0 X0

0 0 1 0 0 X1

0 1 0 0 0 X2

0 1 1 0 0 X3

1 0 0 0 0 X4

1 0 1 0 0 X5

1 1 0 0 0 X6

1 1 1 0 0 X7

X X X 1 0 0

X X X X 1 High

Impedance

X = Don’t Care



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94



L SUFFIX

CERAMIC

CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

PIN ASSIGNMENT

This device contains protection circuitry to

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, Vin and Vout should be constrained

to the range VSS

(Vin or Vout)

VDD.

Unused inputs must always be tied to an

appropriate logic voltage level (e.g., either VSS

or VDD). Unused outputs must be left open.

125

DIS

VDD

INH

VSS

MOTOROLA CMOS LOGIC DATA 371

MC14512B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic

Symbol

VDD

Vdc

– 55

C 25

C 125

Unit

Characteristic

Symbol

VDD

Vdc

Min Max Min Typ # Max Min Max

Unit

Output Voltage

“0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

VOL 5.0

—

0.05

—

0.05

—

0.05

Vdc

“1” Level

Vin = 0 or VDD

VOH 5.0

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

—

4.95

9.95

14.95

—

Vdc

Input Voltage

“0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIL 5.0

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

Vdc

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

VIH 5.0

3.5

7.0

—

3.5

7.0

2.75

5.50

8.25

—

3.5

7.0

—

Vdc

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

IOH 5.0

5.0

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

mAdc

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

IOL 5.0

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

Input Current Iin 15 — ± 0.1 — ±0.00001 ± 0.1 — ± 1.0 µAdc

Input Capacitance

(Vin = 0) Cin — — — — 5.0 7.5 — — pF

Quiescent Current

(Per Package) IDD 5.0

—

5.0

—

0.005

0.010

0.015

5.0

—

150

300

600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

IT5.0

IT = (0.8 µA/kHz) f + IDD

IT = (1.6 µA/kHz) f + IDD

IT = (2.4 µA/kHz) f + IDD

µAdc

Three–State Leakage Current ITL 15 — ± 0.1 — ± 0.0001 ± 0.1 — ± 3.0 µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.

The formulas given are for the typical characteristics only at 25

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MOTOROLA CMOS LOGIC DATAMC14512B

372

SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25

C, See Figure 1)

Characteristic

Symbol

VDD

All Types

Unit

Characteristic

Symbol

VDD

Typ # Max

Unit

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

tTLH,

tTHL 5.0

100

200

100

Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z tPLH 5.0

330

125

650

250

170

Propagation Delay Time (Figure 2)

Inhibit, Control, or Data to Z tPHL 5.0

330

125

650

250

170

3–State Output Delay Times (Figure 3)

“1” or “0” to High Z, and

High Z to “1” or “0”

tPHZ, tPLZ,

tPZH, tPZL 5.0

150

100

*The formulas given are for the typical characteristics only at 25

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.

Figure 1. Power Dissipation Test Circuit and Waveform

VDD

DISABLE

INHIBIT

X7 VSS

PULSE

GENERATOR

50%Vin 50%

DUTY

CYCLE

Parameter Test Conditions

Inhibit to Z A, B, C = VSS, XO = VDD

A, B, C to Z Inh = VSS, XO = VDD

Figure 2. AC Test Circuit and Waveforms

VDD

VSS

VOH

VOL

VDD

VSS

VOH

VOL

VDD

DISABLE

INHIBIT

VSS

PULSE

GENERATOR

20 ns 20 ns

90%

50%

10%

tPLH tPHL

90%

10%

50%

DATA

tTLH tTHL

TEST CONDITIONS:

INHIBIT = VSS

A, B, C = VSS

20 ns 20 ns

tPHL tPLH

50%

90%

10%

tTHL tTLH

INHIBIT,

A, B, OR C 90%

50%

10%

MOTOROLA CMOS LOGIC DATA 373

MC14512B

Figure 3. 3–State AC Test Circuit and Waveform

Test S1 S2 S3 S4

tPHZ Open Closed Closed Open

tPLZ Closed Open Open Closed

tPZL Closed Open Open Closed

tPZH Open Closed Closed Open

Switch Positions for 3–State Test

DISABLE

INHIBIT

VSS

PULSE

GENERATOR

VDD

1 k S1

VSS

VDD

VSS

VDD

VOH

VOL

20 ns

90%

50%

10%

tPLZ tPZL

20 ns

DISABLE

INPUT

OUTPUT

VSS

VOH

VOL

10%

90%

10%

tPHZ tPZH

≈

2.5 V @ VDD = 5 V,

10 V, AND 15 V

≈

2 V @ VDD = 5 V

≈

6 V @ VDD = 10 V

≈

10 V @ VDD = 15 V

LOGIC DIAGRAM

DISABLE

INHIBIT

VDD

VSS

IN OUT IN

OUT

TRANSMISSION

GATE

SELECTED

DEVICE

MC14512B

IOD

ITL

ILLOAD

DATA

BUS

3–STATE MODE OF OPERATION

Output terminals of several MC14512B 8–Bit Data Selec-

tors can be connected to a single date bus as shown. One

MC14512B is selected by the 3–state control, and the re-

maining devices are disabled into a high–impedance “off”

state. The number of 8–bit data selectors, N, that may be

connected to a bus line is determined from the output drive

current, IOD, 3–state or disable output leakage current, ITL,

and the load current, IL, required to drive the bus line (includ-

ing fanout to other device inputs), and can be calculated by:

ITL

N = + 1

IOD – IL

N must be calculated for both high and low logic state of the

bus line.

MOTOROLA CMOS LOGIC DATAMC14512B

374

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

HGD

16 PL

SEATING

1 8

916

PLANE

–T–

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–A–

–B–

–T–

SEATING

PLANE

16 PLD

0.25 (0.010) T

16 PLJ

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.750 0.785 19.05 19.93

B0.240 0.295 6.10 7.49

C––– 0.200 ––– 5.08

D0.015 0.020 0.39 0.50

E0.050 BSC 1.27 BSC

F0.055 0.065 1.40 1.65

G0.100 BSC 2.54 BSC

H0.008 0.015 0.21 0.38

K0.125 0.170 3.18 4.31

L0.300 BSC 7.62 BSC

M0 15 0 15

N0.020 0.040 0.51 1.01

_ _ _ _

16 9

1 8

MOTOROLA CMOS LOGIC DATA 375

MC14512B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

1 8

16 9

SEATING

PLANE

RX 45

8 PLP

–B–

–A–

0.25 (0.010) B S

–T–

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

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MC14512B/D

*MC14512B/D*

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