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1A
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2A
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2Y
DESCRIPTION/ORDERING INFORMATION
SN74LVC2G06-EPDUAL INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
SCES660 – JUNE 2006
•Controlled Baseline •Typical V
OHV
(Output V
OH
Undershoot)>2 V at V
CC
= 3.3 V, T
A
= 25 °C– One Assembly/Test Site, One FabricationSite •Inputs and Open-Drain Outputs AcceptVoltages up to 5.5 V•Extended Temperature Performance of –55 °Cto 125 °C•I
off
Supports Partial-Power-Down ModeOperation•Enhanced Diminishing ManufacturingSources (DMS) Support •Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•Enhanced Product-Change Notification
•ESD Protection Exceeds JESD 22•Qualification Pedigree
(1)
– 2000-V Human-Body Model (A114-A)•Supports 5-V V
CC
Operation
– 200-V Machine Model (A115-A)•Max t
pd
of 4.6 ns at 3.3 V
– 1000-V Charged-Device Model (C101)•Low Power Consumption, 10- µA Max I
CC• ± 24-mA Output Drive at 3.3 V•Typical V
OLP
(Output Ground Bounce)<0.8 V at V
CC
= 3.3 V, T
A
= 25 °C(1) Component qualification in accordance with JEDEC andindustry standards to ensure reliable operation over anextended temperature range. This includes, but is not limitedto, Highly Accelerated Stress Test (HAST) or biased 85/85,temperature cycle, autoclave or unbiased HAST,electromigration, bond intermetallic life, and mold compoundlife. Such qualification testing should not be viewed asjustifying use of this component beyond specifiedperformance and environmental limits.
This dual inverter buffer/driver is designed for 1.65-V to 5.5-V V
CC
operation.
The output of the SN74LVC2G06 device is open drain and can be connected to other open-drain outputs toimplement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
–55 °C to 125 °C SOT (SC-70) – DCK Tape and reel SN74LVC2G06MDCKREP CTO
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
FUNCTION TABLE(each inverter)
INPUT OUTPUTA Y
H LL H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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1A 1Y
1 6
2A 2Y
3 4
Absolute Maximum Ratings
(1)
SN74LVC2G06-EP
DUAL INVERTER BUFFER/DRIVERWITH OPEN-DRAIN OUTPUTS
SCES660 – JUNE 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 6.5 VV
I
Input voltage range
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high-impedance or power-off state
(2)
–0.5 6.5 VV
O
Voltage range applied to any output in the high or low state
(2) (3)
–0.5 6.5 VI
IK
Input clamp current V
I
< 0 –50 mAI
OK
Output clamp current V
O
< 0 –50 mAI
O
Continuous output current ±50 mAContinuous current through V
CC
or GND ±100 mAθ
JA
Package thermal impedance
(4)
259 °C/WT
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The value of V
CC
is provided in the recommended operating conditions table.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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Recommended Operating Conditions
(1)
Electrical Characteristics
SN74LVC2G06-EPDUAL INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
SCES660 – JUNE 2006
MIN MAX UNIT
Operating 1.65 5.5V
CC
Supply voltage VData retention only 1.5V
CC
= 1.65 V to 1.95 V 0.65 ×V
CC
V
CC
= 2.3 V to 2.7 V 1.7V
IH
High-level input voltage VV
CC
= 3 V to 3.6 V 2V
CC
= 4.5 V to 5.5 V 0.7 ×V
CC
V
CC
= 1.65 V to 1.95 V 0.35 ×V
CC
V
CC
= 2.3 V to 2.7 V 0.7V
IL
Low-level input voltage VV
CC
= 3 V to 3.6 V 0.8V
CC
= 4.5 V to 5.5 V 0.3 ×V
CC
V
I
Input voltage 0 5.5 VV
O
Output voltage 0 5.5 VV
CC
= 1.65 V 4V
CC
= 2.3 V 8I
OL
Low-level output current 16 mAV
CC
= 3 V
24V
CC
= 4.5 V 32V
CC
= 1.8 V ±0.15 V, 2.5 V ±0.2 V 20∆t/ ∆v Input transition rise or fall rate V
CC
= 3.3 V ±0.3 V 10 ns/VV
CC
= 5 V ±0.5 V 5T
A
Operating free-air temperature –55 125 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OL
= 100 µA 1.65 V to 5.5 V 0.1I
OL
= 4 mA 1.65 V 0.45I
OL
= 8 mA 2.3 V 0.3V
OL
VI
OL
= 16 mA 0.43 VI
OL
= 24 mA 0.55I
OL
= 32 mA 4.5 V 0.55I
I
A inputs V
I
= 5.5 V or GND 0 to 5.5 V ±5µAI
off
V
I
or V
O
= 5.5 V 0 ±10 µAI
CC
V
I
= 5.5 V or GND, I
O
= 0 1.65 V to 5.5 V 10 µA∆I
CC
One input at V
CC
– 0.6 V, Other inputs at V
CC
or GND 3 V to 5.5 V 500 µAC
i
V
I
= V
CC
or GND 3.3 V 3.5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 °C.
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Switching Characteristics
Operating Characteristics
SN74LVC2G06-EP
DUAL INVERTER BUFFER/DRIVERWITH OPEN-DRAIN OUTPUTS
SCES660 – JUNE 2006
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VFROM TO
±0.15 V ±0.2 V ±0.3 V ±0.5 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A Y 1.8 9.1 0.9 5.7 0.9 4.6 0.7 3.9 ns
T
A
= 25 °C
V
CC
= 1.8 V V
CC
= 2.5 V V
CC
= 3.3 V V
CC
= 5 VPARAMETER TEST CONDITIONS UNITTYP TYP TYP TYP
C
pd
Power dissipation capacitance f = 10 MHz 2 2 3 4 pF
4
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PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at VLOAD
(see Note B)
VOL
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VLOAD/2 − V∆
≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd.
F. tPZL is measured at VM.
G. tPLZ is measured at VOL + V∆.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
INPUT
tPZL (see Notes E and F)
tPLZ (see Notes E and G)
tPHZ/tPZH
VLOAD
VLOAD
VLOAD
TEST S1
VLOAD/2
SN74LVC2G06-EPDUAL INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
SCES660 – JUNE 2006
(Open Drain)
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LVC2G06MDCKREP ACTIVE SC70 DCK 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
V60/06640-01XE ACTIVE SC70 DCK 6 TBD Call TI Call TI
V62/06640-01XE ACTIVE SC70 DCK 6 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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PACKAGE OPTION ADDENDUM
www.ti.com 5-Feb-2007
Addendum-Page 1
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