I2C Bus Interface - Master ver 3.01 OVERVIEW I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CM core provides an interface between a microprocessor / microcontroller and an I2C bus. It can work as a master transmitter or master receiver depending on working mode determined by microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and High-speed transmission mode. Built-in timer allows operation from a wide range of the clk frequencies. KEY FEATURES 2 Build-in 8-bit timer for data transfers speed adjusting Host side interface dedicated for microprocessors/microcontrollers User-defined timing (data setup, start setup, start hold, etc.) Fully synthesizable Static synchronous design with positive edge clocking and synchronous reset No internal tri-states Scan test ready APPLICATIONS Embedded microprocessor boards Consumer and professional audio/video Conforms to v.2.1 of the I C specification Home and automotive radio Master operation Low-power applications Master transmitter Communication systems Master receiver Cost-effective reliable automotive systems Support for all transmission speeds Standard (up to 100 kb/s) Fast (up to 400 kb/s) High Speed (up to 3,4 Mb/s) Arbitration and clock synchronization Support for multi-master systems Support for both 7-bit and 10-bit addressing formats on the I2C bus Interrupt generation All trademarks mentioned in this document are trademarks of their respective owners. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support SYMBOL datai(7:0) rd we address(1:0) cs rst clk Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. TYPE DESCRIPTION rst input Global reset address(1:0) input Processor address lines cs input Chip select we input Processor write strobe rd input Processor read strobe scli input I C bus clock line (input) sdai input I C bus data line (input) datai(7:0) input Processor data bus (input) datao(7:0) output Processor data bus (output) VHDL, Verilog source code called HDL Source sclo output I C bus clock line (output) sclhs output High-speed clock line (output) Encrypted, or plain text EDIF called Netlist sdao output I C bus data line (output) int output Processor interrupt line One Year license for PIN Global clock Single Design license for PINS DESCRIPTION input In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. int clk Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. sclhs sclo sdao scli sdai LICENSING Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. datao(7:0) 2 2 2 2 Encrypted Netlist only Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM IMPLEMENTATION Figure below shows the DI2CM IP Core block diagram. Figures below show the typical DI2CM implementations in system with Standard/Fast and High-speed devices. Slave Address address(1:0) datai(7:0) datao(7:0) cs we rd Shift Register CPU Interface Send Data VDD Input Filter sdai Output Register sdao RP RP SDA SCL Receive Data int RS Control Register Status Register Control Logic Timer Clock Generator RS RS sdai sda sdao Clock Synchronization rst clk Arbitration Logic RS Input Filter scli Output Register sclo Output Register sclhs open drain Slave device DI2CM scli scl sclo open drain sclhs CPU Interface - Performs the interface functions between DI2CM internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system. Control Logic - Manages execution of all commands sent via interface. Synchronizes internal data flow. 2 DI2CM implementation in I C-bus system with Standard/Fast devices only VDD RP RP SDA SCL Shift Register - Controls SDA line, performs data and address shifts during the data transmission and reception. Control Register - Contains five control bits used for performing all types of I2C Bus transmissions. Status Register - Contains seven status bits that indicates state of the I2C Bus and the DI2CM core. Clock Generator - Performs generation of the serial clock. Input Filter - Performs spike filtering. Clock Synchronization - Performs clock synchronization. RS RS RS sdai sdao sda open drain Slave device DI2CM scli sclo RS scl open drain current-source pull-up sclhs VDD 2 DI2CM implementation in I C-bus system with High-speed devices Arbitration Logic - Performs arbitration during operations in multi-master systems. Timer - Allows operation from a wide range of the input frequencies. It is programmed by an user before transmission and can be reprogrammed to change the SCL frequency. All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. PERFORMANCE The following table gives a survey about the Core area and performance in the LATTICE(R) devices after Place & Route (all key features have been included): Speed LUTs/PFUs Fmax grade ispXPGA -4 363/103 91 MHz ORCA 4 -3 387/ 57 66 MHz Core performance in LATTICE(R) devices Device - - Spike filtering User defined timing High-speed mode Fast mode - Standard mode - 10-bit addressing - - 7-bit addressing Arbitration - Clock synchronization Passive device interface CPU interface - Interrupt generation DI2CM DI2CS DI2CSB Slave operation Master operation 3.0 2.1 2.1 2 Design I C specification version The main features of each Digital Core Design I2C compliant cores have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. - 2 I C cores summary table All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved. CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND @ddccdd..ppll e-mail: iinnffoo@ tel. : +48 32 282 82 66 fax : +48 32 282 74 37 Field Office: Texas Research Park 14815 Omicron Dr. suite 100 San Antonio, TX 78245,USA e-mail: iinnffooU USS@ @ddccdd..ppll tel. : +1 210 422 8268 fax : +1 210 679 7511 Distributors: MTC - Micro Tech Components GmbH AM Reitweg 15 89407 Dillingen, GERMANY MTTC Ciinnffoo@ @m mttcc..ddee e-mail : M tel. : +49 9071 7945-0 fax : +49 9071 7945-20 Territory: Germany, Austria, Switzerland All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2003 DCD - Digital Core Design. All Rights Reserved.