General Description
The MAX8904 power-management IC provides a com-
plete power-supply solution for 2-cell Li+ handheld/Li-Poly
applications such as point-of-sale terminals, digital SLR
cameras, digital video cameras and ultra-mobile PCs.
The MAX8904 includes five step-down converters (1V2,
1V8, 3V3, 5V0, and ADJ) with internal MOSFETs and
+1%/-3% accurate output voltages for processor core,
memory, I/O, and other system power rail requirements.
LCD backlighting is supported by a WLED boost con-
verter that can provide 35mA for up to 8 WLEDs. This
boost converter is also configurable as a 6-bit program-
mable voltage source that can provide up to 63mA of
output current. A 500mA, internal MOSFET, current-lim-
ited switch (CLS), allows system designers to control
input power to external peripheral devices.
The MAX8904 controls an external n-MOSFET for input
overvoltage protection (13.5V, typ) and an external
p-MOSFET for reverse polarity protection (up to -28V) of
downstream circuits. System input current monitoring
for power management is facilitated by an on-board
current-sense amplifier (CSA) with differential inputs
and a 1.2V full scale, ground-referenced analog output.
A 400kHz, I2C interface supports output voltage setting
of the ADJ power rail and boost regulator (voltage
source mode), WLED current setting for the boost regu-
lator (WLED current regulator mode), GPIO control, and
enable/disable of ADJ, 5V0, boost regulator, CSA
blocks. The I2C interface also enables the host proces-
sor to read on-board fault status registers when inter-
rupted by the MAX8904 FLT pin under system fault
conditions.
An emergency shutdown input, SHDN allows convert-
ers preselected through I2C to turn off immediately
under power-fail conditions, thus saving valuable
firmware execution time. An uncommitted, active-low,
14V open-drain comparator (CMP) with a 1.25V internal
reference is also provided in the MAX8904. The
MAX8904 PWREN logic input turns on the 1V2, 1V8,
3V3, and 5V0 default power rails.
The MAX8904 is available in a 56-pin, 7mm x 7mm
TQFN package.
Applications
Point-of-Sale Terminals
Digital Video Cameras
Digital SLR Cameras
Ultra-Mobile PCs
Features
o3.4V to 13.2V Input Voltage Range
o1MHz, Up to 90% Efficient, Synchronous DC-DC
Step-Down Converters
oPower Converters 1V2, 1V8, and ADJ Operated
Out-of-Phase with Respect to 3V3 and 5V0
o667kHz Step-Up Converter Provides Up to 32V
Output for Driving Up to Eight WLEDs
oInternal Compensation on All Power Converters
oFast Line and Load Transient Responses
oInternal Soft-Start and Short-Circuit Protection on
All Power Converter Outputs
oInput Overvoltage and Reverse Polarity Protection
o250ms Fault Timer-Based Protection for Overload,
Short Circuit
oI2C Serial Interface for On/Off Control, Output
Voltage, WLED Current, GPIO Setting, Fault
Monitoring
o< 15µA Standby Current Over Operating Voltage
Range and Temperature
oCompact, 56-Pin, 7mm x 7mm TQFN Package
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
________________________________________________________________
Maxim Integrated Products
1
19-4497; Rev 0; 7/09
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
T = Tape and reel.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
MAX8904ETN+T -40°C to +85°C
56 THIN QFN-EP*
(7mm x 7mm)
Pin Configuration appears at end of data sheet.
1.2V, 600mA
1.8V, 975mA
1mA TO 63mA
UP TO 8 WLEDs
CS-
BSTLX
SDA
CS+
8-BIT GPIO
PORT
1V2LX
1V8LX
ADJLX2
GPIO7
GPIO0
PCS
OVGATE
VIN
SCL
PWREN
SHDN
FLT
LVROUT
LVRIN5V
RPGATE
LVRPWR
OVPWR
3V3LX
5V0LX
ADJLX1
3.3V, 1250mA
5V, 800mA
3.0V TO 5.067V,
1500mA
GND
CMPI
CMPO
VIN
VIN
CLSIN
CLSOUT
CSOUT
VEXT
VIN
MAX8904
Typical Operating Circuit
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
OVPWR to GND......................................................-0.3V to +30V
RPGATE to GND.....................................................-0.3V to +17V
OVPWR to RPGATE................................................-0.3V to +22V
OVGATE to CS+ .......................................................-0.3V to +6V
BSTFB to GND........................................................-0.3V to +40V
BSTLX to Exposed Pad (EP) ..................................-0.3V to +40V
BSTSW to BSTIN ....................................................-16V to +0.3V
LVRPWR, BSTIN, BSTSW, 1V2IN, 3V3IN, 1V8IN, ADJIN,
5V0IN, CMPO, CLSIN to EP...............................-0.3V to +16V
GPIO_ to EP..............................................................-0.3V to +6V
CS+, CS- to GND ...................................................-0.3V to +16V
CS+ to CS- ............................................................-0.3V to +0.3V
CLSOUT to GND....................................-0.3V to (VCLSIN + 0.3V)
LVROUT to GND.................................-0.3V to (VLVRPWR + 0.3V)
1V2FB, 1V8FB, 3V3FB, 5V0FB, ADJFB, REF, CSOUT,
CMPI to GND .................................-0.3V to (VLVRIN5V + 0.3V)
1V2BST to 1V2LX, 1V8BST to 1V8LX, 3V3BST to 3V3LX,
5V0BST to 5V0LX, ADJBST to ADJLX_................-0.3V to +6V
LVRIN5V, LVROUT, SHDN, PWREN, FLT, SDA, SCL,
GPIOPWR to GND ...............................................-0.3V to +6V
PCS to GND ...........................................-0.3V to (VBSTIN + 0.3V)
EP to GND .............................................................-0.3V to +0.3V
GPIOPWR to LVRIN5V..............................................-6V to +0.3V
LVROUT to LVRIN5V .............................................-0.3V to +0.3V
ADJLX_, 5V0LX, 3V3LX, 1V8LX, 1V2LX,
BSTLX (Note 1)........................................................±1.7ARMS
Continuous Power Dissipation (TA= +70°C)
56-Pin TQFN-EP Single-Layer PCB
(derate 27.8mW/°C above +70°C) ............................2222mW
56-Pin TQFN-EP Multilayer PCB
(derate 40mW/°C above +70°C) ...............................3200mW
Junction-to-Case Thermal Resistance (θJC) (Note 2) .....0.8°C/W
Junction-to-Ambient Thermal Resistance (θJA) (Note 2)
Single-Layer PCB ........................................................36°C/W
Multilayer PCB .............................................................25°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
COMMON BLOCKS
V_IN falling, OVP circuit not used 3.6 14
V_IN rising, OVP circuit not used 5.8 14
V_IN falling, OVP circuit used 3.6 12.8
Input Operating Supply Range V_IN
V_IN rising, OVP circuit used 5.8 13.2
V
Input Standoff Voltage VOVPWR 28 V
Standby Mode Supply Current
I_IN +
ILVRPWR +
ICS_
V_IN = 13.2V; all channels off 5.5 µA
Quiescent Supply Current
(CH7 + CH2 + CH3 + CH4 Only)
∆IQLVRPWR
+ I1V2IN +
I1V8IN +
I3V3IN +
I5V0IN +
I5V0FB
No switching, V1V2FB = 1.3V,
V1V8FB = 1.9V, V3V3FB = 3.4V,
V5V0FB = 5.1V
100 165 µA
Note 1: _LX pins have internal clamp diodes to _IN and EP. Applications that forward bias these diodes should take care not to exceed
the device’s power-dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
_______________________________________________________________________________________ 3
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IREF = 0µA 1.240 1.250 1.260
REF Output Voltage VREF IREF = 10µA 1.249 V
OSC Frequency fOSC 0.9 1 1.1 MHz
LVROUT Output Voltage 5.4V < VLVRPWR < 14V 4.9 5.1 5.3 V
VLVRPWR rising 5.3 5.55 5.8
LVRPWR Undervoltage Lockout
Threshold VLVRPWR falling 3.2 3.4 3.6 V
VLVRIN5V rising 3.45
LVRIN5V Undervoltage Lockout
Threshold VLVRIN5V falling 2.6 V
SHDN Input High Voltage VIH 3V < VLVRIN5V < 5.5V 1.6 V
SHDN Input Low Voltage VIL 3V < VLVRIN5V < 5.5V 0.5 V
S HD N P ul l up Resi stance to
LV RIN 5V 1MΩ
SHDN Pulldown Resistance
to GND 2MΩ
PWREN Input High Voltage VIH 3.4V < VLVRPWR < 14V 1.6 V
PWREN Input Low Voltage VIL 3.4V < VLVRPWR < 14V 0.5 V
PWREN Pulldown Resistance 1MΩ
PWREN Deglitch Delay Rising 10 µs
FLT Output-Voltage Low VFLT IFLT = 20mA 0 0.4 V
TA = +25°C 0.01 0.1
FLT Open-Drain Leakage Current VFLT = 5.5V TA = +85°C 0.1 µA
FAULT Timer Delay tFAULT 250 ms
Overtemperature Warning Flag Rising (Note 3) (bit D3 of register 0Dh) 110 120 130 °C
Overtemperature Warning Flag
Hysteresis 10 °C
Thermal Shutdown Latch
Threshold (Note 3) 140 152 165 °C
INPUT VOLTAGE PROTECTION
VOVPWR rising 3.75 4 4.25
OVPWR Undervoltage Lockout
Threshold VOVPWR falling 2.7 2.85 3.0 V
OVPWR_UVLO_Rising to
OVGATE Startup Delay tSTARTUP VOVPWR > VOVPWR_UVLO_RISING 32 ms
VOVPWR rising 13.3 13.65 14
OVP Threshold VOVP Hysteresis 0.17 V
OVGATE Charge Current IOV GATE _C H GVOVGATE = 7.2V 10 µA
OVGATE Discharge Resistance RDCHG VCS+ = 14.1V, VOVGATE = 15.1V 40 Ω
RPGATE Pulldown Resistor RRPGATE 50 kΩ
RPGATE Clamp Voltage VCLAMP 14V ≤ VOVPWR ≤ 28V 16 19 V
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CH1 (CURRENT-LIMITED SWITCH)
Current-Limited Switch
On-Resistance RONCLS ICLS = 400mA 200 300 425 m_
Current Limit ILIMCLS VCLSIN = 12V, VCLSOUT = 9V 450 600 mA
Overcurrent Fault Latch-Off Delay tOLFLT 250 ms
Fault Voltage VACT VCLSIN - VCLSOUT > 1V, 150mV hysteresis 1 V
Thermal Loop Threshold THMTH Current-limit-foldback temperature
threshold (Note 3) 110 120 130 °C
TA = +25°C 0.01 1
CLSOUT Leakage Current ICLSOUTLKG VCLSIN = 14V,
VCLSOUT = 0 TA = +85°C 0.1 µA
CH2 (1V8 STEP-DOWN CONVERTER)
Output Voltage V1V8FB No load 1.800 1.818 1.836 V
Operating Frequency f1V8LX 1 MHz
Load Regulation -2.5 %/A
Line Regulation V1V8IN = 3.4V to 14V 0.04 %/V
Idle-Mode Trip Level (Note 4) 150 mA
TA = +25°C -5 0.01 +5
1V8LX Leakage Current I1V8LXLKG V1V8LX = 0, 14V,
V1V8IN = 14V TA = +85°C 0.1 µA
TA = +25°C 0.01 0.1
1V8BST Leakage Current I1V8BSTLKG V1V8BST = 5V + V1V8IN TA = +85°C 0.1 µA
Low-Side Switch On-Resistance RONLS1V8 0.185 _
High-Side Switch On-Resistance RONHS1V8 0.27 _
High-Side Switch Current Limit ILIMHS1V8 1.3 1.43 1.6 A
Low-Side Switch Turn-Off Current 10 mA
Rising 94
Output-OK (1V8OK) Threshold (Bit D3 of register 0Fh) Falling 90 %
Soft-Start Rate 1 V/ms
LX Discharge Resistance PWREN = GND 350 _
Output-OK (1V8OK) Fault
Blanking Time After Soft-Start
Done
2ms
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CH3 (3V3 STEP-DOWN CONVERTER)
Output Voltage V3V3FB No load 3.349 3.383 3.416 V
Operating Frequency f3V3LX 1 MHz
Load Regulation -1.1 %/A
Line Regulation V3V3IN = 3.4V to 14V 0.04 %/V
Idle-Mode Trip Level (Note 4) 150 mA
TA = +25°C -5 0.01 +5
3V3LX Leakage Current I3V3LXLKG V3V3LX = 0, 14V,
V3V3IN = 14V TA = +85°C 0.1 µA
TA = +25°C 0.01 0.1
3V3BST Leakage Current I3V 3 BS TLKG V3V3BST = 5V + V3V3IN TA = +85°C 0.1 µA
Low-Side Switch On-Resistance RONLS3V3 0.185 _
High-Side Switch On-Resistance RONHS3V3 0.185 _
High-Side Switch Current Limit ILIMHS3V3 1.8 2 2.2 A
Low-Side Switch Turn-Off Current 10 mA
Rising 94
Output-OK (3V3OK) Threshold (Bit D4 of register 0Fh) Falling 90 %
Maximum Duty Cycle 95 %
Soft-Start Rate 1 V/ms
LX Discharge Resistance PWREN = GND 175 _
Output-OK (3V3OK) Fault
Blanking Time After Soft-Start
Done
2ms
CH4 (5V0 STEP-DOWN CONVERTER)
Output Voltage V5V0FB No load 5.000 5.050 5.100 V
Operating Frequency f5V0LX 1 MHz
Load Regulation -1.25 %/A
Line Regulation V5V0IN = 5.4V to 14V 0.04 %/V
Idle-Mode Trip Level (Note 4) 60 mA
TA = +25°C -5 +0.01 +5
5V0LX Leakage Current I5V0LXLKG V5V0LX = 0, 14V,
V5V0IN = 14V TA = +85°C 0.1 µA
TA = +25°C 0.01 0.1
5V0BST Leakage Current I5V 0B S TL KG V5V0BST = 5V + V5V0IN TA = +85°C 0.1 µA
Low-Side Switch On-Resistance RONLS5V0 0.27 _
High-Side Switch On-Resistance RONHS5V0 0.27 _
High-Side Switch Current Limit ILIMHS5V0 1.26 1.4 1.54 A
Low-Side Switch Turn-Off Current 10 mA
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Rising 94
Output-OK ( 5V 0O K) Threshold (Bit D5 of register 0Fh) Falling 90 %
S oft- S tar t Rate 1 V/ms
LX D i schar g e Resi stance PWREN = GND 350 _
Outp ut- OK ( 5V 0O K) Faul t Bl anki ng
Ti m e After S oft- S tar t D one 2ms
CH5 (ADJ STEP-DOWN CONVERTER)
Quiescent Supply Current
∆(IQLVRPWR
+ I5V0FB) +
IADJIN
No switching (CH5 only), VADJFB = 4V,
ADJSP register = 1Fh 65 100 µA
Output Voltage Adjust Range VADJFB 3 5.067 V
Operating Frequency fADJLX_ 1 MHz
Output Voltage Accuracy No load -1 0 +1 %
Load Regulation -0.75 %/A
Line Regulation VADJIN = 5.4V to 14V, VADJFB = 4V,
ADJSP register = 1Fh 0.04 %/V
Idle-Mode Trip Level (Note 4) 180 mA
TA = +25°C -5 0.01 +5
ADJLX_ Leakage Current IADJLX_ VADJLX = 0, 14V,
VADJIN = 14V TA = +85°C 0.1 µA
TA = +25°C 0.01 0.1
ADJBST Leakage Current IAD JB S TL KG VADJBST = 5V +
VADJIN TA = +85°C 0.1 µA
Low-Side Switch On-Resistance RONLSADJ 0.185 _
High-Side Switch On-Resistance RONHSADJ 0.185 _
High-Side Switch Current Limit ILIMHSADJ 2.7 3.0 3.3 A
Low-Side Switch Turn-Off Current 10 mA
Rising 94
Output-OK (ADJOK) Threshold (Bit D6 of register 0Fh) Falling 90 %
Soft-Start Rate 1 V/ms
LX Discharge Resistance ADJEN = logic 0 (bit D3 of register 07h) 175 _
Outp ut- OK ( AD JO K) Faul t Bl anki ng
Ti m e After S oft- S tar t D one 2ms
CH6 (BST STEP-UP CONVERTER)
Quiescent Supply Current ∆IQLVRPWR
+ IBSTIN
No switching (CH6 only), BSTIV = logic 1
(bit D4 of register 09h), VBSTFB = 14V,
BSTVSP register (0Ch) = 0Fh
100 µA
Current mode 17.4 33.5
Typical Output Voltage Range VBSTFB Voltage mode (typical DAC codes) 12.5 18.7 V
Overvoltage Protection Range Current mode (typical DAC codes) 17.4 36 V
Overvoltage Protection Accuracy Current mode, VBSTFB = 26.7V -3 +3 %
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Voltage Accuracy V ol tag e m od e, BS TV S P r eg i ster ( 0C h) = 10h -3 +3 %
Operating Frequency fBSTLX 667 kHz
Minimum Duty Cycle 10 %
Maximum Duty Cycle 90 93 97 %
TA = +25°C 31.04 32 32.96
PCS Current Accuracy IPCS BSTCSP register
(0Bh) = 20h TA = -40°C to +85°C 30.4 33.6 mA
TA = +25°C 0.01 1
PCS Leakage Current IPCSLKG VPCS = 0 to
LVRIN5V TA = +85°C 0.1 µA
TA = +25°C 0.01 5
BSTSW Leakage Current IBSTSWLKG
V
B S T S W = 0, V
B S T IN
= 14V , BS TE N =
l og i c 0 ( b i t D 4 of
Re
g
i ster 09h)
TA = +85°C 0.1 µA
TA = +25°C 0.01 5
BSTLX Leakage Current IBSTLXLKG VBSTLX = 0 to 36V TA = +85°C 1 µA
BSTSW Switch On-Resistance RONBSTSW 0.1 _
BSTLX Switch On-Resistance RONBSTLX 0.3 _
BSTSW Switch Short-Circuit
Current Limit ILIMBSTSW 1.35 A
BSTLX Switch Current Limit ILIMBSTLX 1.13 A
Rising, voltage mode
only 95
Output Voltage OK (BSTOK)
Threshold
(Bit D7 of register
0Fh) Falling, voltage mode
only 90
%
Soft-Start Time Voltage mode and current mode 4.096 ms
BSTOK Fault Blanking Time After
Soft-Start Done Voltage mode and current mode 1.024 ms
CH7 (1V2 STEP-DOWN CONVERTER)
Output Voltage V1V2FB No load 1.200 1.212 1.224 V
Operating Frequency f1V2LX 1 MHz
Load Regulation -2.5 %/A
Line Regulation V1V2IN = 3.4V to 14V 0.04 %/V
Idle-Mode Trip Level (Note 4) 200 mA
TA = +25°C -5 0.01 +5
1V2LX Leakage Current I1V2LXLKG V1V2LX = 0, 14V,
V1V2IN = 14V TA = +85°C 0.1 µA
TA = +25°C 0.01 0.1
1V2BST Leakage Current I1 V 2 BS TL K GV1V2BST = 5V +
V1V2IN TA = +85°C 0.1 µA
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
8 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Low-Side Switch On-Resistance RONLS1V2 0.185 _
High-Side Switch On-Resistance RONHS1V2 0.27 _
High-Side Switch Current Limit ILIMHS1V2 1.08 1.2 1.32 A
Low-Side Switch Turn-Off Current 10 mA
Rising 94
Output-OK (1V2OK) Threshold (Bit D2 of register
0Fh) Falling 90 %
Soft-Start Rate 1 V/ms
LX Discharge Resistance PWREN = GND 175 _
Output-OK (1V2OK) Fault
Blanking Time After Soft-Start
Done
2ms
CSA (CURRENT-SENSE AMPLIFIER)
Differential Input Range VCS+ - VCS- VLVRPWR = VCS- = 5.4V to 14V 0 60 mV
Maximum CSOUT Output
Capacitive Load CLOAD (Note 3) 50 pF
CSOUT Pulldown Resistor RPD 350 k_
Bandwidth 150 kHz
Common-Mode Voltage Range VCMR 5.4 14 V
Common-Mode Rejection CMR VLVRPWR = VCS- = 5.4V to 14V,
VCS+ = VCS- + 24mV 100 dB
CS_ Input Current (ICS- + ICS+)V
LVRPWR = VCS- = VCS+ = 5.4V to 13.2V 2 4 µA
CS+/CS- Input-Referred Offset VIOCS Gain = 20, VCS+ = VCS- = VLVRPWR =
5.4V to 14V -2.0 0 +2.0 mV
VCS+ - VCS- = 48mV,
gain = 20 15
VCS+ - VCS- = 24mV,
gain = 20 25
CSOUT Voltage Accuracy VLVRPWR = 5.4V
to 14V
VCS+ - VCS- = 24mV,
gain = 40 15
%
CSOUT Load Current ICSOUT VCS+ - VCS- = 48mV, gain = 20 20 µA
Rising,
CSFLGEN = logic 1 0.912 0.96 1.008
CS Flag (BIT D1 of Register 0Dh) (Bit D6 of register
09h) Falling,
CSFLGEN = logic 1 0.862 0.91 0.958
V
Start-Up Time 60 µs
CSOUT Clamp Voltage V
C S OU TC LP 1.215 1.242 1.270 V
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
_______________________________________________________________________________________ 9
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
GPIO LOGIC INPUT/OUTPUT
Rising 2.8
GPIOPWR UVLO Falling 2.5 V
Rising 0.7 x
VGPIOPWR
Input Threshold
Falling 0.25 x
VGPIOPWR
V
Output-Voltage Low IGPIO_ = -20mA, open-drain output 0.5 V
TA = +25°C 0.01 0.1
Open-Drain Leakage Current VGPIO_ = 5.5V TA = +85°C 0.1 µA
Minimum Input Data Setup Time tDS 100 ns
Minimum Input Data Hold Time tDH 1µs
Minimum Delay to Output
Data Valid 5µs
Input mode 1 M_
Pullup Resistor from GPIO_ to
GPIOPWR VGPIOPWR = 5V Open-drain output
mode 10 k_
GPIO_ PWM Clock Frequency 244 Hz
OPEN-DRAIN COMPARATOR
CMPI Input Current ICMPI VCMPI = 600mV 0.01 µA
CMPI Threshold VCMPI Rising 1.2125 1.25 1.2875 V
CMPI Hysteresis VCMPIHYS 40 mV
CMPO Delay t
CMPO 25mV overdrive 5 µs
Output-Voltage Low V
CMPO I
CMPO = -20mA 0.4 V
TA = +25°C 0.01 1.0
Open-Drain Leakage Current ICMPOLKG V
CMPO = 14V TA = +85°C 0.1 µA
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
10 ______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V_IN = 7.2V, EP = GND, VPWREN = 5V, _LX unconnected, CREF = 0.1µF; when V_IN is specified, it implies all _IN pins; TA= -40°C to
+85°C. Typical values are at TA= +25°C, unless otherwise noted. Limits are 100% production tested at TA= +25°C. Limits over the
operating temperature range are guaranteed by design and characterization.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I2C SERIAL INPUT/OUTPUT AND LOGIC
Logic Input Low Voltage VIL 0.8 V
Logic Input High Voltage VIH 2.0 V
Input Leakage Current ILKG -1 +1 µA
Output-Voltage Low VOL ISINK = 3mA 0.4 V
Input/Output Capacitance CI/O 10 pF
Serial-Clock Frequency fSCL 400 kHz
Clock Low Period tLOW 1.3 µs
Clock High Period tHIGH 0.6 µs
BUS Free Time tBUF 1.3 µs
START Setup Time tSU:STA 0.6 µs
START Hold Time tHD:STA 0.6 µs
STOP Setup Time tSU:STO 0.6 µs
Data-In Setup Time tSU:DAT 100 ns
Data-In Hold Time tHD:DAT 0 900 ns
Receive SCL/SDA Minimum Rise
Time tR(Note 5) 20 + 0.1
x CBUS ns
Receive SCL/SDA Maximum Rise
Time tR(Note 5) 300 ns
Receive SCL/SDA Minimum Fall
Time tF(Note 5) 20 + 0.1
x CBUS ns
Receive SCL/SDA Maximum Fall
Time tF(Note 5) 300 ns
Transmit SDA Fall Time tFCBUS = 400pF 20 + 0.1
x CBUS 300 ns
Pulse Width of Spike Suppressed tSP (Note 6) 50 ns
SEQUENCER
POWER-UP SEQUENCING
1V8 VOK to 3V3 Start Delay 3.6 ms
POWER-DOWN SEQUENCING
3V3 Disable to 1V8 Disable Delay 15 ms
1V8 Disable to 1V2 Disable Delay 15 ms
Note 3: Not tested. Design guidance only.
Note 4: The idle-mode current threshold is the transition point between fixed-frequency PWM operation and idle-mode operation. The
specification is given in terms of output load current for inductor values specified in Figure 1.
Note 5: CBUS = total capacitance of one bus line in pF. Rise and fall times are measured between 0.1 x VBUS and 0.9 x VBUS.
Note 6: Input filters on SDA and SCL suppress noise spikes < 50ns.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________
11
Typical Operating Characteristics
(VIN = 7.2V, VPWREN = 3V, SHDN unconnected, VADJ = 4V, CREF = 0.1µF, circuit of Figure 1, TA= +25°C, unless otherwise noted.)
REFERENCE VOLTAGE vs. TEMPERATURE
TEMPERATURE (NC)
REFERENCE VOLTAGE (V)
MAX8904 toc01
-40 -15 10 35 60 85
1.247
1.248
1.249
1.250
1.251
LVROUT VOLTAGE vs. TEMPERATURE
TEMPERATURE (NC)
LVROUT VOLTAGE (V)
MAX8904 toc02
-40 -15 10 35 60 85
5.060
5.065
5.070
5.075
5.080
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE
INPUT VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT (uA)
MAX8904 toc03
2468101214
0
5
10
15
20
25
30
VPWREN = 0V
INPUT CURRENT vs. INPUT VOLTAGE
(CH2 + CH3 + CH7 SWITCHING, NO LOAD)
INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENT (mA)
MAX8904 toc04
3 6 9 12 15
0
0.3
0.5
0.8
1.0
1.3
1.5
1V2, 1V8, AND 3V3 ARE ON
INPUT CURRENT vs. TEMPERATURE
(CH2 + CH3 + CH7, SWITCHING, NO LOAD)
TEMPERATURE (NC)
NO-LOAD SUPPLY CURRENT (mA)
MAX8904 toc05
-40 -15 10 35 60 85
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1V2, 1V8, AND 3V3 ARE ON
STARTUP SEQUENCING WAVEFORMS
MAX8904 toc06
VPWREN 5V/div
0V 3V
0V
0V
0V
0V
2V/div
2V/div
2V/div
2V/div
V1V2
V1V8
V3V3
V5V0
2ms/div
1.2V
1.8V
3.3V
5V
SHUTDOWN SEQUENCING WAVEFORMS
MAX8904 toc07
VPWREN
V1V2
V1V8
V3V3
10ms/div
5V/div
2V/div
2V/div
2V/div
1.2V
0V
0V
0V
0V
1.8V
3.3V
3V
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN = 7.2V, VPWREN = 3V, SHDN unconnected, VADJ = 4V, CREF = 0.1µF, circuit of Figure 1, TA= +25°C, unless otherwise noted.)
SHUTDOWN SEQUENCING WAVEFORMS
MAX8904 toc08
VPWREN
V3V3
V5V0
VADJ
4ms/div
5V/div
2V/div
2V/div
2V/div
5.0V
2.3V
0V
3V
4V
0V
0V
0V
EFFICIENCY vs. INPUT VOLTAGE (1V8)
INPUT VOLTAGE (V)
EFFICIENCY (%)
MAX8904 toc09
36 91215
70
75
80
85
90
95
100
IOUT = 600mA
EFFICIENCY vs. OUTPUT CURRENT (1V8)
OUTPUT CURRENT (mA)
EFFICIENCY (%)
MAX8904 toc10
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
1V8 LOAD TRANSIENT RESPONSE
(10mA TO 485mA)
MAX8904 toc11
500mA/div
50mV/div
IOUT
V1V8
AC RIPPLE
200µs/div
485mA
10mA
1V8 LOAD TRANSIENT RESPONSE
(500mA TO 1000mA)
MAX8904 toc12
20mV/div
500mA/div
V1V8
AC RIPPLE
IOUT
20µs/div
1000mA
500mA
OUTPUT VOLTAGE LOAD
REGULATION (1V8)
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
MAX8904 toc13
1.70
1.74
1.78
1.82
1.86
1.90
1 10 100 1000
VIN = 7.2V
VIN = 3.4V
VIN = 12V
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________
13
Typical Operating Characteristics (continued)
(VIN = 7.2V, VPWREN = 3V, SHDN unconnected, VADJ = 4V, CREF = 0.1µF, circuit of Figure 1, TA= +25°C, unless otherwise noted.)
EFFICIENCY vs. INPUT VOLTAGE (3V3)
INPUT VOLTAGE (V)
EFFICIENCY (%)
MAX8904 toc14
36 91215
60
70
80
90
100
IOUT = 800mA
EFFICIENCY vs. OUTPUT
CURRENT (3V3)
OUTPUT CURRENT (mA)
EFFICIENCY (%)
MAX8904 toc15
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000 10,000
3V3 LOAD TRANSIENT RESPONSE
(10mA TO 625mA)
MAX8904 toc16
500mA/div
50mV/div
IOUT
V3V3
AC RIPPLE
200µs/div
10mA
625mA
3V3 LOAD TRANSIENT RESPONSE
(625mA TO 1250mA)
MAX8904 toc17
1A/div
20mV/div
IOUT
I3V3
AC RIPPLE
200µs/div
625mA
1250mA
OUTPUT VOLTAGE LOAD
REGULATION (3V3)
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
MAX8904 toc18
3.28
3.32
3.36
3.40
3.44
1 10 100 1000 10,000
VIN = 7.2V
VIN = 12V
EFFICIENCY vs. INPUT VOLTAGE (5V0)
INPUT VOLTAGE (V)
EFFICIENCY (%)
MAX8904 toc19
5 7 9 11 13 15
70
75
80
85
90
95
100
IOUT = 650mA
EFFICIENCY vs. OUTPUT CURRENT (5V0)
OUTPUT CURRENT (mA)
EFFICIENCY (%)
MAX8904 toc20
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
14 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN = 7.2V, VPWREN = 3V, SHDN unconnected, VADJ = 4V, CREF = 0.1µF, circuit of Figure 1, TA= +25°C, unless otherwise noted.)
5V0 LOAD TRANSIENT RESPONSE
(10mA TO 400mA)
MAX8904X toc21
50mV/div
500mA/div
IOUT
V5V0
AC RIPPLE
200Fs/div
10mA
400mA
5V0 LOAD TRANSIENT RESPONSE
(400mA TO 800mA)
MAX8904X toc22
20mV/div
500mA/div
IOUT
V5V0
AC RIPPLE
200µs/div
400mA
800mA
OUTPUT VOLTAGE LOAD REGULATION (5V0)
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
MAX8904 toc23
4.92
4.97
5.02
5.07
5.12
1 10 100 1000
VIN = 5.5V
VIN = 12V
VIN = 7.2V
EFFICIENCY vs. INPUT VOLTAGE (ADJ)
INPUT VOLTAGE (V)
EFFICIENCY (%)
MAX8904 toc24
5 7 9 11 13 15
70
75
80
85
90
95
100
IOUT = 1000mA
VADJ = 4V
EFFICIENCY vs. OUTPUT CURRENT (ADJ)
OUTPUT CURRENT (mA)
EFFICIENCY (%)
MAX8904 toc25
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000 10,000
PULSE-SKIPPING MODE ENABLED
ADJ LOAD TRANSIENT RESPONSE
(200mA TO 2000mA TO 200mA)
MAX8904X toc26
50mV/div
1A/div
IOUT
VADJ
AC RIPPLE
200µs/div
200 mA
2000mA
ADJ VOLTAGE vs. LOAD CURRENT (ADJ)
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
MAX8904 toc27
3.90
3.95
4.00
4.05
4.10
1 10 100 1000
VIN = 7.2V
VIN = 12V
VIN = 5.4V
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________
15
Typical Operating Characteristics (continued)
(VIN = 7.2V, VPWREN = 3V, SHDN unconnected, VADJ = 4V, CREF = 0.1µF, circuit of Figure 1, TA= +25°C, unless otherwise noted.)
ADJ STARTUP RESPONSE
MAX8904X toc28
1A/div
2V/div
IOUT
VADJ
1ms/div
0V
4V
0A
1A
ADJ SHUTDOWN RESPONSE
MAX8904X toc29
1A/div
2V/div
IOUT
VADJ
1ms/div
0V
0A
4V
1A
EFFICIENCY vs. LED CURRENT (BST)
LED CURRENT (mA)
EFFICIENCY (%)
MAX8904 toc30
0 6 12 18 24 30
40
50
60
70
80
90
100
4 LEDS
6 LEDS
8 LEDS
LED CURRENT vs. TEMPERATURE
TEMPERATURE (NC)
LED CURRENT (mA)
MAX8904 toc31
-40 -15 10 35 60 85
20.20
20.25
20.30
20.35
20.40
ILED = 20mA
BST SWITCHING FREQUENCY
vs. TEMPERATURE
TEMPERATURE (NC)
SWITCHING FREQUENCY (MHz)
MAX8904 toc32
-40 -15 10 35 60 85
0.5
0.6
0.7
0.8
0.9
BST STARTUP RESPONSE
(CURRENT MODE)
MAX8904X toc33
20mA/div
10V/div
ILED
VBST
2s/div
8 WLEDS
0mA
30mA
0V
EFFICIENCY vs. INPUT VOLTAGE
(BST VOLTAGE MODE)
INPUT VOLTAGE (V)
EFFICIENCY (%)
MAX8904 toc34
5 7 9 11 13 15
70
75
80
85
90
95
100
VOUT = 13.2V
IOUT = 50mA
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
16 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN = 7.2V, VPWREN = 3V, SHDN unconnected, VADJ = 4V, CREF = 0.1µF, circuit of Figure 1, TA= +25°C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT
(BST VOLTAGE MODE)
LOAD CURRENT (mA)
EFFICIENCY (%)
MAX8904 toc35
0
10
20
30
40
50
60
70
80
90
100
110100
VOUT = 13.2V
BST LOAD TRANSIENT RESPONSE
(10mA TO 60mA, VOLTAGE MODE)
MAX8904X toc36
25mA/div
100mV/div
IOUT
VBST
AC RIPPLE
200µs/div
10mA
60mA
BST VOLTAGE vs. LOAD CURRENT
LOAD CURRENT (mA)
OUTPUT VOLTAGE (V)
MAX8904 toc37
13.197
13.198
13.199
13.200
13.201
13.202
13.203
1 10 100
VIN = 12V
VIN = 5.4V
VIN = 7.2V
EFFICIENCY vs. INPUT VOLTAGE (1V2)
INPUT VOLTAGE (V)
EFFICIENCY (%)
MAX8904 toc38
3 6 9 12 15
70
75
80
85
90
95
100
IOUT = 300mA
EFFICIENCY vs. OUTPUT CURRENT (1V2)
OUTPUT CURRENT (mA)
EFFICIENCY (%)
MAX8904 toc39
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
MAX8904 toc40
200mA/div
50mV/div
IOUT
V1V2
AC RIPPLE
200Fs/div
1V2 LOAD TRANSIENT RESPONSE
(1mA TO 300mA)
1mA
300mA
1V2 LOAD TRANSIENT RESPONSE
(300mA TO 600mA)
MAX8904X toc41
500mA/div
20mV/div
IOUT
V1V2
AC RIPPLE
200Fs/div
300mA
600mA
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________
17
Typical Operating Characteristics (continued)
(VIN = 7.2V, VPWREN = 3V, SHDN unconnected, VADJ = 4V, CREF = 0.1µF, circuit of Figure 1, TA= +25°C, unless otherwise noted.)
OUTPUT VOLTAGE LOAD REGULATION (1V2)
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
MAX8904 toc42
1.18
1.20
1.22
1.24
1.26
1.28
1 10 100 1000
VIN = 7.2V
VIN = 3.4V
VIN = 12V
CLS STARTUP RESPONSE
(NO LOAD)
MAX8904X toc43
VCLSIN
ICLSIN
ICLSOUT
VCLSOUT
20ms/div
0V
12V
10V/div
0V
500mA/div
500mA/div
10V/div
CCLSOUT = 2000µF
CLS STARTUP AND SHUTDOWN RESPONSE
(425mA LOAD)
MAX8904X toc44
VCLSIN
ICLSIN
ICLSOUT
VCLSOUT
200ms/div
0V
12V
10V/div
0V
500mA/div
500mA/div
10V/div
CCLSOUT = 2000µF
CLS SHORT-CIRCUIT PROTECTION
MAX8904X toc45
VCLSOUT
ICLSIN
ICLSOUT
100ms/div
VFLT
3.3V
0V
0V
12V
0mA
0mA
10V/div
500mA/div
500mA/div
5V/div
OPEN-DRAIN COMPARATOR
MAX8904X toc46
VCMPI
10µs/div
VCMPO
0V
0V
0V
7.2V
7.2V
1.3V
1V/div
5V/div
CSOUT VOLTAGE vs. TEMPERATURE
(GAIN = 20, VCS+ - VCS- = 48mV)
TEMPERATURE (NC)
CSOUT VOLTAGE (V)
MAX8904 toc47
-40 -15 10 35 60 85
0.925
0.930
0.935
0.940
0.945
0.950
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
18 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(VIN = 7.2V, VPWREN = 3V, SHDN unconnected, VADJ = 4V, CREF = 0.1µF, circuit of Figure 1, TA= +25°C, unless otherwise noted.)
CSOUT VOLTAGE vs. TEMPERATURE
(GAIN = 40, VCS+ - VCS- = 24mV)
OUTPUT VOLTAGE (V)
MAX8904 toc48
-40 -15 10 35 60 85
0.925
0.930
0.935
0.940
0.945
0.950
TEMPERATURE (NC)
CSA OUTPUT VOLTAGE
vs. INPUT VOLTAGE
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
MAX8904 toc49
5 7 9 11 13 15
0.90
0.92
0.94
0.96
0.98
1.00
GAIN = 20
VCS+ - VCS- = 48mV
CSA OUTPUT VOLTAGE
vs. INPUT VOLTAGE
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
MAX8904 toc50
5 7 9 11 13 15
0.90
0.92
0.94
0.96
0.98
1.00
GAIN = 40
VCS+ - VCS- = 24mV
OVERVOLTAGE PROTECTION
MAX8904 toc51
5V/div
5V/div
5V/div
5V/div
VOVPWR
VOVGATE
V_IN
3.3V
12V
12V
14V
14.5V
VFLT
10ms/div
REVERSE-POLARITY PROTECTION
MAX8904 toc52
10V/div
5V/div
5V/div
100mA/div
VEXT
VRPGATE
VIN
IEXT
10ms/div
0V
0V
0V
-28V
MAX8904 toc53
2V/div
5V/div
5V/div
5V/div
V5VO
VADJ
VBST
4ms/div
SHDN FUNCTIONALITY
VSHDN 0V
0V
0V
0V
3V
5V
4V
13.2V
MAX8904 toc54
5V/div
5V/div
5V/div
5V/div
VGPIO5
VGPIO6
VGPIO7
2ms/div
GPIO PWM OPERATION
VGPIO4
REGISTER 05h = 20h
REGISTER 06h = 40h
REGISTER 05h = 80h
REGISTER 06h = 100h
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 19
Pin Description
PIN NAME FUNCTION
1 CSOUT Output Voltage of the Current-Sense Amplifier. CSOUT is referenced to analog ground, GND. Its full-
scale voltage is 1.2V for 60mV differential input voltage at CS+ and CS-.
2 RPGATE
External p-MOSFET Gate Control Node for Reverse Polarity Protection. Internal reverse polarity sense
circuitry controls the gate so that power is applied to the following n-MOSFET stage if and only if
proper (positive) polarity of power is applied. If reverse polarity input power is applied, the p-MOSFET
is kept off to protect the n-MOSFET stage and the IC.
3 OVPWR
Supply Voltage and Overvoltage Detection Node for the Overvoltage Protection Circuitry. Connect
OVPWR to system external supply in the absence of reverse polarity protection
p-MOSFET. When reverse polarity protection p-MOSFET is used, connect OVPWR to the source of
the reverse polarity protection p-MOSFET.
4 OVGATE
External n-MOSFET Gate Control Node for Input Overvoltage Protection. The external
n-MOSFET is turned on as long as VOVPWR is less than 13.3V. The external n-MOSFET is immediately
turned off by pulling OVGATE low, when VOVPWR exceeds 13.3V, and the IC asserts the FLT output.
The external n-MOSFET is turned back on when VOVPWR falls below OVP threshold. Note that the I2C
interface is always alive, is independent of the overvoltage protection circuit, and turns off only when
VLVROUT falls below 3.4V.
5 ADJBST ADJ Step-Down Converter Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor between
ADJBST and ADJLX_.
6, 7 ADJLX1,
ADJLX2
ADJ Step-Down Converter Switching Node. Connect an inductor between ADJLX_ and the output of
the ADJ converter. Connect a 0.1µF ceramic capacitor between ADJLX_ and ADJBST. Connect
ADJLX1 to ADJLX2.
8 ADJIN ADJ Step-Down Converter Supply Input. Bypass ADJIN to power ground with a 4.7µF ceramic
capacitor. Connect ADJIN to the input power supply node, VIN.
9 ADJFB AD J S tep - D ow n C onver ter Feed b ack Inp ut. C onnect tw o 22µF or a 47µF outp ut cer am i c cap aci tor fr om
the outp ut i nd uctor to p ow er g r ound , and r oute the sense tr ace to AD JFB.
10 REF 1.25V Reference Output. Bypass REF to GND with a 0.1µF ceramic capacitor. REF is internally pulled
to GND in shutdown.
11 GND Ground. Connect GND to the ground plane. Connect the ground plane with a short wide connection
to the exposed pad (EP).
12 LVRIN5V
Power Supply for the Internal Analog Circuitry. It is derived from an internal low-voltage regulator
output, LVROUT. Connect a 10_ resistor between LVRIN5V and LVROUT. Bypass LVRIN5V to GND
with a 1.0µF or greater ceramic capacitor.
13 LVROUT
Internal Low-Voltage Regulator Output Bootstrapped to 5V0 Step-Down Converter Output. LVROUT is
the power supply for the internal drive circuitry. LVROUT provides a 5V output when PWREN is pulled
high. Bypass LVROUT to power ground with a 1.0µF or greater ceramic capacitor.
14 LVRPWR Internal 5V Low-Voltage Linear Regulator Input Supply. Decouple LVRPWR to power ground with a
0.22µF or greater ceramic capacitor. Connect LVRPWR to the input power-supply node, VIN.
15 5V0FB 5V0 Step-Down Converter Feedback Input. Connect a 22µF output ceramic capacitor from the output
inductor to power ground, and route the sense trace to 5V0FB.
16 5V0IN 5V0 Step-Down Converter Input Supply. Bypass 5V0IN to power ground with a 10µF ceramic
capacitor. Connect 5V0IN to the input power-supply node, V
IN
.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
20 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
17 5V0LX
5V0 Step-Down Converter Switching Node. Connect an inductor between 5V0LX and the output of
the 5V0 converter. Connect a 0.1µF capacitor between 5V0LX and 5V0BST.
18 5V0BST
5V0 Step-Down Converter Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor
between 5V0BST and 5V0LX.
19 GPIOPWR
Power Supply for GPIO Inputs and Outputs. GPIOPWR can be connected to a supply voltage from
3.0V up to 5.5V. Correct a 1µF ceramic capacitor between GPIOPWR and GND.
20–27 GPIO0–
GPIO7
I2C-Controlled GPIO Port. GPIO_ can be configured as:
•Schmitt-trigger inputs with internal 1M pullup resistor to GPIOPWR
•Open-drain outputs with internal 10k pullup resistor off-state and capable of sinking 20mA
current from GPIOPWR
•Open-drain outputs with high-impedance off-state and capable of sinking 20mA current from
GPIOPWR
•High-impedance outputs
The default configuration during power-up is Schmitt-trigger inputs until reconfigured through the
I2C interface. The GPIO block has a dedicated power input supply, GPIOPWR. The MAX8904
samples its GPIO0 at GPIOPWR power-up and selects one of two internal hardwired slave
addresses for I2C addressing.
28 CMPO Active-Low, Open-Drain Output of an Uncommitted Comparator. CMPO can be pulled up to 14V.
29 CMPI Comparator Input. Internal reference voltage is 1.25V.
30 3V3FB
3V3 Step-Down Converter Feedback Input. Connect two 22µF or a 47µF output ceramic capacitor
from the inductor to power ground, and route the sense trace to 3V3FB. The 3V3FB provides power
to the I2C registers. Connect the SDA and SCL pullup resistors to 3V3FB.
31 3V3IN
3V3 Step-Down Converter Input Supply. Connect a 4.7µF ceramic capacitor between 3V3IN and
power ground. Connect 3V3IN to the input power supply node, VIN.
32 3V3LX
3V3 Step-Down Converter Switching Node. Connect an inductor between 3V3LX and the output of
the 3V3 converter. Connect a 0.1µF ceramic capacitor between 3V3LX and 3V3BST.
33 3V3BST
3V3 Step-Down Converter Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor
between 3V3BST and 3V3LX.
34 SCL I2C Serial-Clock Input
35 SDA I2C Serial-Data Input/Output. Data is read on the rising edge of SCL.
36 1V2BST
1V2 Step-Down Converter Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor
between 1V2BST and 1V2LX.
37 1V2LX
1V2 Step-Down Converter Switching Node. Connect an inductor between 1V2LX and the output of
the 1V2 converter. Connect a 0.1µF ceramic capacitor between 1V2LX and 1V2BST.
38 1V2IN
1V2 Step-Down Converter Input Supply. Bypass 1V2IN to power ground with a 4.7µF ceramic
capacitor. Connect 1V2IN to the input power supply node, VIN.
39 1V2FB
1V2 Step-Down Converter Feedback Input. Connect two 22µF or a 47µF output ceramic capacitor
from the inductor to power ground, and route sense trace to 1V2FB. 1V2FB is sampled at power-up
to determine if the 1V2 step-down converter is used or not. See the Power-Up/Down Sequencing for
1V2, 1V8, 3V3, and 5V0 Supplies section. Pull 1V2FB to LVRIN5V to configure the IC for operation
without the 1V2 step-down converter.
40 FLT Active-Low, Open-Drain Fault Output. Low FLT indicates a fault condition. See the Fault Handling
section for details.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 21
Pin Description (continued)
PIN NAME FUNCTION
41 SHDN
Shutdown Input. When SHDN is pulled low, the power converters that are selected in the SHUTDOWN
register, if currently active, are immediately shut down. The IC recognizes a valid signal on SHDN
only if 1V2, 1V8, and 3V3 supplies are in regulation.
42 PWREN
Enable Input. When PWREN is driven high, the LVROUT regulator is turned on, and the 1V2, 1V8, 3V3,
and 5V0, are turned on with correct sequencing depending on the status of 1V2FB at LVR power-up.
When PWREN is pulled low, the MAX8904 turns off all converters and internal blocks and goes into
low-power standby mode.
43 TEST Test Pin. Leave as no connection. Do not connect power or ground.
44 1V8FB
1V8 Step-Down Converter Feedback Input. Connect a 22µF output ceramic capacitor from the output
inductor to power ground, and route the sense trace to 1V8FB.
45 1V8IN
1V8 Step-Down Converter Input Supply. Bypass 1V8IN to power ground with a 4.7µF ceramic
capacitor. Connect the 1V8IN to the input power supply node, VIN.
46 1V8LX
1V8 Step-Down Converter Switching Node. Connect an inductor between 1V8LX and the output of 1V8
converter. Connect a 0.1µF ceramic capacitor between 1V8LX and 1V8BST.
47 1V8BST
1V8 Step-Down Converter Boost Capacitor Connection. Connect a 0.1µF ceramic capacitor between
1V8BST and 1V8LX.
48 BSTLX
BST Open-Drain Switch Node. Connect an inductor between BSTSW and BSTLX. BSTLX is high
impedance in standby mode.
49 BSTSW
BST True Shutdown Switch Terminal. Connect an inductor between BSTSW and BSTLX. Bypass
BSTSW to power ground with a 2.2µF ceramic capacitor.
50 BSTIN
BST Step-Up Converter Supply Input. Bypass BSTIN to power ground with a 1µF ceramic capacitor.
Connect BSTIN to the input power supply node, VIN.
51 BSTFB
BST Step-Up Converter Feedback Input. Connect BSTFB to the output ceramic capacitor of the step-up
converter. Use a 1µF capacitor in current regulator mode and use a 10µF capacitor for voltage
regulator mode.
52 PCS
LED Current Sink. When the BST step-up converter is in current-mode operation, connect the cathode
of WLED string to PCS and the anode of the WLED string to the output capacitor. In voltage mode, PCS
must be connected to GND.
53 CLSOUT
Current-Limited Switch Output. Turn on the load switch through the I2C interface to connect the switch
input, CLSIN, to the load.
54 CLSIN Current-Limited Switch Input. Connect CLSIN to the input power supply node, VIN.
55 CS- Current-Sense Amplifier Inverting Input. Connect CS- to the load side of current-sense resistor.
56 CS+ Current-Sense Amplifier Noninverting Input. Connect CS+ to the supply-side of current-sense resistor.
— EP
Exposed Pad. Power grounds and ground plane must be star-connected to the EP. All large currents
from converters flow through the exposed pad that also acts as a heat sink. A large number of vias
are needed to connect EP to board power ground plane.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
22 ______________________________________________________________________________________
LVROUT LVRIN5V
GND
INTERNAL OSC
1MHz ±10%
THERMAL FLAG
AND SHUTDOWN
LOGIC CENTER
SERIAL I/O, OUTPUT VOLTAGE PROGRAMMING,
ON/OFF CONTROL, SOFT-START
FAULT MANAGEMENT
SDA
SCL
5V0
REF
PWREN
FLT
CH4 5V0
STEP-DOWN
CONVERTER
(800mA MAX)
5V0LX
5V0IN
5V0BST
5V0FB
C23
22µF
VIN
VIN
VIN
CH6 BST
STEP-UP
CONVERTER
667kHz, 12.8V TO
32V, 1.12W
OUTPUT POWER,
I2C PROGRAMMABLE
BSTLX
BST
BSTSW
BSTIN
1.25V
PCS
CMPI
CMPO
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO0
8-BIT I2C
PROGRAMMABLE I/O
CS+
CS-
CSOUT
(0 TO 1.2V)
LEVEL
SHIFT
R2
15mΩ
SHDN
INTERNAL
CHIP SUPPLY
LINEAR
REGULATOR
BSTFB
OVP SENSE,
REVERSE
POLARITY SENSE
AND CPUMP
DRIVE
REF
5V
R1
10Ω
GPIOPWR
C24
4.7µF
C22
0.1µF
C5
2.2µF
C2
1µF
C3
1µF
L6
10µHL1
10µH
4 TO 8 WLEDS
REG2
ALWAYS ON
CH1 425mA
CURRENT
LIMITER
CLSOUT
VEXT
3.4V TO 13.2V
(+30V/-28V FAULT PROTECTED)
LOAD
3V3 OR 5V0
LVRIN5V
CLK
CLK
CH7 1V2 STEP-DOWN
CONVERTER
(600mA MAX)
L2
4.7µH
C9
0.1µF
1V2BST
1V2LX
1V2IN
C8
2x 22µF
C7
4.7µF
LVRPWR
5V
BOOTSTRAP
RPGATE
C1
0.22µF
CLSIN
C11
680µF
Q1
Q2
VCS+ -VCS-
= 0 TO 60mV
LVROUT
1V2FB
1V2
OVGATE
OVPWR
C12
0.1µF
VIN
VIN
VIN
EP
MAX8904
3V3
CH3 3V3
STEP-DOWN
CONVERTER
(1250mA MAX)
3V3LX
3V3IN
3V3BST
3V3FB
C20
2x 22µF
C21
4.7µF
C19
0.1µF
L5
4.3µH
VIN
1V8 CH2 1V8
STEP-DOWN
CONVERTER
(975mA MAX)
1V8LX
1V8IN
1V8BST
1V8FB
C17
22µF
C18
4.7µF
C16
0.1µF
L4
4.7µH
VIN
ADJ
NOTE: 1V2, 1V8, AND ADJ OPERATE IN PHASE. 3V3 AND 5V0 OPERATE INPHASE WITH RESPECT TO EACH OTHER, BUT ARE DELAYED BY 300ns WITH RESPECT TO 1V2, 1V8, AND ADJ.
CH5 ADJ
STEP-DOWN
CONVERTER
(3V TO 5.1V I2C PROG,)
(1500mA MAX RMS,
2A PULSE)
ADJLX1
ADJIN
ADJBST
ADJFB
C14
2x 22µF
C15
4.7µF
C13
0.1µF
L3
4.3µH
VIN
ADJLX2
VIN
C4
1µF
C6
1µF
D2
D1
R3
10Ω
C10
1µF
C25
0.022µF
20
Figure 1. Typical Application Circuit and Function Diagram
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 23
Detailed Description
The MAX8904 power-management ICs provide a com-
plete power-supply solution for 2-cell Li+ handheld/Li-Poly
applications such as point-of-sale terminals, digital SLR
cameras, digital video cameras, and ultra-mobile PCs.
The MAX8904 include five step-down converters (1V2-
0.6A, 1V8-0.975A, 3V3-1.25A, 5V0-0.8A, and ADJ-
1.5A) with internal MOSFETs and +1%/-3% accurate
output voltages for processor core, memory, I/O, and
other system power rail requirements. The ADJ con-
verter provides an adjustable output voltage that is 6-
bit programmable through the I2C interface from 3.0V
to 5.1V, in 33.3mV steps.
LCD backlighting is supported by a WLED boost con-
verter that can provide 35mA for up to 8 WLEDs while
operating in the current regulator mode. This boost
converter is also configurable as a 6 bit programmable
voltage source that can provide up to 63mA of output
current. In this voltage mode, the output voltage is 6-bit
programmable through the I2C interface from 12.5V to
18.7V, in 100mV steps.
System input current monitoring for power manage-
ment is facilitated by an on-board Current Sense
Amplifier (CSA) with differential inputs and a 1.2V full
scale ground referenced analog output. The CSA has
an I2C programmable gain of 20V/V and 40V/V for full-
scale outputs of 4A and 2A, respectively, when used
with a 15mΩcurrent-sense resistor.
A 400kHz, I2C interface supports output voltage setting
of ADJ power rail and boost regulator (voltage source
mode), WLED current setting for the boost regulator
(WLED current regulator mode), enable/disable of ADJ,
5V0, boost regulator, CSA and GPIO control. The I2C
interface also enables the host processor to read on-
board fault status registers when interrupted by the
MAX8904 FLT pin under system fault conditions. An
emergency shutdown input, SHDN allows converters
preselected through I2C to turn off immediately, thus
saving valuable firmware execution time under power
fail conditions.
The MAX8904 features an 8-bit GPIO port controller with
PWM capability. The GPIO port pins power up as Schmitt-
trigger CMOS inputs. Programmable configurations are:
• Schmitt-trigger input with internal 1MΩpullup to
GPIOPWR
• Open-drain output, with internal 10kΩpullup resis-
tor off-state, capable of sinking up to 20mA current
from GPIOPWR
• Open-drain output with high-impedance state, capa-
ble of sinking up to 20mA current from GPIOPWR
• High-impedance output
GPIO0 can be used to set the I2C slave address of the
MAX8904 to either CEh or 8Eh (see Table 1).
A current-limited switch (CLS) is provided, with a minimum
output current of 425mA, which allows system designers
to control input power to external peripheral devices.
The MAX8904 supports input overvoltage protection
(OVP) at 13.5V (typ) by controlling an external n-MOSFET
and reverse polarity protection (down to -28V) of down-
stream circuits by controlling an external p-MOSFET.
An uncommitted, active-low, high voltage open-drain
comparator (CMP) with a 1.25V internal reference and
20mA sink current capability that can function as a
buzzer driver or can be used for power fail sensing is
also provided.
The MAX8904’s PWREN logic input turns on 1V2, 1V8,
3V3, and 5V0 default power rails. An internal 5V low-
voltage linear regulator powered from the input power
source provides power for the internal drive and control
blocks. When the input is below 5V, the regulator out-
put follows the input down to 3.4V. When the input volt-
age drops below 3.4V (UVLO), all circuitry except the
overvoltage protection block are turned off. When the
input voltage drops below 2.85V (OVPWR UVLO), the
overvoltage protection block is turned off.
I
2
C Interface
The MAX8904 internal I2C serial interface provides flex-
ible control setup, including ON/OFF control of all
power converters (except 1V2, 1V8, and 3V3), CLS,
CSA and CMP, the ADJ output voltage, the BST output
voltage or output current, and the 8-bit GPIO port func-
tionality. The MAX8904 internal control and fault status
registers are also accessed through the standard bi-
directional, 2-wire I2C serial interface. The I2C serial
interface consists of a serial-data line (SDA) and a seri-
al-clock line (SCL) to achieve bidirectional communica-
tion between the master and the slave. The MAX8904 is
a slave-only device, relying upon a master to generate
a clock signal. The master (typically a microprocessor)
initiates data transfer on the bus and generates SCL to
permit data transfer. The MAX8904 supports SCL clock
rates up to 400kHz.
I2C is an open-drain bus. SDA and SCL require pullup
resistors (500Ωor greater). Optional resistors (24Ω) in
series with SDA and SCL protect the device inputs from
high-voltage spikes on the bus lines. Series resistors
also minimize crosstalk and undershoot on bus signals.
I
2
C Slave Address
A bus master initiates communication with MAX8904 as
a slave device by issuing a START condition followed
by the MAX8904 address. As shown in Table 1, the
MAX8904 responds to either one of two internally hard-
wired slave addresses depending on the GPIO0 status
when GPIOPWR powers up for the first time and
exceeds its UVLO (rising) threshold. This address is
latched internally and can only be changed if the LVRP-
WR voltage is cycled, and the GPIOPWR voltage
exceeds UVLO again.
Pullup Voltage
The MAX8904 I2C interface SDA and SCL line should
use the 3V3 supply as its pullup voltage.
START and STOP Conditions
Both SDA and SCL remain high when the serial inter-
face is inactive. The master signals the beginning of a
transmission with a START (S) condition by transitioning
SDA from high to low while SCL is high. When the master
has finished communicating with the MAX8904, it
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2). Both START and STOP
conditions are generated by the bus master.
To send a series of commands to the MAX8904, the
master issues REPEATED START (Sr) commands
instead of a STOP command to maintain the bus con-
trol. In general, a REPEATED START command is func-
tionally equivalent to a regular START command.
When a STOP condition or incorrect address is detect-
ed, the MAX8904 internally disconnect SCL from the
bus until the next START condition to minimize digital
noise and feedthrough.
Data Transfer
Each data bit, from the most significant bit to the least
significant bit, is transferred one by one during each
SCL clock cycle. The data on SDA must remain stable
during the high period of the SCL clock. Changes in
SDA while SCL is high are control signals (see the
START and STOP Conditions
section).
Each transmit sequence is framed by a START condi-
tion and a STOP condition. Each data packet is nine
bits long: eight bits of data followed by an acknowl-
edge bit.
Acknowledge
Both the I2C bus master and the MAX8904 (slave) gen-
erate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each nine bit data
packet. To generate an acknowledge (A) signal, the
receiving device pulls SDA low before the rising edge
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
24 ______________________________________________________________________________________
GPIO0 STATUS AT
VGPIOPWR > VGPIOPWR_UVLO
(RISING)
SLAVE
ADDRESS
READ
SLAVE
ADDRESS
WRITE
Logic 0 (GPIO0 pulled down by
an internal 100k resistor
between GPIO0 and GND)
8Fh 8Eh
Logic 1 (GPIO0 pulled up by an
internal 1M resistor between
GPIO0 and GPIOPWR)
CFh CEh
Table 1. MAX8904 Slave Addresses
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD, STA
tSU, STA tHD, STA
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tRtF
Figure 2. 2-Wire Serial Interface Timing Detail
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 25
of the acknowledge-related clock pulse (ninth pulse)
and keeps it low during the high period of the clock
pulse (Figure 3). To generate a not-acknowledge (NA)
signal, the receiving device allows SDA to be pulled
high before the rising edge of the acknowledge-related
clock pulse and leaves it high during the high period of
the clock pulse. Monitoring the acknowledge bits allows
for detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
Communication Protocols
The following I2C communication protocols are support-
ed by the MAX8904:
• Writing to a single register
• Writing multiple bytes using register-data pairs
• Reading from a single register
• Reading from sequential registers
Writing to a Single Register
Figure 4 shows the protocol for the master device to
write one byte of data to the MAX8904. The write byte
protocol is as follows:
1) The master sends a START (S) command.
2) The master sends the 7-bit slave address followed
by a write bit (low).
3) The addressed slave asserts an acknowledge (A)
by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data
8) The slave acknowledges the data byte.
9) The master sends a STOP (P) condition.
S
SCL
SDA
12 89
NOT ACKNOWLEDGE (NA) ACKNOWLEDGE (A)
tHD:DAT
tSU:DAT
Figure 3. Acknowledge
1
S
NUMBER OF BITS
R/nW
SLAVE ADDRESS
7
0
18
REGISTER POINTERA
1
A
18
DATA A
1
P
1
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
Figure 4. Write-Byte Format
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
26 ______________________________________________________________________________________
Writing Multiple Bytes Using Register-Data Pairs
Figure 5 shows the protocol for the master device to
write multiple bytes to the MAX8904 using register-data
pairs. It allows the master to address the slave only once
and then send data to multiple registers in a random
order. Registers may be written continuously until the
master issues a STOP (P) condition. The write multiple
bytes using register-data pairs protocol is as follows:
1) The master sends a START (S) command.
2) The master sends the 7-bit slave address followed
by a write bit (low).
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
7) The slave updates with the new data.
8) The slave acknowledges the data byte.
9) Steps 5 to 8 are repeated as many times as the
master requires. Registers may be accessed in
random order.
10) The master sends a STOP (P) condition.
Reading from a Single Register
Figure 6 shows the protocol for the master device to
read one byte of data from the MAX8904. The read byte
protocol is as follows:
1) The master sends a START (S) command.
2) The master sends the 7-bit slave address followed
by a write bit (low).
3) The addressed slave asserts an acknowledge (A)
by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START (Sr) com-
mand.
1
SSLAVE ADDRESS
7
0
18
REGISTER POINTER X
A
1
A
18
DATA X A
1
P
1
8
REGISTER POINTER n A
18
DATA n A
1
8
REGISTER POINTER Z A
18
DATA Z A
1
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
NUMBER OF BITS
R/nW
NUMBER OF BITS
NUMBER OF BITS
Figure 5. Multiple Bytes Register-Data Pair Format
1
S SLAVE ADDRESS
7
0
18
REGISTER POINTER XA
1
A
11
Sr SLAVE ADDRESS
7
1
18
DATA XA
1
nA
1
P
1
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
R/nW R/nW
NUMBER OF BITS
Figure 6. Read-Byte Format
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 27
7) The master sends the 7-bit slave address followed
by a read bit (high).
8) The addressed slave asserts an acknowledge (A)
by pulling SDA low.
9) The addressed slave places 8-bits of data on the
bus from the location specified by the register
pointer.
10) The master asserts a not-acknowledge on the
data line to complete operations.
11) The master issues a STOP (P) condition.
Reading from Sequential Registers
Figure 7 shows the protocol for reading from sequential
registers. This protocol is similar to the read byte proto-
col except that the master issues an acknowledge to
signal the slave that it wants more data. When the mas-
ter has all the data, it issues a not-acknowledge (NA)
and a STOP condition (P) to end the transmission. The
continuous read from sequential registers protocol is as
follows:
1) The master sends a START (S) command.
2) The master sends the 7-bit slave address followed
by a write bit (low).
3) The addressed slave asserts an acknowledge (A)
by pulling SDA low.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
6) The master sends a REPEATED START (Sr) com-
mand.
7) The master sends the 7-bit slave address followed
by a read bit (high).
8) The addressed slave asserts an acknowledge by
pulling SDA low.
9) The addressed slave places 8-bits of data on the
bus from the location specified by the register
pointer.
10) The master issues an acknowledge (A) signaling
the slave that more data is needed.
11) Steps 9 and 10 are repeated as many times as
the master requires. Following the last byte of
data, the master issues a not-acknowledge (NA)
to signal that it wishes to stop receiving data.
12) The master issues a STOP (P) condition.
1
1
SSLAVE ADDRESS
7
0
18
REGISTER POINTER X
A
1
A
11
Sr SLAVE ADDRESS
7
1
18
DATA XA
1
A
1
8
DATA X + 3 A
1
8
DATA X + 2 A
1
DATA X + 1 A
81
8
DATA n nA
1
8
DATA n - 1 A
1
DATA n - 2 A
81
P
SLAVE TO MASTERMASTER TO SLAVE
LEGEND
R/nW R/nW
NUMBER OF BITS
NUMBER OF BITS
NUMBER OF BITS
Figure 7. Read from Sequential Registers Format
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
28 ______________________________________________________________________________________
REGISTER
A D DR ESS R/W POR
VAL UE
REGISTER
NAME D7 D6 D5 D4 D3 D2 D1 D0
00h R/W 00h GPIO-A
CONFIG
PWM
enable/
disable
PWM
bank
select
GPIO1
configuration bits
PWM
enable/
disable
PWM
bank
select
GPIO0
configuration bits
01h R/W 00h GPIO-B
CONFIG
PWM
enable/
disable
PWM
bank
select
GPIO3
configuration bits
PWM
enable/
disable
PWM
bank
select
GPIO2
configuration bits
02h R/W 00h GPIO-C
CONFIG
PWM
enable/
disable
PWM
bank
select
GPIO5
configuration bits
PWM
enable/
disable
PWM
bank
select
GPIO4
configuration bits
03h R/W 00h GPIO-D
CONFIG
PWM
enable/
disable
PWM
bank
select
GPIO7
configuration bits
PWM
enable/
disable
PWM
bank
select
GPIO6
configuration bits
04h R/W 00h GPIO-DATA I/O-8 I/O-7 I/O-6 I/O-5 I/O-4 I/O-2 I/O-1 I/O-0
05h R/W 00h PWM-BANK0 MSB — — — — — — LSB
06h R/W 00h PWM-BANK1 MSB — — — — — — LSB
07h R/W 00h ENABLE CSAEN X CMPEN BSTEN ADJEN 5V0EN IN IT CLSEN
08h R/W 00h SHUTDOWN
(SHDN)CSA X CMP BST ADJ 5V0 X CLS
09h R/W 00h MODE CSAG C S FLGE N X BSTIV ADJM X X OVOFF
0Ah R/W 00h ADJSP Lockout X MSB — — — — LSB
0Bh R/W 00h BSTCSP X X MSB — — — — LSB
0Ch R/W 00h BSTVSP Lockout X MSB — — — — LSB
0Dh R 00h FA ULT STA TUS BS TFLT1 BSTFLT0 VOKFLT OLFLT TMP120 X OCIN OVIN
0Eh R 00h OVERLOAD BSTOL ADJOL 5V0OL 3V3OL 1V8OL 1V2OL X CLSOL
0Fh R FFh VOK BSTOK ADJOK 5V0OK 3V3OK 1V8OK 1V2OK X CLSOK
10h R — DEVICE ID Chip ID
MSB ———
Chip ID
LSB
Chip
Rev
MSB
—
Chip
Rev
LSB
11h W 00h CLRFLTS Fault status and fault registers are cleared and FLT goes to high when CLRFLTS
register is set to 01h. Fault detection rearms when CLRFLTS is set back to 00h.
Table 2. Register Assignments
I2C Accessible Registers
The I2C accessible registers are used to store all the
control information from the SDA line and configure the
MAX8904 for different operating conditions. Recycling
power at LVRPWR causes the MAX8904 to initialize the
registers to their POR values. The register assignments
of the MAX8904 are in Table 2.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 29
PWM ENABLE PWM BANK GPIO CONFIGURATION GPIO CONFIGRUATION DESCRIPTION
D7/D3 D6/D2 D5/D1 D4/D0 DATA BITS
00
XX
GPIO-Data (04h): 0 = low, 1 = high Input with 1MΩ pullup resistor to GPIO
01
0 = Disabled
1 = Enabled
0 = BANK0
1 = BANK1 GPIO-Data (04h):
0 = sink, 1 = pullup
Open-drain n-device with 10kΩ pullup resistor
to GPIO, and tolerant of sinking current from 5V
power supply
10
0 = Disabled
1 = Enabled
0 = BANK0
1 = BANK1 GPIO-Data (04h):
0 = pull, 1 = push
Open-drain n-device with high-impedance
state, and tolerant of sinking current from 5V
power supply
11
XX GPIO-Data (04h):
0 = Hi-Z, 1 = Hi-Z
High-impedance (Hi-Z) output
0 0 0 0 Reset value = 0h
Table 3. GPIO Configuration Register (00h to 03h)
D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS
IO8 IO7 IO6 IO5 IO4 IO3 IO2 IO1 Reset value = 00h
Table 4. GPIO Data Register (04h)
D7 D6 D5 D4 D3 D2 D1 D0 DATA BITS
MSB — — — — — — LSB PWM-BANK0
MSB — — — — — — LSB PWM-BANK1
00000000Reset value = 00h
Table 5. GPIO PWM Bank Register (05h, 06h)
GPIO Configuration Register
The 00h to 03h registers allow the host processor to
setup GPIO0–GPIO7 configuration through the I2C
interface. Each nibble represents a physical GPIO port.
These eight nibbles address all the operating require-
ments of the 8-bit GPIO port, including PWM dimming.
LED blinking requirement is addressed by turning the
LEDs on and off at the required rate through the I2C
interface. The least significant two bits of each nibble
define whether the particular GPIO bit is either an input
or an output. If it is an output bit, the output device
structure (open-drain/pullup, open-drain/high imped-
ance, or high impedance/high impedance) is also
defined by these two bits. On power-up, the eight GPIO
bits are configured as inputs. See Table 3 for details.
GPIO Data Register
The GPIO Data register (04h) is a read/write (R/W) reg-
ister that allows the host processor to read those GPIO
bits that are programmed as inputs and write to those
GPIO bits that are programmed as outputs through the
I2C interface. For a read operation, all eight bits are
read regardless of whether they are configured as
inputs or outputs. It allows the host processor to read
status of all eight bits. For a write operation, only those
bits that are configured as outputs are written to, and
the input bits are neglected. On power-up, all GPIO bits
are configured to inputs by default. Each data bit repre-
sents a physical GPIO port and its functionality is given
in Table 3.
PWM Bank Register
The PWM Bank registers PWM-BANK0 (05h) and PWM-
BANK1 (06h) are used to set up two different pulse-
width modulation values and switch between them by
changing the value of the PWM bank select bit (D6/D2)
in the GPIO Configuration registers (00h to 04h).
Running at a clocking rate of 244Hz, these two regis-
ters allow the LEDs to be driven at 256 discrete levels
of intensity control, from 0.0µs on/4.1ms off (0%) to
4.084ms on/16µs off (99.6%). When multiple LEDs are
controlled by the GPIO ports, the use of two PWM reg-
isters allows some LEDs to be dimmed while other
LEDs are simultaneously brightened. Individual LEDs
can also be switched between two intensities by tog-
gling its PWM-BANK assignment. See Table 5.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
30 ______________________________________________________________________________________
D7 D6 D5 D4 D3 D2 D1 D0 RESET
CSAEN X CMPEN BSTEN ADJEN 5V0EN INIT CLSEN 00h
Table 6. Enable Register (07h)
D7 D6 D5 D4 D3 D2 D1 D0 RESET
CSA X CMP BST ADJ 5V0 X CLS 00h
Table 7. Shutdown Register (08h)
Enable Register
With the exception of the 1V2, 1V8, and 3V3 power con-
verters, the Enable register (Table 6) allows the host
processor to enable/disable the individual channel
when needed. If a bit is programmed to 1, the corre-
sponding power converter is enabled; otherwise, with a
value of 0, the corresponding power converter remains
disabled, even if valid data has been programmed in
the associated set point register (0Ah, 0Bh, or 0Ch) for
the ADJ or BST power converter. Conversely, if the
ADJEN bit for ADJ or the BSTEN bit for BST is set to 1,
with a set point register (0Ah, 0Bh, or 0Ch) value of
00h, the ADJ or BST power converter remains disabled.
When the MAX8904 turns off a particular power con-
verter under a fault condition, it sets the corresponding
Enable register bit to 0.
Note that the 1V2, 1V8, 3V3, and 5V0 converters are
turned on when PWREN is pulled high, but the 5V0 con-
verter can be turned on/off by the Enable register bits
once it is above its VOK thresholds. The 1V2, 1V8, and
3V3 converters can be turned off only by pulling
PWREN low.
Firmware Initialization at Power-Up
The MAX8904 requires a mandatory firmware proce-
dure to be executed by the host processor at power-up
to initialize the part correctly. The following register
writes should be executed before responding to an
interrupt on the FLT pin of the MAX8904.
• 04(h) Register 07(h) (Sets the INIT bit to 0)
• 01(h) Register 11(h)
• 00(h) Register 11(h)
Note that the firmware should keep the INIT bit set to 0
under all operating conditions.
Firmware Initialization for CLS Operation
The MAX8904 requires a mandatory firmware proce-
dure to be executed by the host processor after turning
ON the CLS block to initialize the CLS block correctly.
The following firmware steps should be executed after
turning ON the CLS block before responding to an
interrupt on the FLT pin of the MAX8904:
• Execute a 300ms (min) delay.
• After the 300ms delay, execute the following register
writes:
01(h) Register 11(h)
00(h) Register 11(h)
Shutdown Register
The Shutdown register works in conjunction with SHDN
to program which converters are turned off in the event
of a power failure. SHDN is connected to the midpoint
of a resistor-divider from LVRIN5V to GND, and is nomi-
nally at 3.3V (see Table 7).
Upon receiving a power-fail signal, the host processor
asserts the active-low SHDN, and only those power
converters whose corresponding bits are programmed
to 0 in the Shutdown register are turned off, and their
associated Enable bits in the Enable register, if current-
ly programmed to 1, are set to 0. The power converters
whose bits in the Shutdown register are programmed to
1 remain enabled.
If a power failure occurs, where the external power
source voltage falls below the 3.4V, the MAX8904 enters
the UVLO state. It powers up with default settings when it
subsequently comes out of UVLO. Note that the host
processor can still hold SHDN low at this point and it
does not cause any action on the MAX8904. The
MAX8904 performs the shutdown operation only when it
detects a high-to-low transition on SHDN.
Note that the 1V2, 1V8, and 3V3 power controllers are
always ON and can not be turned off through the
Shutdown register.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 31
D7 D6 D5 D4 D3 D2 D1 D0 RESET
CSAG CSFLGEN X BSTIV ADJM X X OVOFF 00h
Table 8. Mode Register (09h)
D7 D6 D5 D4 D3 D2 D1 D0 RESET
LOCKOUT X MSB — — — — LSB 00h
0000000000h
Table 9. ADJSP Register (0Ah)
Mode Register
The Mode register is used to configure the operating
mode of various functional blocks. See Table 8.
CSAG (Bit 7): The MAX8904 provides a programmable
gain current-sense amplifier. The CSAG bit is used to
determine the gain setting for CSA. If it is programmed
to 0, the amplifier gain is set to 20V/V. If it is pro-
grammed to 1, the amplifier gain is set to 40V/V.
CSFLGEN (Bit 6): The CSFLGEN bit is used to
enable/disable the CSA input over-current fault detec-
tion feature. If the CSFLGEN bit is high, the MAX8904
sets the OCIN (D1) bit in the FAULT STATUS register,
and asserts FLT when an input overcurrent is sensed at
CSOUT. The input overcurrent fault detection is dis-
abled if CSFLGEN is set to 0.
BSTIV (Bit 4): The BST step-up converter supports
voltage mode or current mode operation and the mode
selection is realized by the BSTIV bit. If it is pro-
grammed to 0, the converter operates in the current
mode with the BSTCSP register setting. If it is pro-
grammed to 1, the converter operates in the voltage
mode with the BSTVSP register setting.
ADJM (Bit 3): The MAX8904 supports automatic
switching from pulse-width modulation (PWM) to pulse-
skipping modulation (PSM) to improve power supply
efficiency at light loads for all of the power converters
except the ADJ step-down converter that must be set
by the ADJM bit. Because the pulse-skipping mode has
inherently larger voltage ripple, it may be necessary for
the ADJ supply to remain in pulse-width modulation
mode when powering noise sensitive loads such as a
GPRS radio module. ADJM bit allows the host proces-
sor to force the ADJ controller to remain in PWM mode,
if desired. When it is programmed to 0, the ADJ power
converter automatically switches between PSM and
PWM modes. When it is programmed to 1, the power
controller is forced to remain in PWM mode.
OVOFF (Bit 0): The OVOFF bit is used to turn off the
external overvoltage protection n-MOSFET, for the pur-
pose of battery pack conditioning. When it is programmed
to 0, the overvoltage protection circuit determines the state
of the external overvoltage protection n-MOSFET. When it
is programmed to 1, the overvoltage protection n-MOSFET
is turned off.
ADJSP Register
The MAX8904 uses the I2C interface to set the output
voltage of ADJ power controller. A 6-bit value adjusts
the ADJ output voltage from 3V to 5.067V, in 33.3mV
increments (see Table 10). It is an invalid setting if the
ADJSP register is set as 00h (2.967V). The first valid
setting is 01h (3V). See Table 9 for the ADJSP register
definition.
Table 10 shows hex codes for various output voltage
settings of the ADJ power controller.
Bit 7 (LOCKOUT) of the ADJSP register allows the volt-
age setting to be programmed only one time after
power-up. After power-up, the host processor sets the
ADJSP value only once. When the host processor
changes the 00h setting to a valid number, the
MAX8904 sets the LOCKOUT bit to 1. Once it is set to
1, subsequent changes to the 6-bit ADJSP value are
locked out. Only by recycling power, the LOCKOUT bit
can be restored to 0. Note that the ADJSP register is an
R/W register, and it allows the user to read the lockout
bit and determine whether the MAX8904 had already
been set to a valid output voltage.
When the MAX8904 detects that the ADJEN bit is 1,
and recognizes valid data in the ADJSP register, the
ADJ controller is enabled and soft-starts to the target
output voltage. When the Enable bit for the ADJ power
converter is set to 1 with an ADJSP register value of
00h, the ADJ stays in the off condition. Conversely, with
the ADJEN bit set to 0, the regulator remains disabled,
even if valid data has been programmed in the ADJSP
register. Neither of these two conditions generates a
FLT assertion, since the power converter is considered
to be in the off state. Fault detection is enabled only if
the ADJEN bit is high, and valid data has been pro-
grammed in the ADJSP register. See Table 11.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
32 ______________________________________________________________________________________
ADJ VOLTAGE HEX CODE ADJ VOLTAGE HEX CODE
3.000 1 4.066 21
3.033 2 4.099 22
3.066 3 4.133 23
3.099 4 4.166 24
3.133 5 4.199 25
3.166 6 4.233 26
3.199 7 4.266 27
3.233 8 4.299 28
3.266 9 4.333 29
3.299 A 4.366 2A
3.333 B 4.399 2B
3.366 C 4.433 2C
3.399 D 4.466 2D
3.433 E 4.499 2E
3.466 F 4.533 2F
3.499 10 4.566 30
3.533 11 4.599 31
3.566 12 4.633 32
3.599 13 4.666 33
3.633 14 4.699 34
3.666 15 4.733 35
3.699 16 4.766 36
3.733 17 4.799 37
3.766 18 4.833 38
3.799 19 4.866 39
3.833 1A 4.899 3A
3.866 1B 4.933 3B
3.899 1C 4.966 3C
3.933 1D 4.999 3D
3.966 1E 5.033 3E
3.999 1F 5.066 3F
4.033 20 — —
Table 10. ADJ Output Voltage Settings
ADJEN BIT ADJSP VALID SET POINT ADJ ENABLED FAULT DETECTION ENABLED
0 00h No No
0 > 00h No No
1 00h No No
1 > 00h Yes Yes
Table 11. ADJEN/ADJSP Truth Table
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 33
D7 D6 D5 D4 D3 D2 D1 D0 RESET VALUE
Reserved Reserved MSB ————LSB 00h
XX000000 00h
Table 12. BSTCSP Register (0Bh)
BST Current Set Point Register
The BST step-up converter has two modes of operation:
current and voltage. The current-mode operation is
used to drive a WLED string, while the voltage-mode
operation provides a regulated DC voltage for TFT or
OLED panels.
In the current mode, the WLED string is connected from
the BST output to PCS and the control loop regulates the
LED current to the value set in the BSTCSP register
through the I2C interface. The BSTCSP register (0Bh) is
defined in Table 12. A 6-bit value allows the host proces-
sor to adjust the current from 1mA to 63mA, in 1mA mini-
mum increments. The maximum recommended
increment is 16mA per I2C command. It is an invalid
setting if the BSTCSP register is set to 00h (0mA). The
first valid number is 01h (1mA). The 3Fh setting corre-
sponds to 63mA (see Table 13 for WLED current set-
tings and corresponding hex codes).
The host processor can change the dimming levels as
many times as desired during normal operation.
In current mode, the value programmed in the BSTVSP
register (0Ch) is used as an overvoltage threshold.
When the output voltage in current mode reaches the
threshold, the converter is immediately latched off, and
it requires either the host processor to issue either a
CLRFLTS command and drive BSTEN high, or recycling
input power to start up again. Recommended overvolt-
age threshold settings for the LED strings are provided
in Table 14. The overvoltage threshold is programmable
from 13.4V to 32V in 300mV increments. A 00h setting in
the BSTVSP register corresponds to 13.1V and is an
invalid setting. A 01h value corresponds to a valid 13.4V
overvoltage setting. The host processor can only pro-
gram this overvoltage setting in the BSTVSP register
once, after which the lockout bit is set to 1 to prevent
subsequent programming attempts. The one-time pro-
grammability of the BSTVSP register applies to overvolt-
age setting in both current mode and voltage mode.
LED CURRENT
(mA) HEX CODE LED CURRENT
(mA) HEX CODE
1013321
2023422
3033523
4043624
5053725
6063826
7073927
8084028
9094129
10 0A 42 2A
11 0B 43 2B
12 0C 44 2C
13 0D 45 2D
14 0E 46 2E
15 0F 47 2F
16 10 48 30
17 11 49 31
18 12 50 32
19 13 51 33
20 14 52 34
21 15 53 35
22 16 54 36
23 17 55 37
24 18 56 38
25 19 57 39
26 1A 58 3A
27 1B 59 3B
28 1C 60 3C
29 1D 61 3D
30 1E 62 3E
31 1F 63 3F
32 20 — —
Table 13. BSTCSP LED Current Settings
NO. OF SERIES WLEDs BSTVSP SETTING (V) CODE IN BSTVSP REGISTER (0Ch)
4 18.3 04h
5 22.5 12h
6 26.7 20h
7 30.9 2Eh
8 35.1 3Ch
Table 14. Overvoltage Threshold Settings for BST Regulator Current-Mode Operation
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
34 ______________________________________________________________________________________
BST Voltage Set Point Register
When the BST operates in voltage mode, a device such
as a TFT or OLED display panel can be connected
between the BST output and power ground. PCS is
connected to GND in this application to disable the cur-
rent sink function. In this mode, the BST acts as a volt-
age source with current limit functionality and regulate
its output to the value set in the BSTVSP register (see
Table 15). A 6-bit value adjusts the voltage from 12.5V
to 18.7V in 100mV increments (see Table 16). It is an
invalid setting if the BSTVSP register is set to 00h
(12.4V). The first valid number is 01h (12.5V). Note that
with an output of 12.5V, the converter may be operating
in dropout for an input voltage of 12.6V.
D7 D6 D5 D4 D3 D2 D1 D0 RESET
Lockout Reserved MSB — — — — LSB —
0X00000000h
Table 15. BSTVSP Register (0Ch)
OUPUT VOLTAGE (V) HEX CODE OUTPUT VOLTAGE (V) HEX CODE
12.5 01 15.7 21
12.6 02 15.8 22
12.7 03 15.9 23
12.8 04 16 24
12.9 05 16.1 25
13 06 16.2 26
13.1 07 16.3 27
13.2 08 16.4 28
13.3 09 16.5 29
13.4 0A 16.6 2A
13.5 0B 16.7 2B
13.6 0C 16.8 2C
13.7 0D 16.9 2D
13.8 0E 17 2E
13.9 0F 17.1 2F
14 10 17.2 30
14.1 11 17.3 31
14.2 12 17.4 32
14.3 13 17.5 33
14.4 14 17.6 34
14.5 15 17.7 35
14.6 16 17.8 36
14.7 17 17.9 37
14.8 18 18 38
14.9 19 18.1 39
15 1A 18.2 3A
15.1 1B 18.3 3B
15.2 1C 18.4 3C
15.3 1D 18.5 3D
Table 16. BSTVSP Voltage Settings and Hex Codes
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 35
Bit 7 (LOCKOUT) of the BSTVSP register allows the volt-
age setting to be programmed only one time after
power-up. After power-up, the host processor sets the
BSTVSP value only once. When the host processor
changes the 00h setting to a valid number, the MAX8904
sets LOCKOUT bit to 1. Once it is set to 1, subsequent
changes to the 6-bit BSTVSP value are locked out. Only
by recycling power, the LOCKOUT bit can be restored
to 0. Note that the BSTVSP register is an R/W register,
and it allows the user to check the lockout bit.
In voltage mode, when the MAX8904 detects that the
BSTEN bit is 1 and recognizes valid data in the BSTVSP
register, the BST regulator is enabled and soft-starts to
the target output voltage. When the BSTEN is set to 1
with a BSTVSP register value of 00h, the BST regulator
stays in the off condition. Conversely, with the BSTEN
bit set to 0, the regulator remains disabled, even if the
valid data has been programmed in the BSTVSP regis-
ter. Neither of these two conditions generates a FLT
assertion, since the regulator is considered to be in the
off state. Fault detection is enabled only if the BSTEN
bit is high, and valid data has been programmed in the
BSTVSP register. See Table 17.
Fault Handling
The MAX8904 has two fault registers (VOK and OVER-
LOAD) and a fault status register (FAULTSTATUS). See
Tables 18, 20, and 21 for details about these register bits.
BSTEN BIT BST_SP VALID
SET POINT BST ENABLED FAULT DETECTION ENABLED
0 00h No No
0 > 00h No No
1 00h No No
1 > 00h Yes Yes
Table 17. BSTEN/BST_SP Truth Table
OUPUT VOLTAGE (V) HEX CODE OUTPUT VOLTAGE (V) HEX CODE
15.4 1E 18.6 3E
15.5 1F 18.7 3F
15.6 20 — —
Table 16. BSTVSP Voltage Settings and Hex Codes (Voltage Mode) (continued)
BSTFLT1 BSTFLT0 FAULT DESCRIPTION
0 0 No fault.
0 1 Overvoltage (current mode only).
1 0 Open or reverse output diode, or open BSTFB connection (detected at startup before BSTLX switching).
11
PCS short to GND fault, or BST output short to PCS fault (current mode only, detected at startup before
BSTLX switching).
Table 19. BST Fault Bit Description
D7 D6 D5 D4 D3 D2 D1 D0 RESET
BSTOL VADJOL 5V0OL 3V3OL 1V8OL 1V2OL X CLSOL 00h
Table 20. Overload Register (0Eh)
D7 D6 D5 D4 D3 D2 D1 D0 RESET
BSTFLT1 BSTFLT0 VOKFLT OLFLT TMP120 X OCIN OVIN 00h
Table 18. Fault Status Register (0Dh)
D7 D6 D5 D4 D3 D2 D1 D0 RESET
BSTOK VADJOK 5V0OK 3V3OK 1V8OK 1V2OK X CLSOK 11h
Table 21. VOK Register (0Fh)
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
36 ______________________________________________________________________________________
The MAX8904 handles faults as outlined in Tables 22
and 23.
The FAULTSTATUS register indicates the type of system
fault that has occurred. The BSTFLT0, BSTFLT1 bits are
set based on the type of fault that has occurred in the
BST step-up converter (see Table 19). The VOKFLT bit
is set when a VOK fault has occurred on any one of the
power converters.
A VOK fault occurs either when a converter fails to soft-
start or due to overload/short-circuit conditions on the
output under normal operation, causing the output volt-
age to fall below its VOK threshold. The _OK bits in the
VOK register are set to 1 at power up. When a VOK
fault occurs, the _OK bit corresponding to the faulty
converter is set to 0, indicating a VOK fault in the partic-
ular converter.
The OLFLT bit is set when the output current on a converter
exceeds its overload threshold. The _OL bit in the OVER-
LOAD register corresponding to the faulty converter is set
to 1 indicating an overload fault in the particular converter.
The TMP120 bit is set when the internal die temperature
exceeds +120°C. With the current sense resistor across
CS+, CS- pins of the MAX8904 connected in series with
the input power source, the OCIN bit is set when the
CSOUT voltage exceeds its CSFLAG threshold, indicat-
ing an input overcurrent condition. The OVIN bit is set
when the input voltage sensed at the OVPWR pin
exceeds the overvoltage threshold.
FAULT TYPE FAULT RESPONSE AND RECOVERY
• Overload on 1V2, 1V8, 3V3
• VOK fault on 1V2, 1V8, 3V3
(detected after internal soft-start
time plus a 2ms delay).
• FLT goes to low, all regulators are turned off immediately after fault detection, and the
corresponding bits in FAULTSTATUS, OVERLOAD, and VOK registers are set.
• Fault detection is enabled for a regulator only if CLRFLTS=00h, and PWREN is high.
• Toggling PWREN (highlowhigh) if PWREN is still high, or driving PWREN from low to
high resets all fault status and fault registers, pulls FLT to high, and causes the MAX8904
to restart the 1V2, 1V8, 3V3, and 5V0 supplies.
• Recycling power to the LVRPWR input of the internal linear regulator causes the MAX8904
to power up and remain in standby mode if PWREN is low. If PWREN is high, the MAX8904
attempts to start the 1V2, 1V8, 3V3, and 5V0 supplies.
• VCLSIN-VCLSOUT > 1V, VOK fault
on the current limited switch at
the end of 250ms soft-start time
• Overvoltage, open LED fault on
LED step-up converter (current
mode only)
• LED cathode (PCS) short to
ground detected before BSTLX
switching (current mode only)
• LED cathode (PCS) short to LED
boost output, detected before
BSTLX switching (current mode
only)
• Missing or reversed output diode,
open BSTFB connection,
detected before BSTLX
switching.
• FLT goes to low and the regulator turns off immediately after fault detection. The
corresponding bits in FAULTSTATUS, OVERLOAD, and VOK registers are set.
• Setting CLRFLTS to 01h followed by CLRFLTS to 00h at any time clears all fault registers
bits, pulls FLT to high, and rearms the MAX8904 for subsequent fault detection.
• Fault detection is enabled for a regulator only if CLRFLTS=00h, and _EN=1 (The ADJ and
BST step-up regulators also require valid data to be programmed in the ADJSP and
BSTCSP/BSTVSP registers).
• The regulator restarts, fault registers are cleared, FLT goes to high, if the _EN bit is
toggled from 0 to 1.
• Toggling PWREN (highlowhigh) if PWREN is still high, or driving PWREN from low to
high resets all fault status and fault registers, pulls FLT to high, and causes the MAX8904
to restart the 1V2, 1V8, 3V3, and 5V0 supplies.
• Recycling power to the LVRPWR input of the internal linear regulator causes the MAX8904
to power up and remain in standby mode if PWREN is low. If PWREN is high, the MAX8904
attempts to start the 1V2, 1V8, 3V3, and 5V0 supplies.
Table 22. Fault Handling
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 37
FAULT TYPE FAULT RESPONSE AND RECOVERY
• BSTFB or LED anode shorted to
ground (an external 40V-rated
Schottky diode must be
connected from power ground to
BSTFB, as close as possible to
the BSTFB capacitor)
• FLT goes to low and BSTLX switching stop immediately after fault detection. The
corresponding bits in FAULTSTATUS, OVERLOAD registers are set. The BST regulator
turns off 250ms after the fault.
• Setting CLRFLTS to 01h followed by CLRFLTS to 00h at any time clears all fault registers
bits, pulls FLT to high, and rearms the MAX8904 for subsequent fault detection.
• Fault detection is enabled for a regulator only if CLRFLTS = 00h, and BSTEN = 1. Valid
data must be programmed in the BSTCSP/BSTVSP registers).
• The regulator restarts, fault registers are cleared, FLT goes to high, if the BSTEN bit is
toggled from 0 to 1.
• Toggling PWREN (highlowhigh) if PWREN is still high, or driving PWREN from low to
high resets all fault status and fault registers, pulls FLT to high, and causes the MAX8904
to restart the 1V2, 1V8, 3V3, and 5V0 supplies.
• Recycling power to the LVRPWR input of the internal linear regulator causes the MAX8904
to power up and remain in standby mode if PWREN is low. If PWREN is high, the
MAX8904 attempts to start the 1V2, 1V8, 3V3, and 5V0 supplies.
• Overload on 5V0, ADJ, BST.
VCLSIN-VCLSOUT > 1V, VOK fault
on the current limiter in normal
operation.
• Output voltage < VOK falling
threshold on 5V0, ADJ, BST
(voltage mode only), (detected
after soft-start time plus 2ms
delay for 5V0, ADJ, and 1.024ms
for BST.
• FLT goes to low immediately after fault detection, and fault status and fault registers
are set.
• For tFLT ≥ 250ms, the _EN bit is set to 0, and the regulator turns off.
• Setting CLRFLTS to 01h followed by CLRFLTS to 00h at any time clears all fault status and
fault register bits, pulls FLT to high, and rearms the MAX8904 for subsequent fault
detection.
• FLT goes to low, fault status and fault register information of a tFLT < 250ms momentary
fault event is latched until the command of setting CLRFLTS to 01h is issued.
• Momentary tFLT < 250ms faults do not cause the regulator to turn off.
• Fault detection is enabled for a regulator only if CLRFLTS = 00h, and _EN = 1. The ADJ
and LED boost regulators also require valid data to be programmed in the ADJSP and
BSTCSP or BSTVSP registers.
• Regulator restarts and fault register and fault status register are cleared, FLT goes to high,
if the _EN bit is toggled (0 to 1).
• Toggling PWREN (highlowhigh) if PWREN is still high, or driving PWREN from low to
high resets all fault status and fault registers, pulls FLT to high, and causes the MAX8904
to restart the 1V2, 1V8, 3V3, and 5V0 supplies.
• Recycling power to the LVRPWR input of the internal linear regulator causes the MAX8904
to power up and remain in standby mode if PWREN is low. If PWREN is high, the
MAX8904 attempts to start the 1V2, 1V8, 3V3, and 5V0 supplies.
• Input overvoltage at OVPWR
• If an overvoltage event occurs in normal operation, the MAX8904 turns off the external
n-MOSFET through OVGATE immediately.
• FLT goes to low and OVIN goes to 1 in fault status register immediately after fault
detection.
• If the input voltage falls below the voltage of VOV - VHYS_OV, the OVP n-MOSFET turns
back on. However, FLT stays low and OVIN stays high until the MAX8904 receives the
command setting CLRFLTS to 01h.
• Setting CLRFLTS to 01h followed by CLRFLTS to 00h at any time clears all fault status and
fault register bits, pulls FLT to high, and rearms the MAX8904 for subsequent fault
detection.
• If overvoltage persists, the OV n-MOSFET remains off, and the MAX8904 regulator input
supply decays to 2.85V, and the MAX8904 turns off at this point.
• If an overvoltage condition occurs at startup, the external OVP n-MOSFET does not turn on
and the MAX8904 does not startup. Therefore no fault information is stored.
Table 22. Fault Handling (continued)
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
38 ______________________________________________________________________________________
FAULT TYPE ACTIONS
Overload or short circuit on 1V2,
1V8, 3V3, 5V0, ADJ, and BST
OLFLT is set to 1 in the FAULTSTATUS register, and corresponding _OL is set to 1 in the
OVERLOAD register.
VOK fault on 1V2, 1V8, 3V3, 5V0,
ADJ, BST (voltage mode only), and
current limiter
VOKFLT is set to 1 in the FAULTSTATUS register, and corresponding _OK is set to 0 in the
VOK register.
Overvoltage on BST, open or
reversed output diode, open BSTFB
connection, PCS shorted to ground,
PCS shorted to BST output
FAULTSTATUS register:
BSTFLT1 and BSTFLT0 are set to 00 if none of the listed faults has occurred.
BSTFLT1 and BSTFLT0 are set to 01 for overvoltage on BST step-up converter (current mode
only).
BSTFLT1 and BSTFLT0 are set to 10 for open or reversed output diode, or open BSTFB
connection (detected at startup before BSTLX switching).
BSTFLT1 and BSTFLT0 are set to 11 for PCS shorted to ground or PCS shorted to BST output
(current mode only, detected at startup before BSTLX switching).
Input overvoltage fault OVIN is set to 1 in the FAULTSTATUS register.
Input overcurrent fault OCIN is set to 1 in the FAULTSTATUS register for CSFLGEN = 1.
+120°C overtemperature flag TMP120 is set to 1 in the FAULTSTATUS register.
Table 23. Summary of MAX8904 Fault Status Register and Fault Register Actions
D7 D6 D5 D4 D3 D2 D1 D0 —
Chip ID
MSB ———
Chip ID
LSB
Chip Rev
MSB —Chip Rev
LSB Read only
Table 24. Device Identification Register (10h)
Device Identification Register
Device identification register (10h) identifies the chip ID
and revision, and is shown in Table 24. It is a read-only
register.
CLRFLTS Register
The MAX8904 clears all fault registers when the CLRFLTS
register (11h) is set to 01h, to allow the processor to
reset the fault and restart the system. When a fault
occurs, the host processor is interrupted and enters its
interrupt service routine (ISR). It masks the interrupt,
services the fault by reading the MAX8904 registers,
and may clear the fault(s) to recheck for fault(s) or
immediately act upon the faults, and unmasks the inter-
rupt. If the fault is still present, the FLT signal goes low
and the host processor enters its ISR again. CLRFLTS
must be set to 00h to rearm fault detection.
FAULT TYPE FAULT RESPONSE AND RECOVERY
• 120°C Overtemperature Flag
• The MAX8904 sets the TMP120 bit in fault status register and pulls FLT low if the internal
temperature reaches +120°C (typ). All converters latch off when the temperature reaches
+150°C (typ), and the MAX8904 goes into standby mode. In this mode, the internal linear
regulator is turned off and the I2C interface is no longer powered. Note that PWREN may
still be held high in this mode.
• Toggling PWREN (highlowhigh) or recycling MAX8904 power at LVRPWR allows the
MAX8904 to come out of thermal shutdown.
• Input Overcurrent
• If CSFLGEN is high, then the OCIN bit in the fault status register is set to 1 in the fault
status register, and FLT goes high. If CSFLGEN is low, no action is taken.
• S etti ng C LRFLTS to 01h fol l ow ed b y C LRFLTS to 00h at any ti m e cl ear s al l faul t status and faul t
r eg i ster b i ts, p ul l s FLT to hi g h, and r ear m s the M AX 8904 for sub seq uent faul t d etecti on.
Table 22. Fault Handling (continued)
Overvoltage and Reverse
Polarity Protection
The MAX8904 has an overvoltage protection block as
shown in Figure 8. This block has its own UVLO thresh-
olds, linear regulator, and reference. It essentially oper-
ates as a stand-alone overvoltage protection block.
Applying an external voltage greater than 4V (typ) to
OVPWR causes the overvoltage protection block to
commence operation. At this time, the external n-MOS-
FET has not yet been turned on. After a 30ms delay, if
the OVPWR voltage is less than 13.65V (typ), the over-
voltage charge pump gate drive is powered up and
OVGATE turns on the external n-MOSFET. Otherwise, if
the OVPWR voltage is greater than 13.65V, OVGATE
holds the n-MOSFET off.
After the OVP n-MOSFET (Q1) powers up, the system
voltage VINT comes up and powers the internal LVR linear
regulator and all power inputs (_IN). When VIN exceeds
the UVLO (rising), the MAX8904 waits for a logic-high sig-
nal on PWREN to start up the 1V2, 1V8, 3V3 and 5V0 sup-
plies, provided VIN is greater than 5.6V (typ).
Reverse polarity protection down to -28V is provided by
use of an external p-MOSFET (Q2) to protect downstream
circuitry. When the input voltage goes negative, RPGATE
goes high to turn off the external p-MOSFET. When the
input voltage rises in the positive direction to a maximum
of +30V, RPGATE pulls low and turns on the p-MOSFET.
When an overvoltage event of up to +30V occurs, an
internal clamp protects the gate of the p-MOSFET from
excessive voltage such that the VGATE-SOURCE voltage of
the external p-MOSFET (Q2) does not exceed 16V (typ).
Current Limited Switch
The current limited switch (CLS) allows the MAX8904 to
control the amount of current that an external device
draws from the supply voltage. The CLS is connected
between the input supply voltage and the target periph-
eral device. It provides a peripheral current of at least
425mA, and is protected under short-circuit conditions. A
short-circuit condition that lasts greater than 250ms latch-
es the CLS off. The CLS can be enabled and disabled
through the Enable register and can be selected for
immediate power-fail shutdown in the Shutdown register.
An internal thermal loop protects the CLS from an over-
load or short-circuit fault that causes excessive power
dissipation across the switch. It reduces the current
delivered by the CLS if the die temperature rises above
a preset temperature threshold (+120°C) and thus limits
the power dissipation in the CLS. The thermal loop is
enabled only when VCLSIN - VCLSOUT > 1V.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 39
DC
INPUT
OVPWR
Q2
LVROUT
LVR
OVERVOLTAGE
AND REVERSE
POLARITY
SENSE
REG2
5V0FB
UVLO
OVGATE
_IN PINS
CS-
CS+
BULK
CAPACITOR
RPGATE
LVRPWR
Q1
MAX8904
VIN
VINT
15mΩ
Figure 8. Overvoltage and Reverse Polarity Protection
MAX8904
With bit CLSEN in Enable register set to 1, the 250ms
timer is activated. During normal operation, if VCLSIN -
VCLSOUT > 1V, FLT is set, CLSOK bit is set to 0, the
VOKFLT bit is set to 1, and the 250ms timer is started. If
VCLSIN - VCLSOUT < 1V before the timer expires, the
timer is reset and the IC resumes normal operation. The
fault information is preserved and the status of FLT,
CLSOK, and VOKFLT remain unchanged until the I2C
receives a CLRFLTS command. If VCLSIN - VCLSOUT >
1V after 250ms, the CLS is turned off, FLT is asserted,
the CLSOK bit is set to 0, the VOKFLT bit is set to 1,
and the CLSEN is set to 0. The MAX8904 needs a
CLRFLTS command to clear the fault information in the
FAULTSTATUS and VOK registers and pull FLT high.
Current-Sense Amplifier
The current-sense amplifier measures the differential volt-
age across a current-sense resistor and generates an
analog voltage proportional to the current-sense resistor
differential voltage. This voltage is clamped internally to a
maximum of 1.25V. The CSA has two programmable-gain
settings, 20V/V and 40V/V. When used with a 15mΩcur-
rent-sense resistor, it allows full-scale (1.2V) output for 4A
and 2A currents, respectively. The CSA sets the CSAOL
bit in the Overload register if the maximum current is
exceeded. The CSA can be enabled and disabled
through the Enable register and can be selected for
immediate power-fail shutdown in the Shutdown register.
Open-Drain Comparator
The open-drain comparator (CMP) is an uncommitted,
14V open-drain output comparator with 20mA of sinking
capability. The CMP can be used for various functions
such as independent print-head temperature monitoring,
voltage comparison, driving a Piezo Buzzer, or a 20mA
load sinking. The CMP can be enabled and disabled
through the Enable register and can be selected for
immediate power-fail shutdown in the Shutdown register.
FLT
Interrupt
The FLT interrupt is an active-low output that indicates
any fault condition. The fault condition can be either inter-
nal (overtemperature) or external (overloaded output).
For certain types of faults such as an overload fault, when
FLT is driven low, an internal 250ms timer is started.
When the timer expires the MAX8904 disables the
affected power converter. During the 250ms, from the
time of the interrupt until the time the converter is dis-
abled, the host processor can respond to the interrupt
and take an action such as shutting down the power
converter or some other appropriate action, such as,
reducing the load current. For other emergency faults
such as an overvoltage fault, there is no 250ms timer
related operation, FLT is asserted and the converter is
immediately turned off.
ADJ Step-Down Converter
The ADJ power converter is an adjustable voltage step-
down converter that can be adjusted over a 6-bit range
from 3.0V to 5.067V, in 33.3mV increments. The ADJ
power converter is intended to be used for powering var-
ious radio modules, such as Wi-Fi, GPRS, and CDMA.
The ADJ supply is designed to support a 2A peak and
1.414A RMS output current load. An L-C filter may be
connected to the output capacitor to attenuate the
switching frequency ripple component to within radio
module specification.
Power-Up/Down Sequencing for
1V2, 1V8, 3V3, and 5V0 Supplies
The PWREN signal initiates power-up of the default volt-
age rails on the MAX8904 if LVRPWR (the input of inter-
nal linear regulator) exceeds 5.6V (typ). The default
power-up rails are 1V2, 1V8, 3V3, and 5V0. If the 1V2
rail is not used, pulling 1V2FB to LVRIN5 configures the
MAX8904 to operate without its 1V2 rail, with the corre-
sponding power sequencing option. Power-down
sequencing operates in the reverse sequence of
power-up after PWREN goes low.
Figures 9 and 10 show the two power-up/down
sequencing cases. Table 25 shows the sequencing
truth table. The ADJ and BST supplies can be turned
on by the host processor any time after the 3V3 supply
reaches its regulation, but all rails and MAX8904 blocks
are shut down when PWREN pulls low. Note that there
is a fixed time delay (D5, 3.6ms, typ) between the 1V8
supply reaching its VOK threshold and the 3V3 supply
start time.
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
40 ______________________________________________________________________________________
STATE OF 1V2FB
DURING D2 SEQUENCING MODE
01V2, 1V8, and 3V3 sequenced,
followed by 5V0
11V8 and 3V3 sequenced, followed
by 5V0
Table 25. Sequencing Truth Table
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 41
1V2FB
1V8FB
3V3FB
5V0FB
PWREN
LVRIN5V D3 D4 D8 D8 D8
D5
D6
D7
ADJFB
BSTFB
D2
D_UP
D_UP D_DOWN
Figure 9. Power-Up/Down Sequencing with 1V2 Rail Used (See Table 26 for Timing Details)
D4 D8 D8
D5 D7
D6
1V8FB
3V3FB
5V0FB
PWREN
1V2FB
LVRIN5V
ADJFB
BSTFB
Figure 10. Power-Up/Down Sequencing Without 1V2 Rail Used (See Table 26 for Timing Details)
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
42 ______________________________________________________________________________________
Applications Information
Inductors for Step-Down
and BST Converters
The MAX8904 power converters are optimized to work
with specific values of inductors. Either 4.7µH or 4.3µH
inductors should be used for the 1V2, 1V8, 3V3, and
ADJ step-down converters. A 10µH inductor should be
used for the 5V0 step-down converter. Ensure that the
inductor saturation current rating exceeds the peak
inductor current, and the rated maximum DC inductor
current exceeds the maximum output current. For most
applications, use an inductor with a DC current rating
1.25 times the maximum required output current. For
maximum efficiency, the inductor DC resistance should
be as low as possible. A 10µH inductor is recommend-
ed for the BST step-up converter. See Table 27 for rec-
ommended inductor specifications.
Input and Output Capacitors
The input capacitor in a DC-DC converter reduces cur-
rent peaks drawn from the input power source and
reduces switching noise in the controller. The imped-
ance of the input capacitor at the switching frequency
should be less than the input source’s output imped-
ance so that high-frequency switching currents do not
pass through the input source. The DC-DC converter
output capacitor keeps output ripple small and ensures
control-loop stability. The output capacitor must also
have low impedance at the switching frequency.
Ceramic capacitors with X5R or X7R dielectrics are
highly recommended for both input and output capaci-
tors due to their small size, low ESR, and small temper-
ature coefficients. It should be noted that the effective
capacitance that can be obtained in ceramic capaci-
tors should be derated based on their operating DC
bias (maximum converter input voltage in the case of
input capacitors and maximum converter output volt-
age in the case of output capacitors). See Table 27 for
recommended capacitor specifications based on the
considerations outlined above.
CLS Output Capacitor
To prevent the MAX8904 from sensing a startup fault
condition, the maximum capacitance that should be
connected to the CLSOUT pin is given by the following
equation:
CCLSOUT(MAX) <(425 - ILOAD) x 225/VCLSIN(MAX)
where ILOAD is the load current on CLSOUT in mA,
VCLSIN(MAX) is the maximum input voltage at CLSIN in
volts, and CCLSOUT is in µF.
Bootstrap Capacitors
Connect a 0.1µF low-ESR ceramic capacitor between
the _LX and _BST for all the step-down converters. The
bootstrap capacitor provides the gate-drive voltage for
the internal high-side MOSFET. X7R or X5R grade
dielectrics are recommended due to their stable values
over temperature.
DELAY TIME (ms)
D2 (response time) < 1
D3 (1V/ms ramp rate) 1.2
D4 (1V/ms ramp rate) 1.8
D5 (fixed delay) 3.6
D6 (1V/ms ramp rate) 3.4
D7 (1V/ms ramp rate) 5
D8 (estimated voltage decay time) 15
D_UP (maximum power-up sequence) 11.6 for all supplies, 10ms for 1V2, 1V8, and 3V3
D_DOWN (estimated voltage decay time) 45
Table 26. Delay Time
PCB Layout and Routing
High switching frequencies and relatively large peak
currents make the PCB layout a very important aspect
of power converter design. Good design minimizes
ground bounce, excessive EMI on the feedback paths,
and voltage gradients in the ground plane, which can
result in instability or regulation errors.
A separate low-noise analog ground plane containing
the reference, linear regulator, signal ground, and
GND must connect to the power-ground plane at only
one point to minimize the effects of power-ground cur-
rents. Connect GND to the exposed pad directly under
the IC. Use multiple tightly spaced vias to the ground
plane under the exposed pad to help cool the IC.
Position the input capacitors from _IN to the power
ground plane as close as possible to the IC. Connect
the inductors and output capacitors as close as possi-
ble to the IC and keep the traces short, direct, and
wide. Refer to the MAX8904 evaluation kit for the rec-
ommended PCB layout.
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
______________________________________________________________________________________ 43
COMPONENT PART NUMBER PART DESCRIPTION
L1 TOKO, DE3518 Series, 1127AS-100M Inductor, SMT 10µH, 20%, 145mΩ DCR, 1.2A
L2, L4 TOKO, DE3518 Series, 1127AS-4R7M Inductors, SMT 4.7µH, 20%, 60mΩ DCR, 1.75A
L3, L5 TOKO, DE4518 Series, 1124BS-4R3M Inductors, SMT 4.3µH, 20%, 70mΩ DCR, 2.65A
L6 TOKO, DE4518 Series, 1124BS-100M Inductor, SMT 10µH, 20%, 120mΩ DCR, 1.75A
C1 Murata, GRM188R71C224KA01D Ceramic capacitor, 0.22µF, 10%, 16V, X7R, 0603
C2, C3, C10 Murata, GRM188R70J105KA01D Ceramic capacitors, 1.0µF, 10%, 6.3V, X7R, 0603
C4 Taiyo Yuden, EMK212BJ105KG-T Ceramic capacitor, 1.0µF, 10%, 16V, X7R, 0805
C5 Taiyo Yuden, EMK212BJ225KG-T Ceramic capacitor, 2.2µF 10%, 16V, X7R, 0805
C6 (current mode) Taiyo Yuden, UMK316B7105KL-T Ceramic capacitor, 1.0µF, 10%, 50V, X7R, 1206
C6 (voltage mode) Murata GRM32DR61E106KA12L Ceramic capacitor, 10µF, 10%, 25V, X5R, 1210
C7, C15, C18, C21, C24 Taiyo Yuden, TMK212BJ475KG Ceramic capacitors, 4.7µF, 10%, 25V, X7R, 0805
C8 Taiyo Yuden, AMK107BJ226MA Ceramic capacitor, 2 x 22µF, 20%, 4V, X5R, 0603
C9, C12, C13, C16, C19, C22 Taiyo Yuden, EMK105B7104KV Ceramic capacitors, 0.1µF, 10%, 16V, X7R, 0402
C11 Sanyo, 16CE680AX Electrolytic capacitor, SMT 680µF, 20%, 16V
C14 Taiyo Yuden, JMK316BJ226KL Ceramic capacitor, 2 x 22µF 10%, 6.3V, X5R, 1206
C17 Taiyo Yuden, JMK212BJ226KG Ceramic capacitor, 22µF, 10%, 6.3V, X5R, 0805
C20 Taiyo Yuden, JMK316BJ226KL Ceramic capacitor, 2 x 22µF, 10%, 6.3V, X5R, 1206
C23 Taiyo Yuden, JMK316BJ226KL Ceramic capacitor, 22µF, 10%, 6.3V, X5R, 1206
C25 Taiyo Yuden, TMK105B7223KV Ceramic capacitor, 0.022µF, 10%, 25V, X7R, 0402
D1 ON Semiconductor, MBR0540T1G Schottky diode, 40V, 0.5A, SOD123
D2 (the MAX8904 is protected for
short-circuit fault at startup, D2
required only for short-circuit
protection in normal operation)
ON Semiconductor, MBR0540T1G Schottky diode, 40V, 0.5A, SOD123
Q1, Q2 Fairchild Semiconductor, FDS8962C Dual n-/p-MOSFETs, 30V, 8-pin SO
R1 Yageo, RC0402FR-0710RL Resistor, SMT 10.0Ω, 1/16W, 1%, 0402
R2 Vishay, WSL1206R0150FEA Resistor, 0.015Ω, 1/4W, 1%, 1206 SMD
R3 (the MAX8904 is protected for
PCS to BSTFB short fault at startup,
R3 required only for short PCS to
BSTFB short-circuit protection in
normal operation)
Yageo, RC0402FR-0710RL Resistor, SMT 10.0Ω, 1/16W, 1%, 0402
Table 27. Recommended Component Specifications (See Figure 1)
MAX8904
High-Efficiency Power-Management IC with I2C
Control for 2-Cell Li+ Battery Operated Devices
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
44
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
56 TQFN-EP T5677+2 21-0144
TOP VIEW
MAX8904
TQFN
+
15
17
16
18
19
20
21
22
23
24
25
26
27
28
5V0FB
5V0IN
5V0LX
5V0BST
GPIOPWR
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
CMPO
CS+
CS-
CLSIN
CLSOUT
PCS
BSTFB
BSTIN
BSTSW
BSTLX
1V8BST
1V8LX
1V8IN
1V8FB
TEST
48
47
46
45
44
43
54
53
56
55
52
51
50
49
1 2 3 4 5 6 7 8 9 1011121314
42 41 40 39 38 37 36 35 34 33 32 31 30 29
LVRIN5V
LVROUT
LVRPWR
GND
REF
ADJFB
ADJIN
ADJLX2
ADJLX1
ADJBST
OVGATE
OVPWR
RPGATE
CSOUT
3V3IN
3V3FB
CMPI
3V3LX
3V3BST
SCL
SDA
1V2BST
1V2LX
1V2IN
1V2FB
FLT
SHDN
PWREN
Pin Configuration
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
