DS1874T+T&R - Maxim Integrated

General Description

The DS1874 controls and monitors all functions for SFF,

SFP, and SFP+ modules including all SFF-8472 func-

tionality. The combination of the DS1874 with the

MAX3798/MAX3799 laser driver/limiting amplifier pro-

vides APC loop, modulation current control, and eye

safety functionality. The DS1874 continuously monitors

for high output current, high bias current, and low and

high transmit power to ensure that laser shutdown for

eye safety requirements are met without adding external

components. Six ADC channels monitor VCC, tempera-

ture, and four external monitor inputs (MON1–MON4)

that can be used to meet all monitoring requirements.

MON3 is differential with support for common mode to

VCC. Two digital-to-analog (DAC) outputs with tempera-

ture-indexed lookup tables (LUTs) are available for addi-

tional monitoring and control functionality.

Applications

SFF, SFP, and SFP+ Transceiver Modules

Features

♦Meets All SFF-8472 Control and Monitoring

Requirements

♦Laser Bias Controlled by APC Loop and

Temperature LUT to Compensate for Tracking

Error

♦Laser Modulation Controlled by Temperature LUT

♦Six Analog Monitor Channels: Temperature, VCC,

MON1–MON4

MON1–MON4 Support Internal and External

Calibration

Scalable Dynamic Range

Internal Direct-to-Digital Temperature Sensor

Alarm and Warning Flags for All Monitored

Channels

♦Two 9-Bit Delta-Sigma Outputs with 36 Entry

Temperature LUTs

♦Digital I/O Pins: Five Inputs, Five Outputs

♦Comprehensive Fault-Measurement System with

Maskable Laser Shutdown Capability

♦Flexible, Two-Level Password Scheme Provides

Three Levels of Security

♦256 Additional Bytes Located at A0h Slave

Address

♦I2C-Compatible Interface

♦3-Wire Master to Communicate with the MAX3798/

MAX3799 Laser Driver/Limiting Amplifier

♦+2.85V to +3.9V Operating Voltage Range

♦-40°C to +95°C Operating Temperature Range

♦28-Pin TQFN (5mm x 5mm) Package

DS1874

________________________________________________________________

Maxim Integrated Products

THIN QFN

(5mm

5mm

0.8mm)

TOP VIEW

SCL

TXF

LOS

IN1

TXD

RSELOUT

DAC2

REFIN

GND

MON2

VCC

SCLOUT

4567

2021 19 17 16 15

SDAOUT

LOSOUT

MON3P

MON4

TXDOUT

RSEL

SDA DAC1

28 8

OUT1 GND

CSELOUT

23 13 MON3N

VCC

22 14 MON1

N.C.

DS1874

*EP

*EXPOSED PAD.

Pin Configuration

Ordering Information

19-4691; Rev 0; 6/09

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Denotes a lead(Pb)-free/RoHS-compliant package.

T&R = Tape and reel.

EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

DS1874T+ -40°C to +95°C 28 TQFN-EP*

DS1874T+T&R -40°C to +95°C 28 TQFN-EP*

SFP+ Controller with Digital LDD Interface

DS1874
2 _______________________________________________________________________________________
Absolute Maximum Ratings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended Operating Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DC Electrical Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
DAC1, DAC2 Electrical Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Quick-Trip Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Analog Voltage Monitoring Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Digital Thermometer Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
AC Electrical Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Timing Characteristics (Control Loop and Quick Trip)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3-Wire Digital Interface Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
I2C AC Electrical Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Nonvolatile Memory Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Typical Operating Characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Pin Description  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Block Diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Typical Operating Circuit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
MAX3798/MAX3799 DAC Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
BIAS Register/APC Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
MODULATION Control  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
BIAS and MODULATION Control During Power-Up  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
BIAS and MODULATION Registers as a Function of Transmit Disable (TXD)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
APC and Quick-Trip Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Monitors and Fault Detection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Monitors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Five Quick-Trip Monitors and Alarms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Six ADC Monitors and Alarms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ADC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Right-Shifting ADC Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Enhanced RSSI Monitoring (Dual-Range Functionality)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Low-Voltage Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Power-On Analog (POA)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Delta-Sigma Outputs (DAC1 and DAC2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
LOS, LOSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
IN1, RSEL, OUT1, RSELOUT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
TXF, TXD, TXDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
TABLE OF CONTENTS
SFP+ Controller with Digital LDD Interface

DS1874
_______________________________________________________________________________________ 3
Transmit Fault (TXF) Output  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Die Identification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3-Wire Master for Controlling the MAX3798/MAX3799  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Protocol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3-Wire Interface Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
DS1874 and MAX3798/MAX3799 Communication  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Normal Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Manual Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Initialization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
MAX3798/MAX3799 Register Map and DS1874 Corresponding Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
I2C Communication  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
I2C Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
I2C Protocol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Shadowed EEPROM  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Lower Memory Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 01h Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 02h Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 04h Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 05h Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 06h Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 07h Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 08h Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Auxiliary A0h Memory Register Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Lower Memory Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 01h Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 02h Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 04h Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Table 06h Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 07h Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Table 08h Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Auxiliary Memory A0h Register Descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Applications Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
SDA and SCL Pullup Resistors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Package Information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
TABLE OF CONTENTS (continued)
SFP+ Controller with Digital LDD Interface

DS1874
SFP+ Controller with Digital LDD Interface
4 _______________________________________________________________________________________
Figure 1. Modulation LUT Loading to MAX3798/MAX3799 MOD DAC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 2. Power-Up Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 3. TXD Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 4. APC Loop and Quick-Trip Sample Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 5. ADC Round-Robin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 6. MON3 Differential Input for High-Side RSSI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7. RSSI Flowchart  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 8. Low-Voltage Hysteresis Example  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 9. Recommended RC Filter for DAC1/DAC2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 10. Delta-Sigma Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 11. DAC1/DAC2 LUT Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 12. Logic Diagram 1  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 13. Logic Diagram 2  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 14a. TXF Nonlatched Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 14b. TXF Latched Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 15. 3-Wire Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 16. 3-Wire State Machine  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 17. I2C Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 18. Example I2C Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 19. Memory Map  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 1. Acronyms  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 2. Update Rate Timing  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 3. ADC Default Monitor Full-Scale Ranges  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 4. MON3 Hysteresis Threshold Values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 5. MON3 Configuration Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
LIST OF FIGURES
LIST OF TABLES

DS1874

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on MON1–MON4, RSEL,

IN1, LOS, TXF, and TXD Pins

Relative to Ground .................................-0.5V to (VCC + 0.5V)*

Voltage Range on VCC, SDA, SCL, OUT1,

RSELOUT, and LOSOUT Pins

Relative to Ground.................................................-0.5V to +6V

Operating Temperature Range ...........................-40°C to +95°C

Programming Temperature Range .........................0°C to +95°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature...........................Refer to the IPC/JEDEC

J-STD-020 Specification.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Main Supply Voltage VCC (Note 1) +2.85 +3.9 V

High-Level Input Voltage

(SDA, SCL, SDAOUT) VIH:1 0.7 x

VCC

VCC +

0.3 V

Low-Level Input Voltage

(SDA, SCL, SDAOUT) VIL:1 -0.3 0.3 x

VCC V

High-Level Input Voltage

(TXD, TXF, RSEL, IN1, LOS) VIH:2 2.0 VCC +

0.3 V

Low-Level Input Voltage

(TXD, TXF, RSEL, IN1, LOS) VIL:2 -0.3 +0.8 V

DC ELECTRICAL CHARACTERISTICS

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

Subject to not exceeding +6V.

RECOMMENDED OPERATING CONDITIONS

(TA= -40°C to +95°C, unless otherwise noted.)

ABSOLUTE MAXIMUM RATINGS

SFP+ Controller with Digital LDD Interface

_______________________________________________________________________________________ 5

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Current ICC (Notes 1, 2) 2.5 10 mA

Output Leakage

(SDA, SDAOUT, OUT1,

RSELOUT, LOSOUT, TXF)

ILO 1 μA

IOL = 4mA 0.4

Low-Level Output Voltage (SDA,

SDAOUT, SCLOUT, CSELOUT,

OUT1, RSELOUT, LOSOUT,

TXDOUT, DAC1, DAC2, TXF)

VOL

IOL = 6mA 0.6

High-Level Output Voltage

(DAC1, DAC2, SCLOUT,

SDAOUT, CSELOUT, TXDOUT)

VOH I

OH = 4mA VCC -

0.4 V

TXDOUT Before EEPROM Recall 10 100 nA

DAC1 and DAC2 Before LUT

Recall Figure 11 10 100 nA

Input Leakage Current

(SCL, TXD, LOS, RSEL, IN1) ILI 1 μA

Digital Power-On Reset POD 1.0 2.2 V

Analog Power-On Reset POA 2.0 2.75 V

DS1874

SFP+ Controller with Digital LDD Interface

6 _______________________________________________________________________________________

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

ADC Resolution 13 Bits

Input/Supply Accuracy

(MON1–MON4, VCC)ACC At factory setting 0.25 0.50 %FS

Update Rate for Temperature,

MON1–MON4, and VCC tRR 64 75 ms

Input/Supply Offset

(MON1–MON4, VCC)VOS (Note 3) 0 5 LSB

MON1–MON4 2.5

VCC 6.5536 V

Factory Setting

MON3 Fine

(Note 4)

312.5 μV

ANALOG VOLTAGE MONITORING CHARACTERISTICS

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MON2, TXP HI, TXP LO Full-

Scale Voltage VAPC 2.5 V

HBIAS, LOS Full-Scale Voltage 1.25 V

MON2 Input Resistance 35 50 65 k

Resolution 8 Bits

Error TA = +25°C ±2 %FS

Integral Nonlinearity -1 +1 LSB

Differential Nonlinearity -1 +1 LSB

Temperature Drift -2.5 +2.5 %FS

LOS Offset -5 mV

ANALOG QUICK-TRIP CHARACTERISTICS

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Main Oscillator Frequency fOSC 5 MHz

Delta-Sigma Input-Clock

Frequency fDS f

OSC/2 MHz

Reference Voltage Input (REFIN) VREFIN Minimum 0.1μF to GND 2 VCC V

Output Range 0 VREFIN V

Output Resolution See the Delta-Sigma Outputs (DAC1 and

DAC2) section for details. 9 Bits

Output Impedance RDS 35 100 

DAC1, DAC2 ELECTRICAL CHARACTERISTICS

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

DS1874

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCLOUT Clock Frequency fSCLOUT (Note 13) 833 kHz

SCLOUT Duty Cycle t3WDC 50 %

SDAOUT Setup Time tDS 100 ns

SDAOUT Hold Time tDH 100 ns

CSELOUT Pulse-Width Low tCSW 500 ns

CSELOUT Leading Time Before

the First SCLOUT Edge tL 500 ns

CSELOUT Trailing Time After the

Last SCLOUT Edge tT (Note 14) 500 ns

SDAOUT, SCLOUT Load CB3W Total bus capacitance on one line (Note 14) 10 pF

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output-Enable Time Following POA tINIT (Note 8) 20 ms

Binary Search Time tSEARCH (Note 12) 8 10 BIAS

Samples

3-WIRE DIGITAL INTERFACE SPECIFICATION

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted. See Figure 15.)

SFP+ Controller with Digital LDD Interface

_______________________________________________________________________________________ 7

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TXD Enable tOFF From  TXD (Notes 5, 6) 5 μs

Recovery from TXD Disable

(Figure 14) tON From  TXD (Notes 5, 7) 1 ms

Recovery After Power-Up tINIT_DAC From  VCC > VCC LO alarm (Notes 5, 8) 20 ms

tINITR1 From TXD 131

Fault Reset Time (to TXF = 0) tINITR2 From  VCC > VCC LO alarm (Note 8) 161 ms

Fault Assert Time (to TXF = 1) tFAULT After HTXP, LTXP, HBATH, IBIASMAX

(Note 9) 6.4 55 μs

LOSOUT Assert Time tLOSS_ON LLOS (Notes 9, 10) 6.4 55 μs

LOSOUT Deassert Time tLOSS_OFF HLOS (Notes 9, 11) 6.4 55 μs

TIMING CHARACTERISTICS (CONTROL LOOP AND QUICK TRIP)

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

AC ELECTRICAL CHARACTERISTICS

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Thermometer Error TERR -40°C to +95°C -3 +3 °C

DIGITAL THERMOMETER CHARACTERISTICS

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, unless otherwise noted.)

Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.

Note 2: Inputs are at supply rail. Outputs are not loaded.

Note 3: This parameter is guaranteed by design.

Note 4: Full-scale is user programmable.

Note 5: The DACs are the bias and modulation DACs found in the MAX3798/MAX3799 that are controlled by the DS1874.

Note 6: The DS1874 is configured with TXDOUT connected to the MAX3798/MAX3799 DISABLE input.

Note 7: This includes writing to the modulation DAC and the initial step written to the bias DAC.

Note 8: A temperature conversion is completed and the modulation register value is recalled from the LUT and VCC has been

measured to be above VCC LO alarm.

Note 9: The timing is determined by the choice of the update rate setting (see Table 02h, Register 88h).

Note 10: This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.

Note 11: This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.

Note 12: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four

steps, the bias current will be within 3% within the time specified by the binary search time. See the

BIAS and MODULA-

TION Control During Power-Up

section.

Note 13: I2C interface timing shown is for fast mode (400kHz). This device is also backward compatible with I2C standard mode

timing.

Note 14: CB—the total capacitance of one bus line in pF.

Note 15: EEPROM write begins after a STOP condition occurs.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SCL Clock Frequency fSCL (Note 13) 0 400 kHz

Clock Pulse-Width Low tLOW 1.3 μs

Clock Pulse-Width High tHIGH 0.6 μs

Bus-Free Time Between STOP and START

Condition tBUF 1.3 μs

START Hold Time tHD:STA 0.6 μs

START Setup Time tSU:STA 0.6 μs

Data Out Hold Time tHD:DAT 0 0.9 μs

Data In Setup Time tSU:DAT 100 ns

Rise Time of Both SDA and SCL Signals tR (Note 14) 20 + 0.1CB 300 ns

Fall Time of Both SDA and SCL Signals tF (Note 14) 20 + 0.1CB 300 ns

STOP Setup Time tSU:STO 0.6 μs

EEPROM Write Time tW (Note 15) 20 ms

Capacitive Load for Each Bus Line CB 400 pF

DS1874

SFP+ Controller with Digital LDD Interface

8 _______________________________________________________________________________________

NONVOLATILE MEMORY CHARACTERISTICS

(VCC = +2.85V to +3.9V, unless otherwise noted.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

At +25°C 200,000

EEPROM Write Cycles At +85°C 50,000

I2C AC ELECTRICAL CHARACTERISTICS

(VCC = +2.85V to +3.9V, TA= -40°C to +95°C, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted. See Figure 17.)

DS1874

SFP+ Controller with Digital LDD Interface

_______________________________________________________________________________________

Typical Operating Characteristics

(VCC = +2.85V to +3.9V, TA= +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

DS1874 toc01

VCC (V)

SUPPLY CURRENT (mA)

3.853.603.10 3.35

1.7

1.9

2.1

2.3

2.7

2.5

2.9

1.5

2.85

SDA = SCL = VCC

+95°C

-40°C

+25°C

SUPPLY CURRENT vs. TEMPERATURE

DS1874 toc02

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

806040200-20

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.0

-40

SDA = SCL = VCC

VCC = 3.9V

VCC = 2.85V

VCC = 3.3V

MON1–MON4 INL

DS1874 toc03

MON1–MON4 INPUT VOLTAGE (V)

MON1–MON4 INL (LSB)

2.01.51.00.5

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

0 2.5

USING FACTORY-PROGRAMMED

FULL-SCALE VALUE OF 2.5V

MON1–MON4 DNL

DS1874 toc04

MON1–MON4 INPUT VOLTAGE (V)

MON1–MON4 DNL (LSB)

2.01.51.00.5

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

0 2.5

USING FACTORY-PROGRAMMED

FULL-SCALE VALUE OF 2.5V

DAC1 AND DAC2 DNL

DS1874 toc05

DAC1 AND DAC2 POSITION (DEC)

DAC1 AND DAC2 DNL (LSB)

500400300200100

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

1.0

-1.0

DAC1 AND DAC2 INL

DS1874 toc06

DAC1 AND DAC2 POSITION (DEC)

DAC1 AND DAC2 INL (LSB)

500400100 200 300

-1.5

-1.0

-0.5

0.5

1.0

1.5

2.0

-2.0

DS1874

SFP+ Controller with Digital LDD Interface

10 ______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1 RSELOUT Rate-Select Output

2 SCL I2C Serial-Clock Input

3 SDA I2C Serial-Data Input/Output

4 TXF Transmit-Fault Input and Output. The output is open drain.

5 LOS Loss-of-Signal Input

6 IN1 Digital Input. General-purpose input with AS1 in SFF-8079 or RS1 in SFF-8431.

7 TXD Transmit-Disable Input

8, 17, 21 GND Ground Connection

9 RSEL Rate-Select Input

10 TXDOUT Transmit-Disable Output

11 MON4 External Monitor Input 4

12, 13 MON3P,

MON3N Differential External Monitor Input 3 and LOS Quick Trip

14 MON1 External Monitor Input 1 and HBATH Quick Trip

15, 23 VCC Power-Supply Input

16 MON2 External Monitor Input 2. Feedback voltage for APC loop and HTXP/LTXP quick trip.

18 REFIN Reference Input for DAC1 and DAC2

19, 20 DAC1, DAC2 Delta-Sigma Output 1/2

22 N.C. No Connection

24 CSELOUT

Chip-Select Output. Part of the 3-wire interface to the MAX3798/MAX3799 laser driver/limiting

amplifier.

25 SCLOUT

Serial-Clock Output. Part of the 3-wire interface to the MAX3798/MAX3799 laser driver/limiting

amplifier.

26 SDAOUT

Serial-Data Input/Output. Part of the 3-wire interface to the MAX3798/MAX3799 laser driver/limiting

amplifier.

27 LOSOUT Open-Drain Receive Loss-of-Signal Output

28 OUT1 Digital Output. General-purpose output with AS1 output in SFF-8079 or RS1 output in SFF-8431.

— EP Exposed Pad

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 11

Block Diagram

ANALOG MUX

MAIN MEMORY

EEPROM/SRAM

ADC CONFIGURATION/RESULTS,

SYSTEM STATUS/CONTROL BITS,

ALARMS/WARNINGS,

LOOKUP TABLES,

USER MEMORY

I2C

INTERFACE

3-WIRE

INTERFACE

TEMPERATURE

SENSOR

APC

INTEGRATOR

SEE

FIGURE 12

POWER-ON

ANALOG

INTERRUPT

13-BIT

ADC

EEPROM

256 BYTES

AT A0h

SDA

SCL

VCC

MON1

MON2

MON4

TXD

MON3P

MON3N

SEE

FIGURE 13

9-BIT

DELTA-SIGMA

9-BIT

DELTA-SIGMA

8-BIT

QTs

DAC1

DAC2

SDAOUT

SCLOUT

CSELOUT

TXF

REFIN

TXDOUT

RSELOUT

OUT1

LOSOUT

RSEL

IN1

LOS

GND

DS1874

VCC

LOS

TXF

TXD

TXDOUT

RSEL

FAULT

DISABLE

RSEL

RSELOUT

LOS

LOSOUT

TX_FAULT

SDA

SCL

MODE_DEF2 (SDA)

RATE SELECT

LOS

MODE_DEF1 (SCL)

TX_DISABLE

MODE

DAC

BIAS

DAC

LDD

EEPROM

QUICK

TRIP

LOS

ADC

I2C

DS1874

MAX3798/MAX3799

MON1

MON2

MON3

BMON

RMON

100Ω

+3.3V

RBD

PIN-ROSA

VCSEL-TOSA

DS1874

SFP+ Controller with Digital LDD Interface

12 ______________________________________________________________________________________

Detailed Description

The DS1874 integrates the control and monitoring func-

tionality required to implement a VCSEL-based SFP or

SFP+ system using Maxim’s MAX3798/MAX3799 com-

bined limiting amplifier and laser driver. Key compo-

nents of the DS1874 are shown in the

Block Diagram

and described in subsequent sections.

MAX3798/MAX3799 DAC Control

The DS1874 controls two 9-bit DACs inside the

MAX3798/MAX3799. One DAC is used for laser bias

control while the other is used for laser modulation con-

trol. The DS1874 communicates with the MAX3798/

MAX3799 over a 3-wire digital interface (see the

3-Wire

Master for Controlling the MAX3798/MAX3799

section).

The communication between the DS1874 and

MAX3798/MAX3799 is transparent to the end user.

BIAS Register/APC Control

The MAX3798/MAX3799 control their laser bias current

DAC using the APC loop within the DS1874. The APC

loop’s feedback to the DS1874 is the monitor diode

(MON2) current, which is converted to a voltage using

Typical Operating Circuit

an external resistor. The feedback is sampled by a com-

parator and compared to a digital set-point value. The

output of the comparator has three states: up, down, or

no-operation. The no-operation state prevents the output

from excessive toggling once steady state is reached.

As long as the comparator output is in either the up or

down states, the bias is adjusted by writing increment

and decrement values to the MAX3798/MAX3799

through the BIASINC register (3-wire address 13h).

The DS1874 has an LUT to allow the APC set point to

change as a function of temperature to compensate for

tracking error (TE). The TE LUT has 36 entries that

determine the APC setting in 4°C windows between

-40°C to +100°C.

MODULATION Control

The MAX3798/MAX3799 control the laser modulation

using the internal temperature-indexed LUT within the

DS1874. The modulation LUT is programmed in 2°C

increments over the -40°C to +102°C range to provide

temperature compensation for the laser’s modulation.

The modulation is updated after each temperature con-

version using the 3-wire interface that connects to the

MAX3798/MAX3799. The MAX3798/MAX3799 include a

9-bit DAC. The modulation LUT is 8 bits.

Figure 1 demonstrates how the 8-bit LUT controls the

9-bit DAC with the use of a temperature control bit

(MODTC, Table 02h, Register C6h) and a temperature

index register (MODTI, Table 02h, Register C2h).

DS1874

______________________________________________________________________________________ 13

Table 1. Acronyms

ACRONYM DEFINITION

ADC Analog-to-Digital Converter

AGC Automatic Gain Control

APC Automatic Power Control

APD Avalanche Photodiode

ATB Alarm Trap Bytes

BM Burst Mode

DAC Digital-to-Analog Converter

LOS Loss of Signal

LUT Lookup Table

NV Nonvolatile

QT Quick Trip

TE Tracking Error

TIA Transimpedance Amplifier

ROSA Receiver Optical Subassembly

SEE Shadowed EEPROM

SFF Small Form Factor

SFF-8472 Document Defining Register Map of SFPs

and SFFs

SFP Small Form Factor Pluggable

SFP+ Enhanced SFP

TOSA Transmit Optical Subassembly

TXP Transmit Power

SFP+ Controller with Digital LDD Interface

MOD LUT

LOADED TO [7:0]

MOD LUT

LOADED TO [7:0]

MODTI

MODTC = 0

TEMPERATURE (°C)

-40 +102 TEMPERATURE (°C)

-40 +102

MODTC = 1

MOD LUT

LOADED TO [8:1]

(DAC BIT 0 = 0)

MOD LUT

LOADED TO [8:1]

(DAC BIT 0 = 0)

MAX3798/MAX3799 DAC BIT

Figure 1. Modulation LUT Loading to MAX3798/MAX3799 MOD DAC

DS1874

SFP+ Controller with Digital LDD Interface

14 ______________________________________________________________________________________

BIAS and MODULATION Control

During Power-Up

The DS1874 has two internal registers, MODULATION

and BIAS, that represent the values written to the

MAX3798/MAX3799’s modulation DAC and bias DAC

through the 3-wire interface. On power-up, the DS1874

sets the MODULATION and BIAS registers to 0. When

VCC is above POA, the DS1874 initializes the MAX3798/

MAX3799. After a temperature conversion is completed

and if the VCC LO alarm is enabled, an additional VCC

conversion above the customer-defined VCC LO alarm

level is required before the MAX3798/MAX3799 MODU-

LATION register is updated with the value determined

by the temperature conversion and the modulation LUT.

When the MODULATION register is set, the BIAS regis-

ter is set to a value equal to ISTEP (see Figure 2). The

startup algorithm checks if this bias current causes a

feedback voltage above the APC set point, and if not, it

continues increasing the BIAS register by ISTEP until the

APC set point is exceeded. When the APC set point is

exceeded, the device begins a binary search to quickly

reach the bias current corresponding to the proper

power level. After the binary search is completed, the

APC integrator is enabled and single LSB steps are

used to tightly control the average power.

The TXP HI, TXP LO, HBAL, and BIAS MAX QT alarms

are masked until the binary search is completed.

However, the BIAS MAX alarm is monitored during this

time to prevent the BIAS register from exceeding

IBIASMAX. During the bias current initialization, the

BIAS register is not allowed to exceed IBIASMAX. If this

occurs during the ISTEP sequence, then the binary

search routine is enabled. If IBIASMAX is exceeded

during the binary search, the next smaller step is acti-

vated. ISTEP or binary increments that would cause the

BIAS register to exceed IBIASMAX are not taken.

Masking the alarms until the completion of the binary

search prevents false positive alarms during startup.

ISTEP is programmed by the customer using Table

02h, Register BBh. During the first steps, the MAX3798/

MAX3799’s bias DAC is directly written using

SET_IBIAS (3-wire address 09h). ISTEP should be pro-

grammed to the maximum safe increase that is allow-

able during startup. If this value is programmed too

low, the DS1874 still operates, but it could take signifi-

cantly longer for the algorithm to converge and hence

to control the average power.

If a fault is detected, and TXD is toggled to reenable

the outputs, the DS1874 powers up following a similar

sequence to an initial power-up. The only difference is

that the DS1874 already has determined the present

temperature, so the tINIT time is not required for the

DS1874 to recall the APC and MOD set points from

EEPROM.

12345678910111213

VPOA

MODULATION REGISTER

BIAS REGISTER

VCC

BIAS SAMPLE

tINIT

tSEARCH

BINARY SEARCH

APC INTEGRATOR ON

4x ISTEP

3x ISTEP

2x ISTEP

ISTEP

Figure 2. Power-Up Timing

BIAS and MODULATION Registers as a

Function of Transmit Disable (TXD)

If TXD is asserted (logic 1) during normal operation, the

outputs are disabled within tOFF. When TXD is deassert-

ed (logic 0), the DS1874 sets the MODULATION regis-

ter with the value associated with the present

temperature, and initializes the BIAS register using the

same search algorithm as done at startup. When

asserted, soft TXD (TXDC) (Lower Memory, Register

6Eh) would allow a software control identical to the TXD

pin (see Figure 3).

APC and Quick-Trip Timing

As shown in Figure 4, the DS1874’s input comparator is

shared between the APC control loop and the quick-

trip alarms (TXP HI, TXP LO, LOS, and BIAS HI). The

comparator polls the alarms in a multiplexed sequence.

Five of every eight comparator readings are used for

APC loop bias-current control. The other three updates

are used to check the HTXP/LTXP (monitor diode volt-

age), the HBATH (MON1), and LOS (MON3) signals

against the internal APC, BIAS, and MON3 reference,

respectively. If the last APC comparison was higher

than the APC set point, it makes an HTXP comparison,

and if it is lower, it makes an LTXP comparison.

Depending on the results of the comparison, the corre-

sponding alarms and warnings (TXP HI, TXP LO) are

asserted or deasserted.

The DS1874 has a programmable comparator sample

time based on an internally generated clock to facilitate

a wide variety of external filtering options and time

delays resulting from writing values to the MAX3798/

MAX3799’s bias DAC. The UPDATE RATE register

(Table 02h, Register 88h) determines the sampling

time. Samples occur at a regular interval, tREP. Table 2

shows the sample rate options available. Any quick-trip

alarm that is detected by default remains active until a

subsequent comparator sample shows the condition no

longer exists. A second bias current monitor (BIAS

MAX) compares the MAX3798/MAX3799’s BIAS DAC’s

code to a digital value stored in the IBIASMAX register.

This comparison is made at every bias current update

to ensure that a high-bias current is quickly detected.

An APC sample that requires an update of the BIAS

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 15

APC QUICK-TRIP SAMPLE TIMES HBIAS

SAMPLE

HBIAS

SAMPLE

LOS

SAMPLE

APC

SAMPLE

APC

SAMPLE

APC

SAMPLE

APC

SAMPLE

APC

SAMPLE

APC

SAMPLE

HTXP/LTXP

SAMPLE

tREP

Figure 4. APC Loop and Quick-Trip Sample Timing

Table 2. Update Rate Timing

APC_SR[2:0] SAMPLE PERIOD (tREP)

(ns)

000b 800

001b 1200

010b 1600

011b 2000

100b 2800

101b 3200

110b 4400

111b 6400

tOFF

tON

TXD

BIAS REGISTER

MODULATION REGISTER

Figure 3. TXD Timing

DS1874

SFP+ Controller with Digital LDD Interface

16 ______________________________________________________________________________________

ignored until the end of the 3-wire communication that

updates the MAX3798/MAX3799’s BIAS DAC, plus an

additional 16 sample periods (tREP).

Monitors and Fault Detection

Monitors

Monitoring functions on the DS1874 include five quick-trip

comparators and six ADC channels. This monitoring

combined with the alarm enables (Table 01h/05h) deter-

mines when/if the DS1874 turns off the MAX3798/

MAX3799 DACs and triggers the TXF and TXDOUT out-

puts. All the monitoring levels and interrupt masks are

user programmable.

Five Quick-Trip Monitors and Alarms

Five quick-trip monitors are provided to detect potential

laser safety issues and LOS status. These monitor the

following:

1) High Bias Current (HBATH)

2) Low Transmit Power (LTXP)

3) High Transmit Power (HTXP)

4) Max Output Current (IBIASMAX)

5) Loss-of-Signal (LOS LO)

The high-transmit and low-transmit power quick-trip reg-

isters (HTXP and LTXP) set the thresholds used to com-

pare against the MON2 voltage to determine if the

transmit power is within specification. The HBATH quick

trip compares the MON1 input (generally from the

MAX3798/MAX3799 bias monitor output) against its

threshold setting to determine if the present bias current

is above specification. The BIAS MAX quick trip deter-

mines if the BIAS register is above specification. The

BIAS register is not allowed to exceed the value set in

the IBIASMAX register. When the DS1874 detects that

the bias is at the limit it sets the BIAS MAX status bit

and holds the BIAS register setting at the IBIASMAX

level. The bias and power quick trips are routed to the

TXF through interrupt masks to allow combinations of

these alarms to be used to trigger these outputs. The

user can program up to eight different temperature-

indexed threshold levels for MON1 (Table 02h,

Registers D0h–D7h). The LOS LO quick trip compares

the MON3 input against its threshold setting to deter-

mine if the present received power is below the specifi-

cation. The LOS LO quick trip can be used to set the

LOSOUT pin. These alarms can be latched using Table

02h, Register 8Ah.

Six ADC Monitors and Alarms

The ADC monitors six channels that measure tempera-

ture (internal temp sensor), VCC, and MON1–MON4

using an analog multiplexer to measure them round

robin with a single ADC (see the

ADC Timing

section).

The five voltage channels have a customer-programma-

ble full-scale range and all channels have a customer-

programmable offset value that is factory programmed to

default value (see Table 3). Additionally, MON1–MON4

can right-shift results by up to 7 bits before the results

are compared to alarm thresholds or read over the I2C

bus. This allows customers with specified ADC ranges to

calibrate the ADC full scale to a factor of 1/2nof their

specified range to measure small signals. The DS1874

can then right-shift the results by n bits to maintain the bit

weight of their specification (see the

Right-Shifting ADC

Result

and

Enhanced RSSI Monitoring (Dual-Range

Functionality)

sections).

The ADC results (after right-shifting, if used) are com-

pared to the alarm and warning thresholds after each

conversion, and the corresponding alarms are set,

which can be used to trigger the TXF output. These

ADC thresholds are user programmable, as are the

masking registers that can be used to prevent the

alarms from triggering the TXF output.

ADC Timing

There are six analog channels that are digitized in a

round-robin fashion in the order shown in Figure 5. The

total time required to convert all six channels is tRR (see

the

Analog Voltage Monitoring Characteristics

for details).

Right-Shifting ADC Result

If the weighting of the ADC digital reading must con-

form to a predetermined full-scale (PFS) value defined

by a standard’s specification (e.g., SFF-8472), then

right-shifting can be used to adjust the PFS analog

measurement range while maintaining the weighting of

the ADC results. The DS1874’s range is wide enough to

cover all requirements; when the maximum input value

is ≤1/2 of the FS value, right-shifting can be used to

obtain greater accuracy. For instance, the maximum

voltage might be 1/8 the specified PFS value, so only

1/8 the converter’s range is effective over this range.

An alternative is to calibrate the ADC’s full-scale range

to 1/8 the readable PFS value and use a right-shift

value of 3. With this implementation, the resolution of

Table 3. ADC Default Monitor Full-Scale

Ranges

SIGNAL +FS

SIGNAL

+FS

hex

-FS

SIGNAL

-FS

hex

Temperature (°C) 127.996 7FFF -128 8000

VCC (V) 6.5528 FFF8 0 0000

MON1–MON4 (V) 2.4997 FFF8 0 0000

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 17

TEMP VCC MON1 MON2 MON3 MON4 TEMP

ONE ROUND-ROBIN ADC CYCLE

tRR

NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC

IS ABOVE THE VCC ALARM LOW THRESHOLD.

the measurement is increased by a factor of 8, and

because the result is digitally divided by 8 by right-

shifting, the bit weight of the measurement still meets

the standard’s specification (i.e., SFF-8472).

The right-shift operation on the ADC result is carried out

based on the contents of right-shift control registers (Table

02h, Registers 8Eh–8Fh) in EEPROM. Four analog chan-

nels, MON1–MON4, each have 3 bits allocated to set the

number of right-shifts. Up to seven right-shift operations

are allowed and are executed as a part of every conver-

sion before the results are compared to the high-alarm

and low-alarm levels, or loaded into their corresponding

measurement registers (Lower Memory, Registers

64h–6Bh). This is true during the setup of internal calibra-

tion as well as during subsequent data conversions.

Enhanced RSSI Monitoring (Dual-Range

Functionality)

The DS1874 offers a feature to improve the accuracy

and range of MON3, which is most commonly used for

monitoring RSSI. The accuracy of the RSSI measure-

ments is increased at the small cost of reduced range

(of input signal swing). The DS1874 eliminates this

trade-off by offering “dual range” calibration on the

MON3 channel (see Figure 6). This feature enables

right-shifting (along with its gain and offset settings)

when the input signal is below a set threshold (within the

range that benefits using right-shifting) and then automat-

ically disables right-shifting (recalling different gain and

offset settings) when the input signal exceeds the thresh-

old. Also, to prevent “chattering,” hysteresis prevents

excessive switching between modes in addition to ensur-

ing that continuity is maintained. Dual-range operation is

enabled by default (factory programmed in EEPROM).

However, it can easily be disabled through the RSSI_FC

and RSSI_FF bits, which are described in the

Descriptions

section. When dual-range operation is dis-

abled, MON3 operates identically to the other MON

channels, although featuring a differential input.

Dual-range functionality consists of two modes of opera-

tion: fine mode and coarse mode. Each mode is calibrat-

ed for a unique transfer function, hence the term, dual

range. Table 5 highlights the registers related to MON3.

Fine mode is equivalent to the other MON channels. Fine

mode is calibrated using the gain, offset, and right-shift-

ing registers at locations shown in Table 5 and is ideal

for relatively small analog input voltages. Coarse mode is

automatically switched to when the input exceeds a

threshold (to be discussed in a subsequent paragraph).

Coarse mode is calibrated using different gain and offset

registers, but lacks right-shifting (since coarse mode is

only used on large input signals). The gain and offset

registers for coarse mode are also shown in Table 5.

Additional information for each of the registers can be

found in the

section.

Dual-range operation is transparent to the end user.

The results of MON3 analog-to-digital conversions are

still stored/reported in the same memory locations

(68h–69h, Lower Memory) regardless of whether the

conversion was performed in fine mode or coarse

mode. The only way to tell which mode generated the

digital result is by reading the RSSIR bit.

When the DS1874 is powered up, analog-to-digital con-

versions begin in a round-robin fashion. Every MON3

timeslice begins with a fine mode analog-to-digital con-

version (using fine mode’s gain, offset, and right-shifting

settings). See the flowchart in Figure 7 for more details.

DS1874

MON3P

MON3N ADC

100Ω

ROSA

VCC

Figure 6. MON3 Differential Input for High-Side RSSI

Figure 5. ADC Round-Robin Timing

DS1874

SFP+ Controller with Digital LDD Interface

18 ______________________________________________________________________________________

Then, depending on whether the last MON3 timeslice

resulted in a coarse-mode conversion and also depend-

ing on the value of the current fine conversion, decisions

are made whether to use the current fine-mode conver-

sion result or to make an additional conversion (within

the same MON3 timeslice), using coarse mode (using

coarse mode’s gain and offset settings and no right-

shifting) and reporting the coarse-mode result. The flow-

chart in Figure 7 also illustrates how hysteresis is

implemented. The fine-mode conversion is compared to

one of two thresholds. The actual threshold values are a

function of the number of right-shifts being used. With

the use of right-shifting, the fine mode full-scale is pro-

grammed to (1/2nth) of the coarse mode full-scale. The

DS1874 now auto ranges to choose the range that gives

the best resolution for the measurement. Hysteresis is

applied to eliminate chatter when the input resides at

the boundary of the two ranges. See Figure 7 for details.

Table 4 shows the threshold values for each possible

number of right-shifts.

The RSSI_FF and RSSI_FC bits are used to force fine-

mode or coarse-mode conversions, or to disable the

dual-range functionality. Dual-range functionality is

enabled by default (both RSSI_FC and RSSI_FF are

factory programmed to 0 in EEPROM). It can be dis-

abled by setting RSSI_FC to 0 and RSSI_FF to 1. These

bits are also useful when calibrating MON3. For addi-

tional information, see Figure 19.

Table 5. MON3 Configuration Registers

GAIN 98h–99h, Table 02h 9Ch–9Dh, Table 02h

OFFSET A8h–A9h, Table 02h ACh–ADh, Table 02h

RIGHT-SHIFT08Fh, Table 02h —

CNFGC 8Bh, Table 02h

UPDATE

(RSSIR BIT) 6Fh, Lower Memory

MON3 VALUE 68h–69h, Lower Memory

NUMBER OF

RIGHT-SHIFTS

FINE MODE

MAX (hex)

COARSE MODE

MIN* (hex)

0 FFF8 F000

1 7FFC 7800

2 3FFE 3C00

3 1FFF 1E00

4 0FFF 0F00

5 07FF 0780

6 03FF 03C0

7 01FF 01E0

MON3

TIMESLICE

END OF MON3

TIMESLICE

PERFORM FINE-

MODE CONVERSION

REPORT FINE

CONVERSION RESULT

REPORT COARSE

CONVERSION RESULT

DID PRIOR MON3

TIMESLICE RESULT IN A

COARSE CONVERSION?

(LAST RSSIR = 1?)

LAST RSSI = 0 LAST RSSIR = 1

WAS CURRENT FINE-

MODE CONVERSION

≥ 93.75% OF FS?

PERFORM COARSE-

MODE CONVERSION

DID CURRENT FINE-

MODE CONVERSION

REACH MAX?

Figure 7. RSSI Flowchart

Table 4. MON3 Hysteresis Threshold

Values

This is the minimum reported coarse-mode conversion.

DS1874

Low-Voltage Operation

The DS1874 contains two power-on reset (POR) levels.

The lower level is a digital POR (POD) and the higher

level is an analog POR (POA). At startup, before the

supply voltage rises above POA, the outputs are dis-

abled, all SRAM locations are set to their defaults,

shadowed EEPROM (SEE) locations are zero, and all

analog circuitry is disabled. When VCC reaches POA,

the SEE is recalled, and the analog circuitry is enabled.

While VCC remains above POA, the device is in its nor-

mal operating state, and it responds based on its non-

volatile configuration. If during operation VCC falls

below POA, but is still above POD, then the SRAM

retains the SEE settings from the first SEE recall, but the

device analog is shut down and the outputs disabled. If

the supply voltage recovers back above POA, then the

device immediately resumes normal operation. If the

supply voltage falls below POD, then the device SRAM

is placed in its default state and another SEE recall is

required to reload the nonvolatile settings. The EEPROM

recall occurs the next time VCC exceeds POA. Figure 8

shows the sequence of events as the voltage varies.

Any time VCC is above POD, the I2C interface can be

used to determine if VCC is below the POA level. This is

accomplished by checking the RDYB bit in the STATUS

(Lower Memory, Register 6Eh) byte. RDYB is set when

VCC is below POA; when VCC rises above POA, RDYB

is timed (within 500µs) to go to 0, at which point the

part is fully functional.

For all device addresses sourced from EEPROM (Table

02h, Register 8Ch), the default device address is A2h

until VCC exceeds POA, allowing the device address to

be recalled from the EEPROM.

Power-On Analog (POA)

POA holds the DS1874 in reset until VCC is at a suitable

level (VCC > POA) for the device to accurately measure

with its ADC and compare analog signals with its quick-

trip monitors. Because VCC cannot be measured by the

ADC when VCC is less than POA, POA also asserts the

VCC LO alarm, which is cleared by a VCC ADC conver-

sion greater than the customer-programmable VCC

alarm low ADC limit. This allows a programmable limit

to ensure that the headroom requirements of the trans-

ceiver are satisfied during a slow power-up. The TXF

output does not latch until there is a conversion above

VCC low limit. The POA alarm is nonmaskable. The TXF

output is asserted when VCC is below POA. See the

Low-Voltage Operation

section for more information.

Delta-Sigma Outputs (DAC1 and DAC2)

Two delta-sigma outputs are provided, DAC1 and

DAC2. With the addition of an external RC filter, these

outputs provide two 9-bit resolution analog outputs with

the full-scale range set by the input REFIN. Each output

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 19

VPOA

VPOD

VCC

SEE RECALLED VALUE RECALLED VALUE

PRECHARGED

TO 0

PRECHARGED

TO 0

PRECHARGED TO 0

SEE RECALL SEE RECALL

Figure 8. Low-Voltage Hysteresis Example

DS1874

is either manually controlled or controlled using a tem-

perature-indexed LUT. A delta-sigma is a digital output

using pulse-density modulation. It provides much lower

output ripple than a standard digital PWM output given

the same clock rate and filter components. Before tINIT,

the DAC1 and DAC2 outputs are high impedance.

The external RC filter components are chosen based

on ripple requirements, output load, delta-sigma fre-

quency, and desired response time. A recommended

filter is shown in Figure 9.

The DS1874’s delta-sigma outputs are 9 bits. For illus-

trative purposes, a 3-bit example is provided. Each

possible output of this 3-bit delta-sigma DAC is given in

Figure 10.

In LUT mode, DAC1 and DAC2 are each controlled by a

separate 8-bit, 4°C-resolution, temperature-addressed

LUT. The delta-sigma outputs use a 9-bit structure. The

8-bit LUTs are either loaded directly into the MSBs (8:1)

or the LSBs (7:0). This is determined by DAC1TI (Table

02h, Register C3h), DAC2TI (Table 02h, Register C4h),

DAC1TC (Table 02h, Register C6h, bit 6), and DAC2TC

(Table 02h, Register C6h, bit 5). See Figure 11 for more

details. The DAC1 LUT (Table 07h) and DAC2 LUT

(Table 08h) are nonvolatile and password-2 protected.

The reference input, REFIN, is the supply voltage for

the output buffer of DAC1 and DAC2. The voltage con-

nected to REFIN must be able to support the edge rate

requirements of the delta-sigma outputs. In a typical

application, a 0.1µF capacitor should be connected

between REFIN and ground.

20 ______________________________________________________________________________________

LUT LOADED TO [7:0] LUT LOADED TO [7:0]

DAC[1/2]TI

DAC[1/2]TC = 0

TEMPERATURE (°C)

-40 +102 TEMPERATURE (°C)

-40 +102

DAC[1/2]TC = 1

LUT LOADED TO [8:1]

(DAC BIT 0 = 0)

LUT LOADED TO [8:1]

(DAC BIT 0 = 0)

DELTA-SIGMA DACA OR DACB

Figure 11. DAC1/DAC2 LUT Assignments

DS1874

DAC1/DAC2

3.24kΩ3.24kΩ

0.01μF 0.01μF

OUTPUT

SFP+ Controller with Digital LDD Interface

Figure 10. Delta-Sigma Outputs

Figure 9. Recommended RC Filter for DAC1/DAC2

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 21

Digital I/O Pins

Five digital input and five digital output pins are provid-

ed for monitoring and control.

LOS, LOSOUT

By default (LOSC = 1, Table 02h, Register 89h), the

LOS pin is used to convert a standard comparator out-

put for loss of signal (LOS) to an open-collector output.

This means the mux shown in the

Block Diagram

default selects the LOS pin as the source for the

LOSOUT output transistor. The output of the mux can

be read in the STATUS byte (Lower Memory,

inverted (INV LOS = 1) before driving the open-drain

output transistor using the XOR gate provided. Setting

LOSC = 0 configures the mux to be controlled by LOS

LO, which is driven by the output of the LOS quick trip

(Table 02h, Registers BEh and BFh). The mux setting

(stored in EEPROM) does not take effect until VCC >

POA, allowing the EEPROM to recall.

IN1, RSEL, OUT1, RSELOUT

The digital input IN1 and RSEL pins primarily serve to

meet the rate-select requirements of SFP and SFP+.

They also serve as general-purpose inputs. OUT1 and

RSELOUT are driven by a combination of the IN1,

RSEL, and logic dictated by control registers in the

EEPROM (Figure 13). The levels of IN1 and RSEL can

be read using the STATUS register (Lower Memory,

controlled and/or inverted using the CNFGB register

(Table 02h, Register 8Ah). The open-drain RSELOUT

output is software-controlled and/or inverted through

the Status register and CNFGA register (Table 02h,

ed on OUT1 and RSELOUT to realize high logic levels.

TXF, TXD, TXDOUT

TXDOUT is generated from a combination of TXF, TXD,

and the internal signal FETG. A software control identi-

cal to TXD is available (TXDC, Lower Memory, Register

6Eh). A TXD pulse is internally extended (TXDEXT) by

time tINITR1 to inhibit the latching of low alarms and

warnings related to the APC loop to allow for the loop to

stabilize. The nonlatching alarms and warnings are TXP

LO, LOS LO, and MON1–MON4 LO alarms and warn-

ings. In addition, TXP LO is disabled from creating

FETG. TXF is both an input and an output (Figure 12).

See the

Transmit Fault (TXF) Output

section for a

detailed explanation of TXF. Figure 12 shows that the

OUT IN

TXDS

RPU

TXF

SET BIAS REGISTER TO 0 AND

MAX3798/MAX3799

SET_IMOD TO 0

TXD

MINT

HBAL FLAG

TXP HI FLAG

TXP LO FLAG

BIAS MAX FLAG

TXP HI FLAG

TXP HI ENABLE

BIAS MAX

BIAS MAX ENABLE

HBAL FLAG

HBAL ENABLE

TXP LO FLAG

TXP LO ENABLE

TXDEXT

TXDC

VCC

TXD

TXF

TXDOUT

TXDIO

TXDFG

FETG

TXDFLT

FAULT RESET TIMER

(130ms)

OUT

POWER-ON

RESET

Figure 12. Logic Diagram 1

DS1874

same signals and faults can also be used to generate

the internal signal FETG (Table 01h/05h, Registers FAh

and FBh). FETG is used to send a fast “turn-off” com-

mand to the laser driver. The intended use is a direct

connection to the MAX3798/MAX3799’s TXD input if

this is desired. When VCC < POA, TXDOUT is high

impedance.

Transmit Fault (TXF) Output

TXF can be triggered by all alarms, warnings, and

quick trips (Figure 12). The six ADC alarms, warnings,

and the LOS quick trips require enabling (Table

01h/05h, Registers F8h and FDh). See Figures 14a and

14b for nonlatched and latched operation. Latching of

the alarms is controlled by the CNFGB and CNFGC

registers (Table 02h, Registers 8Ah–8Bh).

Die Identification

The DS1874 has an ID hardcoded in its die. Two regis-

ters (Table 02h, Registers CEh–CFh) are assigned for

this feature. The CEh register reads 74h to identify the

part as the DS1874, while the CFh register reads the

current device version.

3-Wire Master for Controlling

the MAX3798/MAX3799

The DS1874 controls the MAX3798/MAX3799 over a

proprietary 3-wire interface. The DS1874 acts as the

master, initiating communication with and generating

the clock for the MAX3798/MAX3799. It is a 3-pin inter-

face consisting of SDAOUT (a bidirectional data line),

an SCLOUT clock signal, and a CSELOUT chip-select

output (active high).

Protocol

The DS1874 initiates a data transfer by asserting the

CSELOUT pin. It then starts to generate a clock signal

22 ______________________________________________________________________________________

DETECTION OF TXF FAULT

TXD

TXF

Figure 14b. TXF Latched Operation

INVOUT1

IN1C

IN1

IN1S OUT1

INV LOSLOSC

MUX

LOSOUT

RSELOUT

RSELC

RSEL

LOS

LOS LO

RSELS

RXL

SFP+ Controller with Digital LDD Interface

DETECTION OF TXF FAULT

TXF

Figure 14a. TXF Nonlatched Operation

Figure 13. Logic Diagram 2

after the CSELOUT has been set to 1. Each operation

consists of 16-bit transfers (15-bit address/data, 1-bit

RWN). All data transfers are MSB first.

Write Mode (RWN = 0): The master generates 16 clock

cycles at SCLOUT in total. It outputs 16 bits (MSB first)

to the SDAOUT line at the falling edge of the clock. The

master closes the transmission by setting the

CSELOUT to 0.

Read Mode (RWN = 1): The master generates 16 clock

cycles at SCLOUT in total. It outputs 8 bits (MSB first)

to the SDAOUT line at the falling edge of the clock. The

SDAOUT line is released after the RWN bit has been

transmitted. The slave outputs 8 bits of data (MSB first)

at the rising edge of the clock. The master samples

SDAOUT at the falling edge of SCLOUT. The master

closes the transmission by setting the CSELOUT to 0.

3-Wire Interface Timing

Figure 15 shows the 3-wire interface timing. Figure 16

shows the 3-wire state machine. See the

3-Wire Digital

Interface Specification

table for more information.

DS1874 and MAX3798/MAX3799

Communication

Normal Operation

The majority of the communication between the two

devices consists of bias adjustments for the APC loop.

After each temperature conversion, the laser modula-

tion setting must be updated. Status registers TXSTAT1

and TXSTAT2 are read between temperature updates

at a regular interval: tRR (see the

Analog Voltage

Monitoring Characteristics

table). The results are stored

in TXSTAT1 and TXSTAT2 (Table 02h, FCh–FDh).

Manual Operation

The MAX3798/MAX3799 are manually controllable

using four registers in the DS1874: 3WCTRL,

ADDRESS, WRITE, and READ. Commands can be

manually issued while the DS1874 is in normal opera-

tion mode. It is also possible to suspend normal 3-wire

commands so that only manual operation commands

are sent (3WCTRL, Table 02h, Register F8h).

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 23

BIT NAME DESCRIPTION

15:9 Address 7-bit internal register address

8 RWN 0: write; 1: read

7:0 Data 8-bit read or write data

CSELOUT

SCLOUT

SDAOUT

CSELOUT

SCLOUT

SDAOUT

12345678

9 1011121314150

1234567891011121314150

A5 A4 A3 A2 A1 RWN D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0RWN

WRITE MODE

READ MODE

A6 A5 A4 A3 A2 A1 A0

tDS

tDH

tDS

tDH

Figure 15. 3-Wire Timing

DS1874

24 ______________________________________________________________________________________

POR

TXD_LATCHED = 1

SET TXD FLAG HERE

SET RTXPOR2_FLAG HERE

READ TXPOR1 UPDATE

MODULATION

START APC

LOOP

UPDATE BIAS

INCREMENT

MODULATION

UPDATE

TXSTAT, BIAS, MOD

STANDBY

READ TXPOR3

RESET FLAGS HERE

READ TXPOR4

READ TXPOR2

WRITE MOD, BIAS = 00

UPDATE CTRL

TXD HIGH_STDBY

1011

TX_POR = 1?

MAN_MODE_RDWR = 1?

TX_POR = = 1?

APC_BINARY = = 1?

TXD = = 0?

TX_POR = = 1?

MODINC = 1?

TEMP_CONV_START = = 1?

AND TXDIS = 0

YES

BIASINC = = 1?

MODINC = = 1?

TXD_FLAG = = 1

OR TXDIS = 1 OR

RTXPOR2 FLAG

BIASINC = = 1?

APC_BINARY = = 1?

TXD_FLAG = = 1? OR

RTXPOR2 FLAG = 1

YES

YES YES

NO NO

YES

READ/WRITE

MANMODE

MAN_MODE_RDWR = 1?

TX_POR = = 1?

TXDIS = 1?

STROBE

Figure 16. 3-Wire State Machine

SFP+ Controller with Digital LDD Interface

Initialization

During initialization, the DS1874 transfers all its 3-wire

EEPROM control registers to the MAX3798/MAX3799.

The 3-wire control registers include the following:

• RXCTRL1

• RXCTRL2

• SET_CML

• SET_LOS

• TXCTRL

• IMODMAX

• IBIASMAX

• SET_PWCTRL

• SET_TXDE

The control registers are first written when VCC exceeds

POA. They are also written if the MAX3798/MAX3799

TX_POR bit is set high (visible in 3W TXSTAT1, bit 7). In

the MAX3798/MAX3799, this bit is “sticky” (latches high

and is cleared on a read). They are also updated on a

rising edge of TXD. Any time one of these events

occurs, the DS1874 reads and updates TXSTAT1 and

TXSTAT2 and sets SET_IBIAS and SET_IMOD in the

MAX3798/MAX3799 to 0.

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 25

MAX3798/MAX3799 Register Map and DS1874 Corresponding Location

MAX3798/MAX3799 REGISTER FUNCTION REGISTER NAME DS1874 LOCATION

Receiver Control 1 RXCTRL1 Table 02h, E8h

Receiver Control 2 RXCTRL2 Table 02h, E9h

Receiver Status RXSTAT Lower Memory, 6Eh, Bit1

Output CML Level Setting SET_CML Table 02h, EAh

LOS Threshold Level Setting SET_LOS Table 02h, EBh

Transmitter Control TXCTRL Table 02h, ECh

Transmitter Status 1 TXSTAT1 Table 02h, FCh

Transmitter Status 2 TXSTAT2 Table 02h, FDh

Bias Current Setting SET_IBIAS/BIAS Table 02h, CBh–CCh

Modulation Current Setting SET_IMOD/MODULATION Table 02h, 82h–83h

Maximum Modulation Current Setting IMODMAX Table 02h, EDh

Maximum Bias Current Setting IBIASMAX Table 02h, EEh

Modulation Current Increment Setting MODINC (see Note)

Bias Current Increment Setting BIASINC

Automatically performed by APC loop. Disable

APC before using 3-wire manual mode. Manual

Mode: Table 02h, F8h–FBh

Mode Control MODECTRL (see Note)

Transmitter Pulse-Width Control SET_PWCTRL Table 02h, EFh

Transmitter Deemphasis Control SET_TXDE Table 02h, F0h

Note: This register is not present in the DS1874. To access this register, use manual operation (see the

Manual Operation

section).

DS1874

SFP+ Controller with Digital LDD Interface

26 ______________________________________________________________________________________

SCL

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

SDA

STOP START REPEATED

START

tBUF

tHD:STA

tHD:DAT tSU:DAT

tSU:STO

tHD:STA

tSP

tSU:STA

tHIGH

tLOW

Figure 17. I2C Timing

I2C Communication

I2C Definitions

The following terminology is commonly used to

describe I2C data transfers.

Master device: The master device controls the

slave devices on the bus. The master device gen-

erates SCL clock pulses and START and STOP

conditions.

Slave devices: Slave devices send and receive

data at the master’s request.

Bus idle or not busy: Time between STOP and

START conditions when both SDA and SCL are inac-

tive and in their logic-high states.

START condition: A START condition is generated

by the master to initiate a new data transfer with a

slave. Transitioning SDA from high to low while SCL

remains high generates a START condition. See

Figure 17 for applicable timing.

STOP condition: A STOP condition is generated by

the master to end a data transfer with a slave.

Transitioning SDA from low to high while SCL

remains high generates a STOP condition. See

Figure 17 for applicable timing.

Repeated START condition: The master can use a

repeated START condition at the end of one data

transfer to indicate that it will immediately initiate a

new data transfer following the current one.

Repeated STARTs are commonly used during read

operations to identify a specific memory address to

begin a data transfer. A repeated START condition

is issued identically to a normal START condition.

See Figure 17 for applicable timing.

Bit write: Transitions of SDA must occur during the

low state of SCL. The data on SDA must remain valid

and unchanged during the entire high pulse of SCL

plus the setup and hold time requirements (Figure

17). Data is shifted into the device during the rising

edge of the SCL.

Bit read: At the end a write operation, the master

must release the SDA bus line for the proper amount

of setup time (Figure 17) before the next rising edge

of SCL during a bit read. The device shifts out each

bit of data on SDA at the falling edge of the previous

SCL pulse and the data bit is valid at the rising edge

of the current SCL pulse. Remember that the master

generates all SCL clock pulses, including when it is

reading bits from the slave.

Acknowledgement (ACK and NACK): An acknowl-

edgement (ACK) or not acknowledge (NACK) is

always the ninth bit transmitted during a byte trans-

fer. The device receiving data (the master during a

read or the slave during a write operation) performs

an ACK by transmitting a zero during the ninth bit. A

device performs a NACK by transmitting a one dur-

ing the 9th bit. Timing (Figure 17) for the ACK and

NACK is identical to all other bit writes. An ACK is

the acknowledgment that the device is properly

receiving data. A NACK is used to terminate a read

sequence or as an indication that the device is not

receiving data.

Byte write: A byte write consists of 8 bits of informa-

tion transferred from the master to the slave (most

significant bit first) plus a 1-bit acknowledgement

from the slave to the master. The 8 bits transmitted

by the master are done according to the bit-write

definition and the acknowledgement is read using

the bit-read definition.

Byte read: A byte read is an 8-bit information trans-

fer from the slave to the master plus a 1-bit ACK or

NACK from the master to the slave. The 8 bits of

information that are transferred (most significant bit

first) from the slave to the master are read by the

master using the bit-read definition, and the master

transmits an ACK using the bit-write definition to

receive additional data bytes. The master must

NACK the last byte read to terminate communication

so the slave returns control of SDA to the master.

Slave address byte: Each slave on the I2C bus

responds to a slave address byte sent immediately

following a START condition. The slave address byte

contains the slave address in the most significant 7

bits and the R/Wbit in the least significant bit.

The DS1874 responds to two slave addresses. The

auxiliary memory always responds to a fixed I2C

slave address, A0h. The Lower Memory and Tables

00h–08h respond to I2C slave addresses that can

be configured to any value between 00h–FEh using

the DEVICE ADDRESS byte (Table 02h, Register

8Ch). The user also must set the ASEL bit (Table

02h, Register 89h) for this address to be active. By

writing the correct slave address with R/W= 0, the

master indicates it will write data to the slave. If R/W

= 1, the master reads data from the slave. If an

incorrect slave address is written, the DS1874

assumes the master is communicating with another

I2C device and ignores the communications until the

next START condition is sent. If the main device’s

slave address is programmed to be A0h, access to

the auxiliary memory is disabled.

Memory address: During an I2C write operation to

the DS1874, the master must transmit a memory

address to identify the memory location where the

slave is to store the data. The memory address is

always the second byte transmitted during a write

operation following the slave address byte.

I2C Protocol

Writing a single byte to a slave: The master must

generate a START condition, write the slave address

byte (R/W= 0), write the memory address, write the

byte of data, and generate a STOP condition.

Remember the master must read the slave’s

acknowledgement during all byte-write operations.

Writing multiple bytes to a slave: To write multiple

bytes to a slave, the master generates a START con-

dition, writes the slave address byte (R/W= 0),

writes the memory address, writes up to 8 data

bytes, and generates a STOP condition. The

DS1874 writes 1 to 8 bytes (one page or row) with a

single write transaction. This is internally controlled

by an address counter that allows data to be written

to consecutive addresses without transmitting a

memory address before each data byte is sent. The

address counter limits the write to one 8-byte page

(one row of the memory map). Attempts to write to

additional pages of memory without sending a STOP

condition between pages results in the address

counter wrapping around to the beginning of the

present row.

For example, a 3-byte write starts at address 06h

and writes 3 data bytes (11h, 22h, and 33h) to three

“consecutive” addresses. The result is that address-

es 06h and 07h would contain 11h and 22h, respec-

tively, and the third data byte, 33h, would be written

to address 00h.

To prevent address wrapping from occurring, the

master must send a STOP condition at the end of

the page, then wait for the bus-free or EEPROM

write time to elapse. Then the master can generate a

new START condition and write the slave address

byte (R/W= 0) and the first memory address of the

next memory row before continuing to write data.

Acknowledge polling: Any time a EEPROM page is

written, the DS1874 requires the EEPROM write time

(tW) after the STOP condition to write the contents of

the page to EEPROM. During the EEPROM write

time, the DS1874 will not acknowledge its slave

address because it is busy. It is possible to take

advantage of that phenomenon by repeatedly

addressing the DS1874, which allows the next page

to be written as soon as the DS1874 is ready to

receive the data. The alternative to acknowledge

polling is to wait for maximum period of tWto elapse

before attempting to write again to the DS1874.

EEPROM write cycles: When EEPROM writes occur,

the DS1874 writes the whole EEPROM memory page,

even if only a single byte on the page was modified.

Writes that do not modify all 8 bytes on the page are

allowed and do not corrupt the remaining bytes of

memory on the same page. Because the whole page

is written, bytes on the page that were not modified

during the transaction are still subject to a write

DS1874

______________________________________________________________________________________ 27

SFP+ Controller with Digital LDD Interface

DS1874

SFP+ Controller with Digital LDD Interface

28 ______________________________________________________________________________________

START

START STOP

SLAVE

ACK

SLAVE

ACK

STOP

SINGLE-BYTE WRITE

-WRITE 00h TO REGISTER BAh

TWO-BYTE WRITE

-WRITE 01h AND 75h

TO C8h AND C9h

SINGLE-BYTE READ

-READ REGISTER BAh

TWO-BYTE READ

-READ C8h AND C9h

REPEATED

START

MASTER

NACK

10100010

A2h

10111010

BAh

SLAVE

ACK

START SLAVE

ACK

10100010

A2h

10100011

A3h

10111010

BAh

SLAVE

ACK

SLAVE

ACK

STOP

00000000

00h

STOP

SLAVE

ACK

STOP

01110101

75h

START SLAVE

ACK

10100010

A2h

11001000

C8h

SLAVE

ACK

SLAVE

ACK

00000001

01h

SLAVE

ACK DATA IN BAh

DATA

REPEATED

START

MASTER

ACK

START SLAVE

ACK

10100010

A2h

10100011

A3h

11001000

C8h

SLAVE

ACK

SLAVE

ACK DATA IN C8h

DATA

MASTER

NACK

DATA IN C9h

DATA

EXAMPLE I2C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS

*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h FOR THE MAIN MEMORY.

IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Ch FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED

ADDRESS FOR THE MAIN MEMORY IS A0h.

TYPICAL I2C WRITE TRANSACTION

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

MSB LSB

b7 b6 b5 b4 b3 b2 b1 b0

DATA

SLAVE

ACK

SLAVE

ACK

SLAVE

ADDRESS*

1 0 1 0 0 0 1 R/W

MSB LSB

READ/

WRITE

Figure 18. Example I2C Timing

cycle. This can result in a whole page being worn out

over time by writing a single byte repeatedly. Writing

a page one byte at a time wears the EEPROM out

eight times faster than writing the entire page at

once. The DS1874’s EEPROM write cycles are speci-

fied in the

Nonvolatile Memory Characteristics

table.

The specification shown is at the worst-case temper-

ature. It can handle approximately ten times that

many writes at room temperature. Writing to SRAM-

shadowed EEPROM memory with SEEB = 1 does not

count as an EEPROM write cycle when evaluating

the EEPROM’s estimated lifetime.

Reading a single byte from a slave: Unlike the

write operation that uses the memory address byte

to define where the data is to be written, the read

operation occurs at the present value of the memory

address counter. To read a single byte from the

slave, the master generates a START condition,

writes the slave address byte with R/W= 1, reads

the data byte with a NACK to indicate the end of the

transfer, and generates a STOP condition.

Manipulating the address counter for reads: A

dummy write cycle can be used to force the address

pointer to a particular value. To do this, the master

generates a START condition, writes the slave

address byte (R/W= 0), writes the memory address

where it desires to read, generates a repeated

START condition, writes the slave address byte (R/W

= 1), reads data with ACK or NACK as applicable,

and generates a STOP condition.

Memory Organization

The DS1874 features nine separate memory tables that

are internally organized into 8-byte rows.

The Lower Memory is addressed from 00h to 7Fh and

contains alarm and warning thresholds, flags, masks,

several control registers, password entry area (PWE),

and the table-select byte.

Table 01h primarily contains user EEPROM (with PW1

level access) as well as alarm and warning-enable

bytes.

Table 02h is a multifunction space that contains config-

uration registers, scaling and offset values, passwords,

interrupt registers as well as other miscellaneous con-

trol bytes.

Table 04h contains a temperature-indexed LUT for

control of the modulation voltage. The modulation LUT

can be programmed in 2°C increments over the -40°C

to +102°C range.

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 29

Table 05h is empty by default. It can be configured to

contain the alarm- and warning-enable bytes from Table

01h, Registers F8h–FFh with the MASK bit enabled

(Table 02h, Register 89h). In this case Table 01h is

empty.

Table 06h contains a temperature-indexed LUT that

allows the APC set point to change as a function of

temperature to compensate for tracking error (TE). The

APC LUT has 36 entries that determine the APC setting

in 4°C windows between -40°C and +100°C.

Table 07h contains a temperature-indexed LUT for con-

trol of DAC1. The LUT has 36 entries that determine the

DAC setting in 4°C windows between -40°C and +100°C.

Table 08h contains a temperature-indexed LUT for con-

trol of DAC2. The LUT has 36 entries that determine the

DAC setting in 4°C windows between -40°C and +100°C.

Auxiliary Memory (device A0h) contains 256 bytes of

EE memory accessible from address 00h–FFh. It is

selected with the device address of A0h.

See the

section for more com-

plete details of each byte’s function, as well as for

read/write permissions for each byte.

Shadowed EEPROM

Many NV memory locations (listed within the

Descriptions

section) are actually shadowed EEPROM

that are controlled by the SEEB bit in Table 02h,

The DS1874 incorporates shadowed-EEPROM memory

locations for key memory addresses that can be written

many times. By default the shadowed-EEPROM bit,

SEEB, is not set and these locations act as ordinary

EEPROM. By setting SEEB, these locations function like

SRAM cells, which allow an infinite number of write

cycles without concern of wearing out the EEPROM.

Setting SEEB also eliminates the requirement for the

EEPROM write time, tW. Because changes made with

SEEB enabled do not affect the EEPROM, these

changes are not retained through power cycles. The

power-on value is the last value written with SEEB dis-

abled. This function can be used to limit the number of

EEPROM writes during calibration or to change the

monitor thresholds periodically during normal operation

helping to reduce the number of times EEPROM is writ-

ten. Figure 19 indicates which locations are shadowed

EEPROM.

EEPROM

(256 BYTES)

FFh

I2C ADDRESS A0h

AUXILIARY DEVICE

MAIN DEVICE

00h

ALARM-

ENABLE ROW

(8 BYTES)

PASSWORD ENTRY

(PWE) (4 BYTES)

TABLE-SELECT

BYTE

FFh

80h

F8h

TABLE 01h

EEPROM

(120 BYTES)

F7h

7Fh

00h

LOWER

MEMORY

3W CONFIG

FFh

80h

E8h

TABLE 02h

NONLOOKUP

TABLE CONTROL

AND

CONFIGURATION

REGISTERS

E7h

80h

TABLE 04h

MOD

LOOKUP TABLE

(72 BYTES)

C7h

F8h TABLE 05h

ALARM-ENABLE ROW

(8 BYTES) FFh

80h TABLE 06h

TRACKING ERROR

LOOKUP TABLE

(36 BYTES) A3h

80h

TABLE 07h

DAC1 LUT

A3h

80h

TABLE 08h

DAC2 LUT

A3h

NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h.

IF ASEL = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN

TABLE 02h, REGISTER 8Ch.

NOTE 2: TABLE 00h DOES NOT EXIST.

NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE

MASK BIT IN TABLE 02h, REGISTER 89h.

Figure 19. Memory Map

The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is locat-

ed in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two

memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. For more

information about each of these bytes see the corresponding register description.

Lower Memory Register Map

DS1874

SFP+ Controller with Digital LDD Interface

30 ______________________________________________________________________________________

LOWER MEMORY

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex) ROW NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

00 <1>THRESHOLD0 TEMP ALARM HI TEMP ALARM LO TEMP WARN HI TEMP WARN LO

08 <1>THRESHOLD1 V

CC ALARM HI VCC ALARM LO VCC WARN HI VCC WARN LO

10 <1>THRESHOLD2 MON1 ALARM HI MON1 ALARM LO MON1 WARN HI MON1 WARN LO

18 <1>THRESHOLD3 MON2 ALARM HI MON2 ALARM LO MON2 WARN HI MON2 WARN LO

20 <1>THRESHOLD4 MON3 ALARM HI MON3 ALARM LO MON3 WARN HI MON3 WARN LO

28 <1>THRESHOLD5 MON4 ALARM HI MON4 ALARM LO MON4 WARN HI MON4 WARN LO

30–5F <1>EEPROM EE EE EE EE EE EE EE EE

60 <2>ADC

VALUES0TEMP VALUE VCC VALUE MON1 VALUE MON2 VALUE

68 <0>ADC

VALUES1

<2>MON3 VALUE <2>MON4 VALUE <2>RESERVED <0>STATUS <3>UPDATE

70 <2>ALARM/

WARN ALARM3ALARM2ALARM1 ALARM0 WARN3WARN2RESERVED

78 <0>TABLE

SELECT

<2>RESERVED <2>

RESERVED

<6>PWE MSW <6>PWE LSW <5>TBL

SEL

ACCESS

CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>

Read

Access All All All PW2 All N/A PW1 PW2 N/A PW2 All

Write

Access

See each

bit/byte

separately PW2 N/A

All and

DS1874

hardware

PW2 +

mode

bit

All All PW1 PW2 PW2 N/A PW1

Table 01h Register Map

The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist in Table 05h instead of here at Table 01h

with the MASK bit (Table 02h, Register 89h). If the row is configured to exist in Table 05h, then these locations are

empty in Table 01h.

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 31

TABLE 01h

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex)

ROW

NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–BF <7>EEPROM EE EE EE EE EE EE EE EE

C0–F7 <8>EEPROM EE EE EE EE EE EE EE EE

F8 <8>ALARM

ENABLE

ALARM

EN3

ALARM

EN2

ALARM

EN1

ALARM

EN0WARN EN3WARN EN2RESERVED RESERVED

ACCESS

CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>

Read

Access All All All PW2 All N/A PW1 PW2 N/A PW2 All

Write

Access

See each

bit/byte

separately PW2 N/A

All and

DS1874

hardware

PW2 +

mode

bit

All All PW1 PW2 PW2 N/A PW1

DS1874

Table 02h Register Map

SFP+ Controller with Digital LDD Interface

32 ______________________________________________________________________________________

TABLE 02h

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex)

ROW

NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80 <0>CONFIG0<8>MODE <4>TINDEX <4>MODULATION

<4>DAC1 VALUE <4>DAC2 VALUE

88 <8>CONFIG1SAMPLE

RATE CNFGA CNFGB CNFGC DEVICE

ADDRESS RESERVED RSHIFT1RSHIFT0

90 <8>SCALE0RESERVED VCC SCALE MON1 SCALE MON2 SCALE

98 <8>SCALE1MON3 FINE SCALE MON4 SCALE MON3 COARSE SCALE RESERVED

A0 <8>OFFSET0RESERVED VCC OFFSET MON1 OFFSET MON2 OFFSET

A8 <8>OFFSET1MON3 FINE OFFSET MON4 OFFSET MON3 COARSE OFFSET INTERNAL TEMP

OFFSET*

B0 <9>PWD VALUE PW1 MSW PW1 LSW PW2 MSW PW2 LSW

B8 <8>THRESHOLD LOS

RANGING

COMP

RANGING RESERVED ISTEP HTXP LTXP HLOS LLOS

C0 <8>PWD

ENABLE PW_ENA PW_ENB MODTI DAC1TI DAC2TI RESERVED LUTTC TBLSELPON

C8 <0>APC <4>MAN BIAS <4>MAN_

CNTL

<10>BIAS REGISTER <4>APC

DAC

<10>DEVICE

VER

D0 <8>HI BIAS

LUT HBATH HBATH HBATH HBATH HBATH HBATH HBATH HBATH

D8–E7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY

E8 <8>3W

CONFIG0RXCTRL1 RXCTRL2 SETCML SETLOS TXCTRL IMODMAX IBIASMAX SETPWCTRL

F0 <8>3W

CONFIG1SETTXDE RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED

F8 <0>3W

CONFIG2

<8>3WCTRL <8>ADDRESS <8>WRITE <10>READ <10>TXSTAT1 <10>TXSTAT2 RESERVED RESERVED

ACCESS

CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>

Read

Access All All All PW2 All N/A PW1 PW2 N/A PW2 All

Write

Access

See each

bit/byte

separately PW2 N/A

All and

DS1874

hardware

PW2 +

mode

bit

All All PW1 PW2 PW2 N/A PW1

The final result must be XORed with BB40h before writing to this register.

Table 04h Register Map

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 33

TABLE 04h (MODULATION LUT)

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex)

ROW

NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–C7 <8>LUT4 MOD MOD MOD MOD MOD MOD MOD MOD

ACCESS

CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>

Read

Access All All All PW2 All N/A PW1 PW2 N/A PW2 All

Write

Access

See each

bit/byte

separately PW2 N/A

All and

DS1874

hardware

PW2 +

mode

bit

All All PW1 PW2 PW2 N/A PW1

Table 05h Register Map

Table 05h is empty by default. It can be configured to contain the alarm and warning-enable bytes from Table 01h,

Registers F8h–FFh with the MASK bit enabled (Table 02h, Register 89h). In this case Table 01h is empty.

TABLE 05h

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex)

ROW

NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY

F8 <8>ALARM

ENABLE

ALARM

EN3

ALARM

EN2

ALARM

EN1

ALARM

EN0WARN EN3WARN EN2RESERVED RESERVED

Table 06h Register Map

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).

TABLE 06h (APC LUT)

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex)

ROW

NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–9F <8>LUT6 APC REF APC REF APC REF APC REF APC REF APC REF APC REF APC REF

A0 <8>LUT6 APC REF APC REF APC REF APC REF RESERVED RESERVED RESERVED RESERVED

Table 08h Register Map

DS1874

SFP+ Controller with Digital LDD Interface

34 ______________________________________________________________________________________

TABLE 07h (DAC1 LUT)

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex)

ROW

NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–9F <8>LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1

A0 <8>LUT7 DAC1 DAC1 DAC1 DAC1 RESERVED RESERVED RESERVED RESERVED

ACCESS

CODE <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>

Read

Access All All All PW2 All N/A PW1 PW2 N/A PW2 All

Write

Access

See each

bit/byte

separately PW2 N/A

All and

DS1874

hardware

PW2 +

mode

bit

All All PW1 PW2 PW2 N/A PW1

TABLE 08h (DAC2 LUT)

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex)

ROW

NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–9F <8>LUT8 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2

A0 <8>LUT8 DAC2 DAC2 DAC2 DAC2 RESERVED RESERVED RESERVED RESERVED

Table 07h Register Map

Auxiliary A0h Memory Register Map

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).

AUXILIARY MEMORY (A0h)

WORD 0 WORD 1 WORD 2 WORD 3

ROW

(hex)

ROW

NAME BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

00–FF <8>AUX EE EE EE EE EE EE EE EE EE

DS1874

Lower Memory Register Descriptions

Lower Memory, Register 00h–01h: TEMP ALARM HI

Lower Memory, Register 04h–05h: TEMP WARN HI

FACTORY DEFAULT 7FFFh

READ ACCESS All

WRITE ACCESS PW2 or (PW1 and WLOWER)

MEMORY TYPE Nonvolatile (SEE)

00h, 04h S 26 2

5 2

4 2

3 2

2 2

1 2

01h, 05h 2-1 2

-2 2

-3 2

-4 2

-5 2

-6 2

-7 2

-8

BIT 7 BIT 0

Temperature measurement updates above this two’s complement threshold set corresponding alarm or warning bits.

Temperature measurement updates equal to or below this threshold clear alarm or warning bits.

Lower Memory, Register 02h–03h: TEMP ALARM LO

Lower Memory, Register 06h–07h: TEMP WARN LO

FACTORY DEFAULT 8000h

READ ACCESS All

WRITE ACCESS PW2 or (PW1 and WLOWER)

MEMORY TYPE Nonvolatile (SEE)

02h, 06h S 26 2

5 2

4 2

3 2

2 2

1 2

03h, 07h 2-1 2

-2 2

-3 2

-4 2

-5 2

-6 2

-7 2

-8

BIT 7 BIT 0

Temperature measurement updates below this two’s complement threshold set corresponding alarm or warning bits.

Temperature measurement updates equal to or above this threshold clear alarm or warning bits.

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 35

DS1874

SFP+ Controller with Digital LDD Interface

36 ______________________________________________________________________________________

Lower Memory, Register 08h–09h: VCC ALARM HI

Lower Memory, Register 0Ch–0Dh: VCC WARN HI

Lower Memory, Register 10h–11h: MON1 ALARM HI

Lower Memory, Register 14h–15h: MON1 WARN HI

Lower Memory, Register 18h–19h: MON2 ALARM HI

Lower Memory, Register 1Ch–1Dh: MON2 WARN HI

Lower Memory, Register 20h–21h: MON3 ALARM HI

Lower Memory, Register 24h–25h: MON3 WARN HI

Lower Memory, Register 28h–29h: MON4 ALARM HI

Lower Memory, Register 2Ch–2Dh: MON4 WARN HI

FACTORY DEFAULT FFFFh

READ ACCESS All

WRITE ACCESS PW2 or (PW1 and WLOWER)

MEMORY TYPE Nonvolatile (SEE)

08h, 0Ch, 10h,

14h, 18h, 1Ch,

20h, 24h, 28h,

2Ch

215 214 2

13 2

12 2

11 2

10 2

9 2

09h, 0Dh, 11h,

15h, 19h, 1Dh,

21h, 25h, 29h,

2Dh

27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Voltage measurement updates above this unsigned threshold set corresponding alarm or warning bits. Voltage

measurements equal to or below this threshold clear alarm or warning bits.

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 37

Lower Memory, Register 0Ah–0Bh: VCC ALARM LO

Lower Memory, Register 0Eh–0Fh: VCC WARN LO

Lower Memory, Register 12h–13h: MON1 ALARM LO

Lower Memory, Register 16h–17h: MON1 WARN LO

Lower Memory, Register 1Ah–1Bh: MON2 ALARM LO

Lower Memory, Register 1Eh–1Fh: MON2 WARN LO

Lower Memory, Register 22h–23h: MON3 ALARM LO

Lower Memory, Register 26h–27h: MON3 WARN LO

Lower Memory, Register 2Ah–2Bh: MON4 ALARM LO

Lower Memory, Register 2Eh–2Fh: MON4 WARN LO

FACTORY DEFAULT 0000h

READ ACCESS All

WRITE ACCESS PW2 or (PW1 and WLOWER)

MEMORY TYPE Nonvolatile (SEE)

0Ah, 0Eh,

12h, 16h,

1Ah, 1Eh,

22h, 26h,

2Ah, 2Eh

215 214 2

13 2

12 2

11 2

10 2

9 2

0Bh, 0Fh,

13h, 17h,

1Bh, 1Fh,

23h, 27h,

2Bh, 2Fh

27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Voltage measurement updates below this unsigned threshold set corresponding alarm or warning bits. Voltage

measurements equal to or above this threshold clear alarm or warning bits.

DS1874

SFP+ Controller with Digital LDD Interface

38 ______________________________________________________________________________________

Lower Memory, Register 30h–5Fh: EE

FACTORY DEFAULT 00h

READ ACCESS All

WRITE ACCESS PW2 or (PW1 and WLOWER)

MEMORY TYPE Nonvolatile (EE)

30h to 5Fh EE EE EE EE EE EE EE EE

BIT 7 BIT 0

PW2 level access-controlled EEPROM.

POWER-ON VALUE 0000h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE Volatile

60h S 26 2

5 2

4 2

3 2

2 2

1 2

61h 2-1 2

-2 2

-3 2

-4 2

-5 2

-6 2

-7 2

-8

BIT 7 BIT 0

Signed two’s complement direct-to-temperature measurement.

Lower Memory, Register 60h–61h: TEMP VALUE

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 39

Lower Memory, Register 6Ch–6Dh: RESERVED

POWER-ON VALUE 00h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE

6Ch, 6Dh 0 0 0 0 0 0 0 0

BIT 7 BIT 0

These registers are reserved. The value when read is 00h.

POWER-ON VALUE 0000h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE Volatile

62h, 64h,

66h, 68h,

6Ah

215 214 2

13 2

12 2

11 2

10 2

9 2

63h, 65h,

67h, 69h,

6Bh

27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Left-justified unsigned voltage measurement.

Lower Memory, Register 62h–63h: VCC VALUE

Lower Memory, Register 64h–65h: MON1 VALUE

Lower Memory, Register 66h–67h: MON2 VALUE

Lower Memory, Register 68h–69h: MON3 VALUE

Lower Memory, Register 6Ah–6Bh: MON4 VALUE

DS1874

SFP+ Controller with Digital LDD Interface

40 ______________________________________________________________________________________

POWER-ON VALUE X0XX 0XXXb

READ ACCESS All

WRITE ACCESS See below

MEMORY TYPE Volatile

Write Access N/A All N/A All All N/A N/A N/A

6Eh TXDS TXDC IN1S RSELS RSELC TXF RXL RDYB

BIT 7 BIT 0

BIT 7

TXDS: TXD Status Bit. Reflects the logic state of the TXD pin (read only).

0 = TXD pin is logic-low.

1 = TXD pin is logic-high.

BIT 6

TXDC: TXD Software Control Bit. This bit allows for software control that is identical to the TXD pin.

See the section on TXD for further information. Its value is wire-ORed with the logic value of the

TXD pin (writable by all users).

0 = (Default).

1 = Forces the device into a TXD state regardless of the value of the TXD pin.

BIT 5

IN1S: IN1 Status Bit. Reflects the logic state of the IN1 pin (read only).

0 = IN1 pin is logic-low.

1 = IN1 pin is logic-high.

BIT 4

RSELS: RSEL Status Bit. Reflects the logic state of the RSEL pin (read only).

0 = RSEL pin is logic-low.

1 = RSEL pin is logic-high.

BIT 3

RSELC: RSEL Software Control Bit. This bit allows for software control that is identical to the RSEL

pin. Its value is wire-ORed with the logic value of the RSEL pin to create the RSELOUT pin’s logic

value (writable by all users).

0 = (Default).

1 = Forces the device into a RSEL state regardless of the value of the RSEL pin.

BIT 2

TXF: Reflects the driven state of the TXF pin (read only).

0 = TXF pin is driven low.

1 = TXF pin is pulled high.

BIT 1

RXL: Reflects the driven state of the LOSOUT pin (read only).

0 = LOSOUT pin is driven low.

1 = LOSOUT pin is pulled high.

BIT 0

RDYB: Ready Bar.

0 = VCC is above POA.

1 = VCC is below POA and/or too low to communicate over the I2C bus.

Lower Memory, Register 6Eh: STATUS

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 41

Lower Memory, Register 6Fh: UPDATE

POWER-ON VALUE 00h

READ ACCESS All

WRITE ACCESS All and DS1874 Hardware

MEMORY TYPE Volatile

6Fh TEMP RDY VCC RDY MON1 RDY MON2 RDY MON3 RDY MON4 RDY RESERVED RSSIR

BIT 7 BIT 0

BITS 7:2

Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is

completed. These bits can be cleared so that a completion of a new conversion is verified.

BIT 1 RESERVED

BIT 0

RSSIR: RSSI Range. Reports the range used for conversion update of MON3.

0 = Fine range is the reported value.

1 = Coarse range is the reported value.

DS1874

SFP+ Controller with Digital LDD Interface

42 ______________________________________________________________________________________

POWER-ON VALUE 10h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE Volatile

70h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO

BIT 7 BIT 0

BIT 7

TEMP HI: High-alarm status for temperature measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 6

TEMP LO: Low-alarm status for temperature measurement.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

BIT 5

VCC HI: High-alarm status for VCC measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 4

VCC LO: Low-alarm status for VCC measurement. This bit is set when the VCC supply is below the POA trip

point value. It clears itself when a VCC measurement is completed and the value is above the low threshold.

0 = Last measurement was equal to or above threshold setting.

1 = (Default) Last measurement was below threshold setting.

BIT 3

MON1 HI: High-alarm status for MON1 measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 2

MON1 LO: Low-alarm status for MON1 measurement.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

BIT 1

MON2 HI: High-alarm status for MON2 measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 0

MON2 LO: Low-alarm status for MON2 measurement.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

Lower Memory, Register 70h: ALARM3

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 43

Lower Memory, Register 71h: ALARM2

POWER-ON VALUE 00h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE Volatile

71h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED TXFINT

BIT 7 BIT 0

BIT 7

MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this alarm.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 6

MON3 LO: Low-alarm status for MON3 measurement. A TXD event does not clear this alarm.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

BIT 5

MON4 HI: High-alarm status for MON4 measurement. A TXD event does not clear this alarm.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 4

MON4 LO: Low-alarm status for MON4 measurement. A TXD event does not clear this alarm.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

BITS 3:1 RESERVED

BIT 0

TXFINT: TXF Interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with their

corresponding enable bits in addition to nonmaskable alarms TXP HI, TXP LO, BIAS MAX, and HBAL. The

enable bits are found in Table 01h, Registers F8h–FFh.

DS1874

SFP+ Controller with Digital LDD Interface

44 ______________________________________________________________________________________

Lower Memory, Register 72h: ALARM1

POWER-ON VALUE 00h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE Volatile

72h RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO

BIT 7 BIT 0

BITS 7:4 RESERVED

BIT 3

HBAL: High-Bias Alarm Status; Fast Comparison. A TXD event clears this alarm.

0 = (Default) Last comparison was below threshold setting.

1 = Last comparison was above threshold setting.

BIT 2 RESERVED

BIT 1

TXP HI: High-Alarm Status TXP; Fast Comparison. A TXD event clears this alarm.

0 = (Default) Last comparison was below threshold setting.

1 = Last comparison was above threshold setting.

BIT 0

TXP LO: Low-Alarm Status TXP; Fast Comparison. A TXD event clears this alarm.

0 = (Default) Last comparison was above threshold setting.

1 = Last comparison was below threshold setting.

POWER-ON VALUE 00h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE Volatile

73h LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED RESERVED RESERVED

BIT 7 BIT 0

BIT 7

LOS HI: High-Alarm Status for MON3; Fast Comparison. A TXD event does not clear this alarm.

0 = (Default) Last comparison was below threshold setting.

1 = Last comparison was above threshold setting.

BIT 6

LOS LO: Low-Alarm Status for MON3; Fast Comparison. A TXD event does not clear this alarm.

0 = (Default) Last comparison was above threshold setting.

1 = Last comparison was below threshold setting.

BITS 5:4 RESERVED

BIT 3

BIAS MAX: Alarm status for maximum digital setting of BIAS. A TXD event clears this alarm.

0 = (Default) The value for BIAS is equal to or below the IBIASMAX register.

1 = Requested value for BIAS is greater than the IBIASMAX register.

BITS 2:0 RESERVED

Lower Memory, Register 73h: ALARM0

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 45

Lower Memory, Register 74h: WARN3

POWER-ON VALUE 10h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE Volatile

74h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO

BIT 7 BIT 0

BIT 7

TEMP HI: High-warning status for temperature measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 6

TEMP LO: Low-warning status for temperature measurement.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

BIT 5

VCC HI: High-warning status for VCC measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 4

VCC LO: Low-warning status for VCC measurement. This bit is set when the VCC supply is below the POA

trip point value. It clears itself when a VCC measurement is completed and the value is above the low

threshold.

0 = Last measurement was equal to or above threshold setting.

1 = (Default) Last measurement was below threshold setting.

BIT 3

MON1 HI: High-warning status for MON1 measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 2

MON1 LO: Low-warning status for MON1 measurement.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

BIT 1

MON2 HI: High-warning status for MON2 measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 0

MON2 LO: Low-warning status for MON2 measurement.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

DS1874

SFP+ Controller with Digital LDD Interface

46 ______________________________________________________________________________________

Lower Memory, Register 75h: WARN2

POWER-ON VALUE 00h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE Volatile

75h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED

BIT 7 BIT 0

BIT 7

MON3 HI: High-warning status for MON3 measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 6

MON3 LO: Low-warning status for MON3 measurement.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

BIT 5

MON4 HI: High-warning status for MON4 measurement.

0 = (Default) Last measurement was equal to or below threshold setting.

1 = Last measurement was above threshold setting.

BIT 4

MON4 LO: Low-warning status for MON4 measurement.

0 = (Default) Last measurement was equal to or above threshold setting.

1 = Last measurement was below threshold setting.

BITS 3:0 RESERVED

POWER-ON VALUE 00h

READ ACCESS All

WRITE ACCESS N/A

MEMORY TYPE

These registers are reserved. The value when read is 00h.

Lower Memory, Register 76h–7Ah: RESERVED MEMORY

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 47

Lower Memory, Register 7Bh–7Eh: Password Entry (PWE)

POWER-ON VALUE FFFF FFFFh

READ ACCESS N/A

WRITE ACCESS All

MEMORY TYPE Volatile

7Bh 231 230 2

29 2

28 227 2

26 2

25 2

7Ch 223 222 2

21 2

20 219 2

18 2

17 2

7Dh 215 214 2

13 2

12 2

11 2

10 2

9 2

7Eh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

There are two passwords for the DS1874. Each password is 4 bytes long. The lower level password (PW1) has all the

access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of

PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory. At

power-up, all PWE bits are set to 1. All reads at this location are 0.

POWER-ON VALUE TBLSELPON (Table 02h, Register C7h)

READ ACCESS All

WRITE ACCESS All

MEMORY TYPE Volatile

7Fh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

The upper memory tables of the DS1874 are accessible by writing the desired table value in this register. The power-on

value of this register is defined by the value written to TBLSELPON (Table 02h, Register C7h).

Lower Memory, Register 7Fh: Table Select (TBL SEL)

DS1874

SFP+ Controller with Digital LDD Interface

48 ______________________________________________________________________________________

Table 01h Register Descriptions

Table 01h, Register 80h–BFh: EEPROM

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A)

WRITE ACCESS PW2 or (PW1 and RWTBL1A)

MEMORY TYPE Nonvolatile (EE)

80h–BFh EE EE EE EE EE EE EE EE

BIT 7 BIT 0

EEPROM for PW1 and/or PW2 level access.

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1B) or (PW1 and RTBL1B)

WRITE ACCESS PW2 or (PW1 and RWTBL1B)

MEMORY TYPE Nonvo latile (EE)

C0h–F7h EE EE EE EE EE EE EE EE

BIT 7 BIT 0

EEPROM for PW1 and/or PW2 level access.

Table 01h, Register C0h–F7h: EEPROM

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 49

Table 01h, Register F8h: ALARM EN3

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

WRITE ACCESS PW2 or (PW1 and RWTBL1C)

MEMORY TYPE Nonvolatile (SEE)

F8h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO

BIT 7 BIT 0

Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory,

or 05h.

BIT 7

TEMP HI:

0 = Disables interrupt from TEMP HI alarm.

1 = Enables interrupt from TEMP HI alarm.

BIT 6

TEMP LO:

0 = Disables interrupt from TEMP LO alarm.

1 = Enables interrupt from TEMP LO alarm.

BIT 5

VCC HI:

0 = Disables interrupt from VCC HI alarm.

1 = Enables interrupt from VCC HI alarm.

BIT 4

VCC LO:

0 = Disables interrupt from VCC LO alarm.

1 = Enables interrupt from VCC LO alarm.

BIT 3

MON1 HI:

0 = Disables interrupt from MON1 HI alarm.

1 = Enables interrupt from MON1 HI alarm.

BIT 2

MON1 LO:

0 = Disables interrupt from MON1 LO alarm.

1 = Enables interrupt from MON1 LO alarm.

BIT 1

MON2 HI:

0 = Disables interrupt from MON2 HI alarm.

1 = Enables interrupt from MON2 HI alarm.

BIT 0

MON2 LO:

0 = Disables interrupt from MON2 LO alarm.

1 = Enables interrupt from MON2 LO alarm.

DS1874

SFP+ Controller with Digital LDD Interface

50 ______________________________________________________________________________________

Table 01h, Register F9h: ALARM EN2

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

WRITE ACCESS PW2 or (PW1 and RWTBL1C)

MEMORY TYPE Nonvolatile (SEE)

F9h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED

BIT 7 BIT 0

Layout is identical to ALARM2 in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory,

05h.

BIT 7

MON3 HI:

0 = Disables interrupt from MON3 HI alarm.

1 = Enables interrupt from MON3 HI alarm.

BIT 6

MON3 LO:

0 = Disables interrupt from MON3 LO alarm.

1 = Enables interrupt from MON3 LO alarm.

BIT 5

MON4 HI:

0 = Disables interrupt from MON4 HI alarm.

1 = Enables interrupt from MON4 HI alarm.

BIT 4

MON4 LO:

0 = Disables interrupt from MON4 LO alarm.

1 = Enables interrupt from MON4 LO alarm.

BIT 3:0 RESERVED

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 51

Table 01h, Register FAh: ALARM EN1

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

WRITE ACCESS PW2 or (PW1 and RWTBL1C)

MEMORY TYPE Nonvolatile (SEE)

FAh RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO

BIT 7 BIT 0

Layout is identical to ALARM1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see

Figure 12) logic. The MASK bit (Table 02h, Register 89h) determines whether this memory exists in Table 01h or

05h.

BITS 7:4 RESERVED

BIT 3

HBAL:

0 = Disables interrupt from HBAL alarm.

1 = Enables interrupt from HBAL alarm.

BIT 2 RESERVED

BIT 1

TXP HI:

0 = Disables interrupt from TXP HI alarm.

1 = Enables interrupt from TXP HI alarm.

BIT 0

TXP LO:

0 = Disables interrupt from TXP LO alarm.

1 = Enables interrupt from TXP LO alarm.

DS1874

SFP+ Controller with Digital LDD Interface

52 ______________________________________________________________________________________

Table 01h, Register FBh: ALARM EN0

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

WRITE ACCESS PW2 or (PW1 and RWTBL1C)

MEMORY TYPE Nonvolatile (SEE)

FBh LOS HI LOS LO RESERVED RESERVED BIAS MAX RESERVED RESERVED RESERVED

BIT 7 BIT 0

Layout is identical to ALARM0 in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 89h) determines

whether this memory exists in Table 01h or 05h.

BIT 7

LOS HI: Enables alarm to create TXFINT (Lower Memory, Register 71h) logic.

0 = Disables interrupt from LOS HI alarm.

1 = Enables interrupt from LOS HI alarm.

BIT 6

LOS LO: Enables alarm to create TXFINT (Lower Memory, Register 71h) logic.

0 = Disables interrupt from LOS LO alarm.

1 = Enables interrupt from LOS LO alarm.

BITS 5:4 RESERVED

BIT 3

BIAS MAX: Enables alarm to create internal signal FETG (see Figure 12) logic.

0 = Disables interrupt from BIAS MAX alarm.

1 = Enables interrupt from BIAS MAX alarm.

BITS 2:0 RESERVED

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 53

Table 01h, Register FCh: WARN EN3

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

WRITE ACCESS PW2 or (PW1 and RWTBL1C)

MEMORY TYPE Nonvolatile (SEE)

F8h TEMP HI TEMP LO VCC HI VCC LO MON1 HI MON1 LO MON2 HI MON2 LO

BIT 7 BIT 0

Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory,

or 05h.

BIT 7

TEMP HI:

0 = Disables interrupt from TEMP HI warning.

1 = Enables interrupt from TEMP HI warning.

BIT 6

TEMP LO:

0 = Disables interrupt from TEMP LO warning.

1 = Enables interrupt from TEMP LO warning.

BIT 5

VCC HI:

0 = Disables interrupt from VCC HI warning.

1 = Enables interrupt from VCC HI warning.

BIT 4

VCC LO:

0 = Disables interrupt from VCC LO warning.

1 = Enables interrupt from VCC LO warning.

BIT 3

MON1 HI:

0 = Disables interrupt from MON1 HI warning.

1 = Enables interrupt from MON1 HI warning.

BIT 2

MON1 LO:

0 = Disables interrupt from MON1 LO warning.

1 = Enables interrupt from MON1 LO warning.

BIT 1

MON2 HI:

0 = Disables interrupt from MON2 HI warning.

1 = Enables interrupt from MON2 HI warning.

BIT 0

MON2 LO:

0 = Disables interrupt from MON2 LO warning.

1 = Enables interrupt from MON2 LO warning.

DS1874

SFP+ Controller with Digital LDD Interface

54 ______________________________________________________________________________________

Table 01h, Register FDh: WARN EN2

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

WRITE ACCESS PW2 or (PW1 and RWTBL1C)

MEMORY TYPE Nonvolatile (SEE)

F9h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED RESERVED RESERVED RESERVED

BIT 7 BIT 0

Layout is identical to WARN2 in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory,

05h.

BIT 7

MON3 HI:

0 = Disables interrupt from MON3 HI warning.

1 = Enables interrupt from MON3 HI warning.

BIT 6

MON3 LO:

0 = Disables interrupt from MON3 LO warning.

1 = Enables interrupt from MON3 LO warning.

BIT 5

MON4 HI:

0 = Disables interrupt from MON4 HI warning.

1 = Enables interrupt from MON4 HI warning.

BIT 4

MON4 LO:

0 = Disables interrupt from MON4 LO warning.

1 = Enables interrupt from MON4 LO warning.

BITS 3:0 RESERVED

POWER-ON VALUE 00h

READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)

WRITE ACCESS PW2 or (PW1 and RWTBL1C)

MEMORY TYPE Nonvolatile (SEE)

These registers are reserved.

Table 01h, Register FEh–FFh: RESERVED

DS1874

SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 55

Table 02h Register Descriptions

Table 02h, Register 80h: MODE

POWER-ON VALUE 3Fh

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RTBL246)

MEMORY TYPE Volatile

80h SEEB RESERVED DAC1 EN DAC2 EN AEN MOD EN APC EN BIAS EN

BIT 7 BIT 0

BIT 7

SEEB:

0 = (Default) Enables EEPROM writes to SEE bytes.

1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part

is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the

SEE locations again for data to be written to the EEPROM.

BIT 6 RESERVED

BIT 5

DAC1 EN:

0 = DAC1 VALUE is writable by the user and the LUT recalls are disabled. This allows users to

interactively test their modules by writing the values for DAC1. The output is updated with the new

value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.

1 = (Default) Enables auto control of the LUT for DAC1 VALUE.

BIT 4

DAC2 EN:

0 = DAC2 VALUE is writable by the user and the LUT recalls are disabled. This allows users to

interactively test their modules by writing the values for DAC2. The output is updated with the new

value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.

1 = (Default) Enables auto control of the LUT for DAC2 VALUE.

BIT 3

AEN:

0 = The temperature-calculated index value TINDEX is writable by users and the updates of

calculated indexes are disabled. This allows users to interactively test their modules by

controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC

registers after the next completion of a temperature conversion.

BIT 2

MOD EN:

0 = Modulation is writable by the user and the LUT recalls are disabled. This allows users to

interactively test their modules by writing the DAC value for modulation. The output is updated with the

new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle.

1 = (Default) Enables auto control of the LUT for modulation.

BIT 1

APC EN:

0 = APC DAC is writable by the user and the LUT recalls are disabled. This allows users to

interactively test their modules by writing the DAC value for APC reference. The output is updated with

the new value at the end of the write cycle through the 3-wire interface. The I2C STOP condition is the

end of the write cycle.

1 = (Default) Enables auto control of the LUT for APC reference.

BIT 0

BIAS EN:

0 = BIAS register is controlled by the user and the APC is in manual mode. The BIAS register value

is written with the use of the 3-wire interface. This allows the user to interactively test their modules

by writing the DAC value for bias.

1 = (Default) Enables auto control for the APC feedback.

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56 ______________________________________________________________________________________

Table 02h, Register 81h: Temperature Index (TINDEX)

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS (PW2 and AEN = 0) or (PW1 and RWTBL246 and AEN = 0)

MEMORY TYPE Volatile

81h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

Holds the calculated index based on the temperature measurement. This index is used for the address during

lookup of Tables 04h, 06h–08h. Temperature measurements below -40°C or above +102°C are clamped to 08h and

C7h, respectively. The calculation of TINDEX is as follows:

TINDEX =Temp _ Value +40°C

2°C

+80h

For the temperature-indexed LUTs, the index used during the lookup function for each table is as follows:

Table 04h (MOD) 1 TINDEX6 TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1 TINDEX0

Table 06h (APC) 1 0 TINDEX6 TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1

Table 07h (DAC1) 1 0 TINDEX6 TINDEX5 TINDEX4TINDEX3 TINDEX2 TINDEX1

Table 08h (DAC2) 1 0 TINDEX6 TINDEX5TINDEX4 TINDEX3 TINDEX2 TINDEX1

FACTORY DEFAULT 0000h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS (PW2 and MOD EN = 0) or (PW1 and RWTBL246 and MOD EN = 0)

MEMORY TYPE Volatile

82h 0 0 0 0 0 0 0 28

83h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

The digital value used for MODULATION and recalled from Table 04h at the adjusted memory address found in

TINDEX. This register is updated at the end of the temperature conversion.

Table 02h, Register 82h–83h: MODULATION REGISTER

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Table 02h, Register 84h–85h: DAC1 VALUE

FACTORY DEFAULT 0000h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS (PW2 and DAC1 EN = 0) or (PW1 and RWTBL246 and DAC1 EN = 0)

MEMORY TYPE Volatile

84h 0 0 0 0 0 0 0 28

85h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

The digital value used for DAC1 and recalled from Table 07h at the adjusted memory address found in TINDEX.

This register is updated at the end of the temperature conversion.

VDAC1 =REFIN

512

DAC1 VALUE

FACTORY DEFAULT 0000h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS (PW2 and DAC2 EN = 0) or (PW1 and RWTBL246 and DAC2 EN = 0)

MEMORY TYPE Volatile

86h 0 0 0 0 0 0 0 28

87h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

The digital value used for DAC2 and recalled from Table 08h at the adjusted memory address found in TINDEX. This

VDAC2 =REFIN

512

DAC2 VALUE

Table 02h, Register 86h–87h: DAC2 VALUE

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SFP+ Controller with Digital LDD Interface

58 ______________________________________________________________________________________

Table 02h, Register 88h: SAMPLE RATE

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

88h SEE SEE SEE SEE SEE APC_SR2APC_SR1APC_SR0

BIT 7 BIT 0

BITS 7:3 SEE

BITS 2:0

APC_SR[2:0]: 3-bit sample rate for comparison of APC control. Defines the sample rate for comparison

of APC control.

APC_SR[2:0] Sample Period (tREP) (ns)

000b 800

001b 1200

010b 1600

011b 2000

100b 2800

101b 3200

110b 4400

111b 6400

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FACTORY DEFAULT 80h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

89h LOSC RESERVED INV LOS ASEL MASK INVRSOUT RESERVED RESERVED

BIT 7 BIT 0

BIT 7

LOSC: LOS Configuration. Defines the source for the LOSOUT pin (see Figure 13).

0 = LOS LO alarm is used as the source.

1 = (Default) LOS input pin is used as the source.

BIT 6 RESERVED

BIT 5

INV LOS: Inverts the buffered input pin LOS to output pin LOSOUT (see Figure 13).

0 = Noninverted LOS to LOSOUT pin.

1 = Inverted LOS to LOSOUT pin.

BIT 4

ASEL: Address Select.

0 = Device address is A2h.

1 = Byte DEVICE ADDRESS in Table 02h, Register 8Ch is used as the device address.

BIT 3

MASK:

0 = Alarm-enable row exists at Table 01h, Registers F8h–FFh. Table 05h, Registers F8h–FFh are

empty.

1 = Alarm-enable row exists at Table 05h, Registers F8h–FFh. Table 01h, Registers F8h–FFh are

empty.

BIT 2

INVRSOUT: Allow for inversion of RSELOUT pin (see Figure 13).

0 = RSELOUT is not inverted.

1 = RSELOUT is inverted.

BITS 1:0 RESERVED

Table 02h, Register 89h: CNFGA

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60 ______________________________________________________________________________________

Table 02h, Register 8Ah: CNFGB

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

8Ah IN1C INVOUT1 RESERVED RESERVED RESERVED ALATCH QTLATCH WLATCH

BIT 7 BIT 0

BIT 7

IN1C: IN1 Software Control Bit (see Figure 13).

0 = IN1 pin’s logic controls OUT1 pin.

1 = OUT1 is active (bit 6 defines the polarity).

BIT 6

INVOUT1: Inverts the active state for OUT1 (see Figure 13).

0 = Noninverted.

1 = Inverted.

BITS 5:3 RESERVED

BIT 2

ALATCH: ADC Alarm’s Comparison Latch. Lower Memory, Registers 70h–71h.

0 = ADC alarm flags reflect the status of the last comparison.

1 = ADC alarm flags remain set.

BIT 1

QTLATCH: Quick Trip’s Comparison Latch. Lower Memory, Registers 72h–73h.

0 = QT alarm flags reflect the status of the last comparison.

1 = QT alarm flags remain set.

BIT 0

WLATCH: ADC Warning’s Comparison Latch. Lower Memory, Registers 74h–75h.

0 = ADC warning flags reflect the status of the last comparison.

1 = ADC warning flags remain set.

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Table 02h, Register 8Bh: CNFGC

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

8Bh RESERVED RESERVED TXDM34 TXDFG TXDFLT TXDIO RSSI_FC RSSI_FF

BIT 7 BIT 0

BITS 7:6 RESERVED

BIT 5

TXDM34: Enables TXD to reset alarms and warnings associated to MON3 and MON4 during a TXD

event.

0 = TXD event has no effect on the MON3 and MON4 alarms, warnings, and quick trips.

1 = MON3 and MON4 alarms, warnings, and quick trips are reset during a TXD event.

BIT 4

TXDFG: See Figure 12.

0 = FETG, an internal signal, has no effect on TXDOUT.

1 = FETG is enabled and ORed with other possible signals to create TXDOUT.

BIT 3

TXDFLT: See Figure 12.

0 = TXF pin has no effect on TXDOUT.

1 = TXF pin is enabled and ORed with other possible signals to create TXDOUT.

BIT 2

TXDIO: See Figure 12.

0 = (Default) TXD input signal is enabled and ORed with other possible signals to create TXDOUT.

1 = TXD input signal has no effect on TXDOUT.

BITS 1:0

RSSI_FC and RSSI_FF: RSSI Force Coarse and RSSI Force Fine. Control bits for RSSI mode of

operation on the MON3 conversion.

00b = Normal RSSI mode of operation (default).

01b = The fine settings of scale and offset are used for MON3 conversions.

10b = The coarse settings of scale and offset are used for MON3 conversions.

11b = Normal RSSI mode of operation.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

8Ch 2726 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

This value becomes the I2C slave address for the main memory when the ASEL (Table 02h, Register 89h) bit is

set. If A0h is programmed to this register, the auxiliary memory is disabled.

Table 02h, Register 8Ch: DEVICE ADDRESS

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62 ______________________________________________________________________________________

Table 02h, Register 8Dh: RESERVED

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

This register is reserved.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

8Eh RESERVED MON12MON11MON10RESERVED MON22MON21MON20

BIT 7 BIT 0

Allows for right-shifting the final answer of MON1 and MON2 voltage measurements. This allows for scaling the

measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted

to the correct LSB.

FACTORY DEFAULT 30h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

8Fh RESERVED MON32MON31MON30RESERVED MON42MON41MON40

BIT 7 BIT 0

Allows for right-shifting the final answer of MON3 and MON4 voltage measurements. This allows for scaling the

measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted

to the correct LSB. The MON3 right-shifting is only available for the fine mode of operation. The coarse mode does

not right-shift.

Table 02h, Register 8Eh: RIGHT-SHIFT1(RSHIFT1)

Table 02h, Register 8Fh: RIGHT-SHIFT0(RSHIFT0)

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Table 02h, Register 90h–91h: RESERVED

FACTORY DEFAULT 0000h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

These registers are reserved.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

These registers are reserved.

FACTORY CALIBRATED N/A

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

92h, 94h,

96h, 98h,

9Ah, 9Ch

215 214 2

13 2

12 2

11 2

10 2

9 2

93h, 95h,

97h, 99h,

9Bh, 9Dh

27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Controls the scaling or gain of the FS voltage measurements. The factory-calibrated value produces an FS

voltage of 6.5536V for VCC; 2.5V for MON1, MON2, MON4; and 0.3125V for MON3 fine.

Table 02h, Register 92h–93h: VCC SCALE

Table 02h, Register 94h–95h: MON1 SCALE

Table 02h, Register 96h–97h: MON2 SCALE

Table 02h, Register 98h–99h: MON3 FINE SCALE

Table 02h, Register 9Ah–9Bh: MON4 SCALE

Table 02h, Register 9Ch–9Dh: MON3 COARSE SCALE

Table 02h, Register 9Eh–A1h: RESERVED

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SFP+ Controller with Digital LDD Interface

64 ______________________________________________________________________________________

Table 02h, Register A2h–A3h: VCC OFFSET

Table 02h, Register A4h–A5h: MON1 OFFSET

Table 02h, Register A6h–A7h: MON2 OFFSET

Table 02h, Register A8h–A9h: MON3 FINE OFFSET

Table 02h, Register AAh–ABh: MON4 OFFSET

Table 02h, Register ACh–ADh: MON3 COARSE OFFSET

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

A2h, A4h,

A6h, A8h,

AAh, ACh

S S 215 214 2

13 2

12 2

11 2

A3h, A5h,

A7h, A9h,

ABh, ADh

29 2

8 2

7 2

6 2

5 2

4 2

3 2

BIT 7 BIT 0

Allows for offset control of these voltage measurements if desired. This number is two’s complement.

FACTORY CALIBRATED

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

AEh S 282726 2

5 2

4 2

3 2

AFh 21 2

0 2

-1 2

-2 2

-3 2

-4 2

-5 2

-6

BIT 7 BIT 0

Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h

before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius.

Table 02h, Register AEh–AFh: INTERNAL TEMP OFFSET

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Table 02h, Register B0h–B3h: PW1

FACTORY DEFAULT FFFF FFFFh

READ ACCESS N/A

WRITE ACCESS PW2 or (PW1 and WPW1)

MEMORY TYPE Nonvolatile (SEE)

B0h 231 230 2

29 2

28 2

27 2

26 2

25 2

B1h 223 2

22 2

21 2

20 2

19 2

18 2

17 2

B2h 215 214 2

13 2

12 2

11 2

10 2

9 2

B3h 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the

PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without

writing the password entry. All reads of this register are 00h.

FACTORY DEFAULT FFFF FFFFh

READ ACCESS N/A

WRITE ACCESS PW2

MEMORY TYPE Nonvolatile (SEE)

B4h 231 230 2

29 2

28 2

27 2

26 2

25 2

B5h 223 2

22 2

21 2

20 2

19 2

18 2

17 2

B6h 215 214 2

13 2

12 2

11 2

10 2

9 2

B7h 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE

value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-on without writing the

password entry. All reads of this register are 00h.

Table 02h, Register B4h–B7h: PW2

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66 ______________________________________________________________________________________

Table 02h, Register B8h: LOS RANGING

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

B8h RESERVED HLOS2 HLOS1 HLOS0 RESERVED LLOS2 LLOS21 LLOS0

BIT 7 BIT 0

This register controls the full-scale range of the quick-trip monitoring for the differential input’s of MON3.

BIT 7 RESERVED (Default = 0)

BITS 6:4

HLOS[2:0]: HLOS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for high LOS

found on MON3. Default is 000b and creates an FS of 1.25V.

HLOS[2:0] % of 1.25V FS Voltage

000b 100.00 1.250

001b 80.02 1.0003

010b 66.69 0.8336

011b 50.10 0.6263

100b 40.05 0.5006

101b 33.38 0.4173

110b 26.62 0.3328

111b 25.04 0.3130

BIT 3 RESERVED (Default = 0)

BITS 2:0

LLOS[2:0]: LLOS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for low LOS

found on MON3. Default is 000b and creates an FS of 1.25V.

LLOS[2:0] % of 1.25V FS Voltage

000b 100.00 1.250

001b 80.02 1.0003

010b 66.69 0.8336

011b 50.10 0.6263

100b 40.05 0.5006

101b 33.38 0.4173

110b 26.62 0.3328

111b 25.04 0.3130

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Table 02h, Register B9h: COMP RANGING

FACTORY DEFAULT 00h

READ ACCESS PW2

WRITE ACCESS PW2

MEMORY TYPE Nonvolatile (SEE)

B9h RESERVED BIAS2 BIAS1 BIAS0 RESERVED APC2 APC1 APC0

BIT 7 BIT 0

The upper nibble of this byte controls the full-scale range of the quick-trip monitoring for BIAS. The lower nibble of

this byte controls the full-scale range for the quick-trip monitoring of the APC reference as well as the closed-loop

monitoring of APC.

BIT 7 RESERVED (Default = 0)

BITS 6:4

BIAS[2:0]: BIAS Full-Scale Ranging. 3-bit value to select the FS comparison voltage for BIAS found

on MON1. Default is 000b and creates an FS of 1.25V.

BIAS[2:0] % of 1.25V FS Voltage

000b 100.00 1.250

001b 80.04 1.0005

010b 66.73 0.8341

011b 50.10 0.6263

100b 40.12 0.5015

101b 33.46 0.4183

110b 28.70 0.3588

111b 25.13 0.3141

BIT 3 RESERVED (Default = 0)

BITS 2:0

APC[2:0]: APC Full-Scale Ranging. 3-bit value to select the FS comparison voltage for MON2 with

the APC. Default is 000b and creates an FS of 2.5V.

APC[2:0] % of 2.50V FS Voltage

000b 100.00 2.500

001b 80.04 2.0010

010b 66.73 1.6683

011b 50.10 1.2525

100b 40.12 1.0030

101b 33.46 0.8365

110b 28.70 0.7175

111b 25.13 0.6283

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68 ______________________________________________________________________________________

Table 02h, Register BAh: RESERVED

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

This register is reserved.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

BBh 28 2

7 2

6 2

5 2

4 2

3 2

2 2

BIT 7 BIT 0

The initial step value used at power-on or after a TXD pulse to control the BIAS register. At startup, this value plus

20 = 1 is continuously added to the BIAS register value until the APC feedback (MON2) is greater than its threshold.

At that time, a binary search is used to complete the startup of the APC closed loop. If the resulting math operation is

greater than IBIASMAX (Table 02h, Register EEh), the result is not loaded into the BIAS register, but the binary

search is begun to complete the initial search for APC. During startup, the BIAS register steps causing a higher bias

value than IBIASMAX do not create the BIAS MAX alarm. The BIAS MAX alarm detection is enabled at the end of the

binary search.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

BCh 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Fast-comparison DAC threshold adjust for high TXP. This value is added to the APC DAC value recalled from

Table 06h. If the sum is greater than 0xFF, 0xFF is used. Comparisons greater than VHTXP, compared against

VMON2, create a TXP HI alarm. The same ranging applied to the APC DAC should be used here.

HTXP

=Full Scale

255

HTXP +APC DAC

()

Table 02h, Register BBh: ISTEP

Table 02h, Register BCh: HTXP

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Table 02h, Register BDh: LTXP

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

BDh 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Fast-comparison DAC threshold adjust for low TXP. This value is subtracted from the APC DAC value recalled

from Table 06h. If the difference is less than 0x00, 0x00 is used. Comparisons less than VLTXP, compared

against VMON2, create a TXP LO alarm. The same ranging applied to the APC DAC should be used here.

LTXP

=Full Scale

255

APC DAC LTXP

()

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

BEh 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Fast-comparison DAC threshold adjust for high LOS. The combination of HLOS and LLOS creates a hysteresis

comparator. As RSSI falls below the LLOS threshold, the LOS LO alarm bit is set to 1. The LOS alarm remains set

until the RSSI input is found above the HLOS threshold setting, which clears the LOS LO alarm bit and sets the

LOS HI alarm bit. At power-on, both LOS LO and LOS HI alarm bits are 0 and the hysteresis comparator uses the

LLOS threshold setting.

VHLOS =Full Scale

255

HLOS

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

BFh 2726 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Fast-comparison DAC threshold adjust for low LOS. See HLOS (Table 02h, Register BEh) for functional description.

LLOS

=Full Scale

255

LLOS

Table 02h, Register BEh: HLOS

Table 02h, Register BFh: LLOS

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70 ______________________________________________________________________________________

Table 02h, Register C0h: PW_ENA

FACTORY DEFAULT 10h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

C0h RWTBL78 RWTBL1C RWTBL2 RWTBL1A RWTBL1B WLOWER WAUXA WAUXB

BIT 7 BIT 0

BIT 7

RWTBL78: Tables 07h–08h

0 = (Default) Read and write access for PW2 only.

1 = Read and write access for both PW1 and PW2.

BIT 6

RWTBL1C: Table 01h or 05h bytes F8h–FFh. Table address is dependent on MASK bit (Table 02h,

0 = (Default) Read and write access for PW2 only.

1 = Read and write access for both PW1 and PW2.

BIT 5

RWTBL2: Tables 02h, except for PW1 value locations (Table 02h, Registers B0h–B3h).

0 = (Default) Read and write access for PW2 only.

1 = Read and write access for both PW1 and PW2.

BIT 4

RWTBL1A: Read and Write Table 01h, Registers 80h–BFh

0 = Read and write access for PW2 only.

1 = (Default) Read and write access for both PW1 and PW2.

BIT 3

RWTBL1B: Read and Write Table 01h, Registers C0h–F7h

0 = (Default) Read and write access for PW2 only.

1 = Read and write access for both PW1 and PW2.

BIT 2

WLOWER: Write Lower Memory Bytes 00h–5Fh in main memory. All users can read this area.

0 = (Default) Write access for PW2 only.

1 = Write access for both PW1 and PW2.

BIT 1

WAUXA: Write Auxiliary Memory, Registers 00h–7Fh. All users can read this area.

0 = (Default) Write access for PW2 only.

1 = Write access for both PW1 and PW2.

BIT 0

WAUXB: Write Auxiliary Memory, Registers 80h–FFh. All users can read this area.

0 = (Default) Write access for PW2 only.

1 = Write access for both PW1 and PW2.

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Table 02h, Register C1h: PW_ENB

FACTORY DEFAULT 03h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

C1h RWTBL46 RTBL1C RTBL2 RTBL1A RTBL1B WPW1 WAUXAU WAUXBU

BIT 7 BIT 0

BIT 7

RWTBL46: Read and Write Tables 04h, 06h

0 = (Default) Read and write access for PW2 only.

1 = Read and write access for both PW1 and PW2.

BIT 6

RTBL1C: Read Table 01h or Table 05h, Registers F8h–FFh. Table address is dependent on MASK

bit (Table 02h, Register 89h).

0 = (Default) Read access for PW2 only.

1 = Read access for PW1 and PW2.

BIT 5

RTBL2: Read Table 02h except for PW1 value locations (Table 02h, Registers B0h–B3h)

0 = (Default) Read access for PW2 only.

1 = Read access for PW1 and PW2.

BIT 4

RTBL1A: Read Table 01h, Registers 80h–BFh

0 = (Default) Read access for PW2 only.

1 = Read access for PW1 and PW2.

BIT 3

RTBL1B: Read Table 01h, Registers C0h–F7h

0 = (Default) Read access for PW2 only.

1 = Read access for PW1 and PW2.

BIT 2

WPW1: Write Register PW1 (Table 02h, Registers B0h–B3h). For security purposes these registers

are not readable.

0 = (Default) Write access for PW2 only.

1 = Write access for PW1 and PW2.

BIT 1

WAUXAU: Write Auxiliary Memory, Registers 00h–7Fh. All users can read this area.

0 = Write access for PW2 only.

1 = (Default) Write access for user, PW1 and PW2.

BIT 0

WAUXBU: Write Auxiliary Memory, Registers 80h–FFh

0 = Read and write access for PW2 only.

1 = (Default) Read and write access for user, PW1 and PW2.

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SFP+ Controller with Digital LDD Interface

72 ______________________________________________________________________________________

Table 02h, Register C2h: MODTI

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

C2h 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

The modulation temperature index defines the TempCo boundary for the MODULATION LUT. The MODTC bit

(Table 02h, Register C6h) defines the polarity of the TempCo.

MODTI =Temp _ Value +40°C

2°C

+80h

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

C3h 2726 2

52423222120

BIT 7 BIT 0

DAC1 temperature index (DAC1TI) defines the TempCo boundary for the DAC1 LUT. The DAC1TC bit (Table 02h,

used during the LUT recall, not the value in the TINDEX register (Table 02h, Register 81h).

DAC1TI =Temp _ Value +40°C

4°C

+80h

Table 02h, Register C3h: DAC1TI

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Table 02h, Register C4h: DAC2TI

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

C4h 2726 2

52423222120

BIT 7 BIT 0

DAC2 temperature index defines the TempCo boundary for the DAC2 LUT. The DAC2TC bit (Table 02h, Register

C6h) defines the polarity of the TempCo. This value is compared with the adjusted memory address used during

the LUT recall, not the value in the TINDEX register (Table 02h, Register 81h).

DAC2TI =Temp _ Value +40°C

4°C

+80h

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

This register is reserved.

Table 02h, Register C5h: RESERVED

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SFP+ Controller with Digital LDD Interface

74 ______________________________________________________________________________________

Table 02h, Register C6h: LUTTC

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

C6h MODTC DAC1TC DAC2TC RESERVED RESERVED RESERVED RESERVED RESERVED

BIT 7 BIT 0

BIT 7

MODTC: Modulation TempCo

0 = Negative TempCo. For a TINDEX below the MODTI value, the 8-bit recalled value from the

MODULATION LUT is stored in the upper 8 bits of the MODULATION register. For a TINDEX greater

than or equal to MODTI, the recalled value is stored in the lower 8 bits of the MODULATION register.

1 = Positive TempCo. For a TINDEX (Table 02h, Register 81h) below the MODTI value (Table 02h,

Modulation register. For a TINDEX greater than or equal to MODTI, the recalled value is stored in the

upper 8 bits of the Modulation register.

BIT 6

DAC1TC: DAC1 TempCo

0 = Negative TempCo. For a TINDEX below the DAC1TI value, the 8-bit recalled value from the DAC1

LUT is stored in the upper 8 bits of the DAC1 DAC’s register. For a TINDEX greater than or equal to

DAC1TI, the recalled value is stored in the lower 8 bits of the DAC1 DAC’s register.

1 = Positive TempCo. For a TINDEX (Table 02h, Register 81h) below the DAC1TI value (Table 02h,

DAC’s register. For a TINDEX greater than or equal to DAC1TI, the recalled value is stored in the

upper 8 bits of the DAC1 DAC’s register.

BIT 5

DAC2TC: DAC2 TempCo

0 = Negative TempCo. For a TINDEX below the DAC2TI value, the 8-bit recalled value from the DAC2

LUT is stored in the upper 8 bits of the DAC2 DAC’s register. For a TINDEX greater than or equal to

DAC2TI, the recalled value is stored in the lower 8 bits of the DAC2 DAC’s register.

1 = Positive TempCo. For a TINDEX (Table 02h, Register 81h) below the DAC2TI value (Table 02h,

DAC’s register. For a TINDEX greater than or equal to DAC2TI, the recalled value is stored in the

upper 8 bits of the DAC2 DAC’s register.

BITS 4:0 RESERVED

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SFP+ Controller with Digital LDD Interface

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Table 02h, Register C7h: TBLSELPON

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

C7h 2726 2

52423222120

BIT 7 BIT 0

Chooses the initial value for the table-select byte (Lower Memory, Register 7Fh) at power-on.

FACTORY DEFAULT 0000h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS (PW2 and BIAS EN = 0) or (PW1 and RWTBL246 and BIAS EN = 0)

MEMORY TYPE Volatile

C8h 0 0 0 0 0 0 0 28

C9h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

When BIAS EN (Table 02h, Register 80h) is written to 0, writes to these bytes control the BIAS register, which then

updates the MAX3798/MAX3799 SET_IBIAS register.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS (PW2 and BIAS EN = 0) or (PW1 and RWTBL246 and BIAS EN = 0)

MEMORY TYPE Volatile

CAh RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED MAN_CLK

BIT 7 BIT 0

When BIAS EN (Table 02h, Register 80h) is written to 0, MAN_CLK controls the updates of the MAN BIAS value to

the BIAS register. This new value is sent through the 3-wire interface. The values of MAN BIAS must be written with

a separate write command. Setting MAN_CLK to a 1 clocks the MAN BIAS value to the BIAS register, which then

updates the MAX3798/MAX3799 SET_IBIAS register.

1) Write the MAN BIAS value with a write command.

2) Set the MAN_CLK bit to a 1 with a separate write command.

3) Clear the MAN_CLK bit to a 0 with a separate write command.

Table 02h, Register C8h–C9h: MAN BIAS

Table 02h, Register CAh: MAN_CNTL

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SFP+ Controller with Digital LDD Interface

76 ______________________________________________________________________________________

Table 02h, Register CBh–CCh: BIAS REGISTER

FACTORY DEFAULT 0000h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS N/A

MEMORY TYPE Volatile

CBh RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 28

CCh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

The digital value used for BIAS and resolved from the APC. This register is updated after each decision of the

APC loop.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS (PW2 and APC EN = 0) or (PW1 and RWTBL246 and APC EN = 0)

MEMORY TYPE Volatile

CDh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

The digital value used for APC reference and recalled from Table 06h at the adjusted memory address found in

TINDEX. This register is updated at the end of the temperature conversion.

FACTORY DEFAULT 74h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS N/A

MEMORY TYPE ROM

CEh 0 1 1 1 0 1 0 0

BIT 7 BIT 0

Hardwired connections to show the device ID.

Table 02h, Register CDh: APC DAC

Table 02h, Register CEh: DEVICE ID

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Table 02h, Register CFh: DEVICE VER

FACTORY DEFAULT DEVICE VERSION

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS N/A

MEMORY TYPE ROM

CFh DEVICE VERSION

BIT 7 BIT 0

Hardwired connections to show the device version.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

D0h-D7h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

High-Bias Alarm Threshold (HBATH) is a digital clamp used to ensure that the DAC setting for BIAS currents

does not exceed a set value. The table below shows the range of temperature for each byte’s location. The

table shows a rising temperature; for a falling temperature there is 1°C of hysteresis.

D0h Less than or equal to -8°C

D1h Greater than -8°C up to +8°C

D2h Greater than +8°C up to +24°C

D3h Greater than +24°C up to +40°C

D4h Greater than +40°C up to +56°C

D5h Greater than +56°C up to +72°C

D6h Greater than +72°C up to +88°C

D7h Greater than +88°C

Table 02h, Register D0h–D7h: HBATH

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SFP+ Controller with Digital LDD Interface

78 ______________________________________________________________________________________

Table 02h, Register E8h: RXCTRL1

FACTORY DEFAULT 00h

READ ACCESS N/A

WRITE ACCESS N/A

MEMORY TYPE None

These registers do not exist.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

E8h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

E9h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface.

Table 02h, Register D8h–E7h: EMPTY

Table 02h, Register E9h: RXCTRL2

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SFP+ Controller with Digital LDD Interface

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Table 02h, Register EAh: SETCML

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

EAh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

EBh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

ECh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface.

Table 02h, Register EBh: SETLOS

Table 02h, Register ECh: TXCTRL

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SFP+ Controller with Digital LDD Interface

80 ______________________________________________________________________________________

Table 02h, Register EDh: IMODMAX

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

EDh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

EEh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface. In addition, this value defines the maximum DAC value allowed for the

upper 8 bits of BIAS output during APC closed-loop operations. During the intial step and binary search, this

value does not cause an alarm but still clamps the BIAS register value. After the startup seqence (or normal

APC operations), if the APC loop tries to create a BIAS value greater than this setting, it is clamped and creates

a MAX BIAS alarm.

Table 02h, Register EEh: IBIASMAX

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SFP+ Controller with Digital LDD Interface

______________________________________________________________________________________ 81

Table 02h, Register EFh: SETPWCTRL

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

EFh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

F0h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. After either VCC exceeds POA (after a POR event), the MAX3798/MAX3799 TX_POR

bit is set high (visible in 3W TXSTAT1, Bit 7) or on a rising edge of TXD, this value is written to the MAX3798/

MAX3799 through the 3-wire interface.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (SEE)

These registers are reserved.

Table 02h, Register F0h: SETTXDE

Table 02h, Register F1h–F7h: RESERVED

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SFP+ Controller with Digital LDD Interface

82 ______________________________________________________________________________________

Table 02h, Register F8h: 3WCTRL

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Volatile

F8h RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 3WRW 3WDIS

BIT 7 BIT 0

BITS 7:2 RESERVED

BIT 1

3WRW: Initiates a 3-wire write or read operation. The write command uses the memory address

found in the 3-wire ADDRESS register (Table 02h, Register F9h) and the data from the 3-wire WRITE

The read command uses the memory address found in the 3-wire ADDRESS register (Table 02h,

bit clears itself at the completion of the read operation.

0 = (Default) Reads back as 0 when the write or read operation is completed.

1 = Initiates a 3-wire write or read operation.

BIT 0

3WDIS: Disables all automatic communication across the 3-wire interface. This includes all

updates from the LUTs, APC loop, and status registers. The only 3-wire communication is with the

manual mode of operation.

0 = (Default) Automatic communication is enabled.

1 = Disables automatic communication.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Volatile

F9h 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

This byte is used during manual 3-wire communication. When a manual read or write is initiated, this register

contains the address for the operation.

Table 02h, Register F9h: ADDRESS

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SFP+ Controller with Digital LDD Interface

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Table 02h, Register FAh: WRITE

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Volatile

FAh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

This byte is used during manual 3-wire communication. When a manual write is initiated, this register contains

the data for the operation.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS N/A

MEMORY TYPE Volatile

FBh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

This byte is used during maunual 3-wire communication. When a manual read is initiated, the return data is

stored in this register.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS N/A

MEMORY TYPE Volatile

FCh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. This value is read from the MAX3798/MAX3799 with the 3-wire interface every tRR

(see the MAX3798/MAX3799 electrical characteristics).

Table 02h, Register FBh: READ

Table 02h, Register FCh: TXSTAT1

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84 ______________________________________________________________________________________

Table 02h, Register FDh: TXSTAT2

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS N/A

MEMORY TYPE Volatile

FDh 27 2

6 2

5 2

4 2

322 2

120

BIT 7 BIT 0

MAX3798/MAX3799 register. This value is read from the MAX3798/MAX3799 with the 3-wire interface every tRR

(see the MAX3798/MAX3799 electrical characteristics).

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Volatile

These registers are reserved.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (EE)

80h–C7h 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

The digital value for the modulation DAC output.

The MODULATION LUT is a set of registers assigned to hold the temperature profile for the MODULATION

measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2°C increments from -40°C to

+102°C, starting at 80h in Table 04h. Register 80h defines the -40°C to -38°C MOD output, Register 81h defines

the -38°C to -36°C MOD output, and so on. Values recalled from this EEPROM memory table are written into the

MODULATION REGISTER (Table 02h, Register 82h–83h) location that holds the value until the next temperature

conversion. The DS1874 can be placed into a manual mode (MOD EN bit, Table 02h, Register 80h), where the

MODULATION REGISTER is directly controlled for calibration. If the temperature compensation functionality is

not required, then program the entire Table 04h to the desired modulation setting.

Table 02h, Register FEh–FFh: RESERVED

Table 04h Register Description

Table 04h, Register 80h–C7h: MODULATION LUT

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Table 06h Register Descriptions

Table 06h, Register 80h–A3h: APC LUT

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (EE)

80h–A3h 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

The APC LUT is a set of registers assigned to hold the temperature profile for the APC reference DAC. The

values in this table combined with the APC bits in the COMP RANGING register (Table 02h, Register B9h)

determine the set point for the APC loop. The temperature measurement is used to index the LUT (TINDEX, Table

02h, Register 81h) in 4°C increments from -40°C to +100°C, starting at Register 80h in Table 06h. Register 80h

defines the -40°C to -36°C APC reference value, Register 81h defines the -36°C to -32°C APC reference value,

and so on. Values recalled from this EEPROM memory table are written into the APC DAC (Table 02h, Register

CDh) location that holds the value until the next temperature conversion. The DS1874 can be placed into a

manual mode (APC EN bit, Table 02h, Register 80h), where the APC DAC can be directly controlled for

calibration. If TE temperature compensation is not required by the application, program the entire LUT to the

desired APC set point.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)

WRITE ACCESS PW2 or (PW1 and RWTBL246)

MEMORY TYPE Nonvolatile (EE)

These registers are reserved.

Table 06h, Register A4h–A7h: RESERVED

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SFP+ Controller with Digital LDD Interface

86 ______________________________________________________________________________________

Table 07h Register Descriptions

Table 07h, Register 80h–A3h: DAC1 LUT

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL78) and (PW1 and RTBL78)

WRITE ACCESS PW2 or (PW1 and RWTBL78)

MEMORY TYPE Nonvolatile (EE)

80h–A3h 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

The DAC1 LUT is a set of registers assigned to hold the PWM profile for DAC1. The values in this table

determine the set point for DAC1. The temperature measurement is used to index the LUT (TINDEX, Table 02h,

defines the -40°C to -36°C DAC1 value, Register 81h defines -36°C to -32°C DAC1 value, and so on. Values

recalled from this EEPROM memory table are written into the DAC1 VALUE (Table 02h, Registers 84h–85h)

location, which holds the value until the next temperature conversion. The part can be placed into a manual

mode (DAC1 EN bit, Table 02h, Register 80h), where DAC1 can be directly controlled for calibration. If

temperature compensation is not required by the application, program the entire LUT to the desired DAC1 set

point.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)

WRITE ACCESS PW2 or (PW1 and RWTBL78)

MEMORY TYPE Nonvolatile (EE)

These registers are reserved.

Table 07h, Register A4h–A7h: RESERVED

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______________________________________________________________________________________ 87

Table 08h Register Descriptions

Table 08h, Register 80h–A3h: DAC2 LUT

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)

WRITE ACCESS PW2 or (PW1 and RWTBL78)

MEMORY TYPE Nonvolatile (EE)

80h–A3h 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

The DAC2 LUT is set of registers assigned to hold the PWM profile for DAC2. The values in this table determine

the set point for DAC2. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register

81h) in 4°C increments from -40°C to +100°C, starting at Register 80h in Table 08h. Register 80h defines the

-40°C to -36°C DAC2 value, Register 81h defines -36°C to -32°C DAC2 value, and so on. Values recalled from

this EEPROM memory table are written into the DAC2 VALUE (Table 02h, Registers 86h–87h) location that holds

the value until the next temperature conversion. The DS1874 can be placed into a manual mode (DAC2 EN bit,

Table 02h, Register 80h), where DAC2 can be directly controlled for calibration. If temperature compensation is

not required by the application, program the entire LUT to the desired DAC2 set point.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and RWTBL78) or (PW1 and RTBL78)

WRITE ACCESS PW2 or (PW1 and RWTBL78)

MEMORY TYPE Nonvolatile (EE)

These registers are reserved.

FACTORY DEFAULT 00h

READ ACCESS PW2 or (PW1 and WAUXA) or (PW1 and WAUXAU)

WRITE ACCESS PW2 or (PW1 and WAUXA)

MEMORY TYPE Nonvolatile (EE)

00h–FFh 27 2

6 2

5 2

4 2

3 2

2 2

1 2

BIT 7 BIT 0

Accessible with the slave address A0h.

Table 08h, Register A4h–A7h: RESERVED

Auxiliary Memory A0h Register Descriptions

Auxiliary Memory A0h, Register 00h–FFh: EEPROM

DS1874

SFP+ Controller with Digital LDD Interface

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Applications Information

Power-Supply Decoupling

To achieve best results, it is recommended that the power

supply is decoupled with a 0.01µF or a 0.1µF capacitor.

Use high-quality, ceramic, surface-mount capacitors,

and mount the capacitors as close as possible to the

VCC and GND pins to minimize lead inductance.

SDA and SCL Pullup Resistors

SDA is an open-collector output on the DS1874 that

requires a pullup resistor to realize high logic levels. A

master using either an open-collector output with a

pullup resistor or a push-pull output driver can be uti-

lized for SCL. Pullup resistor values should be chosen

to ensure that the rise and fall times listed in the

C AC

Electrical Characteristics

table are within specification.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

28 TQFN-EP T2855+6 21-0140

Package Information

For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.

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