CP82C88 MD82C88-7 MD82C88-B - Intersil Corporation

4-333

March 1997

82C88

CMOS Bus Controller

Features

• Compatible with Bipolar 8288

• Performance Compatible with:

- 80C86/80C88. . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)

- 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8MHz)

- 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)

- 8089

• Provides Advanced Commands for Multi-Master

Busses

• Three-State Command Outputs

• Bipolar Drive Capability

• Scaled SAJI IV CMOS Process

• Single 5V Power Supply

• Low Power Operation

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max)

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max)

• Operating Temperature Ranges

- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC

- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC

- M82C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC

Description

The Intersil 82C88 is a high performance CMOS Bus Con-

troller manufactured using a self-aligned silicon gate CMOS

process (Scaled SAJI IV). The 82C88 provides the control

and command timing signals for 80C86, 80C88, 8086, 8088,

8089, 80186, and 80188 based systems. The high output

drive capability of the 82C88 eliminates the need for addi-

tional bus drivers.

Static CMOS circuit design insures low operating po w er. The

Intersil advanced SAJI process results in perfor mance equal

to or greater than e xisting equiv alent products at a signiﬁcant

power savings.

Pinouts

20 LEAD PDIP, CERDIP

TOP VIEW 20 LEAD PLCC, CLCC

TOP VIEW

Ordering Information

PART NUMBER PACKAGE TEMPERATURE

RANGE PKG.

NO.

CP82C88 20 Ld PDIP 0oC to +70oC E20.3

CP82C88-10 0oC to +70oC E20.3

IP82C88 -40oC to +85oC E20.3

CS82C88 20 Ld

PLCC 0oC to +70oC N20.35

IS82C88 -40oC to +85oC N20.35

CD82C88 20 Ld

CERDIP 0oC to +70oC F20.3

ID82C88 -40oC to +85oC F20.3

MD82C88/B -55oC to +125oC F20.3

8406901RA SMD# F20.3

MR82C88/B 20 Pad

CLCC -55oC to +125oC J20.A

84069012A SMD# J20.A

IOB

CLK

ALE

GND

DT/ R

AEN

MRDC

AMWC

MWTC

VCC

MCE/PDEN

DEN

CEN

IORC

AIOWC

IOWC

INTA

S2 4

910111213

3212019

ALE

DT/ R

AEN

MRDC

AMWC

GND

IORC

AIOWC

IOWC

MWTC

VCC

IOB

CLK

DEN

CEN

MCE/PDEN

INTA

File Number 2979.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

4-334

Functional Diagram

Pin Description

SYMBOL NUMBER TYPE DESCRIPTION

VCC 20 VCC: The +5V po wer supply pin. A 0.1µF capacitor betw een pins 10 and 20 is recommended f or decoupling.

GND 10 GROUND.

S0, S1, S2 19, 3, 18 I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors.

The 82C88 decodes these inputs to generate command and control signals at the appropriate time.

When Status pins are not in use (passive), command outputs are held HIGH (See Table1).

CLK 2 I CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock

generator and serves to establish when command/control signals are generated.

ALE 5 O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This sig-

nal is active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use

with transparent D type latches, such as the 82C82 and 82C83H.

DEN 16 O DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus.

This signal is active HIGH.

DT/R 4 O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers.

A HIGH on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from

I/O or memory).

AEN 6 I ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns

(250ns maximum) after it becomes active (LOW). AEN going inactive immediately three-states the com-

mand output drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode

(IOB tied HIGH).

CEN 15 I COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN con-

trol outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.

IOB 1 I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus

mode. When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System

Bus sections).

VCC GND

COMMAND

SIGNALS

MULTIBUSTM

CONTROL

INPUT

IOB

CEN

CLK

AEN CONTROL

SIGNAL

GENERATOR

DEN

ALE

DT/R

MCE/PDEN

COMMAND

SIGNAL

GENERATOR

AIOWC

IOWC

AMWC

MWTC

MRDC

IORC

INTA

ADDRESS LATCH,

DATA TRANSCEIVER,

AND INTERRUPT

CONTROL SIGNALS

CONTROL

LOGIC

STATUS

DECODER

82C88

Intel™ is a Registered Trademark of Intel Corporation

4-335

Functional Description

The command logic decodes the three 80C86, 8086, 80C88,

8088, 80186, 80188 or 8089 status lines (S0, S1, S2) to

determine what command is to be issued (see Table 1).

I/O Bus Mode

The 82C88 is in the I/O Bus mode if the IOB pin is strapped

HIGH. In the I/O Bus mode, all I/O command lines IORC,

IOWC, AIOWC, INTA) are always enabled (i.e., not depen-

dent on AEN). When an I/O command is initiated by the pro-

cessor, the 82C88 immediately activates the command lines

using PDEN and DT/R to control the I/O bus transceiv er. The

I/O command lines should not be used to control the system

bus in this conﬁguration because no arbitration is present.

This mode allows one 82C88 Bus Controller to handle two

external busses. No waiting is involved when the CPU wants

to gain access to the I/O bus. Normal memory access

requires a “Bus Ready” signal (AEN LOW) before it will pro-

ceed. It is advantageous to use the IOB mode if I/O or

peripherals dedicated to one processor exist in a multi-pro-

cessor system.

System Bus Mode

The 82C88 is in the System Bus mode if the IOB pin is

strapped LOW. In this mode, no command is issued until a

speciﬁed time period after the AEN line is activated (LOW).

This mode assumes bus arbitration logic will inform the bus

controller (on the AEN line) when the bus is free for use.

Both memory and I/O commands wait for bus arbitration.

This mode is used when only one bus exists. Here, both I/O

and memory are shared by more than one processor.

Command Outputs

The advanced write commands are made a v ailab le to initiate

write procedures ear ly in the machine cycle. This signal can

be used to prevent the processor from entering an unneces-

sary wait state.

AIOWC 12 O ADVANCED I/O WRITE COMMAND: The AIO WC issues an I/O Write Command earlier in the machine

cycle to give I/O devices an early indication of a write instruction. Its timing is the same as a read com-

mand signal. AIOWC is active LOW.

IOWC 11 O I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The

signal is active LOW.

IORC 13 O I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This

signal is active LOW.

AMWC 8 O ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the

machine cycle to give memory devices an early indication of a write instruction. Its timing is the same as

a read command signal. AMWC is active LOW.

MWTC 9 O MEMORY WRITE COMMAND: This command line instructs the memory to record the data present on

the data bus. This signal is active LOW.

MRDC 7 O MEMORY READ COMMAND: This command line instructs the memory to drive its data onto the data

bus. MRDC is active LOW.

INTA 14 O INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its interrupt has been

acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW.

MCE/PDEN 17 O This is a dual function pin. MCE (IOB IS TIED LOW) Master Cascade Enable occurs during an interrupt

sequence and serves to read a Cascade Address from a master 82C59A Priority Interrupt Controller onto

the data bus. The MCE signal is active HIGH. PDEN (IOB IS TIED HIGH): Peripheral Data Enable enables

the data bus transceiver for the I/O bus that DEN performs for the system bus. PDEN is active LOW.

Pin Description

(Continued)

SYMBOL NUMBER TYPE DESCRIPTION

TABLE 1. COMMAND DECODE DEFINITION

S2 S1 S0 PROCESSOR STATE 82C88

COMMAND

0 0 0 Interrupt Acknowledge INTA

0 0 1 Read I/O Port IORC

0 1 0 Write I/O Port IOWC, AIOWC

0 1 1 Halt None

1 0 0 Code Access MRDC

1 0 1 Read Memory MRDC

1 1 0 Write Memory MWTC, AMWC

1 1 1 Passive None

82C88

4-336

INTA (Interr upt Acknowledge) acts as an I/O read during an

interrupt cycle. Its purpose is to inf orm an interrupting device

that its interrupt is being acknowledged and that it should

place vectoring information onto the data bus.

The command outputs are:

MRDC - Memory Read Command

MWTC - Memory Write Command

IORC - I/O Read Command

IOWC - I/O Write Command

AMWC - Advanced Memory Write Command

AIOWC - Advanced I/O Write Command

INTA - Interrupt Acknowledge

Control Outputs

The control outputs of the 82C88 are Data Enable (DEN),

Data Transmit/Receive (DT/R) and Master Cascade Enable/

Peripheral Data Enable (MCE/PDEN). The DEN signal

determines when the external bus should be enabled onto

the local bus and the DT/R determines the direction of data

transfer. These two signals usually go to the chip select and

direction pins of a transceiver.

The MCE/PDEN pin changes function with the two modes of

the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),

the PDEN signal serves as a dedicated data enable signal

for the I/O or Peripheral System bus.

Interrupt Acknowledge and MCE

The MCE signal is used during an interrupt acknowledge

cycle if the 82C88 is in the System Bus mode (IOB LOW).

During any interrupt sequence, there are two interrupt

acknowledge cycles that occur back to back. During the ﬁrst

interrupt cycle no data or address transfers take place. Logic

should be provided to mask off MCE during this cycle. Just

bef ore the second cycle begins the MCE signal gates a mas-

ter Prior ity Interr upt Controller’s (PIC) cascade address onto

the processor’s local bus where ALE (Address Latch Enab le)

strobes it into the address latches. On the leading edge of

the second interrupt cycle, the addressed slav e PIC gates an

interrupt vector onto the system data bus where it is read by

the processor.

If the system contains only one PIC, the MCE signal is not

used. In this case, the second Interrupt Acknowledge signal

gates the interrupt vector onto the processor bus.

Address Latch Enable and Halt

Address Latch Enable (ALE) occurs during each machine

cycle and serves to strobe the current address into the

82C82/82C83H address latches. ALE also serves to strobe

the status (S0, S1, S2) into a latch for halt state decoding.

Command Enable

The Command Enable (CEN) input acts as a command

qualiﬁer for the 82C88. If the CEN pin is high, the 82C88

functions normally. If the CEN pin is pulled LOW, all com-

mand lines are held in their inactive state (not three-state).

This feature can be used to implement memory partitioning

and to eliminate address conﬂicts between system bus

devices and resident bus devices.

82C88

4-337

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range

C82C88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC

I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC

M82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC

Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)

CERDIP Package . . . . . . . . . . . . . . . . 75 18

CLCC Package . . . . . . . . . . . . . . . . . . 85 22

PDIP Package . . . . . . . . . . . . . . . . . . . 75 N/A

PLCC Package . . . . . . . . . . . . . . . . . . 75 N/A

Storage Temperature Range. . . . . . . . . . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC

Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC

(PLCC - Lead Tips Only)

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause per manent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

DC Electrical Speciﬁcations VCC = 5.0V ±10%;

TA = 0oC to +70oC (C82C88);

TA = -40oC to +85oC (I82C88);

TA = -55oC to +125oC (M82C88)

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

VIH Logical One Input Voltage 2.0

2.2 -

-V

VC82C88, I82C88

M82C88

VIL Logical Zero Input Voltage - 0.8 V

VIHC CLK Logical One Input Voltage VCC -0.8 - V

VILC CLK Logical Zero Input Voltage - 0.8 V

VOH Output High Voltage

Command Outputs 3.0

VCC -0.4 -V

VIOH = -8.0mA

IOH = -2.5mA

Output High Voltage

Control Outputs 3.0

VCC -0.4 -V

VIOH = -4.0mA

IOH = -2.5mA

VOL Output Low Voltage

Command Outputs - 0.5 V IOL= +12.0mA

Output Low Voltage

Control Outputs - 0.4 V IOL = +8.0mA

IIInput Leakage Current -1.0 1.0 µAV

IN = GND or VCC, except S0, S1, S2,

DIP Pins 1-2, 6, 15

IBHH Input Leakage Current-Status Bus -50 -300 µAV

IN = 2.0V, S0, S1, S2 (See Note 1)

IO Output Leakage Current -10.0 10.0 µAV

O = GND or VCC, IOB = GND, AEN = VCC,

DIP Pins 7-9, 11-14

ICCSB Standby Power Supply - 10 µAV

CC = 5.5V, VIN = VCC or GND, Outputs Open

ICCOP Operating Power Supply Current - 1 mA/MHz VCC = 5.5V, Outputs Open (See Note 2)

NOTES:

1. IBHH should be measured after raising the VIN on S0, S1, S2 to VCC and then lowering to valid input high level of 2.0V.

2. ICCOP = 1mA/MHz of CLK cycle time (TCLCL)

Capacitance TA = +25oC

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

CIN Input Capacitance 10 pF FREQ = 1MHz, all measurements are

referenced to device GND

COUT Output Capacitance 17 pF

82C88

4-338

AC Testing Input, Output Waveform

A.C. Testing: All input signals (other than CLK) must switch

between VIL -0.4V and VIH +0.4. CLK must switch between 0.4V

and VCC -0.4V. Input rise and fall times are driven at 1ns/V.

A.C. Test Circuit

AC Electrical Speciﬁcations VCC = 5.0V ±10%;

TA = 0oC to +70oC (C82C88);

TA = -40oC to +85oC (I82C88);

TA = -55oC to +125oC (M82C88)

SYMBOL PARAMETER

8MHz 10MHz 12MHz

UNITS TEST

CONDITIONSMIN MAX MIN MAX MIN MAX

TIMING REQUIREMENTS

(1) TCLCL CLK Cycle Period 125 - 100 - 83 - ns

(2) TCLCH CLK Low Time 55 - 50 - 34 - ns

(3) TCHCL CLK High Time 40 - 37 - 34 - ns

(4) TSVCH Status Active Setup Time 35 - 35 - 35 - ns

(5) TCHSV Status Inactive Hold Time 10 - 10 - 5 - ns

(6) TSHCL Status Inactive Setup Time 35 - 35 - 35 - ns

(7) TCLSH Status Active Hold Time 10 - 10 - 5 - ns

TIMING RESPONSES

(8) TCVNV Control Active Delay 5 45 5 45 5 45 ns 1

(9) TCVNX Control Inactive Delay 10 45 10 45 10 35 ns 1

(10) TCLLH ALE Active Delay (from CLK) - 20 - 20 - 20 ns 1

(11) TCLMCH MCE Active Delay (from CLK) - 25 - 23 - 23 ns 1

(12) TSVLH ALE Active Delay (from Status) - 20 - 20 - 20 ns 1

(13) TSVMCH MCE Active Delay (from Status) - 30 - 23 - 23 ns 1

(14) TCHLL ALE Inactive Delay 4 18 4 18 4 18 ns 1

(15) TCLML Command Active Delay 5 35 5 35 5 35 ns 2

(16) TCLMH Command Inactive Delay 5 35 5 35 5 35 ns 2

(17) TCHDTL Direction Control Active Delay - 50 - 50 - 50 ns 1

(18) TCHDTH Direction Control Inactive Delay - 30 - 30 - 30 ns 1

(19) TAELCH Command Enable Time (Note 1) - 40 - 40 - 40 ns 3

(20) TAEHCZ Command Disable Time

(Note 2) -40-40-40ns 4

(21) TAELCV Enable Delay Time 110 250 110 250 110 250 ns 2

(22) TAEVNV AEN to DEN - 25 - 25 - 25 ns 1

(23) TCEVNV CEN to DEN, PDEN - 25 - 25 - 25 ns 1

(24) TCELRH CEN to Command - TCLML

+10 - TCLML - TCLML ns 2

(25) TLHLL ALE High Time TCLCH -

10 - TCLCH -

10 nns 1

NOTES:

1. TAELCH measurement is between 1.5V and 2.5V.

2. TAEHCZ measured at 0.5V change in VOUT.

1.5V 1.5V

VIL -0.4V

INPUT

VIH +0.4V

VOL

OUTPUT

VOH

TABLE 2. TEST CONDITION DEFINITION TABLE

TEST CONDITION V1 R1 C1

1 2.13V 220Ω80pF

2 2.29V 91Ω300pF

3 1.5V 187Ω300pF

4 1.5V 187Ω50pF

TEST

POINT

C1 (SEE NOTE)

OUTPUT FROM

DEVICE

UNDER TEST

NOTE:

INCLUDES STRAY AND JIG CAPACITANCE

82C88

4-339

Timing Waveforms

(Note 3)

NOTES:

1. Address/Data Bus is shown only for reference purposes.

2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.

3. All timing measurements are made at 1.5V unless otherwise specified.

FIGURE 1.

STATE

CLK

S2, S1, S0

ADDRESS/DATA

ALE

MRDC, IORC, INTA,

AMWC, AIOWC

MWTC, IOWC

DEN (READ)

(INTA)

PDEN (READ)

(INTA)

DEN (WRITE)

PDEN (WRITE)

DT/R (READ)

(INTA)

MCE

T4T1T2T3T4

TCLCL

(1) TCLCH

(2)

TCHCL

(3) TCLSH

(7)

TSHCL

(6)

TSVCH

(4)

TCHSV

(5)

TCLLH

(10) TSVLH (12)

TCHLL (14)

TCLML

(15) TCLML

(15)

TCLMH

(16)

TCVNX

(9)

TCVNV

(8)

TCVNV

(8)

TCVNX

(9)

TCHDTH

(18)

TCHDTL

(17) TCHDTH

(18)

TCLMCH

(11) TSVMCH

(13)

TCVNX

(9)

WRITE

DATA VALID

ADDRESS

VALID

82C88

4-340

FIGURE 2. DEN, PDEN QUALIFICATION TIMING

FIGURE 3. ADDRESS ENABLE (AEN) TIMING (THREE-STATE ENABLE/DISABLE)

NOTES:

1. Address/Data Bus is shown only for reference purposes.

2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.

3. All timing measurements are made at 1.5V unless otherwise specified.

Timing Waveforms

(Note 3) (Continued)

TAEVNV (22)

TCEVNV (23)

CEN

DEN

AEN

PDEN

CEN

TAELCV

(21)

1.5V

TAELCH (19) VOH

TCELRH

(24)

TCELRH (24)

TAEHCZ (20)

1.5V

0.5V VOH

OUTPUT

COMMAND

AEN

CEN MUST BE LOW OR INVALID PRIOR TO T2 TO PREVENT THE COMMAND FROM BEING GENERATED.

82C88

4-341

Burn-In Circuits

MD82C88 CERDIP

MR82C88 CLCC

NOTES:

1. VCC = 5.5V ± 0.5V

GND = 0V

2. VIH = 4.5V ± 10%

VIL = -0.2V to +0.4V

3. Component Values:

R1 = 47kΩ, 1/4W, 5%

R2 = 1.5kΩ, 1/4W, 5%

R3 = 10kΩ, 1/4W, 5%

R4 = 1.2kΩ, 1/4W, 5%

C1 = 0.01µF (Min)

F0 = 100kHz ± 10%

F1 = F0/2

F2 = F1/2 . . . F7 = F6/2

1R2

VCC

9101112

3212019

VCC/ 2

R4 R4 R4

VCC/ 2

R1R4 R1 R4

VCC

F0 F7F3 F4

VCC/ 2

VCC

82C88

4-342

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable . However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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P. O. Box 883, Mail Stop 53-204

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Die Characteristics

DIE DIMENSIONS:

103.5 x 116.5 x 19 ± 1mils

METALLIZATION:

Type: Si - Al

Thickness: 11kÅ±2kÅ

GLASSIVATION:

Type: Nitrox

Thickness: 10kÅ

WORST CASE CURRENT DENSITY:

1.9 x 105 A/cm2

Metallization Mask Layout

82C88

S1 CLK IOB VCC S0 S2

MCE/

DEN

CEN

INTA

IORCAIOWCIOWCGNDMWTCAMWC

MRDC

AEN

ALE

DT/R

PDEN

82C88