PCI 9052
32-bit, 33MHz PCI Target I/O Accelerator for 32-bit, 40MHz
Generic and ISA Local Bus Designs
As PCI evolves in today's complex systems, PLX continues to provide market leading
high performance 32-bit PCI solutions. In this tradition, PLX offers the PCI 9052 I/O
Accelerator. The PCI 9052 brings PLX's industry leading experience in the world of PCI
designs to you in a way that is simple and convenient to use. The PCI 9052 is the ideal
choice for implementation of your 32-bit, 33MHz PCI bus target (slave) I/O Accelerator
designs for you 32-bit 40MHz, Industry Standard Architecture (ISA) local bus, or generic
designs.
Add Target Functionality with Ease
The PCI 9052 has the industry's most flexible local bus, which allows for multiple inter-
face options to a wide variety of memory and I/O devices. Combine that with fully tested,
PCI r2.1 compliance, and your design risk is virtually zero. The PCI 9052 has a set of
advanced features to provide high performance and flexibility in order to simplify your
design, such as four programmable GPIOs, local chip select, prefetch read ahead mode,
zero wait state bursting, and on-the-fly big/little endian byte conversion.
Move your ISA Designs Up to Leading PCI Capabilities with Ease
The PCI 9052 accelerates I/O data movement on adapter boards, from ISA’s nominal
bus speed of 8MHz, 5MBytes/second, to high-performance 33MHz, 132Mbytes/second
PCI data transfer. The PCI 9052 enables a simple, rapid, low cost conversion of ISA
adapters to the PCI. The PCI 9052 is a perfect fit for many networking, telecommunica-
tions, imaging, industrial, and storage applications:
■32-bit, 33MHz PCI operation
■32-bit, 40MHz local bus operation
■Glueless ISA interface for low cost adapters
■Serial EEPROM interface for loading configuration
information, to simplify your switch from ISA designs
■Based on the industry-leading architecture of the
PCI 9050, for easy software migration
Connectivity
■
32-bit, 33MHz PCI r2.1 compliant
■
Up to 40MHz local bus operation
■
ISA and Generic 32-bit, 40MHz
local bus designs
■
Glueless ISA interface for
low cost adapters
■
Supports multiplexed and non-
multiplexed 8-, 16-, and 32-bit
generic local buses
■
5V CMOS in 160-pin
PQFP package
Performance
■
Zero wait state burst operation
–PCI unlimited bursts transfers at
up to 132MB/s
■
Direct slave data transfers
–Access 8-, 16-, and 32-bit local
bus devices
■
Deferred reads, read ahead, posted
writes, programmable read
prefetch counter
■
Move from 8MHz, 5MB/s ISA
designs to leading 33MHz,
132MB/s PCI
■
Low power consumption
Control
■
Supports single cycle reads/writes
for 8-, 16-bit memory and
I/O-mapped accesses from
PCI Bus to ISA bus
■
Burst memory-mapped and single
I/O-mapped accesses from the
PCI-to-local bus
■
32-bit, 16-bit, 8-bit data lines
■
Local bus asynchronous
to PCI clock
■
On-the-fly big/little endian
byte conversion
–Redirects current word or byte
lane during 8- or 16-bit local bus
operation
■
Backwards compatibility with the
PCI 9050
■
Five local address spaces
independent from EEPROM
■
Four independently programma-
ble local chip selects
■
Up to four programmable GPIOs
■
Serial EEPROM interface
– Used to switch to ISA
interface mode
FIFOs
PCI Bus
State
Machines
Local Bus
State
Machines
Local Bus
Interface
– Dynamic Bus
Width (8-, 16-,
or 32-bit)
– Endian
Conversion
– Muxed or
non-Muxed
Address/Data
Buses
– ISA Logic
Interface
Control Logic
32-bit, 33MHz PCI Bus
32-bit, 40MHz Local Bus
Direct Slave
PCI Target
(For Direct
Slave Xfers)
Direct Slave Read Local Master
(For Direct
Slave Xfers)
Conguration
Registers
PCI Bus
Interface
EEPROM
Direct Slave Write
PCI Bus
Local Bus
Run-Time
Serial EEPROM
– User-specied
register
initialzation
values
Interrupts
PLX Technology, Inc.
870 Maude Ave.
Sunnyvale, CA 94085 USA
Tel: 1-800-759-3735
Tel: 1-408-774-9060
Fax: 1-408-774-2169
Email: info@plxtech.com
Web Site: www.plxtech.com
©
2001 by PLX Technology, Inc. All rights reserved. PLX and Data Pipe Architecture are trademarks of PLX Technology, Inc. All oth er product names that appear in this material are for identication purposes only and are acknowledged to be
trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and r eliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX
Technology, Inc. reserves the right, without notice, to make changes in product design or specication.
PLX recognizes that software often repre-
sents the largest investment in development.
The PCI 9052 is fully compliant with PLX’s
SDK-LITE that enables quick and easy devel-
opment of high performance local processor
and host PCI software through standard
APIs, PCI debug tools, and sample drivers.
Development Tools Support
To minimize risk and lower your product
development costs, PLX oers Software
Development Kits (SDKs) and Rapid
Development Kits (RDKs) that support the
PCI 9052. These kits enable designers to
quickly bring new designs to production.
The PCI 9052 design support is provided
through RDKs that include a robust PCI
development platform, complete with
OrCAD schematics, documentation, a PCI
9052 chip sample, and software.
9052-SIL-PB-P1-1.0 9/01 750
PCI 9052 Internal Block Diagram
Pr od uc t Or de ri ng I nf or ma ti on
Part Number Description
PCI 9052 32-bit, 33MHz PCI Target I/O Accelerator for Generic and ISA 32-bit,
40MHz Local Bus Designs
32-bit, 33MHz PCI Target I/O Accelerator for Generic and ISA 32-bit,
40MHz Local Bus Designs (Lead-Free)
PCI 9052 G
PCI 9052RDK-LITE PCI 9052 Rapid Development Kit with prototyping area for
Generic & ISA mode Local Bus designs
SDK-LITE Windows Host-Side Software Development Kit for PLX I/O Accelerators
and I/O Processors
