Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 174
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 120A
IDM Pulsed Drain Current 700
PD @TC = 25°C Power Dissipation 200 W
Linear Derating Factor 1.4 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy350 mJ
IAR Avalanche CurrentSee Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche EnergymJ
dv/dt Peak Diode Recovery dv/dt TBD V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
HEXFET® Power MOSFET
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFET utilizes the lastest processing
techniques to achieve extremely low on-resistance per silicon area.
Additional features of this design are a 175°C junction operating
temperature, fast switching speed and improved repetitive avalanche
rating. These benefits combine to make this design an extremely efficient
and reliable device for use in Automotive applications and a wide variety
of other applications.
S
D
G
Absolute Maximum Ratings
VDSS = 20V
RDS(on) = 4.0mΩ
ID = 174A
Description
12/22/04
www.irf.com 1
Benefits
lAdvanced Process Technology
lUltra Low On-Resistance
lDynamic dv/dt Rating
l175°C Operating Temperature
lFast Switching
lRepetitive Avalanche Allowed up to Tjmax
lLead-Free
AUTOMOTIVE MOSFET
Thermal Resistance Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.75 °C/W
RθJA Junction-to-Ambient (PCB mount)––– 40
D2Pak
IRF1302S TO-262
IRF1302L
PD - 95407
IRF1302SPbF
IRF1302LPbF
IRF1302S/LPbF
2www.irf.com
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 20 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.021 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 3.3 4.0 mΩVGS = 10V, ID = 104A
VGS(th) Gate Threshold Voltage 2.0 – –– 4. 0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 59 ––– ––– S VDS = 15V, ID = 104A
––– ––– 20 µA VDS = 20V, VGS = 0V
––– ––– 250 VDS = 16V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– –– – 200 VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -200 nA VGS = -20V
QgTotal Gate Charge –– – 79 120 ID = 104A
Qgs Gate-to-Source Charge ––– 18 27 nC VDS = 16V
Qgd Gate-to-Drain ("Miller") Charge ––– 31 46 VGS = 10V
td(on) Turn-On Delay Time ––– 28 – –– VDD = 11V
trRise Time ––– 13 0 – – – ID = 104A
td(off) Turn-Off Delay Time ––– 47 ––– RG = 4.5Ω
tfFall Time ––– 16 ––– VGS = 10V
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 3600 ––– VGS = 0V
Coss Output Capacitance ––– 2370 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 52 0 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 5710 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 2370 ––– VGS = 0V, VDS = 16V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 3540 ––– VGS = 0V, VDS = 0V to 16V
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
S
D
G
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode) ––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1. 3 V TJ = 25°C, IS = 104A, VGS = 0V
trr Reverse Recovery Time ––– 66 100 ns TJ = 25°C, IF = 104A
Qrr Reverse RecoveryCharge ––– 130 200 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
174
700
A
IRF1302S/LPbF
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Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
-60 -40 -20 020 40 60 80 100 120 140 160 180
0.0
0.5
1.0
1.5
2.0
T , Junction Temperature ( C)
R , Drain-to-Source On Resistance
(Normalized)
J
DS(on)
°
V =
I =
GS
D
10V
174A
4.0 5.0 6.0 7.0
VGS, Gate- to-Sour ce Voltage ( V)
10.00
100.00
1000.00
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 15V
20µs PULSE WIDTH
0.1 110 100
VDS, Dr ain- to-Sour ce Vol tage ( V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
4.5V
20µs PU LSE WID TH
Tj = 25°C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0.1 110 100
VDS, Dr ain- to- Source Voltage (V )
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
4.5V
20µs PU LSE WID TH
Tj = 175° C
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
IRF1302S/LPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
020 40 60 80 100
0
2
5
7
10
12
Q , T o ta l Ga te C h a rge (n C)
V , Gate-to-Source Voltage (V)
G
GS
I =
D104A V = 16V
DS
0.1
1
10
100
1000
0.2 0.7 1.2 1.7 2.2
V ,Source-to-Drain Voltage (V)
I , R ev ers e D r ain C urrent (A)
SD
SD
V = 0 V
GS
T = 175 C
J°
T = 25 C
J°
110 100
VDS, Drain-t o-Sour ce Voltage (V)
100
1000
10000
100000
C, Capacitance(pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = C
gs + Cgd, C
ds SHORTED
Crss
= C
gd
Coss
= Cds + Cgd
1 10 100
V
DS
, Drai n-toS ource Vol t age (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Singl e Pul se
1msec
10msec
OPERATION IN THI S AREA
LIMITED BY RDS(on)
100µsec
IRF1302S/LPbF
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Fig 9. Maximum Drain Current Vs.
Case Temperature
V
DS
9
0%
1
0%
V
GS t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
25 50 75 100 125 150 175
0
44
88
131
175
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
Fig 10a. Switching Time Test Circuit
Fig 10b. Switching Time Waveforms
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Therm al Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRF1302S/LPbF
6www.irf.com
QG
QGS QGD
V
G
Charge
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
25 50 75 100 125 150 175
0
140
280
420
560
700
Starting Tj, Junction Temperature ( C)
E , Single Pulse Avalanche Energy (mJ)
AS
°
ID
TOP
BOTTOM
43A
74A
104A
Fig 14. Threshold Voltage Vs. Temperature
-75 -50 -25 025 50 75 100 125 150 175
TJ , T em perature ( °C )
1.0
2.0
3.0
4.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
IRF1302S/LPbF
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Dut y Cycl e = Single Pul se
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
0.01
25 50 75 100 125 150
Starting TJ , Juncti on Temperature (°C )
10
60
110
160
210
260
310
360
410
EAR , Avalanche Energy (mJ)
TOP Single Pu lse
BOTTOM 1 0 % Duty Cycle
ID = 104A
IRF1302S/LPbF
8www.irf.com
Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
RG
VDD
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T*Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
* Reverse Polarity of D.U.T for P-Channel
VGS
[ ]
[ ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
[ ] ***
Fig 17. For N-channel HEXFET® power MOSFETs
IRF1302S/LPbF
www.irf.com 9
D2Pak Part Marking Information
Note: "P" in assembly line
pos ition indicates "Lead-Free"
F530S
THIS IS AN IRF530S WITH
LOT CODE 8024
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
ASSEMBLY
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
PART NUMBE
R
DATE CODE
YEAR 0 = 2000
WEE K 02
LI NE L
OR
F530S
A = AS SEMBLY S IT E CODE
WEEK 02
P = DESIGNATES LEAD-FREE
PRODUCT (OPTION AL)
RECTIFIER
INTERNATIONAL
LOGO
LOT COD E
ASSEMBLY YEAR 0 = 2000
DA TE C ODE
PART NUMBER
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
IRF1302S/LPbF
10 www.irf.com
TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
ASSEMBLY
LOT CODE
RECTIFIER
INTERNATIONAL
AS SEM BLED ON W W 19, 1997
Note: "P" in ass embly line
pos ition indicates "L ead-F ree"
I N TH E ASSEMBLY LINE "C" LOGO
THIS IS AN IRL3103L
LOT CODE 1789
EXAMPLE:
LINE C
DATE CODE
WEEK 19
YEAR 7 = 1997
PAR T NU MBER
PART N UMBER
LOGO
LOT CODE
ASSEMBLY
INTERNATIONAL
RECTIFIER
PRODUCT (OPTIONAL)
P = DES IGNAT E S LE AD-FREE
A = AS S EMB L Y SIT E CODE
WEEK 19
YEAR 7 = 1997
DATE CODE
OR
IRF1302S/LPbF
www.irf.com 11
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.063mH
RG = 25Ω, IAS = 104A. (See Figure 12).
ISD ≤ 104A, di/dt ≤ 100A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Notes:
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
F
EED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063 )
1.50 (.059 )
4.10 (.161)
3.90 (.153)
TRL
F
EED DIRECTION
10.90 (.429)
10.70 (.421) 16.10 (.634)
15.90 (.626)
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957
)
23.90 (.941
)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27. 40 (1.07 9)
23. 90 (.941 )
60.00 (2.362
)
MIN.
30.40 (1.197)
MAX.
26.40 ( 1 .039)
24.40 ( .961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/