PIC16F193X/LF193X PIC16F193X/LF193X Memory Programming Specification 1.1.2 This document includes the programming specifications for the following devices: * PIC16F1933 * PIC16F1934 * PIC16F1936 * PIC16F1937 * PIC16F1938 * PIC16F1939 LOW-VOLTAGE ICSP PROGRAMMING In Low-Voltage ICSPTM mode, the PIC16F193X and PIC16LF193X devices can be programmed using a single VDD source in the operating range. The MCLR/VPP/RE3 pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. * PIC16LF1933 * PIC16LF1934 * PIC16LF1936 * PIC16LF1937 * PIC16LF1938 * PIC16LF1939 1.1.2.1 1.0 OVERVIEW The LVP bit in Configuration Word 2 enables single-supply (low-voltage) ICSP programming. The LVP bit defaults to a `1' (enabled) from the factory. The LVP bit may only be programmed to `0' by entering the High-Voltage ICSP mode, where MCLR/VPP/RE3 pin is raised to VIHH. Once the LVP bit is programmed to a `0', only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. The PIC16F193X and PIC16LF193X devices can be programmed using either the high-voltage In-Circuit Serial ProgrammingTM (ICSPTM) method or the low-voltage ICSPTM method. 1.1 Hardware Requirements 1.1.1 Single-Supply ICSP Programming HIGH-VOLTAGE ICSP PROGRAMMING Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/VPP/RE3 pin. In High-Voltage ICSPTM mode, the PIC16F193X and PIC16LF193X devices require two programmable power supplies: one for VDD and one for the MCLR/VPP/RE3 pin. 2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and RE3 pin can no longer be used as a general purpose input. 1.2 Pin Utilization Five pins are needed for ICSPTM programming. The pins are listed in Table 1-1. TABLE 1-1: PIN DESCRIPTIONS DURING PROGRAMMING During Programming Pin Name Function Pin Type RB6 ICSPCLK I RB7 ICSPDAT I/O RE3/MCLR/VPP VDD VSS Legend: Note 1: Pin Description Clock Input - Schmitt Trigger Input Data Input/Output - Schmitt Trigger Input (1) Program Mode Select/Programming Power Supply VDD P Power Supply VSS P Ground Program/Verify mode P I = Input, O = Output, P = Power In the PIC16F193X/LF193X, the programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current. (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 1 PIC16F193X/LF193X Table of Contents 1.0 Overview ..................................................................................................................................................................................... 1 1.1 Hardware Requirements ......................................................................................................................................................... 1 1.1.1 High-Voltage ICSP Programming ................................................................................................................................ 1 1.1.2 Low-Voltage ICSP Programming ................................................................................................................................. 1 1.2 Pin Utilization .......................................................................................................................................................................... 1 2.0 Device Pinouts ............................................................................................................................................................................ 3 3.0 Memory Map ............................................................................................................................................................................... 8 3.1 User ID Location ..................................................................................................................................................................... 9 3.2 Device ID ................................................................................................................................................................................ 9 3.3 Configuration Words ............................................................................................................................................................. 10 3.4 Calibration Words ................................................................................................................................................................. 10 4.0 Program/Verify Mode ................................................................................................................................................................ 13 4.1 High Voltage Program/Verify Mode Entry and Exit ............................................................................................................... 13 4.1.1 VPP - First Entry Mode ............................................................................................................................................... 13 4.1.2 VDD - First Entry Mode .............................................................................................................................................. 13 4.1.3 Program/Verify Mode Exit .......................................................................................................................................... 13 4.2 Low-Voltage Programming (LVP) Mode ............................................................................................................................... 13 4.3 Program/Verify Commands ................................................................................................................................................... 14 4.3.1 Load Configuration ..................................................................................................................................................... 15 4.3.2 Load Data For Program Memory ............................................................................................................................... 15 4.3.3 Load Data For Data Memory ...................................................................................................................................... 16 4.3.4 Read Data From Program Memory ............................................................................................................................ 16 4.3.5 Read Data From Data Memory .................................................................................................................................. 17 4.3.6 Increment Address ..................................................................................................................................................... 17 4.3.7 Reset Address ............................................................................................................................................................ 18 4.3.8 Begin Internally Timed Programming ......................................................................................................................... 18 4.3.9 Begin Externally Timed Programming ........................................................................................................................ 19 4.3.10 End Externally Timed Programming .......................................................................................................................... 19 4.3.11 Bulk Erase Program Memory ..................................................................................................................................... 20 4.3.12 Bulk Erase Data Memory ........................................................................................................................................... 20 4.3.13 Row Erase Program Memory ..................................................................................................................................... 21 5.0 Programming Algorithms ........................................................................................................................................................... 22 6.0 Code Protection ......................................................................................................................................................................... 30 6.1 Program Memory .................................................................................................................................................................. 30 6.2 Data Memory ........................................................................................................................................................................ 30 7.0 Hex File Usage .......................................................................................................................................................................... 30 7.1 Configuration Word ............................................................................................................................................................... 30 7.2 Device ID and Revision ......................................................................................................................................................... 30 7.3 Data EEPROM ...................................................................................................................................................................... 30 7.4 Checksum Computation ........................................................................................................................................................ 31 7.4.1 Code Protection Disabled .......................................................................................................................................... 31 7.4.2 Code Protection Enabled ........................................................................................................................................... 32 8.0 Electrical Specifications............................................................................................................................................................. 33 8.1 AC Timing Diagrams ............................................................................................................................................................. 34 DS41360A-page 2 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 2.0 DEVICE PINOUTS The pin diagrams for the PIC16F193X/PIC16LF193X family are shown in Figure 2-1 through Figure 2-5. The pins that are required for programming are listed in Table 1-1 and shown in bold lettering in the pin diagrams. FIGURE 2-1: 28-PIN PDIP/SOIC/SSOP DIAGRAM FOR PIC16F1933/1936/1938 AND PIC16LF1933/1936/1938 28-pin SPDIP, SOIC, SSOP FIGURE 2-2: 28 RB7/ICSPDAT RA0 2 27 RB6/ICSPCLK RA1 3 26 RB5 RA2 4 25 RA3 5 24 RB4 RB3 RA4 RA5 VSS 6 23 RB2 22 21 20 RB1 RB0 VDD 19 VSS 18 RC7 PIC16F1933/1936/1938 1 PIC16LF1933/1936/1938 VPP/MCLR/RE3 RA7 7 8 9 RA6 RC0 10 11 RC1 RC2 RC3 12 17 13 16 RC6 RC5 14 15 RC4 28-PIN QFN PACKAGE DIAGRAM FOR PIC16F1933/1936/1938 AND PIC16LF1933/1936/1938 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 28 27 26 25 24 23 22 RA1 RA0 28-pin QFN 1 21 2 20 3 PIC16F1933/1936/1938 19 4 PIC16LF1933/1936/1938 18 5 17 6 16 7 15 RB3 RB2 RB1 RB0 VDD VSS RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 8 9 10 11 12 13 14 RA2 RA3 RA4 RA5 VSS RA7 RA6 (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 3 PIC16F193X/LF193X FIGURE 2-3: 40-PIN PDIP PACKAGE DIAGRAM FOR PIC16F1934/1937/1939 AND PIC16LF1934/1937/1939 40-pin PDIP 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 34 RB1 RE0 8 33 RB0 RE1 9 FIGURE 2-4: PIC16F1934/1937/1939 PIC16LF1934/1937/1939 1 VPP/MCLR/RE3 32 VDD 31 VSS 30 RD7 29 RD6 28 RD5 RE2 10 VDD 11 VSS 12 RA7 13 RA6 14 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 RC2 17 24 RC5 RC3 18 23 RC4 RD0 19 22 RD3 RD1 20 21 RD2 44-PIN QFN PACKAGE DIAGRAM FOR PIC16F1934/1937/1939 AND PIC16LF1934/1937/1939 12 13 14 15 16 17 18 19 20 21 22 1 33 2 32 3 31 4 30 5 PIC16F1934/1937/1939 29 6 PIC16LF1934/1937/1939 28 7 27 8 26 9 25 10 24 11 23 RA6 RA7 VSS VSS NC VDD RE2 RE1 RE0 RA5 RA4 RB3 NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD VDD RB0 RB1 RB2 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 RC0 44-pin QFN DS41360A-page 4 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 2-5: 44-PIN TQFP PACKAGE DIAGRAM FOR PIC16F1934/1937/1939 AND PIC16LF1934/1937/1939 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 PIC16F1934/1937/1939 6 PIC16LF1934/1937/1939 7 8 9 10 11 NC RC0 RA6 RA7 VSS VDD RE2 RE1 RE0 RA5 RA4 NC NC RB4 RB5 ICSPCLK/RB6 ICSPDAT/RB7 VPP/MCLR/RE3 RA0 RA1 RA2 RA3 RC7 RD4 RD5 RD6 RD7 VSS VDD RB0 RB1 RB2 RB3 44 43 42 41 40 39 38 37 36 35 34 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 NC 44-pin TQFP (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 5 PIC16F193X/LF193X 3.0 MEMORY MAP The memory for the PIC16F193X/LF193X devices is broken into two sections: program memory and configuration memory. Only the size of the program memory changes between devices, the configuration memory remains the same. FIGURE 3-1: PIC16F1933/PIC16LF1933, PIC16F1934/PIC16LF1934 PROGRAM MEMORY MAPPING 4 KW 0000h 0FFFh Implemented Maps to 0-0FFF 8000h User ID Location 8001h User ID Location 8002h User ID Location 8003h User ID Location 8004h Reserved 8005h Reserved 8006h Device ID 8007h Configuration Word 1 8008h Configuration Word 2 8009h Calibration Word 1 800Ah Calibration Word 2 7FFFh 8000h Program Memory Implemented 8200h Maps to 8000-81FF Configuration Memory FFFFh 800Bh-81FFh DS41360A-page 6 Reserved Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 3-2: PIC16F1936/PIC16LF1936, PIC16F1937/PIC16LF1937 PROGRAM MEMORY MAPPING 8 KW 0000h Implemented 1FFFh Program Memory 8000h User ID Location 8001h User ID Location 8002h 8003h User ID Location User ID Location 8004h Reserved 8005h Reserved 8006h Device ID 8007h Configuration Word 1 8008h Configuration Word 2 8009h Calibration Word 1 800Ah Calibration Word 2 Maps to 0-1FFF 7FFFh 8000h Implemented 8200h Maps to 8000-81FF Configuration Memory FFFFh 800Bh-81FFh (c) 2008 Microchip Technology Inc. Reserved Advance Information DS41360A-page 7 PIC16F193X/LF193X FIGURE 3-3: PIC16F1938/PIC16LF1938, PIC16F1939/PIC16LF1939 PROGRAM MEMORY MAPPING 16 KW 0000h Implemented 3FFFh Program Memory 8000h User ID Location 8001h User ID Location 8002h User ID Location 8003h User ID Location 8004h Reserved 8005h Reserved 8006h Device ID 8007h Configuration Word 1 8008h Configuration Word 2 8009h Calibration Word 1 800Ah Calibration Word 2 Maps to 0-3FFF 7FFFh 8000h Implemented 8200h Maps to 8000-81FF Configuration Memory FFFFh 800Bh-81FFh DS41360A-page 8 Reserved Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 3.1 User ID Location 3.2 A user may store identification information (user ID) in four designated locations. The user ID locations are mapped to 8000h-8003h. Each location is 14 bits in length. Code protection has no effect on these memory locations. Each location may be read with code protection enabled or disabled. Note: Device ID The device ID word for the PIC16F193X/LF193X is located at 8006h. This location is read-only and can not be erased or modified. MPLAB(R) IDE only displays the 7 Least Significant bits (LSb) of each user ID location, the upper bits are not read. It is recommended that only the 7 LSb's be used if MPLAB IDE is the primary tool used to read these addresses. DEVICEID: DEVICE ID REGISTER(1) REGISTER 3-1: R-q R-q R-q R-q R-q R-q R-q DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 bit 13 bit 7 R-q R-q R-q R-q R-q R-q R-q DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 6 bit 0 Legend: P = Programmable bit U = Unimplemented bit, read as `0' R = Readable bit W = Writable bit `0' = Bit is cleared -n = Value at POR `1' = Bit is set x = Bit is unknown bit 13-5 DEV<8:0>: Device ID bits These bits are used to identify the part number. bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. TABLE 3-1: DEVICE ID VALUES DEVICE ID VALUES DEVICE DEV REV PIC16F1933 10 0011 001 x xxxx PIC16F1934 10 0011 010 x xxxx PIC16F1936 10 0011 011 x xxxx PIC16F1937 10 0011 100 x xxxx PIC16F1938 10 0011 101 x xxxx PIC16F1939 10 0011 110 x xxxx PIC16LF1933 10 0100 001 x xxxx PIC16LF1934 10 0100 010 x xxxx PIC16LF1936 10 0100 011 x xxxx PIC16LF1937 10 0100 100 x xxxx PIC16LF1938 10 0100 101 x xxxx PIC16LF1939 10 0100 110 x xxxx (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 9 PIC16F193X/LF193X 3.3 Configuration Words The PIC16F193X/PIC16LF193X has two Configuration Words, Configuration Word 1 (8007h) and Configuration Word 2 (8008h). The individual bits within these Configuration Words are used to enable or disable device functions such as the Brown-out Reset, code protection and Power-up Timer. 3.4 Calibration Words For the PIC16F193X/PIC16LF193X devices, the internal calibration values are factory calibrated and stored in Calibration Words 1 and 2 (8009h and 800Ah). The Calibration Words do not participate in erase operations. The device can be erased without affecting the Calibration Words. DS41360A-page 10 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X REGISTER 3-2: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN BOREN1 BOREN0 CPD CP bit 13 bit 7 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 MCLRE PWRTE WDTE1 WDTE0 FOSC2 FOSC1 FOSC0 bit 6 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit W = Writable bit `0' = Bit is cleared -n = Value at POR `1' = Bit is set x = Bit is unknown bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT 0 = CLKOUT function is enabled on RA6/CLKOUT bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled bit 8 CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled bit 7 CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: RE3/MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = RE3/MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = RE3/MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit. bit 5 PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep. 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled bit 2-0 FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode: CLKIN on RA7/OSC1/CLKIN 110 = ECM: External Clock, Medium-Power mode: CLKIN on RA7/OSC1/CLKIN 101 = ECL: External Clock, Low-Power mode: CLKIN on RA7/OSC1/CLKIN 100 = INTOSC oscillator: I/O function on RA7/OSC1/CLKIN 011 = EXTRC oscillator: RC function on RA7/OSC1/CLKIN 010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN 001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN 000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKOUT pin and RA7/OSC1/CLKIN Note 1: 2: 3: Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 11 PIC16F193X/LF193X REGISTER 3-3: CONFIGURATION WORD 2 R/P-1 R/P-1 U-1 R/P-1 R/P-1 R/P-1 U-1 LVP DEBUG -- BORV STVREN PLLEN -- bit 13 bit 7 U-1 R/P-1 R/P-1 U-1 U-1 R/P-1 R/P-1 -- VCAPEN1 VCAPEN0 -- -- WRT1 WRT0 bit 6 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit W = Writable bit `0' = Bit is cleared -n = Value at POR `1' = Bit is set x = Bit is unknown bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = HV on MCLR/VPP must be used for programming. bit 12 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6/ICSPCLK and RB7/ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, RB6/ICSPCLK and RB7/ICSPDAT are dedicated to the debugger bit 11 Unimplemented: Read as `1' bit 10 BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage set to 1.9V 0 = Brown-out Reset voltage set to 2.7V bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack overflow or underflow will cause a Reset 0 = Stack overflow or underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7-6 Unimplemented: Read as `1' bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits(2) 00 = VCAP functionality is enabled on RA0. 01 = VCAP functionality is enabled on RA5. 10 = VCAP functionality is enabled on RA6. 11 = No capacitor on VCAP pin. bit 3-2 Unimplemented: Read as `1' bit 1-0 WRT<1:0>: Flash memory self-write protection bits 4 kW FLASH memory (PIC16F1933/PIC16LF1933 and PIC16F1934/PIC16LF1934 only): 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write protected, no addresses may be modified by EECON control 8 kW FLASH memory (PIC16F1936/PIC16LF1936 and PIC16F1937/PIC16LF1937 only): 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control 01 = 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control 00 = 000h to 1FFFh write protected, no addresses may be modified by EECON control 16 kW FLASH memory (PIC16F1938/PIC16LF1938 and PIC16F1939/PIC16LF1939 only): 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to 3FFFh may be modified by EECON control 01 = 000h to 1FFFh write protected, 2000h to 3FFFh may be modified by EECON control 00 = 000h to 3FFFh write protected, no addresses may be modified by EECON control Note 1: 2: The LVP bit cannot be programmed to `0' when Programming mode is entered via LVP. Reads as `11' on PIC16LF193X only. DS41360A-page 12 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.0 PROGRAM/VERIFY MODE 4.1.3 PROGRAM/VERIFY MODE EXIT In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data words are transmitted LSb first. Data changes on the rising edge of the ICSPCLK and latched on the falling edge. In Program/Verify mode both the ICSPDAT and ICSPCLK are Schmitt Trigger inputs. The sequence that enters the device into Program/Verify mode places all other logic into the Reset state. Upon entering Program/Verify mode, all I/O's are automatically configured as high-impedance inputs and the address is cleared. To exit Program/Verify mode take MCLR to VDD or lower (VIL). See Figures 8-4 and 8-5. 4.1 Entry into the Low-Voltage ICSP Program/Verify modes requires the following steps: High-Voltage Program/Verify Mode Entry and Exit There are two different methods Program/Verify mode via high-voltage: of entering * VPP - First entry mode * VDD - First entry mode 4.1.1 VPP - FIRST ENTRY MODE To enter Program/Verify mode via the VPP-first method the following sequence must be followed: 1. 2. 3. Hold ICSPCLK and ICSPDAT low. All other pins should be unpowered. Raise the voltage on MCLR from 0V to VIHH. Raise the voltage on VDD FROM 0V to the desired operating voltage. The VPP-first entry prevents the device from executing code prior to entering Program/Verify mode. For example, when the Configuration Word has MCLR disabled (MCLRE = 0), the power-up time is disabled (PWRTE = 0), the internal oscillator is selected (FOSC = 100), and RB6 and RB7 are driven by the user application, the device will execute code. Since this may prevent entry, VPP-first entry mode is strongly recommended. See the timing diagram in Figure 8-3. 4.1.2 4.2 Low-Voltage Programming (LVP) Mode The Low-Voltage Programming mode allows the PIC16F193X/LF193X devices to be programmed using VDD only, without high voltage. When the LVP bit of the Configuration Word 2 register is set to '1', the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to '0'. This can only be done while in the High-Voltage Entry mode. 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. The key sequence is a specific 32-bit pattern, '0100 1101 0100 0011 0100 1000 0101 0000' (more easily remembered as MCHP in ASCII). The device will enter Program/Verify mode only if the sequence is valid. The Least Significant bit of the Least Significant nibble must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. For low-voltage programming timing, see Figures 8-9 and 8-10. Exiting Program/Verify mode is done by no longer driving MCLR to VIL. See Figures 8-9 and 8-10. VDD - FIRST ENTRY MODE To enter Program/Verify mode via the VDD-first method the following sequence must be followed: 1. 2. 3. Hold ICSPCLK and ICSPDAT low. Raise the voltage on VDD from 0V to the desired operating voltage. Raise the voltage on MCLR from VDD or below to VIHH. The VDD-first method is useful when programming the device when VDD is already applied, for it is not necessary to disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 8-2. (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 13 PIC16F193X/LF193X 4.3 Program/Verify Commands The PIC16F193X and PIC16LF193X implement 13 programming commands, each six bits in length. The commands are summarized in Table 4-1. Commands that have data associated with them are specified to have a minimum delay of TDLY between the command and the data. After this delay 16 clocks are required to either clock in or clock out the 14-bit data word. The first clock is for the Start bit and the last clock is for the Stop bit. TABLE 4-1: COMMAND MAPPING FOR PIC16F193X/LF193X Mapping Data/Note Command Binary (MSb ... LSb) Hex Load Configuration x 0 0 0 0 0 00h 0, data (14), 0 Load Data For Program Memory x 0 0 0 1 0 02h 0, data (14), 0 Load Data For Data Memory x 0 0 0 1 1 03h 0, data (8), zero (6), 0 Read Data From Program Memory x 0 0 1 0 0 04h 0, data (14), 0 Read Data From Data Memory x 0 0 1 0 1 05h 0, data (8), zero (6), 0 Increment Address x 0 0 1 1 0 06h -- Reset Address x 1 0 1 1 0 16h -- Begin Internally Timed Programming x 0 1 0 0 0 08h -- Begin Externally Timed Programming x 1 1 0 0 0 18h -- End Externally Timed Programming x 0 1 0 1 0 0Ah -- Bulk Erase Program Memory x 0 1 0 0 1 09h Internally Timed Bulk Erase Data Memory x 0 1 0 1 1 0Bh Internally Timed Row Erase Program Memory x 1 0 0 0 1 11h Internally Timed DS41360A-page 14 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.3.1 LOAD CONFIGURATION After issuing the Load Configuration command, use the Increment Address command until the proper address to be programmed is reached. The address is then programmed by issuing either the Begin Internally Timed Programming or Begin Externally Timed Programming command. The Load Configuration command is used to access the configuration memory (User ID Locations, Configuration Words, Calibration Words). The Load Configuration command sets the address to 8000h and loads the data latches with one word of data (see Figure 4-1). FIGURE 4-1: The only way to get back to the program memory (address 0) is to exit Program/Verify mode or issue the Reset Address command after the configuration memory has been accessed by the Load Configuration command. LOAD CONFIGURATION 1 2 5 4 3 2 1 6 16 15 TDLY ICSPCLK ICSPDAT 4.3.2 0 0 0 0 X 0 0 LSb 1 2 MSb 0 LOAD DATA FOR PROGRAM MEMORY The Load Data for Program Memory command is used to load one 14-bit word into the data latches. The word programs into program memory after the Begin Internally Timed Programming or Begin Externally Timed Programming command is issued (see Figure 4-2). FIGURE 4-2: LOAD DATA FOR PROGRAM MEMORY 1 2 3 4 5 6 15 16 TDLY ICSPCLK ICSPDAT 0 (c) 2008 Microchip Technology Inc. 1 0 0 0 X Advance Information 0 LSb MSb 0 DS41360A-page 15 PIC16F193X/LF193X 4.3.3 LOAD DATA FOR DATA MEMORY The Load Data for Data Memory command will load a 14-bit "data word" when 16 cycles are applied. However, the data memory is only 8 bits wide and thus, only the first 8 bits of data after the Start bit will be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow the internal circuitry to reset properly (see Figure 4-3). FIGURE 4-3: LOAD DATA FOR DATA MEMORY COMMAND 1 2 5 4 3 2 1 6 16 15 TDLY ICSPCLK 1 ICSPDAT 4.3.4 1 0 0 X 0 0 LSb MSb 0 READ DATA FROM PROGRAM MEMORY The Read Data from Program Memory command will transmit data bits out of the program memory map currently accessed, starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the first falling clock edge, and it will revert to Input mode (high-impedance) after the 16th falling edge of the clock. If the program memory is code-protected (CP), the data will be read as zeros (see Figure 4-4). FIGURE 4-4: READ DATA FROM PROGRAM MEMORY 1 2 3 4 5 6 1 2 15 16 TDLY ICSPCLK ICSPDAT (from Programmer) 0 0 1 0 0 ICSPDAT (from device) X x Input DS41360A-page 16 Advance Information LSb MSb Output Input (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.3.5 READ DATA FROM DATA MEMORY The Read Data from Data Memory command will transmit data bits out of the data memory starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the second rising edge, and it will revert to Input mode (high-impedance) after the 16th rising edge. The data memory is 8 bits wide, and therefore, only the first 8 bits that are output are actual data. If the data memory is code-protected, the data is read as all zeros. A timing diagram of this command is shown in Figure 4-5. FIGURE 4-5: READ DATA FROM DATA MEMORY COMMAND 1 2 3 4 5 6 1 2 15 16 TDLY ICSPCLK ICSPDAT (from Programmer) 1 1 0 0 0 X ICSPDAT (from device) x MSb Input Output Input 4.3.6 LSb INCREMENT ADDRESS The address is incremented when this command is received. It is not possible to decrement the address. To reset this counter, the user must use the Reset Address command or exit Program/Verify mode and re-enter it. If the address is incremented from address 7FFFh, it will wrap around to location 0000h. If the address is incremented from FFFFh, it will wrap around to location 8000h. FIGURE 4-6: INCREMENT ADDRESS Next Command 1 2 4 3 1 6 5 2 3 TDLY ICSPCLK 0 1 1 0 0 X ICSPDAT Address (c) 2008 Microchip Technology Inc. Advance Information X X X Address + 1 DS41360A-page 17 PIC16F193X/LF193X 4.3.7 RESET ADDRESS The Reset Address command will reset the address to 0000h, regardless of the current value. The address is used in program memory or the configuration memory. FIGURE 4-7: RESET ADDRESS Next Command 1 2 4 3 5 2 1 6 3 TDLY ICSPCLK 0 1 1 0 1 X X X X ICSPDAT 4.3.8 0000h N Address BEGIN INTERNALLY TIMED PROGRAMMING A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. An internal timing mechanism executes the write. The user must allow for the program cycle time, TPINT, for the programming to complete. The End Externally Timed Programming command is not needed when the Begin Internally Timed Programming is used to start the programming. The program memory address that is being programmed is not erased prior to being programmed. However, the EEPROM memory address that is being programmed is erased prior to being programmed with internally timed programming. FIGURE 4-8: BEGIN INTERNALLY TIMED PROGRAMMING 1 2 5 4 3 Next Command 1 2 3 6 TPINT ICSPCLK ICSPDAT DS41360A-page 18 0 0 0 1 0 X Advance Information X X X (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.3.9 BEGIN EXTERNALLY TIMED PROGRAMMING A Load Configuration, Load Data for Program Memory or Load Data for Data Memory command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. To complete the programming the End Externally Timed Programming command must be sent in the specified time window defined by TPEXT. No internal erase is performed for the data EEPROM, therefore, the device should be erased prior to executing this command. The Begin Externally Timed Programming command can not be used for programming the Configuration Words (see Figure 4-9). FIGURE 4-9: BEGIN EXTERNALLY TIMED PROGRAMMING End Externally Timed Programming Command 1 2 3 5 4 1 6 2 3 TPEXT ICSPCLK 0 ICSPDAT 4.3.10 0 0 1 0 X 1 1 0 END EXTERNALLY TIMED PROGRAMMING This command is required after a Begin Externally Timed Programming command is given. This command must be sent within the time window specified by TPEXT after the Begin Externally Timed Programming command is sent. After sending the End Externally Timed Programming command, an additional delay (TDIS) is required before sending the next command. This delay is longer than the delay ordinarily required between other commands (see Figure 4-10). FIGURE 4-10: END EXTERNALLY TIMED PROGRAMMING 1 2 5 4 3 Next Command 2 1 3 6 TDIS ICSPCLK ICSPDAT (c) 2008 Microchip Technology Inc. 0 1 0 1 1 X Advance Information X X X DS41360A-page 19 PIC16F193X/LF193X 4.3.11 BULK ERASE PROGRAM MEMORY After receiving the Bulk Erase Program Memory command the erase will not complete until the time interval, TERAB, has expired. The Bulk Erase Program Memory command performs two different functions dependent on the current state of the address. Note: Address 0000h-7FFFh: Program Memory is erased The code protection Configuration bit (CP) has no effect on the Bulk Erase Program Memory command. Configuration words are erased If CPD = 0, Data Memory is erased Address 8000h-8008h: Program Memory is erased Configuration Words are erased User ID Locations are erased If CPD = 0, Data Memory is erased A Bulk Erase Program Memory command should not be issued when the address is greater than 8008h. FIGURE 4-11: BULK ERASE PROGRAM MEMORY 1 2 3 5 4 Next Command 2 1 3 6 TERAB ICSPCLK ICSPDAT 4.3.12 0 1 0 0 1 X X X After receiving the Bulk Erase Data Memory command, the erase will not complete until the time interval, TERAB, has expired. BULK ERASE DATA MEMORY To perform an erase of the data memory, after a Bulk Erase Data Memory command, wait a minimum of TERAB to complete Bulk Erase. Note: To erase data memory when data code-protect is active (CPD = 0), the Bulk Erase Program Memory command should be used. FIGURE 4-12: X Data memory will not code-protected (CPD = 0). erase if BULK ERASE DATA MEMORY COMMAND Wait a minimum of TERAB 1 2 3 4 5 6 1 Next Command 2 ICSPCLK ICSPDAT DS41360A-page 20 1 1 0 1 X X Advance Information X 0 (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 4.3.13 ROW ERASE PROGRAM MEMORY The Row Erase Program Memory command will erase an individual row. A row of program memory consists of 32 consecutive 14-bit words. A row is addressed by the address PC<15:5>. If the program memory is code-protected the Row Erase Program Memory command will be ignored. When the address is 8000h-8008h the Row Erase Program Memory command will only erase the user ID locations regardless of the setting of the CP Configuration bit. After receiving the Row Erase Program Memory command the erase will not complete until the time interval, TERAR, has expired. FIGURE 4-13: ROW ERASE PROGRAM MEMORY 1 2 5 4 3 Next Command 1 2 3 6 TERAR ICSPCLK ICSPDAT (c) 2008 Microchip Technology Inc. 1 0 0 0 1 X Advance Information X X X DS41360A-page 21 PIC16F193X/LF193X 5.0 PROGRAMMING ALGORITHMS The PIC16F193X/PIC16LF193X devices have the capability of storing eight 14-bit words in its data latches. The data latches are internal to the PIC16F193X/PIC16LF193X devices and are only used for programming. The data latches allow the user to program up to eight program words with a single Begin Externally Timed Programming or Begin Internally Timed Programming command. The Load Program Data or the Load Configuration command is used to load a single data latch. The data latch will hold the data until the Begin Externally Timed Programming or Begin Internally Timed Programming command is given. The data latches are aligned with the 3 LSb of the address. The address at the time the Begin Externally Timed Programming or Begin Internally Timed Programming command is given will determine which location(s) in memory are written. Writes can not cross a physical eight-word boundary. For example, attempting to write from address 0002h-0009h will result in data being written to 0008h-000Fh. If more than 8 data latches are written without a Begin Externally Timed Programming or Begin Internally Timed Programming command the data in the data latches will be overwritten. The following figures show the recommended flowcharts for programming. DS41360A-page 22 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 5-1: DEVICE PROGRAM/VERIFY FLOWCHART Start Enter Programming Mode Bulk Erase Device Write Program Memory(1) Write User IDs Write Data Memory(3) Verify Program Memory Verify User IDs Verify Data Memory Write Configuration Words(2) Verify Configuration Words Exit Programming Mode Done Note 1: See Figure 5-2. 2: See Figure 5-5. 3: See Figure 5-6. (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 23 PIC16F193X/LF193X FIGURE 5-2: PROGRAM MEMORY FLOWCHART Start Bulk Erase Program Memory(1, 2) Program Cycle(3) Read Data from Program Memory No Data Correct? Report Programming Failure Yes Increment Address Command No All Locations Done? Yes Done Note 1: This step is optional if device has already been erased or has not been previously programmed. 2: If the device is code-protected or must be completely erased, then Bulk Erase device per Figure 5-8. 3: See Figure 5-3 or Figure 5-4. DS41360A-page 24 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 5-3: ONE-WORD PROGRAM CYCLE Program Cycle Load Data for Program Memory Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 25 PIC16F193X/LF193X FIGURE 5-4: MULTIPLE-WORD PROGRAM CYCLE Program Cycle Load Data for Program Memory Latch 1 Increment Address Command Load Data for Program Memory Latch 2 Increment Address Command Load Data for Program Memory Latch 8 Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS DS41360A-page 26 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 5-5: CONFIGURATION MEMORY PROGRAM FLOWCHART Start Load Configuration Bulk Erase Program Memory(1) One-word Program Cycle(2) (User ID) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Increment Address Command No Address = 8004h? Yes Increment Address Command Increment Address Command Increment Address Command One-word Program Cycle(2) (Config. Word 1) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Increment Address Command One-word Program Cycle(2) (Config. Word 2) Read Data From Program Memory Command Data Correct? No Report Programming Failure Yes Note 1: This step is optional if device is erased or not previously programmed. 2: See Figure 5-3. (c) 2008 Microchip Technology Inc. Advance Information Done DS41360A-page 27 PIC16F193X/LF193X FIGURE 5-6: DATA MEMORY PROGRAM FLOWCHART Start Bulk Erase Data Memory Data Program Cycle(1) Read Data From Data Memory Command Data Correct? No Report Programming Failure Yes Increment Address Command No All Locations Done? Yes Done Note 1: DS41360A-page 28 See Figure 5-7. Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 5-7: DATA MEMORY PROGRAM CYCLE Program Cycle Load Data for Data Memory Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS FIGURE 5-8: ERASE FLOWCHART Start Load Configuration Bulk Erase Program Memory Bulk Erase Data Memory Done Note: This sequence does not erase the Calibration Words. (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 29 PIC16F193X/LF193X 6.0 CODE PROTECTION 7.0 Code protection is controlled using the CP bit in Configuration Word 1. When code protection is enabled, all program memory locations (0000h-7FFFh) read as all `0'. Further programming is disabled for the program memory (0000h-7FFFh). Data memory is protected with its own Code-Protect bit (CPD). When data code-protection is enabled (CPD = 0), all data memory locations read as `0'. Further programming is disabled for the data memory. Data memory can still be programmed and read during program execution. The user ID locations and Configuration Words can be programmed and read out regardless of the code protection settings. 6.1 Program Memory Code protection is enabled by programming the CP bit in Configuration Word 1 register to `0'. The only way to disable code protection is to use the Bulk Erase Program Memory command. HEX FILE USAGE In the hex file there are two bytes per program word stored in the Intel(R) INHX32 hex format. Data is stored LSB first, MSB second. Because there are two bytes per word, the addresses in the hex file are 2x the address in program memory. (Example: The Configuration Word 1 is stored at 8007h on the PIC16F193X/PIC16LF193X. In the hex file this will be referenced as 1000Eh-1000Fh). 7.1 Configuration Word To allow portability of code, it is strongly recommended that the programmer is able to read the Configuration Words and user ID locations from the hex file. If the Configuration Words information was not present in the hex file, a simple warning message may be issued. Similarly, while saving a hex file, Configuration Words and user ID information should be included. 7.2 Device ID and Revision Data memory protection is enabled by programming the CPD bit in Configuration Word 1 register to `0'. If a device ID is present in the hex file at 1000Ch-1000Dh (8006h on the part), the programmer should verify the device ID (excluding the revision) against the value read from the part. On a mismatch condition the programmer should generate a warning message. The only way to disable code protection is to use the Bulk Erase Program Memory command. 7.3 6.2 Note: Data Memory To ensure system security, if CPD bit = 0, the Bulk Erase Program Memory command will also erase data memory. Data EEPROM The programmer should be able to read data memory information from a hex file and write data memory contents to a hex file. The physical address range of the 256 data memory is 0000h-00FFh. However, these addresses are logically mapped to address 1E000h-1E1FFh in the hex file. This provides a way of differentiating between the data and program memory locations in this range. The format for data memory storage is one data byte per address location, LSb aligned. DS41360A-page 30 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 7.4 7.4.1 Checksum Computation The checksum is calculated by two different methods dependent on the setting of the CP Configuration bit. TABLE 7-1: Device CONFIGURATION WORD MASK VALUES Config. Word 1 Mask Config. Word 2 Mask PIC16F1933 3FFFh 3733h PIC16LF1933 3FFFh 3703h PIC16F1934 3FFFh 3733h PIC16LF1934 3FFFh 3703h PIC16F1936 3FFFh 3733h PIC16LF1936 3FFFh 3703h PIC16F1937 3FFFh 3733h PIC16LF1937 3FFFh 3703h PIC16F1938 3FFFh 3733h PIC16LF1938 3FFFh 3703h PIC16F1939 3FFFh 3733h PIC16LF1939 3FFFh 3703h EXAMPLE 7-1: PIC16F1936 PROGRAM CODE PROTECTION DISABLED With the program code protection disabled, the checksum is computed by reading the contents of the PIC16F193X/PIC16LF193X program memory locations and adding up the program memory data starting at address 0000h, up to the maximum user addressable location (e.g., 1FFFH for the PIC16F1936). Any Carry bit exceeding 16 bits are ignored. Additionally, the relevant bits of the Configuration Words are added to the checksum. All unimplemented Configuration bits are masked to `0'. Note: Data memory checksum. does not effect the CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED (PIC16F1936) Sum of Memory addresses 0000h-1FFFh 2534h Configuration Word 1 2D83h Configuration Word 1 mask 3FFFh Configuration Word 2 3AEFh Configuration Word 2 mask Checksum 3733h = 2534h + (2D83h and 3FFFh) + (3AEFh and 3733h) = 2534h + 2D83h + 3223h = 84DAh EXAMPLE 7-2: PIC16LF1936 CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED (PIC16LF1936) Sum of Memory addresses 0000h-1FFFh 2534h Configuration Word 1 2D83h Configuration Word 1 mask 3FFFh Configuration Word 2 3AFFh Configuration Word 2 mask(1) 3703h Checksum = 2534h + (2D83h and 3FFFh) + (3AFFh and 3703h) = 2534h + 2D83h + 3203h = 84BAh Note 1: In PIC16LF193X devices, the VCAPEN<1:0> bits are not implemented in Configuration Word 2 and the Configuration Word 2 mask is 3703h. (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 31 PIC16F193X/LF193X 7.4.2 PROGRAM CODE PROTECTION ENABLED With the program code protection enabled the checksum is computed in the following manner. The Configuration Words are summed (all unimplemented Configuration bits are masked to `0') with the Least Significant nibble of the user ID's. Note: Data memory checksum. EXAMPLE 7-3: PIC16F1936 does not effect the CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED (PIC16F1936) Configuration Word 1 2C03h Configuration Word 1 mask 3FFFh Configuration Word 2 3AECh Configuration Word 2 mask 3733h User ID (8000h) 0123h User ID (8001h) 4567h User ID (8002h) 89ABh User ID (8003h) CDEFh Checksum = (2C03h and 3FFFh) + (3AECh and 3733h) + (0123h and 000Fh) + (4567h and 000Fh) + (89ABh and 000Fh) +(CDEFh and 000Fh) = 2C03h +3220h + 0003h + 0007h + 000Bh + 000Fh = 5E47h EXAMPLE 7-4: PIC16LF1936 CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED (PIC16LF1936) Configuration Word 1 2C03h Configuration Word 1 mask 3FFFh Configuration Word 2 3AFCh Configuration Word 2 mask(1) 3703h User ID (8000h) 0123h User ID (8001h) 4567h User ID (8002h) 89ABh User ID (8003h) CDEFh Checksum = (2C03h and 3FFFh) + (3AFCh and 3703h) + (0123h and 000Fh) + (4567h and 000Fh) + (89ABh and 000Fh) +(CDEFh and 000Fh) = 2C03h +3200h + 0003h + 0007h + 000Bh + 000Fh = 5E27h Note 1: In PIC16LF193X devices, the VCAPEN<1:0> bits are not implemented in Configuration Word 2 and the Configuration Word 2 mask is 3703h. DS41360A-page 32 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X 8.0 ELECTRICAL SPECIFICATIONS Refer to device specific data sheet for absolute maximum ratings. TABLE 8-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE Standard Operating Conditions (unless otherwise stated) Operating Temperature -40C TA +85C AC/DC CHARACTERISTICS Sym. Characteristics Min. Typ. Max. Units Conditions/Comments Supply Voltages and currents VDD VDD Read/Write and Row Erase operations Bulk Erase operations PIC16F193X PIC16LF193X PIC16F193X PIC16LF193X 2.1 2.1 2.7 2.7 -- -- -- -- 5.5 3.6 5.5 3.6 V V V V IDDI Current on VDD, Idle -- -- 1.0 mA IDDP Current on VDD, Programming -- -- 3.0 mA VPP IPP Current on MCLR/VPP -- -- 600 A VIHH High voltage on MCLR/VPP for Program/Verify mode entry 8.0 -- 9.0 V TVHHR MCLR rise time (VIL to VIHH) for Program/Verify mode entry -- -- 1.0 s VIH (ICSPCLK, ICSPDAT, MCLR/VPP) input high level 0.8 VDD -- -- V -- VDD-0.7 VDD-0.7 VDD-0.7 -- 0.2 VDD V -- -- V -- -- VSS+0.6 VSS+0.6 VSS+0.6 V -- ns -- s -- -- -- -- ns ns ns ns 80 ns 80 ns 80 ns -- s 5 2.5 2.5 5 2.1 ms ms ms ms ms -- s -- s I/O pins VIL (ICSPCLK, ICSPDAT, MCLR/VPP) input low level ICSPDAT output high level VOH ICSPDAT output low level VOL TENTS TENTH TCKL TCKH TDS TDH TCO TLZD THZD TDLY TERAB TERAR TPINT TPEXT TDIS TEXIT Programming mode entry and exit Programing mode entry setup time: ICSPCLK, 100 -- ICSPDAT setup time before VDD or MCLR Programing mode entry hold time: ICSPCLK, 250 -- ICSPDAT hold time after VDD or MCLR Serial Program/Verify Clock Low Pulse Width 100 -- Clock High Pulse Width 100 -- Data in setup time before clock 100 -- Data in hold time after clock 100 -- Clock to data out valid (during a 0 -- Read Data command) Clock to data low-impedance (during a 0 -- Read Data command) Clock to data high-impedance (during a 0 -- Read Data command) Data input not driven to next clock input (delay required between command/data or 1.0 -- command/command) Bulk Erase cycle time -- -- Row Erase cycle time -- -- Internally timed programming operation time -- -- -- -- Externally timed programming pulse 1.0 -- Time delay from program to compare 100 -- (HV discharge time) Time delay when exiting Program/Verify mode 1 -- (c) 2008 Microchip Technology Inc. Advance Information IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.3V IOH = 2 mA, VDD = 1.8V IOH = 8 mA, VDD = 5V IOH = 6 mA, VDD = 3.3V IOH = 3 mA, VDD = 1.8V Program memory Configuration words DS41360A-page 33 PIC16F193X/LF193X 8.1 FIGURE 8-5: AC Timing Diagrams FIGURE 8-2: PROGRAMMING MODE ENTRY - VDD FIRST TENTS PROGRAMMING MODE EXIT - VDD LAST TEXIT VIHH TENTH VPP VIL VIHH VPP VDD VIL ICSPDAT VDD ICSPCLK ICSPDAT ICSPCLK FIGURE 8-6: CLOCK AND DATA TIMING TCKH FIGURE 8-3: PROGRAMMING MODE ENTRY - VPP FIRST TENTS TCKL ICSPCLK TENTH TDS TDH VIHH ICSPDAT as input VPP VIL TCO VDD ICSPDAT as output ICSPDAT TLZD ICSPCLK ICSPDAT from input to output FIGURE 8-4: PROGRAMMING MODE EXIT - VPP LAST TEXIT THZD ICSPDAT from output to input VIHH VPP VIL VDD ICSPDAT ICSPCLK DS41360A-page 34 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X FIGURE 8-7: WRITE COMMAND-PAYLOAD TIMING TDLY 1 2 3 4 5 X X X X X 2 1 6 15 16 ICSPCLK 0 LSb X MSb ICSPDAT FIGURE 8-8: Next Command Payload Command 0 READ COMMAND-PAYLOAD TIMING TDLY 1 2 3 4 5 X ICSPDAT (from Programmer) X X X X 2 1 6 15 16 ICSPCLK X x LSb MSb ICSPDAT (from Device) Command (c) 2008 Microchip Technology Inc. Advance Information Payload 0 Next Command DS41360A-page 35 PIC16F193X/LF193X FIGURE 8-9: LVP ENTRY (POWERING UP) VDD MCLR TENTS TENTH 33 clocks TCKH TCKL ICSPCLK TDH TDS LSb of Pattern 0 ICSPDAT FIGURE 8-10: MSb of Pattern 1 2 ... 31 LVP ENTRY (POWERED) VDD MCLR TENTH 33 Clocks TCKH TCKL ICSPCLK TDH TDS LSb of Pattern 0 ICSPDAT Note 1: 1 2 ... MSb of Pattern 31 Sequence matching can start with no edge on MCLR first. DS41360A-page 36 Advance Information (c) 2008 Microchip Technology Inc. PIC16F193X/LF193X APPENDIX A: REVISION HISTORY Revision A (11/2008) Original release of this document. (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 37 PIC16F193X/LF193X NOTES: DS41360A-page 38 Advance Information (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. Advance Information DS41360A-page 39 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/02/08 DS41360A-page 40 Advance Information (c) 2008 Microchip Technology Inc.