CLK1A (8 KHz)
CLK1B (8 KHz)
CLK2A (19.44 MHz)
CLK2B (19.44 MHz)
CLK3A (User Defined up to 100 MHz)
CLK3B (User Defined up to 100 MHz)
80W RT
80W RT
80W RT
80W RT
80W RT
80W RT
80W RT
80W RT
80W RT
80W RT
80W RT
80W RT
ATCA Backplane
Slot Card N Slot Card N+1
MLVDS Drivers/Receivers
MLVDS Drivers/Receivers
DS91C180, DS91D180
www.ti.com
SNLS158M –MARCH 2006–REVISED APRIL 2013
DS91D180/DS91C180 100 MHz M-LVDS Line Driver/Receiver Pair
Check for Samples: DS91C180,DS91D180
1FEATURES DESCRIPTION
The DS91D180 and DS91C180 are 100 MHz M-
2• DC to 100+ MHz / 200+ Mbps Low Power, Low LVDS (Multipoint Low Voltage Differential Signaling)
EMI Operation line driver/receiver pairs designed for applications
• Optimal for ATCA, uTCA Clock Distribution that utilize multipoint networks (e.g. clock distribution
Networks in ATCA and uTCA based systems). M-LVDS is a
bus interface standard (TIA/EIA-899) optimized for
• Meets or Exceeds TIA/EIA-899 M-LVDS multidrop networks. Controlled edge rates, tight input
Standard receiver thresholds and increased drive strength are
• Wide Input Common Mode Voltage for sone of the key enhancments that make M-LVDS
Increased Noise Immunity devices an ideal choice for distributing signals via
• DS91D180 has Type 1 Receiver Input multipoint networks.
• DS91C180 has Type 2 Receiver Input for Fail- The DS91D180/DS91C180 driver input accepts
Safe Functionality LVTTL/LVCMOS signals and converts them to
differential M-LVDS signal levels. The
• Industrial Temperature Range DS91D180/DS91C180 receiver accepts low voltage
• Space Saving SOIC-14 Package (JEDEC MS- differential signals (LVDS, B-LVDS, M-LVDS, LV-
012) PECL and CML) and converts them to 3V LVCMOS
signals. The DS91D180 device has a M-LVDS type 1
receiver input with no offset.The DS91C180 device
has a type 2 receiver input which enable failsafe
functionality.
Typical Application in an ATCA Clock Distribution Network
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
xxx
xxx
xxx
High High
Low Low
0 V
2.4 V
-2.4 V
50 mV
-50 mV
150 mV
Transition Region
Type 1 Type 2
VID
DS91C180, DS91D180
SNLS158M –MARCH 2006–REVISED APRIL 2013
www.ti.com
Figure 1. Connection Diagram
Top View
See Package Number D0014A
Logic Diagram
M-LVDS Receiver Types
The EIA/TIA-899 M-LVDS standard specifies two different types of receiver input stages. A type 1 receiver has a
conventional threshold that is centered at the midpoint of the input amplitude, VID/2. A type 2 receiver has a built
in offset that is 100mV greater than VID/2. The type 2 receiver offset acts as a failsafe circuit where open or short
circuits at the input will always result in the output stage being driven to a low logic state.
Figure 2. M-LVDS Receiver Input Thresholds
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNLS158M –MARCH 2006–REVISED APRIL 2013
Absolute Maximum Ratings (1)(2)
Supply Voltage, VCC −0.3V to +4V
Control Input Voltages −0.3V to (VCC + 0.3V)
Driver Input Voltage −0.3V to (VCC + 0.3V)
Driver Output Voltages −1.8V to +4.1V
Receiver Input Voltages −1.8V to +4.1V
Receiver Output Voltage −0.3V to (VCC + 0.3V)
Maximum Package Power Dissipation at +25°C SOIC Package 1.1 W
Derate SOIC Package 8.8 mW/°C above +25°C
Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC) θJA 113.7 °C/W
θJC 36.9 °C/W
Maximum Junction Temperature 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 4 seconds) 260°C
ESD Ratings: (HBM 1.5kΩ, 100pF) ≥5 kV
(EIAJ 0Ω, 200pF) ≥250 V
(CDM 0Ω, 0pF) ≥1000 V
(1) “Absolute Maximum Ratings” are those beyond which the safety of the device cannot be ensured. They are not meant to imply that the
device should be operated at these limits. The tables of “Electrical Characteristics” provide conditions for actual device operation.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
Recommended Operating Conditions Min Typ Max Units
Supply Voltage, VCC 3.0 3.3 3.6 V
Voltage at Any Bus Terminal (Separate or Common-Mode) −1.4 +3.8 V
Differential Input Voltage VID 2.4 V
High Level Input Voltage VIH 2.0 VCC V
Low Level Input Voltage VIL 0 0.8 V
Operating Free Air Temperature TA−40 +25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)(4)
Symbol Parameter Conditions Min Typ Max Units
M-LVDS Driver
|VYZ| Differential output voltage magnitude RL= 50Ω, CL= 5pF 480 650 mV
Figure 3 and Figure 5
ΔVYZ Change in differential output voltage magnitude −50 0 +50 mV
between logic states
VOS(SS) Steady-state common-mode output voltage RL= 50Ω, CL= 5pF 0.3 1.8 2.1 V
Figure 3 and Figure 4
|ΔVOS(SS)| Change in steady-state common-mode output voltage 0 +50 mV
between logic states
VOS(PP) Peak-to-peak common-mode output voltage (VOS(pp) @ 500KHz clock) 143 mV
VY(OC) Maximum steady-state open-circuit output voltage Figure 6 0 2.4 V
VZ(OC) Maximum steady-state open-circuit output voltage 0 2.4 V
VP(H) Voltage overshoot, low-to-high level output RL= 50Ω, CL= 5pF, 1.2VSS V
CD= 0.5pF
VP(L) Voltage overshoot, high-to-low level output −0.2VSS V
Figure 8 and Figure 9(5)
IIH High-level input current (LVTTL inputs) VIH = 2.0V -15 15 μA
(1) All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
(2) All typicals are given for VCC = 3.3V and TA= 25°C.
(3) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this datasheet.
(4) CLincludes fixture capacitance and CDincludes probe capacitance.
(5) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
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SNLS158M –MARCH 2006–REVISED APRIL 2013
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)(4)
Symbol Parameter Conditions Min Typ Max Units
IIL Low-level input current (LVTTL inputs) VIL = 0.8V -15 15 μA
VIKL Input Clamp Voltage (LVTTL inputs) IIN = -18 mA -1.5 V
IOS Differential short-circuit output current Figure 7 -43 43 mA
M-LVDS Receiver
VIT+ Positive-going differential input voltage threshold See Function Tables Type 1 20 50 mV
Type 2 94 150 mV
VIT−Negative-going differential input voltage threshold See Function Tables Type 1 −50 20 mV
Type 2 50 94 mV
VOH High-level output voltage IOH =−8mA 2.4 2.7 V
VOL Low-level output voltage IOL = 8mA 0.28 0.4 V
IOZ TRI-STATE output current VO= 0V or 3.6V −10 10 μA
IOSR Short circuit Rrceiver output current (LVTTL Output) VO= 0V -90 -48 mA
M-LVDS Bus (Input and Output) Pins
IA, IYReceiver input or driver high-impedance output VA,Y = 3.8V, VB,Z = 1.2V, 32 µA
current DE = GND
VA,Y = 0V or 2.4V, VB,Z = 1.2V, DE −20 +20 µA
= GND
VA,Y =−1.4V, VB,Z = 1.2V, −32 µA
DE = GND
IB, IZReceiver input or driver high-impedance output VB,Z = 3.8V, VA,Y = 1.2V, 32 µA
current DE = GND
VB,Z = 0V or 2.4V, VA,Y = 1.2V, DE −20 +20 µA
= GND
VB,Z =−1.4V, VA,Y = 1.2V, −32 µA
DE = GND
IAB, IYZ Receiver input or driver high-impedance output VA,Y = VB,Z,−1.4V ≤V≤3.8V, DE −4 +4 µA
differential current (IA−IBor IY−IZ) = GND
IA(OFF), Receiver input or driver high-impedance output VA,Y = 3.8V, VB,Z = 1.2V,
IY(OFF) power-off current DE = 0V 32 µA
0V ≤VCC ≤1.5V
VA,Y = 0V or 2.4V, VB,Z = 1.2V,
DE = 0V −20 +20 µA
0V ≤VCC ≤1.5V
VA,Y =−1.4V, VB,Z = 1.2V,
DE = 0V −32 µA
0V ≤VCC ≤1.5V
IB(OFF), Receiver input or driver high-impedance output VB,Z = 3.8V, VA,Y = 1.2V,
IZ(OFF) power-off current DE = 0V 32 µA
0V ≤VCC ≤1.5V
VB,Z = 0V or 2.4V, VA,Y = 1.2V,
DE = 0V −20 +20 µA
0V ≤VCC ≤1.5V
VB,Z =−1.4V, VA,Y = 1.2V,
DE = 0V −32 µA
0V ≤VCC ≤1.5V
IAB(OFF), Receiver input or driver high-impedance output VA,Y = VB,Z,−1.4V ≤V≤3.8V,
IYZ(OFF) power-off differential current DE = 0V −4 +4 µA
(IA(OFF) −IB(OFF) or IY(OFF) −IZ(OFF)) 0V ≤VCC ≤1.5V
CA, CBReceiver input capacitance VCC = OPEN 5.1 pF
CY, CZDriver output capacitance 8.5 pF
CAB Receiver input differential capacitance 2.5 pF
CYZ Driver output differential capacitance 5.5 pF
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SNLS158M –MARCH 2006–REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified. (1)(2)(3)(4)
Symbol Parameter Conditions Min Typ Max Units
CA/B, Receiver input or driver output capacitance balance 1.0
CY/Z (CA/CBor CY/CZ)
SUPPLY CURRENT (VCC)
ICCD Driver Supply Current RL= 50Ω, DE = VCC, RE = VCC 17 29.5 mA
ICCZ TRI-STATE Supply Current DE = GND, RE = VCC 7 9.0 mA
ICCR Receiver Supply Current DE = GND, RE = GND 14 18.5 mA
ICCB Supply Current, Driver and Receiver Enabled DE = VCC, RE = GND 20 29.5 mA
Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (1) (2)
Symbol Parameter Conditions Min Typ Max Units
DRIVER AC SPECIFICATION
tPLH Differential Propagation Delay Low to High RL= 50Ω, CL= 5 pF, 1.0 3.4 5.5 ns
tPHL Differential Propagation Delay High to Low CD= 0.5 pF 1.0 3.1 5.5 ns
tSKD1 (tsk(p)) Pulse Skew |tPLHD −tPHLD|(3) (4) Figure 8 and Figure 9 300 420 ps
tSKD3 Part-to-Part Skew (5) (4) 1.9 ns
tTLH (tr) Rise Time (4) 1.0 1.8 3.0 ns
tTHL (tf) Fall Time (4) 1.0 1.8 3.0 ns
tPZH Enable Time (Z to Active High) RL= 50Ω, CL= 5 pF, 8 ns
tPZL Enable Time (Z to Active Low ) CD= 0.5 pF 8 ns
tPLZ Disable Time (Active Low to Z) Figure 10 and Figure 11 8 ns
tPHZ Disable Time (Active High to Z) 8 ns
tJIT Random Jitter, RJ (4) 100MHz clock pattern(6) 2.5 5.5 psrms
fMAX Maximum Data Rate 200 Mbps
RECEIVER AC SPECIFICATION
tPLH Propagation Delay Low to High CL= 15 pF 2.0 4.7 7.5 ns
tPHL Propagation Delay High to Low Figure 12 Figure 13 and Figure 14 2.0 5.3 7.5 ns
tSKD1 (tsk(p)) Pulse Skew |tPLHD −tPHLD|(3)(4) 0.6 1.9 ns
tSKD3 Part-to-Part Skew (5)(4) 1.5 ns
tTLH (tr) Rise Time(4) 0.5 1.2 3.0 ns
tTHL (tf) Fall Time(4) 0.5 1.2 3.0 ns
tPZH Enable Time (Z to Active High) RL= 500Ω, CL= 15 pF 10 ns
tPZL Enable Time (Z to Active Low) Figure 15 and Figure 16 10 ns
tPLZ Disable Time (Active Low to Z) 10 ns
tPHZ Disable Time (Active High to Z) 10 ns
fMAX Maximum Data Rate 200 Mbps
(1) All typicals are given for V = 3.3V and TA= 25°C.
(2) CLincludes fixture capacitance and CDincludes probe capacitance.
(3) tSKD1, |tPLHD −tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(4) Not production tested. Ensured by a statistical analysis on a sample basis at the time of characterization.
(5) tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
(6) Stimulus and fixture jitter has been subtracted.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
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A
B
~ 2.1V
~ 1.5V
'VOS(SS)
VOS(PP)
VOS
DS91C180, DS91D180
SNLS158M –MARCH 2006–REVISED APRIL 2013
www.ti.com
Test Circuits and Waveforms
Figure 3. Differential Driver Test Circuit
Figure 4. Differential Driver Waveforms
Figure 5. Differential Driver Full Load Test Circuit
Figure 6. Differential Driver DC Open Test Circuit
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SNLS158M –MARCH 2006–REVISED APRIL 2013
Figure 7. Differential Driver Short-Circuit Test Circuit
Figure 8. Driver Propagation Delay and Transition Time Test Circuit
Figure 9. Driver Propagation Delays and Transition Time Waveforms
Figure 10. Driver TRI-STATE Delay Test Circuit
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Figure 11. Driver TRI-STATE Delay Waveforms
Figure 12. Receiver Propagation Delay and Transition Time Test Circuit
Figure 13. Type 1 Receiver Propagation Delay and Transition Time Waveforms
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SNLS158M –MARCH 2006–REVISED APRIL 2013
Figure 14. Type 2 Receiver Propagation Delay and Transition Time Waveforms
Figure 15. Receiver TRI-STATE Delay Test Circuit
Figure 16. Receiver TRI-STATE Delay Waveforms
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FUNCTION TABLES
Table 1. DS91D180/DS91C180 Transmitting(1)
Inputs Outputs
DE D Z Y
2.0V 2.0V L H
2.0V 0.8V H L
0.8V X Z Z
(1) X — Don't care condition
Z — High impedance state
Table 2. DS91D180 Receiving(1)
Inputs Output
RE A −B R
0.8V ≥+0.05V H
0.8V ≤ −0.05V L
0.8V 0V X
2.0V X Z
(1) X — Don't care condition
Z — High impedance state
Table 3. DS91C180 Receiving(1)
Inputs Output
RE A −B R
0.8V ≥+0.15V H
0.8V ≤+0.05V L
0.8V 0V L
2.0V X Z
(1) X — Don't care condition
Z — High impedance state
Table 4. DS91D180 Receiver Input Threshold Test Voltages(1)
Applied Voltages Resulting Differential Input Voltage Resulting Common-Mode Input Receiver Output
Voltage
VIA VIB VID VIC R
2.400V 0.000V 2.400V 1.200V H
0.000V 2.400V −2.400V 1.200V L
3.800V 3.750V 0.050V 3.775V H
3.750V 3.800V −0.050V 3.775V L
−1.400V −1.350V −0.050V −1.375V H
−1.350V −1.400V 0.050V −1.375V L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
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Table 5. DS91C180 Receiver Input Threshold Test Voltages(1)
Applied Voltages Resulting Differential Input Voltage Resulting Common-Mode Input Receiver Output
Voltage
VIA VIB VID VIC R
2.400V 0.000V 2.400V 1.200V H
0.000V 2.400V −2.400V 1.200V L
3.800V 3.650V 0.150V 3.725V H
3.800V 3.750V 0.050V 3.775V L
−1.250V −1.400V 0.150V −1.325V H
−1.350V −1.400V 0.050V −1.375V L
(1) H — High Level
L — Low Level
Output state assumes that the receiver is enabled (RE = L)
PIN DESCRIPTIONS
Pin No. Name Description
1, 8 NC No connect.
2 R Receiver output pin
3 RE Receiver enable pin: When RE is high, the receiver is disabled. When RE is low or open, the
receiver is enabled.
4 DE Driver enable pin: When DE is low, the driver is disabled. When DE is high, the driver is enabled.
5 D Driver input pin
6, 7 GND Ground pin
9 Y Non-inverting driver output pin
10 Z Inverting driver output pin
11 B Inverting receiver input pin
12 A Non-inverting receiver input pin
13, 14 VCC Power supply pin, +3.3V ± 0.3V
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REVISION HISTORY
Changes from Revision L (April 2013) to Revision M Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS91C180TMA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS91C180
TMA
DS91C180TMAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS91C180
TMA
DS91D180TMA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS91D180
TMA
DS91D180TMAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 DS91D180
TMA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 26-Aug-2017
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS91C180TMAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
DS91D180TMAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS91C180TMAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
DS91D180TMAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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