R5F6417BHDFB - Renesas Electronics

RENESAS MCU

M16C Family / R32C/100 Series

Rev.1.20 Feb 2013

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest informaton published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

User's Manual

www.renesas.com

R32C/117 Group

User’s Manual: Hardware

R32C/117 Group User’s Manual: Hardware

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of

semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,

and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you

or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics

does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages

incurred by you resulting from errors in or omissions from the information included herein.

3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of

thir d parties by or ari s ing from t he use of Renesas Electro nics products or technical information described in this document. No

license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of

Renesas Electronics or others.

4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,

modification, copy or otherwise misappropriation of Renesas Electronics product.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The

recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-

crime systems; and safety equipment etc.

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to

human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property

damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas

Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any

application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred

by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas

Electronics.

6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,

especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or

damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have

specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,

Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to

guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas

Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and

malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation

of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by

you.

8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility

of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and

regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive.

Renesas Electronics assume s no liability for damages or losse s occurring as a result of your noncompliance with applicable laws

and regulations.

9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose

manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use

Renesas Electronics products or technology described in this document for any purpose relating to military applications or use

by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas

Electronics products or technology described in this document, you should comply with the applicable export control laws and

regulations and follow the procedures required by such laws and regulations.

10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise

places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this

document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of

unauthorized use of Renesas Electronics products.

11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas

Electronics.

12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document

or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-

owned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

About This Manual

1. Purpose and Target User

This manual is designed to be read primarily by application developers who have an understanding of this

microcomputer (MCU) including its hardware functions and electrical characteristics. The user should have

a basic understanding of electric circuits, logic circuits and, MCUs.

This manual consists of 29 chapters covering six main categories: Overview, CPU, System Control,

Peripherals, Electrical Characteristics, and Usage Notes.

The R32C/117 Group includes the documents listed below. Verify this manual is the latest version by visiting

the Renesas Electronics website.

Carefully read all notes in this document prior to use. Notes are found throughout each chapter, at the end

of each chapter, and in the dedicated Usage Notes chapter.

The Revision History at the end of this manual summarizes primary modifications and additions to the

previous versions. For details, please refer to the relative chapters or sections of this manual.

Type of Document Contents Document Name Document Number

Datasheet Overview of Hardware and Electrical

Characteristics

R32C/117 Group

Datasheet

R01DS0064EJ0120

User’s Manual:

Hardware

Specifications and detailed

descriptions of:

-pin layout

-memory map

-peripherals

-electrical characteristics

-timing characteristics

Refer to the Application Manual for

peripheral usage.

R32C/117 Group

User’s Manual:

Hardware

This publication

User’s Manual:

Software/Software

Manual

Descriptions of instruction set R32C/100 Series

Software Manual

REJ09B0267-0100

Application Note -Usages

-Applications

-Sample programs

-Programing technics using

Assembly language or C

programming language

Available on the Renesas Electronics

website.

Renesas Technical

Update

Bulletins on product specifications,

documents, etc.

2. Numbers and Symbols

The following explains the denotations used in this manual for registers, bits, pins and various numbers.

(1) Registers, bits, and pins

Registers, bits, and pins are indicated by symbols. Each symbol has a register/bit/pin identifier

after the symbol.

Example: PM03 bit in the PM0 register

P3_5 pin, VCC pin

(2) Numbers

A binary number has the suffix “b” except for a 1-bit value.

A hexadecimal number has the suffix “h”.

A decimal number has no suffix.

Example: Binary notation: 11b

Hexadecimal notation: EFA0h

Decimal notation: 1234

3. Registers

The following illustration describes registers used throughout this manual.

• • • Register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol

• • • •

Address

• • • h

Reset Value

• • • • • b

Bit Symbol Bit Name Function RW

Blank box: Set this bit to 0 or 1 according to the function.

0: Set this bit to 0.

1: Set this bit to 1.

X: Nothing is assigned to this bit.

RW: Read and write

RO: Read only

WO: Write only (the read value is undefined)

—: Not applicable

0 1

• • • 0

• • • 1

—

(b2)

—

(b3)

—

(b4)

• • • 5

• • • 6

• • • 7

—

• • • Bit

No register bit. If necessary, set to 0. When read, the read value is

undefined.

Reserved Should be written with 1

• • • Bit

• • • Flag

Reserved

0: • • • • •

1: • • • • •

Functions vary with operating modes

Should be written with 0 and read as

undefined value

Reserved bit: This bit field is reserved. Set this bit to a specified value. For RW bits, the written value is

read unless otherwise noted.

No register bit(s): No register bit(s) is/are assigned to this field. If necessary, set to 0 for possible future

implementation.

Do not use this combination: Proper operation is not guaranteed when this value is set.

Functions vary with operating modes: Functions vary with peripheral operating modes. Refer to register

illustrations of the respective mode.

b2 b1

0 0 : • • • • •

0 1 : • • • • •

1 0 : Do not use this combination

1 1 : • • • • •

4. Abbreviations and Acronyms

The following acronyms and terms are used throughout this manual.

All trademarks and registered trademarks are the property of their respective owners.

Abbreviation/Acronym Meaning

ACIA Asynchronous Communications Interface Adapter

bps bits per second

CRC Cyclic Redundancy Check

DMA Direct Memory Access

DMAC Direct Memory Access Controller

GSM Global System for Mobile Communications

Hi-Z High Impedance

IEBus Inter Equipment Bus

I/O Input/Output

IrDA Infrared Data Association

LSB Least Significant Bit

MSB Most Significant Bit

NC Non-Connection

PLL Phase Locked Loop

PWM Pulse Width Modulation

SIM Subscriber Identity Module

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

A- 1
TABLE OF CONTENTS
Overview 1
1 Features........................................................................................................................................... 1
1.1 Applications .............................................................................................................................. 1
1.2 Performance Overview ............................................................................................................. 2
2 Product Information ......................................................................................................................... 6
3 Block Diagram ................................................................................................................................. 9
4 Pin Assignments ............................................................................................................................ 10
5 Pin Definitions and Functions ........................................................................................................ 19
Central Processing Unit (CPU) 24
1 General Purpose Registers ........................................................................................................... 25
1.1 Data Registers (R2R0, R3R1, R6R4, and R7R5)................................................................... 25
1.2 Address Registers (A0, A1, A2, and A3) ................................................................................ 25
1.3 Static Base Register (SB) ....................................................................................................... 25
1.4 Frame Base Register (FB)...................................................................................................... 25
1.5 Program Counter (PC)............................................................................................................ 25
1.6 Interrupt Vector Table Base Register (INTB) .......................................................................... 25
1.7 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) .................................................. 25
1.8 Flag Register (FLG)................................................................................................................ 25
2 Fast Interrupt Registers ................................................................................................................. 27
2.1 Save Flag Register (SVF)....................................................................................................... 27
2.2 Save PC Register (SVP) ........................................................................................................ 27
2.3 Vector Register (VCT) ............................................................................................................ 27
3 DMAC-associated Registers.......................................................................................................... 27
3.1 DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3) .................................................... 27
3.2 DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3) ........................................ 27
3.3 DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3) .......................... 27
3.4 DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3) ....................................... 27
3.5 DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3).......................... 27
3.6 DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3) ............................... 27
3.7 DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and DDR3) .................. 27
Memory 28
Special Function Registers (SFRs) 29
Resets 68
1 Hardware Reset............................................................................................................................. 68
2 Software Reset .............................................................................................................................. 71
3 Watchdog Timer Reset .................................................................................................................. 71
4 Reset Vector .................................................................................................................................. 71

A- 2
Power Management 72
1 Voltage Regulators for Internal Logic............................................................................................. 72
1.1 Decoupling Capacitor ............................................................................................................. 73
2 Low Voltage Detector..................................................................................................................... 74
2.1 Operational State of Low Voltage Detector............................................................................. 77
2.2 Low Voltage Detection Interrupt ............................................................................................. 77
2.3 Application Example of the Low Voltage Detector .................................................................. 78
Processor Mode 79
1 Types of Processor Modes ............................................................................................................ 79
2 Processor Mode Setting ................................................................................................................ 79
Clock Generator 82
1 Clock Generator Types .................................................................................................................. 82
1.1 Main Clock.............................................................................................................................. 91
1.2 Sub Clock (fC) ........................................................................................................................ 92
1.3 PLL Clock ............................................................................................................................... 93
1.4 On-chip Oscillator Clock ......................................................................................................... 96
2 Oscillator Stop Detection ............................................................................................................... 97
2.1 How to Use Oscillator Stop Detection..................................................................................... 97
3 Base Clock..................................................................................................................................... 97
4 CPU Clock and Peripheral Bus Clock............................................................................................ 98
5 Peripheral Clock ............................................................................................................................ 98
6 Clock Output Function ................................................................................................................... 99
7 Power Control .............................................................................................................................. 100
7.1 Normal Operating Mode ....................................................................................................... 101
7.2 Wait Mode............................................................................................................................. 106
7.3 Stop Mode ............................................................................................................................ 109
8 System Clock Protection...............................................................................................................111
9 Notes on Clock Generator ............................................................................................................112
9.1 Sub Clock ..............................................................................................................................112
9.2 Power Control........................................................................................................................112
Bus 113
1 Bus Settings..................................................................................................................................113
2 Peripheral Bus Timing Setting ......................................................................................................114
3 External Bus Setting .....................................................................................................................115
3.1 External Address Space Setting ............................................................................................115
3.2 External Data Bus Width Setting .......................................................................................... 121
3.3 Separate Bus/Multiplexed Bus Selection.............................................................................. 123
3.4 Read and Write Signals........................................................................................................ 126
3.5 External Bus Timing.............................................................................................................. 128

A- 3
3.6 ALE Signal............................................................................................................................ 132
3.7 RDY Signal ........................................................................................................................... 133
3.8 HOLD Signal......................................................................................................................... 136
3.9 BCLK Output ........................................................................................................................ 136
4 External Bus State when Accessing Internal Space .................................................................... 136
5 Notes on Bus ............................................................................................................................... 137
5.1 Notes on Designing a System .............................................................................................. 137
5.2 Notes on Register Settings................................................................................................... 137
Protection 138
1 Protect Register (PRCR Register) ............................................................................................... 138
2 Protect Register 2 (PRCR2 Register) .......................................................................................... 139
3 Protect Register 3 (PRCR3 Register) .......................................................................................... 139
4 Protect Release Register (PRR Register) ................................................................................... 140
Interrupts 141
1 Interrupt Types............................................................................................................................. 141
2 Software Interrupts ...................................................................................................................... 142
3 Hardware Interrupts ..................................................................................................................... 143
3.1 Special Interrupts.................................................................................................................. 143
3.2 Peripheral Interrupts ............................................................................................................. 143
4 Fast Interrupt ............................................................................................................................... 144
5 Interrupt Vectors .......................................................................................................................... 144
5.1 Fixed Vector Table ................................................................................................................ 145
5.2 Relocatable Vector Table...................................................................................................... 145
6 Interrupt Request Acceptance ..................................................................................................... 150
6.1 I Flag and IPL ....................................................................................................................... 150
6.2 Interrupt Control Registers ................................................................................................... 151
6.3 Wake-up IPL Setting Register .............................................................................................. 154
6.4 Interrupt Sequence ............................................................................................................... 155
6.5 Interrupt Response Time ...................................................................................................... 156
6.6 IPL after Accepting an Interrupt Request ............................................................................. 157
6.7 Register Saving .................................................................................................................... 157
7 Register Restoring from Interrupt Handler................................................................................... 158
8 Interrupt Priority ........................................................................................................................... 158
9 Priority Resolver .......................................................................................................................... 158
10 External Interrupt ......................................................................................................................... 160
11 NMI .............................................................................................................................................. 161
12 Key Input Interrupt ....................................................................................................................... 162
13 Intelligent I/O Interrupt ................................................................................................................. 163
14 Notes on Interrupts ...................................................................................................................... 166
14.1 ISP Setting............................................................................................................................ 166

A- 4
14.2 NMI ....................................................................................................................................... 166
14.3 External Interrupts ................................................................................................................ 166
Watchdog Timer 167
DMAC 169
1 Transfer Cycle.............................................................................................................................. 178
1.1 Effect of Transfer Address and Data Bus Width ................................................................... 178
1.2 Effect of Bus Timing.............................................................................................................. 179
1.3 Effect of RDY Signal............................................................................................................. 179
2 DMA Transfer Cycle..................................................................................................................... 181
3 Channel Priority and DMA Transfer Timing ................................................................................. 182
4 Notes on DMAC........................................................................................................................... 183
4.1 DMAC-associated Register Settings .................................................................................... 183
4.2 Reading DMAC-associated Registers .................................................................................. 183
DMAC II 184
1 DMAC II Settings ......................................................................................................................... 184
1.1 Registers RIPL1 and RIPL2 ................................................................................................. 185
1.2 DMAC II Index ...................................................................................................................... 186
1.3 Interrupt Control Register of the Peripherals ........................................................................ 189
1.4 Relocatable Vector Table of the Peripherals......................................................................... 189
1.5 IRLT Bit in the IIOiIE Register (i = 0 to 11)............................................................................ 189
2 DMAC II Operation ...................................................................................................................... 189
3 Transfer Types ............................................................................................................................. 189
3.1 Memory-to-memory Transfer ................................................................................................ 189
3.2 Immediate Data Transfer ...................................................................................................... 190
3.3 Calculation Result Transfer .................................................................................................. 190
4 Transfer Modes............................................................................................................................ 190
4.1 Single Transfer ..................................................................................................................... 190
4.2 Burst Transfer ....................................................................................................................... 190
4.3 Multiple Transfer ................................................................................................................... 190
5 Chain Transfer ............................................................................................................................. 191
6 DMA II Transfer Complete Interrupt............................................................................................. 191
7 Execution Time ............................................................................................................................ 192
Programmable I/O Ports 193
1 Port Pi Register (Pi register, i = 0 to 15) ...................................................................................... 195
Timers 196
1 Timer A ........................................................................................................................................ 198
1.1 Timer Mode........................................................................................................................... 205
1.2 Event Counter Mode............................................................................................................. 207

A- 5
1.3 One-shot Timer Mode............................................................................................................211
1.4 Pulse-width Modulation Mode............................................................................................... 213
2 Timer B ........................................................................................................................................ 216
2.1 Timer Mode........................................................................................................................... 219
2.2 Event Counter Mode............................................................................................................. 221
2.3 Pulse Period/Pulse-width Measure Mode............................................................................. 223
3 Notes on Timers........................................................................................................................... 226
3.1 Timer A and Timer B............................................................................................................. 226
3.2 Timer A ................................................................................................................................. 226
3.3 Timer B ................................................................................................................................. 228
Three-phase Motor Control Timers 229
1 Modulation Modes of Three-phase Motor Control Timers ........................................................... 236
2 Timer B2 ...................................................................................................................................... 237
3 Timers A4, A1, and A2................................................................................................................. 239
4 Simultaneous Conduction Prevention and Dead Time Timer ...................................................... 242
5 Three-phase Motor Control Timer Operation............................................................................... 243
6 Notes on Three-phase Motor Control Timers .............................................................................. 246
6.1 Shutdown.............................................................................................................................. 246
6.2 Register Setting .................................................................................................................... 246
Serial Interface 247
1 Synchronous Serial Interface Mode............................................................................................. 264
1.1 Reset Procedure on Transmit/Receive Error........................................................................ 269
1.2 CLK Polarity.......................................................................................................................... 269
1.3 LSB First and MSB First Selection ....................................................................................... 270
1.4 Continuous Receive Mode ................................................................................................... 270
1.5 Serial Data Logic Inversion................................................................................................... 271
1.6 CTS/RTS Function................................................................................................................ 271
2 Asynchronous Serial Interface Mode (UART Mode).................................................................... 272
2.1 Bit Rate................................................................................................................................. 277
2.2 Reset Procedure on Transmit/Receive Error........................................................................ 278
2.3 LSB First and MSB First Selection ....................................................................................... 278
2.4 Serial Data Logic Inversion................................................................................................... 279
2.5 TXD and RXD I/O Polarity Inversion .................................................................................... 280
2.6 CTS/RTS Function................................................................................................................ 280
3 Special Mode 1 (I2C Mode).......................................................................................................... 281
3.1 START Condition and STOP Condition Detection................................................................ 287
3.2 START Condition and STOP Condition Generation ............................................................. 287
3.3 Arbitration ............................................................................................................................. 288
3.4 SCL Control and Clock Synchronization .............................................................................. 289
3.5 SDA Output .......................................................................................................................... 291

A- 6
3.6 SDA Input ............................................................................................................................. 291
3.7 Acknowledge ........................................................................................................................ 291
3.8 Transmit/Receive Operation Reset....................................................................................... 291
4 Special Mode 2 ............................................................................................................................ 292
4.1 SSi Input Pin Function (i = 0 to 6)......................................................................................... 294
4.2 Clock Phase Setting ............................................................................................................. 295
5 Notes on Serial Interface ............................................................................................................. 297
5.1 Changing the UiBRG Register (i = 0 to 8) ............................................................................ 297
5.2 Synchronous Serial Interface Mode ..................................................................................... 297
5.3 Special Mode 1 (I2C Mode) .................................................................................................. 297
5.4 Reset Procedure on Communication Error........................................................................... 298
A/D Converter 299
1 Mode Descriptions ....................................................................................................................... 307
1.1 One-shot Mode..................................................................................................................... 307
1.2 Repeat Mode ........................................................................................................................ 308
1.3 Single Sweep Mode.............................................................................................................. 309
1.4 Repeat Sweep Mode 0 ......................................................................................................... 310
1.5 Repeat Sweep Mode 1 ..........................................................................................................311
1.6 Multi-port Single Sweep Mode.............................................................................................. 312
1.7 Multi-port Repeat Sweep Mode 0 ......................................................................................... 313
2 Functions ..................................................................................................................................... 314
2.1 Resolution Selection............................................................................................................. 314
2.2 Sample and Hold Function ................................................................................................... 314
2.3 Trigger Selection................................................................................................................... 314
2.4 DMAC Operating Mode ........................................................................................................ 314
2.5 Function-extended Analog Input Pins................................................................................... 315
2.6 External Operating Amplifier (Op-Amp) Connection Mode................................................... 315
2.7 Power Saving ....................................................................................................................... 316
2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion .............................. 316
3 Notes on A/D Converter............................................................................................................... 318
3.1 Notes on Designing Boards.................................................................................................. 318
3.2 Notes on Programming......................................................................................................... 319
D/A Converter 320
CRC Calculator 322
X-Y Conversion 325
1 Data Conversion When Reading ................................................................................................. 326
2 Data Conversion When Writing.................................................................................................... 328

A- 7
Intelligent I/O 329
1 Base Timer for Groups 0 to 2....................................................................................................... 344
2 Time Measurement for Groups 0 and 1 ....................................................................................... 350
3 Waveform Generation for Groups 0 to 2...................................................................................... 354
3.1 Single-phase Waveform Output Mode for Groups 0 to 2...................................................... 355
3.2 Inverted Waveform Output Mode for Groups 0 to 2.............................................................. 357
3.3 Set/Reset Waveform Output Mode (SR Waveform Output Mode) for Groups 0 to 2 ........... 359
3.4 Bit Modulation PWM Output Mode for Group 2 .................................................................... 362
3.5 Real-time Port Output Mode (RTP Output Mode) for Group 2 ............................................. 364
3.6 Parallel Real-time Port Output Mode (RTP Output Mode) for Group 2 ................................ 366
4 Group 2 Serial Interface............................................................................................................... 368
4.1 Variable Synchronous Serial Interface Mode for Group 2 .................................................... 373
Multi-master I2C-bus Interface 376
1 Multi-master I2C-bus Interface-associated Registers .................................................................. 378
1.1 I2C-bus Transmit/Receive Shift Register (I2CTRSR) ........................................................... 378
1.2 I2C-bus Slave Address Register (I2CSAR) .......................................................................... 379
1.3 I2C-bus Control Register 0 (I2CCR0) ................................................................................... 380
1.4 I2C-bus Clock Control Register (I2CCCR)............................................................................ 382
1.5 I2C-bus START and STOP Conditions Control Register (I2CSSCR) ................................... 384
1.6 I2C-bus Control Register 1 (I2CCR1) ................................................................................... 385
1.7 I2C-bus Control Register 2 (I2CCR2) ................................................................................... 388
1.8 I2C-bus Status Register (I2CSR) .......................................................................................... 390
1.9 I2C-bus Mode Register (I2CMR) .......................................................................................... 394
2 Generating a START Condition ................................................................................................... 395
3 Generating a STOP Condition ..................................................................................................... 397
4 START Condition Redundancy Prevention Function ................................................................... 398
5 Detecting START and STOP Conditions ..................................................................................... 399
6 Data Transmission and Reception............................................................................................... 401
6.1 Master Transmission ............................................................................................................ 402
6.2 Slave Reception ................................................................................................................... 403
7 Notes on Using Multi-master I2C-bus Interface ........................................................................... 404
7.1 Accessing Multi-master I2C-bus Interface-associated Registers.......................................... 404
7.2 Generating a Repeated START condition ............................................................................ 406
CAN Module 407
1 CAN SFRs ................................................................................................................................... 410
1.1 CAN0 Control Register (C0CTLR) ........................................................................................411
1.2 CAN0 Clock Select Register (C0CLKR)  .............................................................................. 415
1.3 CAN0 Bit Configuration Register (C0BCR)  ......................................................................... 416
1.4 CAN0 Mask Register k (C0MKRk) (k = 0 to 7) ..................................................................... 418
1.5 CAN0 FIFO Received ID Compare Register n (C0FIDCR0 and C0FIDCR1) 

A- 8
(n = 0, 1) ............................................................................................................................... 419
1.6 CAN0 Mask Invalid Register (C0MKIVLR) .......................................................................... 421
1.7 CAN0 Mailbox (C0MBj) (j = 0 to 31) ..................................................................................... 422
1.8 CAN0 Mailbox Interrupt Enable Register (C0MIER) ............................................................ 426
1.9 CAN0 Message Control Register j (C0MCTLj) (j = 0 to 31).................................................. 427
1.10 CAN0 Receive FIFO Control Register (C0RFCR)  ............................................................... 430
1.11 CAN0 Receive FIFO Pointer Control Register (C0RFPCR)  ................................................ 433
1.12 CAN0 Transmit FIFO Control Register (C0TFCR) .............................................................. 434
1.13 CAN0 Transmit FIFO Pointer Control Register (C0TFPCR) ................................................ 436
1.14 CAN0 Status Register (C0STR)  .......................................................................................... 437
1.15 CAN0 Mailbox Search Mode Register (C0MSMR)  .............................................................. 440
1.16 CAN0 Mailbox Search Status Register (C0MSSR)  ............................................................. 441
1.17 CAN0 Channel Search Support Register (C0CSSR)  .......................................................... 443
1.18 CAN0 Acceptance Filter Support Register (C0AFSR) ......................................................... 444
1.19 CAN0 Error Interrupt Enable Register (C0EIER) ................................................................. 445
1.20 CAN0 Error Interrupt Factor Judge Register (C0EIFR)  ....................................................... 447
1.21 CAN0 Receive Error Count Register (C0RECR) ................................................................. 450
1.22 CAN0 Transmit Error Count Register (C0TECR)  ................................................................ 451
1.23 CAN0 Error Code Store Register (C0ECSR) ....................................................................... 452
1.24 CAN0 Time Stamp Register (C0TSR)  ................................................................................. 454
1.25 CAN0 Test Control Register (C0TCR) ................................................................................. 455
2 Operating Modes ......................................................................................................................... 458
2.1 CAN Reset Mode.................................................................................................................. 459
2.2 CAN Halt Mode..................................................................................................................... 460
2.3 CAN Sleep Mode.................................................................................................................. 461
2.4 CAN Operation Mode (Excluding Bus-off State)................................................................... 462
2.5 CAN Operation Mode (Bus-off State) ................................................................................... 463
3 CAN Communication Speed Configuration.................................................................................. 464
3.1 CAN Clock Configuration...................................................................................................... 464
3.2 Bit Timing Configuration ....................................................................................................... 464
3.3 Bit rate .................................................................................................................................. 465
4 Mailbox and Mask Register Structure .......................................................................................... 466
5 Acceptance Filtering and Masking Function ................................................................................ 468
6 Reception and Transmission ....................................................................................................... 471
6.1 Reception ............................................................................................................................. 472
6.2 Transmission ........................................................................................................................ 474
7 CAN Interrupts ............................................................................................................................. 475
I/O Pins 476
1 Port Pi Direction Register (PDi Register, i = 0 to 15) ................................................................... 477
2 Output Function Select Registers ................................................................................................ 478

A- 9
3 Input Function Select Registers................................................................................................... 496
4 Pull-up Control Registers 0 to 4 (Registers PUR0 to PUR4) ....................................................... 501
5 Port Control Register (PCR Register).......................................................................................... 504
6 Configuring Unused Pins ............................................................................................................. 505
Flash Memory 508
1 Overview...................................................................................................................................... 508
2 Flash Memory Protection............................................................................................................. 510
2.1 Lock Bit Protection................................................................................................................ 510
2.2 ROM Code Protection .......................................................................................................... 510
2.3 ID Code Protection ................................................................................................................511
2.4 Forcible Erase Function........................................................................................................ 512
2.5 Standard Serial I/O Mode Disable Function ......................................................................... 513
3 CPU Rewrite Mode ...................................................................................................................... 514
3.1 CPU Operating Mode and Flash Memory Rewrite ............................................................... 522
3.2 Flash Memory Rewrite Bus Timing....................................................................................... 523
3.3 Software Commands ............................................................................................................ 527
3.4 Mode Transition .................................................................................................................... 528
3.5 Issuing Software Commands................................................................................................ 529
3.6 Status Check ........................................................................................................................ 535
4 Standard Serial I/O Mode ............................................................................................................ 536
5 Parallel I/O mode ......................................................................................................................... 539
6 Notes on Flash Memory Rewriting............................................................................................... 540
6.1 Note on Power Supply.......................................................................................................... 540
6.2 Note on Hardware Reset ...................................................................................................... 540
6.3 Note on Flash Memory Protection ........................................................................................ 540
6.4 Notes on Programming......................................................................................................... 540
6.5 Notes on Interrupts ............................................................................................................... 540
6.6 Notes on Rewrite Control Program....................................................................................... 541
6.7 Notes on Number of Program/Erase Cycles and Software Command Execution Time ....... 541
6.8 Other Notes .......................................................................................................................... 541
Electrical Characteristics 542
Usage Notes 583
1 Notes on Board Designing........................................................................................................... 583
1.1 Power Supply Pins ............................................................................................................... 583
1.2 Supply Voltage...................................................................................................................... 583
2 Notes on Register Setting............................................................................................................ 584
2.1 Registers with Write-only Bits ............................................................................................... 584
3 Notes on Clock Generator ........................................................................................................... 586
3.1 Sub Clock ............................................................................................................................. 586

A- 10
3.2 Power Control....................................................................................................................... 586
4 Notes on Bus ............................................................................................................................... 587
4.1 Notes on Designing a System .............................................................................................. 587
4.2 Notes on Register Settings................................................................................................... 587
5 Notes on Interrupts ...................................................................................................................... 588
5.1 ISP Setting............................................................................................................................ 588
5.2 NMI ....................................................................................................................................... 588
5.3 External Interrupts ................................................................................................................ 588
6 Notes on DMAC........................................................................................................................... 589
6.1 DMAC-associated Register Settings .................................................................................... 589
6.2 Reading DMAC-associated Registers .................................................................................. 589
7 Notes on Timers........................................................................................................................... 590
7.1 Timer A and Timer B............................................................................................................. 590
7.2 Timer A ................................................................................................................................. 590
7.3 Timer B ................................................................................................................................. 592
8 Notes on Three-phase Motor Control Timers .............................................................................. 593
8.1 Shutdown.............................................................................................................................. 593
8.2 Register Setting .................................................................................................................... 593
9 Notes on Serial Interface ............................................................................................................. 594
9.1 Changing the UiBRG Register (i = 0 to 8) ............................................................................ 594
9.2 Synchronous Serial Interface Mode ..................................................................................... 594
9.3 Special Mode 1 (I2C Mode) .................................................................................................. 594
9.4 Reset Procedure on Communication Error........................................................................... 595
10 Notes on A/D Converter............................................................................................................... 596
10.1 Notes on Designing Boards.................................................................................................. 596
10.2 Notes on Programming......................................................................................................... 597
11 Notes on Flash Memory Rewriting............................................................................................... 598
11.1 Note on Power Supply.......................................................................................................... 598
11.2 Note on Hardware Reset ...................................................................................................... 598
11.3 Note on Flash Memory Protection ........................................................................................ 598
11.4 Notes on Programming......................................................................................................... 598
11.5 Notes on Interrupts ............................................................................................................... 598
11.6 Notes on Rewrite Control Program....................................................................................... 599
11.7 Notes on Number of Program/Erase Cycles and Software Command Execution Time ....... 599
11.8 Other Notes .......................................................................................................................... 599
Appendix 1. Package Dimensions 600
INDEX 601

R01UH0211EJ0120 Rev.1.20 Page 1 of 604

Feb 18, 2013

R32C/117 Group

RENESAS MCU

R01UH0211EJ0120

Rev.1.20

Feb 18, 2013

1. Overview

1.1 Features

The M16C Family offers a robust platform of 32-/16-bit CISC microcomputers (MCUs) featuring high ROM

code efficiency, extensive EMI/EMS noise immunity, ultra-low power consumption, high-speed processing

in actual applications, and numerous and varied integrated peripherals. Extensive device scalability from

low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral

functions, provides support for a vast range of application fields.

The R32C/100 Series is a high-end microcontroller series in the M16C Family. With a 4-Gbyte memory

space, it achieves maximum code efficiency and high-speed processing with 32-bit CISC architecture,

multiplier, multiply-accumulate unit, and floating point unit. The selection from the broadest choice of on-

chip peripheral devices — UART, CRC, DMAC, A/D and D/A converters, timers, I2C, and watchdog timer

enables to minimize external components.

The R32C/117 Group is the standard MCU within the R32C/100 Series. This product, provided as 100-pin

and 144-pin plastic molded LQFP packages, has nine channels of serial interface, one channel of multi-

master I2C-bus interface, and one channel of CAN module.

1.1.1 Applications

Car audio, audio, printer, office/industrial equipment, etc.

R01UH0211EJ0120 Rev.1.20 Page 2 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

1.1.2 Performance Overview

Tables 1.1 to 1.4 list the performance overview of the R32C/117 Group.

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 1.1 Performance Overview for the 144-pin Package (1/2)

Unit Function Explanation

CPU Central

processing unit

R32C/100 Series CPU Core

• Basic instructions: 108

• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)

• Multiplier: 32-bit × 32-bit  64-bit

• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit  64-bit

• IEEE-754 compatible FPU: Single precision

• 32-bit barrel shifter

• Operating mode: Single-chip mode, memory expansion mode,

microprocessor mode (optional (1))

Memory Flash memory: 384 Kbytes to 1 Mbyte

RAM: 40 K/48 K/63 Kbytes

Data flash: 4 Kbytes × 2 blocks

Refer to Table 1.5 for each product’s memory size

Voltage

Detector

Low voltage

detector

Optional (1)

Low voltage detection interrupt

Clock Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator)

• Oscillation stop detector: Main clock oscillator stop/restart detection

• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable

• Low power modes: Wait mode, stop mode

External Bus

Expansion

Bus and memory

expansion

• Address space: 4 Gbytes (of which up to 64 Mbytes is user

accessible)

• External bus Interface: Support for wait-state insertion, 4 chip select

outputs

• Bus format: Separate bus/Multiplexed bus selectable, data bus width

selectable (8/16/32 bits)

Interrupts Interrupt vectors: 261

External interrupt inputs: NMI, INT × 9, key input × 4

Interrupt priority levels: 7

Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output)

DMA DMAC 4 channels

• Cycle-steal transfer mode

• Request sources: 57

• 2 transfer modes: Single transfer, repeat transfer

DMAC II • Triggered by an interrupt request of any peripheral

• 3 characteristic transfer functions: Immediate data transfer,

calculation result transfer, chain transfer

I/O Ports Programmable

I/O ports

• 2 input-only ports

• 120 CMOS I/O ports (of which 32 are 5 V tolerant)

• A pull-up resistor is selectable for every 4 input ports (except 5 V

tolerant inputs)

R01UH0211EJ0120 Rev.1.20 Page 3 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 1.2 Performance Overview for the 144-pin Package (2/2)

Unit Function Explanation

Timer Timer A 16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-

phase encoder input) × 3

Timer B 16-bit timer × 6

Timer mode, event counter mode, pulse frequency measurement

mode, pulse-width measurement mode

Three-phase

motor control

timer

Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

8-bit programmable dead time timer

Serial

Interface

UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels

•I

2C-bus (UART0 to UART6)

• Special mode 2 (UART0 to UART6)

• IEBus (optional (1)) (UART0 to UART6)

A/D Converter 10-bit resolution × 34 channels

Sample and hold functionality integrated

D/A Converter 8-bit resolution × 2

CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1)

X-Y Converter 16 bits × 16 bits

Intelligent I/O Time measurement (input capture): 16 bits × 16

Waveform generation (output compare): 16 bits × 24

Serial interface: Variable-length synchronous serial I/O mode, IEBus

mode (optional (1))

Multi-master I2C-bus Interface 1 channel

CAN Module 1 channel

CAN functionality compliant with ISO 11898-1

32 mailboxes

Flash Memory Programming and erasure supply voltage: VCC = 3.0 to 5.5 V

Minimum endurance: 1,000 program/erase cycles

Security protection: ROM code protect, ID code protect

Debugging: On-chip debug, on-board flash programming

Operating Frequency/Supply

Voltage

64 MHz (high speed version)/VCC = 3.0 to 5.5 V

50 MHz (normal speed version)/VCC = 3.0 to 5.5 V

Operating Temperature -20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

Current Consumption 45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)

35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)

8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)

Package 144-pin plastic molded LQFP (PLQP0144KA-A)

R01UH0211EJ0120 Rev.1.20 Page 4 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 1.3 Performance Overview for the 100-pin Package (1/2)

Unit Function Explanation

CPU Central

processing unit

R32C/100 Series CPU Core

• Basic instructions: 108

• Minimum instruction execution time: 15.625 ns (f(CPU) = 64 MHz)

• Multiplier: 32-bit × 32-bit  64-bit

• Multiply-accumulate unit: 32-bit × 32-bit + 64-bit  64-bit

• IEEE-754 compatible FPU: Single precision

• 32-bit barrel shifter

• Operating mode: Single-chip mode, memory expansion mode,

microprocessor mode (optional (1))

Memory Flash memory: 128 Kbytes to 1 Mbyte

RAM: 20 K/40 K/48 K/63 Kbytes

Data flash: 4 Kbytes × 2 blocks

Refer to Table 1.5 for each product’s memory size

Voltage

Detector

Low voltage

detector

Optional (1)

Low voltage detection interrupt

Clock Clock generator • 4 circuits (main clock, sub clock, PLL, on-chip oscillator)

• Oscillation stop detector: Main clock oscillator stop/restart detection

• Frequency divide circuit: Divide-by-2 to divide-by-24 selectable

• Low power modes: Wait mode, stop mode

External Bus

Expansion

Bus and memory

expansion

• Address space: 4 Gbytes (of which up to 64 Mbytes is user

accessible)

• External bus Interface: Support for wait-state insertion, 4 chip select

outputs

• Bus format: Separate bus/Multiplexed bus selectable, data bus width

selectable (8/16 bits)

Interrupts Interrupt vectors: 261

External interrupt inputs: NMI, INT × 6, key input × 4

Interrupt priority levels: 7

Watchdog Timer 15 bits × 1 (selectable input frequency from prescaler output)

DMA DMAC 4 channels

• Cycle-steal transfer mode

• Request sources: 51

• 2 transfer modes: Single transfer, repeat transfer

DMAC II • Triggered by an interrupt request of any peripheral

• 3 characteristic transfer functions: Immediate data transfer,

calculation result transfer, chain transfer

I/O Ports Programmable

I/O ports

• 2 input-only ports

• 84 CMOS I/O ports (of which 32 are 5 V tolerant)

• A pull-up resistor is selectable for every 4 input ports (except 5 V

tolerant inputs)

R01UH0211EJ0120 Rev.1.20 Page 5 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 1.4 Performance Overview for the 100-pin Package (2/2)

Unit Function Explanation

Timer Timer A 16-bit timer × 5

Timer mode, event counter mode, one-shot timer mode, pulse-width

modulation (PWM) mode

Two-phase pulse signal processing in event counter mode (two-

phase encoder input) × 3

Timer B 16-bit timer × 6

Timer mode, event counter mode, pulse frequency measurement

mode, pulse-width measurement mode

Three-phase

motor control

timer

Three-phase motor control timer × 1 (timers A1, A2, A4, and B2 used)

8-bit programmable dead time timer

Serial

Interface

UART0 to UART8 Asynchronous/synchronous serial interface × 9 channels

•I

2C-bus (UART0 to UART6)

• Special mode 2 (UART0 to UART6)

• IEBus (optional (1)) (UART0 to UART6)

A/D Converter 10-bit resolution × 26 channels

Sample and hold functionality integrated

D/A Converter 8-bit resolution × 2

CRC Calculator CRC-CCITT (X16 + X12 + X5 + 1)

X-Y Converter 16 bits × 16 bits

Intelligent I/O Time measurement (input capture): 16 bits × 16

Waveform generation (output compare): 16 bits × 19

Serial interface: Variable-length synchronous serial I/O mode, IEBus

mode (optional (1))

Multi-master I2C-bus Interface 1 channel

CAN Module 1 channel

CAN functionality compliant with ISO 11898-1

32 mailboxes

Flash Memory Programming and erasure supply voltage: VCC = 3.0 to 5.5 V

Minimum endurance: 1,000 program/erase cycles

Security protection: ROM code protect, ID code protect

Debugging: On-chip debug, on-board flash programming

Operating Frequency/Supply

Voltage

64 MHz (high speed version)/VCC = 3.0 to 5.5 V

50 MHz (normal speed version)/VCC = 3.0 to 5.5 V

Operating Temperature -20°C to 85°C (N version)

-40°C to 85°C (D version)

-40°C to 85°C (P version)

Current Consumption 45 mA (VCC = 5.0 V, f(CPU) = 64 MHz)

35 mA (VCC = 5.0 V, f(CPU) = 50 MHz)

8 µA (VCC = 3.3 V, f(XCIN) = 32.768 kHz, in wait mode)

Package 100-pin plastic molded LQFP (PLQP0100KB-A)

R01UH0211EJ0120 Rev.1.20 Page 6 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

1.2 Product Information

Tables 1.5 and 1.6 list the product information and Figure 1.1 shows the details of the part number.

Notes:

1. The old package codes are as follows:

PLQP0100KB-A: 100P6Q-A; PLQP0144KA-A: 144P6Q-A

2. “8 Kbytes” in the ROM capacity indicates the data flash memory capacity.

Table 1.5 R32C/117 Group Product List for Normal Speed Version (1/2) As of February, 2013

Part Number Package Code (1) ROM Capacity (2) RAM Capacity Remarks

R5F6417BNFB (P)

PLQP0100KB-A 128 Kbytes

+ 8 Kbytes

20 Kbytes

-20°C to 85°C (N version)

R5F6417BDFB -40°C to 85°C (D version)

R5F6417BPFB -40°C to 85°C (P version)

R5F6417ANFB (P)

PLQP0100KB-A 256 Kbytes

+ 8 Kbytes

-20°C to 85°C (N version)

R5F6417ADFB -40°C to 85°C (D version)

R5F6417APFB -40°C to 85°C (P version)

R5F64175NFD (P)

PLQP0144KA-A

384 Kbytes

+ 8 Kbytes

40 Kbytes

-20°C to 85°C (N version)

R5F64175DFD -40°C to 85°C (D version)

R5F64175PFD -40°C to 85°C (P version)

R5F64175NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64175DFB -40°C to 85°C (D version)

R5F64175PFB -40°C to 85°C (P version)

R5F64176NFD (P)

PLQP0144KA-A

512 Kbytes

+ 8 Kbytes

-20°C to 85°C (N version)

R5F64176DFD -40°C to 85°C (D version)

R5F64176PFD -40°C to 85°C (P version)

R5F64176NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64176DFB -40°C to 85°C (D version)

R5F64176PFB -40°C to 85°C (P version)

R5F64177NFD (P)

PLQP0144KA-A

640 Kbytes

+ 8 Kbytes 48 Kbytes

-20°C to 85°C (N version)

R5F64177DFD -40°C to 85°C (D version)

R5F64177PFD -40°C to 85°C (P version)

R5F64177NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64177DFB -40°C to 85°C (D version)

R5F64177PFB -40°C to 85°C (P version)

R5F64178NFD (P)

PLQP0144KA-A

768 Kbytes

+ 8 Kbytes

63 Kbytes

-20°C to 85°C (N version)

R5F64178DFD -40°C to 85°C (D version)

R5F64178PFD -40°C to 85°C (P version)

R5F64178NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64178DFB -40°C to 85°C (D version)

R5F64178PFB -40°C to 85°C (P version)

R5F64179NFD (P)

PLQP0144KA-A

1 Mbyte

+ 8 Kbytes

-20°C to 85°C (N version)

R5F64179DFD -40°C to 85°C (D version)

R5F64179PFD -40°C to 85°C (P version)

R5F64179NFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64179DFB -40°C to 85°C (D version)

R5F64179PFB -40°C to 85°C (P version)

(P): On planning phase

R01UH0211EJ0120 Rev.1.20 Page 7 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Notes:

1. The old package codes are as follows:

PLQP0100KB-A: 100P6Q-A; PLQP0144KA-A: 144P6Q-A

2. “8 Kbytes” in the ROM capacity indicates the data flash memory capacity.

Table 1.6 R32C/117 Group Product List for High Speed Version (2/2) As of February, 2013

Part Number Package Code (1) ROM Capacity (2) RAM Capacity Remarks

R5F6417BHNFB (P)

PLQP0100KB-A 128 Kbytes

+ 8 Kbytes

20 Kbytes

-20°C to 85°C (N version)

R5F6417BHDFB -40°C to 85°C (D version)

R5F6417BHPFB -40°C to 85°C (P version)

R5F6417AHNFB (P)

PLQP0100KB-A 256 Kbytes

+ 8 Kbytes

-20°C to 85°C (N version)

R5F6417AHDFB -40°C to 85°C (D version)

R5F6417AHPFB -40°C to 85°C (P version)

R5F64175HNFD (P)

PLQP0144KA-A

384 Kbytes

+ 8 Kbytes

40 Kbytes

-20°C to 85°C (N version)

R5F64175HDFD -40°C to 85°C (D version)

R5F64175HPFD -40°C to 85°C (P version)

R5F64175HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64175HDFB -40°C to 85°C (D version)

R5F64175HPFB -40°C to 85°C (P version)

R5F64176HNFD (P)

PLQP0144KA-A

512 Kbytes

+ 8 Kbytes

-20°C to 85°C (N version)

R5F64176HDFD -40°C to 85°C (D version)

R5F64176HPFD -40°C to 85°C (P version)

R5F64176HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64176HDFB -40°C to 85°C (D version)

R5F64176HPFB -40°C to 85°C (P version)

R5F64177HNFD (P)

PLQP0144KA-A

640 Kbytes

+ 8 Kbytes 48 Kbytes

-20°C to 85°C (N version)

R5F64177HDFD -40°C to 85°C (D version)

R5F64177HPFD -40°C to 85°C (P version)

R5F64177HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64177HDFB -40°C to 85°C (D version)

R5F64177HPFB -40°C to 85°C (P version)

R5F64178HNFD (P)

PLQP0144KA-A

768 Kbytes

+ 8 Kbytes

63 Kbytes

-20°C to 85°C (N version)

R5F64178HDFD -40°C to 85°C (D version)

R5F64178HPFD -40°C to 85°C (P version)

R5F64178HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64178HDFB -40°C to 85°C (D version)

R5F64178HPFB -40°C to 85°C (P version)

R5F64179HNFD (P)

PLQP0144KA-A

1 Mbyte

+ 8 Kbytes

-20°C to 85°C (N version)

R5F64179HDFD -40°C to 85°C (D version)

R5F64179HPFD -40°C to 85°C (P version)

R5F64179HNFB (P)

PLQP0100KB-A

-20°C to 85°C (N version)

R5F64179HDFB -40°C to 85°C (D version)

R5F64179HPFB -40°C to 85°C (P version)

(P): On planning phase

R01UH0211EJ0120 Rev.1.20 Page 8 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Figure 1.1 Part Numbering

Part Number

R5 F 64 17 9 H P XXX FD

Package Code

FB : PLQP0100KB-A

FD : PLQP0144KA-A

ROM Number

Omitted in the flash memory version

ROM/RAM Capacity

B : 128 KB/20 KB

A : 256 KB/20 KB

5 : 384 KB/40 KB

6 : 512 KB/40 KB

7 : 640 KB/48 KB

8 : 768 KB/63 KB

9 : 1 MB/63 KB

Temperature Code

N : -20°C to 85°C

D : -40°C to 85°C

P : -40°C to 85°C

Memory Type

F : Flash memory version

R32C/117 Group

R32C/100 Series

Rated Operating Frequency

H : 64 MHz (High speed version)

None : 50 MHz (Normal speed version)

R01UH0211EJ0120 Rev.1.20 Page 9 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

1.3 Block Diagram

Figure 1.2 shows the block diagram for the R32C/117 Group.

Figure 1.2 R32C/117 Group Block Diagram

Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6

8888888

Port P7 P8_5 Port P9 Port P10

8 7 8 (3) 8

Peripherals

Timers:

Timer A 16 bits × 5 timers

Timer B 16 bits × 6 timers

Three-phase motor

controller

Watchdog timer:

15 bits

D/A converter:

8 bits × 2 channels

A/D converter:

10 bits × 1 circuit

Standard: 10 inputs

Maximum: 34 inputs (1)

Serial interface:

9 channels X-Y converter:

16 bits × 16 bits

Clock generator:

4 circuits

- XIN-XOUT

- XCIN-XCOUT

- On-chip oscillator

- PLL frequency synthesizer

DMAC

CRC calculator (CCITT)

X16 + X12 + X5 + 1

Intelligent I/O

Time measurement: 16

Wave generation: 24 (2)

Serial interface:

- Variable-length

synchronous serial I/O

- IEBus

R32C/100 Series CPU Core

R2R0

R3R1

R6R4

R7R5

FLG

INTB

ISP

USP

SVF

SVP

VCT

R2R0

R3R1

R6R4

R7R5

Memory

ROM

RAM

Multiplier

Port P14 Port P14_1 Port P11Port P12Port P13

4 588

DMAC II

Floating-point unit

Port P8

Port P15

(Note 4)

Notes:

1. The 144-pin package has 34 inputs. The 100-pin package can have up to 26 inputs.

2. The 144-pin package has 24 outputs. The 100-pin package has 19 outputs.

3. The 144-pin package has eight ports. The 100-pin package has five I/O ports and one input-only port

(P9_1).

4. Ports P11 to P15 are only available in the 144-pin package.

Multi-master I2C-bus

interface:

1 channel

CAN module:

1 channel

R01UH0211EJ0120 Rev.1.20 Page 10 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

1.4 Pin Assignments

Figures 1.3 and 1.4 show the pin assignments (top view) and Tables 1.7 to 1.13 list the pin characteristics.

Figure 1.3 Pin Assignment for the 144-pin Package (top view)

Notes:

1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.

2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3.

3. The position of pin number 1 varies by product. Refer to the index mark in attached “Package Dimensions”.

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

RXD4 / SCL4 / STXD4 / ADTRG / P9_7 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA

P6_7 / TXD1 / SDA1 / SRXD1AVCC

VREF

AN_0 / P10_0

AVSS

AN_1 / P10_1

AN_2 / P10_2

AN_3 / P10_3

KI0 / AN_4 / P10_4

KI1 / AN_5 / P10_5

KI2 / AN_6 / P10_6

KI3 / AN_7 / P10_7

VCC

IIO0_0 / TXD7 / AN15_0 / P15_0

VSS

IIO0_1 / CLK7 / AN15_1 / P15_1

IIO0_2 / RXD7 / AN15_2 / P15_2

IIO0_3 / CTS7 / RTS7 / AN15_3 / P15_3

IIO0_4 / TXD6 / SDA6 / SRXD6 / AN15_4 / P15_4

IIO0_5 / RXD6 / SCL6 / STXD6 / AN15_5 / P15_5

IIO0_6 / CLK6 / AN15_6 / P15_6

IIO0_7 / CTS6 / RTS6 / SS6 / AN15_7 / P15_7

AN0_0 / D0 / P0_0

AN0_1 / D1 / P0_1

AN0_2 / D2 / P0_2

AN0_3 / D3 / P0_3

IIO1_0 / TXD8 / CS0 / P11_0

IIO1_1 / CLK8 / CS1 / P11_1

IIO1_2 / RXD8 / CS2 / P11_2

IIO1_3 / CTS8 / RTS8 / WR2 / CS3 / P11_3

WR3 / BC3 / P11_4

AN0_4 / D4 / P0_4

AN0_5 / D5 / P0_5

AN0_6 / D6 / P0_6

AN0_7 / D7 / P0_7

IIO0_0 / IIO1_0 / D8 / P1_0

VCC

P6_6 / RXD1 / SCL1 / STXD1

VSS

P6_5 / CLK1

P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2

P6_3 / TXD0 / SDA0 / SRXD0

P6_2 / TB2IN / RXD0 / SCL0 / STXD0

P6_1 / TB1IN / CLK0

P6_0 / TB0IN / CTS0 / RTS0 / SS0

P13_7 / D31 / OUTC2_7

P13_6 / D30 / OUTC2_1 / ISCLK2

P13_5 / D29 / OUTC2_2 / ISRXD2 / IEIN

P13_4 / D28 / OUTC2_0 / ISTXD2 / IEOUT

P5_7 / RDY / CS3 / CTS7 / RTS7

P5_6 / ALE / CS2 / RXD7

P5_5 / HOLD / CLK7

P5_4 / HLDA / CS1 / TXD7

P13_3 / D27 / OUTC2_3

VSS

P13_2 / D26 / OUTC2_6

VCC

P13_1 / D25 / OUTC2_5

P13_0 / D24 / OUTC2_4

P5_3 / CLKOUT / BCLK

P5_2 / RD

P5_1 / WR1 / BC1

P5_0 / WR0 / WR

P12_7 / D23

P12_6 / D22

P12_5 / D21

P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6

P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6

P4_5 / CS2 / A21 / CLK6

P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6

TXD4 / SDA4 / SRXD4 / ANEX1 / P9_6

CLK4 / ANEX0 / P9_5

CTS4 / RTS4 / SS4 / TB4IN / DA1 / P9_4

OUTC2_0 / ISTXD2 / IEOUT / TXD3 / SDA3 / SRXD3 / TB2IN / P9_2

ISRXD2 / IEIN / RXD3 / SCL3 / STXD3 / TB1IN / P9_1

CLK3 / TB0IN / P9_0

INT8 / P14_6

INT7 / P14_5

INT6 / P14_4

P14_3

NSD

CNVSS

XCIN / P8_7

XCOUT / P8_6

RESET

XOUT

VSS

XIN

VCC

NMI / P8_5

INT2 / P8_4

CAN0IN / CAN0WU / INT1 / P8_3

CAN0OUT / INT0 / P8_2

IIO1_5 / UD0B / UD1B / CTS5 / RTS5 / SS5 / U / TA4IN / P8_1

UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0

CAN0IN / CAN0WU / IIO1_4 / UD0B / UD1B / CLK5 / TA3IN / P7_7

CAN0OUT / IIO1_3 / UD0A / UD1A / CTS8 / RTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6

IIO1_2 / RXD8 / W / TA2IN / P7_5

IIO1_1 / CLK8 / W / TA2OUT / P7_4

IIO1_0 / TXD8 / CTS2 / RTS2 / SS2 / V / TA1IN / P7_3

CLK2 / V / TA1OUT / P7_2

MSCL / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN / RXD2 / SCL2 / STXD2 / TA0IN / TB5IN / P7_1

CTS3 / RTS3 / SS3 / TB3IN / DA0 / P9_3

VDC0

P14_1

VDC1

P1_1 / D9 / IIO0_1 / IIO1_1

P1_2 / D10 / IIO0_2 / IIO1_2

P1_3 / D11 / IIO0_3 / IIO1_3

P1_4 / D12 / IIO0_4 / IIO1_4

P1_5 / D13 / INT3 / IIO0_5 / IIO1_5

P1_6 / D14 / INT4 / IIO0_6 / IIO1_6

P1_7 / D15 / INT5 / IIO0_7 / IIO1_7

P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0

VSS

P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A

VCC

P12_0 / D16 / TXD6 / SDA6 / SRXD6

P12_1 / D17 / CLK6

P12_2 / D18 / RXD6 / SCL6 / STXD6

P12_3 / D19 / CTS6 / RTS6 / SS6

P12_4 / D20

P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B

P3_2 / A10 / [A10/D10] / TA1OUT / V

P3_3 / A11 / [A11/D11] / TA1IN / V

P3_4 / A12 / [A12/D12] / TA2OUT / W

P3_5 / A13 / [A13/D13] / TA2IN / W

P3_6 / A14 / [A14/D14] / TA4OUT / U

P3_7 / A15 / [A15/D15] / TA4IN / U

P4_0 / A16 / CTS3 / RTS3 / SS3

P4_1 / A17 / CLK3

VSS

P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN

VCC

P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT

P2_1 / A1 / [A1/D1] / BC2 / [BC2/D1] / AN2_1

P2_2 / A2 / [A2/D2] / AN2_2

P2_3 / A3 / [A3/D3] / AN2_3

P2_4 / A4 / [A4/D4] / AN2_4

P2_5 / A5 / [A5/D5] / AN2_5

P2_6 / A6 / [A6/D6] / AN2_6

P2_7 / A7 / [A7/D7] / AN2_7

PLQP0144KA-A

(144P6Q-A)

(Top view)

R32C/117 Group

(Note 3)

(Note 1)

(Note 2)

R01UH0211EJ0120 Rev.1.20 Page 11 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Table 1.7 Pin Characteristics for the 144-pin Package (1/4)

No.

Control

Pin Port Interrupt

Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog

Bus Control

1 P9_6 TXD4/SDA4/SRXD4 ANEX1

2 P9_5 CLK4 ANEX0

3P9_4TB4INCTS4/RTS4/SS4 DA1

4P9_3TB3INCTS3/RTS3/SS3 DA0

5 P9_2 TB2IN TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/

IEOUT

6 P9_1 TB1IN RXD3/SCL3/STXD3 ISRXD2/IEIN

7 P9_0 TB0IN CLK3

8 P14_6 INT8

9 P14_5 INT7

10 P14_4 INT6

11 P14_3

12 VDC0

13 P14_1

14 VDC1

15 NSD

16 CNVSS

17 XCIN P8_7

18 XCOUT P8_6

19 RESET

20 XOUT

21 VSS

22 XIN

23 VCC

24 P8_5 NMI

25 P8_4 INT2

26 P8_3 INT1 CAN0IN/CAN0WU

27 P8_2 INT0 CAN0OUT

28 P8_1 TA4IN/UCTS5/RTS5/SS5 IIO1_5/UD0B/UD1B

29 P8_0 TA4OUT/U RXD5/SCL5/STXD5 UD0A/UD1A

30 P7_7 TA3IN CLK5/CAN0IN/

CAN0WU

IIO1_4/UD0B/UD1B

31 P7_6 TA3OUT TXD5/SDA5/SRXD5/

CTS8/RTS8/CAN0OUT

IIO1_3/UD0A/UD1A

32 P7_5 TA2IN/WRXD8 IIO1_2

33 P7_4 TA2OUT/W CLK8 IIO1_1

34 P7_3 TA1IN/VCTS2/RTS2/SS2/TXD8 IIO1_0

35 P7_2 TA1OUT/V CLK2

36 P7_1 TA0IN/

TB5IN

RXD2/SCL2/STXD2/

MSCL

IIO1_7/OUTC2_2/

ISRXD2/IEIN

R01UH0211EJ0120 Rev.1.20 Page 12 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Table 1.8 Pin Characteristics for the 144-pin Package (2/4)

No.

Control

Pin Port Interrupt

Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog

Bus Control

37 P7_0 TA0OUT TXD2/SDA2/SRXD2/

MSDA

IIO1_6/OUTC2_0/

ISTXD2/IEOUT

38 P6_7 TXD1/SDA1/SRXD1

39 VCC

40 P6_6 RXD1/SCL1/STXD1

41 VSS

42 P6_5 CLK1

43 P6_4 CTS1/RTS1/SS1 OUTC2_1/ISCLK2

44 P6_3 TXD0/SDA0/SRXD0

45 P6_2 TB2IN RXD0/SCL0/STXD0

46 P6_1 TB1IN CLK0

47 P6_0 TB0IN CTS0/RTS0/SS0

48 P13_7 OUTC2_7 D31

49 P13_6 OUTC2_1/ISCLK2 D30

50 P13_5 OUTC2_2/ISRXD2/

IEIN

D29

51 P13_4 OUTC2_0/ISTXD2/

IEOUT

D28

52 P5_7 CTS7/RTS7 RDY/CS3

53 P5_6 RXD7 ALE/CS2

54 P5_5 CLK7 HOLD

55 P5_4 TXD7 HLDA/CS1

56 P13_3 OUTC2_3 D27

57 VSS

58 P13_2 OUTC2_6 D26

59 VCC

60 P13_1 OUTC2_5 D25

61 P13_0 OUTC2_4 D24

62 P5_3 CLKOUT/

BCLK

63 P5_2 RD

64 P5_1 WR1/BC1

65 P5_0 WR0/WR

66 P12_7 D23

67 P12_6 D22

68 P12_5 D21

69 P4_7 TXD6/SDA6/SRXD6 CS0/A23

70 P4_6 RXD6/SCL6/STXD6 CS1/A22

71 P4_5 CLK6 CS2/A21

72 P4_4 CTS6/RTS6/SS6 CS3/A20

73 P4_3 TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/

IEOUT

A19

74 VCC

R01UH0211EJ0120 Rev.1.20 Page 13 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Table 1.9 Pin Characteristics for the 144-pin Package (3/4)

No.

Control

Pin Port Interrupt

Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog

Bus Control

75 P4_2 RXD3/SCL3/STXD3 ISRXD2/IEIN A18

76 VSS

77 P4_1 CLK3 A17

78 P4_0 CTS3/RTS3/SS3 A16

79 P3_7 TA4IN/UA15(/D15)

80 P3_6 TA4OUT/U A14(/D14)

81 P3_5 TA2IN/WA13(/D13)

82 P3_4 TA2OUT/W A12(/D12)

83 P3_3 TA1IN/VA11(/D11)

84 P3_2 TA1OUT/V A10(/D10)

85 P3_1 TA3OUT UD0B/UD1B A9(/D9)

86 P12_4 D20

87 P12_3 CTS6/RTS6/SS6 D19

88 P12_2 RXD6/SCL6/STXD6 D18

89 P12_1 CLK6 D17

90 P12_0 TXD6/SDA6/SRXD6 D16

91 VCC

92 P3_0 TA0OUT UD0A/UD1A A8(/D8)

93 VSS

94 P2_7 AN2_7 A7(/D7)

95 P2_6 AN2_6 A6(/D6)

96 P2_5 AN2_5 A5(/D5)

97 P2_4 AN2_4 A4(/D4)

98 P2_3 AN2_3 A3(/D3)

99 P2_2 AN2_2 A2(/D2)

100 P2_1 AN2_1 A1(/D1)/

BC2(/D1)

101 P2_0 AN2_0 A0(/D0)/

BC0(/D0)

102 P1_7 INT5 IIO0_7/IIO1_7 D15

103 P1_6 INT4 IIO0_6/IIO1_6 D14

104 P1_5 INT3 IIO0_5/IIO1_5 D13

105 P1_4 IIO0_4/IIO1_4 D12

106 P1_3 IIO0_3/IIO1_3 D11

107 P1_2 IIO0_2/IIO1_2 D10

108 P1_1 IIO0_1/IIO1_1 D9

109 P1_0 IIO0_0/IIO1_0 D8

110 P0_7 AN0_7 D7

111 P0_6 AN0_6 D6

112 P0_5 AN0_5 D5

113 P0_4 AN0_4 D4

114 P11_4 BC3/WR3

R01UH0211EJ0120 Rev.1.20 Page 14 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Table 1.10 Pin Characteristics for the 144-pin Package (4/4)

No.

Control

Pin Port Interrupt

Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog

Bus Control

115 P11_3 CTS8/RTS8 IIO1_3 CS3/WR2

116 P11_2 RXD8 IIO1_2 CS2

117 P11_1 CLK8 IIO1_1 CS1

118 P11_0 TXD8 IIO1_0 CS0

119 P0_3 AN0_3 D3

120 P0_2 AN0_2 D2

121 P0_1 AN0_1 D1

122 P0_0 AN0_0 D0

123 P15_7 CTS6/RTS6/SS6 IIO0_7 AN15_7

124 P15_6 CLK6 IIO0_6 AN15_6

125 P15_5 RXD6/SCL6/STXD6 IIO0_5 AN15_5

126 P15_4 TXD6/SDA6/SRXD6 IIO0_4 AN15_4

127 P15_3 CTS7/RTS7 IIO0_3 AN15_3

128 P15_2 RXD7 IIO0_2 AN15_2

129 P15_1 CLK7 IIO0_1 AN15_1

130 VSS

131 P15_0 TXD7 IIO0_0 AN15_0

132 VCC

133 P10_7 KI3 AN_7

134 P10_6 KI2 AN_6

135 P10_5 KI1 AN_5

136 P10_4 KI0 AN_4

137 P10_3 AN_3

138 P10_2 AN_2

139 P10_1 AN_1

140 AVSS

141 P10_0 AN_0

142 VREF

143 AVCC

144 P9_7 RXD4/SCL4/STXD4 ADTRG

R01UH0211EJ0120 Rev.1.20 Page 15 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Figure 1.4 Pin Assignment for the 100-pin Package (top view)

100

RXD4 / SCL4 / STXD4 / ADTRG / P9_7 P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6 / OUTC2_0 / ISTXD2 / IEOUT / MSDA

P6_7 / TXD1 / SDA1 / SRXD1AVCC

VREF

AN_0 / P10_0

AVSS

AN_1 / P10_1

AN_2 / P10_2

AN_3 / P10_3

KI0 / AN_4 / P10_4

KI1 / AN_5 / P10_5

KI2 / AN_6 / P10_6

KI3 / AN_7 / P10_7

AN0_0 / D0 / P0_0

AN0_1 / D1 / P0_1

AN0_2 / D2 / P0_2

AN0_3 / D3 / P0_3

AN0_4 / D4 / P0_4

AN0_5 / D5 / P0_5

AN0_6 / D6 / P0_6

AN0_7 / D7 / P0_7

P6_6 / RXD1 / SCL1 / STXD1

P6_5 / CLK1

P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2

P6_3 / TXD0 / SDA0 / SRXD0

P6_2 / TB2IN / RXD0 / SCL0 / STXD0

P6_1 / TB1IN / CLK0

P6_0 / TB0IN / CTS0 / RTS0 / SS0

P5_7 / RDY / CS3 / CTS7 / RTS7

P5_6 / ALE / CS2 / RXD7

P5_5 / HOLD / CLK7

P5_4 / HLDA / CS1 / TXD7

P5_3 / CLKOUT / BCLK

P5_2 / RD

P5_1 / WR1 / BC1

P5_0 / WR0 / WR

P4_7 / CS0 / A23 / TXD6 / SDA6 / SRXD6

P4_6 / CS1 / A22 / RXD6 / SCL6 / STXD6

P4_5 / CS2 / A21 / CLK6

P4_4 / CS3 / A20 / CTS6 / RTS6 / SS6

TXD4 / SDA4 / SRXD4 / ANEX1 / P9_6

CLK4 / ANEX0 / P9_5

CTS4 / RTS4 / SS4 / TB4IN / DA1 / P9_4

VDC0

P9_1

VDC1

NSD

CNVSS

XCIN / P8_7

XCOUT / P8_6

RESET

XOUT

VSS

XIN

VCC

NMI / P8_5

INT2 / P8_4

CAN0IN / CAN0WU / INT1 / P8_3

CAN0OUT / INT0 / P8_2

IIO1_5 / UD0B / UD1B / CTS5 / RTS5 / SS5 / U / TA4IN / P8_1

UD0A / UD1A / RXD5 / SCL5 / STXD5 / U / TA4OUT / P8_0

CAN0IN / CAN0WU / IIO1_4 / UD0B / UD1B / CLK5 / TA3IN / P7_7

CAN0OUT / IIO1_3 / UD0A / UD1A / CTS8 / RTS8 / TXD5 / SDA5 / SRXD5 / TA3OUT / P7_6

IIO1_2 / RXD8 / W / TA2IN / P7_5

IIO1_1 / CLK8 / W / TA2OUT / P7_4

IIO1_0 / TXD8 / CTS2 / RTS2 / SS2 / V / TA1IN / P7_3

P7_2 / TA1OUT / V / CLK2

P7_1 / TA0IN / TB5IN / RXD2 / SCL2 / STXD2 / IIO1_7 / OUTC2_2 / ISRXD2 / IEIN / MSCL

TB3IN / DA0 / P9_3

IIO0_1 / IIO1_1 / D9 / P1_1

IIO0_2 / IIO1_2 / D10 / P1_2

P1_3 / D11 / IIO0_3 / IIO1_3

P1_4 / D12 / IIO0_4 / IIO1_4

P1_5 / D13 / INT3 / IIO0_5 / IIO1_5

P1_6 / D14 / INT4 / IIO0_6 / IIO1_6

P1_7 / D15 / INT5 / IIO0_7 / IIO1_7

P2_0 / A0 / [A0/D0] / BC0 / [BC0/D0] / AN2_0

VSS

P3_0 / A8 / [A8/D8] / TA0OUT / UD0A / UD1A

VCC

P3_1 / A9 / [A9/D9] / TA3OUT / UD0B / UD1B

P3_2 / A10 / [A10/D10] / TA1OUT / V

P3_3 / A11 / [A11/D11] / TA1IN / V

P3_4 / A12 / [A12/D12] / TA2OUT / W

P3_5 / A13 / [A13/D13] / TA2IN / W

P3_6 / A14 / [A14/D14] / TA4OUT / U

P3_7 / A15 / [A15/D15] / TA4IN / U

P4_0 / A16 / CTS3 / RTS3 / SS3

P4_1 / A17 / CLK3

P4_2 / A18 / RXD3 / SCL3 / STXD3 / ISRXD2 / IEIN

P4_3 / A19 / TXD3 / SDA3 / SRXD3 / OUTC2_0 / ISTXD2 / IEOUT

P2_1 / A1 / [A1/D1] / AN2_1

P2_2 / A2 / [A2/D2] / AN2_2

P2_3 / A3 / [A3/D3] / AN2_3

P2_4 / A4 / [A4/D4] / AN2_4

P2_5 / A5 / [A5/D5] / AN2_5

P2_6 / A6 / [A6/D6] / AN2_6

P2_7 / A7 / [A7/D7] / AN2_7

IIO0_0 / IIO1_0 / D8 / P1_0

PLQP0100KB-A

(100P6Q-A)

(Top view)

R32C/117 Group

(Note 1)

(Note 3)

(Note 2)

Notes:

1. Pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins.

2. The following pins are 5 V tolerant inputs: P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7, P7_0 to P7_7, and P8_0 to P8_3.

3. The position of pin number 1 varies by product. Refer to the indexmark in attached “Package Dimensions”.

R01UH0211EJ0120 Rev.1.20 Page 16 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Table 1.11 Pin Characteristics for the 100-pin Package (1/3)

No.

Control

Pin Port Interrupt

Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog

Bus Control

1P9_4TB4INCTS4/RTS4/SS4 DA1

2P9_3TB3IN DA0

3 VDC0

4P9_1

5 VDC1

6NSD

7 CNVSS

8XCINP8_7

9 XCOUT P8_6

10 RESET

11 XOUT

12 VSS

13 XIN

14 VCC

15 P8_5 NMI

16 P8_4 INT2

17 P8_3 INT1 CAN0IN/CAN0WU

18 P8_2 INT0 CAN0OUT

19 P8_1 TA4IN/UCTS5/RTS5/SS5 IIO1_5/UD0B/UD1B

20 P8_0 TA4OUT/U RXD5/SCL5/STXD5 UD0A/UD1A

21 P7_7 TA3IN CLK5/CAN0IN/

CAN0WU

IIO1_4/UD0B/UD1B

22 P7_6 TA3OUT TXD5/SDA5/SRXD5/

CTS8/RTS8/CAN0OUT

IIO1_3/UD0A/UD1A

23 P7_5 TA2IN/WRXD8 IIO1_2

24 P7_4 TA2OUT/W CLK8 IIO1_1

25 P7_3 TA1IN/VCTS2/RTS2/SS2/TXD8 IIO1_0

26 P7_2 TA1OUT/V CLK2

27 P7_1 TA0IN/

TB5IN

RXD2/SCL2/STXD2/

MSCL

IIO1_7/OUTC2_2/

ISRXD2/IEIN

28 P7_0 TA0OUT TXD2/SDA2/SRXD2/

MSDA

IIO1_6/OUTC2_0/

ISTXD2/IEOUT

29 P6_7 TXD1/SDA1/SRXD1

30 P6_6 RXD1/SCL1/STXD1

31 P6_5 CLK1

32 P6_4 CTS1/RTS1/SS1 OUTC2_1/ISCLK2

33 P6_3 TXD0/SDA0/SRXD0

34 P6_2 TB2IN RXD0/SCL0/STXD0

35 P6_1 TB1IN CLK0

36 P6_0 TB0IN CTS0/RTS0/SS0

37 P5_7 CTS7/RTS7 RDY/CS3

38 P5_6 RXD7 ALE/CS2

R01UH0211EJ0120 Rev.1.20 Page 17 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Table 1.12 Pin Characteristics for the 100-pin Package (2/3)

No.

Control

Pin Port Interrupt

Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog

Bus Control

39 P5_5 CLK7 HOLD

40 P5_4 TXD7 HLDA/CS1

41 P5_3 CLKOUT/

BCLK

42 P5_2 RD

43 P5_1 WR1/BC1

44 P5_0 WR0/WR

45 P4_7 TXD6/SDA6/SRXD6 CS0/A23

46 P4_6 RXD6/SCL6/STXD6 CS1/A22

47 P4_5 CLK6 CS2/A21

48 P4_4 CTS6/RTS6/SS6 CS3/A20

49 P4_3 TXD3/SDA3/SRXD3 OUTC2_0/ISTXD2/

IEOUT

A19

50 P4_2 RXD3/SCL3/STXD3 ISRXD2/IEIN A18

51 P4_1 CLK3 A17

52 P4_0 CTS3/RTS3/SS3 A16

53 P3_7 TA4IN/UA15(/D15)

54 P3_6 TA4OUT/U A14(/D14)

55 P3_5 TA2IN/WA13(/D13)

56 P3_4 TA2OUT/W A12(/D12)

57 P3_3 TA1IN/VA11(/D11)

58 P3_2 TA1OUT/V A10(/D10)

59 P3_1 TA3OUT UD0B/UD1B A9(/D9)

60 VCC

61 P3_0 TA0OUT UD0A/UD1A A8(/D8)

62 VSS

63 P2_7 AN2_7 A7(/D7)

64 P2_6 AN2_6 A6(/D6)

65 P2_5 AN2_5 A5(/D5)

66 P2_4 AN2_4 A4(/D4)

67 P2_3 AN2_3 A3(/D3)

68 P2_2 AN2_2 A2(/D2)

69 P2_1 AN2_1 A1(/D1)

70 P2_0 AN2_0 A0(/D0)/

BC0(/D0)

71 P1_7 INT5 IIO0_7/IIO1_7 D15

72 P1_6 INT4 IIO0_6/IIO1_6 D14

73 P1_5 INT3 IIO0_5/IIO1_5 D13

74 P1_4 IIO0_4/IIO1_4 D12

75 P1_3 IIO0_3/IIO1_3 D11

R01UH0211EJ0120 Rev.1.20 Page 18 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Table 1.13 Pin Characteristics for the 100-pin Package (3/3)

No.

Control

Pin Port Interrupt

Pin Timer Pin UART/CAN Module Pin Intelligent I/O Pin Analog

Bus Control

76 P1_2 IIO0_2/IIO1_2 D10

77 P1_1 IIO0_1/IIO1_1 D9

78 P1_0 IIO0_0/IIO1_0 D8

79 P0_7 AN0_7 D7

80 P0_6 AN0_6 D6

81 P0_5 AN0_5 D5

82 P0_4 AN0_4 D4

83 P0_3 AN0_3 D3

84 P0_2 AN0_2 D2

85 P0_1 AN0_1 D1

86 P0_0 AN0_0 D0

87 P10_7 KI3 AN_7

88 P10_6 KI2 AN_6

89 P10_5 KI1 AN_5

90 P10_4 KI0 AN_4

91 P10_3 AN_3

92 P10_2 AN_2

93 P10_1 AN_1

94 AVSS

95 P10_0 AN_0

96 VREF

97 AVCC

98 P9_7 RXD4/SCL4/STXD4 ADTRG

99 P9_6 TXD4/SDA4/SRXD4 ANEX1

100 P9_5 CLK4 ANEX0

R01UH0211EJ0120 Rev.1.20 Page 19 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

1.5 Pin Definitions and Functions

Tables 1.14 to 1.18 list the pin definitions and functions.

Notes:

1. Pins INT6 to INT8 are available in the 144-pin package only.

2. Pins D16 to D31 are available in the 144-pin package only.

Table 1.14 Pin Definitions and Functions (1/4)

Function Symbol I/O Description

Power supply VCC, VSS I Applicable as follows: VCC = 3.0 to 5.5 V, VSS = 0 V

Connecting pins

for decoupling

capacitor

VDC0, VDC1

—

A decoupling capacitor for internal voltage should be

connected between VDC0 and VDC1

Analog power

supply

AVCC, AVSS IPower supply for the A/D converter. AVCC and AVSS

should be connected to VCC and VSS, respectively

Reset input RESET I The MCU is reset when this pin is driven low

CNVSS CNVSS I This pin should be connected to VSS via a resistor

Debug port NSD I/O This pin is to communicate with a debugger. It should be

connected to VCC via a resistor of 1 to 4.7 k

Main clock input XIN IInput/output for the main clock oscillator. A crystal, or a

ceramic resonator should be connected between pins XIN

and XOUT. An external clock should be input at the XIN

while leaving the XOUT open

Main clock output XOUT O

Sub clock input XCIN IInput/output for the sub clock oscillator. A crystal oscillator

should be connected between pins XCIN and XCOUT. An

external clock should be input at the XCIN while leaving the

XCOUT open

Sub clock output XCOUT O

BCLK output BCLK O BCLK output

Clock output CLKOUT OOutput of the clock with the same frequency as low speed

clocks, f8, or f32

External interrupt

input

INT0 to INT8 (1) IInput for external interrupts

NMI input P8_5/NMI I Input for NMI

Key input interrupt KI0 to KI3 I Input for the key input interrupt

Bus control pins D0 to D7 I/O Input/output of data (D0 to D7) while accessing an external

memory space with a separate bus

D8 to D15 I/O Input/output of data (D8 to D15) while accessing an

external memory space with 16-bit or 32-bit separate bus

D16 to D31 (2) I/O Input/output of data (D16 to D31) while accessing an

external memory space with 32-bit separate bus

A0 to A23 O Output of address bits A0 to A23

A0/D0 to A7/D7

I/O

Output of address bits (A0 to A7) and input/output of data

(D0 to D7) by time-division while accessing an external

memory space with multiplexed bus

A8/D8 to

A15/D15 I/O

Output of address bits (A8 to A15) and input/output of data

(D8 to D15) by time-division while accessing an external

memory space with 16-bit or 32-bit multiplexed bus

R01UH0211EJ0120 Rev.1.20 Page 20 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Note:

1. Pins BC2/D1, WR2, WR3, BC2, and BC3 are available in the 144-pin package only.

Table 1.15 Pin Definitions and Functions (2/4)

Function Symbol I/O Description

Bus control pins BC0/D0, BC2/D1

(1) I/O

Output of byte control (BC0 and BC2) and input/output of

data (D0 and D1) by time-division while accessing an

external memory space with multiplexed bus

CS0 to CS3 O Chip select output

WR0/WR1/WR2/

WR3,

WR/BC0/BC1/

BC2/BC3,

RD (1)

Output of write, byte control, and read signals. Either WRx

or WR and BCx can be selected by a program.

Data is read when RD is low.

• When WR0, WR1, WR2, WR3, and RD are selected,

data is written to the following address:

4n+0, when WR0 is low

4n+1, when WR1 is low

4n+2, when WR2 is low

4n+3, when WR3 is low

on 32-bit external data bus

an even address, when WR0 is low

an odd address, when WR1 is low

on 16-bit external data bus

• When WR, BC0, BC1, BC2, BC3, and RD are selected,

data is written, when WR is low

and

the following address is accessed:

4n+0, when BC0 is low

4n+1, when BC1 is low

4n+2, when BC2 is low

4n+3, when BC3 is low

on 32-bit external data bus

an even address, when BC0 is low

an odd address, when BC1 is low

on 16-bit external data bus

ALE O Latch enable signal in multiplexed bus format

HOLD I The MCU is in a hold state while this pin is held low

HLDA O This pin is driven low while the MCU is held in a hold state

RDY IBus cycle is extended by the CPU if this pin is low on the

falling edge of BCLK

R01UH0211EJ0120 Rev.1.20 Page 21 of 604
Feb 18, 2013
R32C/117 Group 1.  Overview
Notes:
1. Port P9_1 in the 100-pin package is an input-only port.
2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only.
Table 1.16 Pin Definitions and Functions (3/4)
Function Symbol I/O Description
I/O port (1, 2) P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P6_0 to P6_7,
P7_0 to P7_7,
P8_0 to P8_4,
P8_6, P8_7,
P9_0 to P9_7,
P10_0 to P10_7,
P11_0 to P11_4,
P12_0 to P12_7,
P13_0 to P13_7,
P14_3 to P14_6,
P15_0 to P15_7
I/O
I/O ports in CMOS. Each port can be programmed to input 
or output under the control of the direction register.
Some ports are 5 V tolerant inputs. 
Pull-up resistors and N-channel open drain setting can be 
enabled on some ports. Refer to Table 1.18 “Pin 
Specifications” for details
Input port (2) P9_1 (for 100-pin 
package)
P14_1 (for 144-
pin package)
I
Input port in CMOS
Pull-up resistor is selectable.
Refer to Table 1.18 “Pin Specifications” for details
Timer A TA0OUT to
TA4OUT I/O Timers A0 to A4 input/output
TA0IN to TA4IN I Timers A0 to A4 input
Timer B TB0IN to TB5IN I Timers B0 to B5 input
Three-phase 
motor control 
timer output
U, U, V, V, W, W
O
Three-phase motor control timer output
Serial interface CTS0 to CTS8 I Handshake input
RTS0 to RTS8 O Handshake output
CLK0 to CLK8 I/O Transmit/receive clock input/output
RXD0 to RXD8 I Serial data input
TXD0 to TXD8 O Serial data output
I2C-bus
(simplified)
SDA0 to SDA6 I/O Serial data input/output
SCL0 to SCL6 I/O Transmit/receive clock input/output
Serial interface 
special functions
STXD0 to
STXD6 OSerial data output in slave mode
SRXD0 to 
SRXD6 ISerial data input in slave mode
SS0 to SS6 I Input to control serial interface special functions

R01UH0211EJ0120 Rev.1.20 Page 22 of 604

Feb 18, 2013

R32C/117 Group 1. Overview

Notes:

1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.

2. Pins OUTC2_3 to OUTC2_7 are available in the 144-pin package only.

Table 1.17 Pin Definitions and Functions (4/4)

Function Symbol I/O Description

A/D converter AN_0 to AN_7,

AN0_0 to AN0_7,

AN2_0 to AN2_7,

AN15_0 to

AN15_7 (1)

Analog input for the A/D converter

ADTRG I External trigger input for the A/D converter

ANEX0 I/O Expanded analog input for the A/D converter and output in

external op-amp connection mode

ANEX1 I Expanded analog input for the A/D converter

D/A converter DA0, DA1 O Output for the D/A converter

Reference voltage

input

VREF IReference voltage input for the A/D converter and D/A

converter

Intelligent I/O IIO0_0 to IIO0_7 I/O Input/output for Intelligent I/O group 0. Either input capture

or output compare is selectable

IIO1_0 to IIO1_7 I/O Input/output for Intelligent I/O group 1. Either input capture

or output compare is selectable

UD0A, UD0B,

UD1A, UD1B IInput for the two-phase encoder

OUTC2_0 to

OUTC2_7 (2) OOutput for OC (output compare) of Intelligent I/O group 2

ISCLK2 I/O Clock input/output for the serial interface

ISRXD2 I Receive data input for the serial interface

ISTXD2 O Transmit data output for the serial interface

IEIN I Receive data input for the serial interface

IEOUT O Transmit data output for the serial interface

Multi-master I2C-

bus

MSDA I/O Serial data input/output

MSCL I/O Transmit/receive clock input/output

CAN Module CAN0IN I Receive data input for the CAN communications

CAN0OUT O Transmit data output for the CAN communications

CAN0WU I Input for the CAN wake-up interrupt

R01UH0211EJ0120 Rev.1.20 Page 23 of 604

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R32C/117 Group 1. Overview

Table 1.18 Pin Specifications

Notes:

1. Pull-up resistors are selected for the following 4-pin units: Pi_0 to Pi_3 and Pi_4 to Pi_7 (i = 0 to 15);

however, they are enabled only for the input pins.

2. N-channel open drain output can be enabled on the applicable pins on a discrete pin basis.

3. 5 V tolerant input is enabled when an applicable pin is set as an input port. When it is set as an I/O

port, to enable 5 V tolerant input, this pin should be set as N-channel open drain output.

Pin Names

Package Selectable Functions

5 V Tolerant Input (3)

144-

100-

pin Pull-up resistor (1) N-channel

open drain (2)

P0_0 to P0_7  

P1_0 to P1_7  

P2_0 to P2_7  

P3_0 to P3_7  

P4_0 to P4_7   

P5_0 to P5_3  

P5_4 to P5_7   

P6_0 to P6_7   

P7_0 to P7_7   

P8_0 to P8_3   

P8_4, P8_6, P8_7  

P9_0 to P9_3 (144-pin) 

P9_1, P9_3 (100-pin) 

P9_4 to P9_7   

P10_0 to P10_7  

P11_0 to P11_3 

P11_4 

P12_0 to P12_3 

P12_4 to P12_7 

P13_0 to P13_7 

P14_1, P14_3 

P14_4 to P14_6 

P15_0 to P15_7 

R01UH0211EJ0120 Rev.1.20 Page 24 of 604

Feb 18, 2013

R32C/117 Group 2. Central Processing Unit (CPU)

2. Central Processing Unit (CPU)

The CPU contains the registers shown below. There are two register banks each consisting of registers

R2R0, R3R1, R6R4, R7R5, A0 to A3, SB, and FB.

Figure 2.1 CPU Registers

DDA0

DDR0

DSA0

DSR0

DDA0

DCR0

DCT0

DMD0

DDR0

DSA0

DSR0

DDA0

DCR0

DCT0

DMD0

DDR0

DSA0

DSR0

DDA0

DCR0

DCT0

DMD0

DDR0

DSA0

DSR0

DCR0

DCT0

DMD0

b0b31

VCT

SVP

SVF

INTB

USP

ISP

R5R7

R6 R4

R1LR1HR3LR3H

R2H R2L R0H R0L

FLG

b0b31

General purpose

registers

Fast interrupt

registers

DMAC-associated

registers (2)

Notes:

1.There are two banks of these registers.

2.There are four identical sets of DMAC-associated registers.

DMA destination address reload register

Flag register

Data registers (1)

Address registers (1)

Static base register (1)

Frame base register (1)

User stack pointer

Interrupt stack pointer

Interrupt vector table base register

Program counter

Save flag register

Save PC register

Vector register

R2R0

R3R1

R6R4

R7R5

DMA source address register

DMA source address reload register

DMA terminal count reload register

DMA terminal count register

DMA mode register

CDZSBOIUIPLRND

b0b31 b8 b7b16 b15

b0b31

b23 b15 b7

DMA destination address register

Blank spaces are reserved.

b24 b23

b23

R01UH0211EJ0120 Rev.1.20 Page 25 of 604

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R32C/117 Group 2. Central Processing Unit (CPU)

2.1 General Purpose Registers

2.1.1 Data Registers (R2R0, R3R1, R6R4, and R7R5)

These 32-bit registers are primarily used for transfers and arithmetic/logic operations.

Each of the registers can be divided into upper and lower 16-bit registers, e.g. R2R0 can be divided into

R2 and R0, R3R1 can be divided into R3 and R1, etc.

Moreover, data registers R2R0 and R3R1 can be divided into four 8-bit data registers: upper (R2H and

R3H), mid-upper (R2L and R3L), mid-lower (R0H and R1H), and lower (R0L and R1L).

2.1.2 Address Registers (A0, A1, A2, and A3)

These 32-bit registers have functions similar to data registers. They are also used for address register

indirect addressing and address register relative addressing.

2.1.3 Static Base Register (SB)

This 32-bit register is used for SB relative addressing.

2.1.4 Frame Base Register (FB)

This 32-bit register is used for FB relative addressing.

2.1.5 Program Counter (PC)

This 32-bit counter indicates the address of the instruction to be executed next.

2.1.6 Interrupt Vector Table Base Register (INTB)

This 32-bit register indicates the start address of a relocatable vector table.

2.1.7 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Two types of 32-bit stack pointers (SPs) are provided: user stack pointer (USP) and interrupt stack

pointer (ISP).

Use the stack pointer select flag (U flag) to select either the user stack pointer (USP) or the interrupt

stack pointer (ISP). The U flag is bit 7 in the flag register (FLG). Refer to 2.1.8 “Flag Register (FLG)” for

details.

To minimize the overhead of interrupt sequence due to less memory access, set the user stack pointer

(USP) or the interrupt stack pointer (ISP) to a multiple of 4.

2.1.8 Flag Register (FLG)

This 32-bit register indicates the CPU status.

2.1.8.1 Carry Flag (C flag)

This flag retains a carry, borrow, or shifted-out bit generated by the arithmetic logic unit (ALU).

2.1.8.2 Debug Flag (D flag)

This flag is only for debugging. Only set this bit to 0.

2.1.8.3 Zero Flag (Z flag)

This flag becomes 1 when the result of an operation is 0; otherwise it is 0.

2.1.8.4 Sign Flag (S flag)

This flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.

R01UH0211EJ0120 Rev.1.20 Page 26 of 604

Feb 18, 2013

R32C/117 Group 2. Central Processing Unit (CPU)

2.1.8.5 Register Bank Select Flag (B flag)

This flag selects a register bank. It indicates 0 when register bank 0 is selected, and 1 when register

bank 1 is selected.

2.1.8.6 Overflow Flag (O flag)

This flag becomes 1 when the result of an operation overflows; otherwise it is 0.

2.1.8.7 Interrupt Enable Flag (I flag)

This flag enables maskable interrupts. To disable maskable interrupts, set this flag to 0. To enable

them, set this flag to 1. When an interrupt is accepted, the flag becomes 0.

2.1.8.8 Stack Pointer Select Flag (U flag)

To select the interrupt stack pointer (ISP), set this flag to 0. To select the user stack pointer (USP), set

this flag to 1.

It becomes 0 when a hardware interrupt is accepted or when an INT instruction designated by a

software interrupt number from 0 to 127 is executed.

2.1.8.9 Floating-point Underflow Flag (FU flag)

This flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. It also

becomes 1 when the operand contains invalid numbers (subnormal numbers).

2.1.8.10 Floating-point Overflow Flag (FO flag)

This flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. It also

becomes 1 when the operand contains invalid numbers (subnormal numbers).

2.1.8.11 Processor Interrupt Priority Level (IPL)

The processor interrupt priority level (IPL), consisting of 3 bits, selects a processor interrupt priority

level from level 0 to 7. An interrupt is enabled when the interrupt request level is higher than the

selected IPL.

When the processor interrupt priority level (IPL) is set to 111b (level 7), all interrupts are disabled.

2.1.8.12 Fixed-point Radix Point Designation Bit (DP bit)

This bit designates the radix point. It also specifies which portion of the fixed-point multiplication result

to extract. It is used for the MULX instruction.

2.1.8.13 Floating-point Rounding Mode (RND)

The 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results.

2.1.8.14 Reserved

Only set this bit to 0. The read value is undefined.

R01UH0211EJ0120 Rev.1.20 Page 27 of 604

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R32C/117 Group 2. Central Processing Unit (CPU)

2.2 Fast Interrupt Registers

The following three registers are provided to minimize the overhead of the interrupt sequence. Refer to

11.4 “Fast Interrupt” for details.

2.2.1 Save Flag Register (SVF)

This 32-bit register is used to save the flag register when a fast interrupt occurs.

2.2.2 Save PC Register (SVP)

This 32-bit register is used to save the program counter when a fast interrupt occurs.

2.2.3 Vector Register (VCT)

This 32-bit register is used to indicate a jump address when a fast interrupt occurs.

2.3 DMAC-associated Registers

There are seven types of DMAC-associated registers. Refer to 13. “DMAC” for details.

2.3.1 DMA Mode Registers (DMD0, DMD1, DMD2, and DMD3)

These 32-bit registers are used to set DMA transfer mode, bit rate, etc.

2.3.2 DMA Terminal Count Registers (DCT0, DCT1, DCT2, and DCT3)

These 24-bit registers are used to set the number of DMA transfers.

2.3.3 DMA Terminal Count Reload Registers (DCR0, DCR1, DCR2, and DCR3)

These 24-bit registers are used to set the reloaded values for DMA terminal count registers.

2.3.4 DMA Source Address Registers (DSA0, DSA1, DSA2, and DSA3)

These 32-bit registers are used to set DMA source addresses.

2.3.5 DMA Source Address Reload Registers (DSR0, DSR1, DSR2, and DSR3)

These 32-bit registers are used to set the reloaded values for DMA source address registers.

2.3.6 DMA Destination Address Registers (DDA0, DDA1, DDA2, and DDA3)

These 32-bit registers are used to set DMA destination addresses.

2.3.7 DMA Destination Address Reload Registers (DDR0, DDR1, DDR2, and

DDR3)

These 32-bit registers are used to set reloaded values for DMA destination address registers.

R01UH0211EJ0120 Rev.1.20 Page 28 of 604

Feb 18, 2013

R32C/117 Group 3. Memory

3. Memory

Figure 3.1 shows the memory map of the R32C/117 Group.

The R32C/117 Group provides a 4-Gbyte address space from 00000000h to FFFFFFFFh.

The internal ROM is mapped from address FFFFFFFFh in the inferior direction. For example, the 1-Mbyte

internal ROM is mapped from FFF00000h to FFFFFFFFh.

The fixed interrupt vector table contains the start address of interrupt handlers and is mapped from

FFFFFFDCh to FFFFFFFFh.

The internal RAM is mapped from address 00000400h in the superior direction. For example, the 63-Kbyte

internal RAM is mapped from 00000400h to 0000FFFFh. Besides being used for data storage, the internal

RAM functions as a stack(s) for subroutine calls and/or interrupt handlers.

Special function registers (SFRs), which are control registers for peripheral functions, are mapped from

00000000h to 000003FFh, and from 00040000h to 0004FFFFh. Unoccupied SFR locations are reserved,

and no access is allowed.

In memory expansion mode or microprocessor mode, some spaces are reserved for internal use and should

not be accessed.

Figure 3.1 Memory Map

Internal RAM

SFR1

SFR2

00000000h

FFFFFFFFh Reset

NMI

Reserved

BRK instruction

Overflow

Undefined instruction

Watchdog timer (5)

FFFFFFFFh

FFFFFFDCh

YYYYYYYYh

00000400h

XXXXXXXXh

Reserved

00040000h

Internal ROM

(Data space) (1)

00060000h

00062000h

00050000h Reserved

Internal RAM

Capacity XXXXXXXXh

63 Kbytes 00010000h

40 Kbytes 0000A400h

Internal ROM

Capacity YYYYYYYYh

512 Kbytes FFF80000h

640 Kbytes FFF60000h

768 Kbytes FFF40000h

1 Mbyte FFF00000h

48 Kbytes 0000C400h

External space (2)

Reserved

00080000h

Reserved (3)

FFE00000h

Internal ROM (4)

384 Kbytes FFFA0000h

Notes:

1. The flash memory version provides two additional 4-Kbyte spaces (blocks A and B) for storing data.

2. This space can be used in memory expansion mode or microprocessor mode. Addresses from 02000000h

to FDFFFFFFh are inaccessible.

3. This space is reserved in memory expansion mode. It becomes an external space in microprocessor mode.

4. This space can be used in single-chip mode or memory expansion mode. It becomes an external space in

microprocessor mode.

5. The watchdog timer interrupt shares a vector with the oscillator stop detection interrupt and low voltage

detection interrupt.

20 Kbytes 00005400h

256 Kbytes FFFC0000h

128 Kbytes FFFE0000h

R01UH0211EJ0120 Rev.1.20 Page 29 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

4. Special Function Registers (SFRs)

SFRs are memory-mapped peripheral registers that control the operation of peripherals. Table 4.1 SFR List

(1) to Table 4.39 SFR List (39) list the SFR details.

Table 4.1 SFR List (1)

Address Register Symbol Reset Value

000000h

000001h

000002h

000003h

000004h Clock Control Register CCR 0001 1000b

000005h

000006h Flash Memory Control Register FMCR 0000 0001b

000007h Protect Release Register PRR 00h

000008h

000009h

00000Ah

00000Bh

00000Ch

00000Dh

00000Eh

00000Fh

000010h External Bus Control Register 3/Flash Memory Rewrite Bus

Control Register 3

EBC3/FEBC3 0000h

000011h

000012h Chip Selects 2 and 3 Boundary Setting Register CB23 00h

000013h

000014h External Bus Control Register 2 EBC2 0000h

000015h

000016h Chip Selects 1 and 2 Boundary Setting Register CB12 00h

000017h

000018h External Bus Control Register 1 EBC1 0000h

000019h

00001Ah Chip Selects 0 and 1 Boundary Setting Register CB01 00h

00001Bh

00001Ch External Bus Control Register 0/Flash Memory Rewrite Bus

Control Register 0

EBC0/FEBC0 0000h

00001Dh

00001Eh Peripheral Bus Control Register PBC 0504h

00001Fh

000020h to

00005Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 30 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.2 SFR List (2)

Address Register Symbol Reset Value

000060h

000061h Timer B5 Interrupt Control Register TB5IC XXXX X000b

000062h UART5 Transmit/NACK Interrupt Control Register S5TIC XXXX X000b

000063h UART2 Receive/ACK Interrupt Control Register/I2C-bus Line

Interrupt Control Register

S2RIC/I2CLIC XXXX X000b

000064h UART6 Transmit/NACK Interrupt Control Register S6TIC XXXX X000b

000065h UART3 Receive/ACK Interrupt Control Register S3RIC XXXX X000b

000066h UART5/6 Bus Collision, START Condition/STOP Condition

Detection Interrupt Control Register

BCN5IC/BCN6IC XXXX X000b

000067h UART4 Receive/ACK Interrupt Control Register S4RIC XXXX X000b

000068h DMA0 Transfer Complete Interrupt Control Register DM0IC XXXX X000b

000069h UART0/3 Bus Collision, START Condition/STOP Condition

Detection Interrupt Control Register

BCN0IC/BCN3IC XXXX X000b

00006Ah DMA2 Transfer Complete Interrupt Control Register DM2IC XXXX X000b

00006Bh

A/D Converter 0 Convert Completion Interrupt Control Register

AD0IC XXXX X000b

00006Ch Timer A0 Interrupt Control Register TA0IC XXXX X000b

00006Dh Intelligent I/O Interrupt Control Register 0 IIO0IC XXXX X000b

00006Eh Timer A2 Interrupt Control Register TA2IC XXXX X000b

00006Fh Intelligent I/O Interrupt Control Register 2 IIO2IC XXXX X000b

000070h Timer A4 Interrupt Control Register TA4IC XXXX X000b

000071h Intelligent I/O Interrupt Control Register 4 IIO4IC XXXX X000b

000072h UART0 Receive/ACK Interrupt Control Register S0RIC XXXX X000b

000073h Intelligent I/O Interrupt Control Register 6 IIO6IC XXXX X000b

000074h UART1 Receive/ACK Interrupt Control Register S1RIC XXXX X000b

000075h Intelligent I/O Interrupt Control Register 8 IIO8IC XXXX X000b

000076h Timer B1 Interrupt Control Register TB1IC XXXX X000b

000077h Intelligent I/O Interrupt Control Register 10 IIO10IC XXXX X000b

000078h Timer B3 Interrupt Control Register TB3IC XXXX X000b

000079h

00007Ah INT5 Interrupt Control Register INT5IC XX00 X000b

00007Bh CAN0 Wake-up Interrupt Control Register C0WIC XXXX X000b

00007Ch INT3 Interrupt Control Register INT3IC XX00 X000b

00007Dh

00007Eh INT1 Interrupt Control Register INT1IC XX00 X000b

00007Fh

000080h

000081h UART2 Transmit/NACK Interrupt Control Register/I2C-bus

Interrupt Control Register

S2TIC/I2CIC XXXX X000b

000082h UART5 Receive/ACK Interrupt Control Register S5RIC XXXX X000b

000083h UART3 Transmit/NACK Interrupt Control Register S3TIC XXXX X000b

000084h UART6 Receive/ACK Interrupt Control Register S6RIC XXXX X000b

000085h UART4 Transmit/NACK Interrupt Control Register S4TIC XXXX X000b

000086h

000087h UART2 Bus Collision, START Condition/STOP Condition

Detection Interrupt Control Register

BCN2IC XXXX X000b

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 31 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.3 SFR List (3)

Address Register Symbol Reset Value

000088h DMA1 Transfer Complete Interrupt Control Register DM1IC XXXX X000b

000089h UART1/4 Bus Collision, START Condition/STOP Condition

Detection Interrupt Control Register

BCN1IC/BCN4IC XXXX X000b

00008Ah DMA3 Transfer Complete Interrupt Control Register DM3IC XXXX X000b

00008Bh Key Input Interrupt Control Register KUPIC XXXX X000b

00008Ch Timer A1 Interrupt Control Register TA1IC XXXX X000b

00008Dh Intelligent I/O Interrupt Control Register 1 IIO1IC XXXX X000b

00008Eh Timer A3 Interrupt Control Register TA3IC XXXX X000b

00008Fh Intelligent I/O Interrupt Control Register 3 IIO3IC XXXX X000b

000090h UART0 Transmit/NACK Interrupt Control Register S0TIC XXXX X000b

000091h Intelligent I/O Interrupt Control Register 5 IIO5IC XXXX X000b

000092h UART1 Transmit/NACK Interrupt Control Register S1TIC XXXX X000b

000093h Intelligent I/O Interrupt Control Register 7 IIO7IC XXXX X000b

000094h Timer B0 Interrupt Control Register TB0IC XXXX X000b

000095h Intelligent I/O Interrupt Control Register 9 IIO9IC XXXX X000b

000096h Timer B2 Interrupt Control Register TB2IC XXXX X000b

000097h Intelligent I/O Interrupt Control Register 11 IIO11IC XXXX X000b

000098h Timer B4 Interrupt Control Register TB4IC XXXX X000b

000099h

00009Ah INT4 Interrupt Control Register INT4IC XX00 X000b

00009Bh

00009Ch INT2 Interrupt Control Register INT2IC XX00 X000b

00009Dh

00009Eh INT0 Interrupt Control Register INT0IC XX00 X000b

00009Fh

0000A0h Intelligent I/O Interrupt Request Register 0 IIO0IR 0000 0XX1b

0000A1h Intelligent I/O Interrupt Request Register 1 IIO1IR 0000 0XX1b

0000A2h Intelligent I/O Interrupt Request Register 2 IIO2IR 0000 0X01b

0000A3h Intelligent I/O Interrupt Request Register 3 IIO3IR 0000 XXX1b

0000A4h Intelligent I/O Interrupt Request Register 4 IIO4IR 000X 0XX1b

0000A5h Intelligent I/O Interrupt Request Register 5 IIO5IR 000X 0XX1b

0000A6h Intelligent I/O Interrupt Request Register 6 IIO6IR 000X 0XX1b

0000A7h Intelligent I/O Interrupt Request Register 7 IIO7IR X00X 0XX1b

0000A8h Intelligent I/O Interrupt Request Register 8 IIO8IR XX0X 0XX1b

0000A9h Intelligent I/O Interrupt Request Register 9 IIO9IR 0X00 0XX1b

0000AAh Intelligent I/O Interrupt Request Register 10 IIO10IR 0X00 0XX1b

0000ABh Intelligent I/O Interrupt Request Register 11 IIO11IR 0X00 0XX1b

0000ACh

0000ADh

0000AEh

0000AFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 32 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.4 SFR List (4)

Address Register Symbol Reset Value

0000B0h Intelligent I/O Interrupt Enable Register 0 IIO0IE 00h

0000B1h Intelligent I/O Interrupt Enable Register 1 IIO1IE 00h

0000B2h Intelligent I/O Interrupt Enable Register 2 IIO2IE 00h

0000B3h Intelligent I/O Interrupt Enable Register 3 IIO3IE 00h

0000B4h Intelligent I/O Interrupt Enable Register 4 IIO4IE 00h

0000B5h Intelligent I/O Interrupt Enable Register 5 IIO5IE 00h

0000B6h Intelligent I/O Interrupt Enable Register 6 IIO6IE 00h

0000B7h Intelligent I/O Interrupt Enable Register 7 IIO7IE 00h

0000B8h Intelligent I/O Interrupt Enable Register 8 IIO8IE 00h

0000B9h Intelligent I/O Interrupt Enable Register 9 IIO9IE 00h

0000BAh Intelligent I/O Interrupt Enable Register 10 IIO10IE 00h

0000BBh Intelligent I/O Interrupt Enable Register 11 IIO11IE 00h

0000BCh

0000BDh

0000BEh

0000BFh

0000C0h

0000C1h CAN0 Transmit Interrupt Control Register C0TIC XXXX X000b

0000C2h

0000C3h CAN0 Error Interrupt Control Register C0EIC XXXX X000b

0000C4h

0000C5h

0000C6h

0000C7h

0000C8h

0000C9h

0000CAh

0000CBh

0000CCh

0000CDh

0000CEh

0000CFh

0000D0h CAN0 Transmit FIFO Interrupt Control Register C0FTIC XXXX X000b

0000D1h

0000D2h

0000D3h

0000D4h

0000D5h

0000D6h

0000D7h

0000D8h

0000D9h

0000DAh

0000DBh

0000DCh

0000DDh UART7 Transmit Interrupt Control Register S7TIC XXXX X000b

0000DEh INT7 Interrupt Control Register INT7IC XX00 X000b

0000DFh UART8 Transmit Interrupt Control Register S8TIC XXXX X000b

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 33 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.5 SFR List (5)

Address Register Symbol Reset Value

0000E0h

0000E1h CAN0 Receive Interrupt Control Register C0RIC XXXX X000b

0000E2h

0000E3h

0000E4h

0000E5h

0000E6h

0000E7h

0000E8h

0000E9h

0000EAh

0000EBh

0000ECh

0000EDh

0000EEh

0000EFh

0000F0h CAN0 Receive FIFO Interrupt Control Register C0FRIC XXXX X000b

0000F1h

0000F2h

0000F3h

0000F4h

0000F5h

0000F6h

0000F7h

0000F8h

0000F9h

0000FAh

0000FBh

0000FCh INT8 Interrupt Control Register INT8IC XX00 X000b

0000FDh UART7 Receive Interrupt Control Register S7RIC XXXX X000b

0000FEh INT6 Interrupt Control Register INT6IC XX00 X000b

0000FFh UART8 Receive Interrupt Control Register S8RIC XXXX X000b

000100h Group 1 Time Measurement/Waveform Generation Register 0 G1TM0/G1PO0 XXXXh

000101h

000102h Group 1 Time Measurement/Waveform Generation Register 1 G1TM1/G1PO1 XXXXh

000103h

000104h Group 1 Time Measurement/Waveform Generation Register 2 G1TM2/G1PO2 XXXXh

000105h

000106h Group 1 Time Measurement/Waveform Generation Register 3 G1TM3/G1PO3 XXXXh

000107h

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 34 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.6 SFR List (6)

Address Register Symbol Reset Value

000108h Group 1 Time Measurement/Waveform Generation Register 4 G1TM4/G1PO4 XXXXh

000109h

00010Ah Group 1 Time Measurement/Waveform Generation Register 5 G1TM5/G1PO5 XXXXh

00010Bh

00010Ch Group 1 Time Measurement/Waveform Generation Register 6 G1TM6/G1PO6 XXXXh

00010Dh

00010Eh Group 1 Time Measurement/Waveform Generation Register 7 G1TM7/G1PO7 XXXXh

00010Fh

000110h Group 1 Waveform Generation Control Register 0 G1POCR0 0000 X000b

000111h Group 1 Waveform Generation Control Register 1 G1POCR1 0X00 X000b

000112h Group 1 Waveform Generation Control Register 2 G1POCR2 0X00 X000b

000113h Group 1 Waveform Generation Control Register 3 G1POCR3 0X00 X000b

000114h Group 1 Waveform Generation Control Register 4 G1POCR4 0X00 X000b

000115h Group 1 Waveform Generation Control Register 5 G1POCR5 0X00 X000b

000116h Group 1 Waveform Generation Control Register 6 G1POCR6 0X00 X000b

000117h Group 1 Waveform Generation Control Register 7 G1POCR7 0X00 X000b

000118h Group 1 Time Measurement Control Register 0 G1TMCR0 00h

000119h Group 1 Time Measurement Control Register 1 G1TMCR1 00h

00011Ah Group 1 Time Measurement Control Register 2 G1TMCR2 00h

00011Bh Group 1 Time Measurement Control Register 3 G1TMCR3 00h

00011Ch Group 1 Time Measurement Control Register 4 G1TMCR4 00h

00011Dh Group 1 Time Measurement Control Register 5 G1TMCR5 00h

00011Eh Group 1 Time Measurement Control Register 6 G1TMCR6 00h

00011Fh Group 1 Time Measurement Control Register 7 G1TMCR7 00h

000120h Group 1 Base Timer Register G1BT XXXXh

000121h

000122h Group 1 Base Timer Control Register 0 G1BCR0 0000 0000b

000123h Group 1 Base Timer Control Register 1 G1BCR1 0000 0000b

000124h Group 1 Time Measurement Prescaler Register 6 G1TPR6 00h

000125h Group 1 Time Measurement Prescaler Register 7 G1TPR7 00h

000126h Group 1 Function Enable Register G1FE 00h

000127h Group 1 Function Select Register G1FS 00h

000128h

000129h

00012Ah

00012Bh

00012Ch

00012Dh

00012Eh

00012Fh

000130h to

00013Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 35 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.7 SFR List (7)

Address Register Symbol Reset Value

000140h Group 2 Waveform Generation Register 0 G2PO0 XXXXh

000141h

000142h Group 2 Waveform Generation Register 1 G2PO1 XXXXh

000143h

000144h Group 2 Waveform Generation Register 2 G2PO2 XXXXh

000145h

000146h Group 2 Waveform Generation Register 3 G2PO3 XXXXh

000147h

000148h Group 2 Waveform Generation Register 4 G2PO4 XXXXh

000149h

00014Ah Group 2 Waveform Generation Register 5 G2PO5 XXXXh

00014Bh

00014Ch Group 2 Waveform Generation Register 6 G2PO6 XXXXh

00014Dh

00014Eh Group 2 Waveform Generation Register 7 G2PO7 XXXXh

00014Fh

000150h Group 2 Waveform Generation Control Register 0 G2POCR0 0000 0000b

000151h Group 2 Waveform Generation Control Register 1 G2POCR1 0000 0000b

000152h Group 2 Waveform Generation Control Register 2 G2POCR2 0000 0000b

000153h Group 2 Waveform Generation Control Register 3 G2POCR3 0000 0000b

000154h Group 2 Waveform Generation Control Register 4 G2POCR4 0000 0000b

000155h Group 2 Waveform Generation Control Register 5 G2POCR5 0000 0000b

000156h Group 2 Waveform Generation Control Register 6 G2POCR6 0000 0000b

000157h Group 2 Waveform Generation Control Register 7 G2POCR7 0000 0000b

000158h

000159h

00015Ah

00015Bh

00015Ch

00015Dh

00015Eh

00015Fh

000160h Group 2 Base Timer Register G2BT XXXXh

000161h

000162h Group 2 Base Timer Control Register 0 G2BCR0 0000 0000b

000163h Group 2 Base Timer Control Register 1 G2BCR1 0000 0000b

000164h Base Timer Start Register BTSR XXXX 0000b

000165h

000166h Group 2 Function Enable Register G2FE 00h

000167h Group 2 RTP Output Buffer Register G2RTP 00h

000168h

000169h

00016Ah Group 2 Serial Interface Mode Register G2MR 00XX X000b

00016Bh Group 2 Serial Interface Control Register G2CR 0000 X110b

00016Ch Group 2 SI/O Transmit Buffer Register G2TB XXXXh

00016Dh

00016Eh Group 2 SI/O Receive Buffer Register G2RB XXXXh

00016Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 36 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.8 SFR List (8)

Address Register Symbol Reset Value

000170h Group 2 IEBus Address Register IEAR XXXXh

000171h

000172h Group 2 IEBus Control Register IECR 00XX X000b

000173h Group 2 IEBus Transmit Interrupt Source Detect Register IETIF XXX0 0000b

000174h Group 2 IEBus Receive Interrupt Source Detect Register IERIF XXX0 0000b

000175h

000176h

000177h

000178h

000179h

00017Ah

00017Bh

00017Ch

00017Dh

00017Eh

00017Fh

000180h Group 0 Time Measurement/Waveform Generation Register 0 G0TM0/G0PO0 XXXXh

000181h

000182h Group 0 Time Measurement/Waveform Generation Register 1 G0TM1/G0PO1 XXXXh

000183h

000184h Group 0 Time Measurement/Waveform Generation Register 2 G0TM2/G0PO2 XXXXh

000185h

000186h Group 0 Time Measurement/Waveform Generation Register 3 G0TM3/G0PO3 XXXXh

000187h

000188h Group 0 Time Measurement/Waveform Generation Register 4 G0TM4/G0PO4 XXXXh

000189h

00018Ah Group 0 Time Measurement/Waveform Generation Register 5 G0TM5/G0PO5 XXXXh

00018Bh

00018Ch Group 0 Time Measurement/Waveform Generation Register 6 G0TM6/G0PO6 XXXXh

00018Dh

00018Eh Group 0 Time Measurement/Waveform Generation Register 7 G0TM7/G0PO7 XXXXh

00018Fh

000190h Group 0 Waveform Generation Control Register 0 G0POCR0 0000 X000b

000191h Group 0 Waveform Generation Control Register 1 G0POCR1 0X00 X000b

000192h Group 0 Waveform Generation Control Register 2 G0POCR2 0X00 X000b

000193h Group 0 Waveform Generation Control Register 3 G0POCR3 0X00 X000b

000194h Group 0 Waveform Generation Control Register 4 G0POCR4 0X00 X000b

000195h Group 0 Waveform Generation Control Register 5 G0POCR5 0X00 X000b

000196h Group 0 Waveform Generation Control Register 6 G0POCR6 0X00 X000b

000197h Group 0 Waveform Generation Control Register 7 G0POCR7 0X00 X000b

000198h Group 0 Time Measurement Control Register 0 G0TMCR0 00h

000199h Group 0 Time Measurement Control Register 1 G0TMCR1 00h

00019Ah Group 0 Time Measurement Control Register 2 G0TMCR2 00h

00019Bh Group 0 Time Measurement Control Register 3 G0TMCR3 00h

00019Ch Group 0 Time Measurement Control Register 4 G0TMCR4 00h

00019Dh Group 0 Time Measurement Control Register 5 G0TMCR5 00h

00019Eh Group 0 Time Measurement Control Register 6 G0TMCR6 00h

00019Fh Group 0 Time Measurement Control Register 7 G0TMCR7 00h

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 37 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.9 SFR List (9)

Address Register Symbol Reset Value

0001A0h Group 0 Base Timer Register G0BT XXXXh

0001A1h

0001A2h Group 0 Base Timer Control Register 0 G0BCR0 0000 0000b

0001A3h Group 0 Base Timer Control Register 1 G0BCR1 0000 0000b

0001A4h Group 0 Time Measurement Prescaler Register 6 G0TPR6 00h

0001A5h Group 0 Time Measurement Prescaler Register 7 G0TPR7 00h

0001A6h Group 0 Function Enable Register G0FE 00h

0001A7h Group 0 Function Select Register G0FS 00h

0001A8h

0001A9h

0001AAh

0001ABh

0001ACh

0001ADh

0001AEh

0001AFh

0001B0h

0001B1h

0001B2h

0001B3h

0001B4h

0001B5h

0001B6h

0001B7h

0001B8h

0001B9h

0001BAh

0001BBh

0001BCh

0001BDh

0001BEh

0001BFh

0001C0h

0001C1h

0001C2h

0001C3h

0001C4h UART5 Special Mode Register 4 U5SMR4 00h

0001C5h UART5 Special Mode Register 3 U5SMR3 00h

0001C6h UART5 Special Mode Register 2 U5SMR2 00h

0001C7h UART5 Special Mode Register U5SMR 00h

0001C8h UART5 Transmit/Receive Mode Register U5MR 00h

0001C9h UART5 Bit Rate Register U5BRG XXh

0001CAh UART5 Transmit Buffer Register U5TB XXXXh

0001CBh

0001CCh UART5 Transmit/Receive Control Register 0 U5C0 0000 1000b

0001CDh UART5 Transmit/Receive Control Register 1 U5C1 0000 0010b

0001CEh UART5 Receive Buffer Register U5RB XXXXh

0001CFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 38 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.10 SFR List (10)

Address Register Symbol Reset Value

0001D0h

0001D1h

0001D2h

0001D3h

0001D4h UART6 Special Mode Register 4 U6SMR4 00h

0001D5h UART6 Special Mode Register 3 U6SMR3 00h

0001D6h UART6 Special Mode Register 2 U6SMR2 00h

0001D7h UART6 Special Mode Register U6SMR 00h

0001D8h UART6 Transmit/Receive Mode Register U6MR 00h

0001D9h UART6 Bit Rate Register U6BRG XXh

0001DAh UART6 Transmit Buffer Register U6TB XXXXh

0001DBh

0001DCh UART6 Transmit/Receive Control Register 0 U6C0 0000 1000b

0001DDh UART6 Transmit/Receive Control Register 1 U6C1 0000 0010b

0001DEh UART6 Receive Buffer Register U6RB XXXXh

0001DFh

0001E0h UART7 Transmit/Receive Mode Register U7MR 00h

0001E1h UART7 Bit Rate Register U7BRG XXh

0001E2h UART7 Transmit Buffer Register U7TB XXXXh

0001E3h

0001E4h UART7 Transmit/Receive Control Register 0 U7C0 00X0 1000b

0001E5h UART7 Transmit/Receive Control Register 1 U7C1 XXXX 0010b

0001E6h UART7 Receive Buffer Register U7RB XXXXh

0001E7h

0001E8h UART8 Transmit/Receive Mode Register U8MR 00h

0001E9h UART8 Bit Rate Register U8BRG XXh

0001EAh UART8 Transmit Buffer Register U8TB XXXXh

0001EBh

0001ECh UART8 Transmit/Receive Control Register 0 U8C0 00X0 1000b

0001EDh UART8 Transmit/Receive Control Register 1 U8C1 XXXX 0010b

0001EEh UART8 Receive Buffer Register U8RB XXXXh

0001EFh

0001F0h UART7, UART8 Transmit/Receive Control Register 2 U78CON X000 0000b

0001F1h

0001F2h

0001F3h

0001F4h

0001F5h

0001F6h

0001F7h

0001F8h

0001F9h

0001FAh

0001FBh

0001FCh

0001FDh

0001FEh

0001FFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 39 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.11 SFR List (11)

Address Register Symbol Reset Value

000200h to

0002BFh

0002C0h X0 Register/Y0 Register X0R/Y0R XXXXh

0002C1h

0002C2h X1 Register/Y1 Register X1R/Y1R XXXXh

0002C3h

0002C4h X2 Register/Y2 Register X2R/Y2R XXXXh

0002C5h

0002C6h X3 Register/Y3 Register X3R/Y3R XXXXh

0002C7h

0002C8h X4 Register/Y4 Register X4R/Y4R XXXXh

0002C9h

0002CAh X5 Register/Y5 Register X5R/Y5R XXXXh

0002CBh

0002CCh X6 Register/Y6 Register X6R/Y6R XXXXh

0002CDh

0002CEh X7 Register/Y7 Register X7R/Y7R XXXXh

0002CFh

0002D0h X8 Register/Y8 Register X8R/Y8R XXXXh

0002D1h

0002D2h X9 Register/Y9 Register X9R/Y9R XXXXh

0002D3h

0002D4h X10 Register/Y10 Register X10R/Y10R XXXXh

0002D5h

0002D6h X11 Register/Y11 Register X11R/Y11R XXXXh

0002D7h

0002D8h X12 Register/Y12 Register X12R/Y12R XXXXh

0002D9h

0002DAh X13 Register/Y13 Register X13R/Y13R XXXXh

0002DBh

0002DCh X14 Register/Y14 Register X14R/Y14R XXXXh

0002DDh

0002DEh X15 Register/Y15 Register X15R/Y15R XXXXh

0002DFh

0002E0h X-Y Control Register XYC XXXX XX00b

0002E1h

0002E2h

0002E3h

0002E4h UART1 Special Mode Register 4 U1SMR4 00h

0002E5h UART1 Special Mode Register 3 U1SMR3 00h

0002E6h UART1 Special Mode Register 2 U1SMR2 00h

0002E7h UART1 Special Mode Register U1SMR 00h

0002E8h UART1 Transmit/Receive Mode Register U1MR 00h

0002E9h UART1 Bit Rate Register U1BRG XXh

0002EAh UART1 Transmit Buffer Register U1TB XXXXh

0002EBh

0002ECh UART1 Transmit/Receive Control Register 0 U1C0 0000 1000b

0002EDh UART1 Transmit/Receive Control Register 1 U1C1 0000 0010b

0002EEh UART1 Receive Buffer Register U1RB XXXXh

0002EFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 40 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.12 SFR List (12)

Address Register Symbol Reset Value

0002F0h

0002F1h

0002F2h

0002F3h

0002F4h UART4 Special Mode Register 4 U4SMR4 00h

0002F5h UART4 Special Mode Register 3 U4SMR3 00h

0002F6h UART4 Special Mode Register 2 U4SMR2 00h

0002F7h UART4 Special Mode Register U4SMR 00h

0002F8h UART4 Transmit/Receive Mode Register U4MR 00h

0002F9h UART4 Bit Rate Register U4BRG XXh

0002FAh UART4 Transmit Buffer Register U4TB XXXXh

0002FBh

0002FCh UART4 Transmit/Receive Control Register 0 U4C0 0000 1000b

0002FDh UART4 Transmit/Receive Control Register 1 U4C1 0000 0010b

0002FEh UART4 Receive Buffer Register U4RB XXXXh

0002FFh

000300h Count Start Register for Timers B3, B4, and B5 TBSR 000X XXXXb

000301h

000302h Timer A1-1 Register TA11 XXXXh

000303h

000304h Timer A2-1 Register TA21 XXXXh

000305h

000306h Timer A4-1 Register TA41 XXXXh

000307h

000308h Three-phase PWM Control Register 0 INVC0 00h

000309h Three-phase PWM Control Register 1 INVC1 00h

00030Ah Three-phase Output Buffer Register 0 IDB0 XX11 1111b

00030Bh Three-phase Output Buffer Register 1 IDB1 XX11 1111b

00030Ch Dead Time Timer DTT XXh

00030Dh Timer B2 Interrupt Generating Frequency Set Counter ICTB2 XXh

00030Eh

00030Fh

000310h Timer B3 Register TB3 XXXXh

000311h

000312h Timer B4 Register TB4 XXXXh

000313h

000314h Timer B5 Register TB5 XXXXh

000315h

000316h

000317h

000318h

000319h

00031Ah

00031Bh Timer B3 Mode Register TB3MR 00XX 0000b

00031Ch Timer B4 Mode Register TB4MR 00XX 0000b

00031Dh Timer B5 Mode Register TB5MR 00XX 0000b

00031Eh

00031Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 41 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.13 SFR List (13)

Address Register Symbol Reset Value

000320h

000321h

000322h

000323h

000324h UART3 Special Mode Register 4 U3SMR4 00h

000325h UART3 Special Mode Register 3 U3SMR3 00h

000326h UART3 Special Mode Register 2 U3SMR2 00h

000327h UART3 Special Mode Register U3SMR 00h

000328h UART3 Transmit/Receive Mode Register U3MR 00h

000329h UART3 Bit Rate Register U3BRG XXh

00032Ah UART3 Transmit Buffer Register U3TB XXXXh

00032Bh

00032Ch UART3 Transmit/Receive Control Register 0 U3C0 0000 1000b

00032Dh UART3 Transmit/Receive Control Register 1 U3C1 0000 0010b

00032Eh UART3 Receive Buffer Register U3RB XXXXh

00032Fh

000330h

000331h

000332h

000333h

000334h UART2 Special Mode Register 4 U2SMR4 00h

000335h UART2 Special Mode Register 3 U2SMR3 00h

000336h UART2 Special Mode Register 2 U2SMR2 00h

000337h UART2 Special Mode Register U2SMR 00h

000338h UART2 Transmit/Receive Mode Register U2MR 00h

000339h UART2 Bit Rate Register U2BRG XXh

00033Ah UART2 Transmit Buffer Register U2TB XXXXh

00033Bh

00033Ch UART2 Transmit/Receive Control Register 0 U2C0 0000 1000b

00033Dh UART2 Transmit/Receive Control Register 1 U2C1 0000 0010b

00033Eh UART2 Receive Buffer Register U2RB XXXXh

00033Fh

000340h Count Start Register TABSR 0000 0000b

000341h Clock Prescaler Reset Register CPSRF 0XXX XXXXb

000342h One-shot Start Register ONSF 0000 0000b

000343h Trigger Select Register TRGSR 0000 0000b

000344h Increment/Decrement Select Register UDF 0000 0000b

000345h

000346h Timer A0 Register TA0 XXXXh

000347h

000348h Timer A1 Register TA1 XXXXh

000349h

00034Ah Timer A2 Register TA2 XXXXh

00034Bh

00034Ch Timer A3 Register TA3 XXXXh

00034Dh

00034Eh Timer A4 Register TA4 XXXXh

00034Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 42 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.14 SFR List (14)

Address Register Symbol Reset Value

000350h Timer B0 Register TB0 XXXXh

000351h

000352h Timer B1 Register TB1 XXXXh

000353h

000354h Timer B2 Register TB2 XXXXh

000355h

000356h Timer A0 Mode Register TA0MR 0000 0000b

000357h Timer A1 Mode Register TA1MR 0000 0000b

000358h Timer A2 Mode Register TA2MR 0000 0000b

000359h Timer A3 Mode Register TA3MR 0000 0000b

00035Ah Timer A4 Mode Register TA4MR 0000 0000b

00035Bh Timer B0 Mode Register TB0MR 00XX 0000b

00035Ch Timer B1 Mode Register TB1MR 00XX 0000b

00035Dh Timer B2 Mode Register TB2MR 00XX 0000b

00035Eh Timer B2 Special Mode Register TB2SC XXXX XXX0b

00035Fh Count Source Prescaler Register TCSPR 0000 0000b

000360h

000361h

000362h

000363h

000364h UART0 Special Mode Register 4 U0SMR4 00h

000365h UART0 Special Mode Register 3 U0SMR3 00h

000366h UART0 Special Mode Register 2 U0SMR2 00h

000367h UART0 Special Mode Register U0SMR 00h

000368h UART0 Transmit/Receive Mode Register U0MR 00h

000369h UART0 Bit Rate Register U0BRG XXh

00036Ah UART0 Transmit Buffer Register U0TB XXXXh

00036Bh

00036Ch UART0 Transmit/Receive Control Register 0 U0C0 0000 1000b

00036Dh UART0 Transmit/Receive Control Register 1 U0C1 0000 0010b

00036Eh UART0 Receive Buffer Register U0RB XXXXh

00036Fh

000370h

000371h

000372h

000373h

000374h

000375h

000376h

000377h

000378h

000379h

00037Ah

00037Bh

00037Ch CRC Data Register CRCD XXXXh

00037Dh

00037Eh CRC Input Register CRCIN XXh

00037Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 43 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.15 SFR List (15)

Address Register Symbol Reset Value

000380h A/D0 Register 0 AD00 00XXh

000381h

000382h A/D0 Register 1 AD01 00XXh

000383h

000384h A/D0 Register 2 AD02 00XXh

000385h

000386h A/D0 Register 3 AD03 00XXh

000387h

000388h A/D0 Register 4 AD04 00XXh

000389h

00038Ah A/D0 Register 5 AD05 00XXh

00038Bh

00038Ch A/D0 Register 6 AD06 00XXh

00038Dh

00038Eh A/D0 Register 7 AD07 00XXh

00038Fh

000390h

000391h

000392h A/D0 Control Register 4 AD0CON4 XXXX 00XXb

000393h

000394h A/D0 Control Register 2 AD0CON2 XX0X X000b

000395h A/D0 Control Register 3 AD0CON3 XXXX X000b

000396h A/D0 Control Register 0 AD0CON0 00h

000397h A/D0 Control Register 1 AD0CON1 00h

000398h D/A Register 0 DA0 XXh

000399h

00039Ah D/A Register 1 DA1 XXh

00039Bh

00039Ch D/A Control Register DACON XXXX XX00b

00039Dh

00039Eh

00039Fh

0003A0h

0003A1h

0003A2h

0003A3h

0003A4h

0003A5h

0003A6h

0003A7h

0003A8h

0003A9h

0003AAh

0003ABh

0003ACh

0003ADh

0003AEh

0003AFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 44 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.16 SFR List (16)

Address Register Symbol Reset Value

0003B0h

0003B1h

0003B2h

0003B3h

0003B4h

0003B5h

0003B6h

0003B7h

0003B8h

0003B9h

0003BAh

0003BBh

0003BCh

0003BDh

0003BEh

0003BFh

0003C0h Port P0 Register P0 XXh

0003C1h Port P1 Register P1 XXh

0003C2h Port P0 Direction Register PD0 0000 0000b

0003C3h Port P1 Direction Register PD1 0000 0000b

0003C4h Port P2 Register P2 XXh

0003C5h Port P3 Register P3 XXh

0003C6h Port P2 Direction Register PD2 0000 0000b

0003C7h Port P3 Direction Register PD3 0000 0000b

0003C8h Port P4 Register P4 XXh

0003C9h Port P5 Register P5 XXh

0003CAh Port P4 Direction Register PD4 0000 0000b

0003CBh Port P5 Direction Register PD5 0000 0000b

0003CCh Port P6 Register P6 XXh

0003CDh Port P7 Register P7 XXh

0003CEh Port P6 Direction Register PD6 0000 0000b

0003CFh Port P7 Direction Register PD7 0000 0000b

0003D0h Port P8 Register P8 XXh

0003D1h Port P9 Register P9 XXh

0003D2h Port P8 Direction Register PD8 00X0 0000b

0003D3h Port P9 Direction Register PD9 0000 0000b

0003D4h Port P10 Register P10 XXh

0003D5h Port P11 Register P11 XXh

0003D6h Port P10 Direction Register PD10 0000 0000b

0003D7h Port P11 Direction Register PD11 XXX0 0000b

0003D8h Port P12 Register P12 XXh

0003D9h Port P13 Register P13 XXh

0003DAh Port P12 Direction Register PD12 0000 0000b

0003DBh Port P13 Direction Register PD13 0000 0000b

0003DCh Port P14 Register P14 XXh

0003DDh Port P15 Register P15 XXh

0003DEh Port P14 Direction Register PD14 X000 0000b

0003DFh Port P15 Direction Register PD15 0000 0000b

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 45 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.17 SFR List (17)

Address Register Symbol Reset Value

0003E0h

0003E1h

0003E2h

0003E3h

0003E4h

0003E5h

0003E6h

0003E7h

0003E8h

0003E9h

0003EAh

0003EBh

0003ECh

0003EDh

0003EEh

0003EFh

0003F0h Pull-up Control Register 0 PUR0 0000 0000b

0003F1h Pull-up Control Register 1 PUR1 XXXX X0XXb

0003F2h Pull-up Control Register 2 PUR2 000X XXXXb

0003F3h Pull-up Control Register 3 PUR3 0000 0000b

0003F4h Pull-up Control Register 4 PUR4 XXXX 0000b

0003F5h

0003F6h

0003F7h

0003F8h

0003F9h

0003FAh

0003FBh

0003FCh

0003FDh

0003FEh

0003FFh Port Control Register PCR 0XXX XXX0b

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 46 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Note:

1. The reset value reflects the value of the protect bit for each block in the flash memory.

Table 4.18 SFR List (18)

Address Register Symbol Reset Value

040000h Flash Memory Control Register 0 FMR0 0X01 XX00b

040001h Flash Memory Status Register 0 FMSR0 1000 0000b

040002h

040003h

040004h

040005h

040006h

040007h

040008h Flash Register Protection Unlock Register 0 FPR0 00h

040009h Flash Memory Control Register 1 FMR1 0000 0010b

04000Ah Block Protect Bit Monitor Register 0 FBPM0 ??X? ????b (1)

04000Bh Block Protect Bit Monitor Register 1 FBPM1 XXX? ????b (1)

04000Ch

04000Dh

04000Eh

04000Fh

040010h

040011h Block Protect Bit Monitor Register 2 FBPM2 ???? ????b (1)

040012h

040013h

040014h

040015h

040016h

040017h

040018h

040019h

04001Ah

04001Bh

04001Ch

04001Dh

04001Eh

04001Fh

040020h PLL Control Register 0 PLC0 0000 0001b

040021h PLL Control Register 1 PLC1 0001 1111b

040022h

040023h

040024h

040025h

040026h

040027h

040028h

040029h

04002Ah

04002Bh

04002Ch

04002Dh

04002Eh

04002Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 47 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Note:

1. The value in the PM0 register is retained even after a software reset or watchdog timer reset.

Table 4.19 SFR List (19)

Address Register Symbol Reset Value

040030h to

04003Fh

040040h

040041h

040042h

040043h

040044h Processor Mode Register 0 (1) PM0 1000 0000b

(CNVSS pin = Low)

0000 0011b

(CNVSS pin = High)

040045h

040046h System Clock Control Register 0 CM0 0000 1000b

040047h System Clock Control Register 1 CM1 0010 0000b

040048h Processor Mode Register 3 PM3 00h

040049h

04004Ah Protect Register PRCR XXXX X000b

04004Bh

04004Ch Protect Register 3 PRCR3 0000 0000b

04004Dh Oscillator Stop Detection Register CM2 00h

04004Eh

04004Fh

040050h

040051h

040052h

040053h Processor Mode Register 2 PM2 00h

040054h Chip Select Output Pin Setting Register 0 CSOP0 1000 XXXXb

040055h Chip Select Output Pin Setting Register 1 CSOP1 01X0 XXXXb

040056h Chip Select Output Pin Setting Register 2 CSOP2 XXXX 0000b

040057h

040058h

040059h

04005Ah Low Speed Mode Clock Control Register CM3 XXXX XX00b

04005Bh

04005Ch

04005Dh

04005Eh

04005Fh

040060h Voltage Regulator Control Register VRCR 0000 0000b

040061h

040062h Low Voltage Detector Control Register LVDC 0000 XX00b

040063h

040064h Detection Voltage Configuration Register DVCR 0000 XXXXb

040065h

040066h

040067h

040068h to

040093h

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 48 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.20 SFR List (20)

Address Register Symbol Reset Value

040094h

040095h

040096h

040097h Three-phase Output Buffer Control Register IOBC 0XXX XXXXb

040098h Input Function Select Register 0 IFS0 X000 0000b

040099h Input Function Select Register 1 IFS1 XXXX X0X0b

04009Ah Input Function Select Register 2 IFS2 0000 00X0b

04009Bh Input Function Select Register 3 IFS3 XXXX XX00b

04009Ch

04009Dh

04009Eh

04009Fh

0400A0h Port P0_0 Function Select Register P0_0S 0XXX X000b

0400A1h Port P1_0 Function Select Register P1_0S XXXX X000b

0400A2h Port P0_1 Function Select Register P0_1S 0XXX X000b

0400A3h Port P1_1 Function Select Register P1_1S XXXX X000b

0400A4h Port P0_2 Function Select Register P0_2S 0XXX X000b

0400A5h Port P1_2 Function Select Register P1_2S XXXX X000b

0400A6h Port P0_3 Function Select Register P0_3S 0XXX X000b

0400A7h Port P1_3 Function Select Register P1_3S XXXX X000b

0400A8h Port P0_4 Function Select Register P0_4S 0XXX X000b

0400A9h Port P1_4 Function Select Register P1_4S XXXX X000b

0400AAh Port P0_5 Function Select Register P0_5S 0XXX X000b

0400ABh Port P1_5 Function Select Register P1_5S XXXX X000b

0400ACh Port P0_6 Function Select Register P0_6S 0XXX X000b

0400ADh Port P1_6 Function Select Register P1_6S XXXX X000b

0400AEh Port P0_7 Function Select Register P0_7S 0XXX X000b

0400AFh Port P1_7 Function Select Register P1_7S XXXX X000b

0400B0h Port P2_0 Function Select Register P2_0S 0XXX X000b

0400B1h Port P3_0 Function Select Register P3_0S XXXX X000b

0400B2h Port P2_1 Function Select Register P2_1S 0XXX X000b

0400B3h Port P3_1 Function Select Register P3_1S XXXX X000b

0400B4h Port P2_2 Function Select Register P2_2S 0XXX X000b

0400B5h Port P3_2 Function Select Register P3_2S XXXX X000b

0400B6h Port P2_3 Function Select Register P2_3S 0XXX X000b

0400B7h Port P3_3 Function Select Register P3_3S XXXX X000b

0400B8h Port P2_4 Function Select Register P2_4S 0XXX X000b

0400B9h Port P3_4 Function Select Register P3_4S XXXX X000b

0400BAh Port P2_5 Function Select Register P2_5S 0XXX X000b

0400BBh Port P3_5 Function Select Register P3_5S XXXX X000b

0400BCh Port P2_6 Function Select Register P2_6S 0XXX X000b

0400BDh Port P3_6 Function Select Register P3_6S XXXX X000b

0400BEh Port P2_7 Function Select Register P2_7S 0XXX X000b

0400BFh Port P3_7 Function Select Register P3_7S XXXX X000b

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 49 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.21 SFR List (21)

Address Register Symbol Reset Value

0400C0h Port P4_0 Function Select Register P4_0S X0XX X000b

0400C1h Port P5_0 Function Select Register P5_0S XXXX X000b

0400C2h Port P4_1 Function Select Register P4_1S X0XX X000b

0400C3h Port P5_1 Function Select Register P5_1S XXXX X000b

0400C4h Port P4_2 Function Select Register P4_2S X0XX X000b

0400C5h Port P5_2 Function Select Register P5_2S XXXX X000b

0400C6h Port P4_3 Function Select Register P4_3S X0XX X000b

0400C7h Port P5_3 Function Select Register P5_3S XXXX X000b

0400C8h Port P4_4 Function Select Register P4_4S X0XX X000b

0400C9h Port P5_4 Function Select Register P5_4S X0XX X000b

0400CAh Port P4_5 Function Select Register P4_5S X0XX X000b

0400CBh Port P5_5 Function Select Register P5_5S X0XX X000b

0400CCh Port P4_6 Function Select Register P4_6S X0XX X000b

0400CDh Port P5_6 Function Select Register P5_6S X0XX X000b

0400CEh Port P4_7 Function Select Register P4_7S X0XX X000b

0400CFh Port P5_7 Function Select Register P5_7S X0XX X000b

0400D0h Port P6_0 Function Select Register P6_0S X0XX X000b

0400D1h Port P7_0 Function Select Register P7_0S X0XX X000b

0400D2h Port P6_1 Function Select Register P6_1S X0XX X000b

0400D3h Port P7_1 Function Select Register P7_1S X0XX X000b

0400D4h Port P6_2 Function Select Register P6_2S X0XX X000b

0400D5h Port P7_2 Function Select Register P7_2S X0XX X000b

0400D6h Port P6_3 Function Select Register P6_3S X0XX X000b

0400D7h Port P7_3 Function Select Register P7_3S X0XX X000b

0400D8h Port P6_4 Function Select Register P6_4S X0XX X000b

0400D9h Port P7_4 Function Select Register P7_4S X0XX X000b

0400DAh Port P6_5 Function Select Register P6_5S X0XX X000b

0400DBh Port P7_5 Function Select Register P7_5S X0XX X000b

0400DCh Port P6_6 Function Select Register P6_6S X0XX X000b

0400DDh Port P7_6 Function Select Register P7_6S X0XX X000b

0400DEh Port P6_7 Function Select Register P6_7S X0XX X000b

0400DFh Port P7_7 Function Select Register P7_7S X0XX X000b

0400E0h Port P8_0 Function Select Register P8_0S X0XX X000b

0400E1h Port P9_0 Function Select Register P9_0S X0XX X000b

0400E2h Port P8_1 Function Select Register P8_1S X0XX X000b

0400E3h Port P9_1 Function Select Register P9_1S X0XX X000b

0400E4h Port P8_2 Function Select Register P8_2S X0XX X000b

0400E5h Port P9_2 Function Select Register P9_2S X0XX X000b

0400E6h Port P8_3 Function Select Register P8_3S X0XX X000b

0400E7h Port P9_3 Function Select Register P9_3S 00XX X000b

0400E8h Port P8_4 Function Select Register P8_4S XXXX X000b

0400E9h Port P9_4 Function Select Register P9_4S 00XX X000b

0400EAh

0400EBh Port P9_5 Function Select Register P9_5S 00XX X000b

0400ECh Port P8_6 Function Select Register P8_6S XXXX X000b

0400EDh Port P9_6 Function Select Register P9_6S 00XX X000b

0400EEh Port P8_7 Function Select Register P8_7S XXXX X000b

0400EFh Port P9_7 Function Select Register P9_7S X0XX X000b

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 50 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.22 SFR List (22)

Address Register Symbol Reset Value

0400F0h Port P10_0 Function Select Register P10_0S 0XXX X000b

0400F1h Port P11_0 Function Select Register P11_0S X0XX X000b

0400F2h Port P10_1 Function Select Register P10_1S 0XXX X000b

0400F3h Port P11_1 Function Select Register P11_1S X0XX X000b

0400F4h Port P10_2 Function Select Register P10_2S 0XXX X000b

0400F5h Port P11_2 Function Select Register P11_2S X0XX X000b

0400F6h Port P10_3 Function Select Register P10_3S 0XXX X000b

0400F7h Port P11_3 Function Select Register P11_3S X0XX X000b

0400F8h Port P10_4 Function Select Register P10_4S 0XXX X000b

0400F9h Port P11_4 Function Select Register P11_4S XXXX X000b

0400FAh Port P10_5 Function Select Register P10_5S 0XXX X000b

0400FBh

0400FCh Port P10_6 Function Select Register P10_6S 0XXX X000b

0400FDh

0400FEh Port P10_7 Function Select Register P10_7S 0XXX X000b

0400FFh

040100h Port P12_0 Function Select Register P12_0S X0XX X000b

040101h Port P13_0 Function Select Register P13_0S XXXX X000b

040102h Port P12_1 Function Select Register P12_1S X0XX X000b

040103h Port P13_1 Function Select Register P13_1S XXXX X000b

040104h Port P12_2 Function Select Register P12_2S X0XX X000b

040105h Port P13_2 Function Select Register P13_2S XXXX X000b

040106h Port P12_3 Function Select Register P12_3S X0XX X000b

040107h Port P13_3 Function Select Register P13_3S XXXX X000b

040108h Port P12_4 Function Select Register P12_4S XXXX X000b

040109h Port P13_4 Function Select Register P13_4S XXXX X000b

04010Ah Port P12_5 Function Select Register P12_5S XXXX X000b

04010Bh Port P13_5 Function Select Register P13_5S XXXX X000b

04010Ch Port P12_6 Function Select Register P12_6S XXXX X000b

04010Dh Port P13_6 Function Select Register P13_6S XXXX X000b

04010Eh Port P12_7 Function Select Register P12_7S XXXX X000b

04010Fh Port P13_7 Function Select Register P13_7S XXXX X000b

040110h

040111h Port P15_0 Function Select Register P15_0S 00XX X000b

040112h

040113h Port P15_1 Function Select Register P15_1S 00XX X000b

040114h

040115h Port P15_2 Function Select Register P15_2S 00XX X000b

040116h Port P14_3 Function Select Register P14_3S XXXX X000b

040117h Port P15_3 Function Select Register P15_3S 00XX X000b

040118h Port P14_4 Function Select Register P14_4S XXXX X000b

040119h Port P15_4 Function Select Register P15_4S 00XX X000b

04011Ah Port P14_5 Function Select Register P14_5S XXXX X000b

04011Bh Port P15_5 Function Select Register P15_5S 00XX X000b

04011Ch Port P14_6 Function Select Register P14_6S XXXX X000b

04011Dh Port P15_6 Function Select Register P15_6S 00XX X000b

04011Eh

04011Fh Port P15_7 Function Select Register P15_7S 00XX X000b

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 51 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.23 SFR List (23)

Address Register Symbol Reset Value

040120h to

04403Fh

044040h

044041h

044042h

044043h

044044h

044045h

044046h

044047h

044048h

044049h

04404Ah

04404Bh

04404Ch

04404Dh

04404Eh Watchdog Timer Start Register WDTS XXXX XXXXb

04404Fh Watchdog Timer Control Register WDC 000X XXXXb

044050h

044051h

044052h

044053h

044054h

044055h

044056h

044057h

044058h

044059h

04405Ah

04405Bh

04405Ch

04405Dh

04405Eh

04405Fh Protect Register 2 PRCR2 0XXX XXXXb

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 52 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.24 SFR List (24)

Address Register Symbol Reset Value

044060h

044061h

044062h

044063h

044064h

044065h

044066h

044067h

044068h

044069h

04406Ah

04406Bh

04406Ch

04406Dh External Interrupt Request Source Select Register 1 IFSR1 X0XX X000b

04406Eh

04406Fh External Interrupt Request Source Select Register 0 IFSR0 0000 0000b

044070h DMA0 Request Source Select Register 2 DM0SL2 XX00 0000b

044071h DMA1 Request Source Select Register 2 DM1SL2 XX00 0000b

044072h DMA2 Request Source Select Register 2 DM2SL2 XX00 0000b

044073h DMA3 Request Source Select Register 2 DM3SL2 XX00 0000b

044074h

044075h

044076h

044077h

044078h DMA0 Request Source Select Register DM0SL XXX0 0000b

044079h DMA1 Request Source Select Register DM1SL XXX0 0000b

04407Ah DMA2 Request Source Select Register DM2SL XXX0 0000b

04407Bh DMA3 Request Source Select Register DM3SL XXX0 0000b

04407Ch

04407Dh Wake-up IPL Setting Register 2 RIPL2 XX0X 0000b

04407Eh

04407Fh Wake-up IPL Setting Register 1 RIPL1 XX0X 0000b

044080h

044081h

044082h

044083h

044084h

044085h

044086h

044087h

044088h

044089h

04408Ah

04408Bh

04408Ch

04408Dh

04408Eh

04408Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 53 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.25 SFR List (25)

Address Register Symbol Reset Value

044090h to

0443FFh

044400h I2C-bus Transmit/Receive Shift Register I2CTRSR XXh

044401h

044402h I2C-bus Slave Address Register I2CSAR 00h

044403h I2C-bus Control Register 0 I2CCR0 0000 0000b

044404h I2C-bus Clock Control Register I2CCCR 0000 0000b

044405h I2C-bus START and STOP Conditions Control Register I2CSSCR 0001 1010b

044406h I2C-bus Control Register 1 I2CCR1 0011 0000b

044407h I2C-bus Control Register 2 I2CCR2 0X00 0000b

044408h I2C-bus Status Register I2CSR 0001 000Xb

044409h

04440Ah

04440Bh

04440Ch

04440Dh

04440Eh

04440Fh

044410h I2C-bus Mode Register I2CMR XXXX 0000b

044411h

044412h

044413h

044414h

044415h

044416h

044417h

044418h

044419h

04441Ah

04441Bh

04441Ch

04441Dh

04441Eh

04441Fh

044420h to

0467FFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 54 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.26 SFR List (26)

Address Register Symbol Reset Value

046800h to

047BFFh

047C00h CAN0 Mailbox 0: Message Identifier C0MB0 XXXX XXXXh

047C01h

047C02h

047C03h

047C04h

047C05h CAN0 Mailbox 0: Data Length XXh

047C06h CAN0 Mailbox 0: Data Field XXXX XXXX

XXXX XXXXh

047C07h

047C08h

047C09h

047C0Ah

047C0Bh

047C0Ch

047C0Dh

047C0Eh CAN0 Mailbox 0: Time Stamp XXXXh

047C0Fh

047C10h CAN0 Mailbox 1: Message Identifier C0MB1 XXXX XXXXh

047C11h

047C12h

047C13h

047C14h

047C15h CAN0 Mailbox 1: Data Length XXh

047C16h CAN0 Mailbox 1: Data Field XXXX XXXX

XXXX XXXXh

047C17h

047C18h

047C19h

047C1Ah

047C1Bh

047C1Ch

047C1Dh

047C1Eh CAN0 Mailbox 1: Time Stamp XXXXh

047C1Fh

047C20h CAN0 Mailbox 2: Message Identifier C0MB2 XXXX XXXXh

047C21h

047C22h

047C23h

047C24h

047C25h CAN0 Mailbox 2: Data Length XXh

047C26h CAN0 Mailbox 2: Data Field XXXX XXXX

XXXX XXXXh

047C27h

047C28h

047C29h

047C2Ah

047C2Bh

047C2Ch

047C2Dh

047C2Eh CAN0 Mailbox 2: Time Stamp XXXXh

047C2Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 55 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.27 SFR List (27)

Address Register Symbol Reset Value

047C30h CAN0 Mailbox 3: Message Identifier C0MB3 XXXX XXXXh

047C31h

047C32h

047C33h

047C34h

047C35h CAN0 Mailbox 3: Data Length XXh

047C36h CAN0 Mailbox 3: Data Field XXXX XXXX

XXXX XXXXh

047C37h

047C38h

047C39h

047C3Ah

047C3Bh

047C3Ch

047C3Dh

047C3Eh CAN0 Mailbox 3: Time Stamp XXXXh

047C3Fh

047C40h CAN0 Mailbox 4: Message Identifier C0MB4 XXXX XXXXh

047C41h

047C42h

047C43h

047C44h

047C45h CAN0 Mailbox 4: Data Length XXh

047C46h CAN0 Mailbox 4: Data Field XXXX XXXX

XXXX XXXXh

047C47h

047C48h

047C49h

047C4Ah

047C4Bh

047C4Ch

047C4Dh

047C4Eh CAN0 Mailbox 4: Time Stamp XXXXh

047C4Fh

047C50h CAN0 Mailbox 5: Message Identifier C0MB5 XXXX XXXXh

047C51h

047C52h

047C53h

047C54h

047C55h CAN0 Mailbox 5: Data Length XXh

047C56h CAN0 Mailbox 5: Data Field XXXX XXXX

XXXX XXXXh

047C57h

047C58h

047C59h

047C5Ah

047C5Bh

047C5Ch

047C5Dh

047C5Eh CAN0 Mailbox 5: Time Stamp XXXXh

047C5Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 56 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.28 SFR List (28)

Address Register Symbol Reset Value

047C60h CAN0 Mailbox 6: Message Identifier C0MB6 XXXX XXXXh

047C61h

047C62h

047C63h

047C64h

047C65h CAN0 Mailbox 6: Data Length XXh

047C66h CAN0 Mailbox 6: Data Field XXXX XXXX

XXXX XXXXh

047C67h

047C68h

047C69h

047C6Ah

047C6Bh

047C6Ch

047C6Dh

047C6Eh CAN0 Mailbox 6: Time Stamp XXXXh

047C6Fh

047C70h CAN0 Mailbox 7: Message Identifier C0MB7 XXXX XXXXh

047C71h

047C72h

047C73h

047C74h

047C75h CAN0 Mailbox 7: Data Length XXh

047C76h CAN0 Mailbox 7: Data Field XXXX XXXX

XXXX XXXXh

047C77h

047C78h

047C79h

047C7Ah

047C7Bh

047C7Ch

047C7Dh

047C7Eh CAN0 Mailbox 7: Time Stamp XXXXh

047C7Fh

047C80h CAN0 Mailbox 8: Message Identifier C0MB8 XXXX XXXXh

047C81h

047C82h

047C83h

047C84h

047C85h CAN0 Mailbox 8: Data Length XXh

047C86h CAN0 Mailbox 8: Data Field XXXX XXXX

XXXX XXXXh

047C87h

047C88h

047C89h

047C8Ah

047C8Bh

047C8Ch

047C8Dh

047C8Eh CAN0 Mailbox 8: Time Stamp XXXXh

047C8Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 57 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.29 SFR List (29)

Address Register Symbol Reset Value

047C90h CAN0 Mailbox 9: Message Identifier C0MB9 XXXX XXXXh

047C91h

047C92h

047C93h

047C94h

047C95h CAN0 Mailbox 9: Data Length XXh

047C96h CAN0 Mailbox 9: Data Field XXXX XXXX

XXXX XXXXh

047C97h

047C98h

047C99h

047C9Ah

047C9Bh

047C9Ch

047C9Dh

047C9Eh CAN0 Mailbox 9: Time Stamp XXXXh

047C9Fh

047CA0h CAN0 Mailbox 10: Message Identifier C0MB10 XXXX XXXXh

047CA1h

047CA2h

047CA3h

047CA4h

047CA5h CAN0 Mailbox 10: Data Length XXh

047CA6h CAN0 Mailbox 10: Data Field XXXX XXXX

XXXX XXXXh

047CA7h

047CA8h

047CA9h

047CAAh

047CABh

047CACh

047CADh

047CAEh CAN0 Mailbox 10: Time Stamp XXXXh

047CAFh

047CB0h CAN0 Mailbox 11: Message Identifier C0MB11 XXXX XXXXh

047CB1h

047CB2h

047CB3h

047CB4h

047CB5h CAN0 Mailbox 11: Data Length XXh

047CB6h CAN0 Mailbox 11: Data Field XXXX XXXX

XXXX XXXXh

047CB7h

047CB8h

047CB9h

047CBAh

047CBBh

047CBCh

047CBDh

047CBEh CAN0 Mailbox 11: Time Stamp XXXXh

047CBFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 58 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.30 SFR List (30)

Address Register Symbol Reset Value

047CC0h CAN0 Mailbox 12: Message Identifier C0MB12 XXXX XXXXh

047CC1h

047CC2h

047CC3h

047CC4h

047CC5h CAN0 Mailbox 12: Data Length XXh

047CC6h CAN0 Mailbox 12: Data Field XXXX XXXX

XXXX XXXXh

047CC7h

047CC8h

047CC9h

047CCAh

047CCBh

047CCCh

047CCDh

047CCEh CAN0 Mailbox 12: Time Stamp XXXXh

047CCFh

047CD0h CAN0 Mailbox 13: Message Identifier C0MB13 XXXX XXXXh

047CD1h

047CD2h

047CD3h

047CD4h

047CD5h CAN0 Mailbox 13: Data Length XXh

047CD6h CAN0 Mailbox 13: Data Field XXXX XXXX

XXXX XXXXh

047CD7h

047CD8h

047CD9h

047CDAh

047CDBh

047CDCh

047CDDh

047CDEh CAN0 Mailbox 13: Time Stamp XXXXh

047CDFh

047CE0h CAN0 Mailbox 14: Message Identifier C0MB14 XXXX XXXXh

047CE1h

047CE2h

047CE3h

047CE4h

047CE5h CAN0 Mailbox 14: Data Length XXh

047CE6h CAN0 Mailbox 14: Data Field XXXX XXXX

XXXX XXXXh

047CE7h

047CE8h

047CE9h

047CEAh

047CEBh

047CECh

047CEDh

047CEEh CAN0 Mailbox 14: Time Stamp XXXXh

047CEFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 59 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.31 SFR List (31)

Address Register Symbol Reset Value

047CF0h CAN0 Mailbox 15: Message Identifier C0MB15 XXXX XXXXh

047CF1h

047CF2h

047CF3h

047CF4h

047CF5h CAN0 Mailbox 15: Data Length XXh

047CF6h CAN0 Mailbox 15: Data Field XXXX XXXX

XXXX XXXXh

047CF7h

047CF8h

047CF9h

047CFAh

047CFBh

047CFCh

047CFDh

047CFEh CAN0 Mailbox 15: Time Stamp XXXXh

047CFFh

047D00h CAN0 Mailbox 16: Message Identifier C0MB16 XXXX XXXXh

047D01h

047D02h

047D03h

047D04h

047D05h CAN0 Mailbox 16: Data Length XXh

047D06h CAN0 Mailbox 16: Data Field XXXX XXXX

XXXX XXXXh

047D07h

047D08h

047D09h

047D0Ah

047D0Bh

047D0Ch

047D0Dh

047D0Eh CAN0 Mailbox 16: Time Stamp XXXXh

047D0Fh

047D10h CAN0 Mailbox 17: Message Identifier C0MB17 XXXX XXXXh

047D11h

047D12h

047D13h

047D14h

047D15h CAN0 Mailbox 17: Data Length XXh

047D16h CAN0 Mailbox 17: Data Field XXXX XXXX

XXXX XXXXh

047D17h

047D18h

047D19h

047D1Ah

047D1Bh

047D1Ch

047D1Dh

047D1Eh CAN0 Mailbox 17: Time Stamp XXXXh

047D1Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 60 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.32 SFR List (32)

Address Register Symbol Reset Value

047D20h CAN0 Mailbox 18: Message Identifier C0MB18 XXXX XXXXh

047D21h

047D22h

047D23h

047D24h

047D25h CAN0 Mailbox 18: Data Length XXh

047D26h CAN0 Mailbox 18: Data Field XXXX XXXX

XXXX XXXXh

047D27h

047D28h

047D29h

047D2Ah

047D2Bh

047D2Ch

047D2Dh

047D2Eh CAN0 Mailbox 18: Time Stamp XXXXh

047D2Fh

047D30h CAN0 Mailbox 19: Message Identifier C0MB19 XXXX XXXXh

047D31h

047D32h

047D33h

047D34h

047D35h CAN0 Mailbox 19: Data Length XXh

047D36h CAN0 Mailbox 19: Data Field XXXX XXXX

XXXX XXXXh

047D37h

047D38h

047D39h

047D3Ah

047D3Bh

047D3Ch

047D3Dh

047D3Eh CAN0 Mailbox 19: Time Stamp XXXXh

047D3Fh

047D40h CAN0 Mailbox 20: Message Identifier C0MB20 XXXX XXXXh

047D41h

047D42h

047D43h

047D44h

047D45h CAN0 Mailbox 20: Data Length XXh

047D46h CAN0 Mailbox 20: Data Field XXXX XXXX

XXXX XXXXh

047D47h

047D48h

047D49h

047D4Ah

047D4Bh

047D4Ch

047D4Dh

047D4Eh CAN0 Mailbox 20: Time Stamp XXXXh

047D4Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 61 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.33 SFR List (33)

Address Register Symbol Reset Value

047D50h CAN0 Mailbox 21: Message Identifier C0MB21 XXXX XXXXh

047D51h

047D52h

047D53h

047D54h

047D55h CAN0 Mailbox 21: Data Length XXh

047D56h CAN0 Mailbox 21: Data Field XXXX XXXX

XXXX XXXXh

047D57h

047D58h

047D59h

047D5Ah

047D5Bh

047D5Ch

047D5Dh

047D5Eh CAN0 Mailbox 21: Time Stamp XXXXh

047D5Fh

047D60h CAN0 Mailbox 22: Message Identifier C0MB22 XXXX XXXXh

047D61h

047D62h

047D63h

047D64h

047D65h CAN0 Mailbox 22: Data Length XXh

047D66h CAN0 Mailbox 22: Data Field XXXX XXXX

XXXX XXXXh

047D67h

047D68h

047D69h

047D6Ah

047D6Bh

047D6Ch

047D6Dh

047D6Eh CAN0 Mailbox 22: Time Stamp XXXXh

047D6Fh

047D70h CAN0 Mailbox 23: Message Identifier C0MB23 XXXX XXXXh

047D71h

047D72h

047D73h

047D74h

047D75h CAN0 Mailbox 23: Data Length XXh

047D76h CAN0 Mailbox 23: Data Field XXXX XXXX

XXXX XXXXh

047D77h

047D78h

047D79h

047D7Ah

047D7Bh

047D7Ch

047D7Dh

047D7Eh CAN0 Mailbox 23: Time Stamp XXXXh

047D7Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 62 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.34 SFR List (34)

Address Register Symbol Reset Value

047D80h CAN0 Mailbox 24: Message Identifier C0MB24 XXXX XXXXh

047D81h

047D82h

047D83h

047D84h

047D85h CAN0 Mailbox 24: Data Length XXh

047D86h CAN0 Mailbox 24: Data Field XXXX XXXX

XXXX XXXXh

047D87h

047D88h

047D89h

047D8Ah

047D8Bh

047D8Ch

047D8Dh

047D8Eh CAN0 Mailbox 24: Time Stamp XXXXh

047D8Fh

047D90h CAN0 Mailbox 25: Message Identifier C0MB25 XXXX XXXXh

047D91h

047D92h

047D93h

047D94h

047D95h CAN0 Mailbox 25: Data Length XXh

047D96h CAN0 Mailbox 25: Data Field XXXX XXXX

XXXX XXXXh

047D97h

047D98h

047D99h

047D9Ah

047D9Bh

047D9Ch

047D9Dh

047D9Eh CAN0 Mailbox 25: Time Stamp XXXXh

047D9Fh

047DA0h CAN0 Mailbox 26: Message Identifier C0MB26 XXXX XXXXh

047DA1h

047DA2h

047DA3h

047DA4h

047DA5h CAN0 Mailbox 26: Data Length XXh

047DA6h CAN0 Mailbox 26: Data Field XXXX XXXX

XXXX XXXXh

047DA7h

047DA8h

047DA9h

047DAAh

047DABh

047DACh

047DADh

047DAEh CAN0 Mailbox 26: Time Stamp XXXXh

047DAFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 63 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.35 SFR List (35)

Address Register Symbol Reset Value

047DB0h CAN0 Mailbox 27: Message Identifier C0MB27 XXXX XXXXh

047DB1h

047DB2h

047DB3h

047DB4h

047DB5h CAN0 Mailbox 27: Data Length XXh

047DB6h CAN0 Mailbox 27: Data Field XXXX XXXX

XXXX XXXXh

047DB7h

047DB8h

047DB9h

047DBAh

047DBBh

047DBCh

047DBDh

047DBEh CAN0 Mailbox 27: Time Stamp XXXXh

047DBFh

047DC0h CAN0 Mailbox 28: Message Identifier C0MB28 XXXX XXXXh

047DC1h

047DC2h

047DC3h

047DC4h

047DC5h CAN0 Mailbox 28: Data Length XXh

047DC6h CAN0 Mailbox 28: Data Field XXXX XXXX

XXXX XXXXh

047DC7h

047DC8h

047DC9h

047DCAh

047DCBh

047DCCh

047DCDh

047DCEh CAN0 Mailbox 28: Time Stamp XXXXh

047DCFh

047DD0h CAN0 Mailbox 29: Message Identifier C0MB29 XXXX XXXXh

047DD1h

047DD2h

047DD3h

047DD4h

047DD5h CAN0 Mailbox 29: Data Length XXh

047DD6h CAN0 Mailbox 29: Data Field XXXX XXXX

XXXX XXXXh

047DD7h

047DD8h

047DD9h

047DDAh

047DDBh

047DDCh

047DDDh

047DDEh CAN0 Mailbox 29: Time Stamp XXXXh

047DDFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 64 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.36 SFR List (36)

Address Register Symbol Reset Value

047DE0h CAN0 Mailbox 30: Message Identifier C0MB30 XXXX XXXXh

047DE1h

047DE2h

047DE3h

047DE4h

047DE5h CAN0 Mailbox 30: Data Length XXh

047DE6h CAN0 Mailbox 30: Data Field XXXX XXXX

XXXX XXXXh

047DE7h

047DE8h

047DE9h

047DEAh

047DEBh

047DECh

047DEDh

047DEEh CAN0 Mailbox 30: Time Stamp XXXXh

047DEFh

047DF0h CAN0 Mailbox 31: Message Identifier C0MB31 XXXX XXXXh

047DF1h

047DF2h

047DF3h

047DF4h

047DF5h CAN0 Mailbox 31: Data Length XXh

047DF6h CAN0 Mailbox 31: Data Field XXXX XXXX

XXXX XXXXh

047DF7h

047DF8h

047DF9h

047DFAh

047DFBh

047DFCh

047DFDh

047DFEh CAN0 Mailbox 31: Time Stamp XXXXh

047DFFh

047E00h CAN0 Mask Register 0 C0MKR0 XXXX XXXXh

047E01h

047E02h

047E03h

047E04h CAN0 Mask Register 1 C0MKR1 XXXX XXXXh

047E05h

047E06h

047E07h

047E08h CAN0 Mask Register 2 C0MKR2 XXXX XXXXh

047E09h

047E0Ah

047E0Bh

047E0Ch CAN0 Mask Register 3 C0MKR3 XXXX XXXXh

047E0Dh

047E0Eh

047E0Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 65 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.37 SFR List (37)

Address Register Symbol Reset Value

047E10h CAN0 Mask Register 4 C0MKR4 XXXX XXXXh

047E11h

047E12h

047E13h

047E14h CAN0 Mask Register 5 C0MKR5 XXXX XXXXh

047E15h

047E16h

047E17h

047E18h CAN0 Mask Register 6 C0MKR6 XXXX XXXXh

047E19h

047E1Ah

047E1Bh

047E1Ch CAN0 Mask Register 7 C0MKR7 XXXX XXXXh

047E1Dh

047E1Eh

047E1Fh

047E20h CAN0 FIFO Receive ID Compare Register 0 C0FIDCR0 XXXX XXXXh

047E21h

047E22h

047E23h

047E24h CAN0 FIFO Receive ID Compare Register 1 C0FIDCR1 XXXX XXXXh

047E25h

047E26h

047E27h

047E28h CAN0 Mask Invalid Register C0MKIVLR XXXX XXXXh

047E29h

047E2Ah

047E2Bh

047E2Ch CAN0 Mailbox Interrupt Enable Register C0MIER XXXX XXXXh

047E2Dh

047E2Eh

047E2Fh

047E30h

047E31h

047E32h

047E33h

047E34h

047E35h

047E36h

047E37h

047E38h

047E39h

047E3Ah

047E3Bh

047E3Ch

047E3Dh

047E3Eh

047E3Fh

047E40h to

047F1Fh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 66 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.38 SFR List (38)

Address Register Symbol Reset Value

047F20h CAN0 Message Control Register 0 C0MCTL0 00h

047F21h CAN0 Message Control Register 1 C0MCTL1 00h

047F22h CAN0 Message Control Register 2 C0MCTL2 00h

047F23h CAN0 Message Control Register 3 C0MCTL3 00h

047F24h CAN0 Message Control Register 4 C0MCTL4 00h

047F25h CAN0 Message Control Register 5 C0MCTL5 00h

047F26h CAN0 Message Control Register 6 C0MCTL6 00h

047F27h CAN0 Message Control Register 7 C0MCTL7 00h

047F28h CAN0 Message Control Register 8 C0MCTL8 00h

047F29h CAN0 Message Control Register 9 C0MCTL9 00h

047F2Ah CAN0 Message Control Register 10 C0MCTL10 00h

047F2Bh CAN0 Message Control Register 11 C0MCTL11 00h

047F2Ch CAN0 Message Control Register 12 C0MCTL12 00h

047F2Dh CAN0 Message Control Register 13 C0MCTL13 00h

047F2Eh CAN0 Message Control Register 14 C0MCTL14 00h

047F2Fh CAN0 Message Control Register 15 C0MCTL15 00h

047F30h CAN0 Message Control Register 16 C0MCTL16 00h

047F31h CAN0 Message Control Register 17 C0MCTL17 00h

047F32h CAN0 Message Control Register 18 C0MCTL18 00h

047F33h CAN0 Message Control Register 19 C0MCTL19 00h

047F34h CAN0 Message Control Register 20 C0MCTL20 00h

047F35h CAN0 Message Control Register 21 C0MCTL21 00h

047F36h CAN0 Message Control Register 22 C0MCTL22 00h

047F37h CAN0 Message Control Register 23 C0MCTL23 00h

047F38h CAN0 Message Control Register 24 C0MCTL24 00h

047F39h CAN0 Message Control Register 25 C0MCTL25 00h

047F3Ah CAN0 Message Control Register 26 C0MCTL26 00h

047F3Bh CAN0 Message Control Register 27 C0MCTL27 00h

047F3Ch CAN0 Message Control Register 28 C0MCTL28 00h

047F3Dh CAN0 Message Control Register 29 C0MCTL29 00h

047F3Eh CAN0 Message Control Register 30 C0MCTL30 00h

047F3Fh CAN0 Message Control Register 31 C0MCTL31 00h

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 67 of 604

Feb 18, 2013

R32C/117 Group 4. Special Function Registers (SFRs)

Table 4.39 SFR List (39)

Address Register Symbol Reset Value

047F40h CAN0 Control Register C0CTLR 0000 0101b

047F41h 0000 0000b

047F42h CAN0 Status Register C0STR 0000 0101b

047F43h 0000 0000b

047F44h CAN0 Bit Configuration Register C0BCR 00 0000h

047F45h

047F46h

047F47h CAN0 Clock Select Register C0CLKR 000X 0000b

047F48h CAN0 Receive FIFO Control Register C0RFCR 1000 0000b

047F49h CAN0 Receive FIFO Pointer Control Register C0RFPCR XXh

047F4Ah CAN0 Transmit FIFO Control Register C0TFCR 1000 0000b

047F4Bh CAN0 Transmit FIFO Pointer Control Register C0TFPCR XXh

047F4Ch CAN0 Error Interrupt Enable Register C0EIER 00h

047F4Dh CAN0 Error Interrupt Factor Judge Register C0EIFR 00h

047F4Eh CAN0 Receive Error Count Register C0RECR 00h

047F4Fh CAN0 Transmit Error Count Register C0TECR 00h

047F50h CAN0 Error Code Store Register C0ECSR 00h

047F51h CAN0 Channel Search Support Register C0CSSR XXh

047F52h CAN0 Mailbox Search Status Register C0MSSR 1000 0000b

047F53h CAN0 Mailbox Search Mode Register C0MSMR 0000 0000b

047F54h CAN0 Time Stamp Register C0TSR 0000h

047F55h

047F56h CAN0 Acceptance Filter Support Register C0AFSR XXXXh

047F57h

047F58h CAN0 Test Control Register C0TCR 00h

047F59h

047F5Ah

047F5Bh

047F5Ch

047F5Dh

047F5Eh

047F5Fh

047F60h to

047FFFh

048000h to

04FFFFh

X: Undefined

Blanks are reserved. No access is allowed.

R01UH0211EJ0120 Rev.1.20 Page 68 of 604

Feb 18, 2013

R32C/117 Group 5. Resets

5. Resets

There are three types of operations for resetting the MCU: hardware reset, software reset, and watchdog

timer reset.

5.1 Hardware Reset

A hardware reset is generated when a low signal is applied to the RESET pin under the recommended

operating conditions of the supply voltage. When the RESET pin is driven low, all pins, and oscillators are

reset (refer to Table 5.1 for details), and the main clock starts oscillating. The CPU and SFRs are reset by

a low-to-high transition on the RESET pin. Then, the CPU starts executing the program from the address

indicated by the reset vector. Internal RAM is not affected by a hardware reset. However, if a hardware

reset occurs during a write operation to the internal RAM, the value is undefined.

Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows the reset sequence. Table 5.1 lists pin

states while the RESET pin is held low. Figure 5.3 shows CPU register states after a reset. Refer to 4.

“Special Function Registers (SFRs)” for details on the states of SFRs after a reset.

A. Reset when the supply voltage is stable

(1) Drive the RESET pin low.

(2) Input at least 20 clock cycles to the XIN pin.

(3) Drive the RESET pin high.

B. Reset when turning on the power

(1) Drive the RESET pin low.

(2) Raise the supply voltage to the recommended operating voltage.

(3) Wait td(P-R) ms until the internal voltage is stabilized.

(4) Input at least 20 clock cycles to the XIN pin.

(5) Drive the RESET pin high.

Figure 5.1 Reset Circuitry

VCC

RESET

0 V

VCC

0 V

RESET

Recommended

operating voltage

0.2 VCC

This width indicates internal power supply stabilization time (td(P-R))

+ at least 20 cycles of a clock input to the XIN pin

R01UH0211EJ0120 Rev.1.20 Page 69 of 604

Feb 18, 2013

R32C/117 Group 5. Resets

Figure 5.2 Reset Sequence

XIN

RESET

BCLK

Input at least 20 clock cycles

Microprocessor mode

8-bit bus

Address

16-bit bus

32-bit bus

Single-chip mode

Address (1)

FFFFFFFCh

Reset vector value

Note:

1. Address data is not output from pins in single-chip mode.

Reset vector value

FFFFFFFCh FFFFFFFCh FFFFFFFDh FFFFFFFEh FFFFFFFFh

Byte access Byte access

Address

Reset vector value

FFFFFFFCh FFFFFFFCh FFFFFFFEh

Byte access Word access

Address

Reset vector value

FFFFFFFCh FFFFFFFCh

Byte access Long word access

R01UH0211EJ0120 Rev.1.20 Page 70 of 604

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R32C/117 Group 5. Resets

Notes:

1. Whether a pull-up resistor is enabled or not is undefined until the internal voltage is stabilized.

2. State after power is on and the internal voltage has stabilized. It is undefined until the internal voltage

is stabilized

3. Ports P11 to P15 are available in the 144-pin package only.

Figure 5.3 CPU Registers after Reset

Table 5.1 Pin States while RESET Pin is Held Low (1)

Pin Name Pin States

CNVSS = VSS CNVSS = VCC

P0 Input port (high-impedance) Inputs data

P1 Input port (high-impedance) Input port (high-impedance)

P2, P3 Input port (high-impedance) Output addresses (undefined)

P4_0 to P4_6 Input port (high-impedance) Output addresses (undefined)

P4_7 Input port (high-impedance) Outputs the CS0 signal (high)

P5_0 Input port (high-impedance) Outputs the WR signal (high)

P5_1 Input port (high-impedance) Outputs the BC1 signal (undefined)

P5_2 Input port (high-impedance) Outputs the RD signal (high)

P5_3 Input port (high-impedance) Outputs BCLK (2)

P5_4 Input port (high-impedance) Outputs the HLDA signal (output signal depends on

an input signal to the HOLD pin) (2)

P5_5 Input port (high-impedance) Inputs the HOLD signal (high-impedance)

P5_6 Input port (high-impedance) Outputs the CS2 signal (high)

P5_7 Input port (high-impedance) Inputs the RDY signal (high-impedance)

P6 to P15 (3) Input port (high-impedance) Input port (high-impedance)

00000000h

0000h0000h

0000h 0000h

00h00h00h00h

00h 00h 00h 00h

00000000h

Reset vector value

00000000h

b0b31

General purpose registers

Flag register (FLG)

Data register (R2H/R2L/R0H/R0L)

Address register (A0)

Static base register (SB)

Frame base register (FB)

User stack pointer (USP)

Interrupt stack pointer (ISP)

Interrupt vector table base register (INTB)

Program counter (PC)

DRA0

DSA0

DMA0

DRC0

DCT0

DMD0

00000000h

XXXXXXXXh

Fast interrupt registers

DMAC-associated registers

DMA destination address register

(DDA0 to DDA3)

Save flag register (SVF)

Save PC register (SVP)

Vector register (VCT)

DMA source address reload register

(DSR0 to DSR3)

DMA source address register (DSA0 to DSA3)

DMA terminal count reload register

(DCR0 to DCR3)

DMA terminal count register (DCT0 to DCT3)

DMA mode register (DMD0 to DMD3)

DRC0

DCT0

DRC0

DCT0

XXXXXXXXh

DRA0

DSA0

DMA0

DRA0

DSA0

DMA0

XXXXXXXXh

Data register (R3H/R3L/R1H/R1L)

Data register (R6/R4)

Data register (R7/R5)

Address register (A1)

Address register (A2)

Address register (A3)

00000000h

0000h0000h

0000h 0000h

00h00h00h00h

00h 00h 00h 00h

00000000h

X X X X X X X X X X X X 0 0 X 0 X 0 0 0 X X 0 0 0 0 0 0 0 0 0 0

b0b31 b24 b23 b16 b15 b8 b7

UIOBSZDC

IPL

b0b31

0: 0 after reset

X: Undefined after reset

b0b31

RND

DRA0 DMA destination address reload register

(DDR0 to DDR3)

DRA0

XXXXXXXXh

b24

R01UH0211EJ0120 Rev.1.20 Page 71 of 604

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R32C/117 Group 5. Resets

5.2 Software Reset

The CPU, SFRs, and pins are reset when the PM03 bit in the PM0 register is set to 1 (the MCU is reset).

Then, the CPU executes the program from the address indicated by the reset vector.

Set the PM03 bit to 1 while the PLL clock is selected as the CPU clock source and the main clock

oscillation is completely stable.

There is no change in processor mode since bits PM01 and PM00 in the PM0 register are not affected by

a software reset.

5.3 Watchdog Timer Reset

The CPU, SFRs, and pins are reset when the watchdog timer underflows while the CM06 bit in the CM0

address indicated by the reset vector.

There is no change in processor mode since bits PM01 and PM00 in the PM0 register are not affected by

a watchdog timer reset.

5.4 Reset Vector

The reset vector in the R32C/100 Series is configured as shown in Figure 5.4.

The start address of a program consists of the upper 30 bits of the reset vector and 00b as lower 2 bits.

The lower 2 bits of the reset vector are bits to select the external bus width in microprocessor mode.

Therefore, the start address of a program requires 4-byte alignment so that the lower 2 bits are 00b.

In single-chip mode, set the external bus width select bits to 00b.

Figure 5.4 Reset Vector Configuration

0 0

FFFFFFFCh

FFFFFFFDh

FFFFFFFEh

FFFFFFFFh

b7 b0

Upper 30 bits of reset vector

Reset vector value

Start address of the

program

External bus width select bits in microprocessor mode (1)

32-bit bus width: 00b

16-bit bus width: 10b

8-bit bus width: 11b

Note:

1. Set these bits to 00b in single-chip mode.

R01UH0211EJ0120 Rev.1.20 Page 72 of 604

Feb 18, 2013

R32C/117 Group 6. Power Management

6. Power Management

6.1 Voltage Regulators for Internal Logic

The supply voltage for internal logic is generated by reducing the input voltage from the VCC pin with the

voltage regulators. Figure 6.1 shows a block diagram of the voltage regulators for internal logic, and

Figure 6.2 shows the VRCR register.

Figure 6.1 Block Diagram of Voltage Regulators for Internal Logic

Figure 6.2 VRCR Register

VCC Main regulator

SHDN

Supply voltage for

internal logic

MRS: Bit in the VRCR register

Sub regulator

MRS

VDC1

VDC0

VSS Internal logic GND

External decoupling

capacitor

b7 b6 b5 b4 b1b2b3 Symbol

VRCR

Address

040060h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Voltage Regulator Control Register (1)

No register bits; should be written with 0 and read as 0

Notes:

1. Set the PRC31 bit in the PRCR3 register to 1 (write enabled) before rewriting this register.

2. This bit is fixed to 0 if the CM05 bit in the CM0 register is 0 (main clock oscillator enabled) or the CM10 bit in

the CM1 register is 0 (PLL oscillator enabled) .

3. While the main regulator is stopped, do not rewrite the flash memory.

0: Main regulator active

1: Main regulator stopped (3)

Main Regulator Shut-down

Bit (2)

MRS

—

(b7-b1) —

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Feb 18, 2013

R32C/117 Group 6. Power Management

6.1.1 Decoupling Capacitor

An external decoupling capacitor is required to stabilize internal voltage. The capacitor should be

beneficially effective at higher frequencies and maintain a more stable capacitance irrespective of

temperature change. In general, ceramic capacitors are recommended. The capacitance varies by

conditions such as operating temperature, DC bias, and aging. To select an appropriate capacitor,

these conditions should be considered. Also, refer to the recommended capacitor specifications listed

in Table 6.1.

The traces between the capacitor and the VDC1/VDC0 pins should be as short and wide as physically

possible.

Table 6.1 Recommended Capacitor Specifications

Temperature Characteristics

Rated Voltage

(V)

Nominal

Capacitance

(µF)

Capacitance

Tolerance (%)

Applicable standard

Operating

temperature

range (°C)

Capacitance

change (%)

B JIS -25 to 85 ±10 6.3 or higher 4.7 ±20 or better

R JIS -55 to 125 ±15 6.3 or higher 4.7 ±20 or better

X5R EIA -55 to 85 ±15 6.3 or higher 4.7 ±20 or better

X7R EIA -55 to 125 ±15 6.3 or higher 4.7 ±20 or better

X8R EIA -55 to 150 ±15 6.3 or higher 4.7 ±20 or better

X6S EIA -55 to 105 ±22 6.3 or higher 4.7 ±20 or better

X7S EIA -55 to 125 ±22 6.3 or higher 4.7 ±20 or better

R01UH0211EJ0120 Rev.1.20 Page 74 of 604

Feb 18, 2013

R32C/117 Group 6. Power Management

6.2 Low Voltage Detector

The low voltage detector monitors the supply voltage input to the VCC pin.

This circuit is used to monitor the power supply upstream of the voltage regulators for internal logic and

provide advanced warning that the power is about to fail. By providing a few milliseconds of advanced

warning, the CPU can save any critical parameters to the flash memory and safely shut down.

Figure 6.3 shows a block diagram of the low voltage detector, and Figures 6.4 and 6.5 show registers

associated with the circuit.

Figure 6.3 Low Voltage Detector Block Diagram

VCC

RVC3 to RVC0

 Vdet

VMF

Low voltage

detection

interrupt

request

VDEN

Voltage

regulators Supply voltage for internal logic

Edge

gene-

rator

LVDIEN

LVDF

VDEN, LVDIEN, LVDF, and VMF: Bits in the LVDC register

RVC3 to RVC0: Bits in the DVCR register

R01UH0211EJ0120 Rev.1.20 Page 75 of 604

Feb 18, 2013

R32C/117 Group 6. Power Management

Figure 6.4 LVDC Register

b7 b6 b5 b4 b1b2b3 Symbol

LVDC

Address

40062h

Reset Value

0000 XX00b

FunctionBit Symbol Bit Name RW

Low Voltage Detector Control Register (1)

0: VCC < Vdet

1: VCC  Vdet or low voltage

detector disabled

Voltage Monitor Flag (3)

VMF

Low Voltage Detector

Enable Bit

VDEN 0: Low voltage detector disabled

1: Low voltage detector enabled

Low Voltage Detection

Interrupt Enable Bit (2)

LVDIEN 0: Interrupt disabled

1: Interrupt enabled

0: Low voltage undetected

1: Low voltage detected (Vdet passed)

Low Voltage Detection

Flag (3, 4)

LVDF

No register bits; should be written with 0 and read as 0

—

(b7-b4) —

Notes:

1. Set the PRC31 bit in the PRCR3 register to 1 (write enabled) before rewriting this register.

2. Before setting this bit to 1, set the VDEN bit to 1 first, and wait until the circuit is stabilized.

3. This bit is enabled when the VDEN bit is set to 1.

4. This bit can be set to 0 by a program (Writing 1 to this bit has no effect).

R01UH0211EJ0120 Rev.1.20 Page 76 of 604

Feb 18, 2013

R32C/117 Group 6. Power Management

Figure 6.5 DVCR Register

b7 b6 b5 b4 b1b2b3 Symbol

DVCR

Address

40064h

Reset Value

0000 XXXXb

FunctionBit Symbol Bit Name RW

Detection Voltage Configuration Register (1)

Notes:

1. Set the PRC31 bit in the PRCR3 register to 1 (write enabled) before rewriting this register. Rewrite this

2. Refer to the following table for detected voltages Vdet(F) and Vdet(R).

Reference Voltage

Configuration Bit (2)

RVC0

Reserved

—

(b7)

RVC1

RVC2

RVC3

—

(b6-b4)

b3 b2 b1 b0

0 0 0 0 : 3.90 V

0 0 0 1 : 3.75 V

0 0 1 0 : 3.60 V

0 0 1 1 : 3.45 V

0 1 0 0 : 3.30 V

1 0 1 1 : 4.65 V

1 1 0 0 : 4.50 V

1 1 0 1 : 4.35 V

1 1 1 0 : 4.20 V

1 1 1 1 : 4.05 V

Only use the combinations listed

above

No register bits; should be written with 0 and read as 0 —

Should be written with 1 RW

Reference Voltage Low-detection Voltage

Vdet(F)

Rise-detection Voltage

Vdet(R)

4.65 V 4.55 V 4.77 V

4.50 V 4.40 V 4.62 V

4.35 V 4.24 V 4.46 V

4.20 V 4.09 V 4.31 V

4.05 V 3.95 V 4.17 V

3.90 V 3.80 V 4.02 V

3.75 V 3.65 V 3.87 V

3.60 V 3.50 V 3.72 V

3.45 V 3.35 V 3.57 V

3.30 V 3.20 V 3.42 V

R01UH0211EJ0120 Rev.1.20 Page 77 of 604

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R32C/117 Group 6. Power Management

6.2.1 Operational State of Low Voltage Detector

The low voltage detector starts operating stably after td(E-A) when the VDEN bit in the LVDC register is

set to 1 (low voltage detector enabled).

When the input voltage to the VCC pin drops below Vdet(F), the VMF bit becomes 0 (VCC < Vdet) and

the LVDF bit becomes 1 (low voltage detected (Vdet passed)). At this point an interrupt request is

generated when the LVDIEN bit is 1 (low voltage detection interrupt enabled). Set the LVDF bit to 0 (low

voltage undetected) by a program.

When the voltage rises to or above Vdet(R) again, the VMF bit becomes 1 (VCC  Vdet)and the LVDF

bit becomes 1. At this point an interrupt request is generated when the LVDIEN bit is 1.

Figure 6.6 shows the operation of the low voltage detector.

Figure 6.6 Low Voltage Detector Operation

6.2.2 Low Voltage Detection Interrupt

A low voltage detection interrupt request is generated when the input voltage at the VCC pin rises to or

above the Vdet(R) level, or falls below the Vdet(F) level while the LVDIEN bit in the LVDC register is 1

(low voltage detection interrupt enabled).

This interrupt shares the interrupt vector with the watchdog timer interrupt and oscillator stop detection

interrupt. When using the low voltage detection interrupt with these interrupts at the same time, read

the LVDF bit in the LVDC register in the interrupt handler and confirm that the low voltage detection

interrupt has been occurred.

The LVDF bit becomes 1 when the input voltage at the VCC pin passes the Vdet(R) level or Vdet(F)

level. When the LVDF bit changes from 0 to 1, a low voltage detection interrupt request is generated.

Set this bit to 0 (low voltage undetected) by a program.

Disabled

VCC

VDEN bit

Voltage detector Unstable Stable

d(E-A)

Vdet(F)

Vdet(R)

VMF bit

LVDF bit

Set to 0 by a program

R01UH0211EJ0120 Rev.1.20 Page 78 of 604

Feb 18, 2013

R32C/117 Group 6. Power Management

6.2.3 Application Example of the Low Voltage Detector

Figure 6.7 shows an example of the low voltage detection interrupt.

The supply voltage for internal logic is generated by reducing the input voltage from the VCC pin with

the voltage regulators. When the input voltage begins to fall, the internal voltage remains steady.

However, as the VCC input voltage continues to fall, the supply voltage for the internal logic also begins

to fall, which may affect MCU operation. Consequently, the system can be safely shut down between

when the VCC input voltage begins to fall and when the supply voltage for internal logic begins to fall.

The low voltage detection interrupt can be applied to detect the falling input voltage.

Figure 6.7 Example of the Low Voltage Detection Interrupt

VCC

Supply voltage for internal logic

Voltage

Time

Vdet

tSAVE

Low voltage detection interrupt

System shutdown

R01UH0211EJ0120 Rev.1.20 Page 79 of 604

Feb 18, 2013

R32C/117 Group 7. Processor Mode

7. Processor Mode

7.1 Types of Processor Modes

The R32C/100 Series supports three types of processor modes: single-chip mode, memory expansion

mode, and microprocessor mode. Table 7.1 lists the characteristics of each processor mode.

Note:

1. Refer to 9. “Bus” for details.

The R32C/117 Group supports two standard processor modes: single-chip mode and memory expansion

mode. Microprocessor mode is optional. Contact a Renesas Electronics sales office to use this mode.

7.2 Processor Mode Setting

The processor mode to be used is selected by the CNVSS pin state and setting of bits PM01 and PM00 in

the PM0 register. After a hardware reset, the operation starts in single-chip mode or microprocessor mode

as shown in Table 7.2.

Note:

1. The CNVSS pin should be connected to VCC or VSS via a resistor.

To change to memory expansion mode after starting an operation in single-chip mode, set bits PM01 and

PM00 in the PM0 register to 01b (memory expansion mode). Note that the microprocessor mode,

selected to start an operation, can be also changed to another mode by setting the bits mentioned above.

In this case, however, the internal ROM is inaccessible in every changed mode.

Notes on changing processor mode are as follows:

1. When rewriting bits PM01 and PM00 to 01b (memory expansion mode) or 11b (microprocessor

mode), do not change bits PM07 to PM02.

2. When rewriting bits PM07 to PM02, do not change bits PM01 and PM00.

3. Do not change the current mode to microprocessor mode while a program in the internal ROM is

being executed.

4. Do not change the current mode to single-chip mode while a program in the external space is

being executed.

5. Do not change microprocessor mode to memory expansion mode while a program in the same

address as that assigned to the internal ROM is being executed.

Figure 7.1 shows the PM0 register and Figure 7.2 shows the memory map for each processor mode.

Table 7.1 Processor Mode Characteristics

Processor Mode Accessible Space Pin State as I/O Ports

Single-chip mode SFRs, internal RAM, internal ROM All pins can be assigned to I/O ports or

I/O pins for the peripheral functions

Memory expansion mode SFRs, internal RAM, internal

ROM, external space

Some pins are assigned to bus control

pins (1)

Microprocessor mode SFRs, internal RAM, external

space

Some pins are assigned to bus control

pins (1)

Table 7.2 Processor Mode after Hardware Reset

Input Level into the CNVSS Pin (1) Processor Mode

Low Single-chip mode

High Microprocessor mode

R01UH0211EJ0120 Rev.1.20 Page 80 of 604

Feb 18, 2013

R32C/117 Group 7. Processor Mode

Figure 7.1 PM0 Register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol

PM0

Address

40044h

Reset Value

1000 0000b (CNVSS pin is held low)

0000 0011b (CNVSS pin is held high)

Bit Symbol Bit Name Function RW

Notes:

1. Rewrite this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).

2. The processor mode is not changed even when the PM03 bit is set to 1 (software reset).

3. Rewrite bits PM01 and PM00 with 01b or 11b after other bit(s) is/are rewritten. They should not be rewritten

simultaneously.

4. In single-chip mode, the BCLK is not output even when the PM07 bit is set to 0.

To stop clock output in memory expansion mode or microprocessor mode, set the PM07 bit to 1 and bits

CM01 and CM00 in the CM0 register to 00b (I/O port P5_3). I/O port P5_3 outputs a low signal in this case.

5. Set bits CM01 and CM00 to 00b when the PM07 bit is 0.

Reserved Should be written with 0

R/W Mode Select Bit 0: RD / WR / BC0 / BC1 / BC2 / BC3

1: RD / WR0 / WR1 / WR2 / WR3

Software Reset Bit The MCU is reset when this bit is set

to 1. The bit is read as 0 RW

Processor Mode Bit (2, 3)

b1 b0

0 0 : Single-chip mode

0 1 : Memory expansion mode

1 0 : Do not use this combination

1 1 : Microprocessor mode

BCLK Output Function

Select Bit (4)

0: Output BCLK (5)

1: Do not output BCLK. Select a

function for port P5_3 using bits

CM01 and CM00 in the CM0

Processor Mode Register 0 (1)

000

PM00

PM01

PM02

PM03

—

(b6-b4)

PM07

R01UH0211EJ0120 Rev.1.20 Page 81 of 604

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R32C/117 Group 7. Processor Mode

Figure 7.2 Memory Map of Each Processor Mode

Single-chip Mode Memory Expansion Mode Microprocessor Mode

SFRs

Internal RAM

Reserved

(internal RAM)

SFRs 2

Reserved

Data ROM

Reserved

(Internal ROM)

Cannot be used (1)

Reserved

(Internal ROM)

Internal ROM

SFRs

Internal RAM

Reserved

(internal RAM)

SFRs 2

Reserved

Data ROM

Reserved

(Internal ROM)

Cannot be used (2)

Reserved

(Internal ROM)

Internal ROM

SFRs

Internal RAM

Reserved

(internal RAM)

SFRs 2

Reserved

Data ROM

Reserved

(Internal ROM)

00000000h

FFFFFFFFh

00000400h

00040000h

00050000h

00060000h

00062000h

00080000h

FFE00000h

FE000000h

02000000h

External space

31.5 MB

External space

30 MB

Cannot be used (2)

External space

31.5 MB

External space

32 MB

Notes:

1. This space cannot be externally expanded in single-chip mode.

2. This space cannot be used in any processor mode.

R01UH0211EJ0120 Rev.1.20 Page 82 of 604

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R32C/117 Group 8. Clock Generator

8. Clock Generator

8.1 Clock Generator Types

The clock generator consists of four circuits:

• Main clock oscillator

• Sub clock oscillator

• PLL frequency synthesizer

• On-chip oscillator (OCO)

Table 8.1 lists the specifications of the clock generator. Figure 8.1 shows a block diagram of the clock

generator, and Figures 8.2 to 8.10 show registers associated with clock control.

Table 8.1 Clock Generator Specifications

Item Main Clock

Oscillator Sub Clock Oscillator PLL Frequency

Synthesizer On-chip Oscillator

Used as • PLL reference

clock source

• Peripheral clock

source

• CPU clock source

• Clock source for

timers A and B

• CPU clock source

• Peripheral clock

source

• CPU clock source

• Clock source for

timers A and B

Clock frequency 4 to 16 MHz 32.768 kHz fSO(PLL) or f(PLL) Approx. 125 kHz

Connectable

oscillators or

additional circuits

Ceramic resonator

Crystal oscillator

——

Pins for oscillators

or additional

circuits

XIN, XOUT XCIN, XCOUT

——

Oscillator stop/

restart function

Available Available Available Available

Oscillator state

after a reset

Running Stopped Running Stopped

Note Externally generated

clock can be input

Externally generated

clock can be input

When the main clock

oscillator stops

running, the PLL

frequency

synthesizer

oscillates at its own

frequency of fSO(PLL)

R01UH0211EJ0120 Rev.1.20 Page 83 of 604

Feb 18, 2013

R32C/117 Group 8. Clock Generator

Figure 8.1 Clock Generation Circuitry

WAIT instruction (wait mode)

STOP instruction (stop mode)

RESET

NMI

Output signal from priority resolver

CM05

XIN XOUT

Main clock oscillator

Main clock

stop detector

CM20 Detection enabled Peripheral clock source

wait_mode

stop_mode

1/p

PM26

CST

f2n

1/8 1/4

fAD

f32

CPU

clock

CM04

XCIN XCOUT

Sub clock oscillator

stop_mode

Sub clock fC

1/32 fC32

CPSR = 1

Divider

reset

CM00 to CM02, CM04, and CM05: Bits in the CM0 register PM26: Bit in the PM2 register

CM10: Bit in the CM1 register CST: Bit in the TCSPR register

CM20: Bit in the CM2 register CPSR: Bit in the CPSRF register

CM30 and CM31: Bits in the CM3 register BCS: Bit in the CCR register

CLKOUT

f32

Low speed clock

CM01 and CM00

stop_mode

wait_mode

(Note 1)

Main clock

BCS

PLL clock

(Note 4)

(Note 2)

(Note 5)

Oscillator stop

detection interrupt

request

PLL frequency

synthesizer

1/q

1/m

1/2n

1/b

BCD

(Note 3) Base

Clock

CCD

PCD Peripheral

bus clock

PLL oscillator

stop

CM02

1/256

CM30

On-chip oscillator

(125 kHz)

1/4

f256

On-chip oscillator clock fOCO

CM31

fOCO4

Notes:

1. The value of p can be selected by setting bits PM36 and PM35 in the PM3 register (p = 2, 4, 6, 8).

2. The value of n can be selected by setting bits CNT3 to CNT0 in the TCSPR register (n = 0 to 15).

When n is 0, the clock is not divided.

3. The value of b can be selected by setting bits BCD1 and BCD0 in the CCR register (b = 2, 3, 4, 6).

4. The value of m can be selected by setting bits CCD1 and CCD0 in the CCR register (m = 1 to 4).

5. The value of q can be selected by setting bits PCD1 and PCD0 in the CCR register (q = 2 to 4).

Peripheral clocks

Low voltage detection interrupt

CM10

BCS

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R32C/117 Group 8. Clock Generator

Figure 8.2 CCR Register

b7 b6 b5 b4 b1b2b3 Symbol

CCR

Address

0004h

Reset Value

0001 1000b

FunctionBit Symbol Bit Name RW

Clock Control Register (1)

Notes:

1. Set the PRR register to AAh (write enabled) before rewriting this register.

2. The divide ratios of the base clock and peripheral bus clock should not be changed simultaneously. Doing

so may cause the peripheral bus clock frequency to go over the maximum operating frequency.

3. The divide ratio of the CPU clock should be equal to or lower than that of peripheral bus clock.

4. Set this bit only once after a reset and do not change the setting afterwards. Rewrite the PBC register

before rewriting this bit.

5. To set this bit to 1, a 32-bit write access to addresses 0004h to 0007h should be performed.

6. To use these low speed clocks, select one of them by setting bits CM31 and CM30 in the CM3 register and

then set the BCS bit to 1.

RWReserved

Base Clock Divide Ratio

Select Bit (2)

b1 b0

0 0 : Divide-by-6

0 1 : Divide-by-4

1 0 : Divide-by-3

1 1 : Divide-by-2 RW

CPU Clock Divide Ratio

Select Bit (3)

b3 b2

0 0 : Divide-by-4

0 1 : Divide-by-3

1 0 : Divide-by-2

1 1 : No division RW

Peripheral Bus Clock

Divide Ratio Select Bit

(2, 3, 4)

b5 b4

0 0 : Do not use this combination

0 1 : Divide-by-2

1 0 : Divide-by-3

1 1 : Divide-by-4 RW

0: PLL clock

1: fC, fOCO4, or f256 (5, 6)

Base Clock Source Select

Bit

BCD0

BCD1

CCD0

CCD1

PCD0

PCD1

—

(b6)

BCS

Should be written with 0

R01UH0211EJ0120 Rev.1.20 Page 85 of 604

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R32C/117 Group 8. Clock Generator

Figure 8.3 CM0 Register

b7 b6 b5 b4 b1b2b3 Symbol

CM0

Address

40046h

Reset Value

0000 1000b

FunctionBit Symbol Bit Name RW

System Clock Control Register 0 (1)

0: Peripheral clock source not

stopped in wait mode

1: Peripheral clock source stopped in

wait mode (4)

Peripheral Clock Source

Stop Bit (3)

Clock Output Function

Select Bit (2)

b1 b0

0 0 : I/O port P5_3

0 1 : Output a low speed clock

1 0 : Output f8

1 1 : Output f32 RW

Watchdog Timer Function

Select Bit (8)

XCIN-XCOUT Drive

Strength Select Bit (5)

0: Low

1: High RW

RWReserved

0: I/O port

1: XCIN-XCOUT oscillator (6)

Port XC Switch Bit

Main Clock Oscillator (XIN-

XOUT) Stop Bit (3, 7)

0: Main clock oscillator enabled

1: Main clock oscillator disabled RW

0: Watchdog timer interrupt

1: Reset (9)

Notes:

1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.

2. When the PM07 bit in the PM0 register is 0 (output BCLK), bits CM01 and CM00 should be set to 00b. In

memory expansion mode, when the PM07 bit is 1 (select a function for port P5_3 using bits CM01 and

CM00 in the CM0 register) and bits CM01 and CM00 are set to 00b, the P5_3 pin is driven low (this pin

does not function as port P5_3).

3. When the PM21 bit in the PM2 register is 1 (clock change disabled), bits CM02 bit and CM05 cannot be

changed by a write access.

4. fC32 and f2n (whose clock source is the main clock) do not stop.

5. When entering stop mode, the CM03 bit becomes 1.

6. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 0 (input), and the PU25 bit in the

PUR2 register to 0 (pull-up resistor disabled).

7. This bit stops the main clock when entering low power mode. It cannot detect whether or not the main clock

oscillator stops. When this bit is set to 1, the clock applied to the XOUT pin becomes high. Since the on-chip

feedback resistor remains connected, the XIN pin is connected to the XOUT pin via the feedback resistor.

8. Set this bit before activating the watchdog timer. When rewriting this bit while the watchdog timer is running,

set it immediately after writing to the WDTS register.

9. Once this bit is set to 1, it cannot be set to 0 by a program.

Should be written with 0

CM02

CM00

CM01

CM03

CM04

CM05

CM06

—

(b7)

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R32C/117 Group 8. Clock Generator

Figure 8.4 CM1 Register

b7 b6 b5 b4 b1b2b3 Symbol

CM1

Address

40047h

Reset Value

0010 0000b

FunctionBit Symbol Bit Name RW

System Clock Control Register 1 (1)

RWPLL Oscillator Stop Bit (2, 3)

0: PLL oscillator enabled

1: PLL oscillator disabled

XIN-XOUT Drive Strength

Select Bit (4)

Notes:

1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.

2. When the BCS bit in the CCR register is 0 (PLL clock selected as base clock source), the PLL frequency

synthesizer does not stop oscillating even if the CM10 bit is set to 1.

3. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM10 bit cannot be changed by a

write access.

4. These bits become 01b when the main clock is stopped. When setting to 00b or 10b, rewrite them after the

main clock is fully stabilized.

5. The oscillator frequency should be 8 MHz or less to select super low mode.

Reserved

RWReserved

Should be written with 0

0 0000

CM10

—

(b4-b1)

CM15

—

(b7)

RWCM16

b6 b5

00:Low

01:High

1 0 : Super low (5)

1 1 : Do not use this combination

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R32C/117 Group 8. Clock Generator

Figure 8.5 CM2 Register

Figure 8.6 CM3 Register

b7 b6 b5 b4 b1b2b3 Symbol

CM2

Address

4004Dh

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Oscillator Stop Detection Register (1)

Oscillator Stop Detection

Enable Bit (2, 3)

0: Disable oscillator stop detection

1: Enable oscillator stop detection RW

RWReserved

0: Main clock oscillator has not been

stopped

1: Main clock oscillator stop detected

Oscillator Stop Detection

Flag (4)

RWReserved

0: Main clock oscillator active

1: Main clock oscillator stopped

Main Clock Monitor Flag (5)

Notes:

1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.

2. Set this bit to 0 when f256 is selected as the base clock source in low speed mode.

3. When the PM21 bit in the PM2 register is 1 (clock change disabled), the CM20 bit cannot be changed by a

write access.

4. When a main clock oscillator stop is detected, this bit becomes 1. It can be set to 0 by a program, however

not to 1. When it is set to 0 while the main clock oscillator is stopped, it does not become 1 until the next

main clock oscillator stop is detected.

5. After an oscillator stop detection interrupt occurs, read this bit several times to determine the main clock

state.

Should be written with 0

0000 0

CM20

—

(b1)

CM22

CM23

—

(b7-b4)

b7 b6 b5 b4 b1b2b3 Symbol

CM3

Address

4005Ah

Reset Value

XXXX XX00b

FunctionBit Symbol Bit Name RW

Low Speed Mode Clock Control Register (1)

Low Speed Mode Base

Clock Select Bit

b1 b0

00:fC

0 1 : f256 (main clock divided by 256)

1 0 : fOCO4 (on-chip oscillator

divided by 4) (2)

1 1 : Do not use this combination

Notes:

1. Rewrite this register after setting the PRC27 bit in the PRCR2 register to 1 (write enabled) and while the

BCS bit in the CCR register is 0 (PLL clock).

2. The on-chip oscillator clock starts when the CM31 bit is set to 1.

CM30

—

(b7-b2)

RWCM31

No register bits; should be written with 0 and read as undefined

value —

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R32C/117 Group 8. Clock Generator

Figure 8.7 TCSPR Register

Figure 8.8 CPSRF Register

b7 b6 b5 b4 b1b2b3 Symbol

TCSPR

Address

035Fh

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Count Source Prescaler Register

f2n is either the main clock or

peripheral clock source divided by

2n. If n = 0, the clock is not divided (n

= setting value)

Divide Ratio Select Bit (1)

0: Stop divider operation

1: Start divider operation

Divider Operation Enable

Bit

Note:

1. Set the CST bit to 0 before rewriting bits CNT3 to CNT0.

Reserved RWShould be written with 0

000

CNT0

CNT1

CNT2

CNT3

—

(b6-b4)

CST

b7 b6 b5 b4 b1b2b3 Symbol

CPSRF

Address

0341h

Reset Value

0XXX XXXXb

FunctionBit Symbol Bit Name RW

Clock Prescaler Reset Register

When this bit is set to 1, the fC

divided-by-32 divider is initialized.

The bit is read as 0

Clock Prescaler Reset Bit

—

No register bits; should be written with 0 and read as undefined

value

—

(b6-b0)

CPSR

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R32C/117 Group 8. Clock Generator

Figure 8.9 PM2 Register

b7 b6 b5 b4 b1b2b3 Symbol

PM2

Address

40053h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Processor Mode Register 2 (1)

System Clock Protect Bit (2, 3)

0: Protect the clock by the PRCR

1: Clock change disabled

0: Peripheral clock source

1: Main clock

f2n Clock Source Select Bit

(5)

Notes:

1. Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting this register.

2. Once this bit is set to 1, it cannot be set to 0 by a program.

3. When the PM21 bit is set to 1, the following bits cannot be changed by a write access:

CM02 bit in the CM0 register (the peripheral clock source state in wait mode)

CM05 bit in the CM0 register (main clock oscillator enabled/disabled)

CM10 bit in the CM1 register (PLL oscillator enabled/disabled)

CM20 bit in the CM2 register (oscillator stop detection enabled/disabled)

4. When the PM24 bit is 0, the forced cutoff of the three-phase motor control timers is also disabled.

5. Stop all the peripherals that use f2n before rewriting this bit.

RWReserved Should be written with 0

Reserved Should be written with 0

0: NMI disabled (4)

1: NMI enabled

NMI Enable Bit (2)

Reserved Should be written with 0

0 0 0 0 0

—

(b0)

PM21

—

(b3-b2)

PM24

—

(b5)

PM26

—

(b7)

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R32C/117 Group 8. Clock Generator

Figure 8.10 PM3 Register

b7 b6 b5 b4 b1b2b3 Symbol

PM3

Address

40048h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Processor Mode Register 3 (1)

Peripheral Clock Source

Divide Ratio Select Bit (2)

b6 b5

0 0 : Divide-by-8

0 1 : Divide-by-6

1 0 : Divide-by-4

1 1 : Divide-by-2 RW

RWReserved

Notes:

1. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register. Stop all the

peripherals that use fAD, f1, f8, f32, or f2n (when the clock source is the peripheral clock source) to rewrite

this register.

2. Select a divide ratio so that the peripheral clock source frequency does not exceed the maximum value

specified in the electrical characteristics

RWReserved Should be written with 0

Should be written with 0

0 00000

—

(b4-b0)

PM35

PM36

—

(b7)

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R32C/117 Group 8. Clock Generator

The following sections illustrate clocks generated in clock generators.

8.1.1 Main Clock

The main clock is generated by the main clock oscillator. This clock can be a clock source for the PLL

reference clock or peripheral clocks. It also functions as an operating clock for the CAN module.

The main clock oscillator is configured with two pins, XIN and XOUT, connected by an oscillator or

resonator. The circuit has an on-chip feedback resistor which is separated from the oscillator in stop

mode to save power consumption. An external clock can be applied to the XIN pin in this circuit. Figure

8.11 shows an example of a main clock circuit connection.

Circuit constants vary depending on the oscillator. Circuit constants should be set as per the oscillator

manufacturer’s recommendations.

After a reset, the main clock oscillator is still independently active and disconnected from the PLL

frequency synthesizer. A PLL frequency synthesizer self-oscillating clock divided by 12 is provided to

the CPU.

Setting the CM05 bit in the CM0 register to 1 (main clock oscillator disabled) enables power-saving. In

this case, the clock applied to the XOUT pin becomes high. The XIN pin connected to the XOUT pin by

an embedded feedback resistor is also driven high. Do not set the CM05 bit to 1 when an external clock

is applied to the XIN pin.

All clocks, including the main clock, stop in stop mode. Refer to 8.7 “Power Control” for details.

Figure 8.11 Main Clock Circuit Connection

XIN

XOUT

CIN

COUT

Oscillator

Rd (1)

MCU

(feedback resistor embedded)

XIN

XOUT

MCU

(feedback resistor embedded)

External clock

Open

VCC

VSS

Note:

1. Insert a damping resistor if required. Resistance values may vary according to oscillator setting. Values

recommended by the manufacturer should be set. A feedback resistor should be placed between XIN and

XOUT if the manufacturer recommends placing a resistor externally.

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R32C/117 Group 8. Clock Generator

8.1.2 Sub Clock (fC)

The sub clock is generated by the sub clock oscillator. This clock can be a clock source for the CPU

clock and a count source for timers A and B. It can be output from the CLKOUT pin.

The sub clock oscillator is configured with pins XCIN and XCOUT connected by a crystal oscillator. The

circuit has a on-chip feedback resistor which is separated from the oscillator in stop mode to save

power consumption. An external clock can be applied to the XCIN pin. Figure 8.12 shows an example

of a sub clock circuit connection. Circuit constants vary depending on the oscillator. Circuit constants

should be set as per the oscillator manufacturer’s recommendations.

After a reset, the sub clock is stopped and the feedback resistor is separated from the oscillator. In

order to start the sub clock oscillation, first set bits PD8_6 and PD8_7 in the PD8 register to 0 (input

mode), and the PU25 bit in the PUR2 register to 0 (pull-up resistor disabled). Then, set the CM04 bit in

the CM0 register to 1 (XCIN-XCOUT oscillator).

To input an external clock to the XCIN pin, set bits PD8_7 and PU25 to 0 and then the CM04 bit to 1.

The clock applied to the XCIN pin becomes a clock source for the sub clock.

When the CM3 register is set to 00h (fC) and the BCS bit in the CCR register is set to 1 (fC, fOCO4, or

f256) after the sub clock oscillation has stabilized, the sub clock becomes the base clock of the CPU

clock and the peripheral bus clock.

All clocks, including the sub clock, stop in stop mode. Refer to 8.7 “Power Control” for details.

Figure 8.12 Sub Clock Circuit Connection

XCIN

XCOUT

CCIN

CCOUT

Oscillator

Rcd (1)

MCU

(feedback resistor embedded)

XCIN

XCOUT

MCU

(feedback resistor embedded)

External clock

Open

VCC

VSS

Note:

1. Insert a damping resistor if required. Resistance values vary according to oscillator setting. Values

recommended by the manufacturer should be set. A feedback resistor should be placed between XCIN and

XCOUT if the manufacturer recommends placing a resistor externally.

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R32C/117 Group 8. Clock Generator

8.1.3 PLL Clock

The PLL clock is generated by the PLL frequency synthesizer based on the main clock. This clock can

be a clock source for any clock including the CPU clock and the peripheral clock.

Figure 8.13 shows a block diagram of the PLL frequency synthesizer. Figures 8.14 and 8.15 show

registers PLC0 and PLC1, respectively.

Figure 8.13 PLL Frequency Synthesizer Block Diagram

Figure 8.14 PLC0 Register

Divider (m)

Reference

counter (r)

Main clock

(XIN)

Phase

comparator Charge pump Filter

VCO

Dual-modulus

prescaler

(p = 5, 6)

Swallow

counter (a)

Main counter

(n)PLL clock

Reference

clock

SEO bit in the

PLC1 register

Symbol

PLC0

Address

40020h

Reset Value

0000 0001b

FunctionBit Symbol Bit Name RW

PLL Control Register 0 (1, 2)

Set the bits to n - 1

(n = divide ratio of the main counter)

Main Counter Divide Ratio

Setting Bit

Swallow Counter Divide

Ratio Setting Bit

The divide ratio of the dual-modulus

prescaler is 6 (in a out of n times) or

5 (in other cases) (a = setting value)

b7 b6 b5 b4 b1b2b3 b0

MCV0

MCV1

MCV2

MCV3

MCV4

SCV0

SCV1

SCV2

Notes:

1. Set the PRC2 bit in the PRCR register to 1 (write enabled) just before rewriting this register. No interrupt

handling or DMA transfers should be inserted between these two instructions.

2. This register can be rewritten only once after a reset.

R01UH0211EJ0120 Rev.1.20 Page 94 of 604

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R32C/117 Group 8. Clock Generator

Figure 8.15 PLC1 Register

In the PLL frequency synthesizer, the pulse-swallow operation is implemented. The divide ratio m is

simply expressed by n×p. However, with the swallow counter, the divide ratio p is 6 in a out of n, or 5 in

other cases, the actual m is therefore given by the formula below:

The setting range of a is , .

As r is the divide ratio of the reference counter, the PLL clock has a m/r times the main clock (XIN)

frequency.

After a reset, the reference counter is divided by 16, and the PLL frequency synthesizer is multiplied by

10. Since the main clock as a reference clock is disconnected, the PLL frequency synthesizer may self-

oscillate at its own frequency of fSO(PLL).

Each register should be set to meet the following conditions:

-The reference clock, which is the main clock divided by r, should be between 2 to 4 MHz.

-The divide ratio m is .

For the setting of registers PLC1 and PLC0, Table 8.2 should be applied. While the main clock

oscillation is stable, a wait time of tLOCK(PLL) is necessary between rewriting registers PLC1 and PLC0,

and the PLL clock becoming stable.

Symbol

PLC1

Address

40021h

Reset Value

0001 1111b

FunctionBit Symbol Bit Name RW

PLL Control Register 1 (1)

Should be written with 0

Note:

1. Set the PRC2 bit in the PRCR register to 1 (write enabled) just before rewriting this register. No interrupt

handling or DMA transfers should be inserted between these two instructions.

Set the bits to r - 1

(r = divide ratio of the main clock)

Reference Counter Divide

Ratio Setting Bit

Self-oscillating Setting Bit 0: PLL lock-in

1: Self-oscillating RW

Reserved

b7 b6 b5 b4 b1b2b3 b0

000

RCV0

RCV1

RCV2

RCV3

SEO

—

(b7-b5)

mnp=

---6na–

------------5+





=

5na+=

0a5

0an

PLL clock frequency fPLL

----main clock frequency=

5na+

--------------- main clock frequency=

25 m100

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R32C/117 Group 8. Clock Generator

Note:

1. Registers PLC1 and PLC0 should be set according to the list above.

Table 8.2 PLC1 and PLC0 Register Settings (1)

Main Clock rReference

Clock nam

PLC1

Setting

PLC0

Setting

m/r PLL Clock

4 MHz 2 2 MHz 9 3 48 01h 68h 24 96 MHz

6 MHz 2 3 MHz 6 2 32 01h 45h 16 96 MHz

8 MHz 3 2.6667 MHz 7 1 36 02h 26h 12 96 MHz

10 MHz 5 2 MHz 9 3 48 04h 68h 9.6 96 MHz

12 MHz 4 3 MHz 6 2 32 03h 45h 8 96 MHz

16 MHz 5 3.2 MHz 6 0 30 04h 05h 6 96 MHz

4 MHz 1 4 MHz 5 0 25 00h 04h 25 100 MHz

6 MHz 3 2 MHz 10 0 50 02h 09h 16.6667 100 MHz

8 MHz 2 4 MHz 5 0 25 01h 04h 12.5 100 MHz

10 MHz 3 3.3333 MHz 6 0 30 02h 05h 10 100 MHz

12 MHz 3 4 MHz 5 0 25 02h 04h 8.3333 100 MHz

16 MHz 4 4 MHz 5 0 25 03h 04h 6.25 100 MHz

4 MHz 1 4 MHz 6 0 30 00h 05h 30 120 MHz

6 MHz 2 3 MHz 8 0 40 01h 07h 20 120 MHz

8 MHz 2 4 MHz 6 0 30 01h 05h 15 120 MHz

10 MHz 3 3.3333 MHz 7 1 36 02h 26h 12 120 MHz

12 MHz 3 4 MHz 6 0 30 02h 05h 10 120 MHz

16 MHz 4 4 MHz 6 0 30 03h 05h 7.5 120 MHz

4 MHz 1 4 MHz 6 2 32 00h 45h 32 128 MHz

6 MHz 3 2 MHz 12 4 64 02h 8Bh 21.3333 128 MHz

8 MHz 2 4 MHz 6 2 32 01h 45h 16 128 MHz

10 MHz 5 2 MHz 12 4 64 04h 8Bh 12.8 128 MHz

12 MHz 3 4 MHz 6 2 32 02h 45h 10.6667 128 MHz

16 MHz 4 4 MHz 6 2 32 03h 45h 8 128 MHz

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R32C/117 Group 8. Clock Generator

8.1.4 On-chip Oscillator Clock

The on-chip oscillator clock is generated by the on-chip oscillator (OCO). This clock can be a clock

source for the CPU clock and a count source for timers A and B. This clock has a frequency of

approximately 125 kHz. The on-chip oscillator clock divided by 4 can be used as the base clock for the

CPU clock and peripheral bus clock.

The on-chip oscillator clock is stopped after a reset. It starts running when setting the CM31 bit in the

CM3 register to 1. It is not necessary to wait for stabilization because the on-chip oscillator instantly

starts oscillating.

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R32C/117 Group 8. Clock Generator

8.2 Oscillator Stop Detection

This function detects the main clock is stopped when its oscillator stops running due to an external factor.

When the CM20 bit in the CM2 register is 1 (enable oscillator stop detection), an oscillator stop detection

interrupt request is generated as soon as the main clock stops. Simultaneously, the PLL frequency

synthesizer starts to self-oscillate at its own frequency. If the PLL frequency synthesizer is the clock

source for CPU clock and peripheral clock, these clocks continue running.

When an oscillator stop is detected, the following bits in the CM2 register become 1:

• The CM22 bit: main clock oscillator stop detected

• The CM23 bit: main clock oscillator stopped

8.2.1 How to Use Oscillator Stop Detection

The oscillator stop detection interrupt shares vectors with the watchdog timer interrupt and the low

voltage detection interrupt. When using these interrupts simultaneously, read the CM22 bit with an

interrupt handler to determine if an oscillator stop detection interrupt request has been generated.

When the main clock oscillator resumes running after an oscillator stop is detected, the PLL clock

frequency may temporarily exceed the preset value before the PLL frequency synthesizer oscillation

stabilizes. As soon as an oscillator stop is detected, the main clock oscillator should be stopped from

resuming (set the CM05 bit in the CM0 register to 1) or the divide ratios of the base clock and peripheral

clock source should be increased by a program. They can be set using bits BCD1 and BCD0 in the

CCR register and bits PM36 and PM35 in the PM3 register.

In low speed mode, when the main clock oscillator stops running, an oscillator stop detection interrupt

request is generated if the CM20 bit is set to 1 (enable oscillator stop detection). The CPU clock

remains running with a low speed clock source. Note that if the base clock is f256, which is the main

clock divided by 256, oscillator stop detection cannot be used.

The oscillator stop detection is provided to handle main clock stop caused by external factors. To stop

the main clock oscillator by a program, i.e., to enter stop mode or to set the CM05 bit to 1 (main clock

oscillator disabled), the CM20 bit in the CM2 register should be set to 0 (disable oscillator stop

detection). To enter wait mode, this bit should be also set to 0.

The oscillator stop detection functions depending on the voltage of a capacitor which is being changed.

In more concrete terms, this function detects that the oscillator is stopped when the main clock goes

lower than approximately 500 kHz. Note that if the CM22 bit is set to 0 by a program in an interrupt

handler while the frequency is around 500 kHz, a stack overflow may occur due to multiple interrupt

requests.

8.3 Base Clock

The base clock is a reference clock for the CPU clock and peripheral bus clock. The base clock after a

reset is the PLL clock divided by 6.

The base clock source is selected between the PLL clock and the low speed clocks which contain the sub

clock (fC), on-chip oscillator clock divided by 4 (fOCO4), and main clock divided by 256 (f256).

If the PLL clock is selected, it is divided by 2, 3, 4, or 6 to become the base clock. If a low speed clock is

selected, the clock itself can be the base clock.

The base clock source is set using the BCS bit in the CCR register and the divide ratio for the PLL clock is

set using bits BCD1 and BCD0. Bits CM31 and CM30 in the CM3 register select a low speed clock.

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R32C/117 Group 8. Clock Generator

8.4 CPU Clock and Peripheral Bus Clock

The CPU operating clock is referred to as the CPU clock. The CPU clock after a reset is the base clock

divided by 2.

The CPU clock source is the base clock, and its divide ratio is selected by setting bits CCD1 and CCD0 in

the CCR register. The base clock divided by 2 to 4 becomes the peripheral bus clock. Its divide ratio is

selected by setting bits PCD1 and PCD0 in the CCR register. The peripheral bus clock also functions as a

count source for the watchdog timer and operating clock the CAN module.

In memory expansion mode or microprocessor mode, the peripheral bus clock can be output as BCLK

from the BCLK pin. This clock is used as a reference clock for external timing generation. Refer to 8.6

“Clock Output Function” for details.

To prevent the CPU clock, whose clock source is the PLL clock, from stopping when the CPU becomes

out of control, set the following while the CM05 bit in the CM0 register is 0 (main clock oscillator enabled)

and the BCS bit in the CCR register is 0 (PLL clock selected as base clock source):

(1) Set the PRC1 bit in the PRCR register to 1 (write enabled to the PM2 register).

(2) Set the PM21 bit in the PM2 register to 1 (clock change disabled).

8.5 Peripheral Clock

The peripheral clock is an operating clock or a count source for the peripherals excluding the watchdog

timer and the CAN module. The source of this clock is generated by a clock, which has the same

frequency as the PLL clock, divided by 2, 4, 6, or 8 according to the settings of bits PM36 and PM35 in the

PM3 register. The peripheral clock is classified into three types of clock as follows:

(1) f1, f8, f32, f2n

f1, f8, and f32 are the peripheral clock sources divided by 1, 8, and 32, respectively. The clock source

for f2n is selected between the peripheral clock source and the main clock by setting the PM26 bit in

the PM2 register. The f2n divide ratio can be set using bits CNT3 to CNT0 in the TCSPR register (n = 1

to 15, not divided when n = 0).

f1, f8, f32, and f2n, whose clock source is the peripheral clock source, stop in low power mode or when

the CM02 bit is set to 1 (peripheral clock source stopped in wait mode) to enter wait mode.

f1, f8, and f2n are used as a count source for timers A and B or an operating clock for the serial

interface. f1 is used as an operating clock for the intelligent I/O as well.

f8 and f32 can be output from the CLKOUT pin. Refer to 8.6 “Clock Output Function” for details.

(2) fAD

fAD, which has the same frequency as peripheral clock source, is an operating clock for the A/D

converter.

This clock stops in low power mode or when the CM02 bit is set to 1 (peripheral clock source stopped in

wait mode) to enter wait mode.

(3) fC32

fC32, which is a sub clock divided by 32, or on-chip oscillator clock divided by 128, is used as the count

source for timers A and B. This clock is available when the sub clock or on-chip oscillator clock is

active.

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R32C/117 Group 8. Clock Generator

8.6 Clock Output Function

Low speed clocks, f8, and f32 can be output from the CLKOUT pin.

In memory expansion mode or microprocessor mode, the BCLK, that is, the peripheral bus clock which is

the base clock divided by 2 to 4 can also be output from the BCLK pin.

Tables 8.3 and 8.4 list the CLKOUT pin functions in single-chip mode and memory expansion mode or

microprocessor mode, respectively.

Notes:

1. Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting this register.

2. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.

Notes:

1. Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting this register.

2. Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.

3. When the PM07 bit is set to 0 (output BCLK), set bits CM01 and CM00 to 00b (I/O port P5_3).

Table 8.3 CLKOUT Pin Functions in Single-chip Mode

PM0 Register (1) CM0 Register (2)

CLKOUT Pin Function

PM07 CM01 CM00

0 or 1 0 0 I/O port P5_3

1 0 1 Output a low speed clock

1 1 0 Output f8

1 1 1 Output f32

Table 8.4 CLKOUT Pin Functions in Memory Expansion Mode or Microprocessor Mode

PM0 Register (1) CM0 Register (2)

CLKOUT Pin Function

PM07 CM01 CM00

00 (3) 0 (3) Output BCLK

1 0 0 Output low (not function as P5_3)

1 0 1 Output a low speed clock

1 1 0 Output f8

1 1 1 Output f32

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R32C/117 Group 8. Clock Generator

8.7 Power Control

Power control has three modes: wait mode, stop mode, and normal operating mode.

The name “normal operating mode” is used restrictively in this chapter, and it indicates all other modes

except wait mode and stop mode. Figure 8.16 shows a block diagram of the state transition in normal

operating mode, stop mode, and wait mode.

Figure 8.16 State Transition in Stop Mode and Wait Mode

Reset

PLL self-oscillation

mode

PLL mode

(high/medium speed)

Low speed mode,

Low power mode

PLL self-oscillation

mode

Normal operating

mode

Wait mode

WAIT

instruction

Interrupt

WAIT

instruction

Interrupt

WAIT

instruction

Interrupt

All oscillators are stopped CPU operation is stopped

BCS: Bit in the CCR register

MCV4 to MCV0, SCV2 to SCV0: Bits in the PLC0 register

SEO, RCV3 to RCV0: Bits in the PLC1 register

SEO = 0

Set MCV4 to MCV0, SCV2 to

SCV0 (1) and RCV3 to RCV0

BCS = 1BCS = 0

BCS = 1 BCS = 0

SEO = 0SEO = 1

Stop mode (2)

STOP

instruction

Interrupt

Notes:

1. The PLC0 register can be set only once after a reset.

2. When the sub clock is selected as the base clock source, do not enter stop mode.

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R32C/117 Group 8. Clock Generator

8.7.1 Normal Operating Mode

Normal operating mode is classified into the five modes shown below.

In normal operating mode, the CPU clock and peripheral clock are provided to operate the CPU and

peripherals. Power consumption is controlled by the CPU clock frequency. The higher the CPU clock

frequency is, the more processing power increases. The lower the CPU clock frequency is, the less

power consumption is required. Power consumption can be reduced by stopping oscillators that are not

being used.

(1) PLL Mode (high speed mode)

In this mode, the PLL clock is selected as the base clock source, and the main clock is provided as the

reference clock source for the PLL frequency synthesizer. High speed mode enables the CPU to

operate at the maximum operating frequency. The PLL clock divided by 2 becomes the base clock. The

base clock frequency should be identical to that of the CPU clock. fAD, f1, f8, f32, and f2n can be used

as the peripheral clocks. When the sub clock or the on-chip oscillator clock is provided, fC32 can be

used as the count source for timers A and B.

(2) PLL Mode (medium speed mode)

This mode indicates all modes in PLL mode except high speed mode. The PLL clock divided by 2, 3, 4,

or 6 becomes the base clock and the base clock divided by 1 to 4 becomes the CPU clock. fAD, f1, f8,

f32, and f2n can be used as the peripheral clocks. When the sub clock or the on-chip oscillator clock is

provided, fC32 can be used as the count source for timers A and B.

(3) Low Speed Mode

In this mode, a low speed clock is used as the base clock source. The low speed clock becomes the

base clock and the base clock divided by 1 to 4 becomes the CPU clock. fAD, f1, f8, f32, and f2n can be

used as the peripheral clocks. When the sub clock or the on-chip oscillator clock is provided, fC32 can

be used as the count source for timers A and B.

(4) Low Power Mode

This is a state where the main clock oscillator and the PLL frequency synthesizer are stopped after

switching to low speed mode. The sub clock or the on-chip oscillator clock divided by 4 becomes the

base clock and the base clock divided by 1 to 4 becomes the CPU clock. fC32, which is the only

peripheral clock available, can be used as the count source for timers A and B. By setting the MRS bit

in the VRCR register to 1 (main regulator stopped), this mode consumes even less power than the

modes above.

(5) PLL Self-oscillation Mode

In this mode, the PLL clock is selected as the base clock source, and the main clock is not provided as

the reference clock source for the PLL frequency synthesizer. The PLL frequency synthesizer self-

oscillates at its own frequency. The PLL clock divided by 2, 3, 4, or 6 becomes the base clock and the

base clock divided by 1 to 4 becomes the CPU clock. fAD, f1, f8, f32, and f2n can be used as the

peripheral clocks. When the sub clock or the on-chip oscillator clock is provided, fC32 can be used as

the count source for timers A and B.

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R32C/117 Group 8. Clock Generator

The state transition within normal operating mode can be very complicated; therefore only the block

diagrams of typical state transitions are shown. Figures 8.17 to 8.19 show block diagrams of the

respective state transitions: state when the sub clock is used, state when the main clock divided by 256

is used, and state when the on-chip oscillator clock is used. As for the state transitions other than the

above, setting of each register and the usage notes below can be used as references.

• PLL can be switched from PLL oscillating to self-oscillating by setting the SEO bit in the PLC1

to 0 (main clock oscillator disabled) to stop the main clock.

• The divide ratio of the clock should be increased and the frequency should be decreased by using

bits BCD1 to BCD0 in the CCR register or bits PM36 to PM35 in the PM3 register before setting the

SEO bit to 0 (PLL oscillating) in order to switch back PLL self-oscillation mode to PLL mode. Set

back the settings of bits BCD1 to BCD0 and bits PM36 to PM35 once PLL oscillation is stabilized

after setting the SEO bit to 0.

• Before switching the CPU clock to another clock, that clock should be stabilized. In particular, the

sub clock oscillator may require more time to stabilize (1). Therefore, certain waiting time to switch

should be taken by a program immediately after turning the MCU on or exiting stop mode.

Note:

1. Contact the oscillator manufacturer for details on oscillator stabilization time.

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R32C/117 Group 8. Clock Generator

Figure 8.17 State Transition When Using the Sub Clock

Main clock oscillation

Sub clock stop

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / 12

PLC0 = 01h PLC1 = 1Fh

CCR = 00011000b

CM04 = 0 CM05 = 0 CM10 = 0

PLL self-oscillation mode (after a reset)

CM04 = 0

Main clock oscillation

Sub clock stop

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / 12

PLC0 = XXh PLC1 = 0Xh

CCR = 00011000b

CM04 = 0 CM05 = 0 CM10 = 0

PLC0 = XXh (1)

PLC1 = 0Xh

Main clock oscillation

Sub clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / 12

PLC0 = 01h PLC1 = 1Fh

CCR = 00011000b

CM04 = 1 CM05 = 0 CM10 = 0

Main clock oscillation

Sub clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(XCIN) / m

PLC0 = XXh PLC1 = 0Xh

CCR = 10XXXXXXb

CM04 = 1 CM05 = 0 CM10 = 0

BCS = 1 (2)

BCS = 0 (3)

Low speed mode

Main clock stop

Sub clock oscillation

PLL clock stop

CPU clock: f(XCIN) / m

PLC0 = XXh PLC1 = 1Xh

CCR = 10XXXXXXb

CM04 = 1 CM05 = 1 CM10 = 1

Low power mode

Main clock oscillation

Sub clock oscillation

PLL clock stop

CPU clock: f(XCIN) / m

PLC0 = XXh PLC1 = 0Xh

CCR = 10XXXXXXb

CM04 = 1 CM05 = 0 CM10 = 1

Low speed mode

CM10 = 0CM10 = 1

PLL mode

Main clock oscillation

Sub clock stop

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM04 = 0 CM05 = 0 CM10 = 0

CCR = 00XXXXXXb

Main clock oscillation

Sub clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM04 = 1 CM05 = 0 CM10 = 0

Main clock oscillation

Sub clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / 12

PLC0 = XXh PLC1 = 0Xh

CCR = 00011000b

CM04 = 1 CM05 = 0 CM10 = 0

CCR = 00XXXXXXb

CM04 = 1

CM05 = 0

SEO = 0

PLL self-oscillation mode

PLC0 = XXh (1)

PLC1 = 0Xh

CM04 = 0

CM04 = 1

CM04 = 0

CM04 = 1

Main clock stop is

detected when CM20 = 1

Main clock stop is detected

when CM20 = 1

Main clock stop is

detected when CM20 = 1

PLL mode

CM10 = 0

CM10 = 1

CM05 = 1

SEO = 1

PLL mode PLL mode

Main clock stop (damaged)

Sub clock stop

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM04 = 0 CM05 = 0 CM10 = 0

PLL self-oscillation modePLL self-oscillation mode

Main clock stop (damaged)

Sub clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(XCIN) / m

PLC0 = XXh PLC1 = 0Xh

CCR = 10XXXXXXb

CM04 = 1 CM05 = 0 CM10 = 0

Low speed mode

Main clock stop (damaged)

Sub clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM04 = 1 CM05 = 0 CM10 = 0

Main clock stop

Sub clock stop

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 1Xh

CCR = 00XXXXXXb

CM04 = 0 CM05 = 1 CM10 = 0

PLL self-oscillation modePLL self-oscillation mode

Main clock stop

Sub clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(XCIN) / m

PLC0 = XXh PLC1 = 1Xh

CCR = 10XXXXXXb

CM04 = 1 CM05 = 1 CM10 = 0

Low speed mode

Main clock stop

Sub clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 1Xh

CCR = 00XXXXXXb

CM04 = 1 CM05 = 1 CM10 = 0

CM04 = 0

CM04 = 1 BCS = 1 (2)

BCS = 0 (3)

: Arrows indicate a one-way transition between modes. No transition should be made unless indicated.

BCS: Bit in the CCR register

CM04 and CM05: Bits in the CM0 register

CM10: Bit in the CM1 register

CM20: Bit in the CM2 register

SEO: Bit in the PLC1 register

PLC0 = XXh: The multiplication ratio of the PLL clock should be set using bits MCV4 to MCV0 and bits SCV2 to

SCV0 in the PLC0 register.

PLC1 = 0Xh: The divisor of the reference clock should be set using bits RCV3 to RCV0 in the PLC1 register. The

PLL clock frequency should not exceed the maximum value specified in the electrical characteristics.

CCR = 00XXXXXXb: The divisor of each clock should be set using the CCR register. The CPU clock frequency and

the peripheral bus clock frequency should not exceed the maximum values specified in the

electrical characteristics.

Notes:

1. The PLC0 register can be set only once after reset is released.

2. This clock should be switched after the sub clock oscillation is fully stabilized.

3. This clock should be switched after the PLL clock oscillation is fully stabilized.

CM05 = 1

SEO = 1

CM05 = 1

SEO = 1

CM05 = 1

SEO = 1

CM10 = 1

CM10 = 0

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R32C/117 Group 8. Clock Generator

Figure 8.18 State Transition When Using the Main Clock Divided by 256

Main clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / 12

PLC0 = 01h PLC1 = 1Fh

CCR = 00011000b

CM05 = 0 CM10 = 0 CM30 = 0

PLL self-oscillation mode (after a reset)

CM30 = 0

Main clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / 12

PLC0 = XXh PLC1 = 0Xh

CCR = 00011000b

CM05 = 0 CM10 = 0 CM30 = 0

PLC0 = XXh (1)

PLC1 = 0Xh

Main clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / 12

PLC0 = 01h PLC1 = 1Fh

CCR = 00011000b

CM05 = 0 CM10 = 0 CM30 = 1

Main clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(XIN) / 256 / m

PLC0 = XXh PLC1 = 0Xh

CCR = 10XXXXXXb

CM05 = 0 CM10 = 0 CM30 = 1

BCS = 1

BCS = 0 (2)

Low speed mode

Main clock oscillation

PLL clock stop

CPU clock: f(XIN) / 256 / m

PLC0 = XXh PLC1 = 0Xh

CC = 10XXXXXXb

CM05 = 0 CM10 = 1 CM30 = 1

Low speed mode

CM10 = 0CM10 = 1

Main clock stop (damaged)

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM05 = 0 CM10 = 0 CM30 = 0

PLL self-oscillation modePLL self-oscillation mode

PLL mode

Main clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM05 = 0 CM10 = 0 CM30 = 0

CCR = 00XXXXXXb

Main clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM05 = 0 CM10 = 0 CM30 = 1

Main clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / 12

PLC0 = XXh PLC1 = 0Xh

CCR = 00011000b

CM05 = 0 CM10 = 0 CM30 = 1

CCR = 00XXXXXXb

CM30 = 1

Main clock stop (damaged)

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM05 = 0 CM10 = 0 CM30 = 1

PLL self-oscillation mode

PLC0 = XXh (1)

PLC1 = 0Xh

CM30 = 0

CM30 = 1

CM30 = 0

CM30 = 1

Main clock stop is detected

when CM20 = 1

Main clock stop is detected

when CM20 = 1

PLL mode

Notes:

1. The PLC0 register can be set only once after reset is released.

2. This clock should be switched after the PLL clock oscillation is fully stabilized.

Main clock stop

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 1Xh

CCR = 00XXXXXXb

CM05 = 1 CM10 = 0 CM30 = 0

PLL self-oscillation modePLL self-oscillation mode

Main clock stop

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 1Xh

CCR = 00XXXXXXb

CM05 = 1 CM10 = 0 CM30 = 1

CM05 = 1

SEO = 1

CM05 = 1

SEO = 1

CM30 = 0

CM30 = 1

PLL mode PLL mode

: Arrows indicate a one-way transition between modes. No transition should be made unless indicated.

BCS: Bit in the CCR register

CM05: Bit in the CM0 register

CM10: Bit in the CM1 register

CM20: Bit in the CM2 register

CM30: Bit in the CM3 register

SEO: Bit in the PLC1 register

PLC0 = XXh: The multiplication ratio of the PLL clock should be set using bits MCV4 to MCV0 and bits SCV2 to SCV0

in the PLC0 register.

PLC1 = 0Xh: The divisor of the reference clock should be set using bits RCV3 to RCV0 in the PLC1 register. The

PLL clock frequency should not exceed the maximum value specified in the electrical characteristics.

CCR = 00XXXXXXb: The divisor of each clock should be set using the CCR register. The CPU clock frequency and

the peripheral bus clock frequency should not exceed the maximum values specified in the

electrical characteristics.

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R32C/117 Group 8. Clock Generator

Figure 8.19 State Transition When Using the On-chip Oscillator Clock

Main clock oscillation

On-chip oscillator clock stop

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / 12

PLC0 = 01h PLC1 = 1Fh

CCR = 00011000b

CM05 = 0 CM10 = 0 CM31 = 0

PLL self-oscillation mode (after a reset)

CM31 = 0

Main clock oscillation

On-chip oscillator clock stop

PLL clock oscillation × ((5n+a) / r)

CPU clock : f(PLL) / 12

PLC0 = XXh PLC1 = 0Xh

CCR = 00011000b

CM05 = 0 CM10 = 0 CM31 = 0

PLC0 = XXh (1)

PLC1 = 0Xh

Main clock oscillation

On-chip oscillator clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / 12

PLC0 = 01h PLC1 = 1Fh

CCR = 00011000b

CM05 = 0 CM10 = 0 CM31 = 1

Main clock oscillation

On-chip oscillator clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(OCO) / 4 / m

PLC0 = XXh PLC1 = 0Xh

CCR = 10XXXXXXb

CM05 = 0 CM10 = 0 CM31 = 1

BCS = 1

BCS = 0 (2)

Main clock stop

On-chip oscillator clock stop

PLL clock stop

CPU clock: f(OCO) / 4 / m

PLC0 = XXh PLC1 = 1Xh

CCR = 10XXXXXXb

CM05 = 1 CM10 = 1 CM31 = 1

Low power mode

Main clock oscillation

On-chip oscillator clock oscillation

PLL clock stop

CPU clock: f(OCO) / 4 / m

PLC0 = XXh PLC1 = 0Xh

CCR = 10XXXXXXb

CM05 = 0 CM10 = 1 CM31 = 1

Low speed mode

CM10 = 0CM10 = 1

PLL mode

Main clock oscillation

On-chip oscillator clock stop

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM05 = 0 CM10 = 0 CM31 = 0

Main clock oscillation

On-chip oscillator clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM05 = 0 CM10 = 0 CM31 = 1

Main clock oscillation

On-chip oscillator clock oscillation

PLL clock oscillation × ((5n+a) / r)

CPU clock : f(PLL) / 12

PLC0 = XXh PLC1 = 0Xh

CCR = 00011000b

CM05 = 0 CM10 = 0 CM31 = 1

CCR = 00XXXXXXb

CM31 = 1

CM05 = 0

SEO = 0

CM05 = 1

SEO = 1

PLL self-oscillation mode

PLC0 = XXh (1)

PLC1 = 0Xh

CM31 = 0

CM31 = 1

CM31 = 0

CM31 = 1

Main clock stop is

detected when CM20 = 1

Main clock stop is

detected when CM20 = 1

Main clock stop is

detected when CM20 = 1

PLL mode

Low speed mode

CCR = 00XXXXXXb

CM10 = 0

CM10 = 1

PLL modePLL mode

Main clock stop (damaged)

On-chip oscillator clock stop

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM05 = 0 CM10 = 0 CM31 = 0

PLL self-oscillation modePLL self-oscillation mode

Main clock stop (damaged)

On-chip oscillator clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(OCO) /4 / m

PLC0 = XXh PLC1 = 0Xh

CCR = 10XXXXXXb

CM05 = 0 CM10 = 0 CM31 = 1

Main clock stop (damaged)

On-chip oscillator clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 0Xh

CCR = 00XXXXXXb

CM05 = 0 CM10 = 0 CM31 = 1

Low speed mode

: Arrows indicate a one-way transition between modes. No transition should be made unless indicated.

BCS: Bit in the CCR register

CM05: Bit in the CM0 register

CM10: Bit in the CM1 register

CM20: Bit in the CM2 register

CM31: Bit in the CM3 register

SEO: Bit in the PLC1 register

PLC0 = XXh: The multiplication ratio of the PLL clock should be set using bits MCV4 to MCV0 and bits SCV2 to SCV0

in the PLC0 register.

PLC1 = 0Xh: The divisor of the reference clock should be set using bits RCV3 to RCV0 in the PLC1 register. The

PLL clock frequency should not exceed the maximum value specified in the electrical characteristics.

CCR = 00XXXXXXb: The divisor of each clock should be set using the CCR register. The CPU clock frequency and

the peripheral bus clock frequency should not exceed the maximum values specified in the

electrical characteristics.

Notes:

1. The PLC0 register can be set only once after reset is released.

2. This clock should be switched after the PLL clock oscillation is fully stabilized.

Main clock stop

On-chip oscillator clock stop

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 1Xh

CCR = 00XXXXXXb

CM05 = 1 CM10 = 0 CM31 = 0

PLL self-oscillation modePLL self-oscillation mode

Main clock stop

On-chip oscillator clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(OCO) /4 / m

PLC0 = XXh PLC1 = 1Xh

CCR = 10XXXXXXb

CM05 = 1 CM10 = 0 CM31 = 1

Main clock stop

On-chip oscillator clock oscillation

PLL clock oscillation (self-oscillation)

CPU clock: f(PLL) / b / m

PLC0 = XXh PLC1 = 1Xh

CCR = 00XXXXXXb

CM05 = 1 CM10 = 0 CM31 = 1

CM05 = 1

SEO = 1

CM05 = 1

SEO = 1

BCS = 1

BCS = 0 (2)

CM05 = 1

SEO = 1

Low speed mode

CM31 = 1

CM31 = 0

CM10 = 1

CM10 = 0

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R32C/117 Group 8. Clock Generator

8.7.2 Wait Mode

The base clock stops in wait mode, so clocks generated by the base clock, the CPU clock and

peripheral bus clock, stop running as well. Thus the CPU and watchdog timer, operated by these two

clocks, also stop. Since the main clock, sub clock, PLL clock, and on-chip oscillator clock continue

running, the peripherals using these clocks also continue operating.

8.7.2.1 Peripheral Clock Source Stop Function

When the CM02 bit in the CM0 register is 1 (peripheral clock source stopped in wait mode), power

consumption is reduced since peripheral clocks f1, f8, f32, f2n (when the clock source is the peripheral

clock source), and fAD stop running in wait mode. fC32 and f2n (when the clock source is the main

clock) do not stop running.

8.7.2.2 Entering Wait Mode

To enter wait mode, the following procedures should be completed before the WAIT instruction is

executed.

• Initial setting

Set the wake-up interrupt priority level (bits RLVL2 to RLVL0 in registers RIPL1 and RIPL2) to 7.

Then set each interrupt request level.

• Steps before entering wait mode

(1) Set the I flag to 0.

(2) Set the interrupt request level for each interrupt source (interrupt number from 1 to 127) to 0, if its

interrupt request level is not 0.

(3) Perform a dummy read of any of the interrupt control registers.

(4) Set the processor interrupt priority level (IPL) in the flag register to 0.

(5) Enable interrupts temporarily by executing the following instructions:

FSET I

NOP

FCLR I

(6) Set the interrupt request level for the interrupt to exit wait mode.

Do not rewrite the interrupt control register after this step.

(7) Set the IPL in the flag register.

(8) Set the interrupt priority level for resuming to the same level as the IPL.

Interrupt request level for the interrupt to exit wait mode > IPL = Interrupt priority level for

resuming

(9) Set the CM20 bit in the CM2 register to 0 (disable oscillator stop detection) when the oscillator

stop detection is used.

(10)Enter either PLL self-oscillation mode, low speed mode, or low power mode.

(11)Set the I flag to 1.

(12)Execute the WAIT instruction.

• After exiting wait mode

Set the wake-up interrupt priority level to 7 immediately after exiting wait mode.

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R32C/117 Group 8. Clock Generator

8.7.2.3 Pin State in Wait Mode

Table 8.5 lists the pin state in wait mode.

8.7.2.4 Exiting Wait Mode

The MCU exits wait mode by a hardware reset, an NMI, or a peripheral interrupt assigned to software

interrupt number from 0 to 63.

To exit wait mode using either a hardware reset or NMI, without using peripheral interrupts, set bits

ILVL2 to ILVL0 for the peripheral interrupts to 000b (interrupt disabled) before executing the WAIT

instruction.

The CM02 bit setting in the CM0 register affects the peripheral interrupts. When the CM02 bit is 0

(peripheral clock source not stopped in wait mode), peripheral interrupts for software interrupt numbers

from 0 to 63 can be used to exit wait mode. When this bit is 1 (peripheral clock source stopped in wait

mode), peripherals operated using clocks (f1, f8, f32, f2n whose clock source is the peripheral clock

source, and fAD) generated by the peripheral clock source stop operating. Therefore, the peripheral

interrupts cannot be used to exit wait mode. However, peripherals operated using clocks which are

independent from the peripheral clock source (fC32, external clock, and f2n whose clock source is the

main clock) do not stop operating. Thus, interrupts generated by these peripherals and assigned to

software interrupt numbers from 0 to 63 can be used to exit wait mode.

The CPU clock used when exiting wait mode by a peripheral interrupt or an NMI is the same clock used

when the WAIT instruction is executed.

Table 8.6 lists interrupts used to exit wait mode and usage conditions.

Table 8.5 Pin State in Wait Mode

Pin Memory Expansion Mode/

Microprocessor Mode Single-chip Mode

Address bus, data bus,

CS0 to CS3, BC0 to BC3

The state immediately before entering

wait mode is held —

RD, WR, WR0 to WR3 High —

HLDA, BCLK High —

ALE High —

Ports The state immediately before entering wait mode is held

DA0, DA1 The state immediately before entering wait mode is held

CLKOUT When a low

speed clock is

selected

The clock is output

When f8 or f32

is selected

The clock is output when the CM02 bit in the CM0 register is 0 (no

peripheral clock source stopped in wait mode).

The state immediately before entering wait mode is held when the CM02

bit is 1 (peripheral clock source stopped in wait mode)

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R32C/117 Group 8. Clock Generator

Notes:

1. INT6 to INT8 are available in the intelligent I/O interrupt only.

2. UART7 and UART8 are excluded.

Table 8.6 Interrupts for Exiting Wait Mode and Usage Conditions

Interrupt When the CM02 Bit is 0 When the CM02 Bit is 1

NMI Available Available

External interrupt (1) Available Available

Key input interrupt Available Available

Low voltage detection interrupt Available Available

Timer A interrupt

Timer B interrupt

Available in any mode Available in event counter mode, or

when the count source is fC32 or

f2n (when the main clock is selected

as the clock source)

Serial interface interrupt (2) Available when an internal or

external clock is used

Available when the external clock or

f2n (when the main clock is selected

as the clock source) is used

A/D conversion interrupt Available in single mode or single-

sweep mode

Should not be used

Intelligent I/O interrupt Available Should not be used

I2C-bus interface interrupt Available Should not be used

I2C-bus line interrupt Available Available

CAN wake-up interrupt Available Available

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R32C/117 Group 8. Clock Generator

8.7.3 Stop Mode

In stop mode, all of the clocks, except for those that are protected, stop running. That is, the CPU and

peripherals, operated by the CPU clock and peripheral clock, also stop. This mode saves the most

power.

8.7.3.1 Entering Stop Mode

To enter stop mode, the following procedures should be done before the STOP instruction is executed.

• Initial setting

Set the wake-up interrupt priority level (bits RLVL2 to RLVL0 in registers RIPL1 and RIPL2) to 7.

Then set each interrupt request level.

• Steps before entering stop mode

(1) Set the I flag to 0.

(2) Set the interrupt request level for each interrupt source (interrupt number from 1 to 127) to 0, if

the interrupt request level is not 0.

(3) Perform a dummy read of any of the interrupt control registers.

(4) Set the processor interrupt priority level (IPL) in the flag register to 0.

(5) Enable interrupts temporarily by executing the following instructions:

FSET I

NOP

FCLR I

(6) Set the interrupt request level for the interrupt to exit stop mode.

Do not rewrite the interrupt control register after this step.

(7) Set the IPL in the flag register.

(8) Set the interrupt priority level for resuming to the same level as the IPL.

Interrupt request level for the interrupt to exit stop mode > IPL = Interrupt priority level for

resuming

(9) Set the CM20 bit in the CM2 register to 0 (oscillator stop detection disabled) when the oscillator

stop detection is used.

(10)Change the base clock to either the main clock divided by 256 (f256) or the on-chip oscillator

clock divided by 4 (fOCO4).

(11)Set the I flag to 1.

(12)Execute the STOP instruction.

• After exiting stop mode

Set the wake-up interrupt priority level to 7 immediately after exiting stop mode.

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R32C/117 Group 8. Clock Generator

8.7.3.2 Pin State in Stop Mode

Table 8.7 lists the pin state in stop mode.

8.7.3.3 Exiting Stop Mode

The MCU exits stop mode by a hardware reset, NMI, low voltage detection interrupt, or a peripheral

interrupt assigned to software interrupt number from 0 to 63.

To exit stop mode using either a hardware reset or NMI, without using peripheral interrupts, set bits

ILVL2 to ILVL0 for the peripheral interrupts to 000b (interrupt disabled) before executing the STOP

instruction.

The CPU clock used when exiting stop mode by a peripheral interrupt or NMI is the same clock used

when the STOP instruction is executed.

Table 8.8 lists interrupts used to exit stop mode and usage conditions.

Note:

1. UART7 and UART8 are excluded.

Table 8.7 Pin State in Stop Mode

Pin Memory Expansion Mode/

Microprocessor Mode Single-chip Mode

Address bus, data bus,

CS0 to CS3, BC0 to BC3

The state immediately before entering

stop mode is held —

RD, WR, WR0 to WR3 High —

HLDA, BCLK High —

ALE High —

Ports The state immediately before entering stop mode is held

DA0, DA1 The state immediately before entering stop mode is held

CLKOUT When a low

speed clock is

selected

High

When f8 or f32

is selected

The state immediately before entering stop mode is held

XIN High-impedance

XOUT High

XCIN, XCOUT High-impedance

Table 8.8 Interrupts for Exiting Stop Mode and Usage Conditions

Interrupt Usage Condition

NMI

Low voltage detection interrupt

External interrupt INT6 to INT8 are available when intelligent I/O interrupt is used

Key input interrupt

Timer A interrupt

Timer B interrupt

Available when a timer counts an external pulse with a frequency of 100

Hz or less in event counter mode

Serial interface interrupt (1) Available when an external clock is used

I2C-bus line interrupt

CAN wake-up interrupt

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R32C/117 Group 8. Clock Generator

8.8 System Clock Protection

The system clock protection disables clock change when the PLL clock is selected as the base clock

source. This prevents the CPU clock from stopping due to a runaway program.

When the PM21 bit in the PM2 register is set to 1 (clock change disabled), the following bits cannot be

written to:

• Bits CM02 and CM05 in the CM0 register

• The CM10 bit in the CM1 register

• The CM20 bit in the CM2 register

• The PM27 bit in the PM2 register

To use the system clock protection, set the CM05 bit in the CM0 register to 0 (main clock oscillator

enabled) and the BCS bit in the CCR register to 0 (PLL clock selected as base clock source) before the

following procedure is done:

(1) Set the PRC1 bit in the PRCR register to 1 (write to the PM2 register enabled).

(2) Set the PM21 bit in the PM2 register to 1 (clock change disabled).

(3) Set the PRC1 bit in the PRCR register to 0 (write to the PM2 register disabled).

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R32C/117 Group 8. Clock Generator

8.9 Notes on Clock Generator

8.9.1 Sub Clock

8.9.1.1 Oscillator Constant Matching

The constant matching of the sub clock oscillator should be evaluated in both cases when the drive

strength is high and low.

Contact the oscillator manufacturer for details on the oscillation circuit constant matching.

8.9.2 Power Control

Do not switch the base clock source until the oscillation of the clock to be used has stabilized. However,

this does not apply to the on-chip oscillator since it starts running immediately after the CM31 bit in the

CM3 register is set to 1.

To switch the base clock source from the PLL clock to a low speed clock, use the MOV.L or OR.L

instruction to set the BCS bit in the CCR register to 1.

• Program example in assembly language

OR.L #80h, 0004h

• Program example in C language

asm("OR.L #80h, 0004h");

8.9.2.1 Stop Mode

• To exit stop mode using a reset, apply a low signal to the RESET pin until the main clock oscillation

stabilizes.

8.9.2.2 Suggestions for Power Saving

The following are suggestions to reduce power consumption when programming or designing systems.

• I/O pins:

If inputs are floating, both transistors may be conducting. Set unassigned pins to input mode and

connect each of them to VSS via a resistor, or set them to output mode and leave them open.

• A/D converter:

When not performing the A/D conversion, set the VCUT bit in the AD0CON1 register to 0 (VREF

disconnected). To perform the A/D conversion, set the VCUT bit to 1 (VREF connected) and wait at

least 1 µs before starting conversion.

• D/A converter:

When not performing the D/A conversion, set the DAiE bit in the DACON register (i = 0, 1) to 0

(output disabled) and the DAi register to 00h.

• Peripheral clock stop:

When entering wait mode, power consumption can be reduced by setting the CM02 bit in the CM0

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R32C/117 Group 9. Bus

9. Bus

This MCU has an internal bus and an external bus. The internal bus contains a fast bus (CPU bus) and a

slow bus (peripheral bus). Figure 9.1 shows a block diagram of the bus.

Figure 9.1 Bus Block Diagram

In memory expansion mode or microprocessor mode, some pins function as bus control pin to control the

address bus and the data bus. The bus control pins are as follows: A0 to A23, D0 to D31, CS0 to CS3,

WR0/WR, BC0, WR1/BC1, WR2/BC2, WR3/BC3, RD, BCLK, HLDA, HOLD, ALE, and RDY.

9.1 Bus Settings

The bus settings are controlled by the two lowest bits of the reset vector, the PBC register, registers EBC0

to EBC3, and CSOP0 to CSOP2.

Table 9.1 lists bus settings and their sources.

Table 9.1 Bus Settings and Sources

Bus Settings Sources

Internal SFR bus timing PBC register

External bus timing Registers EBC0 to EBC3

External data bus width PBC register, registers EBC0 to EBC3

External data bus width after reset Two lowest bits of the reset vector

Separate bus/multiplexed bus selection PBC register, registers EBC0 to EBC3

Pins outputting chip select signals Registers CSOP0 to CSOP2

Peripheral address busCPU address bus (26 bits)

CPU

ROM RAM

BIU

Peripherals

I/O

buffer

CPU data bus (64 bits) Peripheral data bus (16/32 bits)

External data bus

External address bus

Chip select

8/16/32 bits (1)

24 bits

Note:

1. A 32-bit data bus is available in the 144-pin package only. Only a 16-bit data bus is provided in the 100-pin package.

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R32C/117 Group 9. Bus

9.2 Peripheral Bus Timing Setting

The 16-/32-bit wide peripheral bus operates at a frequency up to 32 MHz (the theoretical value and the

maximum frequency of each product group are as defined by f(BCLK) in 28. “Electrical Characteristics”).

The timing adjustment and bus-width conversion with the faster, 64-bit wide CPU bus are controlled in the

bus interface unit (BIU).

Figure 9.2 shows the PBC register which determines the peripheral bus timing.

Figure 9.2 PBC Register

Symbol

PBC

Reset Value

0504h

FunctionBit Symbol Bit Name RW

Peripheral Bus Control Register (1, 2)

Should be written with 0

Notes:

1. Set the PRR register to AAh (write enabled) before rewriting this register.

2. Set this register only once after a reset. Do not rewrite this register after setting the CCR register.

3. If this bit is set to 1 when the all MPX bits in registers EBC0 to EBC3 are set to 1, ports P0, P1, and P4_0 to

P4_3 can be used as programmable I/O ports.

4. This bit should be the maximum bus width set in bits BW1 and BW0 in registers EBC0 to EBC3. The

functions of ports P1, P12, and P13 vary with this bit setting.

5. This bit setting is applicable only in the 144-pin package.

RWRead Timing Setting Bit

Select from the three options below

according to the peripheral bus clock

setting (bits PCD1 and PCD0 in the

CCR register).

When bits PCD1 and PCD0 are set

to:

1. 01b : 00100b

2. 10b : 01101b

3. 11b : 01111b

Reserved RW

RWWrite Timing Setting Bit

0: Separate bus in some spaces

1: Multiplexed bus in all spaces

External Bus Format Select

Bit (3)

External Bus Maximum

Width Setting Bit (4)

b15b14

00:8-bit width

0 1 : 16-bit width

1 0 : 32-bit width (5)

1 1 : Do not use this combination

Select from the three options below

according to the peripheral bus clock

setting (bits PCD1 and PCD0 in the

CCR register).

When bits PCD1 and PCD0 are set

to:

1. 01b : 00101b

2. 10b : 01010b

3. 11b : 01111b

000

b15 b8 b7 b0

PRD0

PRD1

PRD2

PRD3

PRD4

—

(b7-b5)

PWR0

PWR1

PWR2

PWR3

PWR4

EXMPX

EXBW0

EXBW1

Address

001Fh-001Eh

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R32C/117 Group 9. Bus

9.3 External Bus Setting

The 8-/16-/32-bit wide external bus operates at a frequency up to 32 MHz (the theoretical value and the

maximum frequency of each product group are as defined by f(BCLK) in 28. “Electrical Characteristics”).

The timing adjustment and bus-width conversion with the faster 64-bit wide CPU bus are controlled in the

bus interface unit (BIU).

9.3.1 External Address Space Setting

The internal address bus of the R32C/100 Series MCU consists of 26 address lines (A0 to A25). Since

A25 is sign extended to A26 to A31, the MCU has 64 MB of accessible space addresses from

00000000h to 01FFFFFFh and from FE000000h to FFFFFFFFh.

Up to 24 address lines from A0 to A23 can be used for external output. Decoded A18 to A25 function as

4 chip select signals (CS3 to CS0). If a 16 MB space is assigned to each chip select signal, up to 63.5

MB can be used as external address space. When the processor mode is changed from single-chip

mode to memory expansion mode, the address bus status is undefined until an external space is

accessed.

Chip select signals CS3 to CS0 share pins with A20 to A23, respectively. Other combinations of signal

and output port are also available as follows: signals CS0 to CS3 with ports P11_0 to P11_3, and

signals CS1 to CS3 with ports P5_4, P5_6, and P5_7.

In microprocessor mode, the CS0 signal is output from port P4_7 after a reset. The maximum space

per chip select signal is 8 MB since A23 is not available. Signals CS1 to CS3 are output only when

being set.

CSi (i = 0 to 3) is held low while accessing an external space i. It becomes high when accessing

another external space. Figure 9.3 shows output examples of address bus and chip select signals.

Set registers CSOP0 to CSOP2 to select a chip select signal to be used and its output pin. Set registers

CB01, CB12, and CB23 to set the address space for each chip select signal.

Figures 9.4 to 9.6 show registers CSOP0 to CSOP2. Figures 9.7, 9.8, and 9.9 show registers CB01,

CB12, and CB23, respectively. Figures 9.10 and 9.11 show the chip select space.

A chip select signal should not be set for more than two output pins in registers CSOP0 to CSOP2.

Registers CB01, CB12, and CB23 should be set to meet the conditions below:

• In memory expansion mode

• In microprocessor mode

0080000h CB23 218

CB12 218

CB01 218

3DC0000h

0080000h CB23 218

CB12 218

CB01 218

3FC0000h

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R32C/117 Group 9. Bus

Figure 9.3 Address Bus and Chip Select Signal Output Patterns (in separate bus format)

Pattern 1. Both the address bus and chip select signal are

changed after accessing an external space.

Pattern 2. Only the chip select signal is changed after

accessing an external space (the address bus is

not changed).

When the CSy space is accessed after accessing the

CSx space, both the address bus and the chip select

signal are changed.

Data bus

Address bus

Chip select CSx

Chip select CSy

Data

Address

Data

Accessing the

CSx space

Accessing the

CSy space

When an internal space is accessed after accessing the

CSx space, only the chip select signal is changed.

Data bus

Address bus

Chip select CSx

Data

Address

Pattern 3. Only the address bus is changed after accessing an

external space (the chip select signal is not

changed).

When the same CSx space is accessed after accessing

the CSx space, only the address bus is changed.

Data bus

Address bus

Chip select CSx

Data

Address

Data

Accessing the

CSx space

x = 0 to 3

y = 0 to 3, other than x

x = 0 to 3

Accessing the

same CSx space

Pattern 4. Neither the address bus nor the chip select signal is

changed after accessing an external space

When no space is accessed after accessing the CSx

space, (and no instruction prefetching is generated),

neither the address bus nor the chip select signal is

changed.

Data bus

Address bus

Chip select CSx

Data

Accessing the

CSx space

Address

x = 0 to 3

No access

Note:

1. The patterns above show combinations of an address bus and a chip select signal in two sequential cycles. A

chip select signal may be extended to two or more bus cycles according to the combination.

Accessing the

CSx space

Accessing an

internal space

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R32C/117 Group 9. Bus

Figure 9.4 CSOP0 Register

Figure 9.5 CSOP1 Register

b7 b6 b5 b4 b1b2b3 Symbol

CSOP0

Address

40054h

Reset Value

1000 XXXXb

FunctionBit Symbol Bit Name RW

—

Chip Select Output Pin Setting Register 0 (1)

No register bits; should be written with 0 and read as undefined

value

Notes:

1. Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting this register.

2. The P4_7B bit should not be set to 0 when starting an operation in microprocessor mode.

0: Output A20 from P4_4

1: Output CS3 from P4_4

P4_4 Bus Function Setting

Bit

0: Output A21 from P4_5

1: Output CS2 from P4_5

P4_5 Bus Function Setting

Bit

0: Output A22 from P4_6

1: Output CS1 from P4_6

P4_6 Bus Function Setting

Bit

0: Output A23 from P4_7 (2)

1: Output CS0 from P4_7

P4_7 Bus Function Setting

Bit

—

(b3-b0)

P4_4B

P4_5B

P4_6B

P4_7B

b7 b6 b5 b4 b1b2b3 Symbol

CSOP1

Address

40055h

Reset Value

01X0 XXXXb

FunctionBit Symbol Bit Name RW

—

Chip Select Output Pin Setting Register 1 (1)

0: Output HLDA from P5_4

1: Output CS1 from P5_4

P5_4 Bus Function Setting

Bit

0: Output ALE from P5_6

1: Output CS2 from P5_6

P5_6 Bus Function Setting

Bit

0: RDY input pin

1: Output CS3 from P5_7

P5_7 Bus Function Setting

Bit

Note:

1. Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting this register.

—

No register bit; should be written with 0 and read as undefined

value

—

(b3-b0)

P5_4B

—

(b5)

P5_6B

P5_7B

No register bits; should be written with 0 and read as undefined

value

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R32C/117 Group 9. Bus

Figure 9.6 CSOP2 Register

Figure 9.7 CB01 Register

b7 b6 b5 b4 b1b2b3 Symbol

CSOP2

Address

40056h

Reset Value

XXXX 0000b

FunctionBit Symbol Bit Name RW

—

Chip Select Output Pin Setting Register 2 (1)

No register bits; should be written with 0 and read as undefined

value

0: Use P11_0 for a peripheral function

1: Output CS0 from P11_0

P11_0 Bus Function

Setting Bit

Notes:

1. Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting this register.

2. WR2 is output when the PM02 bit in the PM0 register is 1 (RD/WR0/WR1/WR2/WR3) and bits EXBW1 and

EXBW0 in the PBC register are 10b (32-bit width as the maximum width of external bus); otherwise, CS3 is

output.

0: Use P11_1 for a peripheral function

1: Output CS1 from P11_1

P11_1 Bus Function

Setting Bit

0: Use P11_2 for a peripheral function

1: Output CS2 from P11_2

P11_2 Bus Function

Setting Bit

0: Use P11_3 for a peripheral function

1: Output CS3 or WR2 from P11_3 (2)

P11_3 Bus Function

Setting Bit

P11_0B

P11_1B

P11_2B

P11_3B

—

(b7-b4)

b7 Symbol

CB01

Address

001Ah

Reset Value

00h

Setting RangeFunction RW

Chip Selects 0 and 1 Boundary Setting Register (1)

Notes:

1. Set the PRR register to AAh (write enabled) before rewriting this register.

2. The setting value should be equal to or greater than that of the CB12 register.

02h to F8h (2) in memory

expansion mode

02h to FFh (2) in

microprocessor mode

Set this register to the value from A25 to A18 of the

start address in the CS0 space.

The immediately preceding address mentioned

above and lower is designated for CS1 space

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R32C/117 Group 9. Bus

Figure 9.8 CB12 Register

Figure 9.9 CB23 Register

b7 Symbol

CB12

Address

0016h

Reset Value

00h

Setting RangeFunction RW

Chip Selects 1 and 2 Boundary Setting Register (1)

Notes:

1. Set the PRR register to AAh (write enabled) before rewriting this register.

2. The setting value should be equal to or greater than that of the CB23 register and should be equal to or less

than that of the CB01 register.

02h to F8h (2) in memory

expansion mode

02h to FFh (2) in

microprocessor mode

Set this register to the value from A25 to A18 of the

start address in the CS1 space.

The immediately preceding address mentioned

above and lower is designated for CS2 space

b7 Symbol

CB23

Address

0012h

Reset Value

00h

Setting RangeFunction RW

Chip Selects 2 and 3 Boundary Setting Register (1)

Notes:

1. Set the PRR register to AAh (write enabled) before rewriting this register.

2. The setting value should be equal to or less than that of the CB12 register.

02h to F8h (2) in memory

expansion mode

02h to FFh (2) in

microprocessor mode

Set this register to the value from A25 to A18 of the

start address in the CS2 space.

The immediately preceding address mentioned

above and lower is designated for CS3 space

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R32C/117 Group 9. Bus

Figure 9.10 Chip Select Spaces in Memory Expansion Mode

Internal

space

Internal

space

00000000h

FFFFFFFFh

00080000h

FFE00000h

FE000000h

02000000h

CS3 space

CS2 space

CS1 space

CS0 space

Internal

space

Internal

space

CS3 space

CS2 space

Not

available

CS1 space

CS0 space

Not

available

Internal

space

Internal

space

CS3 space

CS2 space

Not

available

CS1 space

CS0 space

CB12

CB23

CB01

Internal

space

Internal

space

CS3 space

CS2 space

Not

available

CS1 space

CS0 space

Internal

space

Internal

space

CS3 space

(1)

CS2 space

(1)

CS1 space

(1)

CS0 space

(1)

Not

available

Setting value

of the CBxx

Address

02h

80h

F8h

Note:

1. Each CS space can be up to 16 MB when the CS signal is not output from port P4. If a space is

oversized, the same data is shown every 16 MB. When the CS signal is output from port P4, the maximum

valid size is reduced depending on the number of address lines reduced.

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R32C/117 Group 9. Bus

Figure 9.11 Chip Select Spaces in Microprocessor Mode

9.3.2 External Data Bus Width Setting

The external data bus width is selectable among 8 bits, 16 bits, and 32 bits. The bus width of each

space is selected by setting bits BW1 and BW0 in registers EBC0 to EBC3. The maximum bus width for

all spaces is selected by setting bits EXBW1 and EXBW0 in the PBC register. The bus width specified

in bits EXBW1 and EXBW0 should be equal to or greater than the value specified in bits BW1 and

BW0.

When an accessed space has a bus width less than that specified in bits EXBW1 and EXBW0, an

undefined value is output from the unused data output pins.

Figure 9.12 shows registers EBC0 to EBC3.

Internal

space

00000000h

FFFFFFFFh

00080000h

FE000000h

02000000h

CS3 space

CS2 space

CS1 space

CS0 space

Internal

space

CS3 space

CS2 space

Not

available

CS1 space

CS0 space

Not

available

Internal

space

CS3 space

CS2 space

Not

available

CS1 space

CS0 space

CB12

CB23

CB01

Internal

space

CS3 space

CS2 space

Not

available

CS1 space

CS0 space

Internal

space

CS3 space

(1)

CS2 space

(1)

CS1 space

(1)

CS0 space

(1)

Not

available

Setting value

of the CBxx

Address

02h

80h

(FFh)

Note:

1. Each CS space can be up to 8 MB when the CS signal (except for the CS0 signal) is not output from port

P4. If a space is oversized, the same data is shown every 8 MB. When the CS signal (except for the CS0

signal) is output from port P4, the maximum valid size is reduced depending on the number of address lines

reduced.

R01UH0211EJ0120 Rev.1.20 Page 122 of 604

Feb 18, 2013

R32C/117 Group 9. Bus

Figure 9.12 Registers EBC0 to EBC3

Symbol

EBC0, EBC1

EBC2, EBC3

Address

001Dh-001Ch, 0019h-0018h

0015h-0014h, 0011h-0010h

Reset Value

0000h

FunctionBit Symbol Bit Name RW

External Bus Control Register i (i = 0 to 3) (1)

Notes:

1. Set the PRR register to AAh (write enabled) before rewriting this register.

2. Refer to 9.3.5. “External Bus Timing” for the relation between register settings and practical timing.

3. The maximum value set here should be applied to bits EXBW1 and EXBW0 in the PBC register.

4. This bit setting is applicable only in the 144-pin package.

Address Setup Cycles

Before Read Setting Bit (2)

b1 b0

00:sur = 0

01:

sur = 1

10:

sur = 2

11:

sur = 3

Read Pulse Width Setting

Bit (2)

b3 b2

00:wr = 1

01:

wr = 2

10:

wr = 3

11:

wr = 4

Address Setup Cycles

Before Write Setting Bit (2)

b9 b8

00:suw = 0

01:

suw = 1

10:

suw = 2

11:

suw = 3

Write Pulse Width Setting

Bit (2)

b11b10

00:ww = 1

01:

ww = 2

10:

ww = 3

11:

ww = 4

0: Separate bus

1: Multiplexed bus

External Bus Format Select

Bit

External Bus Width Setting

Bit (3)

b15b14

00:8-bit width

0 1 : 16-bit width

1 0 : 32-bit width (4)

1 1 : Do not use this combination

0: Ignore RDY

1: Use RDY

RDY Monitor Bit

Multiplied Cycle Setting Bit

(2)

b7 b6

00:mpy = 1

01:

mpy = 2

10:

mpy = 3

11:

mpy = 4

1 1

b15 b8 b7

ESUR0

ESUR1

EWR0

EWR1

RDY

MPY0

MPY1

ESUW0

ESUW1

EWW0

EWW1

MPX

BW0

BW1

—

(b4) Reserved Should be written with 1

—

(b12) Reserved Should be written with 1

R01UH0211EJ0120 Rev.1.20 Page 123 of 604

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R32C/117 Group 9. Bus

9.3.3 Separate Bus/Multiplexed Bus Selection

The bus format is selectable between separate bus format and multiplexed bus format. The bus format

for each space is selected by setting the MPX bit in registers EBC0 to EBC3. To select the multiplexed

bus format for all spaces, the EXPMX bit in the PBC register should be set to 1 (multiplexed bus in all

spaces). In this case, ports P0, P1, and P4_0 to P4_3 can be used as programmable I/O ports.

(1) Separate Bus

In this bus format, the data bus and address bus have their own I/O pins.

To select separate bus mode, the MPX bit in registers EBC0 to EBC3 should be set to 0. The data bus

width is selectable among 8 bits, 16 bits, and 32 bits by setting bits BW1 and BW0 in registers EBC0

to EBC3.

When bits EXBW1 and EXBW0 in the PBC register are 00b (8-bit width), port P0 is the data bus, and

ports P1, P12, and P13 are programmable I/O ports.

When bits EXBW1 and EXBW0 are 01b (16-bit width), ports P0 and P1 are data buses, and Ports P12

and P13 are programmable I/O ports. Note that port P1 (D8 to D15) becomes undefined if the MCU

accesses an space where bits BW1 and BW0 are to 00b (8-bit width).

When bits EXBW1 and EXBW0 are 10b (32-bit width), ports P0, P1, P12, and P13 are data lines. Note

that ports P1, P12, and P13 (D8 to D31) become undefined if the MCU accesses an space where bits

BW1 and BW0 are 00b (8-bit width), and ports P12 and P13 (D16 to D31) become undefined if the

MCU accesses an space where bits BW1 and BW0 are 01b (16-bit width).

(2) Multiplexed Bus

In this bus format, the data bus and address bus are time division multiplexed.

To select multiplexed bus mode, the MPX bit in registers EBC0 to EBC3 should be set to 1.

When bits BW1 and BW0 in registers EBC0 to EBC3 are 00b (8-bit width), D0 to D7 are multiplexed

with A0 to A7. When bits BW1 and BW0 are 01b (16-bit width) or 10b (32-bit width), D0 to D15 are

multiplexed with BC0, A1/BC2, and A2 to A15.

In microprocessor mode, an operation is started in separate bus format after a reset. Therefore the

multiplexed bus format can only be used for CS1 to CS3 spaces and cannot be used for the CS0

space.

Table 9.2 lists pin functions for each processor mode and Table 9.3 lists pin functions for each bus

format.

R01UH0211EJ0120 Rev.1.20 Page 124 of 604

Feb 18, 2013

R32C/117 Group 9. Bus

Notes:

1. Ports P11 to P15 are available only in the 144-pin package.

2. An undefined value is output.

Table 9.2 Processor Mode and Pin Functions (1)

Process

or Mode

Single-

chip Mode Microprocessor Mode/Memory Expansion Mode Memory Expansion Mode

Bus

format —Separate bus only

(EXMPX = 0)

Separate bus and multiplexed bus

(mixed) (EXMPX = 0)

Multiplexed bus only

(EXMPX = 1)

Data bus

width — 8 bits only 8/16 bits

(mixed)

8/16/32 bits

(mixed) 8 bits only 8/16 bits

(mixed)

8/16/32 bits

(mixed) 8 bits only 8/16 bits

(mixed)

8/16/32 bits

(mixed)

P0_0 to

P0_7 I/O ports D0 to D7 I/O ports

P1_0 to

P1_7 I/O ports I/O ports D8 to D15 I/O ports D8 to D15 I/O ports

P2_0 I/O port A0 A0 or BC0 A0 or

A0/D0

A0, A0/D0, BC0, or

BC0/D0 A0/D0 A0/D0 or BC0/D0

P2_1 I/O port A1 A1 or BC2 A1 or A1/D1

A1,A1/

D1,BC2, or

BC2/D1

A1/D1 A1/D1 or

BC2/D1

P2_2 to

P2_7 I/O ports A2 to A7 A2 to A7 or A2/D2 to A7/D7 A2/D2 to A7/D7

P3_0 to

P3_7 I/O ports A8 to A15 A8 to A15 A8 to A15 or

A8/D8 to A15/D15 A8 to A15 A8/D8 to A15/D15

P4_0 to

P4_3 I/O ports A16 to A19 I/O ports

P4_4 I/O port A20 or CS3

P4_5 I/O port A21 or CS2

P4_6 I/O port A22 or CS1

P4_7 I/O port A23 or CS0

P5_0 I/O port WR or WR0

P5_1 I/O port Undefined

(2) BC1 or WR1 Undefined

(2) BC1 or WR1

P5_2 I/O port RD

P5_3 I/O port BCLK

P5_4 I/O port HLDA or CS1

P5_5 I/O port HOLD

P5_6 I/O port ALE or CS2 Set to ALE

P5_7 I/O port RDY or CS3

P11_0 to

P11_2 I/O ports CS0 to CS2 or I/O ports

P11_3 I/O port CS3 or I/O port CS3 or

WR2 CS3 or I/O port CS3 to WR2 CS3 or I/O port CS3 or

WR2

P11_4 I/O port I/O port BC3 or

WR3 I/O port BC3 to WR3 I/O port BC3 or

WR3

P12_0 to

P12_7 I/O ports I/O ports D16 to D23 I/O ports D16 to D23 I/O ports D16 to D23

P13_0 to

P13_7 I/O ports I/O ports D24 to D31 I/O ports D24 to D31 I/O ports D24 to D31

R01UH0211EJ0120 Rev.1.20 Page 125 of 604

Feb 18, 2013

R32C/117 Group 9. Bus

Notes:

1. Ports P11 to P15 are available only in the 144-pin package.

2. An undefined value is output.

Table 9.3 Bus Format and Pin Functions (in Microprocessor Mode/Memory Expansion Mode) (1)

Bus Format Separate Bus Multiplexed Bus

MPX bit 0 1

Bus width 8 bits 16 bits 32 bits 8 bits 16 bits 32 bits

Bits BW1 to

BW0 00b 01b 10b 00b 01b 10b

P0_0 to P0_7 D0 to D7 I/O ports

P1_0 to P1_7 I/O ports D8 to D15 I/O ports

P2_0 A0 BC0 A0/D0 BC0/D0

P2_1 A1 BC2 A1/D1 BC2/D1

P2_2 to P2_7 A2 to A7 A2/D2 to A7/D7

P3_0 to P3_7 A8 to A15 A8/D8 to A15/D15

P4_0 to P4_3 A16 to A19 A16 to A19 or I/O ports

P4_4 A20 or CS3

P4_5 A21 or CS2

P4_6 A22 or CS1

P4_7 A23 or CS0 (CS0 fixed in microprocessor mode)

P5_0 WR or WR0

P5_1 Undefined (2) BC1 or WR1 Undefined (2) BC1 or WR1

P5_2 RD

P5_3 BCLK

P5_4 HLDA or CS1

P5_5 HOLD

P5_6 ALE or CS2 Set to ALE

P5_7 RDY or CS3

P11_0 to

P11_2 CS0 to CS2 or I/O ports

P11_3 CS3 or I/O port CS3 or WR2 CS3 or I/O port CS3 or WR2

P11_4 I/O port BC3 or WR3 I/O port BC3 or WR3

P12_0 to

P12_7 I/O ports D16 to D23 I/O ports D16 to D23

P13_0 to

P13_7 I/O ports D24 to D31 I/O ports D24 to D31

R01UH0211EJ0120 Rev.1.20 Page 126 of 604

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R32C/117 Group 9. Bus

9.3.4 Read and Write Signals

When the data bus is 16 or 32 bits, set the PM02 bit in the PM0 register to select a combination of RD,

WR, BC0, BC1, BC2, and BC3, or RD, WR0, WR1, WR2, and WR3 as read or write signals.

When bits EXBW1 and EXBW0 in the PBC register are 00b (8-bit width), the PM02 bit should be set to

0 (RD/WR/BC0/BC1/BC2/BC3). When accessing an 8-bit space while bits EXBW1 and EXBW0 are

01b (16-bit width) or 10b (32-bit width), the combination of RD, WR, BC0, BC1, BC2, and BC3 is

selected irrespective of the PM02 bit setting.

Tables 9.4 and 9.5 list the operation of each signal.

The read and write signals after a reset are in the following combination: RD, WR, BC0, BC1, BC2, and

BC3. To change to the combination of RD, WR0, WR1, WR2, and WR3, set the PM02 bit before writing

data to external memory.

Notes:

1. Signals WR2 and WR3 are available only in the 144-pin package.

2. Signals for the 32-bit data bus width can only be set in the 144-pin package.

Table 9.4 RD, WR0, WR1, WR2, and WR3 Signals (1)

Data Bus

Width RD WR0 WR1 WR2 WR3 External Data Bus Status

32 bits (2)

L H H H H Read 4-byte data

H L H H H Write 1-byte data to address 4n+0

H H L H H Write 1-byte data to address 4n+1

H H H L H Write 1-byte data to address 4n+2

H H H H L Write 1-byte data to address 4n+3

H L L H H Write 2-byte data to addresses 4n+0 to 4n+1

H H L L H Write 2-byte data to addresses 4n+1 to 4n+2

H H H L L Write 2-byte data to addresses 4n+2 to 4n+3

H L L L H Write 3-byte data to addresses 4n+0 to 4n+2

H H L L L Write 3-byte data to addresses 4n+1 to 4n+3

H L L L L Write 4-byte data to addresses 4n+0 to 4n+3

16 bits

L H H H/L (A1) — Read 2-byte data

H L H H/L (A1) — Write 1-byte data to even address

H H L H/L (A1) — Write 1-byte data to odd address

H L L H/L (A1) — Write 2-byte data to both even and odd addresses

8 bits LH (

WR) — H/L (A1) — Read 1-byte data

HL (

WR) — H/L (A1) — Write 1-byte data

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R32C/117 Group 9. Bus

Notes:

1. Signals BC2 and BC3 are available only in the 144-pin package.

2. Signals for the 32-bit data bus width can only be set in the 144-pin package.

Table 9.5 RD, WR, BC0, BC1, BC2, and BC3 Signals(1)

Data Bus

Width RD WR BC0 BC1 BC2 BC3 External Data Bus Status

32 bits (2)

L H L L L L Read 4-byte data

H L L H H H Write 1-byte data to address 4n+0

H L H L H H Write 1-byte data to address 4n+1

H L H H L H Write 1-byte data to address 4n+2

H L H H H L Write 1-byte data to address 4n+3

H L L L H H Write 2-byte data to addresses 4n+0 to 4n+1

H L H L L H Write 2-byte data to addresses 4n+1 to 4n+2

H L H H L L Write 2-byte data to addresses 4n+2 to 4n+3

H L L L L H Write 3-byte data to addresses 4n+0 to 4n+2

H L H L L L Write 3-byte data to addresses 4n+1 to 4n+3

H L L L L L Write 4-byte data to addresses 4n+0 to 4n+3

16 bits

L H L L H/L (A1) — Read 2-byte data

H L L H H/L (A1) — Write 1-byte data to even address

H L H L H/L (A1) — Write 1-byte data to odd address

H L L L H/L (A1) — Write 2-byte data to both even and odd addresses

8 bits L H H/L (A0) — H/L (A1) — Read 1-byte data

H L H/L (A0) — H/L (A1) — Write 1-byte data

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R32C/117 Group 9. Bus

9.3.5 External Bus Timing

The external bus timing is configured by setting registers EBC0 to EBC3. The reference clock is the

base clock selected by setting bits BCD1 and BCD0 in the CCR register.

Table 9.6 lists the bit setting of MPY1, MPY0, ESUR1, and ESUR0 and the Tsu(A-R) (address setup

cycles before read), Table 9.7 lists the bit setting of MPY1, MPY0, EWR1, and EWR0 and the Tw(R)

(read pulse width), Table 9.8 lists the bit setting of MPY1, MPY0, ESUW1, and ESUW0 and the Tsu(A-

W) (address setup cycles before write), and Table 9.9 lists the bit setting of MPY1, MPY0, EWW1, and

EWW0 and the Tw(W) (write pulse width).

Note:

1. Do not set this value.

Table 9.6 Tsu(A-R) and Bit Settings: MPY1, MPY0, ESUR1, and ESUR0 (unit: cycles)

ESUR1 and

ESUR0

Bit Settings

Separate Bus Multiplexed Bus

MPY1 and MPY0 bit settings MPY1 and MPY0 bit settings

00b 01b 10b 11b 00b 01b 10b 11b

mpy = 1 mpy = 2 mpy = 3 mpy = 4 mpy = 1 mpy = 2 mpy = 3 mpy = 4

00b sur = 0 0.50.50.50.51111

01b sur = 1 1.52.53.54.52345

10b sur = 2 2.54.56.58.53579

11b sur = 3 3.5 6.5 9.5 12.5 4 7 10 13

Formula Tsu(A-R) = sur × mpy + 0.5 Tsu(A-R) = sur × mpy + 1

Table 9.7 Tw(R) and Bit Settings: MPY1, MPY0, EWR1, and EWR0 (unit: cycles)

EWR1 and EWR0

Bit Settings

Separate Bus Multiplexed Bus

MPY1 and MPY0 bit setting MPY1 and MPY0 bit setting

00b 01b 10b 11b 00b 01b 10b 11b

mpy = 1 mpy = 2 mpy = 3 mpy = 4 mpy = 1 mpy = 2 mpy = 3 mpy = 4

00b wr = 1 1.5 2.5 3.5 4.5 0.5 (1) 1.5 2.5 3.5

01b wr = 2 2.54.56.58.51.53.55.57.5

10b wr = 3 3.5 6.5 9.5 12.5 2.5 5.5 8.5 11.5

11b wr = 4 4.5 8.5 12.5 16.5 3.5 7.5 11.5 15.5

Formula Tw(R) = wr × mpy + 0.5 Tw(R) = wr × mpy - 0.5

R01UH0211EJ0120 Rev.1.20 Page 129 of 604

Feb 18, 2013

R32C/117 Group 9. Bus

Note:

1. Do not set this value.

Figure 9.13 and 9.14 show examples of external bus timing in separate bus format (the MPX bit is set to

0) and in multiplexed bus format (the MPX bit is set to 1), respectively.

Note that the actual bus cycles are adjusted to be the integral multiple of peripheral bus clock as

follows:

• Peripheral bus clock divided by 2: If the calculation result is odd, an idle cycle is inserted so that the

bus cycles becomes even.

• Peripheral bus clock divided by 3: If the calculation result is not a multiple of three, (an) idle

cycle(s) is/are inserted so that the bus cycles becomes a multiple of three.

• Peripheral bus clock divided by 4: If the calculation result is not a multiple of four, (an) idle cycle(s)

is/are inserted so that the bus cycles becomes a multiple of four.

Table 9.8 Tsu(A-W) and the Bit Settings: MPY1, MPY0, ESUW1, and ESUW0 (unit: cycles)

ESUW1 and

ESUW0

Bit Settings

MPY1 and MPY0 Bit Settings

00b 01b 10b 11b

mpy = 1 mpy = 2 mpy = 3 mpy = 4

00b suw = 0 1111

01b suw = 1 2345

10b suw = 2 3579

11b suw = 3 4 7 10 13

Formula Tsu(A-W) = suw × mpy + 1

Table 9.9 Tw(W) and the Bit Settings: MPY1, MPY0, EWW1, and EWW0 (unit: cycles)

EWW1 and

EWW0

Bit Settings

MPY1 and MPY0 Bit Settings

00b 01b 10b 11b

mpy = 1 mpy = 2 mpy = 3 mpy = 4

00b ww = 1 0.5 (1) 1.5 2.5 3.5

01b ww = 2 1.5 3.5 5.5 7.5

10b ww = 3 2.5 5.5 8.5 11.5

11b ww = 4 3.5 7.5 11.5 15.5

Formula Tw(W) = ww × mpy - 0.5

R01UH0211EJ0120 Rev.1.20 Page 130 of 604

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R32C/117 Group 9. Bus

Figure 9.13 External Bus Timing in Separate Bus Format (i = 0 to 3)

Base clock

(internal signal)

CS, BC0 to BC3

Address

ReadData Write

Bus cycle

(A) When the EBCi register is XX01 0100 0001 0000b

Data (Write)

Bus cycle

Base clock

(internal signal)

CS, BC0 to BC3

Address

ReadData Write

Bus cycle

(B) When the EBCi register is XX01 1001 0001 0101b

Bus cycle

Base clock

(internal signal)

CS, BC0 to BC3

Address

Data (Read)

WR, WR0 to WR3

Bus cycle

WR, WR0 to WR3

R01UH0211EJ0120 Rev.1.20 Page 131 of 604

Feb 18, 2013

R32C/117 Group 9. Bus

Figure 9.14 External Bus Timing in Multiplexed Bus Format (i = 0 to 3)

Address Data

Address

Base clock

(internal signal)

CS, BC0 to BC3

Address / Data

Read

ALE

Bus cycle

(A) When the EBCi register is XX11 0100 0001 0100b

Address Write

Bus cycle

WR, WR0 to WR3

Base clock

(internal signal)

CS, BC0 to BC3

ALE

(B) When the EBCi register is XX11 1010 0001 1010b

WR, WR0 to WR3

Address

Base clock

(internal signal)

CS, BC0 to BC3

Address / Data (Read)

Data

WR, WR0 to WR3

Bus cycle

Address / Data (Write)

ALE

Address / Data (Read)

Address / Data (Write) Data

Address Data

Bus cycle

Address

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R32C/117 Group 9. Bus

9.3.6 ALE Signal

The ALE signal latches an address of the multiplexed bus. The address should be latched on the falling

edge of the ALE signal. This signal is output to internal space or external space.

Figure 9.15 ALE Signal and Address Bus/Data Bus

The ALE signal becomes high when a bus cycle is started and changes to low at 1/2 base clock before

RD or WR becomes low.

(A) 8-bit data bus

ALE

A0/D0 to A7/D7 Address Data (1)

A8 to A15

A16 to A19 Address (3)

ALE

A0/D0 to A15/D15 Address Data (1)

A16 to A19 Address (3)

Notes:

1. These pins are high-impedance when read.

2. An undefined value is output.

3. When these ports are set as I/O ports,

addresses are not output.

A20/CS3 to

A23/CS0 Address or CS

A20/CS3 to

A23/CS0 Address or CS

(B) 16-bit data bus

ALE

A0/D0 to A15/D15 Address Data (1)

A16 to A19 Address (3)

A20/CS3 to

A23/CS0 Address or CS

D16 to D31 Data (1)

Address Undefined (2)

R01UH0211EJ0120 Rev.1.20 Page 133 of 604

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R32C/117 Group 9. Bus

9.3.7 RDY Signal

The RDY signal facilitates access to external devices requiring longer access time. It is used when

accessing an external device with a lower access rate than the timing set in registers EBC0 to EBC3, or

when accessing multiple devices with different access timing in a CS space.

When the RDY bit in registers EBC0 to EBC3 is set to 1 (use RDY), the RDY pin is sampled on the

every mpyth falling edge of the base clock. If the RDY pin is held low when sampled, wait states are

inserted into the bus cycle. The sampling continues until the RDY pin is held high so that the bus cycle

starts running again.

Since the base clock is not output to external pins, drive the RDY signal low when the RD, WR, and

WR0 to WR3 signals are held in a low level, and drive the RDY signal high synchronizing the rise of the

BCLK signal.

Figure 9.16 shows an example of RDY signal generator and Table 9.10 lists setting conditions of

registers EBC0 to EBC3 to use this circuit. Figure 9.17 shows examples of bus cycle that is extended

by the RDY signal.

Figure 9.16 RDY Signal Generation Circuitry

BCLK

RDY

RCO

ENT

ENP

CLR

BCLK

RD, WR

RCO

FCounter

RDY

74AC08

74AC32

74AC74 74AC74

74AC32

74AC04

74AC08

74AC74

74AC163

Bus cycle

R01UH0211EJ0120 Rev.1.20 Page 134 of 604

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R32C/117 Group 9. Bus

X: Given value

Table 9.10 EBCi Register Setting Conditions when Using the Circuit in Figure 9.16 (i = 0 to 3)

Peripheral Bus Clock

Frequency Setting Condition Setting Example

BCLK = 1/2 base clock mpy = 3

In separate bus format

RD pulse width 9.5

WR pulse width 11.5

RD/WR high level width 2.5

In multiplexed bus format

RD pulse width 11.5

WR pulse width 11.5

In separate bus format

EBCi = XX01 1101 1011 1001b

etc.

In multiplexed bus format

EBCi = XX11 1101 1011 1101b

etc.

BCLK = 1/3 base clock mpy = 3

In separate bus format

RD pulse width 12.5

WR pulse width 11.5

RD/WR high level width 3.5

In multiplexed bus format

RD pulse width 11.5

WR pulse width 11.5

In separate bus format

EBCi = XX01 1101 1011 1101b

etc.

In multiplexed bus format

EBCi = XX11 1101 1011 1101b

etc.

BCLK = 1/4 base clock mpy = 4

In separate bus format

RD pulse width 20.5

WR pulse width 19.5

RD/WR high level width 4.5

In multiplexed bus format

RD pulse width 19.5

WR pulse width 19.5

In separate bus format

Not available

In multiplexed bus format

Not available

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R32C/117 Group 9. Bus

Figure 9.17 An Example of Bus Cycle Extended by RDY Signal (f(BCLK) = 1/2 f(Base)) (i = 0 to 3)

CS, BC0 to BC3

Address

Data (Read)

Data (Write)

Bus cycle = 17 + 3

(A) In separate bus format EBCi register = XX01 1101 1011 1101b (X: given value)

RDY

Bus cycle is completed here when RDY is not used.

: Signal wave when RDY is not used

CS, BC0 to BC3

(B) In multiplexed bus format EBCi register = XX11 1101 1011 1101b (X: given value)

AddressAddress / Data (Read)

Data

WR, WR0 to WR3

AddressAddress / Data (Write)

ALE

Data

RDY

Base clock

Sampling every 3 clocks (mpy = 3)

Base clock

Sampling every 3 clocks (mpy = 3)

Clock enable

(Internal signal)

Clock enable

(Internal signal)

WR, WR0 to WR3

Bus cycle = 17 + 3

Bus cycle is completed here when RDY is not used.

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R32C/117 Group 9. Bus

9.3.8 HOLD Signal

The HOLD signal is used when an external bus master requests the external bus from the CPU. When

the external bus master drives the HOLD pin low, the CPU outputs a low signal from the HLDA pin after

the ongoing bus access is completed. Then the CPU grants the external bus to the external bus master.

While the HOLD pin is held low, the CPU does not start the next bus cycle.

To hand over the external bus to the CPU, the external bus master should verify the HLDA pin is held

low, and then drive the HOLD pin high.

Table 9.11 lists the MCU state in a hold state.

The bus is used in the following priority order: External bus master, DMAC, and CPU.

9.3.9 BCLK Output

The BCLK, which has the same frequency as peripheral bus clock, is a divided clock derived from the

PLL clock. In memory expansion mode or microprocessor mode, BCLK is output from port P5_3 when

the PM07 bit in the PM0 register is set to 0 (output BCLK) and bits CM01 and CM00 in the CM0 register

are set to 00b (I/O port P5_3). In single-chip mode, BCLK cannot be output. Refer to 8. “Clock

Generator” for details.

9.4 External Bus State when Accessing Internal Space

Table 9.12 lists the external bus state when accessing an internal space.

Table 9.11 MCU State in Hold State

Item State

Oscillation On

Address bus, data bus, CS0 to CS3, BC0 to BC3 High-impedance

RD, WR, WR0 to WR3 High-impedance

Programmable I/O port The state when HOLD was received is held

HLDA pin Low is output

Internal peripheral circuit On (excluding the watchdog timer)

ALE pin Low is output

Table 9.12 External Bus State when Accessing Internal Space

Pin Pin State when Accessing SFR Pin State when Accessing Internal

Memory

Address bus Address is output The address of an SFR or external

space last accessed is held

Data bus Read cycle High-impedance High-impedance

Write cycle Data is output Undefined

CS0 to CS3 High is output High is output

BC0 to BC3 BC0 to BC3 are output The address of SFR or external space

last accessed is held

RD, WR, WR0 to WR3 RD, WR, WR0 to WR3 are output High is output

ALE The ALE signal is output The ALE signal is output

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R32C/117 Group 9. Bus

9.5 Notes on Bus

9.5.1 Notes on Designing a System

When a flash memory rewrite is performed in CPU rewrite mode using memory expansion mode, the

use of CS0 space and CS3 space has the following restrictions:

• If the FEBC0 and/or FEBC3 registers are set in CPU rewrite mode, the bus timing for the

corresponding space changes. This may cause external devices to become inaccessible

depending on the register settings.

Devices required to be accessed in CPU rewrite mode should be allocated in CS1 space and/or CS2

space.

9.5.2 Notes on Register Settings

9.5.2.1 Chip Select Boundary Select Registers

When not using memory expansion mode, do not change values after a reset for registers CB01,

CB12, and CB23.

When using memory expansion mode, set all of these registers to a value within the specified range

whether or not each chip select space is used.

9.5.2.2 External Bus Control Registers

Registers EBC0 and EBC3 share respective addresses with registers FEBC0 and FEBC3. If the

FEBC0 and/or FEBC3 registers are set while the flash memory is being rewritten, set the EBC0 and/

or EBC3 registers again after rewriting the flash memory.

• If the FEBC0 and/or FEBC3 registers are set in CPU rewrite mode, the bus format for the

corresponding space functions as separate bus. Any external devices connected in multiplexed

bus format become inaccessible.

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R32C/117 Group 10. Protection

10. Protection

This function protects important registers from being easily overwritten when a program goes out of control.

Registers used to protect other registers from being rewritten are as follows: PRCR, PRCR2, PRCR3, and

PRR.

10.1 Protect Register (PRCR Register)

Figure 10.1 shows the PRCR register. Registers protected by bits in the PRCR register are listed in Table

10.1.

The PRC2 bit becomes 0 (write disabled) when a write operation is performed in any other address after

this bit is set to 1 (write enabled). Set the PRC2 bit to 1 just before rewriting registers PD9, P9_iS, PLC0,

and PLC1 (i = 0 to 7). No interrupt handling or DMA transfers should be inserted between these two

instructions. Bits PRC1 and PRC0 do not become 0 even if a write operation is performed in any other

address. These bits should be set to 0 by a program.

Figure 10.1 PRCR Register

Table 10.1 Registers Protected by the PRCR Register

Bit Protected Registers

PRC0 CM0, CM1, CM2, and PM3

PRC1 PM0, PM2, CSOP0, CSOP1, CSOP2, INVC0, INVC1, IOBC, and I2CMR

PRC2 PLC0, PLC1, PD9, and P9_iS (i = 0 to 7)

b7 b6 b5 b4 b1b2b3 Symbol

PRCR

Address

4004Ah

Reset Value

XXXX X000b

FunctionBit Symbol Bit Name RW

Protect Register

No register bits; should be written with 0 and read as undefined

value

Note:

1. The PRC2 bit becomes 0 when a write operation is performed in any other address after this bit is set to 1.

Enable writing to registers CM0,

CM1, CM2, and PM3

0: Write disabled

1: Write enabled

Protect Bit 0

Enable writing to registers PM0,

PM2, CSOP0, CSOP1, CSOP2,

INVC0, INVC1, IOBC, and I2CMR

0: Write disabled

1: Write enabled

Protect Bit 1

Enable writing to registers PLC0,

PLC1, PD9, and P9_iS (i = 0 to 7)

0: Write disabled

1: Write enabled

Protect Bit 2 (1)

—

(b7-b3)

PRC0

PRC1

PRC2

—

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R32C/117 Group 10. Protection

10.2 Protect Register 2 (PRCR2 Register)

Figure 10.2 shows the PRCR2 register which protects the CM3 register only.

Figure 10.2 PRCR2 Register

10.3 Protect Register 3 (PRCR3 Register)

Figure 10.3 shows the PRCR3 register. Registers protected by the bits in the PRCR3 register are listed in

Table 10.2.

Figure 10.3 PRCR3 Register

Table 10.2 Registers Protected by the PRCR3 Register

Bit Protected Registers

PRC31 VRCR, LVDC, and DVCR

b7 b6 b5 b4 b1b2b3 Symbol

PRCR2

Address

4405Fh

Reset Value

0XXX XXXXb

FunctionBit Symbol Bit Name RW

—

Protect Register 2

Enable writing to the CM3 register

0: Write disabled

1: Write enabled

CM3 Protect BitPRC27

—

(b6-b0)

No register bits; should be written with 0 and read as undefined

value

b7 b6 b5 b4 b1b2b3 Symbol

PRCR3

Address

4004Ch

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Protect Register 3

—

(b7-b2) RWReserved

000000 0

Should be written with 0

PRC31

Enable writing to registers VRCR,

LVDC, and DVCR

0: Write disabled

1: Write enabled

Protect Bit 31 RW

—

(b0) RWReserved Should be written with 0

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R32C/117 Group 10. Protection

10.4 Protect Release Register (PRR Register)

Figure 10.4 shows the PRR register. Registers protected by the PRR register are as follows: CCR,

FMCR, PBC, FEBC0, FEBC3, EBC0 to EBC3, CB01, CB12, and CB23.

To write to the registers above, the PRR register should be set to AAh (write enabled). Otherwise, the

PRR register should be set to any value other than AAh to protect the above registers from unexpected

write accesses.

Figure 10.4 PRR Register

b7 Symbol

PRR

Address

0007h

Reset Value

00h

Function RW

Protect Release Register

Control the protection for registers CCR, FMCR, PBC,

FEBC0, FEBC3, EBC0 to EBC3, CB01, CB12, and CB23.

AAh: Write enabled

Value other than AAh: Write disabled

Setting Range

00h to FFh

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R32C/117 Group 11. Interrupts

11.Interrupts

11.1 Interrupt Types

Figure 11.1 shows the types of interrupts.

Figure 11.1 Interrupts

Interrupts are also classified into maskable/non-maskable.

(1) Maskable Interrupts

Maskable interrupts can be disabled by the interrupt enable flag (I flag).

The priority can be configured by assigning an interrupt request level.

(2) Non-maskable Interrupts

Maskable interrupts cannot be disabled by the interrupt enable flag (I flag).

The interrupt priority cannot be configured.

Interrupt

Software

(Non-maskable interrupts)

Hardware

Special

(Non-maskable interrupts)

Peripheral (1)

(Maskable interrupts)

Undefined instruction (UND instruction)

Overflow (INTO instruction)

BRK instruction

BRK2 instruction (2)

INT instruction

NMI

Watchdog timer

Oscillator stop detection

Low voltage detection

Single-step (2)

DMAC II

Notes:

1. The peripheral interrupts are generated by the corresponding peripherals in the MCU.

2. This interrupt is used exclusively as a development support tool. Users are not allowed to use this interrupt.

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R32C/117 Group 11. Interrupts

11.2 Software Interrupts

Software interrupts are non-maskable. A software interrupt occurs by executing an instruction.

There are five types of software interrupts shown below.

(1) Undefined Instruction Interrupt

This interrupt occurs when the UND instruction is executed.

(2) Overflow Interrupt

This interrupt occurs when the INTO instruction is executed while the O flag is 1. The following

instructions may change the O flag to 1, depending on the operation result:

ABS, ADC, ADCF, ADD, ADDF, ADSF, CMP, CMPF, CNVIF, DIV, DIVF, DIVU, DIVX, EDIV, EDIVU,

EDIVX, MUL, MULF, MULU, MULX, NEG, RMPA, ROUND, SBB, SCMPU, SHA, SUB, SUBF, SUNTIL,

and SWHILE

(3) BRK Instruction Interrupt

This interrupt occurs when the BRK instruction is executed.

(4) BRK2 Instruction Interrupt

This interrupt occurs when the BRK2 instruction is executed.

This interrupt is only meant for use as a development support tool and users are not allowed to use it.

(5) INT Instruction Interrupt

This interrupt occurs when the INT instruction is executed with a selected software interrupt number

from 0 to 255. Software interrupt numbers 0 to 127 are designated for peripheral interrupts. That is, the

INT instruction with a software interrupt number from 0 to 127 has the same interrupt handler as that for

peripheral interrupts.

The stack pointer (SP) used for this interrupt differs depending on the software interrupt numbers. For

software interrupt numbers 0 to 127, when an interrupt request is accepted, the U flag is saved and set

to 0 to select the interrupt stack pointer (ISP) during the interrupt sequence. The saved data of the U

flag is restored upon returning from the interrupt handler. For software interrupt numbers 128 to 255,

the stack pointer does not change during the interrupt sequence.

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11.3 Hardware Interrupts

There are two kinds of hardware interrupts: special interrupts and peripheral interrupts.

In peripheral interrupts, only one interrupt with the highest priority can be specified as a fast interrupt.

11.3.1 Special Interrupts

Special interrupts are non-maskable. There are five special interrupts shown below.

(1) NMI (Non Maskable Interrupt)

This interrupt occurs when an input signal at the NMI pin switches from high to low. Refer to 11.11 “NMI”

for details.

(2) Watchdog Timer Interrupt

The watchdog timer generates this interrupt. Refer to 12. “Watchdog Timer” for details.

(3) Oscillator Stop Detection Interrupt

This interrupt occurs when the MCU detects a main clock oscillator stop. Refer to 8.2 “Oscillator Stop

Detection” for details.

(4) Low Voltage Detection Interrupt

This interrupt occurs when a low voltage input to VCC is detected by the voltage detector. Refer to 6.2

“Low Voltage Detector” for details.

(5) Single-step Interrupt

This interrupt is only meant for use as a development support tool and users are not allowed to use it.

11.3.2 Peripheral Interrupts

Peripheral interrupts occur when an interrupt request from a peripheral in the MCU is accepted. They

share the interrupt vector with software interrupt numbers 0 to 127 for the INT instruction. Peripheral

interrupts are maskable.

Refer to Tables 11.2 to 11.5 for details on the interrupt sources. Refer to the relevant descriptions for

details on each function.

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R32C/117 Group 11. Interrupts

11.4 Fast Interrupt

A fast interrupt enables the CPU to accelerate interrupt response. In peripheral interrupts, only one

interrupt with the highest priority can be specified as the fast interrupt.

Use the following procedure to enable a fast interrupt:

(1) Set the both FSIT bit in registers RIPL1 and RIPL2 to 1 (interrupt request level 7 available for fast

interrupt).

(2) Set the both DMAII bit in registers RIPL1 and RIPL2 to 0 (interrupt request level 7 available for

interrupts).

(3) Set the start address of the fast interrupt handler to the VCT register.

Under the conditions above, bits ILVL2 to ILVL0 in the interrupt control register should be set to 111b

(level 7) to enable the fast interrupt. No other interrupts should be set to interrupt request level 7.

When the fast interrupt is accepted, the flag register (FLG) and program counter (PC) are saved to the

save flag register (SVF) and save PC register (SVP), respectively. The program is executed from the

address indicated by the VCT register.

To return from the fast interrupt handler, the FREIT instruction should be executed. The values saved into

registers SVF and SVP are restored to the FLG register and PC, respectively.

11.5 Interrupt Vectors

Each interrupt vector has a 4-byte memory space, in which the start address of the associated interrupt

handler is stored. When an interrupt request is accepted, a jump to the address set in the interrupt vector

takes place. Figure 11.2 shows an interrupt vector.

Figure 11.2 Interrupt Vector

Lower byte of an address

Mid-lower byte of an address

Mid-upper byte of an address

Upper byte of an address

MSB LSB

Vector address + 0

Vector address + 1

Vector address + 2

Vector address + 3

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R32C/117 Group 11. Interrupts

11.5.1 Fixed Vector Table

The fixed vector table is allocated in addresses FFFFFFDCh to FFFFFFFFh. Table 11.1 lists the fixed

vector table.

11.5.2 Relocatable Vector Table

The relocatable vector table occupies a 1024-byte memory space from the start address set in the INTB

An address in a multiple of 4 should be set in the INTB register for a faster interrupt sequence.

Table 11.1 Fixed Vector Table

Interrupt Source Vector Addresses

(Address (L) to Address (H)) Remarks Reference

Undefined

instruction

FFFFFFDCh to FFFFFFDFh Interrupt by the UND

instruction

R32C/100 Series Software

Manual

Overflow FFFFFFE0h to FFFFFFE3h Interrupt by the INTO

instruction

BRK instruction FFFFFFE4h to FFFFFFE7h If address FFFFFFE7h is FFh,

a jump to the interrupt vector of

software interrupt number 0 in

the relocatable vector table

takes place

— FFFFFFE8h to FFFFFFEBh Reserved

— FFFFFFECh to FFFFFFEFh Reserved

Watchdog timer

Oscillator stop

detection

Low voltage

detection

FFFFFFF0h to FFFFFFF3h These addresses are shared

by the watchdog timer

interrupt, oscillator stop

detection interrupt, and low

voltage detection interrupt

12. “Watchdog Timer”

8. “Clock Generator”

6.2 “Low Voltage Detector”

— FFFFFFF4h to FFFFFFF7h Reserved

NMI FFFFFFF8h to FFFFFFFBh External interrupt by the NMI

Reset FFFFFFFCh to FFFFFFFFh 5. “Resets”

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R32C/117 Group 11.  Interrupts
Notes:
1. Each entry is relative to the base address in the INTB register.
2. Interrupts from this source cannot be disabled by the I flag.
3. In I2C mode, interrupts are generated by NACK, ACK, or detection of a START condition/STOP
condition.
4. The IFSR16 bit in the IFSR1 register selects either the interrupt source in UART5 or UART6.
Table 11.2 Relocatable Vector Table (1/4)
Interrupt Source Vector Table Relative Addresses 
(Address (L) to Address (H)) (1)
Software 
Interrupt 
Number
Reference
BRK instruction (2) +0 to +3 (0000h to 0003h) 0 R32C/100 Series 
Software Manual
Reserved +4 to +7 (0004h to 0007h) 1
UART5 transmission, NACK (3) +8 to +11 (0008h to 000Bh) 2 18. “Serial 
Interface”
UART5 reception, ACK (3) +12 to +15 (000Ch to 000Fh) 3
UART6 transmission, NACK (3) +16 to +19 (0010h to 0013h) 4
UART6 reception, ACK (3) +20 to +23 (0014h to 0017h) 5
Bus collision detection, START 
condition detection, or STOP condition 
detection (UART5 or UART6) (3, 4)
+24 to +27 (0018h to 001Bh) 6
Reserved +28 to +31 (001Ch to 001Fh) 7
DMA0 transfer complete +32 to +35 (0020h to 0023h) 8 13. “DMAC”
DMA1 transfer complete +36 to +39 (0024h to 0027h) 9
DMA2 transfer complete +40 to +43 (0028h to 002Bh) 10
DMA3 transfer complete +44 to +47 (002Ch to 002Fh) 11
Timer A0 +48 to +51 (0030h to 0033h) 12 16.1 “Timer A”
Timer A1 +52 to +55 (0034h to 0037h) 13
Timer A2 +56 to +59 (0038h to 003Bh) 14
Timer A3 +60 to +63 (003Ch to 003Fh) 15
Timer A4 +64 to +67 (0040h to 0043h) 16
UART0 transmission, NACK (3) +68 to +71 (0044h to 0047h) 17 18. “Serial 
Interface”
UART0 reception, ACK (3) +72 to +75 (0048h to 004Bh) 18
UART1 transmission, NACK (3) +76 to +79 (004Ch to 004Fh) 19
UART1 reception, ACK (3) +80 to +83 (0050h to 0053h) 20
Timer B0 +84 to +87 (0054h to 0057h) 21 16.2 “Timer B”
Timer B1 +88 to +91 (0058h to 005Bh) 22
Timer B2 +92 to +95 (005Ch to 005Fh) 23
Timer B3 +96 to +99 (0060h to 0063h) 24
Timer B4 +100 to +103 (0064h to 0067h) 25
INT5 +104 to +107 (0068h to 006Bh) 26 11.10 “External 
Interrupt”
INT4 +108 to +111 (006Ch to 006Fh) 27
INT3 +112 to +115 (0070h to 0073h) 28
INT2 +116 to +119 (0074h to 0077h) 29
INT1 +120 to +123 (0078h to 007Bh) 30
INT0 +124 to +127 (007Ch to 007Fh) 31
Timer B5 +128 to +131 (0080h to 0083h) 32 16.2 “Timer B”

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R32C/117 Group 11.  Interrupts
Notes:
1. Each entry is relative to the base address in the INTB register.
2. In I2C mode, interrupts are generated by NACK, ACK, or detection of a START condition/STOP
condition.
3. Select an interrupt source either of UART2 or I2C-bus interface by setting the I2CEN bit in the I2CMR
register.
4. The IFSR06 bit in the IFSR0 register selects either the interrupt source in UART0 or UART3. The
IFSR07 bit selects either the interrupt source in UART1 or that in UART4.
Table 11.3 Relocatable Vector Table (2/4)
Interrupt Source Vector Table Relative Addresses
(Address (L) to Address (H)) (1)
Software 
Interrupt 
Number
Reference
UART2 transmission, NACK (2)/I2C-bus 
interface (3)
+132 to +135 (0084h to 0087h) 33 18. “Serial 
Interface”/24. “Multi-
master I2C-bus 
Interface”
UART2 reception, ACK (2)/I2C-bus line (3) +136 to +139 (0088h to 008Bh) 34
UART3 transmission, NACK (2) +140 to +143 (008Ch to 008Fh) 35
UART3 reception, ACK (2) +144 to +147 (0090h to 0093h) 36
UART4 transmission, NACK (2) +148 to +151 (0094h to 0097h) 37
UART4 reception, ACK (2) +152 to +155 (0098h to 009Bh) 38
Bus collision detection, START condition 
detection, or STOP condition detection 
(UART2) (2)
+156 to +159 (009Ch to 009Fh) 39
Bus collision detection, START condition 
detection, or STOP condition detection 
(UART3 or UART0) (2, 4)
+160 to +163 (00A0h to 00A3h) 40
Bus collision detection, START condition 
detection, or STOP condition detection 
(UART4 or UART1) (2, 4)
+164 to +167 (00A4h to 00A7h) 41
A/D0 +168 to +171 (00A8h to 00ABh) 42 19. “A/D Converter”
Key input +172 to +175 (00ACh to 00AFh) 43 11.12 “Key Input 
Interrupt”
Intelligent I/O interrupt 0 +176 to +179 (00B0h to 00B3h) 44 11.13 “Intelligent I/O 
Interrupt”,
 23. “Intelligent I/O”
Intelligent I/O interrupt 1 +180 to +183 (00B4h to 00B7h) 45
Intelligent I/O interrupt 2 +184 to +187 (00B8h to 00BBh) 46
Intelligent I/O interrupt 3 +188 to +191 (00BCh to 00BFh) 47
Intelligent I/O interrupt 4 +192 to +195 (00C0h to 00C3h) 48
Intelligent I/O interrupt 5 +196 to +199 (00C4h to 00C7h) 49
Intelligent I/O interrupt 6 +200 to +203 (00C8h to 00CBh) 50
Intelligent I/O interrupt 7 +204 to +207 (00CCh to 00CFh) 51
Intelligent I/O interrupt 8 +208 to +211 (00D0h to 00D3h) 52
Intelligent I/O interrupt 9 +212 to +215 (00D4h to 00D7h) 53
Intelligent I/O interrupt 10 +216 to +219 (00D8h to 00DBh) 54
Intelligent I/O interrupt 11 +220 to +223 (00DCh to 00DFh) 55
Reserved +224 to +227 (00E0h to 00E3h) 56
Reserved +228 to +231 (00E4h to 00E7h) 57
CAN0 wakeup +232 to +235 (00E8h to 00EBh) 58 25. “CAN Module”
Reserved +236 to +239 (00ECh to 00EFh) 59
Reserved +240 to +243 (00F0h to 00F3h) 60
Reserved +244 to +247 (00F4h to 00F7h) 61
Reserved +248 to +251 (00F8h to 00FBh) 62
Reserved +252 to +255 (00FCh to 00FFh) 63

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R32C/117 Group 11. Interrupts

Notes:

1. Entries in this table cannot be used to exit wait mode or stop mode.

2. Each entry is relative to the base address in the INTB register.

Table 11.4 Relocatable Vector Table (3/4) (1)

Interrupt Source Vector Table Relative Addresses

(Address (L) to Address (H)) (2)

Software

Interrupt

Number

Reference

Reserved +256 to +259 (0100h to 0103h) 64

Reserved +260 to +263 (0104h to 0107h) 65

Reserved +264 to +267 (0108h to 010Bh) 66

Reserved +268 to +271 (010Ch to 010Fh) 67

Reserved +272 to +275 (0110h to 0113h) 68

Reserved +276 to +279 (0114h to 0117h) 69

Reserved +280 to +283 (0118h to 011Bh) 70

Reserved +284 to +287 (011Ch to 011Fh) 71

Reserved +288 to +291 (0120h to 0123h) 72

Reserved +292 to +295 (0124h to 0127h) 73

Reserved +296 to +299 (0128h to 012Bh) 74

Reserved +300 to +303 (012Ch to 012Fh) 75

Reserved +304 to +307 (0130h to 0133h) 76

Reserved +308 to +311 (0134h to 0137h) 77

Reserved +312 to +315 (0138h to 013Bh) 78

Reserved +316 to +319 (013Ch to 013Fh) 79

CAN0 transmit FIFO +320 to +323 (0140h to 0143h) 80 25. “CAN Module”

CAN0 receive FIFO +324 to +327 (0144h to 0147h) 81

Reserved +328 to +331 (0148h to 014Bh) 82

Reserved +332 to +335 (014Ch to 014Fh) 83

Reserved +336 to +339 (0150h to 0153h) 84

Reserved +340 to +343 (0154h to 0157h) 85

Reserved +344 to +347 (0158h to 015Bh) 86

Reserved +348 to +351 (015Ch to 015Fh) 87

Reserved +352 to +355 (0160h to 0163h) 88

Reserved +356 to +359 (0164h to 0167h) 89

Reserved +360 to +363 (0168h to 016Bh) 90

Reserved +364 to +367 (016Ch to 016Fh) 91

Reserved +368 to +371 (0170h to 0173h) 92

INT8 +372 to +375 (0174h to 0177h) 93 11.10 “External

Interrupt”

INT7 +376 to +379 (0178h to 017Bh) 94

INT6 +380 to +383 (017Ch to 017Fh) 95

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R32C/117 Group 11. Interrupts

Notes:

1. Entries in this table cannot be used to exit wait mode or stop mode.

2. Each entry is relative to the base address in the INTB register.

3. Interrupts from this source cannot be disabled by the I flag.

Table 11.5 Relocatable Vector Table (4/4) (1)

Interrupt Source Vector Table Relative Addresses

(Address (L) to Address (H)) (2)

Software

Interrupt

Number

Reference

CAN0 transmission +384 to +387 (0180h to 0183h) 96 25. “CAN Module”

CAN0 reception +388 to +391 (0184h to 0187h) 97

CAN0 error +392 to +395 (0188h to 018Bh) 98

Reserved +396 to +399 (018Ch to 018Fh) 99

Reserved +400 to +403 (0190h to 0193h) 100

Reserved +404 to +407 (0194h to 0197h) 101

Reserved +408 to +411 (0198h to 019Bh) 102

Reserved +412 to +415 (019Ch to 019Fh) 103

Reserved +416 to +419 (01A0h to 01A3h) 104

Reserved +420 to +423 (01A4h to 01A7h) 105

Reserved +424 to +427 (01A8h to 01ABh) 106

Reserved +428 to +431 (01ACh to 01AFh) 107

Reserved +432 to +435 (01B0h to 01B3h) 108

Reserved +436 to +439 (01B4h to 01B7h) 109

Reserved +440 to +443 (01B8h to 01BBh) 110

Reserved +444 to +447 (01BCh to 01BFh) 111

Reserved +448 to +451 (01C0h to 01C3h) 112

Reserved +452 to +455 (01C4h to 01C7h) 113

Reserved +456 to +459 (01C8h to 01CBh) 114

Reserved +460 to +463 (01CCh to 01CFh) 115

Reserved +464 to +467 (01D0h to 01D3h) 116

Reserved +468 to +471 (01D4h to 01D7h) 117

Reserved +472 to +475 (01D8h to 01DBh) 118

Reserved +476 to +479 (01DCh to 01DFh) 119

Reserved +480 to +483 (01E0h to 01E3h) 120 18. “Serial Interface”

Reserved +484 to +487 (01E4h to 01E7h) 121

Reserved +488 to +491 (01E8h to 01EBh) 122

Reserved +492 to +495 (01ECh to 01EFh) 123

UART7 transmission +496 to +499 (01F0h to 01F3h) 124

UART7 reception +500 to +503 (01F4h to 01F7h) 125

UART8 transmission +504 to +507 (01F8h to 01FBh) 126

UART8 reception +508 to +511 (01FCh to 01FFh) 127

INT instruction (3) +0 to +3 (0000h to 0003h) to

+1020 to +1023 (03FCh to 03FFh)

0 to 255 11.2 “Software

Interrupts”

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11.6 Interrupt Request Acceptance

Software interrupts and special interrupts are accepted whenever their interrupt request is generated.

Peripheral interrupts, however, are only accepted if the conditions below are met:

• I flag is 1

• IR bit is 1

• Bits ILVL2 to ILVL0 > IPL

The I flag, IPL, IR bit, and bits ILVL2 to ILVL0 do not affect each other. The I flag and IPL are in the FLG

The following section describes these flag and bits.

11.6.1 I Flag and IPL

The I flag (interrupt enable flag) enables or disables maskable interrupts. When the I flag is set to 1

(enabled), all maskable interrupts are enabled; when it is set to 0 (disabled), they are disabled. The I

flag becomes 0 after a reset.

The IPL (processor interrupt priority level) consists of 3 bits and indicates eight interrupt priority levels

from 0 to 7. An interrupt becomes acceptable when its interrupt request level is higher than the

specified IPL (bits ILVL2 to ILVL0 > IPL).

Table 11.6 lists interrupt request levels classified by the IPL.

Table 11.6 Acceptable Interrupt Request Levels and IPL

IPL Acceptable Interrupt Request Levels

IPL2 IPL1 IPL0

1 1 1 All maskable interrupts are disabled

1 1 0 Level 7 only

1 0 1 Level 6 and above

1 0 0 Level 5 and above

0 1 1 Level 4 and above

0 1 0 Level 3 and above

0 0 1 Level 2 and above

0 0 0 Level 1 and above

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11.6.2 Interrupt Control Registers

Each peripheral interrupt is controlled by an interrupt control register.

Figures 11.3 and 11.4 show the interrupt control registers.

Figure 11.3 Interrupt Control Register (1/2)

Interrupt Control Register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol

TA0IC to TA4IC

TB0IC to TB5IC

Address

006Ch, 008Ch, 006Eh, 008Eh, 0070h

0094h, 0076h, 0096h, 0078h, 0098h, 0061h

Reset Value

XXXX X000b

0090h, 0092h, 0081h (1), 0083h, 0085h

0062h, 0064h, 00DDh, 00DFh

0072h, 0074h, 0063h (2), 0065h, 0067h

0082h, 0084h, 00FDh, 00FFh

0069h, 0089h, 0087h, 0069h (3)

0089h (4), 0066h, 0066h (5)

S0TIC to S4TIC

S5TIC to S8TIC

S0RIC to S4RIC

S5RIC to S8RIC

BCN0IC to BCN3IC

BCN4IC to BCN6IC

XXXX X000b

0068h, 0088h, 006Ah, 008Ah

006Bh

008Bh

006Dh, 008Dh, 006Fh, 008Fh, 0071h, 0091h

0073h, 0093h, 0075h, 0095h, 0077h, 0097h

0081h (1), 0063h (2)

DM0IC to DM3IC

AD0IC

KUPIC

IIO0IC to IIO5IC

IIO6IC to IIO11IC

I2CIC, I2CLIC

XXXX X000b

Bit Symbol Bit Name Function RW

Notes:

1. The S2TIC register shares an address with the I2CIC register.

2. The S2RIC register shares an address with the I2CLIC register.

3. The BCN0IC register shares an address with the BCN3IC register.

4. The BCN1IC register shares an address with the BCN4IC register.

5. The BCN5IC register shares an address with the BCN6IC register.

6. This bit can only be set to 0 (do not set it to 1).

No register bits; should be written with 0 and read as undefined

value

Interrupt Request Flag RW

Interrupt Request Level

Select Bit

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

0: No interrupt requested

1: Interrupt requested (6)

C0FTIC

C0FRIC

C0TIC

C0RIC

C0EIC

C0WIC

XXXX X000b

00D0h

00F0h

00C1h

00E1h

00C3h

007Bh

ILVL0

ILVL1

ILVL2

—

(b7-b4) —

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Figure 11.4 Interrupt Control Register (2/2)

Bits ILVL2 to ILVL0

The interrupt request level is selected by setting bits ILVL2 to ILVL0. The higher the level is, the higher

interrupt priority is.

When an interrupt request is generated, its request level is compared to the IPL. The interrupt is

accepted only when the interrupt request level is higher than the IPL. When bits ILVL2 to ILVL0 are set

to 000b, the interrupt is disabled.

IR bit

The IR bit becomes 1 (interrupt requested) when an interrupt request is generated; this bit setting is

retained until the interrupt request is accepted. When the request is accepted and a jump to the

corresponding interrupt vector takes place, the IR bit becomes 0 (no interrupt requested).

The IR bit can be set to 0 by a program. This bit should not be set to 1.

Interrupt Control Register

b7 b6 b5 b4 b3 b2 b1 b0 Symbol

INT0IC to INT2IC

INT3IC to INT5IC (1)

INT6IC to INT8IC

Address

009Eh, 007Eh, 009Ch

007Ch, 009Ah, 007Ah

00FEh, 00DEh, 00FCh

Reset Value

XX00 X000b

Bit Symbol Bit Name Function RW

—

Notes:

1. When the 16- or 32-bit data bus is used in microprocessor mode or memory expansion mode, pins INT3 to

INT5 function as data bus. In this case, set bits ILVL2 to ILVL0 in registers INT3IC to INT5IC to 000b.

2. This bit can only be set to 0 (do not set it to 1).

3. Set this bit to 0 (the falling edge) to set the corresponding bit in registers IFSR0 and IFSR1 to 1 (both

edges).

4. Set the corresponding bit in registers IFSR0 and IFSR1 to 0 (one edge) to select the level sensitive.

No register bits; should be written with 0 and read as undefined

value

Interrupt Request Flag RW

Interrupt Request Level

Select Bit

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

0: No interrupt requested

1: Interrupt requested (2)

Level/Edge Sensitive

Select Bit RW

0: Edge sensitive

1: Level sensitive (4)

Polarity Select Bit RW

0: Select the falling edge or a low

1: Select the rising edge or a high (3)

ILVL0

ILVL1

ILVL2

POL

LVS

—

(b7-b6)

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When rewriting the interrupt control register, no corresponding interrupt request should be generated. If

there is a possibility that an interrupt request may be generated, disable the interrupt request before

rewriting the register.

When enabling an interrupt immediately after changing the interrupt control register, insert NOPs

between two instructions or perform a dummy read of the interrupt control register so that the interrupt

enable flag (I flag) cannot become 1 (interrupt enabled) before writing to the interrupt control register is

completed.

If an interrupt request is generated for the register being rewritten, the IR bit may not become 1

depending on the instruction being used. If it matters, use one of the following instructions to rewrite the

•AND

•OR

•BCLR

• BSET

If the AND or BCLR instruction is used to set the IR bit to 0, the IR bit may not become 0 as these

instructions cause the interrupt request to be retained during the rewrite. To prevent this from

happening, rewrite the register using the MOV instruction. To set just the IR bit to 0, first temporarily

store the read value to memory or a CPU internal register, then execute either the AND or BCLR

instruction in the stored area. After that, write the value back to the register using the MOV instruction.

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11.6.3 Wake-up IPL Setting Register

Set the wake-up IPL setting registers (registers RIPL1 and RIPL2) when using an interrupt to exit wait

or stop mode, or using the fast interrupt.

Refer to 8.7.2 “Wait Mode”, 8.7.3 “Stop Mode”, or 11.4 “Fast Interrupt” for details.

Figure 11.5 shows registers RIPL1 and RIPL2.

Figure 11.5 Registers RIPL1 and RIPL2

Wake-up IPL Setting Register i (i = 1, 2) (1)

Symbol

RIPL1, RIPL2

Address

4407Fh, 4407Dh

Reset Value

XX0X 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Interrupt Priority Level for

Wake-up Select Bit (2)

b2 b1 b0

000:Level 0

001:Level 1

010:Level 2

011:Level 3

100:Level 4

101:Level 5

110:Level 6

111:Level 7

0: Use interrupt request level 7 for

normal interrupt

1: Use interrupt request level 7 for

fast interrupt (4)

Fast Interrupt Select Bit (3)

—

0: Use interrupt request level 7 for

interrupt

1: Use interrupt request level 7 for

DMA II transfer (4)

DMA II Select Bit (5)

—

Notes:

1. Registers RIPL1 and RIPL2 should be set with the same values.

2. The MCU exits wait mode or stop mode when the request level of the requested interrupt is higher than the

level selected using bits RLVL2 to RLVL0. Set these bits to the same value as the IPL in the FLG register.

3. When the FSIT bit is 1, an interrupt with interrupt request level 7 becomes the fast interrupt. In this case, set

the interrupt request level to level 7 with only one interrupt.

4. Set either the FSIT or DMAII bit to 1. The fast interrupt and DMAC II cannot be used simultaneously.

5. Set bits ILVL2 to ILVL0 in the interrupt control register after the DMAII bit is set. DMA II transfer is not

affected by the I flag or IPL.

No register bits; should be written with 0 and read as undefined

value

No register bit; should be written with 0 and read as undefined

value

RLVL0

RLVL1

RLVL2

FSIT

—

(b4)

DMAII

—

(b7-b6)

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11.6.4 Interrupt Sequence

An interrupt sequence is performed from when an interrupt request has been accepted until the interrupt

handler starts.

When an interrupt request is generated while an instruction is being executed, the requested interrupt is

evaluated in the priority resolver after the current instruction is completed, and the interrupt sequence

starts from the next cycle.

However, for instructions RMPA, SCMPU, SIN, SMOVB, SMOVF, SMOVU, SOUT, SSTR, SUNTIL, and

SWHILE, when an interrupt request is generated while an instruction is being executed, the current

instruction is suspended, and the interrupt sequence starts.

The interrupt sequence is as follows:

(1) The CPU acknowledges the interrupt request to obtain the interrupt information (the interrupt

number, and the interrupt request level) from the interrupt controller. Then the corresponding IR bit

becomes 0 (no interrupt requested).

(2) The FLG register value before the interrupt sequence is stored to a temporary register in the CPU.

The temporary register is inaccessible to users.

(3) The following bits in the FLG register become 0:

• The I flag (interrupt enable flag): interrupt disabled

• The D flag (debug flag): single-step interrupt disabled

• The U flag (stack pointer select flag): ISP selected

(4) The temporary register value in the CPU is saved to the stack, or to the SVF register in case of the

fast interrupt.

(5) The PC value is saved to the stack, or to the SVP register in case of the fast interrupt.

(6) The interrupt request level for the accepted interrupt is set in the IPL (processor interrupt priority

level).

(7) The corresponding interrupt vector is read from the interrupt vector table.

(8) This interrupt vector is stored into the PC.

After the interrupt sequence is completed, an instruction is executed from the start address of the interrupt

handler.

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11.6.5 Interrupt Response Time

The interrupt response time, as shown in Figure 11.6, consists of two non-overlapping time segments:

(a) the period from when an interrupt request is generated until the instruction being executed is

completed; and (b) the period required for the interrupt sequence.

Figure 11.6 Interrupt Response Time

Period (a) varies depending on the instruction being executed. Instructions, such as LDCTX and

STCTX in which registers are sequentially saved into or restored from the stack, require the longest

time. For example, the STCTX instruction requires at least 30 cycles for 10 registers to be saved. It

requires more time if the WAIT instruction is in the stack.

Period (b) is listed in Table 11.7.

Notes:

1. These are the values when the interrupt vectors are aligned to the addresses in multiples of 4 in the

internal ROM. However, the condition does not apply to the fast interrupt.

2.  is the number of waits to access SFRs minus 2.

Table 11.7 Interrupt Sequence Execution Time (1)

Interrupt Execution Time in Terms of CPU Clock

Peripherals 13 +  cycles (2)

INT instruction 11 cycles

NMI 10 cycles

Watchdog timer

Oscillator stop detection

Low voltage detection

11 cycles

Undefined instruction 12 cycles

Overflow 12 cycles

BRK instruction (relocatable vector table) 16 cycles

BRK instruction (fixed vector table) 19 cycles

BRK2 instruction 19 cycles

Fast interrupt 11 cycles

Instruction Interrupt sequence Instruction in an interrupt handler

Interrupt request is acceptedInterrupt request is generated

(a) (b)

Interrupt response time

Time

(a) Period from when an interrupt request is generated until when the instruction being executed has

been completed

(b) Period required to perform an interrupt sequence

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11.6.6 IPL after Accepting an Interrupt Request

When a peripheral interrupt request is accepted, the interrupt request level is set in the IPL (processor

interrupt priority level).

Software interrupts and special interrupts have no interrupt request level. When these interrupt

requests are accepted, the value listed in Table 11.8 is set in the IPL as the interrupt request level.

11.6.7 Register Saving

In the interrupt sequence, the FLG register and PC values are saved to the stack, in that order. Figure

11.7 shows the stack status before and after an interrupt request is accepted.

In the fast interrupt sequence, the FLG register and PC values are saved to registers SVF and SVP,

respectively.

If there are any other registers to be saved to the stack, save them at the beginning of the interrupt

handler. A single PUSHM instruction saves all registers except the frame base register (FB) and stack

pointer (SP).

Figure 11.7 Stack Before and After an Interrupt Request is Accepted

Table 11.8 Interrupts without Interrupt Request Level and IPL

Interrupt Sources without Interrupt Request Level IPL Value to be Set

NMI, watchdog timer, oscillator stop detection, low voltage detection 7

Reset 0

Software Unchanged

Stack before interrupt request is accepted Stack after interrupt request is accepted

Content of previous stack

m+1

m-1

m-2

m-3

m-4

m-5

m-6

m-7

m-8

MSB LSB

Stack

Address

Content of previous stack

Flag register (FLGHH)

Flag register (FLGHL)

Flag register (FLGLH)

Flag register (FLGLL)

Program counter (PCHH)

Program counter (PCHL)

Program counter (PCLH)

Program counter (PCLL)

m+1

m-1

m-2

m-3

m-4

m-5

m-6

m-7

m-8 SP

MSB LSB

Stack

Address

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11.7 Register Restoring from Interrupt Handler

When the REIT instruction is executed at the end of the interrupt handler, the FLG register and PC values,

which are saved in the stack, are restored, and the program resumes the operation that was interrupted. In

the fast interrupt, execute the FREIT instruction to restore them from the save registers, instead.

To restore the register values which are saved by software in the interrupt handler, use an instruction such

as POPM before the REIT or FREIT instruction.

If the register bank is switched in the interrupt handler, the bank is automatically switched back to the

original register bank by the REIT or FREIT instruction.

11.8 Interrupt Priority

If two or more interrupt requests are detected at an interrupt request sampling point, the interrupt request

with higher priority is accepted.

For maskable interrupts (peripheral interrupts), the interrupt request level select bits (bits ILVL2 to ILVL0)

select a request level. If two or more interrupt requests have the same request level, the interrupt with

higher priority, predetermined by hardware, is accepted.

The priorities of the reset and special interrupts, such as the watchdog timer interrupt, are determined by

the hardware. Note that the reset has the highest priority. The following is the priority order determined by

the hardware:

Software interrupts are not governed by priority. A jump to the interrupt handler takes place whenever the

relevant instruction is executed.

11.9 Priority Resolver

The priority resolver selects an interrupt that has the highest priority among requested interrupts detected

at the same sampling point.

Figure 11.8 shows the priority resolver.

Reset

Watchdog timer

Oscillator stop detection

Low voltage detection

NMI Peripherals

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R32C/117 Group 11. Interrupts

Figure 11.8 Priority Resolver

DMA0

DMA2

Timer A0

Timer A2

Timer A4

UART0 reception

UART1 reception

Timer B1

Timer B3

INT5

INT3

INT1

Timer B5

UART2 rec. / I2C line

UART3 reception

UART4 reception

Bus collision (UART0, 3)

A/D converter 0

Intelligent I/O0

Intelligent I/O2

DMA1

DMA3

Timer A1

Timer A3

UART0 transmission

UART1 transmission

Timer B0

Timer B2

Timer B4

INT4

INT2

INT0

UART2 trans. / I2C I/F

UART3 transmission

UART4 transmission

Bus collision (UART2)

Bus collision (UART1, 4)

Key input

Intelligent I/O1

Level 0

(default)

IPL

I flag

NMI

Interrupt request

accepted (to CPU)

High

UART5 reception

UART6 reception

Intelligent I/O4

Intelligent I/O6

Intelligent I/O8

Intelligent I/O10

UART5 transmission

UART6 transmission

Bus collision (UART5, 6)

Intelligent I/O3

Intelligent I/O5

Intelligent I/O7

Intelligent I/O9

Intelligent I/O11

CAN0 transmission

INT8

INT6

CAN0 reception

INT7

Level 0

(default)

Peripheral interrupt priority

(for interrupts with same request level)

UART7 transmission

UART8 transmission

UART7 reception

UART8 reception

Wake-up signal

from wait or stop

mode (to clock

generator)

CAN0 error

High

Oscillator stop detection

Watchdog timer

Low voltage detection

CAN0 wakeup

CAN0 receive FIFO

CAN0 transmit FIFO

Low

Request level of interrupts Request level of interrupts Request level of interrupts

Request level of interruptsRequest level of interruptsRequest level of interrupts

Bits RLVL2 to RLVL0 in

the RIPL1 register

DMA II transfer complete

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R32C/117 Group 11. Interrupts

11.10 External Interrupt

An external interrupt occurs by an external input applied to the INTi pin (i = 0 to 8). Set the LVS bit in the

INTiIC register to select whether an interrupt is triggered by the effective edge(s) (edge sensitive), or by

the effective level (level sensitive) of the input signal. The polarity of the input signal is selected by setting

the POL bit in the same register.

When using edge-triggered interrupts, setting the IFSR0j bit in the IFSR0 register to 1 (both edges)

causes interrupt requests to be generated on both rising and falling edges of the external input applied to

the INTj pin (j = 0 to 5). This also applies to setting the IFSR1n bit (n = m - 6) in the IFSR1 register to 1

(both edges) for the INTm pin (m = 6 to 8). Set the POL bit in the corresponding register to 0 (falling edge)

to set the IFSR0j bit or the IFSR1n bit to 1.

When using level-triggered interrupts, set the IFSR0j or IFSR1n bit to 0 (one edge). When an effective

level, which is selected by the POL bit, is detected on the INTi pin, the IR bit in the INTiIC register

becomes 1. The IR bit does not become 0 even if the signal level at the INTi pin changes. This bit is set to

0 when the INTi interrupt is accepted or it is set to 0 by a program.

Figures 11.9 and 11.10 show registers IFSR0 and IFSR1, respectively.

Figure 11.9 IFSR0 Register

b7 b6 b5 b4 b1b2b3 Symbol

IFSR0

Address

4406Fh

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

External Interrupt Request Source Select Register 0

Note:

1. Set this bit to 0 to select the level sensitive input as trigger. To set this bit to 1, set the POL bit in the

corresponding INTiIC register to 0 (falling edge) (i = 0 to 5).

0: One edge

1: Both edges

INT0 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT1 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT2 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT3 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT4 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT5 Pin Polarity Select Bit

(1)

0: Bus collision, START condition

detection, STOP condition detection

in UART3

1: Bus collision, START condition

detection, STOP condition detection

in UART0

UART0/UART3 Interrupt

Source Select Bit

0: Bus collision, START condition

detection, STOP condition detection

in UART4

1: Bus collision, START condition

detection, STOP condition detection

in UART1

UART1/UART4 Interrupt

Source Select Bit

IFSR00

IFSR01

IFSR02

IFSR03

IFSR04

IFSR05

IFSR06

IFSR07

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Figure 11.10 IFSR1 Register

11.11 NMI

The NMI (non maskable interrupt) occurs when an input signal at the NMI pin switches from high to low.

This non maskable interrupt is disabled after a reset. To enable this interrupt, set the PM24 bit in the PM2

shares a pin with port P8_5, which enables the P8_5 bit in the P8 register to indicate the input level at the

NMI pin.

Note:

1. When not using the NMI, do not change the reset value of the PM24 bit in the PM2 register.

b7 b6 b5 b4 b1b2b3 Symbol

IFSR1

Address

4406Dh

Reset Value

X0XX X000b

FunctionBit Symbol Bit Name RW

External Interrupt Request Source Select Register 1

Note:

1. Set this bit to 0 to select the level sensitive input as trigger. To set this bit to 1, set the POL bit in the

corresponding INTiIC register (i = 6 to 8) to 0 (falling edge).

IFSR10 RW

0: One edge

1: Both edges

INT6 Pin Polarity Select Bit

(1)

IFSR11 RW

0: One edge

1: Both edges

INT7 Pin Polarity Select Bit

(1)

IFSR12 RW

0: One edge

1: Both edges

INT8 Pin Polarity Select Bit

(1)

IFSR16 RW

0: Bus collision, START condition

detection, STOP condition detection

in UART5

1: Bus collision, START condition

detection, STOP condition detection

in UART6

UART5/UART6 Interrupt

Source Select Bit

—

No register bit; should be written with 0 and read as undefined

value

—

(b7)

—

No register bits; should be written with 0 and read as undefined

value

—

(b5-b3)

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11.12 Key Input Interrupt

The key input interrupt is enabled by setting ports P10_4 to P10_7 as input ports.

The interrupt request is generated if any of the signals applied to ports P10_4 to P10_7 switch from high

to low. This interrupt also functions as key wake-up to exit wait or stop mode. Figure 11.11 shows a block

diagram of the key input interrupt. If any of the ports are held low, signals applied to other ports are not

detected as interrupt request signals.

To use the key input interrupt, every register from P10_4S to P10_7S should be set to 00h (I/O port) and

bits PD10_4 to PD10_7 should be set to 0 (input). This is the only setting available for the key input

interrupt.

Figure 11.11 Key Input Interrupt Block Diagram

P10_7/KI3

PD10_7 bit

PU31 bit in the PUR3 register

P10_6/KI2

PD10_6 bit

P10_5/KI1

PD10_5 bit

P10_4/KI0

PD10_4 bit

ASEL bit in the

P10_6S register

Interrupt control

circuit

KUPIC register

Key input interrupt request

ASEL bit in the P10_7S register

ASEL bit in the

P10_5S register

ASEL bit in the

P10_4S register

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11.13 Intelligent I/O Interrupt

The intelligent I/O interrupt is assigned to software interrupt numbers 44 to 55.

Figure 11.12 shows a block diagram of the intelligent I/O interrupt. Figures 11.13 and 11.14 show registers

IIOiIR and IIOiIE, respectively (i = 0 to 11).

To use the intelligent I/O interrupt, set the IRLT bit in the IIOiIE register to 1 (interrupt requests used for

interrupt).

The intelligent I/O interrupt has multiple request sources. When an interrupt request is generated with an

intelligent I/O function, the corresponding bit in the IIOiIR register becomes 1 (interrupt requested). If the

corresponding bit in the IIOiIE register is 1 (interrupt enabled), the IR bit in the corresponding IIOiIC

After the IR bit setting changes from 0 to 1, it remains unchanged if a bit in the IIOiIR register becomes 1

by another interrupt request source and the corresponding bit in the IIOiIE register is 1.

Bits in the IIOiIR register do not become 0 even if an interrupt is accepted. They should be set to 0 by

either the AND or BCLR instruction. Note that every generated interrupt request is ignored until these bits

are set to 0.

To use the intelligent I/O interrupt as a DMAC II trigger, set the IRLT bit in the IIOiIE register to 0 (interrupt

requests used for DMA or DMA II) and the bit used for the interrupt source to 1 (interrupt enabled) in the

IIOiIE register.

Figure 11.12 Intelligent I/O Interrupt Block Diagram (i = 0 to 11)

Bit 1

Bit 2

Bit 7

IIOiIR register (2)

Bit 1

Bit 2

Bit 7

IIOiIE register (3)

Intelligent I/O

interrupt i request

IRLT bit in the

IIOiIE register

Interrupt request (1)

Notes:

1. Refer to Figures 11.13 and 11.14 for bits 1

to 7 in registers IIOiIR and IIOiIE and their

respective interrupt request sources.

2. Bits 1 to 7 in the IIOiIR register do not

become 0 even if an interrupt request is

accepted. Set these bits to 0 by a program.

3. The IRLT bit and the interrupt enable bit in

the IIOiIE register should not be rewritten

simultaneously.

R01UH0211EJ0120 Rev.1.20 Page 164 of 604

Feb 18, 2013

R32C/117 Group 11. Interrupts

Figure 11.13 Registers IIO0IR to IIO11IR

b7 b6 b5 b4 b1b2b3 Symbol

IIO0IR to IIO11IR

Address

Refer to the table below

Reset Value

??0? ???1b (1)

FunctionBit Symbol Bit Name RW

—

Intelligent I/O Interrupt Request Register i (i = 0 to 11)

No register bit; this bit is read as 1

Notes:

1. When the register has any function-assigned bit, the reset value is X (undefined); otherwise, the reset value

is 0.

2. Refer to the table below for bit symbols.

3. When this bit is function-assigned, it can only be set to 0. It should not be set to 1. To set it to 0, either the

AND or BCLR instruction should be used; when the bit is not function-assigned (reserved), it should be set

to 0.

0: No interrupt requested

1: Interrupt requested (3)

0: No interrupt requested

1: Interrupt requested (3)

0: No interrupt requested

1: Interrupt requested (3)

0: No interrupt requested

1: Interrupt requested (3)

0: No interrupt requested

1: Interrupt requested (3)

0: No interrupt requested

1: Interrupt requested (3)

Symbol

IIO0IR

Address

00A0h

Bit 7

—

Bit 6

—

Bit 5

—

Bit 4

—

Bit 3

—

Bit 2

TM13R/PO13R

Bit 1

TM02R/PO02R

Bit Symbols for the Intelligent I/O Interrupt Request Register

IIO1IR 00A1h — — — — — TM14R/PO14R TM00R/PO00R

IIO2IR 00A2h — — — — — TM12R/PO12R

IIO3IR 00A3h — — — — PO27R TM10R/PO10R TM03R/PO03R

IIO4IR 00A4h — — — BT1R —TM17R/PO17R TM04R/PO04R

IIO5IR 00A5h — — — SIO2RR —PO21R TM05R/PO05R

IIO6IR 00A6h — — — SIO2TR —PO20R TM06R/PO06R

IIO7IR 00A7h IE0R — — BT0R —PO22R TM07R/PO07R

IIO8IR 00A8h IE1R IE2R —BT2R —PO23R TM11R/PO11R

IIO9IR 00A9h —INT6R ——— PO24R TM15R/PO15R

IIO10IR 00AAh —INT7R ——— PO25R TM16R/PO16R

IIO11IR 00ABh —INT8R ——— PO26R TM01R/PO01R

—

Bit 0

—

BTxR: Intelligent I/O group x base timer interrupt request (x = 0 to 2)

TMxyR: Intelligent I/O group x time measurement channel y interrupt request (x = 0, 1; y = 0 to 7)

POxyR: Intelligent I/O group x waveform generation channel y interrupt request (x = 0 to 2; y = 0 to 7)

IEzR: Intelligent I/O group 2 IEBus interrupt request (z = 0 to 2)

SIO2RR: Intelligent I/O group 2 receive interrupt request

SIO2TR: Intelligent I/O group 2 transmit interrupt request

INTmR: INTm interrupt request (m = 6 to 8)

Reserved Should be written with 0

—

(b0)

(Note 2)

—

(b5)

(Note 2)

R01UH0211EJ0120 Rev.1.20 Page 165 of 604

Feb 18, 2013

R32C/117 Group 11. Interrupts

Figure 11.14 Registers IIO0IE to IIO11IE

b7 b6 b5 b4 b1b2b3 Symbol

IIO0IE to IIO11IE

Address

Refer to the table below.

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Intelligent I/O Interrupt Enable Register i (i = 0 to 11)

Notes:

1. Refer to the table below for bit symbols.

2. To use interrupt requests for interrupt, the IRLT bit should be set to 1, then bits 1 to 4, 6, and 7 should be

set to 1.

0: Disable the interrupt of bit 1 in the IIOiIR register

1: Enable the interrupt of bit 1 in the IIOiIR register

Symbol

IIO0IE

Address

00B0h

Bit 7

—

Bit 6

—

Bit 5

—

Bit 4

—

Bit 3

—

Bit 2

TM13E/PO13E

Bit 1

TM02E/PO02E

Bit Symbols for the Intelligent I/O Interrupt Enable Register

IIO1IE 00B1h — — — — — TM14E/PO14E TM00E/PO00E

IIO2IE 00B2h — — — — — TM12E/PO12E

IIO3IE 00B3h — — — — PO27E TM10E/PO10E TM03E/PO03E

IIO4IE 00B4h ———BT1E —TM17E/PO17E TM04E/PO04E

IIO5IE 00B5h ———SIO2RE —PO21E TM05E/PO05E

IIO6IE 00B6h ———SIO2TE —PO20E TM06E/PO06E

IIO7IE 00B7h IE0E — — BT0E —PO22E TM07E/PO07E

IIO8IE 00B8h IE1E IE2E —BT2E —PO23E TM11E/PO11E

IIO9IE 00B9h —INT6E — — — PO24E TM15E/PO15E

IIO10IE 00BAh —INT7E — — — PO25E TM16E/PO16E

IIO11IE 00BBh —INT8E — — — PO26E TM01E/PO01E

—

Bit 0

IRLT

BTxE: Intelligent I/O group x base timer interrupt enabled (x = 0 to 2)

TMxyE: Intelligent I/O group x time measurement channel y interrupt enabled (x = 0, 1; y = 0 to 7)

POxyE: Intelligent I/O group x waveform generation channel y interrupt enabled (x = 0 to 2; y = 0 to 7)

IEzE: Intelligent I/O group 2 IEBus interrupt enabled (z = 0 to 2)

SIO2RE: Intelligent I/O group 2 receive interrupt enabled

SIO2TE: Intelligent I/O group 2 transmit interrupt enabled

INTmE: INTm interrupt enabled (m = 6 to 8)

0: Use interrupt requests for DMA or

DMA II

1: Use interrupt requests for interrupt

Interrupt Request Select Bit

(2)

0: Disable the interrupt of bit 2 in the IIOiIR register

1: Enable the interrupt of bit 2 in the IIOiIR register

0: Disable the interrupt of bit 3 in the IIOiIR register

1: Enable the interrupt of bit 3 in the IIOiIR register

0: Disable the interrupt of bit 4 in the IIOiIR register

1: Enable the interrupt of bit 4 in the IIOiIR register

0: Disable the interrupt of bit 6 in the IIOiIR register

1: Enable the interrupt of bit 6 in the IIOiIR register

0: Disable the interrupt of bit 7 in the IIOiIR register

1: Enable the interrupt of bit 7 in the IIOiIR register

Reserved Should be written with 0

IRLT

(Note 1)

—

(b5)

(Note 1)

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R32C/117 Group 11. Interrupts

11.14 Notes on Interrupts

11.14.1 ISP Setting

The interrupt stack pointer (ISP) is initialized to 00000000h after a reset. Set a value to the ISP before

an interrupt is accepted, otherwise the program may go out of control. A multiple of 4 should be set to

the ISP, which enables faster interrupt sequence due to less memory access.

When using NMI, in particular, since this interrupt cannot be disabled, set the PM24 bit in the PM2

11.14.2 NMI

• NMI cannot be disabled once the PM24 bit in the PM2 register is set to 1 (NMI enabled). This bit

setting should be done only when using NMI.

• When the PM24 bit in the PM2 register is 1 (NMI enabled), the P8_5 bit in the P8 register is

enabled just for monitoring the NMI pin state. It is not enabled as a general port.

11.14.3 External Interrupts

• The input signal to the INTi pin requires the pulse width specified in the electrical characteristics (i

= 0 to 8). If the pulse width is narrower than the specification, an external interrupt may not be

accepted.

• When the effective level or edge of the INTi pin (i = 0 to 8) is changed by the following bits: bits

POL, LVS in the INTiIC register, the IFSR0i bit (i = 0 to 5) in the IFSR0 register, and the IFSR1j bit

(j = i - 6; i = 6 to 8) in the IFSR1 register, the corresponding IR bit may become 1 (interrupt

requested). When setting the above mentioned bits, preset bits ILVL2 to ILVL0 in the INTiIC

IR bit to 0 (no interrupt requested), then rewrite bits ILVL2 to ILVL0.

• The interrupt input signals to pins INT6 to INT8 are also connected to bits INT6R to INT8R in

registers IIO9IR to IIO11IR. Therefore, these input signals, when assigned to the intelligent I/O, can

be used as a source for exiting wait mode or stop mode. Note that these signals are enabled only

on the falling edge and not affected by the following bit settings: bits POL and LVS in the INTiIC

8) in the IFSR1 register.

R01UH0211EJ0120 Rev.1.20 Page 167 of 604

Feb 18, 2013

R32C/117 Group 12. Watchdog Timer

12. Watchdog Timer

The watchdog timer is used to detect program runaway. The 15-bit watchdog counter decrements with the

cycle which is the peripheral bus clock frequency divided by the prescaler.

Select either an interrupt request or a reset with the CM06 bit in the CM0 register for when the watchdog

timer underflows. Once the CM06 bit is set to 1 (reset), it cannot be changed to 0 (watchdog timer interrupt)

by a program. It can be set to 0 only by a reset.

The watchdog timer has a prescaler which is the peripheral bus clock divided by 16 or 128. To select the

divide ratio, set the WDC7 bit in the WDC register.

The watchdog timer is stopped in wait mode, stop mode, or when the HOLD signal is driven low. It resumes

counting from the value held when exiting the mode or state.

The general formula to calculate a watchdog timer period is:

For example, when the peripheral bus clock is 1/2 of 64 MHz CPU clock and the prescaler has a divide-by-

16 operation, the watchdog timer period is approximately 16.4 ms. Depending on the timing of when a value

is written to the WDTS register, a marginal error of one prescaler output cycle (maximum) may occur in the

watchdog timer period.

The watchdog timer is initialized when a write operation to the WDTS register is performed or when a

watchdog timer interrupt request is generated. The prescaler is initialized only when the MCU is reset.

After a reset, both the watchdog timer and the prescaler are stopped. They start counting when a write

operation to the WDTS register is performed.

Figure 12.1 shows a block diagram of the watchdog timer. Figures 12.2 and 12.3 show registers associated

with the watchdog timer.

Watchdog timer period = Prescaler divisor (16 or 128) × 32768

Peripheral bus clock frequency

----------------------------------------------------------------------------------------------------

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R32C/117 Group 12. Watchdog Timer

Figure 12.1 Watchdog Timer Block Diagram

Figure 12.2 WDC Register

Figure 12.3 WDTS Register

Prescaler

Peripheral bus clock

CM06: Bit in the CM0 register

WDC7: Bit in the WDC register

Watchdog timer

interrupt request

HOLD

Set to

7FFFh

1/16 Watchdog timer

Reset

Write to the WDTS register

RESET

WDC7

1/128

CM06 0

Watchdog Timer Control Register

FunctionBit Symbol Bit Name RW

ROUpper 5 bits of the watchdog timer (b14 to b10)

b7 b6 b5 b4 b1b2b3 b0

RWReserved

0: Divide-by-16

1: Divide-by-128

Prescaler Select Bit (1)

Symbol

WDC

Address

4404Fh

Reset Value

000X XXXXb

Should be written with 0

0 0

—

(b4-b0)

—

(b6-b5)

WDC7

Note:

1. Set this bit before activating the watchdog timer.

Watchdog Timer Start Register

Function RW

b7 b0 Symbol

WDTS

Address

4404Eh

Reset Value

Undefined

The watchdog timer is initialized by a write access. Then it starts counting

downward. Regardless of the value written to, 7FFFh is set as the default value by

writing this register

R01UH0211EJ0120 Rev.1.20 Page 169 of 604

Feb 18, 2013

R32C/117 Group 13. DMAC

13. DMAC

Direct memory access (DMA) is a system that can control data transfer without using a CPU instruction.

The R32C/100 Series’ four channel DMA controller (DMAC) transmits 8-bit (byte), 16-bit (word), or 32-bit

(long word) data in cycle-steal mode from a source address to a destination address each time a transfer

request is generated.

The DMAC, which shares a data bus with the CPU, has a higher bus access priority than the CPU. This

allows the DMAC to perform fast data transfer when a transfer request is generated.

Figure 13.1 shows a map of the CPU-internal registers associated with DMAC. Table 13.1 lists DMAC

specifications. Figures 13.2 to 13.10 show registers associated with DMAC. Since the registers shown in

Figure 13.1 are allocated in the CPU, the LDC or STC instruction should be used to write to the registers.

Figure 13.1 CPU-internal Registers for DMAC

DMAC-associated Registers

DMA1 terminal count register

DMA3 mode register

DMA0 terminal count register

DMA2 mode register

DMA1 terminal count reload register (1)

DMA3 terminal count register

DMA0 terminal count reload register (1)

DMA2 terminal count register

Note:

1. This register is used for repeat transfer, not for single transfer.

DMD2

DCT2

DCT0

DCT1

DMD3

DCT3

DMD0

DMD1

DCR2

DCR1

DCR0

DCR3

DDA3

DDA1

DDA2

DDA0

DSA3

DSA1

DSA2

DSA0

DDR0

DDR2

DDR3

DDR1

DMA1 mode register

DMA0 mode register

DMA3 destination address register

DMA1 destination address register

DMA2 destination address register

DMA0 destination address register

DMA3 source address register

DMA1 source address register

DMA2 source address register

DMA0 source address register

DMA3 terminal count reload register (1)

DMA2 terminal count reload register (1)

DMA3 destination address reload register (1)

DMA2 destination address reload register (1)

DMA1 destination address reload register (1)

DMA0 destination address reload register (1)

DSR3

DSR1

DSR2

DSR0

DMA3 source address reload register (1)

DMA1 source address reload register (1)

DMA2 source address reload register (1)

DMA0 source address reload register (1)

R01UH0211EJ0120 Rev.1.20 Page 170 of 604

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R32C/117 Group 13. DMAC

Note:

1. DMA transfer does not affect any interrupts.

Table 13.1 DMAC Specifications (i = 0 to 3)

Item Specification

Channels 4

Bus request mode Cycle-steal mode

Transfer memory spaces From a given address in a 64-Mbyte space (00000000h to

01FFFFFFh and FE000000h to FFFFFFFFh) to another given

address in the same space

Maximum transfer bytes 64-Mbytes (when 32-bit data is transferred), 32-Mbytes (when 16-bit

data is transferred), 16-Mbytes (when 8-bit data is transferred)

DMA request sources (1) Falling edge or both edges of signals applied to pins INT0 to INT3 or

pins INT6 to INT8

Interrupt requests from timers A0 to A4

Interrupt requests from timers B0 to B5

Transmit/receive interrupt requests from UART0 to UART8

A/D conversion interrupt requests

Intelligent I/O interrupt requests

Multi-master I2C-bus interrupt requests

Software trigger

Channel priority DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has the highest priority)

Transfer sizes 8 bits, 16 bits, or 32 bits

Addressing modes Incrementing addressing or non-incrementing addressing

Transfer modes Single transfer Transfer is completed when the DCTi register becomes 00000000h

Repeat transfer When the DCTi register becomes 00000000h, the value of the DCRi

transfer

DMA transfer complete interrupt

request generation timing

When the DCTi register changes from 00000001h to 00000000h

DMA transfer

start-up

Single transfer When a DMA transfer request is generated after the DCTi register is

set to a value other than 00000000h and bits MDi1 and MDi0 in the

DMDi register are set to 01b (single transfer)

Repeat transfer When a DMA transfer request is generated after the DCTi register is

set to a value other than 00000000h and bits MDi1 and MDi0 are set

to 11b (repeat transfer)

DMA transfer

stop

Single transfer When bits MDi1 and MDi0 are set to 00b (DMA transfer disabled)

Repeat transfer When bits MDi1 and MDi0 are set to 00b (DMA transfer disabled)

Reload timing to DCTi, DSAi, or

DDAi register

When the DCTi register changes from 00000001h to 00000000h in

repeat transfer mode

Minimum DMA transfer cycles 3

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R32C/117 Group 13. DMAC

The DMA transfer request is available by two different sources: software and hardware. More concretely,

they are a write access to the DSR bit in the DMiSL2 register and an interrupt request output from a function

specified in bits DSEL4 to DSEL0 in the DMiSL register, and in bits DSEL24 to DSEL20 in the DMiSL2

interrupt control register. Therefore this request can be accepted even when interrupts are disabled. Since

the DMA transfer does not affect any interrupts, either, the IR bit in the interrupt control register is not

changed by the DMA transfer.

Figure 13.2 Registers DM0SL to DM3SL

b7 b6 b5 b4 b1b2b3 Symbol

DM0SL to DM3SL

Address

44078h, 44079h, 4407Ah, 4407Bh

Reset Value

XXX0 0000b

FunctionBit Symbol Bit Name RW

DMAi Request Source Select Register (i = 0 to 3)

Note:

1. Change the bit settings of bits DSEL4 to DSEL0 while bits MDi1 and MDi0 in the DMDi register of the

corresponding channel are 00b (DMA transfer disabled).

Refer to Table 13.2 “DMiSL Register

Functions (i = 0 to 3)”

DMA Request Source

Select Bit (1)

No register bits; should be written with 0 and read as undefined

value

DSEL0

DSEL1

DSEL2

DSEL3

DSEL4

—

(b7-b5)

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R32C/117 Group 13. DMAC

Figure 13.3 Registers DM0SL2 to DM3SL2

b7 b6 b5 b4 b1b2b3 Symbol

DM0SL2 to DM3SL2

Address

44070h, 44071h, 44072h, 44073h

Reset Value

XX00 0000b

FunctionBit Symbol Bit Name RW

When a software trigger is selected,

a DMA transfer request is generated

by setting this bit to 1 (the bit is read

as 0)

Software DMA Transfer

Request Bit RW

DMAi Request Source Select Register 2 (i = 0 to 3)

No register bits; should be written with 0 and read as undefined

value

Note:

1. Change the bit settings of bits DSEL24 to DSEL20 while bits MDi1 and MDi0 in the DMDi register of the

corresponding channel are 00b (DMA transfer disabled).

Refer to Table 13.3 “DMiSL2

DMA Request Source

Select Bit (1)

DSEL20

DSEL21

DSEL22

DSEL23

DSEL24

DSR

—

(b7-b6)

R01UH0211EJ0120 Rev.1.20 Page 173 of 604
Feb 18, 2013
R32C/117 Group 13.  DMAC
Notes:
1. The falling edge and both edges of signals applied to the INTi pin become the DMA request sources
(i = 0 to 3). These request sources are not affected by external interrupts (the IFSR0 register and bits
POL and LVS in the INTiIC register), and vice versa.
2. When the INT3 pin is used as data bus in memory expansion mode or microprocessor mode, it
cannot be used as a signal input of the DMA3 request source.
3. Registers UiSMR and UiSMR2 are used to switch between the UARTi receive interrupt and ACK
interrupt (i = 0 to 6).
4. Set the I2CEN bit in the I2CMR register to select an interrupt source from either UART2 or I2C-bus.
Table 13.2 DMiSL Register Functions (i = 0 to 3)
Setting Value DMA Request Source
b4 b3 b2 b1 b0 DMA0 DMA1 DMA2 DMA3
0   0   0   0   0 Select from DMiSL2 register
0   0   0   0   1 Falling edge of INT0 (1) Falling edge of INT1 (1) Falling edge of INT2 (1) Falling edge of INT3 (1, 2)
0   0   0   1   0 Both edges of INT0 (1) Both edges of INT1 (1) Both edges of INT2 (1) Both edges of INT3 (1, 2)
0   0   0   1   1 Timer A0 interrupt request
0   0   1   0   0 Timer A1 interrupt request
0   0   1   0   1 Timer A2 interrupt request
0   0   1   1   0 Timer A3 interrupt request
0   0   1   1   1 Timer A4 interrupt request
0   1   0   0   0 Timer B0 interrupt request
0   1   0   0   1 Timer B1 interrupt request
0   1   0   1   0 Timer B2 interrupt request
0   1   0   1   1 Timer B3 interrupt request
0   1   1   0   0 Timer B4 interrupt request
0   1   1   0   1 Timer B5 interrupt request
0   1   1   1   0 UART0 transmit interrupt request
0   1   1   1   1 UART0 receive interrupt request or ACK interrupt request (3)
1   0   0   0   0 UART1 transmit interrupt request
1   0   0   0   1 UART1 receive interrupt request or ACK interrupt request (3)
1   0   0   1   0 UART2 transmit interrupt request or I2C-bus interface interrupt request (4)
1   0   0   1   1 UART2 receive interrupt request, ACK interrupt request (3), or I2C-bus line interrupt request (4)
1   0   1   0   0 UART3 transmit interrupt request UART5 transmit interrupt request
1   0   1   0   1 UART3 receive interrupt request or ACK interrupt 
request (3)
UART5 receive interrupt request or ACK interrupt 
request (3)
1   0   1   1   0 UART4 transmit interrupt request UART6 transmit interrupt request
1   0   1   1   1 UART4 receive interrupt request or ACK interrupt 
request (3)
UART6 receive interrupt request or ACK interrupt 
request (3)
1   1   0   0   0 A/D0 interrupt request
1   1   0   0   1 Intelligent I/O 
 interrupt 0 request
Intelligent I/O
 interrupt 7 request
Intelligent I/O
 interrupt 2 request
Intelligent I/O
 interrupt 9 request
1   1   0   1   0 Intelligent I/O 
 interrupt 1 request
Intelligent I/O
 interrupt 8 request
Intelligent I/O
 interrupt 3 request
Intelligent I/O
 interrupt 10 request
1   1   0   1   1 Intelligent I/O 
 interrupt 2 request
Intelligent I/O
 interrupt 9 request
Intelligent I/O
 interrupt 4 request
Intelligent I/O
 interrupt 11 request
1   1   1   0   0 Intelligent I/O
 interrupt 3 request
Intelligent I/O
 interrupt 10 request
Intelligent I/O
 interrupt 5 request
Intelligent I/O
 interrupt 0 request
1   1   1   0   1 Intelligent I/O
 interrupt 4 request
Intelligent I/O
 interrupt 11 request
Intelligent I/O
 interrupt 6 request
Intelligent I/O
 interrupt 1 request
1   1   1   1   0 Intelligent I/O
 interrupt 5 request
Intelligent I/O
 interrupt 0 request
Intelligent I/O
 interrupt 7 request
Intelligent I/O
 interrupt 2 request
1   1   1   1   1 Intelligent I/O
 interrupt 6 request
Intelligent I/O
 interrupt 1 request
Intelligent I/O
 interrupt 8 request
Intelligent I/O
 interrupt 3 request

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R32C/117 Group 13. DMAC

Note:

1. The falling edge and both edges of signals applied to the INTi pin become the DMA request sources

(i = 6 to 8). These request sources are not affected by external interrupts (the IFSR1 register and bits

POL and LVS in the INTiIC register), and vice versa.

Table 13.3 DMiSL2 Register Functions (i = 0 to 3)

Setting Value DMA Request Source

b4 b3 b2 b1 b0 DMA0 DMA1 DMA2 DMA3

0 0 0 0 0 Software trigger

0 0 0 0 1 Falling edge of INT6 (1) Falling edge of INT7 (1) Falling edge of INT8 (1) Reserved

0 0 0 1 0 Both edges of INT6 (1) Both edges of INT7 (1) Both edges of INT8 (1) Reserved

0 0 0 1 1 Reserved

0 0 1 0 0 Reserved

0 0 1 0 1 Reserved

0 0 1 1 0 Reserved

0 0 1 1 1 Reserved

0 1 0 0 0 Reserved

0 1 0 0 1 Reserved

0 1 0 1 0 Reserved

0 1 0 1 1 Reserved

0 1 1 0 0 Reserved

0 1 1 0 1 Reserved

0 1 1 1 0 Reserved

0 1 1 1 1 Reserved

1 0 0 0 0 Reserved

1 0 0 0 1 Reserved

1 0 0 1 0 Reserved

1 0 0 1 1 Reserved

1 0 1 0 0 Reserved

1 0 1 0 1 Reserved

1 0 1 1 0 Reserved

1 0 1 1 1 Reserved

1 1 0 0 0 UART7 transmit interrupt request

1 1 0 0 1 UART7 receive interrupt request

1 1 0 1 0 UART8 transmit interrupt request

1 1 0 1 1 UART8 receive interrupt request

1 1 1 0 0 Reserved

1 1 1 0 1 Reserved

1 1 1 1 0 Reserved

1 1 1 1 1 Reserved

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R32C/117 Group 13. DMAC

Figure 13.4 Registers DMD0 to DMD3

Figure 13.5 Registers DCT0 to DCT3

DMAi Mode Register (i = 0 to 3) (1)

b7 b6 b5 b4 b1b2b3 b0

Symbol

DMD0 to DMD3

Address

(CPU internal register)

Reset Value

XXXX XXXX XXXX XXXX XXXX XXXX XX00 0000b

FunctionBit Symbol Bit Name RW

Transfer Mode Select Bit (2)

b1 b0

0 0 : DMA transfer disabled

0 1 : Single transfer

1 0 : Do not use this combination

1 1 : Repeat transfer

Transfer Size Select Bit (3)

b3 b2

00:8 bits

0 1 : 16 bits

1 0 : 32 bits

1 1 : Do not use this combination

0: Non-incrementing addressing

1: Incrementing addressing

Source Addressing Mode

Select Bit (3)

0: Non-incrementing addressing

1: Incrementing addressing

Destination Addressing

Mode Select Bit (3)

Notes:

1. Use the LDC instruction to write to this register.

2. Set these bits after all other DMAC-associated registers are set.

3. Set bits MDi1 and MDi0 to 00b before rewriting these bits.

b31 b24 b23 b16 b15 b8 b7 b0

—

No register bits; should be written with 0 and read as undefined

value

No register bits; should be written with 0 and read as undefined

value

MDi0

MDi1

BWi0

BWi1

USAi

UDAi

—

(b7-b6)

—

(b31-b8)

b31 b0b24 b23

DMAi Terminal Count Register (i = 0 to 3) (1)

Symbol

DCT0 to DCT3

Address

(CPU internal register)

Reset Value

XXXX XXXXh

Setting RangeFunction RW

RW000000h to FFFFFFh (2)

Notes:

1. Use the LDC instruction to write to this register. Set this register while bits MDi1 and MDi0 in the DMDi

2. When these bits are set to 000000h, new DMA transfer requests cannot be accepted.

b16 b15 b8 b7

RWShould be set to 00hReserved

Set the number of transfers to be performed

00000000

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R32C/117 Group 13. DMAC

Figure 13.6 Registers DCR0 to DCR3

Figure 13.7 Registers DSA0 to DSA3

DMAi Terminal Count Reload Register (i = 0 to 3) (1)

Symbol

DCR0 to DCR3

Address

(CPU internal register)

Reset Value

XXXX XXXXh

Note:

1. Use the LDC instruction to write to this register. Set this register while bits MDi1 and MDi0 in the DMDi

b31 b0b24 b23 b16 b15 b8 b7

Setting RangeFunction RW

RW000000h to FFFFFFh

RWShould be set to 00hReserved

Set the number of transfers to be performed

00000000

DMAi Source Address Register (i = 0 to 3) (1)

Symbol

DSA0 to DSA3

Address

(CPU internal register)

Reset Value

XXXX XXXXh

Note:

1. Use the LDC instruction to write to this register. Set this register while bits MDi1 and MDi0 in the DMDi

b31 b0b24 b23 b16 b15 b8 b7

Setting RangeFunction RW

00000000h to 01FFFFFFh

and

FE000000h to FFFFFFFFh

(64-Mbyte space)

Set a source address

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R32C/117 Group 13. DMAC

Figure 13.8 Registers DSR0 to DSR3

Figure 13.9 Registers DDA0 to DDA3

Figure 13.10 Registers DDR0 to DDR3

DMAi Source Address Reload Register (i = 0 to 3) (1)

Symbol

DSR0 to DSR3

Address

(CPU internal register)

Reset Value

XXXX XXXXh

Note:

1. Use the LDC instruction to write to this register. Set this register while bits MDi1 and MDi0 in the DMDi

b31 b0b24 b23 b16 b15 b8 b7

Setting RangeFunction RW

00000000h to 01FFFFFFh

and

FE000000h to FFFFFFFFh

(64-Mbyte space)

Set a source address

DMAi Destination Address Register (i = 0 to 3) (1)

Symbol

DDA0 to DDA3

Address

(CPU internal register)

Reset Value

XXXX XXXXh

Note:

1. Use the LDC instruction to write to this register. Set this register while bits MDi1 and MDi0 in the DMDi

b31 b0b24 b23 b16 b15 b8 b7

Setting RangeFunction RW

00000000h to 01FFFFFFh

and

FE000000h to FFFFFFFFh

(64-Mbyte space)

Set a destination address

DMAi Destination Address Reload Register (i = 0 to 3) (1)

Symbol

DDR0 to DDR3

Address

(CPU internal register)

Reset Value

XXXX XXXXh

Note:

1. Use the LDC instruction to write to this register. Set this register while bits MDi1 and MDi0 in the DMDi

b31 b0b24 b23 b16 b15 b8 b7

Setting RangeFunction RW

00000000h to 01FFFFFFh

and

FE000000h to FFFFFFFFh

(64-Mbyte space)

Set a destination address

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R32C/117 Group 13. DMAC

13.1 Transfer Cycle

The transfer cycle is composed of bus cycles to read data from (source read) or to write data to

(destination write) memory or an SFR.

The read and write bus cycles vary with the setting of registers DSAi and DDAi, the width and timing of

the data bus connected to the relevant device (i = 0 to 3).

13.1.1 Effect of Transfer Address and Data Bus Width

Table 13.4 lists the incremental bus cycles caused by transfer address alignment or data bus width.

Table 13.4 Incremental Bus Cycles Caused by Transfer Address and Data Bus Width

Transfer Data

Unit

Data Bus

Width

Transfer

Address

Bus Cycles to be

Incremented Bus Cycles Generated

8-bit transfer 8 to 64 bits n 0 [n]

16-bit transfer

8 bits n +1 [n] - [n + 1]

16 bits 2n 0 [2n]

2n + 1 +1 [2n + 1] - [2n + 2]

32 bits

4n 0 [4n]

4n + 1 0 [4n + 1]

4n + 2 0 [4n + 2]

4n + 3 +1 [4n + 3] - [4n + 4]

64 bits

8n 0 [8n]

8n + 1 0 [8n + 1]

8n + 2 0 [8n + 2]

8n + 3 0 [8n + 3]

8n + 4 0 [8n + 4]

8n + 5 0 [8n + 5]

8n + 6 0 [8n + 6]

8n + 7 +1 [8n + 7] - [8n + 8]

32-bit transfer

8 bits n +3 [n] - [n + 1] - [n + 2] - [n + 3]

16 bits

4n +1 [4n] - [4n + 2]

4n + 1 +2 [4n + 1] - [4n + 2] - [4n + 4]

4n + 2 +1 [4n + 2] - [4n + 4]

4n + 3 +2 [4n + 3] - [4n + 4] - [4n + 6]

32 bits

4n 0 [4n]

4n + 1 +1 [4n + 1] - [4n + 4]

4n + 2 +1 [4n + 2] - [4n + 4]

4n + 3 +1 [4n + 3] - [4n + 4]

64 bits

8n 0 [8n]

8n + 1 0 [8n + 1]

8n + 2 0 [8n + 2]

8n + 3 0 [8n + 3]

8n + 4 0 [8n + 4]

8n + 5 +1 [8n + 5] - [8n + 8]

8n + 6 +1 [8n + 6] - [8n + 8]

8n + 7 +1 [8n + 7] - [8n + 8]

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13.1.2 Effect of Bus Timing
In the R32C/100 Series, a separate bus is connected to each device. The bus width and bus timing
vary with each device. Table 13.5 lists the bus width and access cycles for each device.
Notes:
1. Reserved spaces are included.
2. Access cycles are based on each bus clock.
3. An access to the same page as the previous time requires two cycles. Otherwise, three cycles are
required.
4. If write cycles are generated sequentially, each write cycle except the initial one has two access
cycles. A read cycle just after a write cycle has also two access cycles.
5. If SFRs are sequentially accessed, each access except the initial one has one additional base clock
cycle.
6. Up to one access cycle may be added depending on the phase of peripheral bus clock.
Figure 13.11 shows an example of source-read bus cycles in a transfer cycle. In this figure, the number
of source-read bus cycles is shown under different conditions, provided that the destination address is
in an internal RAM with one bus cycle of destination-write. In a real operation, the transfer cycles
change according to conditions for destination-write bus cycles as well as for source-read bus cycles.
To calculate a transfer cycle, respective conditions should be applied to both destination-write bus cycle
and source-read bus cycle. In (B) of Figure 13.11, for example, if two bus cycles are generated, bus
cycles required for the destination-write is two as well as for the source-read.
13.1.3 Effect of RDY Signal
In memory expansion mode or microprocessor mode, the RDY signal affects a bus cycle in an external
space. Refer to 9.3.7 “RDY Signal” for details.
Table 13.5 Bus Width and Bus Cycles
Device Addresses (1) Bus Width Access Cycles (2) Reference Clock
Flash memory FFE00000h to FFFFFFFFh 64-bit 2 or 3 (3) CPU clock
Data flash 00060000h to 00061FFFh 64-bit 5 CPU clock
RAM 00000400h to 0003FFFFh 64-bit 1 or 2 (4) CPU clock
SFR space 00000000h to 0000001Fh 16-bit 3 (5) Peripheral bus clock
00000020h to 000003FFh 16-bit 2 (5) Peripheral bus clock
SFR2 space 00040000h to 00041FFFh 16-bit 2 (5) Peripheral bus clock
00042000h to 00043FFFh 32-bit 2 (5) Peripheral bus clock
00044000h to 000440DFh 16-bit 2 (5,  6) Peripheral bus clock
000440E0h to 000443FFh 16-bit 3 (5,  6) Peripheral bus clock
00044400h to 00045FFFh 16-bit 2 (5,  6) Peripheral bus clock
00046000h to 000467FFh 32-bit 3 (5,  6) Peripheral bus clock
00046800h to 00047FFFh 32-bit 2 (5,  6) Peripheral bus clock
00048000h to 0004FFFFh 64-bit 2 CPU clock
External bus 00080000h to 01FFFFFFh
FE000000h to FFDFFFFFh 8-/16-/32-bit
Specified by the 
EBCn register 
(n = 0 to 3) (5)
Peripheral bus clock

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R32C/117 Group 13. DMAC

Figure 13.11 Source-read Bus Cycles in a Transfer Cycle

(A) One bus cycle of source-read is generated

Example: 16-bit data transfer from address 8n in the RAM

CPU clock

CPU address bus

CPU data bus

(B) Two bus cycles of source-read are generated

Example: 16-bit data transfer from address 8n+7 in the RAM

Example: 16-bit data transfer from address 16n in the ROM

(D) Two bus cycles of source-read is generated with one wait cycle

Example: 16-bit data transfer from address 16n+7 in the ROM

Note:

1. The above assumes that destination-write completes in one bus cycle. In actual use, the number of

destination-write bus cycles should be considered according to the conditions such as above.

CPU in operation DSA DDA CPU in operation

CPU in operation [DSA] [DDA] CPU in operation

CPU RD signal

CPU WR signal

CPU clock

CPU address bus

CPU data bus

CPU in operation DSA DDA CPU in operation

CPU in operation [DSA] [DDA] CPU in operation

CPU RD signal

CPU WR signal

DSA+1

[DSA+1]

CPU clock

CPU address bus

CPU data bus

CPU in operation DSA DDA CPU in operation

CPU in operation [DSA] [DDA] CPU in operation

CPU RD signal

CPU WR signal

CPU clock

CPU address bus

CPU data bus

CPU in operation DSA DDA CPU in operation

CPU in operation [DSA] [DDA] CPU in operation

CPU RD signal

CPU WR signal

DSA+1

[DSA+1]

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13.2 DMA Transfer Cycle

The DMA transfer cycles are calculated as follows:

where:

j = access cycles for read

k = access cycles for write (refer to Table 13.5)

Each bus cycle, source-read and destination-write, requires at least one cycle. In addition, more cycles

may be required depending on the transfer address. Refer to Table 13.4 for details on the required bus

cycles.

“+1” in the formula above means a cycle required to decrement the value of DCTi register (i = 0 to 3).

The following are calculation examples:

To transfer 32-bit data from address 400h in the RAM to address 800h in the RAM,

Thus, there are three cycles.

To transfer 16-bit data from the AD00 register at address 380h to registers P1 and P0 at addresses 3C1h

and 3C0h, respectively, when the peripheral bus clock frequency is half the CPU clock,

Thus, there are nine cycles.

Number of transfer cycles Source-read bus cycles jDestination-write bus cycles k1++=

Number of the transfer cycles 11111++=

Number of the transfer cycles 122 122 1++=

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13.3 Channel Priority and DMA Transfer Timing

When multiple DMA transfer requests are generated in the same sampling period, between the falling

edge of the CPU clock and the next falling edge, these requests are simultaneously input into the DMAC.

Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3.

Figure 13.12 shows an example of the DMA transfer by external source, specifically when DMA0 and

DMA1 requests are simultaneously generated. The DMA0, whose request priority is higher than that of

DMA1, is received first to start the transfer and then hands over the bus to the CPU after completing one

DMA0 transfer. Once the CPU completes one bus access, the DMA1 transfer starts. The CPU takes the

bus back from the DMA1 after one DMA1 transfer is completed.

DMA transfer requests cannot be counted. Only a single transfer is performed even when an INTi

interrupt occurs more than once before the bus is granted, as shown by DMA1 in Figure 13.12.

Figure 13.12 DMA Transfer by External Source

When DMA request signals by external source are applied to INT0 and INT1 simultaneously, and a DMA transfer with the

minimum number of cycles occurs

CPU clock

DMA0

DMA1

CPU

INT0

DMA0 transfer

request

INT1

DMA1 transfer

request

Bus mastership

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13.4 Notes on DMAC

13.4.1 DMAC-associated Register Settings

• Set DMAC-associated registers while bits MDi1 and MDi0 in the DMDi register are 00b (DMA

transfer disabled) (i = 0 to 3). Then, set bits MDi1 and MDi0 to 01b (single transfer) or 11b (repeat

transfer) at the end of the setup procedure. This procedure also applies when rewriting bits UDAi,

USAi, and BWi1 and BWi0 in the DMDi register.

• When rewriting the DMAC-associated registers while DMA transfer is enabled, stop the peripherals

that can be DMA triggers so that no DMA transfer request is generated, then set bits MDi1 and

MDi0 in the DMDi register of the corresponding channel to 00b (DMA transfer disabled).

• Once a DMA transfer request is accepted, DMA transfer cannot be disabled even if setting bits

MDi1 and MDi0 in the DMDi register to 00b (DMA transfer disabled). Do not change the settings of

any DMAC-associated registers other than bits MDi1 and MDi0 until the DMA transfer is

completed.

• After setting registers DMiSL and DMiSL2, wait at least six peripheral bus clocks to set bits MDi1

and MDi0 in the DMDi register to 01b (single transfer) or 11b (repeat transfer).

13.4.2 Reading DMAC-associated Registers

• Use the following read order to sequentially read registers DMiSL and DMiSL2:

DM0SL, DM1SL, DM2SL, and DM3SL

DM0SL2, DM1SL2, DM2SL2, and DM3SL2

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R32C/117 Group 14. DMAC II

14. DMAC II

DMAC II starts by an interrupt request from any peripheral and performs data transfer without a CPU

instruction. Transfer sources are selectable from memory, immediate data, memory + memory, and

immediate data + memory.

Table 14.1 lists specifications of DMAC II.

Note:

1. When the transfer size is 16 bits and the destination address is FFFFFFFFh, data is transferred to

FFFFFFFFh and 00000000h. This also applies when the source address is FFFFFFFFh.

14.1 DMAC II Settings

To use DMAC II, set the following:

• Registers RIPL1 and RIPL2

•DMAC II index

• Interrupt control registers of the peripherals that trigger DMAC II

• Relocatable vectors of the peripherals that trigger DMAC II

• The IRLT bit in the IIOiIE register when using the intelligent I/O interrupt (i = 0 to 11). Refer to 11.

“Interrupts” for details on the IIOilE register.

Table 14.1 DMAC II Specifications

Item Specification

DMAC II request sources Interrupt requests from the peripherals of which bits ILVL2 to ILVL0 in the

corresponding interrupt control register are set to 111b (level 7)

Transfer types • Data in memory is transferred to memory (memory-to-memory transfer)

• Immediate data is transferred to memory (immediate data transfer)

• Data in memory + data in memory are transferred to memory (calculation

result transfer)

• Immediate data + data in memory are transferred to memory (calculation result

transfer)

Transfer sizes 8 bits or 16 bits

Transfer memory spaces From a given address in a 64-Mbyte space (00000000h to 01FFFFFFh and

FE000000h to FFFFFFFFh) to another given address in the same space (1)

Addressing modes Individually selectable for each source address and destination address from the

following two modes:

• Non-incrementing addressing: Address is held constant throughout a data

transfer/DMA II transaction

• Incrementing addressing: Address increments by 1 (when 8-bit data is

transferred) or 2 (when 16-bit data is transferred) after each data transfer

Transfer modes • Single transfer: Only one data transfer is performed by one transfer request

• Burst transfer: Data transfers are continuously performed for the number of

times set in the transfer counter by one transfer request

• Multiple transfer: Multiple memory-to-memory transfers are performed from

different source addresses to different destination addresses by one transfer

request

Chain transfer Data transfer is sequentially performed by switching among multiple DMAC II

indexes (transfer information)

DMA II transfer complete

interrupt request

An interrupt request is generated when the transfer counter reaches 0000h

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14.1.1 Registers RIPL1 and RIPL2

When the DMAII bit in registers RIPL1 and RIPL2 is set to 1 (DMA II transfer selected) and the FSIT bit

is set to 0 (normal interrupt selected), DMAC II starts by an interrupt request from any peripheral whose

bits ILVL2 to ILVL0 in the corresponding interrupt control register are set to 111b (level 7).

Figure 14.1 shows registers RIPL1 and RIPL2.

Figure 14.1 Registers RIPL1 and RIPL2

Wake-up IPL Setting Register i (i = 1, 2) (1)

Symbol

RIPL1, RIPL2

Address

4407Fh, 4407Dh

Reset Value

XX0X 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Interrupt Priority Level for

Wake-up Select Bit (2)

b2 b1 b0

000:Level 0

001:Level 1

010:Level 2

011:Level 3

100:Level 4

101:Level 5

110:Level 6

111:Level 7

0: Use interrupt request level 7 for

normal interrupt

1: Use interrupt request level 7 for

fast interrupt (4)

Fast Interrupt Select Bit (3)

—

0: Use interrupt request level 7 for

interrupt

1: Use interrupt request level 7 for

DMA II transfer (4)

DMA II Select Bit (5)

—

Notes:

1. Registers RIPL1 and RIPL2 should be set with the same values.

2. The MCU exits wait mode or stop mode when the request level of the requested interrupt is higher than the

level selected using bits RLVL2 to RLVL0. Set these bits to the same value as the IPL in the FLG register.

3. When the FSIT bit is 1, an interrupt with interrupt request level 7 becomes the fast interrupt. In this case, set

the interrupt request level to level 7 with only one interrupt.

4. Set either the FSIT or DMAII bit to 1. The fast interrupt and DMAC II cannot be used simultaneously.

5. Set bits ILVL2 to ILVL0 in the interrupt control register after the DMAII bit is set. DMA II transfer is not

affected by the I flag or IPL.

No register bits; should be written with 0 and read as undefined

value

No register bit; should be written with 0 and read as undefined

value

RLVL0

RLVL1

RLVL2

FSIT

—

(b4)

DMAII

—

(b7-b6)

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14.1.2 DMAC II Index

The DMAC II index is a data table of 12 to 60 bytes. It stores parameters for transfer mode, transfer

counter, source address (or immediate data), operation address as an address to be calculated,

destination address, chain transfer base address, and jump address for the DMA II transfer complete

interrupt handler.

This DMAC II index should be allocated on the RAM.

Figure 14.2 shows a configuration of the DMAC II index and Table 14.2 lists a configuration example of

the DMAC II index.

Figure 14.2 DMAC II Index

Multiple transfer

Memory-to-memory transfer,

Immediate transfer, Calculation transfer

BASE + 12

BASE + 4

BASE + 8

BASE + 2

BASE + 20

BASE + 16

16 bits

Notes:

1. This data is required only for the calculation transfer.

2. This data is required only for the chain transfer.

3. This data is required only for the DMA II transfer complete interrupt.

BASE + 4

BASE + 2

BASE

16 bits

The DMAC II index should be allocated on the RAM. Required data should be set front-aligned. For example, when the

calculation transfer is not used, the destination address should be set to BASE + 8 (refer to the “DMAC II Index

Configuration” on the next page).

Start address of the DMAC II index should be set in the interrupt vector space for the peripheral interrupt triggering DMAC II.

Transfer mode (MOD)

Source address (SADR2)

Source address (SADR1)

Destination address (DADR1)

Transfer counter (COUNT)

Destination address (DADR7)

Source address (SADR7)

Destination address (DADR2)

BASE + 8

BASE + 12

BASE + 16

BASE + 52

BASE + 56

DMAC II index start

address (BASE) Transfer mode

Destination address

Source address

(or immediate data)

Operation address (1)

Transfer counter

Jump address for the DMA II

transfer complete interrupt

handler (3)

Chain transfer base address

(2)

(SADR)

(OADR)

(DADR)

(CADR)

(IADR)

(COUNT)

(MOD)

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The following are the details on the DMAC II index. These parameters should be aligned in the order

listed in Table 14.2 according to the transfer mode to be used.

• Transfer mode (MOD)

Set a transfer mode in 2 bytes. Refer to Figure 14.3 for details on the setting of MOD.

• Transfer counter (COUNT)

Set a number of transfers in 2 bytes.

• Source address (SADR)

Set a source address or immediate data in 4 bytes. Note that the two upper bytes of immediate

data are ignored.

• Operation address (OADR)

Set an address in a to-be calculated memory in 4 bytes. This data setting is required only for the

calculation transfer.

• Destination address (DADR)

Set a destination address in 4 bytes.

• Chain transfer base address (CADR)

Set the start address of the DMAC II index for the next transfer (BASE) in 4 bytes. This data setting

is required only for the chain transfer.

• Jump address for the DMA II transfer complete interrupt handler (IADR)

Set the start address for the DMA II transfer complete interrupt handler in 4 bytes. This data setting

is required only for the DMA II transfer complete interrupt.

The symbols above are hereinafter used in place of their respective parameters.

Table 14.2 DMAC II Index Configuration

Transfer

Data

Memory-to-memory Transfer/

Immediate Data Transfer Calculation Transfer Multiple

Transfer

Chain

transfer Not used Used Not used Used Not used Used Not used Used Not

available

DMA II

transfer

complete

interrupt

Not used Not used Used Used Not used Not used Used Used Not

available

DMAC II

index

MOD

COUNT

SADR

DADR

12 bytes

MOD

COUNT

SADR

DADR

CADR

16 bytes

MOD

COUNT

SADR

DADR

IADR

16 bytes

MOD

COUNT

SADR

DADR

CADR

IADR

20 bytes

MOD

COUNT

SADR

OADR

DADR

16 bytes

MOD

COUNT

SADR

DADR

CADR

20 bytes

OADR

MOD

COUNT

SADR

DADR

IADR

20 bytes

OADR

MOD

COUNT

SADR

DADR

CADR

24 bytes

OADR

IADR

MOD

COUNT

SADR1

DADR1

i = 1 to 7

max. 60

bytes

(when i = 7)

SADRi

DADRi

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Figure 14.3 MOD

Transfer Mode (MOD) (1)

Note:

1. The MOD should be allocated on the RAM.

When multiple transfer is not selected (MULT = 0)

When multiple transfer is selected (MULT = 1)

FunctionBit Symbol Bit Name RW

Transfer Size Select BitSIZE 0: 8 bits

1: 16 bits RW

IMM Transfer Source Select Bit 0: Immediate data

1: Memory RW

UPDS Source Addressing Select

Bit

0: Non-incrementing addressing

1: Incrementing addressing RW

UPDD Destination Addressing

Select Bit

0: Non-incrementing addressing

1: Incrementing addressing RW

OPER Calculation Result Transfer

Select Bit

0: Not used

1: Used RW

BRST Burst Transfer Select Bit 0: Single transfer

1: Burst transfer RW

INTE DMA II Transfer Complete

Interrupt Select Bit

0: Not used

1: Used

CHAIN Chain Transfer Select Bit 0: Not used

1: Used

—

(b14-b8) Reserved Should be written with 0 RW

MULT Multiple Transfer Select Bit 0: Not used RW

0 0 0 0 0 0 0 0

b15 b8 b7 b0

FunctionBit Symbol Bit Name RW

Transfer Size Select BitSIZE 0: 8 bits

1: 16 bits RW

IMM RW

UPDS Source Addressing Select

Bit

0: Non-incrementing addressing

1: Incrementing addressing RW

UPDD Destination Addressing

Select Bit

0: Non-incrementing addressing

1: Incrementing addressing RW

CNT0

Number of Transfers

Setting Bit

CNT1 RW

CNT2

CHAIN

—

(b14-b8) Reserved Should be written with 0 RW

MULT Multiple Transfer Select Bit 1: Used RW

1 0 0 0 0 0 0 0 0 1

b15 b8 b7 b0

Reserved Should be written with 1

b6 b5 b4

0 0 0 : Do not use this combination

001:Once

010:Twice

111:Seven times

Reserved Should be written with 0

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14.1.3 Interrupt Control Register of the Peripherals

Set bits ILVL2 to ILVL0 in the interrupt control register for the peripheral interrupt triggering DMAC II to

111b (level 7).

14.1.4 Relocatable Vector Table of the Peripherals

Set the start address of the DMAC II index in the interrupt vector space for the peripheral interrupt

triggering DMAC II.

To use the chain transfer, allocate the relocatable vector table on the RAM.

14.1.5 IRLT Bit in the IIOiIE Register (i = 0 to 11)

To use the intelligent I/O interrupt as a trigger for DMAC II, set the IRLT bit in the corresponding IIOilE

14.2 DMAC II Operation

Set the DMAII bit in registers RIPL1 and RIPL2 to 1 (interrupt request level 7 used for DMA II transfer) to

perform a DMA II transfer. DMAC II starts by an interrupt request from any peripheral whose bits ILVL2 to

ILVL0 in the corresponding interrupt control register are set to 111b (level 7). These peripheral interrupt

requests are available only for DMA II transfer and cannot be used for the CPU.

When an interrupt request is generated with interrupt request level 7, DMAC II starts irrespective of the

state of the I flag or IPL.

When a peripheral interrupt request triggering DMAC II and a higher-priority request such as the

watchdog timer interrupt, low voltage detection interrupt, oscillator stop detection interrupt, or NMI are

simultaneously generated, the higher-priority interrupt is accepted prior to the DMA II transfer, and the

DMA II transfer starts after the higher-priority interrupt sequence.

14.3 Transfer Types

DMAC II transfers three types of 8-bit or 16-bit data as follows:

• Memory-to-memory transfer: Data is transferred from a given memory location in a 64-Mbyte space

(addresses 00000000h to 01FFFFFFh and FE000000h to

FFFFFFFFh) to another given memory location in the same space.

• Immediate data transfer: Immediate data is transferred to a given memory location in a 64-

Mbyte space.

• Calculation transfer: Two data are added together and the result is transferred to a given

memory location in a 64-Kbyte space.

When 16-bit data is transferred to DADR at FFFFFFFFh, it is transferred to 00000000h as well as

FFFFFFFFh. The same transfer is performed when SADR is FFFFFFFFh.

14.3.1 Memory-to-memory Transfer

Data transfer between any two memory locations can be:

• A transfer from a fixed address to another fixed address

• A transfer from a fixed address to an address range in memory

• A transfer from an address range in memory to a fixed address

• A transfer from an address range in memory to another address range in memory

When increment addressing mode is selected, SADR and DADR increment by 1 in an 8-bit transfer and

by 2 in a 16-bit transfer after a data transfer for the next transfer. When SADR or DADR exceeds

FFFFFFFFh by the incrementation, it returns to 00000000h. Likewise, when SADR or DADR exceeds

01FFFFFFh, it becomes 02000000h, but an actual transfer is performed for FE000000h.

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14.3.2 Immediate Data Transfer

DMAC II transfers immediate data to a given memory location. Either incrementing or non-incrementing

addressing mode can be selected for the destination address. Store the immediate data to be

transferred into SADR. To transfer 8-bit immediate data, set the data to the lower 1 byte of SADR. The

upper 3 bytes are ignored. To transfer 16-bit immediate data, set the data to the lower 2 bytes. The

upper 2 bytes are ignored.

14.3.3 Calculation Result Transfer

After two memory data or immediate data and memory data are added together, DMAC II transfers the

calculated result to a given memory location. Set an address to be calculated or immediate data to

SADR and set the other address to be calculated to OADR. Either incrementing or non-incrementing

addressing mode can be selected for source and destination addresses when performing data in

memory + data in memory calculation transfer. If the source addressing is in incrementing mode, the

operation addressing is also in incrementing mode. When performing immediate data + data in memory

calculation transfer, the addressing mode is selectable only for the destination address.

14.4 Transfer Modes

DMAC II provides three types of basic transfer mode: single transfer, burst transfer, and multiple transfer.

COUNT determines the number of transfers to be performed. Transfers are not performed when COUNT

is 0000h.

14.4.1 Single Transfer

Set the BRST bit in the MOD to 0.

A single data transfer is performed by one transfer request.

When incrementing addressing mode is selected for the source and/or destination address, the

address or addresses increment after a data transfer for the next transfer.

COUNT is decremented each time a data transfer is performed. When COUNT reaches 0000h, the

DMA II transfer complete interrupt request is generated if the INTE bit in the MOD is 1 (DMA II transfer

complete interrupt used).

14.4.2 Burst Transfer

Set the BRST bit in the MOD to 1.

DMAC II continuously transfers data for the number of times determined by COUNT with one transfer

request. COUNT decrements each time a data transfer is performed. When COUNT reaches 0000h,

the burst transfer is completed. The DMA II transfer complete interrupt request is generated if the INTE

bit is 1 (DMA II transfer complete interrupt used).

No interrupts are accepted during a burst transfer.

14.4.3 Multiple Transfer

Set the MULT bit in the MOD to 1.

Multiple memory-to-memory transfers are performed from different source addresses to different

destination addresses using one transfer request.

Set bits CNT2 to CNT0 in the MOD to select the number of transfers to be performed from 001b (once)

to 111b (seven times). Do not set these bits to 000b.

Allocate the required number of SDARs and DADRs alternately following MOD and COUNT.

When the multiple transfer is selected, the following transfer functions are not available: calculation

result transfer, burst transfer, chain transfer, and DMA II transfer complete interrupt.

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R32C/117 Group 14. DMAC II

14.5 Chain Transfer

The chain transfer is available when the CHAIN bit in the MOD is 1.

The chain transfer is performed as follows:

(1) When a transfer request is generated, a data transfer is performed according to the DMAC II

index specified by the corresponding interrupt vector. Either a single transfer (the BRST bit in the

MOD is 0) or burst transfer (the BRST bit is 1) is performed according to the BRST bit setting.

(2) When COUNT reaches 0000h, the value in the interrupt vector in (1) above is overwritten with

the value in CADR. Simultaneously, the DMA II transfer complete interrupt request is generated

when the INTE bit in the MOD is 1.

(3) When the next DMA II transfer request is generated, the data transfer is performed according to

the DMAC II index specified by the peripheral interrupt vector in (2) above.

Figure 14.4 shows the relocatable vector and DMAC II index in a chain transfer.

To use the chain transfer, the relocatable vector table should be allocated on the RAM.

Figure 14.4 Relocatable Vector and DMAC II Index in a Chain Transfer

14.6 DMA II Transfer Complete Interrupt

The DMA II transfer complete interrupt is available when the INTE bit in the MOD is 1.

Set the start address of the DMA II transfer complete interrupt handler to IADR. The interrupt request is

generated when COUNT reaches 0000h.

The initial instruction of the interrupt handler is executed in the eighth cycle after a DMA II transfer is

completed.

BASE(a)

DMAC II

index (b)

INTB

DMAC II

index (a)

(CADR)

BASE(b)

(CADR)

Relocatable

vector

RAM

Peripheral interrupt vector triggering DMAC II

Default value of DMAC II: BASE(a)

BASE(b)

BASE(c)

The above vector is overwritten with BASE(b)

when a data transfer is completed

The next data transfer is performed according to

DMAC II index with the start address at BASE(b)

when a new transfer request is generated

The above vector is overwritten with BASE(c)

when the data transfer above is completed

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R32C/117 Group 14. DMAC II

14.7 Execution Time

The DMAC II execution cycle is calculated by the following equations:

Mode other than multiple transfer: t = 6 + (26 + a + b + c + d) × m + (4 + e) × n cycles

When using multiple transfer: t = 21 + (11 + b + c) × k cycles

a: When IMM is 0 (transfer source is immediate data), a is 0;

When IMM is 1 (transfer source is memory), a is -1

b: When UPDS is 1 (source addressing is incrementing), b is 0;

When UPDS is 0 (source addressing is non-incrementing), b is 1

c: When UPDD is 1 (destination addressing is incrementing), c is 0;

When UPDD is 0 (destination addressing is non-incrementing), c is 1

d: When OPER is 0 (calculation transfer is not selected), d is 0;

When OPER is 1 (calculation transfer is selected) and UPDS is 0 (source addressing is

immediate data or non-incrementing), d is 7;

When OPER is 1 (calculation transfer is selected) and UPDS is 1 (source addressing is

incrementing), d is 8

e: When CHAIN is 0 (chain transfer is not selected), e is 0;

When CHAIN is 1 (chain transfer is selected), e is 4

m: When BRST is 0 (single transfer), m is 1;

When BRST is 1 (burst transfer), m is COUNT

n: When COUNT is 0001h, n is 0; if COUNT is 0002h or more, n is 1

k: The number of transfers set using bits CNT2 to CNT0

The equations above are estimations. The number of cycles may vary depending on CPU state, bus wait

state, and DMAC II index allocation.

Figure 14.5 Transfer Cycles

Transfer counter = 2

Transfer counter decrements

Transfer counter = 1

7 cycles

DMA II transfer request

(a = -1, b = 0, c = 1, d = 0, e = 0, m = 1)

Program

First DMA II transfer t = 6 + (26 - 1 + 0 + 1 + 0) × 1 + (4 + 0) × 1 = 36 cycles

Second DMA II transfer t = 6 + (26 - 1 + 0 + 1 + 0) × 1 + (4 + 0) × 0 = 32 cycles

DMA II transfer request

DMA II transfer

(first time)

DMA II transfer complete

interrupt processing

32 cycles

Program

Transfer counter = 1

Transfer counter decrements

Transfer counter = 0

DMA II transfer

(second time)

36 cycles

The figure below applies under the following conditions:

memory-to-memory transfer; incrementing source address; non-incrementing

destination address; number of transfers = 2; single transfer mode; using a transfer

complete interrupt (transfer counter = 2); no chain transfer

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R32C/117 Group 15. Programmable I/O Ports

15. Programmable I/O Ports

The programmable I/O ports in each pin package are designated as follows:

100-pin package: 84 ports from P0 to P10 (excluding P8_5 and P9_0 to P9_2)

144-pin package: 120 ports from P0 to P15 (excluding P8_5, and P14_0 to P14_2)

Each port status, input or output, can be selected using the direction register except P8_5 and P9_1/P14_1

which are input only. The P8_5 bit in the P8 register indicates an NMI input level since the P8_5 shares a

pin with the NMI.

Figure 15.1 shows a configuration of programmable I/O ports, and Figures 15.2 to 15.4 show a configuration

of each input-only port.

Figure 15.1 Programmable I/O Port Configuration

Port latch

Direction register

Port read signal

Function selector

(See Note 1)

Note:

1. Refer to 26. “I/O Pins” for details on the area enclosed with the dotted line above.

Data bus

Function select

registers PSEL2 to PSEL0 = 000b

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R32C/117 Group 15. Programmable I/O Ports

Figure 15.2 Input-only Port Configuration (1/3)

Figure 15.3 Input-only Port Configuration (2/3) (in the 100-pin package only)

Figure 15.4 Input-only Port Configuration (3/3) (in the 144-pin package only)

Input-only port (P8_5)

Data bus

NMI

P8_5/NMI

P8 read signal

Input-only port (P9_1)

Data bus P9_1

P9 read signal

Input-only port (P14_1)

Data bus P14_1

P14 read signal

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R32C/117 Group 15. Programmable I/O Ports

15.1 Port Pi Register (Pi register, i = 0 to 15)

A write/read operation to the Pi register is required to communicate with external devices. This register

consists of a port latch to hold output data and a circuit to read pin states. Bits in the Pi register

correspond to respective ports.

When a programmable I/O port is selected in the output function select registers, the value in the port

latch is read for output and the pin state is read for input.

In memory expansion mode and microprocessor mode, this register cannot control pins being assigned

bus control signals (A0 to A23, D0 to D31, CS0 to CS3, WR/WR0, BC0, BC1/WR1, BC2/WR2, BC3/WR3,

RD, CLKOUT/BCLK, HLDA, HOLD, ALE, and RDY).

Figure 15.5 shows the Pi register.

Figure 15.5 Registers P0 to P15

Port Pi Register (i = 0 to 15) (1, 2)

Symbol

P0 to P3

P4 to P7

P8 (3), P9 (3, 4)

P10, P11 (2, 5)

P12, P13 (2)

P14 (2, 3, 4, 5), P15 (2)

Address

03C0h, 03C1h, 03C4h, 03C5h

03C8h, 03C9h, 03CCh, 03CDh

03D0h, 03D1h

03D4h, 03D5h

03D8h, 03D9h

03DCh, 03DDh

Reset Value

Undefined

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Port Pi_0 Bit (4)

RWPort Pi_2 Bit (4)

RWPort Pi_3 Bit

RWPort Pi_4 Bit

RWPort Pi_5 Bit (3, 5)

RWPort Pi_6 Bit (5)

RWPort Pi_7 Bit (5)

RWPort Pi_1 Bit (3)

When the direction bit is 0 (input)

A value is written to the

corresponding bit. It is not output

due to input mode selected. The

read value is the corresponding pin

state as follows:

0: Low

1: High

When the direction bit is 1 (output)

A value is written to the

corresponding bit as follows:

0: Output low

1: Output high

The read value has the same

output level as that written to the

corresponding bit

Notes:

1. In memory expansion mode and microprocessor mode, this register cannot control pins being assigned bus

control signals (A0 to A23, D0 to D31, CS0 to CS3, WR/WR0, BC0, BC1/WR1, BC2/WR2, BC3/WR3, RD,

CLKOUT/BCLK, HLDA, HOLD, ALE, and RDY).

2. Registers P11 to P15 are available in the 144-pin package only.

3. The P8_5 bit in the P8 register, the P9_1 bit in the P9 register (in the 100-pin package), and the P14_1 bit in

the P14 register (in the 144-pin package) are read only.

4. Bits P9_0 and P9_2 in the P9 register (in the 100-pin package) and bits P14_0 and P14_2 in the P14

values.

5. No register bits are assigned to bits P11_5 to P11_7 in the P11 register and the P14_7 bit in the P14

Pi_0

Pi_1

Pi_2

Pi_3

Pi_4

Pi_5

Pi_6

Pi_7

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R32C/117 Group 16. Timers

16. Timers

This MCU has eleven 16-bit timers which are divided into two groups according to their functions: five timer

As and six timer Bs. Each timer functions individually. The count source of each timer provides the clock for

timer operations such as counting and reloading.

Figures 16.1 and 16.2 show the configuration of timers A and B, respectively.

Figure 16.1 Timer A Configuration

XCIN

Clock prescaler

1/32

Setting the CPSR bit in

the CPSRF register to 1

Reset

TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TAiMR register

TAiTGH and TAiTGL: Bits in the ONSF or TRGSR register (i = 0 to 4)

fC32

f1 f8 f2n fC32

Timer B2 overflow or

underflow

Timer A0 Timer A0 interrupt

TA0IN

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

00,10,11

TA0TGH and TA0TGL

TCK1 and TCK0

TMOD1 and TMOD0

TA1TGH and TA1TGL

Noise

filter

00,10,11

TA1IN

Timer A1 interrupt

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

00,10,11

TA2IN

Timer A2 interrupt

Timer A2

TA2TGH and TA2TGL

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

00,10,11

TA3IN

Timer A3 interrupt

TA3TGH and TA3TGL

Timer A3

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

00,10,11

TA4IN

Timer A4 interrupt

TA4TGH and TA4TGL

Timer A4

Timer A1

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R32C/117 Group 16. Timers

Figure 16.2 Timer B Configuration

Clock prescaler

1/32

Setting the CPSR bit in

the CPSRF register to 1

Reset

TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register (i = 0 to 5)

fC32

f1 f8 f2n fC32 Timer B2 overflow or underflow (to a timer A count source)

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

TB0IN

Timer B0 interrupt

Timer B0

00,10

TCK1

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

TB1IN

Timer B1 interrupt

Timer B1

00,10

TCK1

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

TB2IN

Timer B2 interrupt

Timer B2

00,10

TCK1

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

TB3IN

Timer B3 interrupt

Timer B3

00,10

TCK1

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

TB4IN

Timer B4 interrupt

Timer B4

00,10

TCK1

TCK1 and TCK0

TMOD1 and TMOD0

Noise

filter

TB5IN

Timer B5 interrupt

Timer B5

00,10

TCK1

XCIN

Overflow or underflow

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R32C/117 Group 16. Timers

16.1 Timer A

Figure 16.3 shows a block diagram of timer A and Figure 16.4 to Figure 16.10 show registers associated

with timer A.

Timer A supports the four modes shown below. Timers A0 to A4 in any mode other than the event counter

mode have the same function. Select a mode by setting bits TMOD1 and TMOD0 in the TAiMR register (i

= 0 to 4).

• Timer mode: The timer counts an internal count source

• Event counter mode: The timer counts an external pulse or overflow and underflow of other timers

• One-shot timer mode: The timer outputs pulses after a trigger input until the counter reaches

0000h

• Pulse-width modulation mode: The timer successively outputs pulses of a given width

Figure 16.3 Timer A Block Diagram

Clock selection

Increment/decrement

TAiUD

TMOD1 and TMOD0

Decrement

Pulse output

TAiOUT

TAiTGH and

TAiTGL

Count source selection

TAiIN

TMOD1 and TMOD0

TCK1 and TCK0

f2n

fC32

TAj overflow (1, 2)

Polarity selector,

Edge detector

10,11

MR2

Reload register

TAiS

Upper byte of data bus

Lower byte of data bus

Lower byte Upper byte

Counter

TB2 overflow (1)

TAk overflow (1, 3)

MR2

00,10,11

Toggle flip flop

Always decrements except

in event counter mode

i = 0 to 4

Notes:

1. The timer overflows or underflows.

2. j = i - 1, or j = 4 if i = 0 (refer to the list on the right)

3. k = i + 1, or k = 0 if i = 4 (refer to the list on the right)

TCK1 and TCK0, TMOD1 and TMOD0, MR2: Bits in the TAiMR register

TAiTGH and TAiTGL: Bits in the ONSF register (i = 0) or in the TRGSR register (i = 1 to 4)

TAiS: Bits in the TABSR register

TAiUD: Bits in the UDF register

TAi TAj TAk

Timer A0 Timer A4 Timer A1

Timer A1 Timer A0 Timer A2

Timer A2 Timer A1 Timer A3

Timer A3 Timer A2 Timer A4

Timer A4 Timer A3 Timer A0

Event/trigger selection

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R32C/117 Group 16. Timers

Figure 16.4 Registers TA0 to TA4

Timer Ai Register (i = 0 to 4) (1)

Symbol

TA0 to TA2

TA3, TA4

Address

0347h-0346h, 0349h-0348h, 034Bh-034Ah

034Dh-034Ch, 034Fh-034Eh

Reset Value

Undefined

FunctionMode Setting Range RW

Divides the count source by n+1

(n = setting value)

0000h to

FFFFh

Divides the count source by FFFFh -n+1

(when incrementing) or by n+1 (when

decrementing)

(n = setting value) (2)

0000h to

FFFFh

Divides the count source by n, then stops

(n = setting value) (3)

0000h to

FFFFh (4)

PWM period: (216 -1) / fj

High level width of PWM pulse: n / fj

(fj = count source frequency, n = setting

value of the TAi register) (5)

0000h to

FFFEh (4)

PWM period: (28 -1) × (m+1) / fj

High level width of PWM pulse: (m+1)n /

fj (fj = count source frequency, n = setting

value of the upper byte in the TAi

byte in the TAi register) (5)

00h to FEh

(upper byte)

00h to FFh

(lower byte) (4)

fj: f1, f8, f2n, fC32

Notes:

1. A 16-bit read/write access to this register should be performed.

2. The timer counts an external input pulse or overflow and underflow of other timers.

3. When the TAi register is set to 0000h, the timer counter does not start, and the TAi interrupt request is not

generated.

4. Use the MOV instruction to set the TAi register.

5. When the TAi register is set to 0000h, the pulse-width modulator does not operate, the TAiOUT pin is held

low, and the TAi interrupt request is not generated. The same restrictions apply in 8-bit pulse-width

modulator mode if the upper byte in the TAi register is set to 00h.

b15 b0b8 b7

Timer Mode

Pulse-width

Modulation Mode

(8-bit PWM)

Pulse-width

Modulation Mode

(16-bit PWM)

One-shot Timer Mode

Event Counter Mode

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R32C/117 Group 16. Timers

Figure 16.5 Registers TA0MR to TA4MR

Figure 16.6 TABSR Register

Timer Ai Mode Register (i = 0 to 4)

b7 b6 b5 b4 b1b2b3 b0 Symbol

TA0MR to TA4MR

Address

0356h, 0357h, 0358h, 0359h, 035Ah

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Operating Mode Select Bit

b1 b0

0 0 : Timer mode

0 1 : Event counter mode

1 0 : One-shot timer mode

1 1 : Pulse-width modulation mode

—Function varies according to the

operating mode

Count Source Select Bit Function varies according to the

operating mode

Reserved Should be written with 0

TMOD0

TMOD1

—

(b2)

MR1

MR2

MR3

TCK0

TCK1

Count Start Register

Symbol

TABSR

Address

0340h

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

RWTimer A0 Count Start Bit

RWTimer A1 Count Start Bit

RWTimer A2 Count Start Bit

RWTimer A3 Count Start Bit

RWTimer A4 Count Start Bit

RWTimer B0 Count Start Bit

RWTimer B1 Count Start Bit

RWTimer B2 Count Start Bit

TA0S

TA1S

TA2S

TA3S

TA4S

TB0S

TB1S

TB2S

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

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R32C/117 Group 16. Timers

Figure 16.7 UDF Register

Increment/Decrement Select Register (1)

Symbol

UDF

Address

0344h

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

0: Count decremented

1: Count incremented (2)

Timer A0

Increment/Decrement

Select Bit

0: Count decremented

1: Count incremented (2)

Timer A1

Increment/Decrement

Select Bit

0: Count decremented

1: Count incremented (2)

Timer A2

Increment/Decrement

Select Bit

0: Count decremented

1: Count incremented (2)

Timer A3

Increment/Decrement

Select Bit

0: Count decremented

1: Count incremented (2)

Timer A4

Increment/Decrement

Select Bit

Timer A2

Two-phase Pulse Signal

Processing Select Bit

Timer A3

Two-phase Pulse Signal

Processing Select Bit

Timer A4

Two-phase Pulse Signal

Processing Select Bit

Notes:

1. Use the MOV instruction to set this register.

2. This bit is enabled in event counter mode and when the MR2 bit in the TAiMR register is set to 0 (the UDF

3. Set this bit to 0 when not using two-pulse signal processing.

0: Two-phase pulse signal processing

disabled

1: Two-phase pulse signal processing

enabled (3)

0: Two-phase pulse signal processing

disabled

1: Two-phase pulse signal processing

enabled (3)

0: Two-phase pulse signal processing

disabled

1: Two-phase pulse signal processing

enabled (3)

TA4P

TA2P

TA3P

TA4UD

TA3UD

TA2UD

TA1UD

TA0UD

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R32C/117 Group 16. Timers

Figure 16.8 ONSF Register

One-shot Start Register

Symbol

ONSF

Address

0342h

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

0: Timer in idle state

1: Start the timer (1)

Timer A0

One-shot Start Bit

0: Timer in idle state

1: Start the timer (1)

Timer A1

One-shot Start Bit

0: Timer in idle state

1: Start the timer (1)

Timer A2

One-shot Start Bit

0: Timer in idle state

1: Start the timer (1)

Timer A3

One-shot Start Bit

0: Timer in idle state

1: Start the timer (1)

Timer A4

One-shot Start Bit

0: Z-phase input disabled

1: Z-phase input enabled

Z-phase Input Enable Bit

Timer A0 Event/Trigger

Select Bit

b7 b6

0 0 : Select the input to the TA0IN pin

0 1 : Select the overflow of TB2 (2)

1 0 : Select the overflow of TA4 (2)

1 1 : Select the overflow of TA1 (2)

Notes:

1. This bit is read as 0.

2. The timer overflows or underflows.

TA0OS

TA1OS

TA2OS

TA3OS

TA4OS

TAZIE

TA0TGL

TA0TGH

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R32C/117 Group 16. Timers

Figure 16.9 TRGSR Register

Trigger Select Register

Symbol

TRGSR

Address

0343h

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Note:

1. The timer overflows or underflows.

Timer A1 Event/Trigger

Select Bit

b1 b0

0 0 : Select the input to the TA1IN pin

0 1 : Select the overflow of TB2 (1)

1 0 : Select the overflow of TA0 (1)

1 1 : Select the overflow of TA2 (1)

Timer A2 Event/Trigger

Select Bit

b2 b3

0 0 : Select the input to the TA2IN pin

0 1 : Select the overflow of TB2 (1)

1 0 : Select the overflow of TA1 (1)

1 1 : Select the overflow of TA3 (1)

Timer A3 Event/Trigger

Select Bit

b4 b5

0 0 : Select the input to the TA3IN pin

0 1 : Select the overflow of TB2 (1)

1 0 : Select the overflow of TA2 (1)

1 1 : Select the overflow of TA4 (1)

Timer A4 Event/Trigger

Select Bit

b6 b7

0 0 : Select the input to the TA4IN pin

0 1 : Select the overflow of TB2 (1)

1 0 : Select the overflow of TA3 (1)

1 1 : Select the overflow of TA0 (1)

TA1TGL

TA4TGH

TA3TGL

TA2TGH

TA2TGL

TA1TGH

TA4TGL

TA3TGH

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R32C/117 Group 16. Timers

Figure 16.10 TCSPR Register

b7 b6 b5 b4 b1b2b3 Symbol

TCSPR

Address

035Fh

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Count Source Prescaler Register

f2n is either the main clock or

peripheral clock source divided by

2n. If n = 0, the clock is not divided (n

= setting value)

Divide Ratio Select Bit (1)

0: Stop divider operation

1: Start divider operation

Divider Operation Enable

Bit

Note:

1. Set the CST bit to 0 before rewriting bits CNT3 to CNT0.

Reserved RWShould be written with 0

000

CNT0

CNT1

CNT2

CNT3

—

(b6-b4)

CST

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R32C/117 Group 16. Timers

16.1.1 Timer Mode

In timer mode, the timer counts an internally generated count source. Table 16.1 lists the specifications

of timer mode. Figure 16.11 shows registers TA0MR to TA4MR in this mode.

Table 16.1 Timer Mode Specifications (i = 0 to 4)

Item Specification

Count sources f1, f8, f2n, or fC32

Count operations • Decrement

• When the timer counter underflows, the reload register value is reloaded

into the counter to continue counting

Divide ratio n: TAi register setting value, 0000h to FFFFh

Count start condition The TAiS bit in the TABSR register is 1 (start counter)

Count stop condition The TAiS bit in the TABSR register is 0 (stop counter)

Interrupt request generating

timing

When the timer counter underflows

TAiIN pin function Functions as a programmable I/O port or a gate input

TAiOUT pin function Functions as a programmable I/O port or a pulse output

Read from timer The TAi register indicates the counter value

Write to timer • While the timer counter is stopped or before the initial count source is

input after starting to count, the value written to the TAi register is written

to both the reload register and the counter

• While the timer counter is running, the value written to the TAi register is

written to the reload register (it is transferred to the counter at the next

reload timing)

Other functions • Gate function

Input signal to the TAiIN pin can control the count start/stop

• Pulse output function

The polarity of the TAiOUT pin is inverted each time the timer counter

underflows.

A low is output while the TAiS bit holds 0 (stop counter)

n1+

------------

R01UH0211EJ0120 Rev.1.20 Page 206 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

Figure 16.11 Registers TA0MR to TA4MR in Timer Mode

Timer Ai Mode Register (i = 0 to 4) (timer mode)

Symbol

TA0MR to TA4MR

Address

0356h, 0357h, 0358h, 0359h, 035Ah

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3

FunctionBit Symbol Bit Name RW

b1 b0

0 0 : Timer modeOperating Mode Select Bit

Note:

1. X can be set to either 0 or 1.

b4 b3

0 X : No gate function (1)

(TAiIN pin functions as

programmable I/O port)

1 0 : Count only while the TAiIN pin is

held low

1 1 : Count only while the TAiIN pin is

held high

Gate Function Select Bit

Should be written with 0 in timer mode

b7 b6

00:f1

01:f8

10:f2n

11:fC32

Count Source Select Bit

Reserved

Should be written with 0

0 0 0 0

TMOD0

TMOD1

—

(b2)

MR1

MR2

MR3

TCK0

TCK1

R01UH0211EJ0120 Rev.1.20 Page 207 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

16.1.2 Event Counter Mode

In event counter mode, the timer counts an external signal or an overflow and underflow of other timers.

Timers A2, A3, and A4 can count two-phase external signals. Table 16.2 lists the specifications in event

count mode and Table 16.3 also lists the specifications when the timers use two-phase pulse signal

processing. Figure 16.12 shows registers TA0MR to TA4MR in this mode.

Table 16.2 Event Counter Mode Specifications (without two-phase pulse signal processing)

(i = 0 to 4)

Item Specification

Count sources • External signal applied to the TAiIN pin (valid edge is selectable by a

program)

• One of the following: the overflow and/or underflow signal of timer B2, the

overflow and/or underflow signal of timer Aj (j = i - 1, or j = 4 if i = 0), or

the overflow and/or underflow signal of timer Ak (k = i + 1, or k = 0 if i = 4)

Count operations • Increment/decrement can be switched by an external signal or program

• When the timer counter underflows or overflows, the reload register value

is reloaded into the counter to continue counting. In a free-running count

operation, the timer counter continues counting without reloading

Divide ratio • when incrementing

• when decrementing

n: TAi register setting value, 0000h to FFFFh

Count start condition The TAiS bit in the TABSR register is 1 (start counter)

Count stop condition The TAiS bit in the TABSR register is 0 (stop counter)

Interrupt request generating

timing

When the timer counter overflows or underflows

TAiIN pin function Functions as a programmable I/O port or a count source input

TAiOUT pin function Functions as a programmable I/O port, a pulse output, or an input for

switching between increment/decrement

Read from timer The TAi register indicates a counter value

Write to timer • While the timer counter is stopped or before the initial count source is

input after starting to count, the value written to the TAi register is written

to both the reload register and the counter

• While the timer counter is running, the value written to the TAi register is

written to the reload register (it is transferred to the counter at the next

reload timing)

Other functions • Free-running count function

The reload register value is not reloaded even if the timer counter

overflows or underflows

• Pulse output function

The polarity of the TAiOUT pin is inverted whenever the timer counter

overflows or underflows.

A low is output while the TAiS bit holds 0 (stop counter)

FFFFh n–1+

-------------------------------------

n1+

------------

R01UH0211EJ0120 Rev.1.20 Page 208 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

Note:

1. Only timer A3 is available for any of the other functions. Timer A2 is exclusively for normal processing

operations and timer A4 is for the quadrupled processing operation.

Table 16.3 Event Counter Mode Specifications (with two-phase pulse signal processing on timers

A2 to A4) (i = 2 to 4)

Item Specification

Count sources Two-phase pulse signal applied to pins TAiIN and TAiOUT

Count operations • Increment/decrement can be switched by a two-phase pulse signal

• When the timer counter underflows or overflows, the reload register value is

reloaded into the counter to continue counting. In a free-running count

operation, the timer counter continues counting without reloading

Divide ratio • when incrementing

• when decrementing n: TAi register setting value, 0000h to FFFFh

Count start condition The TAiS bit in the TABSR register is 1 (start counter)

Count stop condition The TAiS bit in the TABSR register is 0 (stop counter)

Interrupt request

generating timing

When the timer counter overflows or underflows

TAiIN pin function A two-phase pulse input

TAiOUT pin function A two-phase pulse input

Read from timer The TAi register indicates a counter value

Write to timer • While the timer counter is stopped or before the initial count source is input after

starting to count, the value written to the TAi register is written to both the reload

• While the timer counter is running, the value written to the TAi register is written

to the reload register (it is transferred to the counter at the next reload timing)

Other functions (1) • Normal processing operation (timers A2 and A3)

While the input signal applied to the TAjOUT pin is held high, the timer

increments on the rising edge of the TAjIN pin and decrements on the falling

edge (j = 2 or 3)

• Quadrupled processing operation (timers A3 and A4)

When the input signal applied to the TAkOUT pin is held high on the rising edge

of the TAkIN pin, the timer increments on both the rising and falling edges of

pins TAkOUT and TAkIN (k = 3 or 4).

When the signal is held high on the falling edge of the TAkIN pin, the timer

decrements on both the rising and falling edges of pins TAkOUT and TAkIN

• Counter reset by Z-phase input (timer A3)

The counter value is set to 0 by Z-phase input

FFFFh n–1+

-------------------------------------

n1+

------------

TAjOUT

TAjIN

IC: Increments

DC: Decrements

IC IC DC DC DC

TAkOUT

TAkIN

Increments

on all edges

Decrements

on all edges

R01UH0211EJ0120 Rev.1.20 Page 209 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

Figure 16.12 Registers TA0MR to TA4MR in Event Counter Mode

Timer Ai Mode Register (i = 0 to 4) (event counter mode)

Function

(without two-

phase pulse signal

processing)

Bit Name RW

Function

(with two-phase

pulse signal

processing)

Operating Mode Select Bit

0: Count falling

edges

1: Count rising

edges

Count Polarity Select Bit (2)

RWShould be written with 0 in event counter mode

Symbol

TA0MR to TA4MR

Address

0356h, 0357h, 0358h, 0359h, 035Ah

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

b1 b0

0 1 : Event counter mode (1)

Should be written

with 0

0: UDF register

setting

1: Input signal to

the TAiOUT

pin (3)

Increment/Decrement

Switching Source Select Bit

Should be written

with 1

0: Reloading

1: Free-running

Count Operation Type

Select Bit

0: Normal

processing

operation

1: Quadrupled

processing

operation

Two-phase Pulse

Processing Operation

Select Bit (4, 5)

Should be written

with 0

Notes:

1. Set bits TAiTGH and TAiTGL in the ONSF or TRGSR register to select the count source in event counter

mode.

2. This bit setting is enabled only when an external signal is counted.

3. The timer decrements when the input signal to the TAiOUT pin is held low, and increments when the signal

is held high.

4. The TCK1 bit is enabled only in the TA3MR register.

5. For two-phase pulse signal processing, set the TAjP bit in the UDF register to 1 (two-phase pulse signal

processing enabled) and bits TAjTGH and TAjTGL to 00b (input to the TAjIN pin) (j = 2 to 4).

Reserved Should be written with 0

0 0 0 1

Bit Symbol

TMOD0

TMOD1

—

(b2)

MR1

MR2

MR3

TCK0

TCK1

R01UH0211EJ0120 Rev.1.20 Page 210 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

16.1.2.1 Counter Reset by Two-phase Pulse Signal Processing

A Z-phase input signal resets the timer counter when a two-phase pulse signal is being processed.

This function can be used under the following conditions: timer A3 event counter mode, two-phase

pulse signal processing, free-running count operation, and quadrupled processing. The Z-phase signal

is applied to the INT2 pin.

When the TAZIE bit in the ONSF register is set to 1 (Z-phase input enabled), the timer counter can be

reset by Z-phase input. To reset the counter, set the TA3 register to 0000h beforehand.

A Z-phase signal applied to the INT2 pin is detected on an edge. The edge polarity is selected using the

POL bit in the INT2IC register. The Z-phase signal should be input in order to have a pulse width of at

least one count source cycle for timer A3. Figure 16.13 shows the two-phase pulse (phases A and B)

and the Z-phase.

The timer counter is reset at the initial count source input after Z-phase input is detected. Figure 16.14

shows the counter reset timing.

When timer A3 overflows or underflows during a reset by the Z-phase input, two timer A3 interrupt

requests are successively generated. To avoid this, the timer A3 interrupt request should not be used

when using this function.

Figure 16.13 Two-phase Pulse (phases A and B) and Z-phase

Figure 16.14 Counter Reset Timing

TA3OUT

(A-phase)

TA3IN

(B-phase)

Pulse width of at least one count

source cycle is required

Note:

1. This example assumes when the rising edge is selected for the INT signal.

Count source

INT2 (1)

(Z-phase)

The counter is reset at this timing

Note:

1. This example assumes when the rising edge is selected for the INT signal.

TA3OUT

(A-phase)

TA3IN

(B-phase)

Count source

INT2 (1)

(Z-phase)

mm+1 1234567Counter value

R01UH0211EJ0120 Rev.1.20 Page 211 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

16.1.3 One-shot Timer Mode

In one-shot timer mode, the timer operates only once for each trigger. Table 16.4 lists specifications of

one-shot timer mode. Once a trigger occurs, the timer starts and operates for a given period. Figure

16.15 shows registers TA0MR to TA4MR in this mode.

Table 16.4 One-shot Timer Mode Specifications (i = 0 to 4)

Item Specification

Count sources f1, f8, f2n, or fC32

Count operations • Decrement

• When the timer counter reaches 0000h, it stops running after the reload

• When a trigger occurs while counting, the reload register value is

reloaded into the counter to continue counting

Divide ratio n: TAi register setting value, 0000h to FFFFh

(Note that the timer counter does not run if n = 0000h)

Count start conditions The TAiS bit in the TABSR register is 1 (start counter) and any of following

triggers occurs:

• An external trigger applied to the TAiIN pin

• One of the following: the overflow and/or underflow signal of timer B2, the

overflow and/or underflow signal of timer Aj (j = i - 1, or j = 4 if i = 0), or

the overflow and/or underflow signal of timer Ak (k = i + 1, or k = 0 if i = 4)

• The TAiOS bit in the ONSF register is 1 (start the timer)

Count stop conditions • The timer counter reaches 0000h and the reload register value is

reloaded

• The TAiS bit in the TABSR register is 0 (stop counter)

Interrupt request generating

timing

When the timer counter reaches 0000h

TAiIN pin function A programmable I/O port or a trigger input

TAiOUT pin function A programmable I/O port or a pulse output

Read from timer The TAi register indicates an undefined value

Write to timer • While the timer counter is stopped or before the initial count source is

input after starting to count, the value written to the TAi register is written

to both the reload register and the counter

• While the timer counter is running, the value written to the TAi register is

written to the reload register (it is transferred to the counter at the next

reload timing)

Other function • Pulse output function

A low is output while the timer counter is stopped and a high is output

while the timer counter is running

1n1

---------

R01UH0211EJ0120 Rev.1.20 Page 212 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

Figure 16.15 Registers TA0MR to TA4MR in One-shot Timer Mode

Timer Ai Mode Register (i = 0 to 4) (one-shot timer mode)

b7 b6 b5 b4 b1b2b3 b0 Symbol

TA0MR to TA4MR

Address

0356h, 0357h, 0358h, 0359h, 035Ah

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

b1 b0

1 0 : One-shot timer modeOperating Mode Select Bit

External Trigger Select Bit

(1) RW

0: Falling edge of input signal to the

TAiIN pin

1: Rising edge of input signal to the

TAiIN pin

Reserved Should be written with 0

TMOD0

TMOD1

—

(b2)

MR1

0 0 1 0

Trigger Select Bit RW

0: TAiOS bit in the ONSF register is

enabled

1: Selected using bits TAiTGH and

TAiTGL in the ONSF or TRGSR

RWShould be written with 0 in one-shot timer mode

b7 b6

00:f1

01:f8

10:f2n

11:fC32

Count Source Select Bit

Note:

1. The MR1 bit setting is enabled only when bits TAiTGH and TAiTGL in the TRGSR register are set to 00b

(input to the TAiIN pin). This bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b

(overflow or underflow of TB2), 10b (overflow or underflow of TAi), or 11b (overflow or underflow of TAi).

MR2

MR3

TCK0

TCK1

R01UH0211EJ0120 Rev.1.20 Page 213 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

16.1.4 Pulse-width Modulation Mode

In pulse-width modulation mode, the timer outputs pulses of given width successively. Table 16.5 lists

specifications of pulse-width modulation mode. The timer counter functions as either a 16-bit or 8-bit

pulse-width modulator. Figure 16.16 shows registers TA0MR to TA4MR in this mode. Figures 16.17 and

16.18 show operation examples of 16-bit and 8-bit pulse-width modulators.

Table 16.5 Pulse-width Modulation Mode Specifications (i = 0 to 4)

Item Specification

Count sources f1, f8, f2n, or fC32

Count operations • Decrement (the timer counter functions as an 8-bit or a 16-bit pulse-width

modulator)

• The reload register value is reloaded on the rising edge of a PWM pulse

to continue counting

• The timer is not affected by a trigger that occurs while the counter is

running

16-bit PWM • High level width: n: TAi register setting value, 0000h to FFFEh

fj: Count source frequency

• Period: fixed to

8-bit PWM • High level width:

•Period:

n: Upper byte of the TAi register setting value, 00h to FEh

m: Lower byte of the TAi register setting value, 00h to FFh

Count start conditions • The TAiS bit in the TABSR register is 1 (start counter)

• The TAiS bit is 1 and an external trigger is applied to the TAiIN pin

• The TAiS bit is 1 and any of following triggers occurs:

the overflow and/or underflow signal of timer B2, the overflow and/or

underflow signal of timer Aj (j = i - 1, or j = 4 if i = 0), or the overflow and/

or underflow signal of timer Ak (k = i + 1, or k = 0 if i = 4)

Count stop condition The TAiS bit in the TABSR register is 0 (stop counter)

Interrupt request generating

timing

On the falling edge of the PWM pulse

TAiIN pin function A programmable I/O port or trigger input

TAiOUT pin function A pulse output

Read from timer The TAi register indicates an undefined value

Write to timer • While the timer counter is stopped or before the initial count source is

input after starting to count, the value written to the TAi register is written

to both the reload register and the counter

• While the timer counter is running, the value written to the TAi register is

written to the reload register (it is transferred to the counter at the next

reload timing)

1n1

---------

216 1–

-----------------

nm1+

---------------------------

281–m1+

--------------------------------------------

R01UH0211EJ0120 Rev.1.20 Page 214 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

Figure 16.16 Registers TA0MR to TA4MR in Pulse-width Modulation Mode

Timer Ai Mode Register (i = 0 to 4) (pulse-width modulation mode)

Symbol

TA0MR to TA4MR

Address

0356h, 0357h, 0358h, 0359h, 035Ah

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

b1 b0

1 1 : Pulse-width modulation (PWM)

mode

Operating Mode Select Bit

External Trigger Select Bit

(1) RW

0: Falling edge of the input signal to

the TAiIN pin

1: Rising edge of the input signal to

the TAiIN pin

Trigger Select Bit RW

0: TAiS bit in the ONSF register is

enabled

1: Selected using bits TAiTGH and

TAiTGL in the ONSF or TRGSR

16-/8-bit PWM Mode Select

Bit RW

0: Function as a 16-bit pulse-width

modulator

1: Function as a 8-bit pulse-width

modulator

b7 b6

00:f1

01:f8

10:f2n

11:fC32

Count Source Select Bit

Note:

1. The MR1 bit setting is enabled only when bits TAiTGH and TAiTGL in the TRGSR register are set to 00b

(input to the TAiIN pin). This bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b

(overflow or underflow of TB2), 10b (overflow or underflow of TAi), or 11b (overflow or underflow of TAi).

Reserved Should be written with 0

0 1 1

TMOD0

TMOD1

—

(b2)

MR1

MR2

MR3

TCK0

TCK1

R01UH0211EJ0120 Rev.1.20 Page 215 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

Figure 16.17 16-bit Pulse-width Modulator Operation

Figure 16.18 8-bit Pulse-width Modulator Operation

Count source

Input signal to the

TAiIN pin

Note:

1. n is a value from 0000h to FFFEh.

Set to 0 by an interrupt request acceptance or by a program

IR bit in the TAilC

When the reload register is 0003h and an external trigger (the rising edge of an input signal

applied to the TAiIN pin) is selected.

PWM pulse output

from TAiOUT pin

No trigger occurs by this signal

i = 0 to 4

fj: Count source frequency

(f1, f8, f2n, fC32)

1/fj × (216-1)

1/fj × n (1)

Count source (1)

Input signal applied to

the TAiIN pin

i = 0 to 4

fj: Count source frequency

(f1, f8, f2n, fC32)

Set to 0 by an interrupt request acceptance or by a program

PWM pulse output

from the TAiOUT pin

When the upper byte of the reload register is 02h, the lower byte is 02h and an external

trigger (the falling edge of an input signal applied to the TAiIN pin) is selected.

Underflow signal of

8-bit prescaler (2)

1/fj × (m + 1) (1)

1/fj × (m + 1) × (28 - 1)

IR bit in the TAilC

Notes:

1. The 8-bit prescaler counts a count source.

2. The 8-bit pulse-width modulator counts underflow signals of the 8-bit prescaler.

3. m is a value from 00h to FFh, and n is a value from 00h to FEh.

1/fj × (m + 1) × n (3)

R01UH0211EJ0120 Rev.1.20 Page 216 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

16.2 Timer B

Figure 16.19 shows a block diagram of timer B, and Figure 16.20 to Figure 16.23 show registers

associated with timer B.

Timer B supports the three modes shown below. Select a mode by setting bits TMOD1 and TMOD0 in the

TBiMR register (i = 0 to 5).

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts an external pulse or an overflow and underflow of other

timers.

• Pulse period/pulse-width measure mode: The timer measures the pulse period or pulse width of an

external signal.

Figure 16.19 Timer B Block Diagram

Reload register

Count source selection

TBiS

Upper byte of data bus

Lower byte of data bus

Lower byte Upper byte

TBiIN

TMOD1 and TMOD0

TCK1 and TCK0

i = 0 to 5

Notes:

1. The timer overflows or underflows.

2. j = i - 1; j = 2 if i = 0; or j = 5 if i = 3 (refer to the list on the right)

TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register

TBiS: Bits in the TABSR or TBSR register

f2n

fC32

Counter

TBj overflow (1, 2)

Polarity selector,

Edge detector

1TCK1 01

00,10

Counter reset circuit

TBi TBj

Timer B0 Timer B2

Timer B0Timer B1

Timer B2 Timer B1

Timer B3 Timer B5

Timer B3Timer B4

Timer B5 Timer B4

R01UH0211EJ0120 Rev.1.20 Page 217 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

Figure 16.20 Registers TB0 to TB5

Figure 16.21 Registers TB0MR to TB5MR

Increments the counter between one

valid edge and another of TBiIN input

pulse

—RO

Timer Bi Register (i = 0 to 5) (1)

b15 b0b8 b7 Symbol

TB0 to TB2

TB3 to TB5

Address

0351h-0350h, 0353h-0352h, 0355h-0354h

0311h-0310h, 0313h-0312h, 0315h-0314h

Reset Value

Undefined

FunctionMode Setting Range RW

Divides the count source by n+1

(n = setting value)

0000h to

FFFFh

Divides the count source by n+1

(n = setting value) (2)

0000h to

FFFFh

Notes:

1. A 16-bit read/write access to this register should be performed.

2. The TBi register counts an external input pulse, or an overflow and underflow of other timers.

Timer Mode

Event Counter Mode

Pulse Period/Pulse-

width Measure

Mode

Timer Bi Mode Register (i = 0 to 5)

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Operating Mode Select Bit

b1 b0

0 0 : Timer mode

0 1 : Event counter mode

1 0 : Pulse period measure mode,

pulse-width measure mode

1 1 : Do not use this combination

—Function varies according to the

operating mode (1, 2)

Count Source Select Bit Function varies according to the

operating mode

Notes:

1. The MR2 bit is available for registers TB0MR and TB3MR only.

2. The MR2 bit in registers TB1MR, TB2MR, TB4MR and TB5MR are unavailable on this MCU. This bit

should be written with 0 and read as undefined value.

Symbol

TB0MR to TB2MR

TB3MR to TB5MR

Address

035Bh, 035Ch, 035Dh

031Bh, 031Ch, 031Dh

Reset Value

00XX 0000b

TMOD0

TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

R01UH0211EJ0120 Rev.1.20 Page 218 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

Figure 16.22 TABSR Register

Figure 16.23 TBSR Register

Count Start Register

Symbol

TABSR

Address

0340h

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

RWTimer A0 Count Start Bit

RWTimer A1 Count Start Bit

RWTimer A2 Count Start Bit

RWTimer A3 Count Start Bit

RWTimer A4 Count Start Bit

RWTimer B0 Count Start Bit

RWTimer B1 Count Start Bit

RWTimer B2 Count Start Bit

TA0S

TA1S

TA2S

TA3S

TA4S

TB0S

TB1S

TB2S

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

Count Start Register for Timers B3, B4, and B5

Symbol

TBSR

Address

0300h

Reset Value

000X XXXXb

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

No register bits; should be written with 0 and read as undefined

value

0: Stop counter

1: Start counter

Timer B3 Count Start Bit

0: Stop counter

1: Start counter

Timer B4 Count Start Bit

0: Stop counter

1: Start counter

Timer B5 Count Start Bit

—

(b4-b0)

TB3S

TB4S

TB5S

R01UH0211EJ0120 Rev.1.20 Page 219 of 604

Feb 18, 2013

R32C/117 Group 16. Timers

16.2.1 Timer Mode

In timer mode, the timer counts an internally generated count source. Table 16.6 lists specifications of

timer mode. Figure 16.24 shows registers TB0MR to TB5MR in this mode.

Table 16.6 Timer Mode Specifications (i = 0 to 5)

Item Specification

Count sources f1, f8, f2n, or fC32

Count operations • Decrement

• When the timer counter underflows, the reload register value is reloaded

into the counter to continue counting

Divide ratio n: TBi register setting value, 0000h to FFFFh

Count start condition The TBiS bit in the TABSR or TBSR register is 1 (start counter)

Count stop condition The TBiS bit in the TABSR or TBSR register is 0 (stop counter)

Interrupt request generating

timing

When the timer counter underflows

TBiIN pin function Functions as a programmable I/O port

Read from timer The TBi register indicates a counter value

Write to timer • While the timer counter is stopped or before the initial count source is

input after starting to count, the value written to the TBi register is written

to both the reload register and the counter

• While the timer counter is running, the value written to the TBi register is

written to the reload register (it is transferred to the counter at the next

reload timing)

n1+

------------

R01UH0211EJ0120 Rev.1.20 Page 220 of 604

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R32C/117 Group 16. Timers

Figure 16.24 Registers TB0MR to TB5MR in Timer Mode

Timer Bi Mode Register (i = 0 to 5) (timer mode)

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

b1 b0

0 0 : Timer modeOperating Mode Select Bit

—

Disabled in timer mode.

Can be set to 0 or 1

Disabled in timer mode. Should be written with 0 and read as

undefined value

b7 b6

00:f1

01:f8

10:f2n

11:fC32

Count Source Select Bit

Symbol

TB0MR to TB2MR

TB3MR to TB5MR

Address

035Bh, 035Ch, 035Dh

031Bh, 031Ch, 031Dh

Reset Value

00XX 0000b

In registers TB0MR and TB3MR:

Reserved; should be written with 0

—

In registers TB1MR, TB2MR, TB4MR, and TB5MR:

No register bit; should be written with 0 and read as undefined

value

0 0 0

TMOD0

TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

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R32C/117 Group 16. Timers

16.2.2 Event Counter Mode

In event counter mode, the timer counts an external signal or the overflow or underflow of other timers.

Table 16.7 lists specifications of event counter mode. Figure 16.25 shows the TBiMR register in this

mode (i = 0 to 5).

Table 16.7 Event Counter Mode Specifications (i = 0 to 5)

Item Specification

Count sources • External signal applied to the TBiIN pin (valid edge is selectable among

the falling edge, the rising edge, or both)

• The overflow or underflow signal of TBj (j = i - 1; j = 2 if i = 0; or j = 5 if

i = 3)

Count operations • Decrement

• When the timer counter underflows, the reload register value is reloaded

into the counter to continue counting

Divide ratio n: TBi register setting value, 0000h to FFFFh

Count start condition The TBiS bit in the TABSR or TBSR register is 1 (start counter)

Count stop condition The TBiS bit in the TABSR or TBSR register is 0 (stop counter)

Interrupt request generation

timing

When the timer counter underflows

TBiIN pin function Functions as a programmable I/O port or count source input

Read from timer The TBi register indicates a counter value

Write to timer • While the timer counter is stopped or before the initial count source is

input after starting to count, the value written to the TBi register is written

to both the reload register and the counter

• While the timer counter is running, the value written to the TBi register is

written to the reload register (it is transferred to the counter at the next

reload timing)

n1+

------------

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R32C/117 Group 16. Timers

Figure 16.25 Registers TB0MR to TB5MR in Event Counter Mode

Timer Bi Mode Register (i = 0 to 5) (event counter mode)

FunctionBit Symbol Bit Name RW

Operating Mode Select Bit

Count Polarity Select Bit (1)

Disabled in event counter mode.

Should be written with 0 and read as undefined value

b7 b6 b5 b4 b1b2b3 b0

b1 b0

0 1 : Event counter mode

0: Input signal to the TBiIN pin

1: Overflow or underflow of TBj (2)

Disabled in event counter mode.

Can be set to 0 or 1

RWEvent Clock Select Bit

Notes:

1. These bit settings are enabled when the TCK1 bit is 0. When the TCK1 bit is 1, these bits can be set to

either 0 or 1.

2. j = i - 1; j = 2 if i = 0; or j = 5 if i = 3.

—

b3 b2

0 0 : Count falling edges

0 1 : Count rising edges

1 0 : Count both edges

1 1 : Do not use this combination

Symbol

TB0MR to TB2MR

TB3MR to TB5MR

Address

035Bh, 035Ch, 035Dh

031Bh, 031Ch, 031Dh

Reset Value

00XX 0000b

In registers TB0MR and TB3MR:

Reserved; should be written with 0

—

In registers TB1MR, TB2MR, TB4MR, and TB5MR:

No register bit; should be written with 0 and read as undefined

value

0 10

TMOD0

TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

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R32C/117 Group 16. Timers

16.2.3 Pulse Period/Pulse-width Measure Mode

In pulse period/pulse-width measure mode, the timer measures the pulse period or pulse width of an

external signal. Table 16.8 lists specifications of the pulse period/pulse-width measure mode. Figure

16.26 shows registers TB0MR to TB5MR in this mode. Figures 16.27 and 16.28 show an operation

example of pulse period measurement and pulse-width measurement, respectively.

Notes:

1. No interrupt request is generated when the pulse to be measured is applied on the initial valid edge

after the timer counter starts.

2. While the TBiS bit is 1 (start counter), after the MR3 bit becomes 1 (overflow) and at least one count

source cycle has elapsed, a write operation to the TBiMR register sets the MR3 bit to 0 (no overflow).

3. The TBi register indicates an undefined value until the pulse to be measured is applied on the second

valid edge after the timer counter starts.

Table 16.8 Pulse Period/Pulse-width Measure Mode Specifications (i = 0 to 5)

Item Specification

Count sources f1, f8, f2n, or fC32

Count operations • Increment

• The counter value is transferred to the reload register on the valid edge of

a pulse to be measured, then it is set to 0000h to resume counting

Count start condition The TBiS bit in the TABSR or TBSR register is 1 (start counter)

Count stop condition The TBiS bit in the TABSR or TBSR register is 0 (stop counter)

Interrupt request generating

timing

• On the valid edge of a pulse to be measured (1)

• When the timer counter overflows

(when the MR3 bit in the TBiMR register becomes 1 (overflow)) (2)

TBiIN pin function A pulse input to be measured

Read from timer The TBi register indicates a reload register value (measurement results) (3)

Write to timer The value written to the TBi register is written to neither the reload register

nor the counter

R01UH0211EJ0120 Rev.1.20 Page 224 of 604

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R32C/117 Group 16. Timers

Figure 16.26 Registers TB0MR to TB5MR in Pulse Period/Pulse-width Measure Mode

In registers TB0MR and TB3MR:

Reserved; should be written with 0

Timer Bi Mode Register (i = 0 to 5) (pulse period/pulse-width measure mode)

Operating Mode Select Bit

Measure Mode Select Bit (1)

Timer Bi Overflow Flag (2)

Symbol

TB0MR to TB2MR

TB3MR to TB5MR

Address

035Bh, 035Ch, 035Dh

031Bh, 031Ch, 031Dh

Reset Value

00XX 0000b

b7 b6 b5 b4 b1b2b3 b0

b1 b0

1 0 : Pulse period/pulse-width

measure mode

—

0: No overflow

1: Overflow

Count Source Select Bit

In registers TB1MR, TB2MR, TB4MR, and TB5MR:

No register bit; should be written with 0 and read as undefined

value

b3 b2

0 0 : Pulse period measurement 1

0 1 : Pulse period measurement 2

1 0 : Pulse-width measurement

1 1 : Do not use this combination

b7 b6

00:f1

01:f8

10:f2n

11:fC32

Notes:

1. The measure modes selected by setting bits MR1 and MR0 are as follows:

Pulse period measurement 1 (bits MR1 and MR0 = 00b):

Measures between a falling edge and the next falling edge of a pulse

Pulse period measurement 2 (bits MR1 and MR0 = 01b):

Measures between a rising edge and the next rising edge of a pulse

Pulse-width measurement (bits MR1 and MR0 = 10b):

Measures between a falling edge and the next rising edge of a pulse and between the rising edge

and the next falling edge of the pulse

FunctionBit Symbol Bit Name RW

2. The MR3 bit is undefined when the timer is reset.

While the TBiS bit in the TABSR or TBSR register is 1 (start counter), after the MR3 bit becomes 1 and at

least one count source cycle has elapsed, a write operation to the TBiMR register sets the MR3 bit to 0. The

MR3 bit cannot be set to 1 by a program.

1 0

TMOD0

TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

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R32C/117 Group 16. Timers

Figure 16.27 Operation Example in Pulse Period Measurement

Figure 16.28 Operation Example in Pulse-width Measurement

Transferred

(undefined value)

Transferred

(measured value)

See Note 1

Set to 0 by an interrupt request acceptance or by a program

Count source

Measured pulse

Timing when the counter

reaches 0000h

Timing to transfer value from

the counter to the reload

IR bit in the TBilC register

MR3 bit in TBiMR register

TBiS bit in the TABSR

or TBSR register

i = 0 to 5

Notes:

1. The timer counter is reset when the measurement is completed.

2. The timer counter overflows.

See Note 1 See

Note 2

i = 0 to 5

Notes:

1. The timer counter is reset when the measurement is completed.

2. The timer counter overflows.

Count source

Measured pulse

Timing when the counter

reaches 0000h

Timing to transfer value from

the counter to the reload

IR bit in the TBilC register

Transferred

(undefined

value)

MR3 bit in the TBiMR

Transferred

(measured

value)

Transferred

(measured

value)

Transferred

(measured value)

TBiS bit in the TABSR

or TBSR register

See Note 1 See Note 1 See Note 1 See Note 1 See

Note 2

Set to 0 by an interrupt request acceptance or by a program

R01UH0211EJ0120 Rev.1.20 Page 226 of 604

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R32C/117 Group 16. Timers

16.3 Notes on Timers

16.3.1 Timer A and Timer B

All timers are stopped after a reset. To restart timers, configure parameters such as operating mode,

count source, and counter value, then set the TAiS bit or TBjS bit in the TABSR or TBSR register to 1

(count starts) (i = 0 to 4; j = 0 to 5).

The following registers and bits should be set while the TAiS bit or TBjS bit is 0 (count stops):

• Registers TAiMR and TBjMR

• UDF register

• Bits TAZIE, TA0TGL, and TA0TGH in the ONSF register

• TRGSR register

16.3.2 Timer A

16.3.2.1 Timer Mode

• While the timer counter is running, the TAi register indicates a counter value at any given time.

However, FFFFh is read while reloading is in progress. A set value is read if the TAi register is set

while the timer counter is stopped.

16.3.2.2 Event Counter Mode

• While the timer counter is running, the TAi register indicates a counter value at any given time.

However, FFFFh is read if the timer counter underflows or 0000h if overflows while reloading is in

progress. A set value is read if the TAi register is set while the timer counter is stopped.

16.3.2.3 One-shot Timer Mode

• If the TAiS bit in the TABSR register is set to 0 (count stops) while the timer counter is running, the

following operations are performed:

- The timer counter stops and the setting value of the TAi register is reloaded.

- A low signal is output at the TAiOUT pin.

- The IR bit in the TAiIC register becomes 1 (interrupts requested) after one CPU clock cycle.

• The one-shot timer is operated by an internal count source. When the trigger is an input to the

TAiIN pin, the signal is output with a maximum one count source clock delay after a trigger input to

the TAiIN pin.

• The IR bit becomes 1 by any of the settings below. To use the timer Ai interrupt, set the IR bit to 0

after one of the settings below is done:

- Select one-shot timer mode after a reset.

- Switch operating modes from timer mode to one-shot timer mode.

- Switch operating modes from event counter mode to one-shot timer mode.

• If a retrigger occurs while counting, the timer counter decrements by one, reloads the setting value

of the TAi register, and then continues counting. To generate a retrigger while counting, wait at

least one count source cycle after the last trigger is generated.

• When an external trigger input is selected to start counting in timer A one-shot mode, do not

provide an external retrigger for 300 ns before the timer counter reaches 0000h. Otherwise, it may

stop counting.

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R32C/117 Group 16. Timers

16.3.2.4 Pulse-width Modulation Mode

• The IR bit becomes 1 by any of the settings below. To use the timer Ai interrupt, set the IR bit to 0

after one of the settings below is done (i = 0 to 4):

- Select pulse-width modulation mode after a reset.

- Switch operating modes from timer mode to pulse-width modulation mode.

- Switch operating modes from event counter mode to pulse-width modulation mode.

• If the TAiS bit in the TABSR register is set to 0 (count stops) while PWM pulse is output, the

following operations are performed:

- The timer counter stops.

- The output level at the TAiOUT pin changes from high to low. The IR bit becomes 1.

- When a low signal is output at the TAiOUT pin, it does not change. The IR bit does not change,

either.

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R32C/117 Group 16. Timers

16.3.3 Timer B

16.3.3.1 Timer Mode and Event Counter Mode

• While the timer counter is running, the TBj register indicates a counter value at any given time (j =

0 to 5). However, FFFFh is read while reloading is in progress. When a value is set to the TBj

value is read.

16.3.3.2 Pulse Period/Pulse-width Measure Mode

• While the TBjS bit in the TABSR or TBSR register is 1 (start counter), after the MR3 bit becomes 1

(overflow) and at least one count source cycle has elapsed, a write operation to the TBjMR register

sets the MR3 bit to 0 (no overflow).

• Use the IR bit in the TBjIC register to detect overflow. The MR3 bit is used only to determine an

interrupt request source within the interrupt handler.

• The counter value is undefined when the timer counter starts. Therefore, the timer counter may

overflow before a measured pulse is applied on the initial valid edge and cause a timer Bj interrupt

request to be generated.

• When the measured pulse is applied on the initial valid edge after the timer counter starts, an

undefined value is transferred to the reload register. At this time, a timer Bj interrupt request is not

generated.

• The IR bit may become 1 (interrupt requested) by changing bits MR1 and MR0 in the TBjMR

the IR bit does not change.

• Pulse width is continuously measured in pulse-width measure mode. Whether the measurement

result is high-level width or not is determined by a program.

• When an overflow occurs at the same time a pulse is applied on the valid edge, this pulse is not

recognized since an interrupt request is generated only once. Do not let an overflow occur in pulse

period measure mode.

• In pulse-width measure mode, determine whether an interrupt source is a pulse applied on the

valid edge or an overflow by reading the port level in the timer Bj interrupt handler.

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R32C/117 Group 17. Three-phase Motor Control Timers

17. Three-phase Motor Control Timers

A three-phase motor driving waveform can be output using timers A1, A2, A4, and B2. The three-phase

motor control timers are enabled by setting the INV02 bit in the INVC0 register to 1. Timer B2 is used for

carrier wave control, and timers A1, A2, and A4 for three-phase PWM output (U, U, V, V, W, and W) control.

Table 17.1 lists the specifications of the three-phase motor control timers and Figure 17.1 shows its block

diagram. Figures 17.2 to 17.6 show registers associated with this function.

Note:

1. Forced cutoff by a signal input to the NMI pin can be performed when the PM24 bit in the PM2

used), and the INV03 bit is 1 (three-phase motor control timer output enabled).

Table 17.1 Specifications for Three-phase Motor Control Timers

Item Specification

Three-phase PWM waveform

output pins

Six pins: U, U, V, V, W, and W

Forced cutoff (1) A low input to the NMI pin

Timers Timers A4, A1, and A2 are used in one-shot timer mode:

Timer A4 is used for U- and U-phase waveform control

Timer A1 is used for V- and V-phase waveform control

Timer A2 is used for W- and W-phase waveform control

Timer B2 is used in timer mode

Carrier wave cycle control

Dead time timer (three 8-bit timers share a reload register):

Dead time control

Output waveforms Triangular wave modulation and sawtooth wave modulation

• Output of a high or a low waveform for one cycle

• Separately settable levels of high side and low side

Carrier wave periods Triangular wave modulation: count source × (m + 1) × 2

Sawtooth wave modulation: count source × (m + 1)

m: TB2 register setting value from 0000h to FFFFh

Count source: f1, f8, f2n, or fC32

Three-phase PWM output

width

Triangular wave modulation: count source × n × 2

Sawtooth wave modulation: count source × n

n: Setting value of registers TA4, TA1, and TA2 (registers TA4, TA41,

TA1, TA11, TA2, and TA21 when the INV11 bit in the INVC1 register

is 1) from 0001h to FFFFh

Count source: f1, f8, f2n, or fC32

Dead time (width) Count source × p or no dead time

p: DTT register setting value from 01h to FFh

Count source: f1 or f1 divided by 2

Active level Selectable either active high or active low

Simultaneous conduction

prevention

Function to detect simultaneous turn-on signal outputs, function to disable

signal output when simultaneous turn-on signal outputs are detected

Interrupt frequency Selectable from one through 15 time-carrier wave cycle-to-cycle basis for

the timer B2 interrupt

R01UH0211EJ0120 Rev.1.20 Page 230 of 604

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R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.1 Block Diagram for Three-phase Motor Control Timers

INV07

INV00 to INV07: Bits in the INVC0 register

INV10 to INV15: Bits in the INVC1 register

DUi and DUBi: Bits in the IDBi register (i = 0, 1)

TA1S to TA4S: Bits in the TABSR register

Timer B2

(Timer mode)

Write signal

to timer B2

INV10

INV13

INV01

INV11

Circuit to set interrupt

generating frequency

Timer B2 interrupt request bit

INV12

Timer B2 underflows

INV00

Reload register

n = 01h to FFh

Transfer trigger (1)

One-shot pulse of timer A4

INV14

INV03

INV02

INV05

INV04

U-phase output

control circuit

DUB0

bit

W-phase output

signal

W-phase output

controller

TA2 register

Timer A2 counter

TA21 register

(One-shot timer mode)

Trigger

INV11

When the TA2S bit is 0,

the signal becomes 0

Note:

1. When the INV06 bit is 0 (triangular wave modulation mode), the transfer trigger is generated only when the

initial underflow of timer B2 occurs after setting registers IDB0 and IDB1.

Switching to P3_2 to P3_7, P7_2

to P7_5, P8_0, and P8_1 is not

shown in this diagram

RESET

NMI

Start trigger signal for timers A1, A2, A4

DUB1

bit

Dead time timer

n = 01h to FFh

Trigger

W-phase

output signal

INV06

Inverse

control

Inverse

control

V-phase

output

signal

V-phase output

controller

TA1 register

Timer A1 counter

TA11 register

(One-shot timer mode)

Trigger

INV11

Dead time timer

n = 01h to FFh

Trigger

V-phase

output signal

INV06

Inverse

control

Inverse

control

When the TA1S bit is 0,

the signal becomes 0

Reload control signal for timer A2

Reload control signal for timer A1

TA4 register

Timer A4 counter

TA41 register

(One-shot timer mode)

Trigger

INV11

When the TA4S bit is 0,

the signal becomes 0

QT Reload control signal for timer A4

DU0

bit

DU1

bit

Dead time timer

n = 01h to FFh

Trigger

INV06

U-phase

output signal

Inverse

control

Inverse

control

U-phase

output

signal

Three-phase output shift

registers (U-phase)

1/2

ICTB2 counter

n = 01h to 0Fh

ICTB2 register

n = 01h to 0Fh

Value to be written to the INV03 bit

Write signal to the INV03 bit

Reload

R01UH0211EJ0120 Rev.1.20 Page 231 of 604

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R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.2 INVC0 Register

Three-phase PWM Control Register 0 (1)

b7 b6 b5 b4 b1b2b3 b0 Symbol

INVC0

Address

0308h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

ICTB2 Count Condition

Select Bit (2)

0: Do not use this function

1: Use this function (5, 6, 7)

Three-phase Motor Control

Timers Select Bit

0: Disables the three-phase motor

control timer output (7)

1: Enables the three-phase motor

control timer output (8)

Three-phase Motor Control

Timer Output Control Bit

0: Ignores simultaneous turn-on

signal output

1: Disables simultaneous turn-on

signal output

Simultaneous Conduction

Prevention Bit

0: Not detected

1: Detected (9)

Simultaneous Conduction

Detection Flag

0: Triangular wave modulation mode

1: Sawtooth wave modulation mode

(10)

Modulation Mode Select Bit

A transfer trigger is generated when

this bit is set to 1. When the INV06 bit

is 1, another trigger to the dead time

timer is also generated. This bit is

read as 0

Software Trigger Select Bit RW

Notes:

1. Set this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). Also, rewrite bits INV00

to INV02 and INV06 while timers A1, A2, A4, and B2 are stopped.

2. This bit is enabled when the INV11 bit in the INVC1 register is 1 (three-phase mode 1). When the INV11 bit

is 0 (three-phase mode 0), the ICTB2 counter increments by one each time timer B2 underflows irrespective

of the INV00 and INV01 bit settings.

3. Set the ICTB2 register before setting the INV01 bit to 1. Also, set the TA1S bit in the TABSR register to 1

before the initial timer B2 underflow occurs.

4. When the INV00 bit is 1, the first interrupt occurs when timer B2 underflows n-1 times (n is the value set in

the ICTB2 counter). Subsequent interrupts occur every n times timer B2 underflows.

5. Set the INV02 bit to 1 to operate the dead time timer, U-, V-, and W-phase output control circuits, and the

ICTB2 counter.

6. After setting the INV02 bit to 1, pins should be configured first by the IOBC register then by the output

function select registers.

7. When the INV02 bit is set to 1 and the INV03 bit is set to 0, pins U, U, V, V, W, and W, even when they are

assigned to other peripheral functions, become high-impedance.

8. The INV03 bit becomes 0 when any of the following occurs:

- Reset

- Signals of both the high and low sides are simultaneously switched to active when the INV04 bit is 1.

- The INV03 bit is set to 0 by a program.

- The NMI pin goes from high to low when the PM24 bit in the PM2 register is 1 (NMI enabled).

9. This bit cannot be set to 1 by a program. Set the INV04 bit to 0 to set this bit to 0.

10.When the INV06 bit is 1, set the INV11 bit in the INVC1 register to 0 (three-phase mode 0) and the PWCON

bit in the TB2SC register to 0 (timer B2 register reloaded when timer B2 underflows).

b1 b0

0 X : The underflow of timer B2

1 0 : The underflow of timer B2 when

the reload control signal for

timer A1 is 0 (3)

1 1 : The underflow of timer B2 when

the reload control signal for

timer A1 is 1 (3, 4)

INV00

INV01

INV02

INV03

INV04

INV05

INV06

INV07

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R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.3 INVC1 Register

Three-phase PWM Control Register 1 (1)

b7 b6 b5 b4 b1b2b3 b0 Symbol

INVC1

Address

0309h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

0: The underflow of timer B2

1: The underflow of timer B2 and a

write operation to the TB2 register

Timers A1, A2, and A4

Start Trigger Select Bit

0: Three-phase mode 0 (2, 3)

1: Three-phase mode 1

Timers A1-1, A2-1, and

A4-1 Control Bit

0: f1

1: f1 divided-by-2

Dead Time Timer Count

Source Select Bit

0: Timer A1 reload control signal is 0

1: Timer A1 reload control signal is 1

Carrier Wave Detection

Flag (4)

0: Active low output

1: Active high output

Active Level Control Bit

0: Enables dead time

1: Disables dead time

Dead Time Disable Bit

0: Falling edge of a one-shot pulse of

timer (A4, A1, and A2) (5)

1: Rising edge of the three-phase

output shift register (phases U, V,

and W)

Dead Time Timer Trigger

Select Bit

Should be written with 0Reserved RW

Notes:

1. Set this register after setting the PRC1 bit in the PRCR register to 1 (write enabled). Also, rewrite this

2. Set the INV11 bit to 0 when the INV06 bit in the INVC0 register is 1 (sawtooth wave modulation mode).

3. Set the PWCON bit in the TB2SC register to 0 (timer B2 register reloaded if timer B2 underflows) when the

INV11 bit is 0.

4. This bit setting is enabled when the INV06 bit is 0 (triangular wave modulation mode) and the INV11 bit is 1.

5. Set the INV16 bit to 1 when the following conditions are all met:

- The INV15 bit is 0.

- The Dij bit has a different value from the DiBj bit whenever the INV03 bit is 1 (enables the three-phase

motor control timer output); the high- and low-side output signals always have inverse levels on periods

other than dead time (i = U, V, or W; j = 0, 1).

Set the INV16 bit to 0 when the conditions above are not met.

INV10

INV11

INV12

INV13

INV14

INV15

INV16

—

(b7)

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R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.4 IOBC Register

b7 b6 b5 b4 b1b2b3 Symbol

IOBC

Address

40097h

Reset Value

0XXX XXXXb

FunctionBit Symbol Bit Name RW

—

Three-phase Output Buffer Control Register (1)

No register bits; should be written with 0 and read as undefined

value

Notes:

1. Set this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).

2. Set this bit after setting the INV02 bit in the INVC0 register to 1. Then, set the output function select register

of corresponding port. When the INV03 bit in the INVC0 register is 0, output pins for the three-phase motor

control timers become high-impedance by the output enable control of output buffers. However, the output

enable cannot be controlled only by the output function select register when more than two ports are

assigned for output. Thus, a three-state output buffer should be selected using the TBSOUT bit.

0: Use pins U, U, V, V, W, and W of

ports P7 and P8

1: Use pins U, U, V, V, W, and W of

port P3

Three-phase Output Pin

Select Bit (2)

INV02

INV03

U, U, V, V, W, and W of ports P7 and P8

U, U, V, V, W, and W of port P3

TBSOUT

Function select

U, U, V, V, W, W

—

(b6-b0)

TBSOUT

R01UH0211EJ0120 Rev.1.20 Page 234 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.5 Registers IDB0 and IDB1

V-phase Output Buffer i

W-phase Output Buffer i

V-phase Output Buffer i

W-phase Output Buffer i

U-phase Output Buffer i

Three-phase Output Buffer Register i (i = 0, 1) (1)

b7 b6 b5 b4 b1b2b3 b0 Symbol

IDB0, IDB1

Address

030Ah, 030Bh

Reset Value

XX11 1111b

FunctionBit Symbol Bit Name RW

These bits should be written with an

output level of the three-phase output

shift register. The written value is

reflected in each turn-on signal as

follows:

0: Active (ON)

1: Inactive (OFF)

The bits are read as the value of the

three-phase output shift register

U-phase Output Buffer i

Note:

1. Values of registers IDB0 and IDB1 are transferred to the three-phase output shift register by a transfer

trigger. The initial output signal level of each phase is determined by the value written in the IDB0 register

after the transfer trigger occurs. Then the output signal level is determined by the value written in the IDB1

DUi

DUBi

DVi

DVBi

DWi

DWBi

—

(b7-b6)

No register bits; should be written with 0 and read as undefined

value —

R01UH0211EJ0120 Rev.1.20 Page 235 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.6 ICTB2 Register

01h to 0Fh WO

Timer B2 Interrupt Generating Frequency Set Counter (1, 2, 3)

b7 b0 Symbol

ICTB2

Address

030Dh

Reset Value

Undefined

Function Setting Range RW

Notes:

1. Use the MOV instruction to set the ICTB2 register.

2. When the INV01 bit in the INVC0 register is 1, set this register while the TB2S bit in the TABSR register is 0

(timer B2 count stops). Although it can be set even when the TB2S bit is 1 (timer B2 count starts) when the

INV01 bit is 0, do not set this register when timer B2 underflows.

3. When the INV00 bit in the INVC0 register is set to 1, the first interrupt occurs when timer B2 underflows n-1

times. Subsequent interrupts occur every n times timer B2 underflows.

(n = setting value of the ICTB2 counter)

—No register bits; should be written with 0

- When the INV01 bit is 0 (ICTB2 counter increments each time

timer B2 underflows), a timer B2 interrupt request is generated

every nth times timer B2 underflows

- When the INV01 bit is 1 (ICTB2 counter increments when the

timer A1 reload control signal is set to 0 or 1 and timer B2

underflows), a timer B2 interrupt request is generated every

nth times timer B2 underflows when the timer A1 reload

control signal is 0 or 1

(n = setting value)

R01UH0211EJ0120 Rev.1.20 Page 236 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

17.1 Modulation Modes of Three-phase Motor Control Timers

The three-phase motor control timers support two modulation modes: triangular wave modulation mode

and sawtooth wave modulation mode. The triangular wave modulation mode has two modes: three-phase

mode 0 and three-phase mode 1. Table 17.2 lists bit settings and characteristics of each mode.

Note:

1. The transfer trigger is a timer B2 underflow, a write operation to the INV07 bit, or a write operation to

the TB2 register when the INV10 bit is 1.

Table 17.2 Modulation Modes

Item Triangular Wave Modulation Mode Sawtooth Wave

Modulation Mode

Three-phase mode 0 Three-phase mode 1 (Three-phase mode 0)

Bit settings INV06 is 0, INV11 is 0,

PWCON is 0

INV06 is 0, INV11 is 1 INV06 is 1, INV11 is 0,

PWCON is 0

Waveform Triangular wave Sawtooth wave

Registers TA11, TA21, and

TA41

Not used Used Not used

Timing to transfer data from

registers IDB0 and IDB1 to

the three-phase output shift

Only once when a transfer trigger (1) occurs after

setting registers IDB0 and IDB1

Whenever a transfer

trigger (1) occurs

Timing to trigger the dead

time timer when the INV16 bit

is 0

On the falling edge of a one-shot pulse of timers

A1, A2, and A4

When a transfer trigger

occurs, or on the falling

edge of a one-shot pulse

of timers A1, A2, and A4

Bits INV00 and INV01 in the

INVC0 register

Disabled. The ICTB2

counter increments each

time timer B2

underflows, irrespective

of the INV00 and INV01

bit settings

Enabled Disabled. The ICTB2

counter increments each

time timer B2

underflows, irrespective

of the INV00 and INV01

bit settings

INV13 bit Disabled Enabled Disabled

R01UH0211EJ0120 Rev.1.20 Page 237 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

17.2 Timer B2

Timer B2, which operates in timer mode, is used for carrier wave control in the three-phase motor control

timers.

Figures 17.7 and 17.8 show registers TB2 and TB2MR in this function, respectively. Figure 17.9 shows

the TB2SC register which switches timing to change the carrier wave frequency in three-phase mode 1.

Figure 17.7 TB2 Register When Using Three-phase Motor Control Timers

Figure 17.8 TB2MR Register When Using Three-phase Motor Control Timers

0000h to FFFFh RW

Timer B2 Register (1)

b15 b0 Symbol

TB2

Address

0355h-0354h

Reset Value

Undefined

Function Setting Range RW

Note:

1. A 16-bit read/write access to this register should be performed.

b7b8

Divides the count source by n+1. Starts timers A1, A2, and A4

each time an underflow occurs (n = setting value)

Timer B2 Mode Register

Symbol

TB2MR

Address

035Dh

Reset Value

00XX 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Should be written with 00b (timer

mode) when using the three-phase

motor control timers

Operating Mode Select Bit

Disabled when using the three-phase motor control timers. Should

be written with 0 and read as undefined value RW

—

No register bit; should be written with 0 and read as undefined

value

Disabled when using the three-phase motor control timers. Should

be written with 0 and read as undefined value —

b7 b6

00:f1

01:f8

10:f2n

11:fC32

Count Source Select Bit

0000

TMOD0

TMOD1

MR0

MR1

MR2

TCK0

TCK1

MR3

R01UH0211EJ0120 Rev.1.20 Page 238 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.9 TB2SC Register

Timer B2 Special Mode Register

b7 b6 b5 b4 b1b2b3 b0 Symbol

TB2SC

Address

035Eh

Reset Value

XXXX XXX0b

FunctionBit Symbol Bit Name RW

0: The underflow of timer B2

1: The underflow of timer B2 when

the reload control signal for timer

A1 is 0

Timer B2 Reload Timing

Switching Bit (1)

Note:

1. Set this bit to 0 when the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (sawtooth wave

modulation mode).

—

No register bits; should be written with 0 and read as undefined

value

PWCON

—

(b7-b1)

R01UH0211EJ0120 Rev.1.20 Page 239 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

17.3 Timers A4, A1, and A2

Timers A4, A1, and A2 are used for three-phase PWM output (U, U, V, V, W, and W) control when using

the three-phase motor control timers.

These timers should be operated in one-shot timer mode. Every time timer B2 underflows, a trigger is

input to timers A4, A1, and A2 to generate a one-shot pulse. If the values of registers TA4, TA1, and TA2

are rewritten every time a timer B2 interrupt occurs, the duty cycle of the PWM waveform can be varied.

In three-phase mode 1, the value of registers TAi and TAi-1 is alternately reloaded to the counter at each

timer B2 interrupt, which halves the timer B2 interrupt frequency (i = 4, 1, 2).

Figure 17.10 shows registers TA1, TA2, TA4, TA11, TA21, and TA41 in the three-phase motor control

timers. Figure 17.11 shows registers TA1MR, TA2MR, and TA4MR in this function. Figures 17.12 and

17.13 show registers TRGSR and TABSR, respectively, in this function.

Figure 17.10 Registers TA1, TA2, TA4, TA11, TA21, and TA41

0000h to FFFFh WO

Timer Ai/Timer Ai-1 Registers (i = 1, 2, 4) (1 to 6)

b15 b0 Symbol

TA1, TA2, TA4

TA11, TA21, TA41

Address

0349h-0348h, 034Bh-034Ah, 034Fh-034Eh

0303h-0302h, 0305h-0304h, 0307h-0306h

Reset Value

Undefined

Function Setting Range RW

Notes:

1. A 16-bit write access to these registers should be performed.

2. When these registers are set to 0000h, the counter does not start, and no timer Ai interrupt request is

generated.

3. Use the MOV instruction to set these registers.

4. When the INV15 bit in the INVC1 register is 0 (enables dead time), the turn-on output signal is switched to

its active state with a delay. It switches when the dead time timer stops.

5. When the INV11 bit in the INVC1 register is 0 (three-phase mode 0), the value of the TAi register is

transferred to the reload register by a timer Ai start trigger. When the INV11 bit is 1 (three-phase mode 1),

first the value of the TAi1 register is transferred to the reload register by a timer Ai start trigger. Then the

value of the TAi register is transferred by the next timer Ai start trigger. After that, the values of registers

TAi1 and TAi are alternately transferred to the reload register.

6. These registers should not be written when timer B2 underflows.

b7b8

The timer stops when the nth count source is counted after a

start trigger is generated. The output signal for each phase is

switched when timers A1, A2, and A4 stop (n = setting value)

R01UH0211EJ0120 Rev.1.20 Page 240 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.11 Registers TA1MR, TA2MR, and TA4MR When Using Three-phase Motor Control Timers

Timer Ai Mode Register (i = 1, 2, 4)

Symbol

TA1MR, TA2MR, TA4MR

Address

0357h, 0358h, 035Ah

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Should be written with 10b (one-shot

timer mode) when using the three-

phase motor control timers

Operating Mode Select Bit

RWShould be written with 0

External Trigger Select Bit RW

Should be written with 0 when using

the three-phase motor control timers

Trigger Select Bit RW

Should be written with 1 (selected by

the TRGSR register) when using the

three-phase motor control timers

Should be written with 0 when using the three-phase motor control

timers RW

b7 b6

00:f1

01:f8

10:f2n

11:fC32

Count Source Select Bit

Reserved

0 0 0 01 1

TMOD0

TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

R01UH0211EJ0120 Rev.1.20 Page 241 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.12 TRGSR Register in Three-phase Motor Control Timers

Figure 17.13 TABSR Register

Trigger Select Register

Symbol

TRGSR

Address

0343h

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Note:

1. The timer overflows or underflows.

Timer A1 Event/Trigger

Select Bit RW

Should be set to 01b (the underflow

of TB2) to use the V-phase output

control circuit

Timer A2 Event/Trigger

Select Bit RW

Timer A3 Event/Trigger

Select Bit

b5 b4

0 0 : Select the input to the TA3IN pin

0 1 : Select the overflow of TB2 (1)

1 0 : Select the overflow of TA2 (1)

1 1 : Select the overflow of TA4 (1)

Timer A4 Event/Trigger

Select Bit RW

Should be set to 01b (the underflow

of TB2) to the use W-phase output

control circuit

Should be set to 01b (the underflow

of TB2) to the use U-phase output

control circuit

TA1TGL

TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

Count Start Register

Symbol

TABSR

Address

0340h

Reset Value

0000 0000b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

RWTimer A0 Count Start Bit

RWTimer A1 Count Start Bit

RWTimer A2 Count Start Bit

RWTimer A3 Count Start Bit

RWTimer A4 Count Start Bit

RWTimer B0 Count Start Bit

RWTimer B1 Count Start Bit

RWTimer B2 Count Start Bit

TA0S

TA1S

TA2S

TA3S

TA4S

TB0S

TB1S

TB2S

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

0: Stop counter

1: Start counter

R01UH0211EJ0120 Rev.1.20 Page 242 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

17.4 Simultaneous Conduction Prevention and Dead Time Timer

The three-phase motor control timers offer two ways to avoid shoot-through, which occurs when high-side

and low-side transistors are simultaneously turned on.

One is “simultaneous turn-on signal output disable function”. This function prevents high-side and low-

side transistors from being inadvertently switched to active due to events like program errors. The other is

by the use of dead time timers. A dead time timer delays the turn-on of one transistor in order to ensure

that an adequate time (the dead time) passes after the other is turned off.

To disable simultaneous turn-on output signals, the INV04 bit in the INVC0 register should be set to 1. If

outputs for any pair of phases (U and U, V and V, or W and W) are simultaneously switched to an active

state, every three-phase motor control output pin becomes high-impedance. Figure 17.14 shows an

example of output waveform when simultaneous turn-on signal output is disabled.

To enable the dead time timer, the INV15 bit in the INVC1 register should be set to 0. The DTT register

determines the dead time. Figure 17.15 shows the DTT register and Figure 17.16 shows an example of

output waveform on using dead time timer.

Figure 17.14 Output Waveform When Simultaneous Turn-on Signal Output is Disabled

U-phase turn-on

signal output

U-phase turn-on

signal output

U-phase output signal

(internal signal)

U-phase output signal

(internal signal)

High-impedance

ON ON

ON OFF

OFF

OFF OFF

Simultaneous

turn-on signal

V-phase turn-on

signal output

V-phase turn-on

signal output

High-impedance

W-phase turn-on

signal output

W-phase turn-on

signal output

High-impedance

ON ONOFFOFF

ONON OFF OFF

R01UH0211EJ0120 Rev.1.20 Page 243 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.15 DTT Register

Figure 17.16 Output Waveform When Using Dead Time Timer

17.5 Three-phase Motor Control Timer Operation

Figures 17.17 and 17.18 show an operation example of triangular wave modulation and sawtooth wave

modulation, respectively.

01h to FFh WO

Dead Time Timer (1, 2)

b7 b0 Symbol

DTT

Address

030Ch

Reset Value

Undefined

Function Setting Range RW

Notes:

1. Use the MOV instruction to set this register.

2. This register setting is enabled when the INV15 bit in the INVC1 register is 0 (enables dead time). No dead

time can be set when the INV15 bit is 1 (disables dead time).

3. The trigger and count source should be selected using bits INV16 and INV12 in the INVC1 register,

respectively.

The dead time timer is a one-shot timer that delays the timing

for a turn-on signal to be switched to its active state

preventing a simultaneous conduction of high-side and low-

side transistors.

The timer stops when counting a count source n times after a

start trigger occurs (n = setting value) (3)

U-phase turn-on

signal output

U-phase turn-on

signal output

U-phase output signal

(internal signal)

U-phase output signal

(internal signal)

ON ON

ON OFF

OFF

OFF OFF

Dead time

ON ONOFFOFF

ONON OFF OFF

Dead timeDead timeDead time

Dead time timer

OFF

U-phase transistor

ON ONOFFOFF

ONON OFF OFF

OFF

R01UH0211EJ0120 Rev.1.20 Page 244 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.17 Triangular Wave Modulation Operation

Triangular carrier wave

Triangular wave

Reload control signal for

timer A1 (1)

TB2S bit in the

TABSR register

Signal wave

Timer B2

Start trigger signal for

timer A4 (1)

TA4 register (2)

TA41 register (2)

Reload register (2)

One-shot pulse of

timer A4 (1)

U-phase output

signal (1)

U-phase output

signal (1)

INV14 = 0

(active low)

INV14 = 1

(active high)

U-phase

Notes:

1. Internal signal. Refer to the block diagram of three-phase motor control timers.

2. Applicable when the INV11 bit in the INVC1 register is 1 (three-phase mode 1).

(B) When INV11 = 0 (three-phase mode 0)

- INV01 = 0 and ICTB2 = 1h (timer B2 interrupt occurs every time timer B2 underflows)

- TA4 register setting is varied every time a timer B2 interrupt occurs,

Default value: TA4 = a’

On the first timer B2 interrupt: TA4 = a; 2nd time: TA4 = b’; 3rd time: TA4 = b; 4th time: TA4 = c’; 5th time: TA4 = c

- Default value of registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1

On the sixth time: DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 0

a’ b’

a’ a b

Timer B2 interrupt

c’

d’

cd’ d

a’ ab’ bc’ cd’ d

d’c’c’b’b’a’

Dead time timer

output (1)

U-phase

This figure applies when INVC0 = 00XX11XXb (X varies depending on each system) and INVC1 = 010XXXX0b.

PWM output may vary as follows:

Dead time

Registers IDB0 and IDB1 are rewritten Rewritten value is

reflected here

(A) When INV11 = 1 (three-phase mode 1)

- INV01 = 0 and ICTB2 = 2h (timer B2 interrupt occurs every second time timer B2 underflows), or

INV01 = 1, INV00 = 1, and ICTB2 = 1h (timer B2 interrupt occurs every time timer B2 underflows when the

reload control signal for timer A1 is 1)

- The setting of registers TA4 and TA41 are varied every time a timer B2 interrupt occurs,

Default value: TA41 = a’, TA4 = a

On the first timer B2 interrupt: TA41 = b’, TA4 = b; the second time: TA41 = c’, TA4 = c

- Default value of registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1

On the third time: DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 0

R01UH0211EJ0120 Rev.1.20 Page 245 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

Figure 17.18 Sawtooth Wave Modulation Operation

Sawtooth carrier wave

Sawtooth wave

Start trigger signal

for timer A4 (1)

Signal wave

Timer B2

One-shot pulse of

timer A4 (1)

U-phase output

signal (1)

Registers IDB0 and IDB1 are rewritten

This figure applies when INVC0 = 01XX110Xb (X varies depending on each system) and INVC1 = 000XXX00b.

This bit setting is applicable to turn-on control with a phase shift of 120 degrees.

PWM output may vary as follows:

Default value of registers IDB0 and IDB1: DU0 = 0, DUB0 = 1, DU1 = 1, DUB1 = 1

On the third timer B2 interrupt: DU0 = 1, DUB0 = 1, DU1 = 1, DUB1 = 1

On the fifth timer B2 interrupt: DU0 = 1, DUB0 = 0, DU1 = 1, DUB1 = 1

U-phase output

signal (1)

Rewritten value is reflected here

INV14 = 0

(active low)

INV14 = 1

(active high)

U-phase

Dead time timer

output (1)

Dead time

Note:

1. Internal signal. Refer to the block diagram of three-phase motor control timers.

R01UH0211EJ0120 Rev.1.20 Page 246 of 604

Feb 18, 2013

R32C/117 Group 17. Three-phase Motor Control Timers

17.6 Notes on Three-phase Motor Control Timers

17.6.1 Shutdown

• When a low signal is applied to the NMI pin with the following bit settings, pins TA1OUT, TA2OUT,

and TA4OUT become high-impedance: the PM24 bit in the PM2 register is 1 (NMI enabled), the

INV02 bit in the INVC0 register is 1 (three-phase motor control timers used), and the INV03 bit is 1

(three-phase motor control timer output enabled).

17.6.2 Register Setting

• Do not write to the TAi1 register before and after timer B2 underflows (i = 1, 2, 4). Before writing to

the TAi1 register, read the TB2 register to verify that sufficient time remains until timer B2

underflows. Then, immediately write to the TAi1 register so no interrupt handling is performed

during this write procedure. If the TB2 register indicates little time remains until the underflow, write

to the TAi1 register after timer B2 underflows.

R01UH0211EJ0120 Rev.1.20 Page 247 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

18. Serial Interface

The serial interface consists of nine channels: UART0 to UART8.

Each channel has an exclusive timer to generate the transmit/receive clock and operates independently.

Figures 18.1 and 18.2 show block diagrams of UART0 to UART6 and UART7 and UART8, respectively.

UARTi supports the following modes:

• Synchronous serial interface mode (for UART0 to UART8)

• Asynchronous serial interface mode (UART mode) (for UART0 to UART8)

• Special mode 1 (I2C mode) (for UART0 to UART6)

• Special mode 2 (for UART0 to UART6)

• Special mode 4 (Bus collision detection: IE mode) (optional) (1) (for UART0 to UART6)

Figures 18.3 to 18.19 show registers associated with UARTi (i = 0 to 8).

Refer to the tables listing each mode for registers and pin settings.

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Table 18.1 Comparison of UART0 to UART8 Functions

Mode/Function UART0 to UART6 UART7, UART8

Synchronous serial interface mode Available Available

Serial data logic inversion Available Not available

UART mode Available Available

CTS/RTS function selection Available Available

TXD and RXD I/O polarity selection Available Not available

Special mode 1 (I2C mode) Available Not available

Special mode 2 Available Not available

Special mode 4 (IE mode) (optional) (1) Available Not available

Pins TXD and RXD output mode Push-pull output, N-channel

open drain output

programmable by port

function select registers

Push-pull output, N-channel

open drain output

programmable by port

function select registers

R01UH0211EJ0120 Rev.1.20 Page 248 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.1 UARTi Block Diagram (i = 0 to 6)

m = Value set in the UiBRG register

TXDi

CKPOL

CLKi

CTSi/RTSi

010, 100, 101, 110

SMD2 to SMD0

f2n

CLK1 and CLK0

PAR

Logic inversion circuit + Bit order reverse circuit

IOPOL

STPS PRYE

001,

010

001,

101

UiRB register

010,

110

UARTi receive register

100

Upper byte of data bus

Lower byte of data bus

SP: Stop bit

PAR: Parity bit

SMD2 to SMD0, STPS, PRYE, IOPOL, and CKDIR: Bits in the UiMR register

CLK1, CLK0, CKPOL, and CRD: Bits in the UiC0 register

RXDi

RTSi

CTSi

CKDIR UiBRG

CKDIR

001

001,

010,

101,

110

Receive

clock

Transmit

clock

b0b1b2b3b4b5b6

UiTB register

UARTi transmit register

010, 100, 101, 110

001

Receive control

circuit

Transmit control

circuit

Transmit/

receive

unit

TXD polarity

switch circuit

RXD polarity

switch circuit

1/(m+1) 1/16

1/16

1/2

CLK polarity

switch circuit

CKDIR

CRD

RXDi

100,

101,

110

SP b8

0000000D8 D7 D6 D5 D4 D3 D2 D1 D0

Logic inversion circuit + Bit order reverse circuit

D7 D6 D5 D4 D3 D2 D1 D0

b0b1b2b3b4b5b6b7

001,

010

001,

101

010,

110

100

001,

010,

101,

110

100,

101,

110

PAR

STPS PRYE

SMD2 to SMD0

IOPOL

TXDi

Direction register

R01UH0211EJ0120 Rev.1.20 Page 249 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.2 UARTi Block Diagram (i = 7, 8)

m = Value set in the UiBRG register

TXDi

CKPOL

CLKi

CTSi/RTSi

100, 101, 110

SMD2 to SMD0

f2n

CLK1 and CLK0

PAR

Logic inversion circuit + Bit order reverse circuit

STPS PRYE 001

001,

101

UiRB register

110

UARTi receive register

100

Upper byte of data bus

Lower byte of data bus

SP: Stop bit

PAR: Parity bit

SMD2 to SMD0, STPS, PRYE, IOPOL, and CKDIR: Bits in the UiMR register

CLK1, CLK0, CKPOL, and CRD: Bits in the UiC0 register

RXDi

RTSi

CTSi

CKDIR UiBRG

CKDIR

001

001,

101,

110

Receive

clock

Transmit

clock

b0b1b2b3b4b5b6

UiTB register

UARTi transmit register

100, 101, 110

001

Receive control

circuit

Transmit control

circuit

Transmit/

receive

unit

1/(m+1) 1/16

1/16

1/2

CLK polarity

switch circuit

CKDIR

CRD

RXDi

100,

101,

110

SP b8

0000000D8 D7 D6 D5 D4 D3 D2 D1 D0

Logic inversion circuit + Bit order reverse circuit

D7 D6 D5 D4 D3 D2 D1 D0

b0b1b2b3b4b5b6b7

001

001,

101

110

100

001,

101,

110

100,

101,

110

PAR

STPS PRYE

SMD2 to SMD0

TXDi

Direction register

R01UH0211EJ0120 Rev.1.20 Page 250 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.3 Registers U0MR to U6MR

UARTi Transmit/Receive Mode Register (i = 0 to 6)

Symbol

U0MR to U3MR

U4MR to U6MR

Address

0368h, 02E8h, 0338h, 0328h

02F8h, 01C8h, 01D8h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

Serial Interface Mode

Select Bit

b2 b1 b0

0 0 0 : Serial interface disabled

0 0 1 : Synchronous serial interface

mode

010:I

2C mode

1 0 0 : UART mode, 7-bit character

length

1 0 1 : UART mode, 8-bit character

length

1 1 0 : UART mode, 9-bit character

length

Only use the combinations listed

above

0: Internal clock

1: External clock

Internal/External Clock

Select Bit

0: 1 stop bit

1: 2 stop bits

Stop Bit Length Select Bit

Enabled when the PRYE bit is 1

0: Odd parity

1: Even parity

Odd/Even Parity Select Bit

0: Parity disabled

1: Parity enabled

Parity Enable Bit

0: Not inverted

1: Inverted

TXD, RXD Input/Output

Polarity Switch Bit

b7 b6 b5 b4 b1b2b3 b0

SMD0

SMD1

SMD2

CKDIR

STPS

PRY

PRYE

IOPOL

R01UH0211EJ0120 Rev.1.20 Page 251 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.4 Registers U7MR and U8MR

UARTi Transmit/Receive Mode Register (i = 7, 8)

Symbol

U7MR, U8MR

Address

01E0h, 01E8h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

Serial Interface Mode

Select Bit

b2 b1 b0

0 0 0 : Serial interface disabled

0 0 1 : Synchronous serial interface

mode

1 0 0 : UART mode, 7-bit character

length

1 0 1 : UART mode, 8-bit character

length

1 1 0 : UART mode, 9-bit character

length

Only use the combinations listed

above

b7 b6 b5 b4 b1b2b3 b0

SMD0

SMD1

SMD2

0: Internal clock

1: External clock

Internal/External Clock

Select Bit

0: 1 stop bit

1: 2 stop bits

Stop Bit Length Select Bit

Enabled when the PRYE bit is 1

0: Odd parity

1: Even parity

Odd/Even Parity Select Bit

0: Parity disabled

1: Parity enabled

Parity Enable Bit

RWShould be written with 0Reserved

CKDIR

STPS

PRY

PRYE

—

(b7)

R01UH0211EJ0120 Rev.1.20 Page 252 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.5 Registers U0C0 to U6C0

UARTi Transmit/Receive Control Register 0 (i = 0 to 6)

Symbol

U0C0 to U3C0

U4C0 to U6C0

Address

036Ch, 02ECh, 033Ch, 032Ch

02FCh, 01CCh, 01DCh

Reset Value

0000 1000b

RWFunctionBit Symbol Bit Name

UiBRG Count Source

Select Bit

0: Data held in the transmit shift

1: No data held in the transmit shift

Transmit Shift Register

Empty Flag

0: CTS function enabled

1: CTS function disabled

CTS Function Disable Bit

0: Output transmit data on the falling

edge of the transmit/receive clock

and input receive data on the rising

edge

1: Output transmit data on the rising

edge of the transmit/receive clock

and input receive data on the

falling edge

CLK Polarity Select Bit

0: LSB first

1: MSB first

Bit Order Select Bit (1)

b7 b6 b5 b4 b1b2b3 b0

b1 b0

00:f1

01:f8

10:f2n

1 1 : Do not use this combination

Reserved Should be written with 0

Note:

1. This bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (synchronous serial

interface mode) or 101b (UART mode, 8-bit character length). It should be set to 1 when bits SMD2 to

SMD0 are set to 010b (I2C mode) and should be set to 0 when they are set to 100b (UART mode, 7-bit

character length) or 110b (UART mode, 9-bit character length).

0 0

CLK0

CLK1

—

(b2)

TXEPT

CRD

CKPOL

UFORM

RWReserved Should be written with 0

—

(b5)

R01UH0211EJ0120 Rev.1.20 Page 253 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.6 Registers U7C0 and U8C0

UARTi Transmit/Receive Control Register 0 (i = 7, 8)

Symbol

U7C0, U8C0

Address

01E4h, 01ECh

Reset Value

00X0 1000b

RWFunctionBit Symbol Bit Name

UiBRG Count Source

Select Bit

0: Data held in the transmit shift

1: No data held in the transmit shift

Transmit Shift Register

Empty Flag

0: CTS function enabled

1: CTS function disabled

CTS Function Disable Bit

0: Output transmit data on the falling

edge of the transmit/receive clock

and input receive data on the rising

edge

1: Output transmit data on the rising

edge of the transmit/receive clock

and input receive data on the

falling edge

CLK Polarity Select Bit

0: LSB first

1: MSB first

Bit Order Select Bit (1)

b7 b6 b5 b4 b1b2b3 b0

b1 b0

00:f1

01:f8

10:f2n

1 1 : Do not use this combination

Reserved Should be written with 0

Note:

1. This bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (synchronous serial

interface mode) or 101b (UART mode, 8-bit character length). It should be set to 0 when they are set to

100b (UART mode, 7-bit character length) or 110b (UART mode, 9-bit character length).

—

No register bit; should be written with 0 and read as undefined

value

CLK0

CLK1

—

(b2)

TXEPT

CRD

—

(b5)

CKPOL

UFORM

R01UH0211EJ0120 Rev.1.20 Page 254 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.7 Registers U0C1 to U6C1

Figure 18.8 Registers U7C1 and U8C1

UARTi Transmit/Receive Control Register 1 (i = 0 to 6)

Symbol

U0C1 to U3C1

U4C1 to U6C1

Address

036Dh, 02EDh, 033Dh, 032Dh

02FDh, 01CDh, 01DDh

Reset Value

0000 0010b

RWFunctionBit Symbol Bit Name

Transmit Enable Bit RW

0: Transmit buffer is empty (TI = 1)

1: Transmission is completed

(TXEPT = 1)

UARTi Transmit Interrupt

Source Select Bit

0: Continuous receive mode disabled

1: Continuous receive mode enabled

UARTi Continuous Receive

Mode Enable Bit

0: Data is not logic inverted

1: Data is logic inverted

Logic Inversion Select Bit

(1)

b7 b6 b5 b4 b1b2b3 b0

0: Transmission disabled

1: Transmission enabled

Transmit Buffer Empty Flag 0: Data held in the UiTB register

1: No data held in the UiTB register

Receive Enable Bit 0: Reception disabled

1: Reception enabled

ROReceive Complete Flag 0: No data held in the UiRB register

1: Data held in the UiRB register

Note:

1. This bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (synchronous serial

interface mode), 100b (UART mode, 7-bit character length), or 101b (UART mode, 8-bit character length).

Set this bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, 9-bit character

length).

UiIRS

UiRRM

UiLCH

Reserved

—

(b7) Should be written with 0

UARTi Transmit/Receive Control Register 1 (i = 7, 8)

Symbol

U7C1, U8C1

Address

01E5h, 01EDh

Reset Value

XXXX 0010b

RWFunctionBit Symbol Bit Name

Transmit Enable Bit RW

No register bits; should be written with 0 and read as undefined

value

b7 b6 b5 b4 b1b2b3 b0

0: Transmission disabled

1: Transmission enabled

Transmit Buffer Empty Flag 0: Data held in the UiTB register

1: No data held in the UiTB register

Receive Enable Bit 0: Reception disabled

1: Reception enabled

ROReceive Complete Flag 0: No data held in the UiRB register

1: Data held in the UiRB register

—

(b7-b4) —

R01UH0211EJ0120 Rev.1.20 Page 255 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.9 U78CON Register

UART7, UART8 Transmit/Receive Control Register 2

Symbol

U78CON

Address

01F0h

Reset Value

X000 0000b

RWFunctionBit Symbol Bit Name

UART7 Transmit Interrupt

Source Select Bit RW

b7 b6 b5 b4 b1b2b3 b0

0: Transmit buffer is empty (TI = 1)

1: Transmission is completed

(TXEPT = 1)

UART8 Transmit Interrupt

Source Select Bit

0: Transmit buffer is empty (TI = 1)

1: Transmission is completed

(TXEPT = 1)

000

U7IRS

U8IRS

No register bit; should be written with 0 and read as undefined

value

UART7 Continuous

Receive Mode Enable Bit

0: Continuous receive mode disabled

1: Continuous receive mode enabled

UART8 Continuous

Receive Mode Enable Bit

0: Continuous receive mode disabled

1: Continuous receive mode enabled

RWReserved Should be written with 0

—

(b6-b4)

U8RRM

U7RRM

—

(b7) —

R01UH0211EJ0120 Rev.1.20 Page 256 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.10 Registers U0SMR to U6SMR

UARTi Special Mode Register (i = 0 to 6)

Symbol

U0SMR to U3SMR

U4SMR to U6SMR

Address

0367h, 02E7h, 0337h, 0327h

02F7h, 01C7h, 01D7h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

I2C Mode Select Bit (1) RW

0: Rising edge of the transmit/receive

clock

1: Underflow of timer Aj (j = 0, 3, 4) (4)

Bus Collision Detect

Sampling Clock Select Bit

(3)

0: No auto-reset to zero

1: Auto-reset to zero at bus collision

Transmit Enable Bit Auto-

reset to Zero Select Bit (3)

0: No relation with RXDi

1: Synchronized with RXDi

Transmit START Condition

Select Bit (3)

RWShould be written with 0Reserved

b7 b6 b5 b4 b1b2b3 b0

0: Mode other than I2C mode

1: I2C mode

Arbitration Lost Detection

Flag Control (1)

0: Update every bit

1: Update every byte

Bus Busy Flag (1, 2) 0: Detect STOP condition

1: Detect START condition (bus busy)

RWReserved Should be written with 0

Notes:

1. This bit is used in I2C mode.

2. The BBS bit can only be set to 0. Writing 1 to this bit has no effect.

3. This bit is used in IE mode.

4. UART0: timer A3 underflow signal, UART1: timer A4 underflow signal

UART2: timer A0 underflow signal, UART3: timer A3 underflow signal

UART4: timer A4 underflow signal, UART5: timer A3 underflow signal

UART6: timer A4 underflow signal

0 0

ABC

IICM

—

(b3)

ACSE

SSS

BBS

ABSCS

—

(b7)

R01UH0211EJ0120 Rev.1.20 Page 257 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.11 Registers U0SMR2 to U6SMR2

UARTi Special Mode Register 2 (i = 0 to 6)

Symbol

U0SMR2 to U3SMR2

U4SMR2 to U6SMR2

Address

0366h, 02E6h, 0336h, 0326h

02F6h, 01C6h, 01D6h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

I2C Mode Select Bit 2 RW

0: Output the transmit/receive clock

at the SCLi pin

1: Hold the SCLi pin low

UARTi Auto Initialize Bit (2)

RWSCL Wait Output Bit 2 (1)

0: Output data

1: Stop the output (high-impedance)

SDA Output Stop Bit (2)

b7 b6 b5 b4 b1b2b3 b0

Clock Synchronization Bit

(1)

SCL Wait Auto Insert Bit (2)

SDA Output Auto Stop Bit

(1)

When an arbitration lost is detected,

0: Do not stop the SDAi output

1: Stop the SDAi output

Notes:

1. This bit is used in master mode of I2C mode.

2. This bit is used in slave mode of I2C mode.

0: Use ACK/NACK interrupt

1: Use transmit/receive interrupt

0: Clock synchronization disabled

1: Clock synchronization enabled

0: No wait-state/wait-state cleared

1: Hold the SCLi pin low after the

eighth bit is received

When a START condition is detected,

0: Do not initialize the circuit

1: Initialize the circuit

IICM2

CSC

SWC

ALS

STC

SWC2

SDHI

—

(b7) Reserved Should be written with 0

R01UH0211EJ0120 Rev.1.20 Page 258 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.12 Registers U0SMR3 to U6SMR3

UARTi Special Mode Register 3 (i = 0 to 6)

Symbol

U0SMR3 to U3SMR3

U4SMR3 to U6SMR3

Address

0365h, 02E5h, 0335h, 0325h

02F5h, 01C5h, 01D5h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

SS Pin Function Enable Bit

(1, 2) RW

Based on the baud rate generator

count source, the SDAi output is

delayed as follows:

b7 b6 b5

0 0 0 : No delay

0 0 1 : 1 to 2 cycles

0 1 0 : 2 to 3 cycles

0 1 1 : 3 to 4 cycles

1 0 0 : 4 to 5 cycles

1 0 1 : 5 to 6 cycles

1 1 0 : 6 to 7 cycles

1 1 1 : 7 to 8 cycles

RWMode Fault Flag (1)

SDAi Digital Delay Time

Set Bit (4, 5) RW

b7 b6 b5 b4 b1b2b3 b0

0: SS function disabled

1: SS function enabled

0: No clock delay

1: Clock delayed

0: Select the TXDi/RXDi pin (master

mode)

1: Select the STXDi/SRXDi pin (slave

mode)

Clock-phase Set Bit

Serial Input Pin Set Bit (1)

0: No mode fault detected

1: Mode fault detected (3)

Notes:

1. This bit is used in special mode 2.

2. Set the CRD bit in the UiC0 register to 1 (CTS function disabled) to use the SS function.

3. The ERR bit can only be set to 0. Writing 1 to this bit has no effect.

4. Bits DL2 to DL0 in I2C mode generate a digital delay for the SDAi output. Set these bits to 000b in all modes

other than I2C mode.

5. When an external clock is selected, a delay of approximately 100 ns is added.

SSE

CKPH

DINC

ERR

DL0

DL1

DL2

—

(b3) Reserved Should be written with 0 RW

R01UH0211EJ0120 Rev.1.20 Page 259 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.13 Registers U0SMR4 to U6SMR4

Figure 18.14 Registers U0BRG to U8BRG

UARTi Special Mode Register 4 (i = 0 to 6)

Symbol

U0SMR4 to U3SMR4

U4SMR4 to U6SMR4

Address

0364h, 02E4h, 0334h, 0324h

02F4h, 01C4h, 01D4h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

START Condition Generate

Bit (1) RW

0: ACK

1: NACK

ACK Data Bit (4)

0: Serial data output

1: ACK data output

ACK Data Output Enable

Bit (4)

When a STOP condition is detected,

0: Do not stop SCLi output

1: Stop SCLi output

SCL Output Stop Bit (1)

SCL Wait Auto Insert Bit 3

(4)

b7 b6 b5 b4 b1b2b3 b0

0: Clear

1: Start (2)

SCL, SDA Output Select

Bit (1)

0: Select serial I/O circuit

1: Select START condition/STOP

condition generation circuit (3)

Notes:

1. This bit is used in master mode of I2C mode. It can be set to 1 when the IICM bit in the UiSMR register is 1

(I2C mode).

2. This bit becomes 0 when the condition is generated. The setting remains 1 when the condition is

incomplete.

3. Set the STSPSEL bit to 1 after setting the STAREQ, RSTAREQ, or STPREQ bit to 1.

4. This bit is used in slave mode of I2C mode. It can be set to 1 when the IICM bit in the UiSMR register is 1

(I2C mode).

0: Clear

1: Start (2)

0: Clear

1: Start (2) RW

0: No wait-state/wait-state cleared

1: Hold the SCLi pin low after the

ninth bit is received

Repeated START

Condition Generate Bit (1)

STOP Condition Generate

Bit (1)

STAREQ

RSTAREQ

STPREQ

STSPSEL

ACKD

ACKC

SCLHI

SWC9

UARTi Bit Rate Register (i = 0 to 8) (1, 2, 3)

Symbol

U0BRG to U3BRG

U4BRG to U7BRG

U8BRG

Address

0369h, 02E9h, 0339h, 0329h

02F9h, 01C9h, 01D9h, 01E1h

01E9h

Reset Value

Undefined

Notes:

1. Set bits CLK1 and CLK0 in the UiC0 register before rewriting this register.

2. Use the MOV instruction to set this register.

3. Write this register while no data is being transmitted/received.

b7 b0

Setting RangeFunction

WO00h to FFh

The UiBRG register divides the count source by n+1

(n = setting value)

R01UH0211EJ0120 Rev.1.20 Page 260 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.15 Registers U0TB to U8TB

Figure 18.16 Registers U0RB to U6RB

UARTi Transmit Buffer Register (i = 0 to 8) (1)

Symbol

U0TB to U2TB

U3TB to U5TB

U6TB to U8TB

Address

036Bh-036Ah, 02EBh-02EAh, 033Bh-033Ah

032Bh-032Ah, 02FBh-02FAh, 01CBh-01CAh

01DBh-01DAh, 01E3h-01E2h, 01EBh-01EAh

Reset Value

Undefined

FunctionBit Symbol RW

WOData (D7 to D0) to be transmitted

WOData (D8) to be transmitted

—No register bits; should be written with 0

Note:

1. Use the MOV instruction to set this register.

b15 b7 b0b8

—

(b7-b0)

—

(b8)

—

(b15-b9)

UARTi Receive Buffer Register (i = 0 to 6)

Symbol

U0RB to U2RB

U3RB to U5RB

U6RB

Address

036Fh-036Eh, 02EFh-02EEh, 033Fh-033Eh

032Fh-032Eh, 02FFh-02FEh, 01CFh-01CEh

01DFh-01DEh

Reset Value

Undefined

FunctionBit Symbol RW

ROData (D7 to D0) received

ROData (D8) received

—No register bits; should be written with 0 and read as 0

Notes:

1. The ABT bit can only be set to 0.

2. Bits OER, FER, PER, and SUM become 0 when bits SMD2 to SMD0 in the UiMR register are set to 000b

(serial interface disabled) or the RE bit in the UiC1 register is set to 0 (reception disabled). When bits OER,

FER, and PER all become 0, the SUM bit also becomes 0. Bits FER and PER become 0 when the lower

byte in the UiRB register is read.

3. When bits SMD2 to SMD0 are 001b (synchronous serial interface mode) or 010b (I2C mode), these error

flags are disabled and read as an undefined value.

b15 b7 b0b8

Bit Name

—

0: Not detected (win)

1: Detected (lose)

Arbitration Lost Detection

Flag (1)

0: No overrun error occurred

1: Overrun error occurred

Overrun Error Flag (2)

0: No framing error occurred

1: Framing error occurred

Framing Error Flag (2, 3)

0: No parity error occurred

1: Parity error occurred

Parity Error Flag (2, 3)

0: No error occurred

1: Error occurred

Error Sum Flag (2, 3)

—

(b7-b0)

FER

OER

ABT

—

(b10-b9)

—

(b8)

PER

SUM

R01UH0211EJ0120 Rev.1.20 Page 261 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.17 Registers U7RB and U8RB

UARTi Receive Buffer Register (i = 7, 8)

Symbol

U7RB, U8RB

Address

01E7h-01E6h, 01EFh-01EEh

Reset Value

Undefined

FunctionBit Symbol RW

ROData (D7 to D0) received

ROData (D8) received

—No register bits; should be written with 0 and read as 0

Notes:

1. Bits OER, FER, PER, and SUM become 0 when bits SMD2 to SMD0 in the UiMR register are set to 000b

(serial interface disabled) or the RE bit in the UiC1 register is set to 0 (reception disabled). When bits OER,

FER, and PER all become 0, the SUM bit also becomes 0. Bits FER and PER become 0 when the lower

byte in the UiRB register is read.

2. When bits SMD2 to SMD0 are 001b (synchronous serial interface mode) or 010b (I2C mode), these error

flags are disabled and read as an undefined value.

b15 b7 b0b8

Bit Name

—

0: No overrun error occurred

1: Overrun error occurred

Overrun Error Flag (1)

0: No framing error occurred

1: Framing error occurred

Framing Error Flag (1, 2)

0: No parity error occurred

1: Parity error occurred

Parity Error Flag (1, 2)

0: No error occurred

1: Error occurred

Error Sum Flag (1, 2)

—

(b7-b0)

—

(b8)

—

(b11-b9)

OER

FER

PER

SUM

R01UH0211EJ0120 Rev.1.20 Page 262 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.18 IFSR0 Register

b7 b6 b5 b4 b1b2b3 Symbol

IFSR0

Address

4406Fh

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

External Interrupt Request Source Select Register 0

Note:

1. Set this bit to 0 to select the level sensitive input as trigger. To set this bit to 1, set the POL bit in the

corresponding INTiIC register to 0 (falling edge) (i = 0 to 5).

0: One edge

1: Both edges

INT0 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT1 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT2 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT3 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT4 Pin Polarity Select Bit

(1)

0: One edge

1: Both edges

INT5 Pin Polarity Select Bit

(1)

0: Bus collision, START condition

detection, STOP condition detection

in UART3

1: Bus collision, START condition

detection, STOP condition detection

in UART0

UART0/UART3 Interrupt

Source Select Bit

0: Bus collision, START condition

detection, STOP condition detection

in UART4

1: Bus collision, START condition

detection, STOP condition detection

in UART1

UART1/UART4 Interrupt

Source Select Bit

IFSR00

IFSR01

IFSR02

IFSR03

IFSR04

IFSR05

IFSR06

IFSR07

R01UH0211EJ0120 Rev.1.20 Page 263 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

Figure 18.19 IFSR1 Register

b7 b6 b5 b4 b1b2b3 Symbol

IFSR1

Address

4406Dh

Reset Value

X0XX X000b

FunctionBit Symbol Bit Name RW

External Interrupt Request Source Select Register 1

Note:

1. Set this bit to 0 to select the level sensitive input as trigger. To set this bit to 1, set the POL bit in the

corresponding INTiIC register (i = 6 to 8) to 0 (falling edge).

IFSR10 RW

0: One edge

1: Both edges

INT6 Pin Polarity Select Bit

(1)

IFSR11 RW

0: One edge

1: Both edges

INT7 Pin Polarity Select Bit

(1)

IFSR12 RW

0: One edge

1: Both edges

INT8 Pin Polarity Select Bit

(1)

IFSR16 RW

0: Bus collision, START condition

detection, STOP condition detection

in UART5

1: Bus collision, START condition

detection, STOP condition detection

in UART6

UART5/UART6 Interrupt

Source Select Bit

—

No register bit; should be written with 0 and read as undefined

value

—

(b7)

—

No register bits; should be written with 0 and read as undefined

value

—

(b5-b3)

R01UH0211EJ0120 Rev.1.20 Page 264 of 604

Feb 18, 2013

R32C/117 Group 18. Serial Interface

18.1 Synchronous Serial Interface Mode

The synchronous serial interface mode allows data transmission/reception synchronized with the

transmit/receive clock. Table 18.2 lists specifications of synchronous serial interface mode.

Notes:

1. When selecting an external clock, the following preconditions should be met:

• The CLKi pin is held high when the CKPOL bit in the UiC0 register is set to 0 (transmit data output

on the falling edge of the transmit/receive clock and receive data input on the rising edge).

• The CLKi pin is held low when the CKPOL bit is set to 1 (transmit data output on the rising edge of

the transmit/receive clock and receive data input on the falling edge).

2. The UiRB register is undefined when an overrun error occurs. The IR bit in the SiRIC register does

not change to 1 (interrupt requested).

Table 18.2 Synchronous Serial Interface Mode Specifications

Item Specification

Data format 8-bit character length

Transmit/receive clock • The CKDIR bit in the UiMR register is 0 (internal clock) (i = 0 to 8):

fx = f1, f8, f2n; m: UiBRG register setting value, 00h to FFh

• The CKDIR bit is 1 (external clock): input to the CLKi pin

Transmit/receive control CTS function enabled, RTS function enabled, or CTS/RTS function disabled

Transmit start conditions The conditions for starting data transmission are as follows (1):

• The TE bit in the UiC1 register is 1 (transmission enabled)

• The TI bit in the UiC1 register is 0 (data held in the UiTB register)

• Input level at the CTSi pin is low when the CTS function is selected

Receive start conditions The conditions for starting data reception are as follows (1):

• The RE bit in the UiC1 register is 1 (reception enabled)

• The TE bit in the UiC1 register is 1 (transmission enabled)

• The TI bit in the UiC1 register is 0 (data held in the UiTB register)

• Input level at the CTSi pin is low when the CTS function is selected

Interrupt request

generating timing

In transmit interrupt, one of the following conditions can be selected by setting

the UiIRS bit in registers U0C1 to U6C1 and U78CON:

• The UiIRS bit is 0 (transmit buffer is empty):

when data is transferred from the UiTB register to the UARTi transmit register

(when the transmission has started)

• The UiIRS bit is 1 (transmission is completed):

when data transmission from the UARTi transmit register is completed

In receive interrupt,

• When data is transferred from the UARTi receive register to the UiRB register

(when the reception is completed)

Error detection Overrun error (2)

This error occurs when the seventh bit of the next data is received before the

UiRB register is read

Other functions • CLK polarity

Rising or falling edge of the transmit/receive clock for output and input of

transmit/receive data

• Bit order selection

LSB first or MSB first

• Continuous receive mode

Data reception is enabled by a read access to the UiRB register

• Serial data logic inversion (UART0 to UART6)

This function logically inverses transmit/receive data

2m1+

---------------------

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R32C/117 Group 18. Serial Interface

Tables 18.3 and 18.4 list register settings. When UARTi operating mode is selected, a high is output at the

TXDi pin until transmission starts (the TXDi pin is high-impedance when the N-channel open drain output

is selected) (i = 0 to 8).

Figures 18.20 and 18.21 show examples of transmit and receive operations in synchronous serial

interface mode, respectively.

Table 18.3 Register Settings in Synchronous Serial Interface Mode (for UART0 to UART6)

UiMR 7 to 4 Set the bits to 0000b

CKDIR Select either an internal clock or external clock

SMD2 to SMD0 Set the bits to 001b

UiC0 UFORM Select either LSB first or MSB first

CKPOL Select a transmit/receive clock polarity

5 Set the bit to 0

CRD Select CTS function enabled or disabled

TXEPT Transmit register empty flag

2 Set the bit to 0

CLK1 and CLK0 Select a count source for the UiBRG register

UiC1 7 Set the bit to 0

UiLCH Set the bit to 1 to use logic inversion

UiRRM Set the bit to 1 to use continuous receive mode

UiIRS Select a source for the UARTi transmit interrupt

RI Receive complete flag

RE Set the bit to 1 to enable data reception

TI Transmit buffer empty flag

TE Set the bit to 1 to enable data transmission/reception

UiSMR 7 to 0 Set the bits to 00h

UiSMR2 7 to 0 Set the bits to 00h

UiSMR3 7 to 0 Set the bits to 00h

UiSMR4 7 to 0 Set the bits to 00h

UiBRG 7 to 0 Set the bit rate

IFS0 IFS06 Select input pins for CLK3, RXD3, and CTS3

IFS03 and IFS02 Select input pins for CLK6, RXD6, and CTS6

UiTB 7 to 0 Set the data to be transmitted

UiRB OER Overrun error flag

7 to 0 Received data is read

i = 0 to 6

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Table 18.4 Register Settings in Synchronous Serial Interface Mode (for UART7 and UART8)

UiMR 7 to 4 Set the bits to 0000b

CKDIR Select an internal clock or external clock

SMD2 to SMD0 Set the bits to 001b

UiC0 UFORM Select either LSB first or MSB first

CKPOL Select a transmit/receive clock polarity

5 Set the bit to 0

CRD Select CTS function enabled or disabled

TXEPT Transmit register empty flag

2 Set the bit to 0

CLK1 and CLK0 Select a count source for the UiBRG register

UiC1 RI Receive complete flag

RE Set the bit to 1 to enable data reception

TI Transmit buffer empty flag

TE Set the bit to 1 to enable data transmission/reception

U78CON UiRRM Set the bit to 1 to use continuous receive mode

UiIRS Select an interrupt source for UARTi transmit

IFS0 IFS05 Select input pins for CLK7, RXD7, and CTS7

IFS04 Select input pins for CLK8, RXD8, and CTS8

UiBRG 7 to 0 Set the bit rate

UiTB 7 to 0 Set the data to be transmitted

UiRB OER Overrun error flag

7 to 0 Received data can be read

i = 7, 8

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R32C/117 Group 18. Serial Interface

Figure 18.20 Transmit Operation in Synchronous Serial Interface Mode

Internal transmit/

receive clock

Transmit timing (when selecting an internal clock)

TE bit in the

UiC1 register

TI bit in the

UiC1 register

CTSi

CLKi

TXDi

TXEPT bit in the

UiC0 register

IR bit in the

SiTIC register

This figure applies under the following conditions:

- The CKDIR bit in the UiMR register is 0 (internal clock).

- The CRD bit in the UiC0 register is 0 (CTS function enabled).

- The CKPOL bit in the UiC0 register is 0 (output transmit data on the falling edge of the transmit/receive clock).

- The UiIRS bit in registers UiC1 and U78CON is 0 (an interrupt request is generated when the transmit buffer is

empty).

Set to 0 by accepting an interrupt or by a program

TC = TCLK = 2(m + 1)/fx

fx: UiBRG count source frequency (f1, f8, or f2n)

m: Value set in the UiBRG register

D0 D1 D2 D3 D4 D5 D6 D7

TCLK

D0 D1 D2 D3 D4 D5 D6 D7

Data is transferred from the UiTB register to

the UARTi transmit register

Data is set to the UiTB register

Pulse stops because the TE bit is set to 0

Pulse stops because the input

level at the CTSi pin is high

D0 D1 D2 D3 D4 D5 D6 D7

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R32C/117 Group 18. Serial Interface

Figure 18.21 Receive Operation in Synchronous Serial Interface Mode

fEXT: External clock frequency

The following conditions should be met while an input level at the CLKi pin before receiving data is high:

- The TE bit in the UiC1 register is 1 (transmission enabled).

- The RE bit in the UiC1 register is 1 (reception enabled).

- Write of dummy data to the UiTB register.

Set to 0 by accepting an interrupt request or by a program

The UiRB register is read

RE bit in the

UiC1 register

TE bit in the

UiC1 register

TI bit in the

UiC1 register

RTSi

CLKi

RXDi

RI bit in the

UiC1 register

OER bit in the

UiRB register

IR bit in the

SiRIC register

Receive timing (when selecting an external clock)

This figure applies under the following conditions:

- The CKDIR bit in the UiMR register is 1 (external clock).

- The CKPOL bit in the UiC0 register is 0 (input receive data on the rising edge of the transmit/receive clock).

D0 D1 D2 D3 D4 D5 D6 D7D0 D1 D2 D3 D4 D5 D6 D7D0 D1 D2 D3 D4 D5 D6 D7

1/fEXT

Dummy data is set to the UiTB register

The data is transferred from the UiTB register to the UARTi transmit register

Input of receive data

The data is transferred from the UARTi receive register to the UiRB register

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R32C/117 Group 18. Serial Interface

18.1.1 Reset Procedure on Transmit/Receive Error

When a transmit/receive error occurs in synchronous serial interface mode, follow the procedures

below to perform a reset:

A. Reset procedure for the UiRB register (i = 0 to 8)

(1) Set the RE bit in the UiC1 register to 0 (reception disabled).

(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).

(3) Set bits SMD2 to SMD0 to 001b (synchronous serial interface mode).

(4) Set the RE bit in the UiC1 register to 1 (reception enabled).

B. Reset procedure for the UiTB register

(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).

(2) Set bits SMD2 to SMD0 to 001b (synchronous serial interface mode).

(3) Irrespective of its status, set the TE bit in the UiC1 register to 1 (transmission enabled).

18.1.2 CLK Polarity

As shown in Figure 18.22, the polarity of the transmit/receive clock is selected using the CKPOL bit in

the UiC0 register (i = 0 to 8).

Figure 18.22 Transmit/Receive Clock Polarity (i = 0 to 8)

CLKi

(A) When the CKPOL bit in the UiC0 register is 0 (output transmit data on the falling edge of the

transmit/receive clock and input receive data on the rising edge)

Notes:

1. The CLKi pin is held high when no data is transmitted/received.

2. This figure applies under the following conditions:

- The UFORM bit in the UiC0 register is 0 (LSB first).

- The UiLCH bit in the UiC1 register is 0 (data is not logic inverted).

(B) When the CKPOL bit in the UiC0 register is 1 (output transmit data on the rising edge of the

transmit/receive clock and input receive data on the falling edge)

TXDi

RXDi

Notes:

3. The CLKi pin is held low when no data is transmitted/received.

4. This figure applies under the following conditions:

-The UFORM bit in the UiC0 register is 0 (LSB first).

-The UiLCH bit in the UiC1 register is 0 (data is not logic inverted).

D0 D1 D2 D3 D4 D5 D6 D7

TXDi

RXDi

D0 D1 D2 D3 D4 D5 D6 D7

CLKi

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18.1.3 LSB First and MSB First Selection

As shown in Figure 18.23, the bit order is selected by setting the UFORM bit in the UiC0 register (i = 0

to 8).

Figure 18.23 Bit Order (i = 0 to 8)

18.1.4 Continuous Receive Mode

In continuous receive mode, data reception is automatically enabled by a read access to the receive

buffer register without writing dummy data to the transmit buffer register. To start data reception,

however, dummy data is required to read the receive buffer register.

When the UiRRM bit in registers U0C1 to U6C1 and the U78CON register is set to 1 (continuous

receive mode enabled), the TI bit in the UiC1 register becomes 0 (data held in the UiTB register) by a

read access to the UiRB register (i = 0 to 8). In this UiRRM bit setting, no dummy data should be written

to the UiTB register.

CLKi

(A) When the UFORM bit in the UiC0 register is 0 (LSB first)

Note:

1. This figure applies under the following conditions:

- The CKPOL bit in the UiC0 register is 0 (output transmit data on the falling edge of the transmit/

receive clock and input receive data on the rising edge).

- The UiLCH bit in the UiC1 register is 0 (data is not logic inverted).

(B) When the UFORM bit in the UiC0 register is 1 (MSB first)

TXDi

RXDi

Note:

2. This figure applies under the following conditions:

- The CKPOL bit in the UiC0 register is 0 (output transmit data on the falling edge of the transmit/

receive clock and input receive data on the rising edge).

- The UiLCH bit in the UiC1 register is 0 (data is not logic inverted).

D0 D1 D2 D3 D4 D5 D6 D7

CLKi

TXDi

RXDi

D7 D6 D5 D4 D3 D2 D1 D0

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18.1.5 Serial Data Logic Inversion

When the UiLCH bit in the UiC1 register is 1 (data is logic inverted), the logical value written in the UiTB

receive data. Figure 18.24 shows the logic inversion of serial data.

Figure 18.24 Serial Data Logic Inversion (i = 0 to 6)

18.1.6 CTS/RTS Function

CTS function controls data transmission using the CTSi/RTSi pin (i = 0 to 8). When an input level at the

pin becomes low, data transmission starts. If the input level changes to high during transmission, the

transmission of the next data is stopped.

In synchronous serial interface mode, the transmitter is required to operate even during the receive

operation. If CTS function is enabled, the input level at the CTSi/RTSi pin should be low to start data

reception as well.

RTS function indicates receiver status using the CTSi/RTSi pin. When data reception is ready, the

output level at the pin becomes low. It becomes high on the first falling edge of the CLKi pin.

CLKi

(A) When the UiLCH bit in the UiC1 register is 0 (data is not logic inverted)

(B) When the UiLCH bit in the UiC1 register is 1 (data is logic inverted)

TXDi

Note:

1. This figure applies under the following conditions:

- The CKPOL bit in the UiC0 register is 0 (output transmit data on the falling edge of the transmit/receive

clock and input receive data on the rising edge).

- The UFORM bit is 0 (LSB first).

D0 D1 D2 D3 D4 D5 D6 D7

CLKi

TXDi D0 D1 D2 D3 D4 D5 D6 D7

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18.2 Asynchronous Serial Interface Mode (UART Mode)

The UART mode enables data transmission/reception synchronized with an internal clock generated by a

trigger on the falling edge of the start bit. Table 18.5 lists specifications of UART mode.

Note:

1. The UiRB register is undefined when an overrun error occurs. The IR bit in the SiRIC register does

not change to 1 (interrupt requested).

Table 18.5 UART Mode Specifications

Item Specification

Data format • Start bit: 1-bit

• Data bit (data character): 7-bit, 8-bit, or 9-bit

• Parity bit: odd, even, or none

• Stop bit: 1-bit or 2-bit

Transmit/receive clock • The CKDIR bit in the UiMR register is 0 (internal clock) (i = 0 to 8):

fx = f1, f8, f2n; m: UiBRG register setting value, 00h to FFh

• The CKDIR bit is 1 (external clock)

fEXT: Clock applied to the CLKi pin

Transmit/receive control CTS function enabled, RTS function enabled, or CTS/RTS function disabled

Transmit start conditions The conditions for starting data transmission are as follows:

• The TE bit in the UiC1 register is 1 (transmission enabled)

• The TI bit in the UiC1 register is 0 (data held in the UiTB register)

• Input level at the CTSi pin is low when CTS function is selected

Receive start conditions The conditions for starting data reception are as follows:

• The RE bit in the UiC1 register is 1 (reception enabled)

• The start bit is detected

Interrupt request generating

timing

In transmit interrupt, one of the following conditions can be selected by setting the UiIRS

bit in registers U0C1 to U6C1 and the U78CON register:

• The UiIRS bit is 0 (transmit buffer is empty):

when data is transferred from the UiTB register to the UARTi transmit register (when

the transmission has started)

• The UiIRS bit is 1 (transmission is completed):

when data transmission from the UARTi transmit register is completed

In receive interrupt,

• When data is transferred from the UARTi receive register to the UiRB register (when

reception is completed)

Error detection • Overrun error (1)

This error occurs when 1 bit prior to the stop bit (when 1 stop bit length is selected) or

the first stop bit (when 2 stop bit length is selected) of the next data is received before

the UiRB register is read

• Framing error

This error occurs when the required number of stop bits is not detected

• Parity error

This error occurs when an even number of 1’s in parity and character bits is detected

while the odd number is set, or vice versa. The parity should be enabled

• Error sum flag

This flag becomes 1 when any of overrun error, framing error, or parity error occurs

Other functions • Bit order selection

LSB first or MSB first

• Serial data logic inversion

This function logically inverses transmit/receive data. The start bit and stop bit are not

inverted

• TXD/RXD I/O polarity switching

The output level from the TXD pin and the input level to the RXD pin are inverted. All

I/O levels are inverted

16 m1+

------------------------

fEXT

16 m1+

------------------------

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R32C/117 Group 18. Serial Interface

Tables 18.6 and 18.7 list register settings. When UARTi operating mode is selected, a high is output at the

TXDi pin until transmission starts (the TXDi pin is high-impedance when the N-channel open drain output

is selected) (i = 0 to 8). Figures 18.25 and 18.26 show examples of transmit operations in UART mode.

Figure 18.27 shows an example of receive operation.

Note:

1. The bits used are as follows: 7-bit character length: bits 6 to 0

8-bit character length: bits 7 to 0

9-bit character length: bits 8 to 0

Table 18.6 Register Settings in UART Mode (UART0 to UART6)

UiMR IOPOL Select I/O polarity of pins TXD and RXD

PRY and PRYE Select parity enabled or disabled, and odd or even

STPS Select a stop bit length

CKDIR Select an internal clock or external clock

SMD2 to SMD0 Set the bits to 100b in 7-bit character length

Set the bits to 101b in 8-bit character length

Set the bits to 110b in 9-bit character length

UiC0 UFORM Select LSB first or MSB first in 8-bit character length. Set the bit

to 0 in 7-bit or 9-bit character length

CKPOL Set the bit to 0

5 Set the bit to 0

CRD Select CTS function enabled or disabled

TXEPT Transmit register empty flag

2 Set the bit to 0

CLK1 and CLK0 Select a count source for the UiBRG register

UiC1 7 Set the bit to 0

UiLCH Set the bit to 1 to use logic inversion

UiRRM Set the bit to 0

UiIRS Select an interrupt source for UARTi transmission

RI Receive complete flag

RE Set the bit to 1 to enable data reception

TI Transmit buffer empty flag

TE Set the bit to 1 to enable data transmission

UiSMR 7 to 0 Set the bits to 00h

UiSMR2 7 to 0 Set the bits to 00h

UiSMR3 7 to 0 Set the bits to 00h

UiSMR4 7 to 0 Set the bits to 00h

UiBRG 7 to 0 Set the bit rate

IFS0 IFS06 Select input pins for CLK3, RXD3, and CTS3

IFS03 and IFS02 Select input pins for CLK6, RXD6, and CTS6

UiTB 8 to 0 Set the data to be transmitted (1)

UiRB OER, FER, PER, and SUM Error flag

8 to 0 Received data is read (1)

i = 0 to 6

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R32C/117 Group 18. Serial Interface

Note:

1. The bits used are as follows: 7-bit character length: bits 6 to 0

8-bit character length: bits 7 to 0

9-bit character length: bits 8 to 0

Table 18.7 Register Settings in UART Mode (UART7, UART8)

UiMR PRY and PRYE Select parity enabled or disabled, and odd or even

STPS Select a stop bit length

CKDIR Select an internal clock or external clock

SMD2 to SMD0 Set the bits to 100b in 7-bit character length

Set the bits to 101b in 8-bit character length

Set the bits to 110b in 9-bit character length

UiC0 UFORM Select LSB first or MSB first in 8-bit character length. Set the bit

to 0 in 7-bit or 9-bit character length

CKPOL Set the bit to 0

5 Set the bit to 0

CRD Select CTS function enabled or disabled

TXEPT Transmit register empty flag

2 Set the bit to 0

CLK1 and CLK0 Select a count source for the UiBRG register

UiC1 RI Receive complete flag

RE Set the bit to 1 to enable data reception

TI Transmit buffer empty flag

TE Set the bit to 1 to enable data transmission

U78CON UiRRM Set the bit to 0

UiIRS Select an interrupt source for UARTi transmission

UiBRG 7 to 0 Set the bit rate

IFS0 IFS05 Select input pins for CLK7, RXD7, and CTS7

IFS04 Select input pins for CLK8, RXD8, and CTS8

UiTB 8 to 0 Set the data to be transmitted (1)

UiRB OER, FER, PER, and SUM Error flag

8 to 0 Received data is read (1)

i = 7, 8

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R32C/117 Group 18. Serial Interface

Figure 18.25 Transmit Operation in UART Mode (1/2) (i = 0 to 8)

Internal transmit/

receive clock

Example of data transmit timing when the character length is 8-bit (parity enabled, 1 stop bit)

TE bit in the

UiC1 register

TI bit in the UiC1

CTSi

TXDi

TXEPT bit in the

UiC0 register

IR bit in the

SiTIC register

This figure applies under the following conditions:

- The PRYE bit in the UiMR register is 1 (parity enabled).

- The STPS bit in the UiMR register is 0 (1 stop bit).

- The CRD bit in the UiC0 register is 0 (CTS function enabled).

- The UiIRS bit in the UiC1 register is 1 (an interrupt request is generated when transmission is comepleted).

Set to 0 by accepting an interrupt or by a program

TC = 16 (m + 1) / fx or 16 (m + 1) / fEXT

fx: UiBRG count source frequency (f1, f8, or f2n)

fEXT: UiBRG count source frequency (external clock)

m: Value set in the UiBRG register

The transmit/receive clock stops because the input level at the CTSi

pin is high when the stop bit state is verified. It resumes running as

soon as low is verified

D0 D1 D2 D3 D4 D5 D6 D7 PSPST

ST: Start bit

P: Parity bit

SP: Stop bit

D0 D1 D2 D3 D4 D5 D6 D7 PSPST D0ST

Data is transferred from the UiTB

Data is set to the UiTB register

Pulse stops because the TE bit is

set to 0

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R32C/117 Group 18. Serial Interface

Figure 18.26 Transmit Operation in UART Mode (2/2) (i = 0 to 8)

Internal transmit/

receive clock

Example of data transmit timing when the character length is 9-bit (parity disabled, 2 stop bits)

TE bit in the

UiC1 register

TI bit in the

UiC1 register

TXDi

TXEPT bit in the

UiC0 register

IR bit in the

SiTIC register

This figure applies under the following conditions:

- The PRYE bit in the UiMR register is 0 (parity disabled).

- The STPS bit in the UiMR register is 1 (2 stop bits).

- The CRD bit in the UiC0 register is 1 (CTS function disabled).

- The UiIRS bit in the UiC1 register is 0 (an interrupt request is generated when the transmit buffer is empty).

Set to 0 by accepting an interrupt or by a program

TC = 16 (m + 1) / fx or 16 (m + 1) / fEXT

fx: UiBRG count source frequency (f1, f8, or f2n)

fEXT: UiBRG count source frequency (external clock)

m: Value set in the UiBRG register

D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST

ST: Start bit

P: Parity bit

SP: Stop bit

D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SPST ST

Data is transferred from the UiTB

Data is set to the UiTB register

Pulse stops because the TE bit is

set to 0

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R32C/117 Group 18. Serial Interface

Figure 18.27 Receive Operation in UART Mode (i = 0 to 8)

18.2.1 Bit Rate

In UART mode, the bit rate is a clock frequency which is divided by a setting value of the UiBRG

Table 18.8 Bit Rate Setting

Bit Rate (bps) Count Source of

BRG

Peripheral Clock: 30 MHz Peripheral Clock: 32 MHz

Setting value of

BRG: n

Actual bit rate

(bps)

Setting value of

BRG: n

Actual bit rate

(bps)

1200 f8 194 (C2h) 1202 207 (CHh) 1202

2400 f8 97 (61h) 2392 103 (67h) 2404

4800 f8 48 (30h) 4783 51 (33h) 4808

9600 f1 194 (C2h) 9615 207 (CFh) 9615

14400 f1 129 (81h) 14423 138 (8Ah) 14388

19200 f1 97 (61h) 19133 103 (67h) 19231

28800 f1 64 (40h) 28846 68 (44h) 28986

31250 f1 59 (3Bh) 31250 63 (3Fh) 31250

38400 f1 48 (30h) 38265 51 (33h) 38462

51200 f1 36 (24h) 50676 38 (26h) 51282

UiBRG output

RE bit in the

UiC1 register

Set to 0 by accepting an interrupt request or by a program

Transmit/

receive clock

Example of data receive timing when the character length is 8-bit (parity disabled, 1 stop bit)

RXDi

RI bit in the

UiC1 register

IR bit in the

SiRIC register

RTSi

D0 D1 D7

Input of receive dataLow is reverified

Start bit

Data reception starts when the transmit/receive clock is

generated on the falling edge of the start bit

Stop bit

It becomes low when the UiRB

Data is transferred from the UARTi receive register to the UiRB register

This figure applies under the following conditions:

- The PRYE bit in the UiMR register is 0 (parity disabled).

- The STPS bit in the UiMR register is 0 (1 stop bit).

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R32C/117 Group 18. Serial Interface

18.2.2 Reset Procedure on Transmit/Receive Error

When a transmit/receive error occurs in UART mode, follow the procedure below to perform a reset:

A. Reset procedure for the UiRB register (i = 0 to 8)

(1) Set the RE bit in the UiC1 register to 0 (reception disabled).

(2) Set the RE bit in the UiC1 register to 1 (reception enabled).

B. Reset procedure for the UiTB register

(1) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).

(2) Set again bits SMD2 to SMD0 to either of 001b, 101b, or 110b.

(3) Irrespective of its status, set the TE bit in the UiC1 register to 1 (transmission enabled).

18.2.3 LSB First and MSB First Selection

As shown in Figure 18.28, the bit order is selected by setting the UFORM bit in the UiC0 register (i = 0

to 8). This function is available when the character length is 8-bit.

Figure 18.28 Bit Order (i = 0 to 8)

ST: Start bit

P: Parity bit

SP: Stop bit

(A) When the UFORM bit in the UiC0 register is 0 (LSB first)

(B) When the UFORM bit in the UiC0 register is 1 (MSB first)

Note:

1. This figure applies under the following conditions:

- The UiLCH bit in the UiC1 register is 0 (data is not logic inverted).

- The STPS bit in the UiMR register is 0 (1 stop bit).

- The PRYE bit is 1 (parity enabled).

CLKi

TXDi

RXDi

D0 D1 D2 D3 D4 D5 D6

ST D7 SP

D7 SPST

CLKi

TXDi

RXDi

D0D1D2D3D4D5D6ST D7 SP

SPST D0D1D2D3D4D5D6D7

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18.2.4 Serial Data Logic Inversion

When the UiLCH bit in the UiC1 register is 1 (data is logic inverted), the logical value written in the UiTB

receive data. The parity bit is not inverted. Figure 18.29 shows the logic inversion of serial data.

Figure 18.29 Serial Data Logic Inversion (i = 0 to 6)

CLKi

(A) When the UiLCH bit in the UiC1 register is 0 (data is not logic inverted)

(B) When the UiLCH bit in the UiC1 register is 1 (data is logic inverted)

TXDi

(not logic inverted)

CLKi

TXDi

(logic inverted)

Note:

1. This figure applies under the following conditions:

- The UFORM bit in the UiC0 register is 0 (LSB first).

- The STPS bit in the UiMR register is 0 (1 stop bit).

- The PRYE bit is 1 (parity enabled).

ST: Start bit

P: Parity bit

SP: Stop bit

D0 D1 D2 D3 D5 D6 PSPST D4 D7

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18.2.5 TXD and RXD I/O Polarity Inversion

The output level at the TXD pin and the input level at the RXD pin are inverted by this function. All I/O

data levels, including the start bit, stop bit, and parity bit are inverted by setting the IOPOL bit in the

UiMR register to 1 (inverted) (i = 0 to 6). Figure 18.30 shows TXD and RXD I/O polarity inversion.

Figure 18.30 TXD and RXD I/O Polarity Inversion (i = 0 to 6)

18.2.6 CTS/RTS Function

CTS function controls data transmission using the CTSi/RTSi pin (i = 0 to 8). When an input level at the

pin becomes low, data transmission starts. If the input level changes to high during transmit operation,

transmission of the next data is stopped.

RTS function indicates receiver status using the CTSi/RTSi pin. When the MCU is ready to receive

data, the output level at the pin becomes low. It becomes high on the first falling edge of the CLKi pin.

CLKi

(A) When the IOPOL bit in the UiMR register is 0 (not inverted)

(B) When the IOPOL bit in the UiMR register is 1 (inverted)

CLKi

TXDi

(inverted)

Note:

1. This figure applies under the following conditions:

- The UFORM bit in the UiC0 register is 0 (LSB first).

- The STPS bit in the UiMR register is 0 (1 stop bit).

- The PRYE bit is 1 (parity enabled).

RXDi

(not inverted)

RXDi

(inverted)

D0 D1 D2 D3 D5 D6 PSPST D4 D7

TXDi

(not inverted)

ST: Start bit

P: Parity bit

SP: Stop bit

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R32C/117 Group 18. Serial Interface

18.3 Special Mode 1 (I2C Mode)

This mode uses an I2C-typed interface for communication. Table 18.9 lists specifications of the I2C mode.

Notes:

1. When an external clock is selected, the conditions should be met while the external clock signal is

held high.

2. The UiRB register is undefined when an overrun error occurs. The IR bit in the SiRIC register does

not change to 1 (interrupt requested).

Table 18.10 lists register settings in I2C mode, and Tables 18.11 and 18.12 list I2C mode functions. Figure

18.31 shows a block diagram of I2C mode, and Figure 18.32 shows timings for the transfer to the UiRB

As shown in Tables 18.11 and 18.12, UARTi enters this mode when bits SMD2 to SMD0 in the UiMR

signal at the SDAi pin is output via the delay circuit, it changes after the SCLi pin is stably held low.

Table 18.9 I2C Mode Specifications

Item Specification

Data format 8-bit character length

Transmit/receive clock In master mode

• The CKDIR bit in the UiMR register is 0 (internal clock) (i = 0 to 6):

fx = f1, f8, f2n

m: UiBRG register setting value, 00h to FFh

In slave mode

• The CKDIR bit is 1 (external clock): input to the SCLi pin

Transmit start conditions The conditions for starting data transmission are as follows (1):

• The TE bit in the UiC1 register is 1 (transmission enabled)

• The TI bit in the UiC1 register is 0 (data held in the UiTB register)

Receive start conditions The conditions for starting data reception are as follows (1):

• The RE bit in the UiC1 register is 1 (reception enabled)

• The TE bit in the UiC1 register is 1 (transmission enabled)

• The TI bit in the UiC1 register is 0 (data held in the UiTB register)

Interrupt request generating

timing

When any of the following is detected: START condition, STOP condition,

NACK (not-acknowledge), or ACK (acknowledge)

Error detection Overrun error (2)

This error occurs when the eighth bit of the next data is received before the

UiRB register is read

Other functions • Arbitration lost

Update timing of the ABT bit in the UiRB register can be selected

• SDAi digital delay

No digital delay or two to eight cycles of digital delay of UiBRG count

source

• Clock phase setting

Clock delayed or no clock delay

2m1+

---------------------

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R32C/117 Group 18. Serial Interface

Figure 18.31 I2C Mode Block Diagram (i = 0 to 6)

IICM

SDHI ALS

1Transmit

circuit

DMA transfer request

(interrupt request by

UARTi transmission)

Interrupt request by

UARTi transmission

or NACK

START

condition

detection

STOP condition

detection

Interrupt request by

UARTi reception,

ACK interrupt, or

DMA transfer request

Interrupt request by bus collision,

START condition detected, or

STOP condition detected

SWC2

IICM: Bit in the UiSMR register

IICM2, SWC, ALS, SWC2, and SDHI: Bits in the UiSMR2 register

STSPSEL, ACKD, and ACKC: Bits in the UiSMR4 register

NACK

Bus

busy 0

SWC

Falling edge of the 8th bit

External clock

Internal clock 9th bit

ACK

Arbitration lost

SDAi

CLKi

Noise

filter

Clock

control

Delay

circuit

Receive

circuit

SCLi

1IICM

Noise

filter

Noise

filter

1IICM

IICM

IICM2

IICM

IICM2

IICM

STSPSEL

START condition/

STOP condition

generation

ACKC

ACKD

Bus collision detection (IE mode)

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R32C/117 Group 18. Serial Interface

Table 18.10 Register Settings in I2C Mode (i = 0 to 6)

Master Slave

UiMR IOPOL Set the bit to 0

CKDIR Set the bit to 0 Set the bit to 1

SMD2 to SMD0 Set the bit to 010b

UiC0 7 to 4 Set the bits to 1001b

TXEPT Transmit register empty flag

2 Set the bit to 0

CLK1 and CLK0 Select a count source for the UiBRG register Disabled

UiC1 7 to 5 Set the bits to 000b

UiIRS Set the bit to 1

RI Receive complete flag

RE Set the bit to 1 to enable data reception

TI Transmit buffer empty flag

TE Set the bit to 1 to enable data transmission/reception

UiSMR 7 to 3 Set the bits to 00000b

BBS Bus busy flag

ABC Select an arbitration lost detection timing Disabled

IICM Set the bit to 1

UiSMR2 7 Set the bit to 0

SDHI Set the bit to 1 to disable the SDA output

SWC2 Set the bit to 1 to hold the SCL output at a forcible low

STC Set the bit to 0 Set the bit to 1 to reset UARTi by

detecting the START condition

ALS Set the bit to 1 to stop the output at the SDAi pin to detect an

arbitration lost

Set the bit to 0

SWC Set the bit to 1 to hold a low output at the SCLi pin after receiving the eighth bit of the clock

CSC Set the bit to 1 to enable clock synchronization Set the bit to 0

IICM2 Refer to Tables 18.11 and 18.12

UiSMR3 DL2 to DL0 Set the digital delay value of SDAi

4 to 2 Set the bit to 000b

CKPH Refer to Tables 18.11 and 18.12

SSE Set the bit to 0

UiSMR4 SWC9 Set the bit to 0 Set the bit to 1 to hold a low

output at the SCLi pin after

receiving the ninth bit of the clock

SCLHI Set the bit to 1 to stop the SCL output to detect STOP condition Set the bit to 0

ACKC Set the bit to 1 for ACK data output

ACKD Select ACK or NACK

STSPSEL Set the bit to 1 when any condition is output Set the bit to 0

STPREQ Set the bit to 1 to generate a STOP condition Set the bit to 0

RSTAREQ Set the bit to 1 to generate a repeated START condition Set the bit to 0

STAREQ Set the bit to 1 to generate a START condition Set the bit to 0

UiBRG 7 to 0 Set the bit rate Disabled

IFSR0 IFSR06 and

IFSR07

Select a UART as interrupt source

IFSR1 IFSR16 Select a UART as interrupt source

IFS0 IFS06 Select input pins for SCL3 and SDA3

IFS03 and IFS02 Select input pins for SCL6 and SDA6

UiTB 8 Set the bit to 1 when transmitting. Set the bit to the value of the ACK bit when receiving

7 to 0 Set the data to be transmitted when transmitting. Set the register to FFh when receiving

UiRB OER Overrun error flag

ABT Arbitration lost detection flag Disabled

8 D0 is loaded immediately after a receive interrupt occurs. ACK or NACK is loaded after a transmit

interrupt occurs

7 to 0 D7 to D1 are read immediately after a receive interrupt occurs. D7 to D0 are read after a transmit

interrupt occurs

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Note:

1. Steps to change an interrupt source are as follows:

(1) Disable the interrupt of the corresponding software interrupt number.

(2) Change the source of interrupt.

(3) Set the IR bit of the corresponding software interrupt number to 0 (no interrupt requested).

(4) Set bits ILVL2 to ILVL0 of the corresponding software interrupt number.

Table 18.11 I2C Mode Functions (i = 0 to 6) (1/2)

Function

Synchronous

Serial Interface

Mode

(SMD2 to SMD0

are 001b,

IICM is 0)

I2C Mode (SMD2 to SMD0 are 010b, IICM is 1)

IICM2 is 0

(ACK/NACK interrupt)

IICM2 is 1

(Transmit/receive interrupt)

CKPH is 0

(No clock

delay)

CKPH is 1

(Clock

delayed)

CKPH is 0

(No clock delay)

CKPH is 1

(Clock delayed)

Source of software

interrupt numbers 6 and

39 to 41 (1)

(refer to Figure 18.32)

—

START condition or STOP condition detection (refer to Table 18.13)

Source of software

interrupt numbers 2, 4,

17, 19, 33, 35, and 37 (1)

(refer to Figure 18.32)

UARTi

transmission:

Transmission

started or

completed

(selected using

the UiIRS

NACK detection: Rising

edge of the ninth bit of

SCLi

UARTi transmission:

Rising edge of the

ninth bit of SCLi

UARTi transmission:

Falling edge of the

ninth bit of SCLi

Source of software

interrupt numbers 3, 5,

18, 20, 34, 36, and 38 (1)

(refer to Figure 18.32)

UARTi reception:

Receiving at

eighth bit

CKPOL is 0

(rising edge)

CKPOL is 1

(falling edge)

ACK detection: Rising

edge of the ninth bit of

SCLi

UARTi reception: Falling edge of the eighth bit

of SCLi

Data transfer timing from

the UARTi receive

CKPOL is 0

(rising edge)

CKPOL is 1

(falling edge)

Rising edge of the ninth

bit of SCLi

Falling edge of the

eighth bit of SCLi

Falling edge of the

eighth bit and rising

edge of the ninth bit of

SCLi

UARTi transmit output

delay

No delay Delayed

Pins P6_3, P6_7, P7_0,

P7_3, P7_6, P9_2,

P9_6, P11_0, P12_0,

P15_0, and P15_4

TXDi output SDAi I/O

Pins P6_2, P6_6, P7_1,

P7_5, P8_0, P9_1,

P9_7, P11_2, P12_2,

P15_2, and P15_5

RXDi input SCLi I/O

Pins P6_1, P6_5, P7_2,

P7_4, P7_7, P9_0,

P9_5, P11_1, P12_1,

P15_1, and P15_6

Select CLKi input

or output

—

(Not used in I2C mode)

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R32C/117 Group 18. Serial Interface

Notes:

1. The first data transfer to the UiRB register starts on the rising edge of the eighth bit of SCLi.

2. The second data transfer to the UiRB register starts on the rising edge of the ninth bit of SCLi.

Table 18.12 I2C Mode Functions (i = 0 to 6) (2/2)

Function

Synchronous

Serial Interface

Mode

(SMD2 to SMD0

are 001b,

IICM is 0)

I2C Mode (SMD2 to SMD0 are 010b, IICM is 1)

IICM2 is 0

(ACK/NACK interrupt)

IICM2 is 1

(Transmit/receive interrupt)

CKPH is 0

(No clock

delay)

CKPH is 1

(Clock

delayed)

CKPH is 0

(No clock delay)

CKPH is 1

(Clock delayed)

Read level at pins RXDi

and SCLi

Readable irrespective of the port direction bit

Default output value at

the SDAi pin —High (Value set in the port Pi register if the I/O port is selected by output

function select registers (i = 0 to 7))

SCLi default and end

values —High Low High Low

DMA source (refer to

Figure 18.32)

UARTi reception ACK detection UARTi reception: Falling edge of the eighth bit

of SCLi

Store received data The first to

eighth bits of

received data

are stored into

bits 0 to 7 in the

UiRB register

The first to eighth bits of

received data are stored

into bits 7 to 0 in the UiRB

The first to seventh bits

of received data are

stored into bits 6 to 0 in

the UiRB register and

the eighth bit is stored

into bit 8

Same as on the left

column on the first data

storing. (1) The first to

eighth bits of received

data are stored into 7

to 0 bits in the UiRB

bit is stored into bit 8

on the second data

storing (2)

Read received data The UiRB register status is read as it is Bits 6 to 0 in the UiRB

bits 7 to 1 and bit 8 is

read as bit 0

Same as on the left

column on the first

read. (1) The UiRB

as it is on the second

read (2)

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R32C/117 Group 18. Serial Interface

Figure 18.32 Timings for the Transfer and Interrupt to the UiRB Register (i = 0 to 6)

(A) When the IICM2 bit is 0 (Use ACK/NACK interrupt) and the CKPH bit is 0 (no clock delay)

This figure applies under the following condition:

- The CKDIR bit in the UiMR register is 0 (internal clock).

(B) When the IICM2 bit is 0 and the CKPH bit is 1 (clock delayed)

(D) When the IICM2 bit is 1 and the CKPH bit is 1

SCLi

SDAi

ACK interrupt (DMA transfer

request) or NACK interrupt

Transfer to the UiRB register

b15 b9b8b7 b0

UiRB register

ACK interrupt (DMA transfer

request) or NACK interrupt

Transfer to the UiRB register

UiRB register

Transfer to the UiRB register

Receive interrupt (DMA transfer request) Transmit interrupt

The first transfer to the UiRB register

Receive interrupt (DMA transfer request) Transmit interrupt

The second transfer to the UiRB register

D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK/NACK)

D8 D7 D6 D5 D4 D3 D2 D1 D0

SCLi

SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK/NACK)

b15 b9b8b7 b0

D8 D7 D6 D5 D4 D3 D2 D1 D0

SCLi

SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK/NACK)

UiRB register

b15 b9b8b7 b0

D0 D7 D6 D5 D4 D3 D2 D1-

SCLi

SDAi D7 D6 D5 D4 D3 D2 D1 D0 D8 (ACK/NACK)

UiRB register

b15 b9 b8 b7 b0

D0 D7 D6 D5 D4 D3 D2 D1-

UiRB register

b15 b9b8b7 b0

D8 D7 D6 D5 D4 D3 D2 D1 D0

1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit

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R32C/117 Group 18. Serial Interface

18.3.1 START Condition and STOP Condition Detection

The START condition and STOP condition are detected by their respective detectors.

The START condition detection interrupt request is generated by a high-to-low transition at the SDAi pin

while the SCLi pin is held high (i = 0 to 6). The STOP condition detection interrupt request is generated

by a low-to-high transition at the SDAi pin while the SCLi pin is held high.

The START condition detection interrupt shares interrupt control registers and vectors with the STOP

condition detection interrupt. The BBS bit in the UiSMR register determines which interrupt is

requested.

To detect a START condition or STOP condition, both set-up and hold times require at least six cycles

of the peripheral clock (f1) as shown in Figure 18.33. To meet the condition for the Fast-mode

specification, f1 must be at least 10 MHz.

Figure 18.33 START Condition and STOP Condition Detection Timing (i = 0 to 6)

18.3.2 START Condition and STOP Condition Generation

The START condition, repeated START condition, and STOP condition are generated by bits STAREQ,

RSTAREQ, and STPREQ in the UiSMR4 register, respectively (i = 0 to 6). To output a START condition,

set the STSPSEL bit in the UiSMR4 register to 1 (select START condition/STOP condition generation

circuit) after setting the STAREQ bit to 1 (start). To output a repeated START condition or STOP

condition, set the STSPSEL bit to 1 after setting RSTAREQ bit or STPREQ bit to 1, respectively.

Table 18.13 and Figure 18.34 show the functions of the STSPSEL bit.

Table 18.13 STSPSEL Bit Functions

Function STSPSEL is 0 STSPSEL is 1

START condition and STOP

condition generation

Output is provided by the

program with port (no auto

generation by hardware)

START condition or STOP condition is output

according to the STAREQ, RSTAREQ, or

STPREQ bit

START condition and STOP

condition interrupt request

generating timing

When START condition or

STOP condition is detected

When START condition or STOP condition

generation is completed

Note:

1. These are cycles of the peripheral clock (f1).

STOP condition

Set-up time  6 cycles (1)

Hold time  6 cycles (1)

SCLi

START condition

SDAi

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Figure 18.34 STSPSEL Bit Functions (i = 0 to 6)

18.3.3 Arbitration

On the rising edge of the SCLi, the MCU compares the transmit data with the data input from the SDAi

pin. If no match is found, the MCU performes arbitration by stopping the SDAi output.

The update timing for the ABT bit in the UiRB register is selected by setting the ABC bit in the UiSMR

When the ABC bit is 0 (update every bit), the ABT bit becomes 1 (detected (lose)) as soon as a data

discrepancy is detected. If not detected, the ABT bit becomes 0 (not detected (win)). When the ABC bit

is 1 (update every byte), the ABT bit becomes 1 on the falling edge of the eighth bit of the SCLi if any

discrepancy is detected. In this ABC bit setting, set the ABT bit to 0 to start the next 1-byte transfer.

When the ALS bit in the UiSMR2 register is 1 (stop the SDAi output), the SDAi pin becomes high-

impedance as the ABT bit becomes 1 when an arbitration lost occurs.

SCLi

(A) In slave mode

SDAi

(B) In master mode

The CKDIR bit is 1 (external clock) and the STSPSEL bit is 0 (select serial I/O circuit)

The CKDIR bit is 0 (internal clock) and the CKPH bit is 1 (clock delayed)

Interrupt by START condition detection Interrupt by STOP condition detection

SCLi

SDAi

Interrupt by START condition

detection (or generation)

Interrupt by STOP condition

detection (or generation)

01 0 01STSPSEL

0 01STPREQ

01 0STAREQ

Software

Hardware

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18.3.4 SCL Control and Clock Synchronization

Data transmission/reception in I2C mode uses the transmit/receive clock as shown in Figure 18.32. The

clock speed increase makes it difficult to secure the required time for ACK generation and data transmit

procedure. I2C mode supports a function of wait-state insertion to secure this required time and a

function of clock synchronization with a wait-state inserted by other devices.

The SWC bit in the UiSMR2 register is used to insert a wait-state for ACK generation (i = 0 to 6). When

the SWC bit is 1 (hold the SCLi pin low after the eighth bit is received), the SCLi pin is held low on the

falling edge of the eighth bit of the SCLi. When the SWC bit is 0 (no wait-state/wait-state cleared), the

SCLi line is released.

When the SWC2 bit in the UiSMR2 register is 1 (hold the SCLi pin low), the SCLi pin is forced low even

during transmission or reception. When the SWC2 bit is 0 (output the transmit/receive clock at the SCLi

pin), the SCLi line is released to output the transmit/receive clock.

The SWC9 bit in the UiSMR4 register is used to insert a wait-state for checking received acknowledge

bits. While the CKPH bit in the UiSMR3 register is 1 (clock delayed), when the SWC9 bit is set to 1

(hold the SCLi pin low after the ninth bit is received), the SCLi pin is held low on the falling edge of the

ninth bit of the SCLi. When the SWC9 bit is set to 0 (no wait-state/wait-state cleared), the SCLi line is

released.

Figure 18.35 Wait-state Insertion Using the SWC or SWC9 Bit (i = 0 to 6)

SCLi (master) 1 2 3 4

SDAi (master)

5 6 7 8

SCLi (slave)

(A) SWC bit function

Clock line is

held low

Clock line is

released

(SWC is 0)

SDAi (slave)

Address bit comparison, acknowledge generation

A/A

SCLi (master) 1 2 3 4

SDAi (master)

5 6 7 8

(B) SWC9 bit function

Clock line is

held low

Clock line is

released

(SWC9 is 0)

Acknowledge check

A/A

SCLi (slave)

SDAi (slave)

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The CSC bit in the UiSMR2 register is used to synchronize an internally generated clock with the clock

applied to the SCLi pin. For example, if a wait-state is inserted from another device, the two clocks are

not synchronized. While the CSC bit is 1 (clock synchronization enabled) and the internal clock is held

high, when a high at the SCLi pin changes to low, the internal clock becomes low in order to reload the

value of the UiBRG register and to resume counting. While the SCLi pin is held low, when the internal

clock changes from low to high, the count is stopped until the SCLi pin becomes high. That is, the

UARTi transmit/receive clock is the logical AND of the internal clock and the SCLi. The synchronized

period starts from one clock prior to the first synchronized clock and ends when the ninth clock is

completed. The CSC bit can be set to 1 only when the CKDIR bit in the UiMR register is 0 (internal

clock).

The SCLHI bit in the UiSMR4 register is used to leave the SCLi pin open when another master

generates a STOP condition while the master is in transmit/receive operation. If the SCLHI bit is set to

1 (stop SCLi output), the SCLi pin is open (the pin is high-impedance) when a STOP condition is

detected and the clock output is stopped.

Figure 18.36 Clock Synchronization (i = 0 to 6)

Internal clock

SCLi

Change the internal clock

signal from high to low to

start counting low period

Stop counting Resume

counting

(A) Clock synchronization

Clock output of

another device

(B) Synchronization period

2 3 4 5 6 7 8 9SCLi

Internal clock

Write of transmit data Synchronized period

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R32C/117 Group 18. Serial Interface

18.3.5 SDA Output

Values set to bits 8 to 0 (D8 to D0) in the UiTB register are output starting from D7 to D0, and lastly D8,

which is a bit for the acknowledge signal (i = 0 to 6). When transmitting, D8 should be set to 1 to free

the bus. When receiving, D8 should be set to ACK or NACK.

Bits DL2 to DL0 in the UiSMR3 register set a delay time of the SDAi on the falling edge of the SCLi.

Based on the UiBRG count source, the delay time can be selected from zero cycles (no delay) or two to

eight cycles.

The SDAi pin can be high-impedance at any given time once the SDHI bit in the UiSMR2 register is set

to 1 (stop the output). Output at the SDAi pin is low if an I/O port is selected for the SDAi and the pin is

specified as the output port after selecting I2C mode. In this case, if the SDHI bit is 1, the SDAi pin

becomes high-impedance.

When the SDHI bit is rewritten while the SCLi pin is held high, a START condition or STOP condition is

generated. When it is rewritten immediately before the rising edge of SCLi, arbitration lost may be

accidently detected. Therefore, the SDHI bit should be rewritten so the SDAi pin level changes while

the SCLi pin is low.

18.3.6 SDA Input

When the IICM2 bit in the UiSMR2 register is 0 (use ACK/NACK interrupt), the first 8 bits of received

data (D7 to D0) are stored into bits 7 to 0 in the UiRB register and the ninth bit (ACK/NACK) is stored

into bit 8 (i = 0 to 6).

When the IICM2 bit is 1, the first 7 bits of received data (D7 to D1) are stored into bits 6 to 0

in the UiRB register and eighth bit (D0) is stored into bit 8.

If the IICM2 bit is 1 and the CKPH bit in the UiSMR3 register is 1 (clock delayed), the same data that is

set when the IICM2 bit is 0 can be read. To read this data, read the UiRB register after data in the ninth

bit is latched on the rising edge of the SCLi.

18.3.7 Acknowledge

When data is to be received in master mode, ACK is output after 8 bits are received by setting the UiTB

circuit) and the ACKC bit is 1 (ACK data output), the value of the ACKD bit is output at the SDAi pin (i =

0 to 6).

If the IICM2 bit is 0, a NACK interrupt request is generated when the SDAi pin is high on the rising edge

of the ninth bit of the SCLi. An ACK interrupt request is generated when the SDAi pin is low.

When the DMA request source is “UARTi receive interrupt request or ACK interrupt request”, the DMA

transfer starts when an ACK is detected.

18.3.8 Transmit/Receive Operation Reset

When the CKDIR bit in the UiMR register is 1 (external clock), the STC bit in the UiSMR2 register is 1

(initialize the circuit), and a START condition is detected, the following three operations are performed (i

= 0 to 6):

• The transmit register is reset and the UiTB register value is transferred to the transmit register.

New data transmission starts on the falling edge of the first bit of the next SCLi as transmit clock.

The transmit register value before the reset is output at the SDAi pin in the period from the falling

edge of the SCLi until the first data output.

• The receive register is reset and the new data reception starts on the falling edge of the first bit of

the next SCLi.

• The SWC bit in the UiSMR2 register becomes 1 (hold the SCLi pin low after the eighth bit is

received).

The TI bit in the UiC1 register does not change when using this function to start the UARTi

transmission/reception.

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R32C/117 Group 18. Serial Interface

18.4 Special Mode 2

Special mode 2 enables serial communication between one or multiple masters and multiple slaves. The

SSi input pin controls serial bus communication (i = 0 to 6). Table 18.14 lists specifications of special

mode 2.

Notes:

1. When selecting an external clock, the following preconditions should be met:

• The CLKi pin is held high when the CKPOL bit in the UiC0 register is 0 (transmit data output on the falling

edge of the transmit/receive clock and receive data input on the rising edge).

• The CLKi pin is held low when the CKPOL bit is 1 (transmit data output on the rising edge of the transmit/

receive clock and receive data input on the falling edge).

2. The UiRB register is undefined when an overrun error occurs. The IR bit in the SiRIC register does not change to

1 (interrupt requested).

Table 18.14 Special Mode 2 Specifications

Item Specification

Data format 8-bit character length

Transmit/receive clock • The CKDIR bit in the UiMR register is set to 0 (internal clock) (i = 0 to 6):

fx = f1, f8, f2n m: UiBRG register setting value, 00h to FFh

• The CKDIR bit is set to 1 (external clock): input to the CLKi pin

Transmit/receive control SS function

Transmit start conditions The conditions for starting data transmission are as follows (1):

• The TE bit in the UiC1 register is 1 (transmission enabled)

• The TI bit in the UiC1 register is 0 (data held in the UiTB register)

Receive start conditions The conditions for starting data reception are as follows (1):

• The RE bit in the UiC1 register is 1 (reception enabled)

• The TE bit in the UiC1 register is 1 (transmission enabled)

• The TI bit in the UiC1 register is 0 (data held in the UiTB register)

Interrupt request generating

timing

In transmit interrupt, one of the following conditions can be selected by setting the UiIRS

bit in registers U0C1 to U6C1:

• The UiIRS bit is 0 (transmit buffer is empty):

when data is transferred from the UiTB register to the UARTi transmit register (when

the transmission has started)

• The UiIRS bit is 1 (transmission is completed):

when data transmission from the UARTi transmit register is completed

In receive interrupt,

• When data is transferred from the UARTi receive register to the UiRB register (when

the reception is completed)

Error detection Overrun error (2)

This error occurs when the seventh bit of the next data has been received before

reading the UiRB register

Other functions • CLK polarity

Rising or falling edge of the transmit/receive clock for transfer data input and output

• Bit order selection

LSB first or MSB first

• Continuous receive mode

Data reception is enabled by a read access to the UiRB register

• Serial data logic inversion

This function logically inverses transmit/receive data

• Clock phase selection

One of four combinations of transmit/receive clock polarity and phases

•SSi input pin function

Output pin can be high-impedance when the SSi pin is high

2m1+

---------------------

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R32C/117 Group 18. Serial Interface

Table 18.15 lists register settings in special mode 2.

Table 18.15 Register Settings in Special Mode 2 (i = 0 to 6)

UiMR 7 to 4 Set the bits to 0000b

CKDIR Set the bit to 0 in master mode and set it to 1 in slave mode

SMD2 to SMD0 Set the bits to 001b

UiC0 UFORM Select either LSB first or MSB first

CKPOL Clock phase can be set by the combination of bits CKPOL and CKPH in

the UiSMR3 register

5 Set the bit to 0

CRD Set the bit to 1

TXEPT Transmit register empty flag

2 Set the bit to 0

CLK1 and CLK0 Select a count source for the UiBRG register

UiC1 7 and 6 Set the bits to 00b

UiRRM Set the bit to 1 to use continuous receive mode

UiIRS Select a source for UARTi transmit interrupt

RI Receive complete flag

RE Set the bit to 1 to enable data reception

TI Transmit buffer empty flag

TE Set the bit to 1 to enable data transmission/reception

UiSMR 7 to 0 Set the bits to 00h

UiSMR2 7 to 0 Set the bits to 00h

UiSMR3 7 to 5 Set the bits to 000b

ERR Mode fault flag

3 Set the bit to 0

DINC Set to 0 in master mode and set to 1 in slave mode

CKPH Clock phase can be set by the combination of bits CKPH and CKPOL in

the UiC0 register

SSE Set the bit to 1

UiSMR4 7 to 0 Set the bits to 00h

UiBRG 7 to 0 Set the bit rate

IFS0 IFS06 Select input pins for CLK3, RXD3, SRXD3, and SS3

IFS03 and IFS02 Select input pins for CLK6, RXD6, SRXD6, and SS6

UiTB 7 to 0 Set the data to be transmitted

UiRB OER Overrun error flag

7 to 0 Received data is read

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R32C/117 Group 18. Serial Interface

18.4.1 SSi Input Pin Function (i = 0 to 6)

Special mode 2 is selected by setting the SSE bit in the UiSMR3 register to 1 (SS function enabled).

The CTSi/RTSi/SSi pin functions as SSi input.

The DINC bit in the UiSMR3 register determines which MCU performs as a master or slave.

When multiple MCUs perform as masters (multi-master system), the SSi pin setting determines which

master MCU is active and when.

18.4.1.1 SS Function in Slave Mode

When the DINC bit is 1 (slave mode) while input at the SSi pin is high, the STXDi pin becomes high-

impedance and the clock input at the CLKi pin is ignored. When input at the SSi pin is low, the clock

input is valid and serial data is output from the STXDi pin to enable serial communication.

18.4.1.2 SS Function in Master Mode

When the DINC bit is 0 (master mode) while input at the SSi pin is high, which means there is the only

one master MCU or no other master MCU is active, the MCU as master starts communication. The

master provides the transmit/receive clock output at the CLKi pin. When input at the SSi pin is low,

which means that there are more masters, pins TXDi and CLKi become high-impedance. This error is

called a mode fault. It can be verified using the ERR bit in the UiSMR3 register. The ongoing data

transmission/reception does not stop even if a mode fault occurs. To stop transmission/reception, bits

SMD2 to SMD0 in the UiMR register should be set to 000b (serial interface disabled).

Figure 18.37 Serial Bus Communication Control with the SSi Pin

MCU MCU

MCU

(Slave)

(Master)

(Slave)

P1_3

P1_2

SS0

CLK0

RXD0

TXD0

SS0

CLK0

STXD0

SRXD0

SS0

CLK0

STXD0

SRXD0

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R32C/117 Group 18. Serial Interface

18.4.2 Clock Phase Setting

The CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register select one of four

combinations of transmit/receive clock polarity and serial clock phase (i = 0 to 6).

The transmit/receive clock phase and polarity should be identical for the master device and the

communicating slave device.

18.4.2.1 Transmit/Receive Timing in Master Mode

When the DINC bit is 0 (master mode), the CKDIR bit in the UiMR register should be set to 0 (internal

clock) to generate the clock. Figure 18.38 shows transmit/receive timing of each clock phase.

Figure 18.38 Transmit/Receive Timing in Master Mode

SS input for the master

CKPOL = 0, CKPH = 0

Data input timing

Data output timing

(TXDi pin)

CKPOL = 1, CKPH = 1

CKPOL = 0, CKPH = 1

CKPOL = 1, CKPH = 0

D0 D1 D2 D3 D4 D5 D6 D7

Clock output (CLKi pin)

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R32C/117 Group 18. Serial Interface

18.4.2.2 Transmit/Receive Timing in Slave Mode

When the DINC bit is 1 (slave mode), the CKDIR bit in the UiMR register should be set to 1 (external

clock).

When the CKPH bit is 0 (no clock delay) while input at the SSi pin is high, the STXDi pin becomes high-

impedance. When input at the SSi pin is low, the conditions for data transmission are all met, but output

is undefined. Then the data transmission/reception starts synchronizing with the clock. Figure 18.39

shows the transmit/receive timing.

When the CKPH bit is 1 (clock delayed) while input at the SSi pin is high, the STXDi pin becomes high-

impedance. When input at the SSi pin is low, the first data is output. Then the data transmission starts

synchronizing with the clock. Figure 18.40 shows the transmit/receive timing.

Figure 18.39 Transmit/Receive Timing in Slave Mode (CKPH = 0)

Figure 18.40 Transmit/Receive Timing in Slave Mode (CKPH = 1)

SS input for the slave

Clock input (CLKi pin)

Data input timing

Data output timing

(STXDi pin)

CKPOL = 1, CKPH = 0

Hi-ZHi-Z D0 D1 D2 D3 D4 D5 D6 D7

CKPOL = 0, CKPH = 0

SS input for the slave

Clock input (CLKi pin)

Data input timing

Data output timing

(STXDi pin)

CKPOL = 1, CKPH = 1

CKPOL = 0, CKPH = 1

Hi-ZHi-Z D0 D1 D2 D3 D4 D5 D6 D7

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R32C/117 Group 18. Serial Interface

18.5 Notes on Serial Interface

18.5.1 Changing the UiBRG Register (i = 0 to 8)

• Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register. When these bits are

changed, the UiBRG register must be set again.

• When a clock is input immediately after the UiBRG register is set to 00h, the counter may become

FFh. In this case, it requires extra 256 clocks to reload 00h to the register. Once 00h is reloaded,

the counter performs the operation without dividing the count source according to the setting.

18.5.2 Synchronous Serial Interface Mode

18.5.2.1 Selecting an External Clock

• If an external clock is selected, the following conditions must be met while the external clock is held

high when the CKPOL bit in the UiC0 register is 0 (transmit data output on the falling edge of the

transmit/receive clock and receive data input on the rising edge), or while the external clock is held

low when the CKPOL bit is 1 (transmit data output on the rising edge of the transmit/receive clock

and receive data input on the falling edge) (i = 0 to 8):

- The TE bit in the UiC1 register is 1 (transmission enabled).

- The RE bit in the UiC1 register is 1 (reception enabled). This bit setting is not required when only

transmitting.

- The TI bit in the UiC1 register is 0 (data held in the UiTB register).

18.5.2.2 Receive Operation

• In synchronous serial interface mode, the transmit/receive clock is controlled by the transmit

control circuit. Set UARTi-associated registers for a transmit operation, even if the MCU is used

only for receive operation (i = 0 to 8). Dummy data is output from the TXDi pin while receiving when

the TXDi pin is set to output mode.

• When data is received continuously, an overrun error occurs when the RI bit in the UiC1 register is

1 (data held in the UiRB register) and the seventh bit of the next data is received in the UARTi

receive shift register. Then, the OER bit in the UiRB register becomes 1 (overrun error occurred). In

this case, the UiRB register becomes undefined. If an overrun error occurs, the IR bit in the SiRIC

18.5.3 Special Mode 1 (I2C Mode)

• To generate a START condition, STOP condition, or repeated START condition, set the STSPSEL

bit in the UiSMR4 register to 0 (i = 0 to 6). Then, wait at least a half clock cycle of the transmit/

receive clock to change the condition generate bits (STAREQ, RSTAREQ, or STPREQ bit) from 0

to 1.

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R32C/117 Group 18. Serial Interface

18.5.4 Reset Procedure on Communication Error

Operations which result in communication errors such as rewriting function select registers during

transmission/reception should not be performed. Follow the procedure below to reset the internal circuit

once the communication error occurs in the following cases: when the operation above is performed by

a receiver or transmitter or when a bit slip is caused by noise.

A. Synchronous Serial Interface Mode

(1) Set the TE bit in the UiC1 register to 0 (transmission disabled) and the RE bit to 0 (reception

disabled) (i = 0 to 8).

(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).

(3) Set bits SMD2 to SMD0 in the UiMR register to 001b (synchronous serial interface mode).

(4) Set the TE bit in the UiC1 register to 1 (transmission enabled) and the RE bit to 1 (reception

enabled) if necessary.

B. UART Mode

(1) Set the TE bit in the UiC1 register to 0 (transmission disabled) and the RE bit to 0 (reception

disabled).

(2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled).

(3) Set bits SMD2 to SMD0 in the UiMR register to 100b (UART mode, 7-bit character length), 101b

(UART mode, 8-bit character length), or 110b (UART mode, 9-bit character length).

(4) Set the TE bit in the UiC1 register to 1 (transmission enabled) and the RE bit to 1 (reception

enabled) if necessary.

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R32C/117 Group 19. A/D Converter

19. A/D Converter

The A/D converter consists of one 10-bit successive approximation A/D converter with a capacitive coupling

amplifier.

A/D converted results are stored in the A/D registers corresponding to selected pins. Results are stored in

the AD00 register only when the DMAC operating mode is enabled.

When the A/D converter is not in use, power consumption can be reduced by setting the VCUT bit in the

AD0CON1 register to 0 (VREF disconnected). This bit setting enables the power supply from the VREF pin

to the resistor ladder to stop.

Table 19.1 lists specifications of the A/D converter. Figure 19.1 shows a block diagram of the A/D converter.

Figures 19.2 to 19.7 show registers associated with the A/D converter.

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R32C/117 Group 19. A/D Converter

Notes:

1. The analog input voltage is not dependent on whether the sample and hold function is enabled or

disabled.

2. The AD frequency should be as follows:

• When VCC = 4.2 to 5.5 V, 16 MHz or below

• When VCC = 3.0 to 4.2 V, 10 MHz or below

• When not using the sample and hold function, 250 kHz or above

• When using the sample and hold function, 1 MHz or above

3. When AVCC = VREF = VCC, A/D input voltage for pins AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to

AN2_7, AN15_0 to AN15_7, ANEX0, and ANEX1 should be VCC or lower.

4. Specification of the 144-pin package. In the 100-pin package, 26 channels are available.

5. Pins AN15_0 to AN15_7 are not available in the 100-pin package.

Table 19.1 A/D Converter Specifications

Item Specification

A/D conversion method Capacitance-based successive approximation

Analog input voltage (1) 0 V to AVCC (VCC)

Operating clock, AD (2) fAD, fAD divided by 2, fAD divided by 3, fAD divided by 4, fAD divided by 6, or

fAD divided by 8

Resolution 8 bits or 10 bits

Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweet mode 0, repeat

sweep mode 1, multi-port single sweep mode, multi-port repeat sweep mode 0

Analog input pins (3) 34 (4)

8 pins each for AN, AN0, AN2, and AN15 (5)

2 function-extended input pins (ANEX0 and ANEX1)

A/D conversion start

conditions

• Software trigger

The ADST bit in the AD0CON0 register is set to 1 (A/D conversion started) by a

program

• External trigger (retrigger is enabled)

An input signal at the ADTRG pin switches from high to low after the ADST bit

is set to 1 by a program

• Hardware trigger (retrigger is enabled)

• Generation of a timer B2 interrupt request which has passed through the

circuit to set an interrupt generating frequency in the three-phase motor

control timers after the ADST bit is set to 1 by a program

Conversion rates per pin • Without sample and hold function

49 AD cycles at 8-bit resolution

59 AD cycles at 10-bit resolution

including 2 AD cycles for sampling time

• With sample and hold function

28 AD cycles at 8-bit resolution

33 AD cycles at 10-bit resolution

including 3 AD cycles for sampling time

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R32C/117 Group 19. A/D Converter

Figure 19.1 A/D Converter Block Diagram

Successive conversion register

Notes:

1. The Port P15 is available in the 144-pin package.

2. Ports P0 and P2 are available in single-chip mode.

Timer B2 interrupt request which

has passed through the three-phase

motor control timers’ circuit to set

the interrupt generating frequency

TRG0 bit in the

AD0CON2 register

TRG bit in the

AD0CON0 register

EXTRG0

000 AN2_0

AN2_2

AN2_1

AN2_3

AN2_4

AN2_5

AN2_6

AN2_7

AN_0

AN_2

AN_1

AN_3

AN_4

AN_5

AN_6

AN_7

AD00 register

AD07 register

AD06 register

AD05 register

AD04 register

AD03 register

AD02 register

AD01 register

Resistor ladder

AD0CON0 register

Bits CH2 to CH0 in the

AD0CON0 register

P9_6 ANEX1

P9_5 ANEX0

P10

fAD CKS1 bit in the

AD0CON1 register

Bits APS1 and APS0 in

the AD0CON2 register

P2 (2)

Decoder

ADTRG 0

Software trigger

001

010

011

100

101

110

111

000 AN0_0

AN0_2

AN0_1

AN0_3

AN0_4

AN0_5

AN0_6

AN0_7

P0 (2)

001

010

011

100

101

110

111

000 AN15_0

AN15_2

AN15_1

AN15_3

AN15_4

AN15_5

AN15_6

AN15_7

P15 (1)

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

Bits OPA1 and OPA0

in the AD0CON1

00 01 10 11

Compa-

rator 0

AD0CON1 register

AD0CON2 register

AD0CON3 register

AD0CON4 register

1/2

CKS2 bit in the

AD0CON3 register

1/2 1

1/2

1/3

CKS0 bit in the

AD0CON0 register

VREF

AVSS

VCUT bit in the

AD0CON1 register

AD

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R32C/117 Group 19. A/D Converter

Figure 19.2 AD0CON0 Register

A/D0 Control Register 0 (1)

Symbol

AD0CON0

Address

0396h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

Analog Input Pin Select Bit

(2, 3, 4)

0: Software trigger

1: External trigger or hardware trigger

(7)

A/D Operating Mode Select

Bit 0 (2, 5, 6)

Trigger Select Bit

b7 b6 b5 b4 b1b2b3 b0

Notes:

1. When this register is rewritten during an A/D conversion, the converted result is undefined.

2. Set the analog input pins again after changing the A/D operating mode.

3. This bit setting is enabled in one-shot mode or repeat mode.

4. Select a port from AN, AN0, AN2, or AN15 by using bits APS1 and APS0 in the AD0CON2 register.

5. When the MSS bit in the AD0CON3 register is 1 (multi-port sweep mode enabled), set bits MD1 and MD0 to

10b for multi-port single sweep mode and 11b for multi-port repeat sweep mode 0.

6. Set bits MD1 and MD0 to 10b or 11b when the MSS bit in the AD0CON3 register is 1.

7. To use the external trigger or the hardware trigger, select the source of the trigger by setting the TRG0 bit in

the AD0CON2 register. Then set the ADST bit to 1 after setting the TRG bit to 1.

8. The AD frequency should be as follows: 16 MHz or below when VCC = 5 V,

10 MHz or below when VCC = 3.3 V

The AD frequency is selected from the combination of bits CKS0, CKS1, and CKS2 shown as below:

b2 b1 b0

000:ANi_0

001:ANi_1

010:ANi_2

011:ANi_3

100:ANi_4

101:ANi_5

110:ANi_6

1 1 1 : ANi_7 (i = no value, 0, 2, 15)

b4 b3

0 0 : One-shot mode

0 1 : Repeat mode

1 0 : Single sweep mode

1 1 : Repeat sweep mode 0 or 1 RW

0: A/D conversion stopped

1: A/D conversion started (7)

A/D Conversion Start Bit RW

(See Note 8)Frequency Select Bit RW

CKS2 Bit in the

AD0CON3 Register AD

CKS0 Bit in the

AD0CON0 Register

fAD divided by 4

CKS1 Bit in the

AD0CON1 Register

fAD divided by 31

fAD divided by 20

fAD1

fAD divided by 80

fAD divided by 61

CH0

CH2

CH1

MD0

MD1

TRG

ADST

CKS0

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R32C/117 Group 19. A/D Converter

Figure 19.3 AD0CON1 Register

A/D0 Control Register 1 (1)

Symbol

AD0CON1

Address

0397h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

A/D Sweep Pin Select

Bit (2, 3)

b7 b6 b5 b4 b1b2b3 b0

In single sweep mode or repeat

sweep mode 0

b1 b0

0 0 : ANi_0, ANi_1

0 1 : ANi_0 to ANi_3

1 0 : ANi_0 to ANi_5

1 1 : ANi_0 to ANi_7

In repeat sweep mode 1 (4)

b1 b0

00:ANi_0

0 1 : ANi_0, ANi_1

1 0 : ANi_0 to ANi_2

1 1 : ANi_0 to ANi_3

In multi-port single sweep mode or

multi-port repeat sweep mode 0

b1 b0

1 1 : ANi_0 to ANi_7 (5)

(i = no value, 0, 2, 15)

0: VREF disconnected (9)

1: VREF connected (10)

A/D Operating Mode Select

Bit 1

VREF Connection Bit (8)

b7 b6

0 0 : No use of ANEX0 or ANEX1 pin

(convert input at pins ANi_0 to

ANi_7)

0 1 : Convert input at the ANEX0 pin

1 0 : Convert input at the ANEX1 pin

1 1 : External op-amp connected

External Op-Amp Connect

Mode Bit (11, 12)

0: Mode other than repeat sweep

mode 1

1: Repeat sweep mode 1(6)

8/10-bit Mode Select Bit 0: 8-bit mode

1: 10-bit mode RW

Frequency Select Bit (See Note 7) RW

Notes:

1. When this register is rewritten during A/D conversion, the converted result is undefined.

2. This bit setting is enabled in single sweep mode, repeat sweep mode 0, repeat sweep mode 1, multi-port

single sweep mode, or multi-port repeat sweep mode 0.

3. Select a port from AN, AN0, AN2, or AN15 by using bits APS1 and APS0 in the AD0CON2 register.

4. These pins are commonly used in A/D conversion when the MD2 bit is set to 1.

5. Set bits SCAN1 and SCAN0 to 11b in multi-port single sweep mode or multi-port repeat sweep mode 0.

6. When the MSS bit in the AD0CON3 register is 1 (multi-port sweep mode enabled), set the MD2 bit to 0.

7. Refer to the note on the CKS0 bit in the AD0CON0 register.

8. This bit controls the reference voltage to the A/D converter. It does not affect VREF performance of the D/A

converter.

9. Do not set the VCUT bit to 0 during A/D conversion.

10.When the VCUT bit is switched from 0 to 1, wait at least 1 µs before starting A/D conversion.

11.Bits OPA1 and OPA0 can be set to 01b or 10b only in one-shot mode or repeat mode. Set them to 00b or

11b in other modes.

12.Set bits OPA1 and OPA0 to 00b when the MSS bit in the AD0CON3 register is 1 (multi-port sweep mode

enabled).

SCAN0

SCAN1

MD2

BITS

CKS1

VCUT

OPA0

OPA1

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R32C/117 Group 19. A/D Converter

Figure 19.4 AD0CON2 Register

A/D0 Control Register 2 (1)

Symbol

AD0CON2

Address

0394h

Reset Value

XX0X X000b

RWFunctionBit Symbol Bit Name

—

0: Select ADTRG pin

1: Select a timer B2 interrupt request

(after counting the ICTB2 register )

in the three-phase motor control

timers

A/D Conversion Method

Select Bit

External Trigger Request

Source Select Bit

b7 b6 b5 b4 b1b2b3 b0

b2 b1

0 0 : AN_0 to AN_7, ANEX0, ANEX1

0 1 : AN15_0 to AN15_7

1 0 : AN0_0 to AN0_7

1 1 : AN2_0 to AN2_7

Reserved

0: Without sample and hold function

1: With sample and hold function RW

Analog Input Port Select Bit

(2, 3, 4)

No register bits; should be written with 0 and read as undefined

value

Should be written with 0 and read as

undefined value

Notes:

1. When this register is rewritten during A/D conversion, the converted result is undefined.

2. Set bits APS1 and APS0 to 01b when the MSS bit in the AD0CON3 register is 1 (multi-port sweep mode

enabled).

3. Do not set bits APS1 and APS0 to 01b in the 100-pin package when the MSS bit in the AD0CON3 register

is 0 (multi-port sweep mode disabled).

4. These bits can be set to 10b or 11b in single-chip mode only.

SMP

APS0

APS1

—

(b4-b3)

TRG0

—

(b7-b6)

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R32C/117 Group 19. A/D Converter

Figure 19.5 AD0CON3 Register

A/D0 Control Register 3 (1, 2)

Symbol

AD0CON3

Address

0395h

Reset Value

XXXX X000b

RWFunctionBit Symbol Bit Name

DMAC Operating Mode

Select Bit (3)

b7 b6 b5 b4 b1b2b3 b0

b4 b3

0 0 : AN_0 to AN_7

0 1 : AN15_0 to AN15_7

1 0 : AN0_0 to AN0_7

1 1 : AN2_0 to AN2_7

Reserved

0: DMAC operating mode disabled

1: DMAC operating mode enabled (4, 5) RW

Multi-port Sweep Status

Flag (8)

Set to 0. The read value is undefined

Multi-port Sweep Mode

Select Bit

0: Multi-port sweep mode disabled

1: Multi-port sweep mode enabled

(3, 6)

Frequency Select Bit (See Note 7) RW

Notes:

1. When this register is rewritten during A/D conversion, the converted result is undefined.

2. This register may be read incorrectly during A/D conversion. It should be read or written after the A/D

converter stops operating.

3. To set the MSS bit to 1, the DUS bit should be also set to 1.

4. When the DUS bit is set to 1, all A/D converted results are stored into the AD00 register.

5. Configure DMAC when it is used to transfer converted results.

6. To set the MSS bit to 1:

- Set the MD2 bit in the AD0CON1 register to 0 (mode other than repeat sweep mode 1).

- Set bits APS1 and APS0 in the AD0CON2 register to 01b (AN15_0 to AN15_7).

- Set bits OPA1 and OPA0 in the AD0CON1 register to 00b (no use of ANEX0 or ANEX1).

7. Refer to the note on the CKS0 bit in the AD0CON0 register.

8. This bit setting is enabled when the MSS bit is set to 1. The read value is undefined when the MSS bit is set

to 0.

0 0 0

DUS

MSS

CKS2

MSF0

MSF1

—

(b7-b5)

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R32C/117 Group 19. A/D Converter

Figure 19.6 AD0CON4 Register

Figure 19.7 Registers AD00 to AD07

A/D0 Control Register 4 (1)

Symbol

AD0CON4

Address

0392h

Reset Value

XXXX 00XXb

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

b3 b2

00:(Note 4)

0 1 : AN_0 to AN_7, AN15_0 to

AN15_7

1 0 : AN_0 to AN_7, AN0_0 to AN0_7

1 1 : AN_0 to AN_7, AN2_0 to AN2_7

Reserved

Should be written with 0 and read as

undefined value

Multi-port Sweep Port

Select Bit (2, 3)

Reserved Should be written with 0 and read as

undefined value

Notes:

1. When this register is rewritten during A/D conversion, the converted result is undefined.

2. Do not set bits MPS11 and MPS10 to 01b when using the 100-pin package.

3. Bits MPS11 and MPS10 can be set to 10b or 11b in single-chip mode only.

4. When the MSS bit in the AD0CON3 register is 0 (multi-port sweep mode disabled), set bits MSP11 and

MPS10 to 00b. When it is 1 (multi-port sweep mode enabled), set them to any value other than 00b.

00 0 0 0 0

—

(b1-b0)

MPS10

MPS11

—

(b7-b4)

A/D0 Register i (i = 0 to 7) (1 to 4)

Symbol

AD00, AD01

AD02, AD03

AD04, AD05

AD06, AD07

Address

0381h-0380h, 0383h-0382h

0385h-0384h, 0387h-0386h

0389h-0388h, 038Bh-038Ah

038Dh-038Ch, 038Fh-038Eh

Reset Value

0000 0000 XXXX XXXXb

b15 b7 b0b8

Function RW

ROThe lower byte in an A/D converted result

In 10-bit mode: 2 upper bits in an A/D converted result

In 8-bit mode: These bits are read as 0

Notes:

1. If this register is read by a program while the DMAC is configured to transfer converted results, the value is

undefined.

2. The register value written while the A/D converter stops operating is undefined.

3. Only the AD00 register is available when the DUS bit in the AD0CON3 register is 1 (DMAC operating mode

enabled). Other registers are undefined.

4. When a converted result is transferred by DMAC at 10-bit mode, the DMAC should be set for a 16-bit transfer.

ROThese bits are read as 0

—

(b7-b0)

—

(b9-b8)

—

(b15-b10)

Bit Symbol

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R32C/117 Group 19. A/D Converter

19.1 Mode Descriptions

19.1.1 One-shot Mode

In one-shot mode, the analog voltage applied to a selected pin is converted into a digital code only

once. Table 19.2 lists specifications of one-shot mode.

Table 19.2 One-shot Mode Specifications

Item Specification

Function Converts the analog voltage applied to a pin into a digital code only once. The

pin is selected by setting bits CH2 to CH0 in the AD0CON0 register, bits OPA1

and OPA0 in the AD0CON1 register, and bits APS1 and APS0 in the AD0CON2

Start conditions When the TRG bit in the AD0CON0 register is 0 (software trigger)

The ADST bit in the AD0CON0 register is set to 1 (A/D conversion started) by

a program.

When the TRG bit is 1 (external trigger or hardware trigger)

Set the TRG0 bit in the AD0CON2 register to select external trigger request

source.

• When 0 is selected,

an input signal at the ADTRG pin switches from high to low after the ADST bit

is set to 1 by a program.

• When 1 is selected,

generation of a timer B2 interrupt request which has passed through the

circuit to set the interrupt generating frequency in the three-phase motor

control timers after the ADST bit is set to 1 by a program.

Stop conditions • A/D conversion is completed (the ADST bit is set to 0 when the software

trigger is selected)

• The ADST bit is set to 0 (A/D conversion stopped) by a program

Interrupt request

generation timing

When A/D conversion is completed, an interrupt request is generated

Input pin to be selected One pin is selected from among AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to

AN2_7, AN15_0 to AN15_7, ANEX0, and ANEX1

Reading A/D converted

result

When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode

disabled)

Read the AD0j register corresponding to the selected pin (j = 0 to 7)

When the DUS bit is 1 (DMAC operating mode enabled)

Configure the DMAC (refer to 13. “DMAC”).

Then the A/D converted result is stored in the AD00 register after the

conversion is completed. The DMAC transfers the converted result from the

AD00 register to a given memory space.

Do not read the AD00 register by a program

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R32C/117 Group 19.  A/D Converter
19.1.2 Repeat Mode
In repeat mode, the analog voltage applied to a selected pin is repeatedly converted into a digital code.
Table 19.3 lists specifications of repeat mode.
Table 19.3 Repeat Mode Specifications
Item Specification
Function Converts the analog voltage input to a pin into a digital code repeatedly. The pin 
is selected by setting bits CH2 to CH0 in the AD0CON0 register, bits OPA1 and 
OPA0 in the AD0CON1 register, and bits APS1 and APS0 in the AD0CON2 
register
Start conditions When the TRG bit in the AD0CON0 register is 0 (software trigger)
The ADST bit in the AD0CON0 register is set to 1 (A/D conversion started) by 
a program.
When the TRG bit is 1 (external trigger or hardware trigger)
Set  the TRG0 bit in the AD0CON2 register to select external trigger request 
source.
• When 0 is selected,
an input signal at the ADTRG pin switches from high to low after the ADST bit 
is set to 1 by a program.
• When 1 is selected,
generation of a timer B2 interrupt request which has passed through the 
circuit to set the interrupt generating frequency in the three-phase motor 
control timers after the ADST bit is set to 1 by a program.
Stop conditions The ADST bit is set to 0 (A/D conversion stopped) by a program
Interrupt request 
generation timing
When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode 
disabled), no interrupt request is generated.
When the DUS bit is 1 (DMAC operating mode enabled), each time A/D 
conversion is completed, an interrupt request is generated
Analog voltage input 
pins
One pin is selected from among AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to 
AN2_7, AN15_0 to AN15_7, ANEX0, and ANEX1
Reading A/D converted 
result
When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode 
disabled)
Read the AD0j register corresponding to the selected pin (j = 0 to 7)
When the DUS bit is 1 (DMAC operating mode enabled)
• When the converted result is transferred by DMAC
Configure the DMAC (refer to 13. “DMAC”).
Then the A/D converted result is stored in the AD00 register after the 
conversion is completed. The DMAC transfers the converted result from the 
AD00 register to a given memory space.
Do not read the AD00 register by a program
• When the converted result is transferred by a program
Read the AD00 register after the IR bit in the AD0IC register becomes 1. Set 
the IR bit back to 0

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R32C/117 Group 19.  A/D Converter
19.1.3 Single Sweep Mode
In single sweep mode, the analog voltage applied to selected pins is converted one-by-one into a digital
code. Table 19.4 lists specifications of single sweep mode.
Table 19.4 Single Sweep Mode Specifications
Item Specification
Function Converts the analog voltage input to a set of pins into a digital code one-by-one. 
The pins are selected by setting bits SCAN1 and SCAN0 in the AD0CON1 
register and bits APS1 and APS0 in the AD0CON2 register
Start conditions When the TRG bit in the AD0CON0 register is 0 (software trigger)
The ADST bit in the AD0CON0 register is set to 1 (A/D conversion started) by 
a program.
When the TRG bit is 1 (external trigger or hardware trigger)
Set  the TRG0 bit in the AD0CON2 register to select external trigger request 
source.
• When 0 is selected,
an input signal at the ADTRG pin switches from high to low after the ADST bit 
is set to 1 by a program.
• When 1 is selected,
generation of a timer B2 interrupt request which has passed through the 
circuit to set the interrupt generating frequency in the three-phase motor 
control timers after the ADST bit is set to 1 by a program.
Stop conditions • A/D conversion is completed (the ADST bit is set to 0 when the software 
trigger is selected)
• The ADST bit is set to 0 (A/D conversion stopped) by a program
Interrupt request 
generation timing
When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode 
disabled) when a sweep is completed, an interrupt request is generated.
When the DUS bit is 1 (DMAC operating mode enabled), each time A/D 
conversion is completed, an interrupt request is generated
Analog voltage input 
pins
Selected from a group of 2 pins (ANi_0 and ANi_1), 4 pins (ANi_0 to ANi_3), 6 
pins (ANi_0 to ANi_5), or 8 pins (ANi_0 to ANi_7) (i = no value, 0, 2, 15)
Reading A/D converted 
result
When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode 
disabled)
Read the AD0j register corresponding to the selected pin (j = 0 to 7)
When the DUS bit is 1 (DMAC operating mode enabled)
Configure the DMAC (refer to 13. “DMAC”).
Then the A/D converted result is stored in the AD00 register after the 
conversion is completed. The DMAC transfers the converted result from the 
AD00 register to a given memory space.
Do not read the AD00 register by a program

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R32C/117 Group 19.  A/D Converter
19.1.4 Repeat Sweep Mode 0
In repeat sweep mode 0, the analog voltage applied to selected pins is repeatedly converted into a
digital code. Table 19.5 lists specifications of repeat sweep mode 0.
Table 19.5 Repeat Sweep Mode 0 Specifications
Item Specification
Function Converts the analog voltage input to a set of pins into a digital code repeatedly. 
The pins are selected by setting bits SCAN1 and SCAN0 in the AD0CON1 
register and APS1 and APS0 in the AD0CON2 register
Start conditions When the TRG bit in the AD0CON0 register is 0 (software trigger)
The ADST bit in the AD0CON0 register is set to 1 (A/D conversion started) by 
a program.
When the TRG bit is 1 (external trigger or hardware trigger)
Set  the TRG0 bit in the AD0CON2 register to select external trigger request 
source.
• When 0 is selected,
an input signal at the ADTRG pin switches from high to low after the ADST bit 
is set to 1 by a program.
• When 1 is selected,
generation of a timer B2 interrupt request which has passed through the 
circuit to set the interrupt generating frequency in the three-phase motor 
control timers after the ADST bit is set to 1 by a program.
Stop conditions The ADST bit is set to 0 (A/D conversion stopped) by a program
Interrupt request 
generation timing
When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode 
disabled), no interrupt request is generated. 
When the DUS bit is 1 (DMAC operating mode enabled), each time A/D 
conversion is completed, an interrupt request is generated
Analog voltage input 
pins
Selected from a group of 2 pins (ANi_0 and ANi_1), 4 pins (ANi_0 to ANi_3), 6 
pins (ANi_0 to ANi_5), or 8 pins (ANi_0 to ANi_7) (i = no value, 0, 2, 15)
Reading A/D converted 
result
When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode 
disabled)
Read the AD0j register corresponding to the selected pin (j = 0 to 7)
When the DUS bit is 1 (DMAC operating mode enabled)
• When the converted result is transferred by DMAC
Configure the DMAC (refer to 13. “DMAC”).
Then the A/D converted result is stored in the AD00 register after the 
conversion is completed. The DMAC transfers the converted result from the 
AD00 register to a given memory space.
Do not read the AD00 register by a program
• When the converted result is transferred by a program
Read the AD00 register after the IR bit in the AD0IC register becomes 1. Set 
the IR bit back to 0

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R32C/117 Group 19.  A/D Converter
19.1.5 Repeat Sweep Mode 1
In repeat sweep mode 1, the analog voltage applied to eight selected pins including one to four
prioritized pins is repeatedly converted into a digital code. Table 19.6 lists specifications of repeat
sweep mode 1.
Table 19.6 Repeat Sweep Mode 1 Specifications
Item Specification
Function The analog voltage applied to eight selected pins including one to four prioritized 
pins is repeatedly converted into a digital code. The prioritized pins are selected 
by setting bits SCAN1 and SCAN0 in the AD0CON1 register and bits APS1 and 
APS0 in the AD0CON2 register
For example, when AN_0 is selected, the A/D conversion is performed in the 
following order: AN_0AN_1AN_0AN_2AN_0AN_3•••
Start conditions When the TRG bit in the AD0CON0 register is 0 (software trigger)
The ADST bit in the AD0CON0 register is set to 1 (A/D conversion started) by a 
program.
When the TRG bit is 1 (external trigger or hardware trigger)
Set  the TRG0 bit in the AD0CON2 register to select external trigger request 
source.
• When 0 is selected,
an input signal at the ADTRG pin switches from high to low after the ADST bit 
is set to 1 by a program. Retrigger is invalid.
• When 1 is selected,
generation of a timer B2 interrupt request which has passed through the circuit 
to set the interrupt generating frequency in the three-phase motor control 
timers after the ADST bit is set to 1 by a program.
Stop conditions The ADST bit is set to 0 (A/D conversion stopped) by a program
Interrupt request 
generation timing
When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode 
disabled), no interrupt request is generated.
When the DUS bit is 1 (DMAC operating mode enabled), each time A/D 
conversion is completed, an interrupt request is generated
Analog voltage input 
pins
8 (ANi_0 to ANi_7) (i = no value, 0, 2, 15)
Prioritized pin(s) Selected from a group of 1 pin (ANi_0), 2 pins (ANi_0 and ANi_1), 3 pins (ANi_0 
to ANi_2), or 4 pins (ANi_0 to ANi_3) 
Reading A/D converted 
result
When the DUS bit in the AD0CON3 register is 0 (DMAC operating mode 
disabled)
Read the AD0j register corresponding to the selected pin (j = 0 to 7)
When the DUS bit is 1 (DMAC operating mode enabled)
• When the converted result is transferred by DMAC
Configure the DMAC (refer to 13. “DMAC”).
Then the A/D converted result is stored in the AD00 register after the 
conversion is completed. The DMAC transfers the converted result from the 
AD00 register to a given memory space.
Do not read the AD00 register by a program
• When the converted result is transferred by a program
Read the AD00 register after the IR bit in the AD0IC register becomes 1. Set 
the IR bit back to 0

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R32C/117 Group 19. A/D Converter

19.1.6 Multi-port Single Sweep Mode

In multi-port single sweep mode, the analog voltage applied to 16 selected pins is converted one-by-

one into a digital code. The DUS bit in the AD0CON3 register should be set to 1 (DMAC operating

mode enabled). Table 19.7 lists specifications of multi-port single sweep mode.

Table 19.7 Multi-port Single Sweep Mode Specifications

Item Specification

Function Converts the analog voltage input to a set of 16 selected pins into a digital code

one-by-one in the following order: AN_0 to AN_7ANi_0 to ANi_7 (i = 0, 2, 15)

The 16 pins are selected by setting bits MPS11 and MPS10 in the AD0CON4

For example, when bits MPS11 and MPS10 are set to 10b (AN_0 to AN_7,

AN0_0 to AN0_7), the analog voltage is converted into a digital code in the

following order:

AN_0AN_1AN_2AN_3AN_4AN_5AN_6AN_7AN0_0•••

AN0_6AN0_7

Start conditions When the TRG bit in the AD0CON0 register is 0 (software trigger)

The ADST bit in the AD0CON0 register is set to 1 (A/D conversion started) by a

program.

When the TRG bit is 1 (external trigger or hardware trigger)

Set the TRG0 bit in the AD0CON2 register to select external trigger request

source.

• When 0 is selected,

an input signal at the ADTRG pin switches from high to low after the ADST bit

is set to 1 by a program.

• When 1 is selected,

generation of a timer B2 interrupt request which has passed through the circuit

to set the interrupt generating frequency in the three-phase motor control

timers after the ADST bit is set to 1 by a program.

Stop conditions • A/D conversion is completed (the ADST bit is set to 0 when the software trigger

is selected)

• The ADST bit is set to 0 (A/D conversion stopped) by a program

Interrupt request

generation timing

Every time A/D conversion is completed (set the DUS bit to 1)

Analog voltage input

pins

A combination of pin group is selected from AN_0 to AN_7AN15_0 to AN15_7,

AN_0 to AN_7AN0_0 to AN0_7, or AN_0 to AN_7AN2_0 to AN2_7

Reading A/D converted

result

Set the DUS bit to 1 and configure the DMAC (refer to 13. “DMAC”).

Then the A/D converted result is stored in the AD00 register after the conversion

is completed. The DMAC transfers the converted result from the AD00 register to

a given memory space.

Do not read the AD00 register by a program

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R32C/117 Group 19. A/D Converter

19.1.7 Multi-port Repeat Sweep Mode 0

In multi-port repeat sweep mode 0, the analog voltage applied to 16 selected pins is repeatedly

converted into a digital code. The DUS bit in the AD0CON3 register should be set to 1 (DMAC

operating mode enabled). Table 19.8 lists specifications of multi-port repeat sweep mode 0.

Table 19.8 Multi-port Repeat Sweep Mode 0 Specifications

Item Specification

Function Converts the analog voltage input to a set of 16 selected pins into a digital code

repeatedly in the following order: AN_0 to AN_7ANi_0 to ANi_7 (i = 0, 2, 15)

The 16 pins are selected by setting bits MPS11 and MPS10 in the AD0CON4

For example, when bits MPS11 and MPS10 are set to 10b (AN_0 to AN_7,

AN0_0 to AN0_7),the analog voltage is converted into a digital code

repeatedly in the following order:

AN_0AN_1AN_2AN_3AN_4AN_5AN_6AN_7AN0_0•••

AN0_6AN0_7

Start conditions When the TRG bit in the AD0CON0 register is 0 (software trigger)

The ADST bit in the AD0CON0 register is set to 1 (A/D conversion started) by a

program.

When the TRG bit is 1 (external trigger or hardware trigger)

Set the TRG0 bit in the AD0CON2 register to select external trigger request

source.

• When 0 is selected,

an input signal at the ADTRG pin switches from high to low after the ADST bit

is set to 1 by a program.

• When 1 is selected,

generation of a timer B2 interrupt request which has passed through the circuit

to set the interrupt generating frequency in the three-phase motor control

timers after the ADST bit is set to 1 by a program.

Stop conditions The ADST bit is set to 0 (A/D conversion stopped) by a program

Interrupt request

generation timing

Every time A/D conversion is completed (set the DUS bit to 1)

Analog voltage input

pins

A combination of pin group is selected from AN_0 to AN_7AN15_0 to AN15_7,

AN_0 to AN_7AN0_0 to AN0_7, or AN_0 to AN_7AN2_0 to AN2_7

Reading A/D converted

result

Set the DUS bit to 1 and configure the DMAC (refer to 13. “DMAC”).

Then the A/D converted result is stored in the AD00 register after the conversion

is completed. The DMAC transfers the converted result from the AD00 register to

a given memory space.

Do not read the AD00 register by a program

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R32C/117 Group 19. A/D Converter

19.2 Functions

19.2.1 Resolution Selection

Resolution is selected by setting the BITS bit in the AD0CON1 register. When the BITS bit is set to 1

(10-bit precision), the A/D converted result is stored into bits 9 to 0 in the AD0i register (i = 0 to 7).

When the BITS bit is set to 0 (8-bit precision), the result is stored into bits 7 to 0 in the AD0i register.

19.2.2 Sample and Hold Function

This function improves the conversion rate per pin to 28 AD cycles at 8-bit resolution and 33 AD

cycles for 10-bit resolution. This function is available in all operating modes and is enabled by setting

the SMP bit in the AD0CON2 register to 1 (with sample and hold function). Start A/D conversion after

setting the SMP bit.

19.2.3 Trigger Selection

A trigger to start A/D conversion is specified by the combination of TRG bit in the AD0CON0 register

and the TRG0 bit in the AD0CON2 register. Table 19.9 lists the settings of the trigger selection.

Notes:

1. A/D conversion starts when a trigger is generated while the ADST bit is 1 (A/D conversion started).

2. When an external trigger or a hardware trigger is generated during A/D conversion, the A/D converter

aborts the operation in progress. Then, it restarts the operation.

19.2.4 DMAC Operating Mode

DMAC operating mode can be used in all operating modes. DMAC operating mode is highly

recommended when the A/D converter is in multi-port single sweep mode or multi-port repeat sweep

mode 0. When the DUS bit in the AD0CON3 register is set to 1 (DMAC operating mode enabled), all A/

D converted results are stored in the AD00 register. The DMAC transfers the data from the AD00

should be selected for 8-bit resolution. For 10-bit resolution, 16-bit DMA transfer should be selected.

Refer to 13. “DMAC” for details.

Table 19.9 Trigger Selection Settings

Bit and Setting Trigger

AD0CON0 register AD0CON2 register

TRG = 0 —Software trigger

The ADST bit in the AD0CON0 register is set to 1

TRG = 1 (1, 2) TRG0 = 0 External trigger

Falling edge of a signal applied to the ADTRG pin

TRG0 = 1 Hardware trigger

Generation of a timer B2 interrupt request which has passed

through the circuit to set the interrupt generating frequency

in the three-phase motor control timers

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R32C/117 Group 19. A/D Converter

19.2.5 Function-extended Analog Input Pins

In one-shot mode and repeat mode, pins ANEX0 and ANEX1 can be used as analog input pins by

setting bits OPA1 and OPA0 in the AD0CON1 register (refer to Table 19.10). The A/D converted results

of pins ANEX0 and ANEX1 are stored into registers AD00 and AD01, respectively. However, when the

DUS bit in the AD0CON3 register is set to 1 (DMAC operating mode enabled), all results are stored into

the AD00 register.

To use function-extended analog input pins, bits APS1 and APS0 in the AD0CON2 register should be

set to 00b (AN0 to AN7, ANEX0, ANEX1 function as analog input ports) and the MSS bit in the

AD0CON3 register to 0 (multi-port sweep mode disabled).

19.2.6 External Operating Amplifier (Op-Amp) Connection Mode

In external op-amp connection mode, multiple analog inputs can be amplified by one external op-amp

using function-extended analog input pins ANEX0 and ANEX1.

When bits OPA1 and OPA0 in the AD0CON1 register are 11b (external op-amp connected), the voltage

applied to pins AN0 to AN7 is output from the ANEX0 pin. This output signal should be amplified by an

external op-amp and applied to the ANEX1 pin.

The analog voltage applied to the ANEX1 pin is converted into a digital code. The converted result is

stored in the corresponding AD0i register (i = 0 to 7). The conversion rate varies with the response of

the external op-amp. Note that the ANEX0 pin should not be connected to the ANEX1 pin directly.

To use external op-amp connection mode, set bits APS1 and APS0 in the AD0CON2 register to 00b.

Figure 19.8 shows an example of an external op-amp connection.

Figure 19.8 External Op-Amp Connection

Table 19.10 Function-extended Analog Input Pin Settings

AD0CON1 Register ANEX0 ANEX1

OPA1 OPA0

0 0 Not used Not used

0 1 Analog input Not used

1 0 Not used Analog input

1 1 Output to an external op-amp Input from an external op-amp

Successive conversion register

AN_0

AN_2

AN_1

AN_3

AN_4

AN_5

AN_6

AN_7

Analog input

ANEX1

External op-amp

ANEX0

Resistor ladder

Bits APS1 and APS0 in

the AD0CON2 register

00b

Compa-

rator 0

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Feb 18, 2013

R32C/117 Group 19. A/D Converter

19.2.7 Power Saving

When the A/D converter is not in use, power consumption can be reduced by setting the VCUT bit in

the AD0CON1 to 0 (VREF disconnected). With this bit setting, the reference voltage input pin (VREF)

can be disconnected from the resistor ladder, which enables the power supply from the VREF to the

resistor ladder to stop.

To use the A/D converter, set the VCUT bit to 1 (VREF connected) and wait at least 1 µs before setting

the ADST bit in the AD0CON0 register to 1 (A/D conversion started). Bits ADST and VCUT should not

be set to 1 simultaneously. The VCUT bit should not be set to 0 during A/D conversion.

The VCUT bit does not affect VREF performance of the D/A converter (refer to Figure 19.9).

Figure 19.9 Power Supply by VCUT Bit

19.2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion

Figure 19.10 shows an analog input pin and external sensor equivalent circuit.

To perform A/D conversion correctly, the internal capacitor (C) charging, shown in Figure 19.10, should

be completed within the specified period. This period, called the sampling time, is 2 AD cycles for

conversion without the sample and hold function and 3 AD cycles for conversion with this function.

Figure 19.10 Analog Input Pin and External Sensor Equivalent Circuitry

VREF To D/A converter

VCUT bit

AVSS

Resistor ladder

Sensor equivalent

circuit

MCU

VIN

CVC

VIN

R01UH0211EJ0120 Rev.1.20 Page 317 of 604

Feb 18, 2013

R32C/117 Group 19. A/D Converter

The voltage between pins (VC) is expressed as follows:

When t = T and the precision (error) is x or less,

Thus, output impedance of the sensor equivalent circuit (R0) is determined by the following formulas:

where:

T[s] = Sampling time

R0[] = Output impedance of the sensor equivalent circuit

VC = Potential difference between edges of capacitor C

R[] = Internal resistance of the MCU

x[LSB] = Precision (error) of the A/D converter

y[step] = Resolution of the A/D converter (1024 steps at 10-bit mode, 256 steps at 8-bit mode)

When AD = 10 MHz, the A/D conversion mode is 10-bit resolution with the sample and hold function,

the output impedance (R0) with the precision (error) of 0.1 LSB or less is determined by the following

formula:

Using T = 0.3 µs, R = 2.0 k(reference value), C = 6.5 pF (reference value), x = 0.1, y = 1024,

Thus, the allowable output impedance of the sensor equivalent circuit (R0), making the precision (error)

of 0.1 LSB or less, should be less than 3 k

The actual error, however, is the value of absolute precision added to the 0.1 LSB mentioned above.

VC VIN 1e

CR0R+

--------------------------–

–







VC VIN x

-- VIN–VIN 1x

--–





CR0R+

--------------------------– x

--=

CR0R+



--------------------------– x

--ln=

R0T

--ln

------------ R––=

R00.3 10 6–



6.5 10 12–

1n0.1

1024

------------

----------------------------------------------------–2.010

–=

2998=

R01UH0211EJ0120 Rev.1.20 Page 318 of 604

Feb 18, 2013

R32C/117 Group 19. A/D Converter

19.3 Notes on A/D Converter

19.3.1 Notes on Designing Boards

• Three capacitors should be placed between the AVSS pin and pins such as AVCC, VREF, and

analog inputs (AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, and AN15_0 to AN15_7) to

avoid erroneous operations caused by noise or latchup, and to reduce conversion errors. Figure

19.11 shows an example of pin configuration for A/D converter.

Figure 19.11 Pin Configuration for the A/D Converter

• Do not use AN_4 to AN_7 for analog input if the key input interrupt is to be used. Otherwise, a key

input interrupt request occurs when the A/D input voltage becomes VIL or lower.

• When AVCC = VREF = VCC, A/D input voltage for pins AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to

AN2_7, AN15_0 to AN15_7, ANEX0, and ANEX1 should be VCC or lower.

MCU

AVCC

VREF

AVSS

Analog input pins

C1 C2

Notes:

1. C1 0.47 µF, C2 0.47 µF, and C3 100 pF (reference values)

2. The traces for the capacitor and the MCU should be as short and wide as physically possible.

R01UH0211EJ0120 Rev.1.20 Page 319 of 604

Feb 18, 2013

R32C/117 Group 19. A/D Converter

19.3.2 Notes on Programming

• The following registers should be written while A/D conversion is stopped. That is, before a trigger

occurs: AD0CON0 (except the ADST bit), AD0CON1, AD0CON2, AD0CON3, and AD0CON4.

• When the VCUT bit in the AD0CON1 register is changed from 0 (VREF connected) to 1 (VREF

disconnected), wait for at least 1 µs before starting A/D conversion. When not performing A/D

conversion, set the VCUT bit to 0 to reduce power consumption.

• Set the port direction bit for the pin to be used as an analog input pin to 0 (input). Set the ASEL bit

of the corresponding port function select register to 1 (port is used as A/D input).

• When the TRG bit in the AD0CON0 register is 1 (external trigger or hardware trigger), set the

corresponding port direction bit (PD9_7 bit) for the ADTRG pin to 0 (input).

• The AD frequency should be 16 MHz or lower when VCC is 4.2 to 5.5 V, and 10 MHz or lower

when VCC is 3.0 to 4.2 V. It should be 1 MHz or higher when the sample and hold function is

enabled. If not, it should be 250 kHz or higher.

• When A/D operating mode (bits MD1 and MD0 in the AD0CON0 register or the MD2 bit in the

AD0CON1 register) has been changed, reselect analog input pins by setting bits CH2 to CH0 in

the AD0CON0 register or bits SCAN1 and SCAN0 in the AD0CON1 register.

• If the AD0i register is read when the A/D converted result is stored to the register, the stored value

may have an error (i = 0 to 7). Read the AD0i register after A/D conversion is completed.

In one-shot mode or single sweep mode, read the AD0i register after the IR bit in the AD0IC

In repeat mode, repeat sweep mode 0, or repeat sweep mode 1, an interrupt request can be

generated each time A/D conversion is completed when the DUS bit in the AD0CON3 register is 1

(DMAC operating mode enabled). Similar to the other modes above, read the AD00 register after

the IR bit in the AD0IC register becomes 1 (interrupt requested).

• When an A/D conversion is halted by setting the ADST bit in the AD0CON0 register to 0, the

converted result is undefined. In addition, the unconverted AD0i register may also become

undefined. Consequently, the AD0i register should not be used just after A/D conversion is halted.

• External triggers cannot be used in DMAC operating mode. When the DMAC is configured to

transfer converted results, do not read the AD00 register by a program.

• While in single sweep mode, if A/D conversion is halted by setting the ADST bit in the AD0CON0

sweep is not completed. To halt A/D conversion, disable interrupts before setting the ADST bit to 0.

R01UH0211EJ0120 Rev.1.20 Page 320 of 604

Feb 18, 2013

R32C/117 Group 20. D/A Converter

20. D/A Converter

The MCU has two separate 8-bit R-2R resistor ladder D/A converters.

Digital code is converted to an analog voltage when a value is written to the corresponding DAi register

(i = 0, 1). The DAiE bit in the DACON register determines whether the D/A conversion result is output or

not. Set the DAiE bit to 1 (output enabled) to output the converted value. This bit setting disables a pull-up

resistor for the corresponding port.

Analog voltage to be output (V) is calculated based on the value (n) set in the DAi register (n is a decimal

number).

Table 20.1 lists specifications of the D/A converter. Figure 20.1 shows a block diagram of the D/A converter.

Figures 20.2 and 20.3 show registers associated with the D/A converter. Figure 20.4 shows a D/A converter

equivalent circuit.

When the D/A converter is not used, set the DAi register to 00h and the DAiE bit to 0 (output disabled).

Figure 20.1 D/A Converter Block Diagram

Table 20.1 D/A Converter Specifications

Item Specification

D/A conversion method R-2R resistor ladder

Resolution 8 bits

Analog output pins 2 channels

VVREF n



256

-------------------------

=(n = 0 to 255)

VREF: reference voltage

DA0E and DA1E: Bits in the DACON register

Lower byte of data bus

R-2R resistor ladder

DA1 register

R-2R resistor ladder

DA0E

DA1E

DA1

DA0

DA0 register

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Feb 18, 2013

R32C/117 Group 20. D/A Converter

Figure 20.2 DACON Register

Figure 20.3 Registers DA0 and DA1

Figure 20.4 D/A Converter Equivalent Circuitry

D/A Control Register

Symbol

DACON

Address

039Ch

Reset Value

XXXX XX00b

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

No register bits; should be written with 0 and read as undefined

value

0: Output disabled

1: Output enabled

D/A0 Output Enable Bit

—

0: Output disabled

1: Output enabled

D/A1 Output Enable Bit

DA0E

DA1E

—

(b7-b2)

D/A Register i (i = 0, 1)

Symbol

DA0, DA1

Address

0398h, 039Ah

Reset Value

Undefined

b7 b0

Setting RangeFunction

RW00h to FFhOutput value by the D/A conversion

DA0

Notes:

1. This figure applies when the DA0 register is 2Ah.

2. This circuitry also applies to D/A converter 1.

3. To reduce power consumption when the D/A converter is not in use, set the DAiE bit to 0 (output

disabled) and the DAi register to 00h to prevent the current from flowing into the R-2R resistor ladder

(i = 0, 1).

DA0E

LSBMSB

AVSS

VREF

DA0 register

RRRRRR

0101

R01UH0211EJ0120 Rev.1.20 Page 322 of 604

Feb 18, 2013

R32C/117 Group 21. CRC Calculator

21. CRC Calculator

The Cyclic Redundancy Check (CRC) calculator is used for detecting errors in data blocks. A generator

polynomial of CRC-CCITT (X16 + X12 + X5 + 1) generates the CRC.

The CRC is a 16-bit code generated for a given set of blocks of 8-bit data. It is set in the CRCD register

every time 1-byte data is written to the CRCIN register after a default value is set to the CRCD register.

Figure 21.1 shows a block diagram of the CRC calculator. Figures 21.2 and 21.3 show registers associated

with the CRC. Figure 21.4 shows an example of the CRC calculation.

Figure 21.1 CRC Calculator Block Diagram

Figure 21.2 CRCD Register

CRCD register

Upper byte of data bus

Lower byte of data bus

Lower byteUpper byte

CRC generator

X16 + X12 + X5 + 1

CRCIN register

CRC Data Register

Symbol

CRCD

Address

037Dh-037Ch

Reset Value

Undefined

b7 b0

Setting RangeFunction

RW0000h to FFFFh

The CRC calculation result is stored in the CRCD register.

When a default value in a reversed bit position is set in this

CRCIN register, the CRC in the reversed bit position is read

from this register

b15 b8

R01UH0211EJ0120 Rev.1.20 Page 323 of 604

Feb 18, 2013

R32C/117 Group 21. CRC Calculator

Figure 21.3 CRCIN Register

CRC Input Register

Symbol

CRCIN

Address

037Eh

Reset Value

Undefined

b7 b0

Setting RangeFunction

RW00h to FFh

This register is for input data.

Input data should be in the reversed bit position

R01UH0211EJ0120 Rev.1.20 Page 324 of 604

Feb 18, 2013

R32C/117 Group 21. CRC Calculator

Figure 21.4 CRC Calculation

CRC Calculation for R32C

CRC Calculation and Setting Procedure to Generate CRC for 80C4h

(1) Reverse the bit position of 80C4h in 1-byte units by a program

80h to 01h, C4h to 23h

(2) Set 0000h (default value in reversed bit position) in CRCD register

(3) Set 01h (80h in reversed bit position) in CRCIN register

(4) Set 23h (C4h in reversed bit position) in CRCIN register

As shown in (3) above, add 1000 0000 0000 0000 0000 0000b as 80h (1000 0000b) plus 16 digits to 0000 0000 0000

0000 0000 0000b as the default value of the CRCD register, 0000h plus eight digits to perform the modulo-2 division.

1000 0000 0000 0000 0000 0000

0001 0001 1000 1001b (1189h), the reversed-bit-position value of remainder 1001 0001 1000 1000b (9188h) can be

read from the CRCD register.

Generator Polynomial

1000 1000

data

1000 1000 0001 0000 1

1000 0001 0000 1000 0

1000 1000 0001 0000 1

1001 0001 1000 1000

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0

-1 = 1

CRC

Setting Procedure

Details of the CRC Calculation

1000 1000 0001 0000 1

When continuing on to (4) above, add 1100 0100 0000 0000 0000 0000b as C4h (1100 0100b) plus 16 digits to 1001

0001 1000 1000 0000 0000b as the remainder of (3) left in the CRCD register plus eight digits to perform the modulo-2

division.

0000 1010 0100 0001b (0A41h), the reversed-bit-position value of remainder 1000 0010 0101 0000b (8250h) can be

read from the CRCD register.

The modulo-2 calculation is

based on the following law

CRC: a remainder of the division as follows:

Generator Polynomial: X16 + X12 + X5 + 1(1 0001 0000 0010 0001b)

reversed-bit-position value in the CRCIN register

generator polynominal

0000h CRCD register

b15 b0

01h CRCIN register

1189h, CRC for 80h (9188h) in reversed bit position is

stored into the CRCD register in the third cycle.

1189h

b15

CRCD register

0A41h, CRC for 80C4h (8250h) in revered bit position is

stored into the CRCD register in the third cycle.

23h

0A41h

b0b15

CRCIN register

CRCD register

R01UH0211EJ0120 Rev.1.20 Page 325 of 604

Feb 18, 2013

R32C/117 Group 22. X-Y Conversion

22. X-Y Conversion

X-Y conversion rotates a 16 × 16-bit matrix data 90 degrees or reverses the bit position of 16-bit data.

X-Y conversion is set using the XYC register shown in Figure 22.1.

Data is written to the write-only XiR registers and converted data is read from the read-only YjR register (i =

0 to 15; j = 0 to 15). These registers are allocated to the same address. Figures 22.2 and 22.3 show

registers XiR and YjR, respectively. A write/read access to registers XiR and YjR should be performed in

16-bit units from an even address. 8-bit access operation results are undefined.

Figure 22.1 XYC Register

Figure 22.2 Registers X0R to X15R

X-Y Control Register

Symbol

XYC

Address

02E0h

Reset Value

XXXX XX00b

b7 b6 b5 b4 b1b2b3 b0

Function

Bit Symbol Bit Name RW

No register bits; should be written with 0 and read as undefined

value

0: Data rotation

1: No data rotation

Read Mode Set Bit

—

0: No bit position reverse

1: Bit position reverse

Write Mode Set Bit

XYC0

XYC1

—

(b7-b2)

Xi Register (i = 0 to 15) (1)

Symbol

X0R to X2R

X3R to X5R

X6R to X8R

X9R to X11R

X12R to X14R

X15R

Address

02C1h-02C0h, 02C3h-02C2h, 02C5h-02C4h

02C7h-02C6h, 02C9h-02C8h, 02CBh-02CAh

02CDh-02CCh, 02CFh-02CEh, 02D1h-02D0h

02D3h-02D2h, 02D5h-02D4h, 02D7h-02D6h

02D9h-02D8h, 02DBh-02DAh, 02DDh-02DCh

02DFh-02DEh

Reset Value

Undefined

b7 b0

Setting RangeFunction

WO0000h to FFFFh

b15 b8

Note:

1. A 16-bit write access to this register should be performed.

Input data for X-Y conversion

R01UH0211EJ0120 Rev.1.20 Page 326 of 604

Feb 18, 2013

R32C/117 Group 22. X-Y Conversion

Figure 22.3 Registers Y0R to Y15R

22.1 Data Conversion When Reading

Set the XYC0 bit in the XYC register to select a read mode for the YjR register. When the XYC0 bit is 0

(data rotation), bit j in the corresponding registers X0R to X15R is automatically read upon reading the

YjR register (j = 0 to 15).

More concretely, upon reading bit i (i = 0 to 15) in the Y0R register, the data of bit 0 in the XiR register is

read. That is, the read data of bit 0 in the Y15R register means the data of bit 15 in the X0R register and

the data of bit 15 in the Y0R register is identical to that of bit 0 in the X15R register.

Figure 22.4 shows the conversion table when the XYC0 bit is 0 and Figure 22.5 shows an example of X-Y

conversion.

Yj Register (j = 0 to 15) (1)

Symbol

Y0R to Y2R

Y3R to Y5R

Y6R to Y8R

Y9R to Y11R

Y12R to Y14R

Y15R

Address

02C1h-02C0h, 02C3h-02C2h, 02C5h- 02C4h

02C7h-02C6h, 02C9h-02C8h, 02CBh-02CAh

02CDh-02CCh, 02CFh-02CEh, 02D1h-02D0h

02D3h-02D2h, 02D5h-02D4h, 02D7h-02D6h

02D9h-02D8h, 02DBh-02DAh, 02DDh-02DCh

02DFh-02DEh

Reset Value

Undefined

b7 b0

Function

b15 b8

Note:

1. A 16-bit read access to this register should be performed.

Result of X-Y conversion

R01UH0211EJ0120 Rev.1.20 Page 327 of 604

Feb 18, 2013

R32C/117 Group 22. X-Y Conversion

Figure 22.4 Conversion Table (XYC0 Bit is 0)

Figure 22.5 X-Y Conversion

Bits in the XiR register

Bits in the YjR register

X0R

X1R

X2R

X3R

X4R

X5R

X6R

X7R

X8R

X9R

X10R

X11R

X12R

X13R

X14R

X15R

b15

Y0R

Y1R

Y2R

Y3R

Y4R

Y5R

Y6R

X7R

Y8R

Y9R

Y10R

Y11R

Y12R

Y13R

Y14R

Y15R

Addresses to be read

Addresses to be written

i = 0 to 15

j = 0 to 15

X0R

X1R

X2R

X3R

X4R

X5R

X6R

X7R

X8R

X9R

X10R

X11R

X12R

X13R

X14R

X15R

b15

b14

b13

b12

b11

b10

Y0R

Y1R

Y2R

Y3R

Y4R

Y5R

Y6R

X7R

Y8R

Y9R

Y10R

Y11R

Y12R

Y13R

Y14R

Y15R

b15

b14

b13

b12

b11

b10

Registers Registers

R01UH0211EJ0120 Rev.1.20 Page 328 of 604

Feb 18, 2013

R32C/117 Group 22. X-Y Conversion

When the XYC0 bit is set to 1 (no data rotation), the data of each bit in the YjR register is identical to that

written in the XiR register. Figure 22.6 shows the conversion table when the XYC0 bit is set to 1.

Figure 22.6 Conversion Table (XYC0 Bit is 1)

22.2 Data Conversion When Writing

Set the XYC1 bit in the XYC register to select a write mode for the XiR register.

When the XYC1 bit is set to 0 (no bit position reverse), the data is written in order. When it is set to 1 (bit

position reverse), the data is written in reversed order. Figure 22.7 shows the conversion table when the

XYC1 bit is set to 1.

Figure 22.7 Conversion Table (XYC1 Bit is 1)

i = 0 to 15

j = 0 to 15

Bits in the XiR register

Bits in the YjR register

X0R, Y0R

X1R, Y1R

X2R, Y2R

X3R, Y3R

X4R, Y4R

X5R, Y5R

X6R, Y6R

X7R, Y7R

X8R, Y8R

X9R, Y9R

X10R, Y10R

X11R, Y11R

X12R, Y12R

X13R, Y13R

X14R, Y14R

X15R, Y15R

b15 b0

Address to be written,

address to be read

Data to be

written

XiR register

(i = 0 to 15)

b15 b0

R01UH0211EJ0120 Rev.1.20 Page 329 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

23. Intelligent I/O

The intelligent I/O is a multifunctional I/O port for time measurement, waveform generation, variable

character length synchronous serial interface, and IEBus.

It consists of three groups each of which has one free-running 16-bit base timer and eight 16-bit registers for

time measurement or waveform generation.

Table 23.1 lists the functions and channels of the intelligent I/O.

Notes:

1. The time measurement and waveform generation functions share a pin.

2. Contact a Renesas Electronics sales office to use the optional features.

Each channel can be individually assigned for time measurement or waveform generation function.

Figures 23.1 to 23.3 show block diagrams of the intelligent I/O.

Table 23.1 Intelligent I/O Functions and Channels

Functions Group 0 Group 1 Group 2

Time

measurement (1)

Digital filter 8 channels 8 channels

Not availablePrescaler 2 channels 2 channels

Gating 2 channels 2 channels

Waveform

generation (1)

Single-phase waveform output mode 8 channels 8 channels 8 channels

Inverted waveform output mode 8 channels 8 channels 8 channels

SR waveform output mode 8 channels 8 channels 8 channels

Bit modulation PWM mode

Not available Not available

8 channels

RTP mode 8 channels

Parallel RTP mode 8 channels

Serial interface Variable character length synchronous

serial interface mode Not available Not available Available

IEBus mode (optional (2))

R01UH0211EJ0120 Rev.1.20 Page 330 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.1 Intelligent I/O Group 0 Block Diagram (j = 0 to 7)

DIV4 to DIV0, BCK1, and BCK0: Bits in the G0BCR0 register

BTS: Bit in the G0BCR1 register

BT0S: Bit in the BTSR register

CTS1, CTS0, DF1, DF0, GT, and PR: Bits in the G0TMCRj register

BT0R: Bit in the IIO7IR register

BTS

BT0S

IIO0_7 input

IIO0_5 input

IIO0_4 input

IIO0_3 input

IIO0_2 input

IIO0_1 input

IIO0_0 input

CTS1 and CTS0

Digital

filter

Digital

filter

1X Edge

selection

Digital

filter

IIO0_6 input

1Prescaler

Gate

Digital

filter

1Prescaler

Gate

Digital

filter

G0TM4, G0PO4

G0TM5, G0PO5

G0TM6, G0PO6

G0TM7, G0PO7

PWM output

G0TM2, G0PO2

G0TM3, G0PO3

G0TM0, G0PO0

G0TM1, G0PO1

PWM output PWM output PWM output

Interrupt

request

signals

Ch0 to Ch7

IIO0_4 output

IIO0_5 output

IIO0_6 output

IIO0_7 output

IIO0_2 output

IIO0_3 output

IIO0_0 output

IIO0_1 output

Note:

1. Each register is placed in a reset state after the clock is provided via the G0BCR0 register.

Two-phase pulse input

f1 11

BCK1 and BCK0

01 Divide-by-

2(n+1) divider

DIV4 to DIV0

fBT0 Base timer Base timer interrupt request

BT0R

Request by matching the base timer with the G0PO0 register

Group 0 base

timer reset

Base timer overflow

Request from group 1

Request from the INT0 pin or the INT1 pin

Reset

Digital

filter

Digital

filter

Digital

filter

Edge

selection

Edge

selection

Edge

selection

Edge

selection

Edge

selection

Edge

selection

Edge

selection

DF1 and DF0

CTS1 and CTS0

R01UH0211EJ0120 Rev.1.20 Page 331 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.2 Intelligent I/O Group 1 Block Diagram (j = 0 to 7)

DIV4 to DIV0, BCK1, and BCK0: Bits in the G1BCR0 register

BTS: Bit in the G1BCR1 register

BT1S: Bit in the BTSR register

CTS1, CTS0, DF1, DF0, GT, and PR: Bits in the G1TMCRj register

BT1R: Bit in the IIO4IR register

BTS

BT1S

IIO1_7 input

IIO1_5 input

IIO1_4 input

IIO1_3 input

IIO1_2 input

IIO1_1 input

IIO1_0 input

CTS1 and CTS0

Digital

filter

Digital

filter

1X Edge

selection

Digital

filter

IIO1_6 input

1Prescaler

Gate

Digital

filter

1Prescaler

Gate

Digital

filter

G1TM4, G1PO4

G1TM5, G1PO5

G1TM6, G1PO6

G1TM7, G1PO7

PWM output

G1TM2, G1PO2

G1TM3, G1PO3

G1TM0, G1PO0

G1TM1, G1PO1

PWM output PWM output PWM output

Interrupt

request

signals

Ch0 to Ch7

IIO1_4 output

IIO1_5 output

IIO1_6 output

IIO1_7 output

IIO1_2 output

IIO1_3 output

IIO1_0 output

IIO1_1 output

Note:

1. Each register is placed in a reset state after the clock is provided via the G1BCR0 register.

Two-phase pulse input

f1 11

BCK1 and BCK0

01 Divide-by-

2(n+1) divider

DIV4 to DIV0

fBT1 Base timer Base timer interrupt request

BT1R

Request by matching the base timer with the G1PO0 register

Group 1 base

timer reset

Base timer overflow

Request from group 0

Request from the INT0 pin or the INT1 pin

Reset

Digital

filter

Digital

filter

Digital

filter

Edge

selection

Edge

selection

Edge

selection

Edge

selection

Edge

selection

Edge

selection

Edge

selection

DF1 and DF0

CTS1 and CTS0

R01UH0211EJ0120 Rev.1.20 Page 332 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.3 Intelligent I/O Group 2 Block Diagram (j = 0 to 7)

DIV4 to DIV0

Note:

1. Each register is placed in a reset state after the clock is provided via the G2BCR0 register.

BTS

Request from group 1

ISCLK2

Digital

filter

IEIN/ISRXD2

OUTC2_1/

ISCLK2

Waveform

generation interrupt

request PO2jR

DIV4 to DIV0, BCK1, and BCK0: Bits in the G2BCR0 register

BTS: Bit in the G2BCR1 register

BT2S: Bit in the BTSR register

OPOL and IPOL: Bits in the G2CR register

DF: Bit in the IECR register

MOD2 to MOD0: Bits in the G2POCRj register

BT2R, PO2jR, IE0R to IE2R, SIO2TR, and SIO2RR: Bits in registers IIO3IR and IIO5IR to IIO11IR

Reset

Request by matching

the base timer with the

G2PO0

Group 2 base

timer reset

BCK1 and BCK0

MOD2 to MOD0

000 to 010,100 OUTC2_0/

ISTXD2/

IEOUT

MOD2 to MOD0

000 to

010,100

111

Divide-by-

2(n+1) divider

Real-time port

output value

G2PO0

G2PO1

G2PO2

G2PO3

G2PO4

G2PO5

G2PO6

G2PO7

Base timer

fBT2

BT2S

Base timer interrupt request BT2R

Overflow of bit 15 in the

base timer

PWM

output

control

Bit modulation PWM

OUTC2_2

OUTC2_3

OUTC2_4

OUTC2_5

OUTC2_6

OUTC2_7

G2TB register

ID detection

ALL “F” detection

Address detection

Request from the serial

interface

PWM

output

control

PWM

output

control

PWM

output

control

Statement length

detection

Transmit register

Transmit parity

calculation

Byte counter

Receive parity

calculation

G2RB register

Arbitration lost

detection

Start bit detection

Transmit

latch

Bit

counter

Clock

selector

IPOL

OPOL

IE start bit interrupt request: IE0R to IE2R

Synchronous serial interface receive

interrupt request: SIO2RR

IE transmit interrupt request:

IE0R to IE2R

IE receive interrupt request:

IE0R to IE2R

Synchronous serial interface transmit

interrupt request: SIO2TR

ACK calculation

IE, serial interface

interrupt control

Receive register

Output control

Polarity

inversion

Polarity

inversion

R01UH0211EJ0120 Rev.1.20 Page 333 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figures 23.4 to 23.17 show registers associated with the intelligent I/O base timer, time measurement, and

waveform generation (for registers associated with the serial interface, refer to Figures 23.33 to 23.40).

Figure 23.4 Registers G0BT to G2BT

b15 b8 b7 Symbol

G0BT, G1BT

G2BT

Address

01A1h-01A0h, 0121h-0120h

0161h-0160h

Reset Value

Undefined

Setting RangeFunction RW

Group i Base Timer Register (i = 0 to 2) (1)

Notes:

1. The GiBT register reflects the base timer value after a delay of a half fBTi cycle.

2. The base timer stops only when bits BCK1 and BCK0 in the GiBCR0 register are set to 00b (clock stopped).

However, the base timer can be in a “no-counting” state, holding the value 0000h, by setting the BTiS bit in

the BTSR register and the BTS bit in the GiBCR1 register to 0 (reset the base timer). When either of these

bits is set to 1 (start counting), this state is cleared and the base timer starts counting.

RW0000h to FFFFh

- While the base timer is running, this register indicates the

value of base timer; when a value is written, the counter

immediately starts counting from this value. The register is

set to 0000h when the base timer is reset

- While the base timer is being reset, this register is set to

0000h; the register is read as undefined value; no value

can be set (2)

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Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.5 Registers G0BCR0 to G2BCR0

Group i Base Timer Control Register 0 (i = 0 to 2)

Symbol

G0BCR0 to G2BCR0

Address

01A2h, 0122h, 0162h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

Count Source Select Bit

0: Overflow of bit 15 or bit 9

1: Overflow of bit 14

Count Source Divide Ratio

Select Bit

b7 b6 b5 b4 b1b2b3 b0

b1 b2

0 0 : Clock stopped

0 1 : Do not use this combination

1 0 : Two-phase pulse signal input (1)

11:f1

Base Timer Interrupt

Source Select Bit

Divide the count source by 2(n+1).

The count source is not divided when

n = 31 (n = 0 to 31).

b6 b5 b4 b3 b2

00000:divide-by-2 (n = 0)

00001:divide-by-4 (n = 1)

00010:divide-by-6 (n = 2)

11110:divide-by-62 (n = 30)

1 1 1 1 1 : no division (n = 31)

Note:

1. This bit setting is enabled only when bits UD1 and UD0 in the GjBCR1 register are set to 10b (two-phase

pulse signal processing mode) (j = 0, 1). Bits BCK1 and BCK0 should not be set to 10b in other modes or in

group 2.

BCK0

BCK1

DIV0

DIV1

DIV2

DIV3

DIV4

R01UH0211EJ0120 Rev.1.20 Page 335 of 604

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R32C/117 Group 23. Intelligent I/O

Figure 23.6 Registers G0BCR1 and G1BCR1

Group i Base Timer Control Register 1 (i = 0, 1)

Symbol

G0BCR1, G1BCR1

Address

01A3h, 0123h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

b6 b5

0 0 : Increment mode

0 1 : Increment/decrement mode

1 0 : Two-phase pulse signal

processing mode (6)

1 1 : Do not use this combination

Reserved Should be written with 0

Base Timer Reset Source

Select Bit 1 RW

Notes:

1. The group 0 base timer is reset by synchronizing with the reset of group 1 base timer, and vice versa.

2. The base timer is reset after two fBTi clock cycles when the base timer value matches the GiPO0 register

setting. When the RST1 bit is 1, the value of the GiPOj register used for waveform generation should be

smaller than that of the GiPO0 register (j = 1 to 7).

3. The base timer is reset by an input of low signal to the external interrupt input pin selected for the UDiZ

signal by the IFS2 register.

4. To start base timer group 0 and 1 individually, the BTS bit should be set to 1 after setting the BTkS bit in

the BTSR register to 0 (reset the base timer) (k = 0, 1).

5. To start the base timers of multiple groups simultaneously, the BTSR register should be used. The BTS bit

should be set to 0.

6. In two-phase pulse signal processing mode, the base timer is not reset, even if the RST1 bit is 1, if the

timer counter decrements after two clock cycles when the base timer value matches the GiPO0 register.

0: No reset

1: Match with the GiPO0 register (2)

Base Timer Reset Source

Select Bit 2 RW

0: No reset

1: Low signal input into the INT0/INT1

pin (3)

Base Timer Start Bit (4, 5) RW

0: Reset the base timer

1: Start counting

Increment/Decrement

Control Bit

Base Timer Reset Source

Select Bit 0

0: No reset

1: Synchronization with another base

timer reset (1)

Reserved RWShould be written with 0

0 0

RST0

RST1

RST2

—

(b3)

BTS

UD0

UD1

—

(b7)

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Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.7 G2BCR1 Register

Group 2 Base Timer Control Register 1

Symbol

G2BCR1

Address

0163h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

b6 b5 b4 b1b2b3 b0

Reserved

—

(b3) Should be written with 0

Base Timer Reset Source

Select Bit 1

RST1 RW

RST0

Notes:

1. The base timer is reset after two fBT2 clock cycles if the base timer value matches the G2PO0 register

setting. When the RST1 bit is set to 1, the value of G2POj register used for waveform generation or the

serial interface should be smaller than that of the G2PO0 register (j = 1 to 7).

2. To start the group 2 base timer, the BTS bit should be set to 1 after setting the BT2S bit in the BTSR

3. To start the base timers of multiple groups simultaneously, the BTSR register should be used. The BTS bit

should be set to 0.

4. This bit setting is enabled when the RTP bit in the G2POCRi register is set to 1 (real-time port used).

0: No reset

1: Match with the G2PO0 register (1)

Base Timer Reset Source

Select Bit 2

RST2 RW

0: No reset

1: Reset request from the serial

interface

Base Timer Start Bit (2, 3)

BTS RW

0: Reset the base timer

1: Start counting

PRP

Base Timer Reset Source

Select Bit 0

0: No reset

1: Synchronization with group1 base

timer reset

Parallel Real-time Port

Select Bit (4) RW

0: RTP output mode

1: Parallel RTP output mode

Reserved

—

(b6-b5) Should be written with 0 RW

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Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.8 BTSR Register

Base Timer Start Register (1, 2)

Symbol

BTSR

Address

0164h

Reset Value

XXXX 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

No register bits; should be written with 0 and read as undefined

value.

—

(b7-b4) —

Notes:

1. The following initial bit and register settings for the intelligent I/O should be performed:

(1) Set the G2BCR0 register to provide the clock to the group 2 base timer.

(2) Set all bits BT0S to BT2S to 0.

(3) Set other registers associated with the intelligent I/O.

The BTiS bit allows the base timers of two or all groups to start counting simultaneously (i = 0 to 2). To start

counting individually, the BTiS bit should be set to 0 and the BTS bit in the GiBCR1 register should be used.

2. Perform the following procedure to start the base timers of multiple groups simultaneously:

-Bits BCK1 to BCK0 and bits DIV4 to DIV0 in the GiBCR0 register to be used should be set identically (more than

one of i = 0 to 2).

-After bits BCK1 to BCK0 or bits DIV4 to DIV0 are changed, use the following procedure to start the base timers

twice:

(1) Set the BTiS bit to 1.

(2) Set the BTiS bit to 0 after one fBTi clock cycle.

(3) Set the BTiS bit to 1 again after one additional fBTi clock cycle.

Group 0 Base Timer Start

Bit

BT0S RW

0: Reset the base timer

1: Start counting

Group 1 Base Timer Start

Bit

BT1S RW

0: Reset the base timer

1: Start counting

Group 2 Base Timer Start

Bit

BT2S RW

0: Reset the base timer

1: Start counting

Reserved

—

(b3) RWShould be written with 0

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Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.9 Registers G0TMCR0 to G0TMCR7 and G1TMCR0 to G1TMCR7

Figure 23.10 Registers G0TPR6, G0TPR7, G1TPR6, and G1TPR7

Group i Time Measurement Control Register j (i = 0, 1; j = 0 to 7)

Symbol

G0TMCR0 to G0TMCR3

G0TMCR4 to G0TMCR7

G1TMCR0 to G1TMCR3

G1TMCR4 to G1TMCR7

Address

0198h, 0199h, 019Ah, 019Bh

019Ch, 019Dh, 019Eh, 019Fh

0118h, 0119h, 011Ah, 011Bh

011Ch, 011Dh, 011Eh, 011Fh

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Gating is cleared by setting this bit to

Time Measurement Trigger

Select Bit

Notes:

1. These functions are available in registers GiTMCR6 and GiTMCR7. Bits 4 to 7 in registers GiTMCR0 to

GiTMCR5 should be set to 0.

2. These bit settings are enabled when the GT bit is 1.

Digital Filter Select Bit

0: Gating disabled

1: Gating enabled

b1 b0

0 0 : No time measurement

0 1 : Rising edge

1 0 : Falling edge

1 1 : Both edges

b3 b2

0 0 : No digital filter used

0 1 : Do not use this combination

10:fBTi

11:f1

0: Gating not cleared

1: Gating cleared when the base

timer matches the GiPOk register

(k = j - 2)

0: Prescaler disabled

1: Prescaler enabled

Gating Select Bit (1)

Prescaler Select Bit (1)

Gating Clear Bit (1, 2)

Gating Clear Select Bit

(1, 2)

CTS0

CTS1

DF0

DF1

GOC

GSC

00h to FFh RW

Group i Time Measurement Prescaler Register j (i = 0, 1; j = 6, 7)

b7 b0 Symbol

G0TPR6, G0TPR7

G1TPR6, G1TPR7

Address

01A4h, 01A5h

0124h, 0125h

Reset Value

00h

Function Setting Range RW

Note:

1. The first prescaler, after the PR bit in the GiTMCRj register is changed from 0 (prescaler disabled) to 1

(prescaler enabled), may be divided by n rather than n+1. The subsequent prescaler is divided by n+1.

Time measurement is executed whenever a trigger input is

counted by n+1 (n = setting value) (1)

R01UH0211EJ0120 Rev.1.20 Page 339 of 604

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R32C/117 Group 23. Intelligent I/O

Figure 23.11 Registers G0TM0 to G0TM7 and G1TM0 to G1TM7

—RO

Group i Time Measurement Register j (i = 0, 1; j = 0 to 7)

Symbol

G0TM0, G0TM1

G0TM2, G0TM3

G0TM4, G0TM5

G0TM6, G0TM7

G1TM0, G1TM1

G1TM2, G1TM3

G1TM4, G1TM5

G1TM6, G1TM7

Address

0181h-0180h, 0183h-0182h

0185h-0184h, 0187h-0186h

0189h-0188h, 018Bh-018Ah

018Dh-018Ch, 018Fh-018Eh

0101h-0100h, 0103h-0102h

0105h-0104h, 0107h-0106h

0109h-0108h, 010Bh-010Ah

010Dh-010Ch, 010Fh-010Eh

Reset Value

Undefined

Function Setting Range RW

The base timer value is stored every measurement timing

b15 b0b8 b7

R01UH0211EJ0120 Rev.1.20 Page 340 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.12 Registers G0POCR0 to G0POCR7 and G1POCR0 to G1POCR7

Group i Waveform Generation Control Register j (i = 0, 1; j = 0 to 7)

Symbol

G0POCR0

G0POCR1 to G0POCR3

G0POCR4 to G0POCR7

G1POCR0

G1POCR1 to G1POCR3

G1POCR4 to G1POCR7

Address

0190h

0191h, 0192h, 0193h

0194h, 0195h, 0196h, 0197h

0110h

0111h, 0112h, 0113h

0114h, 0115h, 0116h, 0117h

Reset Value

0000 X000b

0X00 X000b

0000 X000b

0X00 X000b

b7 b6 b5 b4 b1b2b3 b0

Notes:

1. This bit setting is enabled only for even channels. In SR waveform output mode, the corresponding odd

channel (the next channel after an even channel) setting is ignored. Waveforms are only output from even

channels.

2. The setting value is output by a write operation to the IVL bit when the FSCj bit in the GiFS register is 0

(select the waveform generation) and the IFEj bit in the GiFE register is 1 (enable the channel j function).

3. This bit is available only in the GiPOCR0 register. Set bit 6 in registers GiPOCR1 to GiPOCR7 to 0.

4. To set the BTRE bit to 1, set bits BCK1 and BCK0 in the GiBCR0 register to 11b (f1) and bits UD1 and UD0

in the GiBCR1 register to 00b (increment mode).

5. The output level inversion is the final step in the waveform generation process. When the INV bit is 1, high

is output by setting the IVL bit to 0, and vice versa.

RWFunctionBit Symbol Bit Name

Default Output Value

Select Bit (2)

—

Operating Mode Select Bit

No register bit; should be written with 0 and read as undefined

value

0: Output low as default value

1: Output high as default value

b2 b1 b0

0 0 0 : Single-phase waveform

output mode

0 0 1 : SR waveform output mode (1)

0 1 0 : Inverted waveform output

mode

0 1 1 : Do not use this combination

1 0 0 : Do not use this combination

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

GiPOj Register Value

Reload Timing Select Bit

Output Level Inversion

Select Bit (5) RW

0: Do not invert the output level

1: Invert the output level

Base Timer Reset Enable

Bit (3)

MOD0

MOD1

MOD2

—

(b3)

IVL

RLD

BTRE

INV

Reload the value into the GiPOj

0: On a write access

1: When the base timer is reset

Reset the base timer when

0: Bit 15 overflows

1: Bit 9 overflows (4)

R01UH0211EJ0120 Rev.1.20 Page 341 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.13 Registers G2POCR0 to G2POCR7

Group 2 Waveform Generation Control Register j (j = 0 to 7)

Symbol

G2POCR0 to G2POCR3

G2POCR4 to G2POCR7

Address

0150h, 0151h, 0152h, 0153h

0154h, 0155h, 0156h, 0157h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Operating Mode Select Bit

(1)

Notes:

1. When the RTP bit is set to 1, the settings of bits MOD2 to MOD0 are disabled.

2. This bit setting is enabled only for even channels. In SR waveform output mode, the corresponding odd

channel (the next channel after an even channel) setting is ignored. Waveforms are only output from even

channels.

3. This bit setting is enabled only for channels 0 and 1 of group 2. To use the ISTXD2 or IEOUT pin as an

output, set bits MOD2 to MOD0 in the G2POCR0 register to 111b. To use the ISCLK2 pin, set the same bits

in the G2POCR1 register to 111b. This bit setting should only be performed with channels 0 and 1.

4. This bit setting is enabled when the RTP bit is 1 and the PRP bit in the G2BCR1 register is 1 (parallel RTP

output mode).

5. The output level inversion is the final step in the waveform generation process. When the INV bit is 1, high

is output by setting the IVL bit to 0, and vice versa.

b2 b1 b0

0 0 0 : Single waveform output mode

0 0 1 : SR waveform output mode (2)

0 1 0 : Inverted waveform output

mode

0 1 1 : Do not use this combination

1 0 0 : Bit modulation PWM output

mode

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Use an output for the serial

interface (3)

Default Output Value

Select Bit RW

0: Output low as default value

1: Output high as default value

G2POj Register Value

Reload Timing Select Bit

0: Reload the value into the G2POj

1: Reload the value into the G2POj

reset

Output Level Inversion

Select Bit (5) RW

0: Do not invert the output level

1: Invert the output level

Parallel Real-time Port

Output Trigger Select Bit (4) RW

0: Not triggered by matching the base

timer with registers G2PO0 to

G2PO7

1: Triggered by matching the base

timer with registers G2PO0 to

G2PO7

RWReal-time Port Select Bit

0: No real-time port function used

1: Use RTP output mode or parallel

RTP output mode

PRT

IVL

RLD

RTP

INV

MOD0

MOD1

MOD2

R01UH0211EJ0120 Rev.1.20 Page 342 of 604

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R32C/117 Group 23. Intelligent I/O

Figure 23.14 Registers G0PO0 to G0PO7, G1PO0 to G1PO7, and G2PO0 to G2PO7

Figure 23.15 Registers G0FS and G1FS

0000h to FFFFh RW

Group i Waveform Generation Register j (i = 0 to 2; j = 0 to 7)

b15 b0 Symbol

G0PO0 to G0PO2

G0PO3 to G0PO5

G0PO6, G0PO7

G1PO0 to G1PO2

G1PO3 to G1PO5

G1PO6, G1PO7

G2PO0 to G2PO2

G2PO3 to G2PO5

G2PO6, G2PO7

Address

0181h-0180h, 0183h-0182h, 0185h-0184h

0187h-0186h, 0189h-0188h, 018Bh-018Ah

018Dh-018Ch, 018Fh-018Eh

0101h-0100h, 0103h-0102h, 0105h-0104h

0107h-0106h, 0109h-0108h, 010Bh-010Ah

010Dh-010Ch, 010Fh-010Eh

0141h-0140h, 0143h-0142h, 0145h-0144h

0147h-0146h, 0149h-0148h, 014Bh-014Ah

014Dh-014Ch, 014Fh-014Eh

Reset Value

Undefined

Function Setting Range RW

b8 b7

- When the RLD bit in the GiPOCRj register is 0, the value is

reloaded into the GiPOj register immediately after being

written and is reflected in the output waveform

- When the RLD bit is 1, the value is reloaded when the base

timer is reset. The register indicates the written value until

the value is reloaded

Group i Function Select Register (i = 0, 1)

Symbol

G0FS, G1FS

Address

01A7h, 0127h

Reset Value

0000 0000b

RWFunction

Bit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Channel 0 Time

Measurement/Waveform

Generation Select Bit

0: Select the waveform generation

1: Select the time measurement

Channel 1 Time

Measurement/Waveform

Generation Select Bit

Channel 2 Time

Measurement/Waveform

Generation Select Bit

Channel 3 Time

Measurement/Waveform

Generation Select Bit

Channel 4 Time

Measurement/Waveform

Generation Select Bit

Channel 5 Time

Measurement/Waveform

Generation Select Bit

Channel 6 Time

Measurement/Waveform

Generation Select Bit

Channel 7 Time

Measurement/Waveform

Generation Select Bit

FSC0

FSC1

FSC2

FSC3

FSC4

FSC5

FSC6

FSC7

R01UH0211EJ0120 Rev.1.20 Page 343 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.16 Registers G0FE to G2FE

Figure 23.17 G2RTP Register

Group i Function Enable Register (i = 0 to 2)

Symbol

G0FE to G2FE

Address

01A6h, 0126h, 0166h

Reset Value

0000 0000b

RWFunction

Bit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Channel 0 Function Enable

Bit

0: Disable the channel j function

1: Enable the channel j function

(j = 0 to 7)

Channel 1 Function Enable

Bit

Channel 2 Function Enable

Bit

Channel 3 Function Enable

Bit

Channel 4 Function Enable

Bit

Channel 5 Function Enable

Bit

Channel 6 Function Enable

Bit

Channel 7 Function Enable

Bit

IFE0

IFE1

IFE2

IFE3

IFE4

IFE5

IFE6

IFE7

Group 2 RTP Output Buffer Register

Symbol

G2RTP

Address

0167h

Reset Value

0000 0000b

RWFunctionBit symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Channel 0 RTP Output

Buffer

0: Output a low level

1: Output a high level

Channel 1 RTP Output

Buffer

Channel 2 RTP Output

Buffer

Channel 3 RTP Output

Buffer

Channel 4 RTP Output

Buffer

Channel 5 RTP Output

Buffer

Channel 6 RTP Output

Buffer

Channel 7 RTP Output

Buffer

RTP0

RTP1

RTP2

RTP3

RTP4

RTP5

RTP6

RTP7

R01UH0211EJ0120 Rev.1.20 Page 344 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

23.1 Base Timer for Groups 0 to 2

The base timer is a free-running counter that counts an internally generated count source. Table 23.2 lists

specifications of the base timer. Figures 23.4 to 23.17 show registers associated with the base timer.

Figure 23.18 shows a block diagram of the base timer. Figures 23.19, 23.20, and 23.21 show operation

examples of the base timer for groups 0 and 1 in increment mode, increment/decrement mode, and two-

phase pulse signal processing mode, respectively.

R01UH0211EJ0120 Rev.1.20 Page 345 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Table 23.2 Base Timer Specifications (i = 0 to 2)

Item Specification

Count source (fBTi) f1 divided by 2(n+1) for groups 0 to 2, two-phase pulse input divided by

2(n+1) for groups 0 and 1

n: setting value using bits DIV4 to DIV0 in the GiBCR0 register

n = 0 to 31; however no division when n = 31

Count operations • Increment

• Increment/decrement

• Two-phase pulse signal processing

Count start conditions • To start each base timer individually,

The BTS bit in the GiBCR1 register is 1 (start counting)

• To start the base timers of multiple groups simultaneously,

The BTiS bit in the BTSR register is 1 (start counting)

Count stop condition The BTiS bit in the BTSR register and the BTS bit in the GiBCR1 register are

0 (reset the base timer)

Reset conditions • The base timer value matches the GiPO0 register setting

• An input of low signal into the external interrupt pin (INT0 or INT1) as

follows:

for group 0: selected using bits IFS23 and IFS22 in the IFS2 register

for group 1: selected using bits IFS27 and IFS26 in the IFS2 register

• The overflow of bit 15 or bit 9 in the base timer

• The base timer reset request from the communication functions (group 2)

Reset value 0000h

Interrupt request When the BTiR bit in the interrupt request register becomes 1 (interrupt

requested) by the overflow of bit 9, 14, or 15 in the base timer (refer to Figure

11.12)

Read from base timer • The GiBT register indicates a counter value while the base timer is running

• The GiBT register is undefined while the base timer is being reset

Write to base timer When a value is written while the base timer is running, the timer counter

immediately starts counting from this value. No value can be written while the

base timer is being reset

Other functions • Increment/decrement mode for groups 0 and 1

The base timer starts counting when the BTS or BTiS bit is set to 1. When

the base timer reaches FFFFh, it starts decrementing. When the RST1 bit

in the GiBCR1 register is 1 (the base timer is reset by matching with the

GiPO0 register), the timer counter starts decrementing two counts after the

base timer value matches the GiPO0 register setting. When the timer

counter reaches 0000h, it starts incrementing again (refer to Figure 23.20).

• Two-phase pulse signal processing mode for groups 0 and 1

Two-phase pulse signals at pins UDiA and UDiB are counted (refer to

Figure 23.21).

UDiA

The timer counter increments

on all edges

The timer counter decrements

on all edges

UDiB

R01UH0211EJ0120 Rev.1.20 Page 346 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.18 Base Timer Block Diagram (i = 0 to 2)

Bit configurations and functions vary by group.

Table 23.3 Base Timer Associated Register Settings (Common Settings for Time Measurement,

Waveform Generation, and Serial Interface) (i = 0 to 2)

G2BCR0 — Provide an operating clock to the BTSR register. Set to 0111 1111b

BTSR — Set to 0000 0000b

GiBCR0 BCK1 and BCK0 Select a count source

DIV4 to DIV0 Select a count source divide ratio

IT Select a base timer interrupt source

GiBCR1 RST2 to RST0 Select a timing for base timer reset

BTS Use this bit when each base timer individually starts counting

UD1 and UD0 Select a count mode in groups 0 and 1

GiPOCR0 BTRE Select a source for base timer reset

GiBT — Read or write the base timer value

The following register settings are required to set the RST1 bit to 1 (the base timer is reset by matching

with the GiPO0 register).

GiPOCR0 MOD2 to MOD0 Set to 000b (single-phase waveform output mode)

GiPO0 — Set the reset cycle

GiFS FSC0 Set the bit to 0 (select the waveform generation)

GiFE IFE0 Set the bit to 1 (channel operation starts)

Two-phase pulse input

(for groups 0 and 1)

BTS bit in the

GiBCR1 register

Match with the

GiPO0 register

Low signal input to the

INT0/INT1 pin

(for groups 0 and 1)

Request from the

communication

functions (for group 2)

BCK1 and BCK0

Overflow signal

Base timer interrput

request (refer to the

BTiR bit in the

intelligent I/O interrupt

request register)

fBTi Base timer

Base timer reset

BCK1, BCK0, and IT: Bits in the GiBCR0 register

RST2 to RST0: Bits in the GiBCR1 register

BTRE: Bit in the GiPOCR0 register

Divide-by-2(n+1)

divider

RST1

RST2

b14 b15

00 b9

BTRE

BTiS bit in the

BTSR register

RST0

A base timer reset

of the other groups

R01UH0211EJ0120 Rev.1.20 Page 347 of 604

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R32C/117 Group 23. Intelligent I/O

Figure 23.19 Base Timer Increment Mode for Groups 0 and 1 (i = 0, 1)

(A) When the IT bit in the GiBCR0 register is 0

(an interrupt is requested by the overflow of bit 15 in the base timer)

Overflow signal of bit 15

BTiR bit in the IIOjIR register

Write 0 by a program

to set to 0

This figure applies under the following conditions:

- The RST1 bit in the GiBCR1 register is 0 (the match with the GiPO0 register is not the reset source for the base

timer)

- Bits UD1 and UD0 in the GiBCR1 register are 00b (increment mode)

FFFFh

Base timer i

8000h

0000h

(B) When the IT bit in the GiBCR0 register is 1

(an interrupt is requested by the overflow of bit 14 in the base timer)

Overflow signal of bit 14

BTiR bit in the IIOjIR register

Write 0 by a program

to set to 0

This figure applies under the following conditions:

- The RST1 bit in the GiBCR1 register is 0 (the match with the GiPO0 register is not the reset source for the base

timer)

- Bits UD1 and UD0 in the GiBCR1 register are 00b (increment mode)

FFFFh

Base timer i 8000h

0000h

C000h

4000h

j = 7, 4

R01UH0211EJ0120 Rev.1.20 Page 348 of 604

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R32C/117 Group 23. Intelligent I/O

Figure 23.20 Base Timer Increment/Decrement for Groups 0 and 1 (i = 0, 1)

(A) When the IT bit in the GiBCR0 register is 0

(an interrupt is requested by the overflow of bit 15 in the base timer)

Overflow signal of bit 15

BTiR bit in the IIOjIR register

Write 0 by a program

to set to 0

FFFFh

Base timer i 8000h

0000h

(B) When the IT bit in the GiBCR0 register is 1

(an interrupt request is requested by the overflow of bit 14 in the base timer)

Overflow signal of bit 14

BTiR bit in the IIOjIR register

FFFFh

Base timer i 8000h

0000h

C000h

4000h

This figure applies under the following conditions:

- The RST1 bit in the GiBCR1 register is 0 (the match with the GiPO0 register is not the reset source for the base

timer)

- Bits UD1 and UD0 in the GiBCR1 register are 01b (increment/decrement mode)

This figure applies under the following conditions:

- The RST1 bit in the GiBCR1 register is 0 (the match with the GiPO0 register is not the reset source for the base

timer)

- Bits UD1 and UD0 in the GiBCR1 register are 01b (increment/decrement mode)

8002h

8000h

Base timer i

0000h

This figure applies under the following conditions:

- The GiPO0 register value is 8000h

- Bits UD1 and UD0 in the GiBCR1 register are 01b (increment/decrement mode)

j = 7, 4

j = 7, 4 Write 0 by a program

to set to 0

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R32C/117 Group 23. Intelligent I/O

Figure 23.21 Base Timer Two-phase Pulse Signal Processing Mode for Groups 0 and 1 (i = 0, 1)

(A) When the base timer is reset while it increments

UD0A/UD1A (A-phase)

min. 1 µs

Base timer i

(See Note 1)

Input

waveform

The base timer starts counting

min. 1 µs

The value becomes

0 in this timing

The value becomes

1 in this timing

fBTi

When no division of the

divide-by-2(n+1) divider is

selected

(B) When the base timer is reset while it decrements

Notes:

1. At least 1.5 fBTi clock cycles are required.

2. Set the RST2 bit in the GiBCR1 register to 1 in two-phase pulse signal processing mode.

UD0B/UD1B (B-phase)

INT0/INT1 (Z-phase) (2)

0mm+1 12

UD0A/UD1A (A-phase)

min. 1 µs

Base timer i

(See Note 1)

Input

waveform

The base timer starts counting

min. 1 µs

The value becomes

0 in this timing

The value becomes

FFFFh in this timing

fBTi

UD0B/UD1B (B-phase)

INT0/INT1 (Z-phase) (2)

0mm+1 FFFFh FFFEh

When no division of the

divide-by-2(n+1) divider is

selected

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R32C/117 Group 23. Intelligent I/O

23.2 Time Measurement for Groups 0 and 1

Every time an external trigger is input, the base timer value is stored into the GiTMj register (i = 0, 1; j = 0

to 7). Table 23.4 lists specifications of the time measurement and Table 23.5 lists its register settings.

Figures 23.22 and 23.23 show operation examples of the time measurement and Figure 23.24 shows

operation examples with the prescaler or gate function.

Table 23.4 Time Measurement Specifications (i = 0, 1; j = 0 to 7)

Item Specification

Time measurement

channels

Group 0: Channels 0 to 7

Group 1: Channels 0 to 7

Trigger input polarity Rising edge, falling edge, or both edges of the IIOi_j pin

Time measurement

start condition

The IFEj bit in the GiFE register is 1 (enable the channel j function) while the FSCj

bit in the GiFS register is 1 (select the time measurement)

Time measurement

stop condition

The IFEj bit is 0 (disable the channel j function)

Time measurement

timing

• Without the prescaler: every time a trigger is input

• With the prescaler for channels 6 and 7: every [GiTPRk register value + 1] times

a trigger is input (k = 6, 7)

Interrupt request When the TMijR bit in the interrupt request register becomes 1 (interrupt

requested) (refer to Figure 11.12)

IIOi_j input pin

function

Trigger input

Other functions • Digital filter

The digital filter determines a trigger input level every f1 or fBTi cycle and passes

the signals holding the same level during three sequential cycles

• Prescaler for channels 6 and 7

Time measurement is executed every [GiTPRk register value + 1] times a trigger

is input

• Gating for channels 6 and 7

This function disables any trigger input to be accepted after the time

measurement by the first trigger input. However, the trigger input can be

accepted again if any of following conditions are met while the GOC bit in the

GiTMCRk register is 1 (the gating is cleared when the base timer matches the

GiPOp register) (p = 4, 5; p = 4 when k = 6; p = 5 when k = 7):

• The base timer value matches the GiPOp register setting

• The GSC bit in the GiTMCRk register is 1

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R32C/117 Group 23. Intelligent I/O

Bit configurations and functions vary with channels and groups.

Registers associated with the time measurement should be set after setting the base timer-associated

registers.

Figure 23.22 Time Measurement Operation (1/2) (i = 0, 1; j = 0 to 7)

Table 23.5 Time Measurement (for Groups 0 and 1) Associated Register Settings (i = 0, 1; j = 0 to

7; k = 6, 7)

GiTMCRj CTS1 and CTS0 Select a time measurement trigger

DF1 and DF0 Select a digital filter

GT, GOC, GSC Select if the gating is used

PR Select if the prescaler is used

GiTPRk — Set the prescaler value

GiFS FSCj Set the bit to 1 (select the time measurement)

GiFE IFEj Set the bit to 1 (enable the channel j function)

Input to the

IIOi_j pin

FFFFh

TMijR bit

Base timer i

TMijR: Bits in registers IIO0IR to IIO11IR

Write 0 by a program to set to 0

GiTMj register

0000h

This figure applies under the following conditions:

- Bits CTS1 and CTS0 in the GiTMCRj register are 01b (rising edge as time measurement trigger), the PR bit is 0

(prescaler disabled), and the GT bit is to 0 (gating disabled)

- Bits RST2 to RST0 in the GiBCR1 register are 000b (reset the base timer) and bits UD1 and UD0 are 00b

(increment mode)

When the base timer is reset by matching with the GiPO0 register (bits RST2 to RST0 in the GiBCR1 register are

010b), the base timer becomes 0000h after it reaches the GiPO0 register setting value + 2.

n p

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R32C/117 Group 23. Intelligent I/O

Figure 23.23 Time Measurement Operation (2/2) (i = 0, 1; j = 0 to 7)

(A) When selecting the rising edge as a time measurement trigger

(bits CTS1 and CTS0 in the GiTMCRj register are 01b)

(B) When selecting both edges as a time measurement trigger

GiTMj register

Base timer i

fBTi

TMijR bit (1)

Input to the

IIOi_j pin

Notes:

1. Bits in registers IIO0IR to IIO11IR.

2. No interrupt occurs if the MCU receives a trigger signal when the TMijR bit is 1. However, the value of

GiTMj register changes.

nn+5n+8

Write 0 by a program

to set to 0

(See Note 2)

n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14

n+2 n+6 n+12

(bits CTS1 and CTS0 in the GiTMCRj register are 11b)

(bits DF1 and DF0 in the GiTMCRj register are 10b or 11b)

GiTMj register

Base timer i

fBTi

TMijR bit (1)

Input to the

IIOi_j pin

Notes:

1. Bits in registers IIO0IR to IIO11IR.

2. Input pulse applied to the IIOi_j pin requires at least 1.5 fBTi clock cycles.

nn+5 n+8

Write 0 by a program

to set to 0

Delayed by max. one clock

(See Note 2)

n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14

f1 or fBTi (1)

The trigger signal is delayed by

passing the digital filter

Maximum 3.5 f1 or fBTi

(1) clock cycles

Signals which do not hold the same level

during three sequential cycles are rejected

Trigger signal

after passing

the digital filter

Input to the

IIOi_j pin

Note:

1. fBTi when bits DF1 and DF0 are 10b, f1 when the bits are 11b.

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R32C/117 Group 23. Intelligent I/O

Figure 23.24 Prescaler and Gate Operations (i = 0, 1; j = 6, 7; k = 4, 5)

(A) Operation with the prescaler

(B) Operation with the gating

(the GiTPRj register is 02h and the PR bit in the GiTMCRj register is 1)

(the gating is cleared by matching the base timer value with the GiPOk register setting, and

bits GT and GOC in the GiTMCRj register are 1, respectively)

fBTi

GiTMj register

Base timer i

Input to the

IIOi_j pin

TMijR bit (1)

Note:

1. Bits in registers IIO0IR to IIO11IR.

Write 0 by a program to set to 0

IFEj bit in the

GiFE register

Internal time

measurement

trigger

Match signal with

the GiPOk register

setting

Gating control

signal

Gating Gating

FFFFh

0000h

GiPOk register value

This trigger input is disabled

by the gating

Gating cleared

fBTi

TMijR bit (2)

Base timer i

Internal time

measurement

trigger

Prescaler (1)

Notes:

1. This example applies to cycles following the first cycle after the PR bit in the GiTMCRj register is set to 1

(prescaler enabled).

2. Bits in registers IIO0IR to IIO11IR.

Write 0 by a program to set to 0

2 1 2

n+12n

GiTMj register

Input to the

IIOi_j pin

n-2 n-1 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13 n+14

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R32C/117 Group 23. Intelligent I/O

23.3 Waveform Generation for Groups 0 to 2

Waveforms are generated when the base timer value matches the GiPOj register setting (i = 0 to 2; j = 0

to 7).

Waveform generation has the following six modes:

• Single-phase waveform output mode for groups 0 to 2

• Inverted waveform output mode for groups 0 to 2

• Set/reset waveform output (SR waveform output) mode for groups 0 to 2

• Bit modulation PWM output mode for group 2

• Real-time port output (RTP output) mode for group 2

• Parallel real-time port output (parallel RTP output) mode for group 2

Table 23.6 lists registers associated with the waveform generation.

Bit configurations and functions vary with channels and groups.

Registers associated with the waveform generation should be set after setting the base timer-associated

registers.

Note:

1. This bit is available in the G2POCRj register only. Neither the G0POCRj nor G1POCRj register has it.

Table 23.6 Waveform Generation Associated Register Settings (i = 0 to 2; j = 0 to 7)

GiPOCRj MOD2 to MOD0 Select a waveform output mode

PRT (1) Set the bit to 1 to use parallel RTP output mode

IVL Select a default value

RLD Select a timing to reload the value into the GiPOj register

RTP (1) Set the bit to 1 to use RTP output mode or parallel RTP output mode.

The settings of bits MOD2 to MOD0 are disabled when this bit is set

to 1

INV Select if output level is inverted

G2BCR1 PRP Set the bit to 1 to use parallel RTP output mode

GiPOj — Set the timing to invert output waveform level

GiFS FSCj Set the bit to 0 (select the waveform generation) for groups 0 and 1

only

GiFE IFEj Set the bit to 1 (enable the channel j function)

G2RTP RTP0 to RTP7 Set the RTP output value in RTP output mode or parallel RTP output

mode

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R32C/117 Group 23. Intelligent I/O

23.3.1 Single-phase Waveform Output Mode for Groups 0 to 2

The output level at the IIOi_j pin (or OUTC2_j pin for group 2) becomes high when the base timer value

matches the GiPOj register (i = 0 to 2; j = 0 to 7). It switches to low when the base timer reaches 0000h.

If the IVL bit in the GiPOCRj register is set to 1 (output high as default value), a high level output is

provided when a waveform output starts. If the INV bit is set to 1 (invert the output level), a waveform

with an inverted level is output. Refer to Figure 23.25 for details on single-phase waveform mode

operation.

Table 23.7 lists specifications of single-phase waveform output mode.

Notes:

1. When the INV bit in the GiPOCRj register is 1 (invert the output level), the high and low widths are

inverted.

2. To use channels shared by time measurement and waveform generation, set the FSCj bit in the GiFS

Table 23.7 Single-phase Waveform Output Mode Specifications (i = 0 to 2)

Item Specification

Output waveform (1) • Free-running operation (when bits RST2 to RST0 in the GiBCR1 register

are 000b)

Cycle:

Low level width:

High level width:

m: GiPOj register setting value (j = 0 to 7), 0000h to FFFFh

• The base timer is reset by matching the base timer value with the GiPO0

Cycle:

Low level width:

High level width:

m: GiPOj register setting value (j = 1 to 7), 0000h to FFFFh

n: GiPO0 register setting value, 0001h to FFFDh

If , the output level is fixed to low

Waveform output start

condition (2)

The IFEj bit in the GiFE register is 1 (enable the channel j function) (j = 0 to 7)

Waveform output stop

condition

The IFEj bit is 0 (disable the channel j function)

Interrupt request When the POijR bit in the intelligent I/O interrupt request register becomes 1

(interrupt requested) by matching the base timer value with the GiPOj register

setting (refer to Figure 11.12)

IIOi_j output pin (or

OUTC2_j pin for group 2)

function

Pulse signal output

Other functions • Default value setting

This function determines the starting waveform output level

• Output level inversion

This function inverts the waveform output level and outputs the inverted

signal from the IIOi_j pin (or OUTC2_j pin for group 2)

65536

fBTi

---------------

fBTi

-----------

65536 m–

fBTi

-------------------------

n2+

fBTi

------------

fBTi

-----------

n2m–+

fBTi

----------------------

mn2+

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R32C/117 Group 23. Intelligent I/O

Figure 23.25 Single-phase Waveform Output Mode Operation (i = 0 to 2)

(A) Free-running operation (bits RST2 to RST0 in the GiBCR register are 000b)

IIOi_j pin (1)

FFFFh

Base timer i

0000h

IIOi_j pin (2)

POijR bit

Write 0 by a program

to set to 0

j = 0 to 7

m: GiPOj register setting value (0000h to FFFFh)

POijR: Bits in registers IIO0IR to IIO11IR

(B) The base timer is reset by matching with the GiPO0 register (bits RST2 to RST0 in the GiBCR register are 010b)

IIOi_j pin

n + 2

Base timer i

0000h

POijR bit

Write 0 by a program

to set to 0

j = 1 to 7

m: GiPOj register setting value (0000h to FFFFh)

n: GiPO0 register setting value (0001h to FFFDh)

POijR: Bits in registers IIO0IR to IIO11IR

Notes:

1. Output waveform when the INV bit in the GiPOCRj register is 0 (do not invert the output level) and the IVL

bit is 0 (output low as default value).

2. Output waveform when the INV bit is 0 (do not invert the output level) and the IVL bit is 1 (output high as

default value).

This figure applies under the following condition:

- Bits UD1 and UD0 in the GiBCR1 register are 00b (increment mode)

This figure applies under the following conditions:

- The IVL bit in the GiPOCRj register is 0 (output low as default value) and the INV bit is 0 (do not invert the output

level)

- Bits UD1 and UD0 in the GiBCR1 register are 00b (increment mode)

-m < n + 2

65536-m

fBTi

65536

fBTi

n+2-m

fBTi

n+2

fBTi

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R32C/117 Group 23. Intelligent I/O

23.3.2 Inverted Waveform Output Mode for Groups 0 to 2

The output level at the IIOi_j pin (or OUTC2_j pin for group 2) is inverted every time the base timer

value matches the GiPOj register setting (i = 0 to 2; j = 0 to 7).

Table 23.8 lists specifications of the inverted waveform output mode. Figure 23.26 shows an example of

the inverted waveform output mode operation.

Note:

1. To use channels shared by time measurement and waveform generation, set the FSCj bit in the GiFS

Table 23.8 Inverted Waveform Output Mode Specifications (i = 0 to 2)

Item Specification

Output waveform • Free-running operation (when bits RST2 to RST0 in the GiBCR1 register

are 000b)

Cycle:

High or low level width:

m: GiPOj register setting value (j = 0 to 7), 0000h to FFFFh

• The base timer is reset by matching the base timer value with the GiPO0

Cycle:

High or low level width:

n: GiPO0 register setting value, 0001h to FFFDh

GiPOj register setting value (j = 1 to 7), 0000h to FFFFh

If the GiPOj register setting  , the output level is not inverted

Waveform output start

condition (1)

The IFEj bit in the GiFE register is 1 (enable the channel j function) (j = 0 to 7)

Waveform output stop

condition

The IFEj bit is 0 (disable the channel j function)

Interrupt request When the POijR bit in the intelligent I/O interrupt request register becomes 1

(interrupt requested) by matching the base timer value with the GiPOj register

setting (refer to Figure 11.12)

IIOi_j output pin (or

OUTC2_j pin for group 2)

function

Pulse signal output

Other functions • Default value setting

This function determines the starting waveform output level

• Output level inversion

This function inverts the waveform output level and outputs the inverted

signal from the IIOi_j pin (or OUTC2_j pin for group 2)

65536 2

fBTi

------------------------

65536

fBTi

---------------

2n2+

fBTi

--------------------

n2+

fBTi

------------

n2+

R01UH0211EJ0120 Rev.1.20 Page 358 of 604

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R32C/117 Group 23. Intelligent I/O

Figure 23.26 Inverted Waveform Output Mode Operation (i = 0 to 2)

(A) Free-running operation (bits RST2 to RST0 in the GiBCR1 register are 000b)

IIOi_j pin (1)

FFFFh

Base timer i

0000h

IIOi_j pin (2)

POijR bit

Write 0 by a program

to set to 0

(B) The base timer is reset by matching with the GiPO0 register (bits RST2 to RST0 are 010b)

IIOi_j pin

n + 2

Base timer i

0000h

POijR bit

Write 0 by a program

to set to 0

Inverted

InvertedInverted Inverted

j = 0 to 7

m: GiPOj register setting value (0000h to FFFFh)

POijR: Bits in registers IIO0IR to IIO11IR

Notes:

1. Output waveform when the INV bit in the GiPOCRj register is 0 (do not invert the output level) and the

IVL bit is 0 (output low as default value).

2. Output waveform when the INV bit is 0 (do not invert the output level) and the IVL bit is 1 (output high as

default value).

This figure applies under the following condition:

- Bits UD1 and UD0 in the GiBCR1 register are 00b (increment mode)

j = 1 to 7

m: GiPOj register setting value (0000h to FFFFh)

n: GiPO0 register setting value (0001h to FFFDh)

POijR: Bits in registers IIO0IR to IIO11IR

This figure applies under the following conditions:

- The IVL bit in the GiPOCRj register is 0 (output low as default value) and the INV bit is 0 (do not invert the output level)

- Bits UD1 and UD0 in the GiBCR1 register are 00b (increment mode)

- m < n + 2

65536

fBTi

65536

fBTi

65536 × 2

fBTi

n + 2

fBTi

n + 2

fBTi

2(n + 2)

fBTi

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R32C/117 Group 23. Intelligent I/O

23.3.3 Set/Reset Waveform Output Mode (SR Waveform Output Mode) for Groups

0 to 2

The output level at the IIOi_j pin (or OUTC2_j pin for group 2) becomes high when the base timer value

matches the GiPOj register setting (i = 0 to 2; j = 0, 2, 4, 6). It becomes low when the base timer value

matches the GiPOk register setting or the base timer reaches 0000h (k = j + 1). When the IVL bit in the

GiPOCRj register is set to 1 (output high as default value), a high output level is provided when a

waveform output starts (j = 0 to 7). When the INV bit is set to 1 (invert the output level), a waveform with

inverted level is output. Refer to Figure 23.27 for details on SR waveform mode operation. Tables 23.9

and 23.10 list specifications of SR waveform output mode.

Notes:

1. When the INV bit in the GiPOCRj register is 1 (invert the output level), the high and low widths are

inverted.

2. Output period from a base timer reset until when the output level becomes high.

3. Output period from when the output level becomes low until the next base timer reset.

4. When the GiPO0 register resets the base timer, channel 0 and channel 1 SR waveform generation

functions are not available.

Table 23.9 SR Waveform Output Mode Specifications (i = 0 to 2) (1/2)

Item Specification

Output waveform (1) • Free-running operation (when bits RST2 to RST0 in the GiBCR1 register

are 000b)

(A)

High level width:

Low level width: (See Note 2) + (See Note 3)

(B)

High level width:

Low level width:

m: GiPOj register setting value (j = 0, 2, 4, 6), 0000h to FFFFh

n: GiPOk register setting value (k = j + 1), 0000h to FFFFh

• The base timer is reset by matching with the GiPO0 register (when bits

RST2 to RST0 are 010b) (4)

(A)

High level width:

Low width: (See Note 2) + (See Note 3)

(B)

High level width:

Low level width:

p: GiPO0 register setting value, 0001h to FFFDh

m: GiPOj register setting value (j = 2, 4, 6), 0000h to FFFFh

n: GiPOk register setting value (k = j + 1), 0000h to FFFFh

mn

nm–

fBTi

-------------

fBTi

-----------

65536 n–

fBTi

------------------------

mn

65536 m–

fBTi

-------------------------

fBTi

-----------

mnp2+

nm+

fBTi

-------------

fBTi

-----------

p2n–+

fBTi

---------------------

mp2n+

p2m–+

fBTi

----------------------

fBTi

-----------

mp2+

R01UH0211EJ0120 Rev.1.20 Page 360 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Note:

1. To use channels shared by time measurement and waveform generation, set the FSCj bit in the GiFS

Table 23.10 SR Waveform Output Mode Specifications (i = 0 to 2) (2/2)

Item Specification

Waveform output start

condition (1)

The IFEq bit in the GiFE register is 1 (enable the channel q function) (q = 0 to

Waveform output stop

condition

The IFEq bit is 0 (disable the channel q function)

Interrupt request When the POijR bit in the intelligent I/O interrupt request register becomes 1

(interrupt requested) by matching the base timer value with the GiPOj register

setting.

When the POikR bit becomes 1 (interrupt requested) by matching the base

timer value with the GiPOk register setting (refer to Figure 11.12)

IIOi_j output pin (or

OUTC2_j pin for group 2)

function

Pulse signal output

Other functions • Default value setting

This function determines the starting waveform output level

• Output level inversion

This function inverts the waveform output level and outputs the inverted

signal from the IIOi_j pin (or OUTC2_j pin for group 2)

R01UH0211EJ0120 Rev.1.20 Page 361 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.27 SR Waveform Output Mode Operation (i = 0 to 2)

(A) Free-running operation (bits RST2 to RST0 in the GiBCR1 register are 000b)

IIOi_j pin (1)

FFFFh

Base timer i

0000h

IIOi_j pin (2)

POijR bit

(B) The base timer is reset by matching with the GiPO0 register

IIOi_j pin

Base timer i

0000h

POijR bit

(bits RST2 to RST0 in the GiBCR1 register are 010b)

Write 0 by a program

to set to 0

POikR bit

n - m

fBTi

65536 - n + m

fBTi

65536

fBTi

n - m

fBTi

p + 2 - n + m

fBTi

p + 2

fBTi

Write 0 by a program

to set to 0

j = 0, 2, 4, 6; k = j + 1

m: GiPOj register setting value, 0000h to FFFFh

n: GiPOk register setting value, 0000h to FFFFh

POijR and POikR: Bits in registers IIO0IR to IIO11IR

Notes:

1. Output waveform when the INV bit in the GiPOCRj register is 0 (do not invert the output level) and the IVL bit is 0 (output

low as default value).

2. Output waveform when the INV bit is 0 (do not invert the output level) and the IVL bit is 1 (output high as default value).

This figure applies under the following conditions:

- Bits UD1 and UD0 in the GiBCR1 register are 00b (increment mode)

-m < n

Write 0 by a program

to set to 0

Write 0 by a program

to set to 0

j = 2, 4, 6; k = j + 1

m: GiPOj register setting value, 0000h to FFFFh

n: GiPOk register setting value, 0000h to FFFDh

p: GiPO0 register setting value, 0001h to FFFDh

POijR and POikR: Bits in registers IIO0IR to IIO11IR

This figure applies under the following conditions:

- The IVL bit is 0 (output low as default value) and the INV bit is 0 (do not invert the output level).

- Bits UD1 and UD0 in the GiBCR1 register are 00b (increment mode)

- m < n < p + 2

R01UH0211EJ0120 Rev.1.20 Page 362 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

23.3.4 Bit Modulation PWM Output Mode for Group 2

In bit modulation PWM output mode, a PWM output has 16-bit resolution.

Pulses are repeatedly output in a period of 1024 consecutive periods of span t. The period of span t is

. The 6 upper bits in the G2POj register determine the base low width (j = 0 to 7). The 10 lower

bits determine the number of span t, within a period, in which the low width is extended by the minimum

resolution bit width, that is, one clock cycle.

When the INV bit is set to 1 (invert the output level), the waveform with an inverted level is output.

Table 23.11 lists specifications of bit modulation PWM output mode. Table 23.12 lists the number of

modulated spans and span ts to be extended with the minimum resolution bit width. Figure 23.28 shows

an example of bit modulation PWM output mode operation.

Notes:

1. Bits RST2 and RST0 in the G2BCR1 register should be set to 000b to use bit modulation PWM

output mode.

2. When the INV bit in the G2POCRj register is set to 1 (invert the output level), the high and low widths

are inverted.

Table 23.11 Bit Modulation PWM Output Mode Specifications (j = 0 to 7)

Item Specification

Output waveform (1,2)

PWM-repeated period T:

Period of span t:

Low width: of m spans

of spans

Mean low width:

n: G2POj register setting value (6 upper bits), 00h to 3Fh

m: G2POj register setting value (10 lower bits), 000h to 3FFh

Waveform output start

condition

The IFEj bit in the G2FE register is 1 (enable the channel j function)

Waveform output stop

condition

The IFEj bit is 0 (disable the channel j function)

Interrupt request When the PO2jR bit in the interrupt request register becomes 1 (interrupt

requested) by matching the 6 lower bits of the base timer value with the 6

upper bits of the G2POj register setting (refer to Figure 11.12)

OUTC2_j pin function Pulse signal output pin

Other functions • Default value setting

This function determines the starting waveform output level

• Output level inversion

This function inverts the waveform output level and outputs the inverted

signal from the OUTC2_j pin

fBT2

------------

65536

fBT2

---------------64

fBT2

------------ 1024

=





fBT2

------------

n1+

fBT2

------------

fBT2

------------

1024 m–

fBT2

------------ nm

1024

------------+







R01UH0211EJ0120 Rev.1.20 Page 363 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.28 Bit Modulation PWM Output Mode Operation

Table 23.12 Number of Modulated Spans and Span t Extended Minimum Resolution Bit Width

Modulated Spans Span ts to be Extended with Minimum Resolution Bit Width

00 0000 0000b none

00 0000 0001b t512

00 0000 0010b t256 and t768

00 0000 0100b t128, t384, t640, and t896

00 0000 1000b t64, t192, t320, t448, t576, t704, t832, and t960

: :

10 0000 0000b t1, t3, t5, t7, ••• t1019, t1021, and t1023

m = 1, j = 0 to 7

PO2jR: Bits in registers IIO3IR to IIO11IR

This figure above applies under the following condition:

- The IVL bit in the G2POCRj register is 0 (output low as default value) and the INV bit is 0 (do not invert the

output level)

Internal signal

3Fh

00h

6 lower bits in

the base timer

OUTC2_j pin

G2POj register

Base width

n = 0 to 63 (3Fh)

b15 b10 b9 b0

Modulated spans

m = 0 to 1023 (3FFh)

PWM-repeated period T

1 span

fBT2

6 lower bits in

the base timer

3Fh

00h

Write 0 by a program

to set to 0

PO2jR bit Low

OUTC2_j pin

Low

Inverted Inverted

nn+1

Minimum resolution bit width

Write 0 by a program

to set to 0

t2 t3 t510 t511 t512 t514 t1022 t1023 t1024

Low width of m spans out of 1024 is extended by

minimum resolution bit width

t513

R01UH0211EJ0120 Rev.1.20 Page 364 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

23.3.5 Real-time Port Output Mode (RTP Output Mode) for Group 2

The OUTC2_j pin outputs the G2RTP register setting value in 1-bit units when the base timer value

matches the G2POj register setting (j = 0 to 7). Table 23.13 lists specifications of RTP output mode.

Figure 23.29 shows a block diagram of RTP output and Figure 23.30 shows an example of RTP output

mode operation.

Note:

1. The G2PO0 register should be set to between 0001h and FFFDh to set the base timer value to

0000h (bits RST2 to RST0 are set to 010b) when the base timer value matches the G2PO0 register

setting.

Figure 23.29 RTP Output Block Diagram

Table 23.13 RTP Output Mode Specifications (j = 0 to 7)

Item Specification

Waveform output start

condition

The IFEj bit in the G2FE register is 1 (enable the channel j function)

Waveform output stop

condition

The IFEj bit is 0 (disable the channel j function)

Interrupt request When the PO2jR bit in the interrupt request register becomes 1 (interrupt

requested) by matching the base timer value with the G2POj register setting

(0000h to FFFFh (1)) (refer to Figure 11.12)

OUTC2_j pin function RTP output pin

Other functions • Default value setting

This function determines the starting waveform output level

• Output level inversion

This function inverts the waveform output level and outputs the inverted

signal from the OUTC2_j pin

G2PO7 register

Base timer G2RTP register Real-time port output

G2PO0 register

RTP0

RTP6

RTP7

OUTC2_0

OUTC2_6

OUTC2_7

G2PO6 register

R01UH0211EJ0120 Rev.1.20 Page 365 of 604

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R32C/117 Group 23. Intelligent I/O

Figure 23.30 RTP Output Mode Operation

(A) Free-running operation (bits RST2 to RST0 in the G2BCR1 register are 000b)

RTPj bit in the

G2RTP register

FFFFh

Base timer 2

0000h

OUTC2_j pin

PO2jR bit

65535

Write 0 by a program

to set to 0

j = 0 to 7

m: G2POj register setting value, 0000h to FFFFh

PO2jR: Bits in registers IIO03R to IIO11IR

This figure applies under the following conditions:

- The IVL bit in the G2POCRj register is 0 (output low as default value) and the INV bit is 0 (do not invert the

output level).

(B) The base timer is reset by matching the base timer value with the G2PO0 register setting

n + 2

Base timer 2

0000h

PO2jR bit

mn + 2

Write 0 by a program to

set to 0

j = 1 to 7

m: G2POj register setting value, 0000h to FFFFh

n: G2POj register setting value, 0001h to FFFDh

PO2jR: Bits in registers IIO03R to IIO11IR

This figure applies under the following conditions:

- The IVL bit in the G2POCRj register is 0 (output low as default value) and the INV bit is 0 (do not invert the

output level).

-m < n + 2

(bits RST2 to RST0 are 010b)

OUTC2_j pin

1 001

RTPj bit 1 001

R01UH0211EJ0120 Rev.1.20 Page 366 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

23.3.6 Parallel Real-time Port Output Mode (RTP Output Mode) for Group 2

The OUTC2_j pin outputs all the G2RTP register setting values in 1-byte units when the base timer

value matches the G2POj register setting (j = 0 to 7). Table 23.14 lists specifications of parallel RTP

output mode. Figure 23.7 shows the G2BCR1 register. Figure 23.31 shows a block diagram of parallel

RTP output and Figure 23.32 shows an example of parallel RTP output mode operation.

Note:

1. The G2PO0 register should be set to between 0001h and FFFDh to set the base timer value to

0000h (bits RST2 to RST0 are set to 010b) when the base timer value matches the G2PO0 register

setting.

Figure 23.31 Parallel RTP Output Mode Block Diagram

Table 23.14 Parallel RTP Output Mode Specifications (j = 0 to 7)

Item Specification

Waveform output start

condition

The IFEj bit in the G2FE register is 1 (enable the channel j function)

Waveform output stop

Condition

The IFEj bit is 0 (disable the channel j function)

Interrupt request The PO2jR bit in the interrupt request register becomes 1 (interrupt

requested) when the base timer value matches the G2POj register setting

(0000h to FFFFh (1)) (refer to Figure 11.12)

OUTC2_j pin function RTP output pin

Other functions • Default value setting

This function determines the starting waveform output level

• Output level inversion

This function inverts the waveform output level and outputs the inverted

signal from the OUTC2_j pin

Base timer G2RTP register Real-time port output

RTP0 OUTC2_0

OUTC2_1

OUTC2_4

OUTC2_5

OUTC2_2

OUTC2_3

OUTC2_7

OUTC2_6

G2PO7 register

G2PO6 register

G2PO5 register

G2PO4 register

G2PO3 register

G2PO2 register

G2PO1 register

G2PO0 register

RTP1

RTP2

RTP3

RTP4

RTP5

RTP6

RTP7

R01UH0211EJ0120 Rev.1.20 Page 367 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.32 Parallel RTP Output Mode Operation

(A)Free-running operation

G2RTP register

OUTC2_0 pin

FFFFh

Base timer 2 n

0000h

PO20R bit

m: G2PO0 register setting value, 0000h to FFFFh

n: G2PO1 register setting value, 0000h to FFFFh

p: G2PO2 register setting value, 0000h to FFFFh

PO20R, PO21R, and PO22R: Bits in registers IIO3IR to IIO11IR

This figure applies under the following conditions:

- The IVL bit in the G2POCRj register is 0 (output low as default value) and the IVL bit is 0 (do not invert

the output level)

- Bits RST2 to RST0 in the G2BCR1 register are 000b (base timer is not reset)

- m < n < p

X1 XCX0

PO21R bit

PO22R bit

X3 X6

OUTC2_1 pin

OUTC2_2 pin

OUTC2_3 pin

R01UH0211EJ0120 Rev.1.20 Page 368 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

23.4 Group 2 Serial Interface

Two 8-bit shift registers and waveform generation enable the serial interface function. In group 2 of the

intelligent I/O, the variable synchronous serial interface and IEBus (optional (1)) are available.

Figures 23.33 to 23.40 show associated registers.

Note:

1. Contact a Renesas Electronics sales office to use the optional features.

Figure 23.33 G2TB Register

Group 2 SI/O Transmit Buffer Register

Symbol

G2TB

Address

016Dh-016Ch

Reset Value

Undefined

RWFunctionBit Symbol Bit Name

b15 b8 b7 b0

Note:

1. Set the PC bit to 1 after setting the P bit to 0.

Data transmittedTransmit Buffer

ACK Function Select Bit RW

0: Do not add the ACK bit

1: Add the ACK bit after last transmit

bit

—

No register bits; should be written with 0 and read as undefined

value

Transmit/Receive

Character Length Select Bit

b10 b9 b8

000:8 bits

001:1 bit

010:2 bits

011:3 bits

100:4 bits

101:5 bits

110:6 bits

111:7 bits

Parity Calculation

Continuing Bit RW

0: Add the parity bit after this transmit

data

1: Carry over a parity to the data to

be transmitted (1)

Parity Select Bit RW

0: No parity

1: Parity (even parity only)

—

(b7-b0)

SZ0

SZ1

SZ2

—

(b12-b11)

R01UH0211EJ0120 Rev.1.20 Page 369 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.34 G2RB Register

Figure 23.35 G2MR Register

Group 2 SI/O Receive Buffer Register

Symbol

G2RB

Address

016Fh-016Eh

Reset Value

Undefined

RWFunctionBit Symbol Bit Name

b15 b8 b7 b0

Note:

1. The OER bit becomes 0 when bits GMD1 and GMD0 in the G2MR register are set to 00b (communication

block is reset) or the RE bit in the G2CR register is set to 0 (reception disabled).

Data receivedReceive Buffer

—

No register bits; should be written with 0 and read as undefined

value

Overrun Error Flag (1) RO

0: No overrun error

1: Overrun error

—

No register bits; should be written with 0 and read as undefined

value

—

(b7-b0)

—

(b11-b8)

OER

—

(b15-b13)

Group 2 Serial Interface Mode Register

Symbol

G2MR

Address

016Ah

Reset Value

00XX X000b

RWFunction

Bit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

—

Notes:

1. At least one base timer clock is required after setting bits GMD1 and GMD0 to 00b.

2. Set bits GMD1 and GMD0 to 01b or 10b while the base timer clock is stopped.

Internal/External Clock

Select Bit RW

Bit Order Select Bit RW

0: LSB first

1: MSB first

Serial Interface Mode

Select Bit

0: Internal clock

1: External clock

0: Transmit buffer is empty

1: Transmission is completed

Transmit Interrupt Source

Select Bit

b1 b0

0 0 : Communication block is reset

(OER bit is set to 0) (1)

0 1 : Variable synchronous serial

interface mode (2)

1 0 : IEBus mode (2)

1 1 : Do not use this combination

No register bits; should be written with 0 and read as undefined

value

GMD0

GMD1

CKDIR

—

(b5-b3)

UFORM

IRS

R01UH0211EJ0120 Rev.1.20 Page 370 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.36 G2CR Register

Group 2 Serial Interface Control Register

Symbol

G2CR

Address

016Bh

Reset Value

0000 X110b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

—

Note:

1. The group 2 base timer may be reset when these bits are rewritten. To avoid unexpected resets, set the

RST2 bit in the G2BCR1 register to 0 (base timer is not reset by a reset request from the serial interface).

Transmit Buffer Empty Flag RO

Receive Enable Bit (1) RW

0: Reception disabled

1: Reception enabled

Transmit Enable Bit

0: Data held in the G2TB register

1: No data held in the G2TB register

0: No data held in the G2RB register

1: Data held in the G2RB register

Receive Complete Flag

No register bit; should be written with 0 and read as undefined

value

0: Transmission disabled

1: Transmission enabled

0: Data in the transmit shift register

(during transmission)

1: No data in the transmit shift

Transmit Shift Register

Empty Flag

ISTXD2 Output Polarity

Switching Bit RW

0: Not inverted

1: Inverted

ISRXD2 Input Polarity

Switching Bit (1) RW

0: Not inverted

1: Inverted

TXEPT

—

(b3)

OPOL

IPOL

R01UH0211EJ0120 Rev.1.20 Page 371 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.37 IECR Register

Figure 23.38 IEAR Register

Group 2 IEBus Control Register

Symbol

IECR

Address

0172h

Reset Value

00XX X000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

—

IEBus Transmit Start

Request Bit RW

No register bits; should be written with 0 and read as undefined

value

Notes:

1. Rewrite the IEB bit while the base timer clock is stopped.

2. Wait at least one fBT2 cycle after setting the IEB bit to 0. To set this bit to 1, set bits BCK1 and BCK0 in

the G2BCR0 register to 00b (clock is stopped).

0: Transmission completed

1: Transmission started

IEBus Bus Busy Flag RO

Digital Filter Select Bit RW

0: No digital filter

1: Use the digital filter

0: IEBus disabled (2)

1: IEBus enabled

IEBus Enable Bit (1)

0: Idle state

1: Busy state (START condition

detected)

0: Mode 1

1: Mode 2

IEBus Mode Select Bit

IEB

IETS

IEBBS

—

(b5-b3)

IEM

Group 2 IEBus Address Register

Symbol

IEAR

Address

0171h-0170h

Reset Value

Undefined

RWFunction

b15 b8 b7 b0

—

Address data

No register bits; should be written with 0 and read as undefined value

R01UH0211EJ0120 Rev.1.20 Page 372 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Figure 23.39 IETIF Register

Figure 23.40 IERIF Register

Group 2 IEBus Transmit Interrupt Source Detect Register

Symbol

IETIF

Address

0173h

Reset Value

XXX0 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

—

Note:

1. This bit can be set to 0 by a program, but cannot be set to 1. To set this bit to 0, set the IEB bit in the IECR

ACK Error Flag RW

Timing Error Flag RW

Normal Completion Flag

0: No error detected

1: Error detected (1)

Arbitration Lost Flag

No register bits; should be written with 0 and read as undefined

value

0: Transmission completed in error

1: Transmission completed

successfully (1)

Maximum Transmit Byte

Error Flag

0: No error detected

1: Error detected (1)

0: No error detected

1: Error detected (1)

0: No error detected

1: Error detected (1)

IETNF

IEACK

IETMB

IETT

IEABL

—

(b7-b5)

Group 2 IEBus Receive Interrupt Source Detect Register

Symbol

IERIF

Address

0174h

Reset Value

XXX0 0000b

RWFunction

Bit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

—

Note:

1. This bit can be set to 0 by a program, but cannot be set to 1. To set this bit to 0, set the IEB bit in the IECR

Parity Error Flag RW

Timing Error Flag RW

Normal Completion Flag

0: No error detected

1: Error detected (1)

Error by Other Sources

Flag

No register bits; should be written with 0 and read as undefined

value

0: Reception completed in error

1: Reception completed successfully

(1)

Maximum Receive byte

Error Flag

0: No error detected

1: Error detected (1)

0: No error detected

1: Error detected (1)

0: No error detected

1: Error detected (1)

IERNF

IEPAR

IERMB

IERT

IERETC

—

(b7-b5)

R01UH0211EJ0120 Rev.1.20 Page 373 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

23.4.1 Variable Synchronous Serial Interface Mode for Group 2

This mode allows data transmission/reception synchronized with the transmit/receive clock. The

character length is selectable from 1 to 8 bits. Table 23.15 lists specifications of the group 2 variable

synchronous serial interface mode and Table 23.16 lists its settings. Figure 23.41 shows an operation

example of data transmission/reception.

Notes:

1. When using the serial interface, set a value greater than or equal to 1 to the G2PO0 register.

2. The highest transmit/receive clock frequency should be fBT2 divided by 20.

3. If an overrun error occurs, the G2RB register is undefined.

Table 23.15 Group 2 Variable Synchronous Serial Interface Mode Specifications

Item Specification

Data format 1- to 8-bit character length

Transmit/receive clock • The CKDIR bit in the G2MR register is 0 (internal clock selected):

n: G2PO0 register setting value, 0000h to FFFFh (1)

The bit rate is set using the G2PO0 register. The clock is generated in the

inverted waveform output mode of the channel 2 waveform generation

• The CKDIR bit is 1 (external clock selected): input into the ISCLK2 pin (2)

Transmit start conditions The conditions for starting data transmission are as follows:

• The TE bit in the G2CR register is 1 (transmission enabled)

• The TI bit in the G2CR register is 0 (data held in the G2TB register)

Receive start conditions The conditions for starting data reception are as follows:

• The RE bit in the G2CR register is 1 (reception enabled)

• The TE bit in the G2CR register is 1 (transmission enabled)

• The TI bit in the G2CR register is 0 (data held in the G2TB register)

Interrupt request In transmit interrupt, either of the following conditions is selected to set the

SIO2TR bit in the IIO6IR register to 1 (interrupt requested) (refer to Figure

11.12):

• The IRS bit in the G2MR register is 0 (transmit buffer in the G2TB register is

empty):

when data is transferred from the G2TB register to the transmit shift register

(when the transmission has started)

• The IRS bit is 1 (transmission is completed):

when data transmission from the transmit shift register is completed

In receive interrupt,

When data is transferred from the receive shift register to the G2RB register

(when the reception is completed), the SIO2PR bit in the IIO5IR register is

set to 1 (interrupt requested) (refer to Figure 11.12)

Error detection Overrun error (3)

This error occurs when the last bit of the next data has been received before

reading the G2RB register

Other functions • Bit order selection

LSB first or MSB first

• ISTXD2 and ISRXD2 I/O polarity

Output levels from the ISTXD2 pin and input levels to the ISRXD2 pin can

be inverted

• Character length for data transmission/reception

1- to 8-bit character length

fBT2

2n2+



--------------------

R01UH0211EJ0120 Rev.1.20 Page 374 of 604

Feb 18, 2013

R32C/117 Group 23. Intelligent I/O

Table 23.16 Register Settings in Group 2 Variable Synchronous Serial Interface Mode

G2BCR0 BCK1 and BCK0 Set the bits to 11b

DIV4 to DIV0 Select a divide ratio of count source

IT Set the bit to 0

G2BCR1 7 to 0 Set the bits to 0001 0010b

G2POCR0 7 to 0 Set the bits to 0000 0111b

G2POCR1 7 to 0 Set the bits to 0000 0111b

G2POCR2 7 to 0 Set the bits to 0000 0010b

G2PO0 15 to 0 Set a comparative value for waveform generation

= transmit/receive clock frequency

G2PO2 15 to 0 Set to a value smaller than that in the G2PO0 register setting

G2FE IFE2 to IFE0 Set the bits to 111b

G2MR GMD1 and GMD0 Set the bits to 01b

CKDIR Select either the internal clock or the external clock

UFORM Select either LSB first or MSB first

IRS Select a source for transmit interrupt

G2CR TE Set the bit to 1 to enable data transmission/reception

TXEPT Transmit shift register empty flag

TI Transmit buffer empty flag

RE Set the bit to 1 to enable data reception

RI Receive complete flag

OPOL Select if the output level at the ISTXD2 pin is inverted (usually set

the bit to 0)

IPOL Select if the input level at the ISRXD2 pin is inverted (usually set

the bit to 0)

G2TB 15 to 0 Set the data to be transmitted/received and its character length

G2RB 15 to 0 Store received data and error flag

fBT2

2 setting value 2+



------------------------------------------------------

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R32C/117 Group 23. Intelligent I/O

Figure 23.41 Group 2 Variable Synchronous Serial Interface Mode Transmit/Receive Operation

Received data

k+2

Base timer 2

t: channel 2 waveform generation register setting value

channel 3 waveform generation register setting value

First write to the

G2TB register

Transmit/receive clock

by the channel 2

waveform generation

The base timer is reset by the

channel 0 waveform

generation

Second write to the

G2TB register

A write to the transmit register

(8-bit data)

Transmitted to the receive

bit 2

bit 8 bit 9 bit 10 bit 11

bit 6 bit 7

bit 6 bit 7bit 2 bit 5

bit 0 bit 1

bit 1

A write to the transmit register

(4-bit data)

bit 0

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R32C/117 Group 24. Multi-master I2C-bus Interface

24. Multi-master I2C-bus Interface

The multi-master I2C-bus interface (MMI2C) is capable of serial, bi-directional data transfer in the I2C-bus

data transmit and receive format. It contains an arbitration lost detector and a clock synchronization

function. Table 24.1 lists specifications of the multi-master I2C-bus interface. Table 24.2 lists detectors of the

multi-master I2C-bus interface. Figure 24.1 shows a block diagram of the multi-master I2C-bus interface.

Table 24.1 Multi-master I2C-bus Interface Specifications

Item Specification

Data format Compliant with the I2C-bus specification

• 7-bit addressing format

• Fast-mode

• Standard-mode

Master/Slave device Selectable

I/O pins Serial data line: MSDA (SDA)

Serial clock line: MSCL (SCL)

Transmit/Receive clock 16.1 to 400 kbps (IIC = 4 MHz) IIC: I2C-bus system clock

Transmit/Receive modes Compliant with the I2C-bus specification

• Master-transmit mode

• Master-receive mode

• Slave-transmit mode

• Slave-receive mode

Interrupt request sources •Six I

2C-bus interface interrupts: Successful transmit, successful receive,

slave address match detection, general call address detection, STOP

condition detection, and timeout detection

•Two I

2C-bus line interrupts: Rising or falling edge of pins MSDA and MSCL

Other functions • Timeout detector

This function detects that the MSCL pin level is held high for longer than

the specified time while the bus is busy

• Free data format selector

This function selects the free data format to generate an interrupt request,

regardless of the slave address value, when the first byte is received

R01UH0211EJ0120 Rev.1.20 Page 377 of 604

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R32C/117 Group 24. Multi-master I2C-bus Interface

Table 24.2 Detectors of Multi-master I2C-bus Interface

Figure 24.1 Multi-master I2C-bus Interface Block Diagram

Item Specification

Slave address match

detector

In slave-receive mode, this detects whether the address sent from the

master device matches the slave address. When they match, an ACK is

automatically sent. When they do not, a NACK is automatically sent and

communication is stopped

General call address

detector

This detects a general call address when in slave-receive mode

Arbitration lost detector This detects an arbitration lost and stops MSDA output immediately when

detected

Bus busy detector This detects that the bus is busy, and sets/resets the BBSY bit

ACKD

LRB

STSPSEL

IIC

Arbitration lost

detector

Bus busy detector

Bit counter

I2C-bus interface

interrupt generator

Address comparator

I2CTRSR register

Data controller

Clock divider

Clock controller

I2C-bus line interrupt

generator

Timeout detector

CLK2

fIIC

MSDA

MSCL

SAD6 to SAD0

SAD6 to SAD0: Bits in the I2CSAR register

CKS4 to CKS0, and ACKD: Bits in the I2CCCR register

BC2 to BC0: Bits in the I2CCR0 register

STIE, RIE, SDAO, SCLO, and ICK0 and ICK1: Bits in the I2CCR1 register

TOE, TOF, TOSEL, and ICK4 to ICK2: Bits in the I2CCR2 register

LRB, AAS, AL, IRF, and BBSY: Bits in the I2CSR register

SSC4 to SSC0, SIP, SIS, and STSPSEL: Bits in the I2CSSCR register

I2CEN, and CLK2 to CLK0: Bits in the I2CMR register

STIE, RIE

SDAO

SCLO

CKS4 to CKS0

BC2 to BC0

AAS

BBSY

IRF

SSC4 to SSC0

SIS, SIP

TOSEL, TOE

TOF

1/2

f2n

CLK1 and CLK0

I2CEN

UART2 receive interrupt

UART2 transmit interrupt

Interrupt

request

Interrupt

request

I2CSAR register

1/n

00000b

00001b

00010b

00100b

01000b

01100b

10000b

ICK4 to ICK0

2.5

ICK4 to ICK0

Only set the values listed above.

fIIC: I2C-bus interface clock

IIC: I2C-bus system clock

Noise filter

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1 Multi-master I2C-bus Interface-associated Registers

24.1.1 I2C-bus Transmit/Receive Shift Register (I2CTRSR)

Figure 24.2 I2CTRSR Register

The I2CTRSR register is an 8-bit shift register where received data is stored and transmit data is written.

When transmit data is written to this register, the data is synchronized with the SCL clock and shifted out

in descending order from bit 7. Every time a bit is shifted out, the data is shifted to the left by 1 bit. During

a receive operation, the data is synchronized with the SCL clock and stored in order starting from bit 0. 1

bit of data is shifted (to the left) for every bit that is input. Figure 24.3 shows the timing when the received

data is stored to the I2CTRSR register.

The I2CTRSR register is write enabled when the ICE bit in the I2CCR0 register is 1 (I2C-bus interface

enabled). When the ICE bit is 1 and the MST bit in the I2CSR register is 1 (master mode), writing data to

the I2CTRSR register resets the bit counter and the SCL clock is output.

Write to the I2CTRSR register when a START condition is generated or the MSCL pin is low. The register

can always be read.

Figure 24.3 Received Data Storing Timing to the I2CTRSR Register

b7 Symbol

I2CTRSR

Address

044400h

Reset Value

Undefined

Function RW

I2C-bus Transmit/Receive Shift Register (1, 2, 3)

Set transmit data in transmit mode.

In receive mode, write dummy data before receiving data, and read received data

after an interrupt is generated.

The data being shifted can be read from this register, regardless of whether it is

transmitting or receiving

Notes:

1. This register is write enabled when the ICE bit in the I2CCR0 register is 1 (I2C-bus interface enabled).

2. This register is used for transmitting and receiving. Read the received data before using this register for

transmitting.

3. When data is written to this register, bits BC2 to BC0 in the I2CCR0 register become 000b, and bits

LRB, AAS, and AL in the I2CSR register become 0.

MSCL

MSDA

Internal SCL

Shift clock

(internal signal)

Internal SDA

tf ts

Data is stored to bit 0 on the rising edge of the shift clock

Data DataI2CTRSR register

tf: Noise canceller delay time (one to two cycles of IIC)

ts: Shift clock delay time (one cycle of IIC) Data is shifted 1 bit to the left.

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.2 I2C-bus Slave Address Register (I2CSAR)

Figure 24.4 I2CSAR Register

The I2CSAR register stores a slave address to automatically recognize itself as a slave device. When the

received address matches the slave address, the device operates as a slave device.

24.1.2.1 Bits SAD6 to SAD0

Bits SAD6 to SAD0 store a slave address. When the addressing format is enabled, the received 7-bit

address and the slave address set in bits SAD6 to SAD0 are compared. When a match is detected,

the device operates as a slave device.

b7 b6 b5 b4 b1b2b3 Symbol

I2CSAR

Address

044402h

Reset Value

00h

FunctionBit Symbol Bit Name RW

I2C-bus Slave Address Register

SAD0

SAD1

—

(b0) Reserved

The slave address must differ from

other slave addresses of slave

devices connected to the I2C-bus.

In slave mode, the device becomes a

slave device when the upper 7 bits

sent in the first frame after the

START condition match bits SAD6 to

SAD0

Slave Address

SAD2

SAD3

SAD4

SAD5

SAD6

Should be written with 0

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.3 I2C-bus Control Register 0 (I2CCR0)

Figure 24.5 I2CCR0 Register

The I2CCR0 register controls data communication format.

24.1.3.1 Bits BC2 to BC0

Bits BC2 to BC0 set the data bit length to be transmitted or received next. When data transmission or

reception is completed for the data length (acknowledge clock pulse is included in the number when

the ACKCLK bit in the I2CCCR register is 1) specified with bits BC2 to BC0, an I2C-bus interface

interrupt request is generated. Consequently, bits BC2 to BC0 become 000b. Note that these bits

also become 000b when a START condition is detected. Address data is transmitted or received in 8

bits regardless of their settings.

b7 b6 b5 b4 b1b2b3 Symbol

I2CCR0

Address

044403h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

I2C-bus Control Register 0

BC1

BC2

0 0

BC0

Transmit/Receive Bit

Length Setting Bit (1)

I2C-bus Interface Enable

Bit

ICE

DFS

RST RW

I2C-bus Interface Reset Bit

b2 b1 b0

000:8 bits

001:7 bits

010:6 bits

011:5 bits

100:4 bits

101:3 bits

110:2 bits

111:1 bit

—

(b7)

—

(b5)

0: I2C-bus interface disabled

1: I2C-bus interface enabled

Data Format Select Bit 0: Addressing format

1: Free data format

Reserved Should be written with 0

Writing 1 to this bit resets the I2C-bus

interface circuit

Reserved Should be written with 0

Note:

1. These bits automatically become 000b in the following cases:

- When a START or STOP condition is detected

- When data transmission is completed

- When data reception is completed

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.3.2 ICE Bit

The ICE bit enables the I2C-bus interface. Set this bit to 1 to enable the I2C-bus interface and 0 to

disable it. When this bit is 0, pins MSDA and MSCL are fixed high (these pins are high-impedance

when the corresponding NOD bits in registers P7_0S and P7_1S are 1), therefore the I2C-bus

interface cannot be used.

When the ICE bit is set to 0, the following occurs:

• Bits ADZ, AAS, AL, BBSY, TRS, and MST in the I2CSR register become 0, and the IRF bit

becomes 1.

• Writing to the I2CTRSR register is disabled.

• The I2C-bus system clock (IIC) is stopped, and the internal counter and flags are reset.

• The TOF bit in the I2CCR2 register becomes 0 (timeout not detected).

24.1.3.3 DFS Bit

The DFS bit enables the automatic recognition of a slave address. When the DFS bit is set to 0, the

addressing format is selected and the slave address is automatically recognized. In this setting, data

is received only when a general call address is received or a slave address match is detected. When

the DFS bit is set to 1, the free data format is selected. In this setting, the slave address is not

recognized, so all data are received.

24.1.3.4 RST Bit

The RST bit resets the I2C-bus interface when a communication error occurs. When the ICE bit is set

to 1 (I2C-bus interface enabled), writing 1 (reset) to the RST bit has the following effects on the I2C-

bus interface:

• Bits ADZ, AAS, AL, BBSY, TRS, and MST in the I2CSR register become 0, and the IRF bit

becomes 1.

• The TOF bit in the I2CCR2 register becomes 0 (timeout not detected).

• The internal counter and flags are reset.

When the RST bit is written with 1, the multi-master I2C-bus interface is reset within a maximum of

2.5IIC cycles. Consequently, the RST bit automatically becomes 0.

Figure 24.6 shows the timing when the I2C-bus interface is reset.

Figure 24.6 I2C-bus Interface Reset Timing

RST bit in the I2CCR0 register

I2C-bus interface reset signal

Up to 2.5 IIC cycles

1 is set by a program

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.4 I2C-bus Clock Control Register (I2CCCR)

Figure 24.7 I2CCCR Register

The I2CCCR register controls ACK and sets SCL mode and SCL clock frequency. While data is being

transmitted or received, only rewrite the ACKD bit.

24.1.4.1 Bits CKS4 to CKS0

Bits CKS4 to CKS0 set the SCL clock frequency. The SCL clock frequency varies as shown in Table

24.3, where n is a setting value of bits CKS4 to CKS0 (n = 3 to 31). Do not rewrite these bits while

data is being transmitted or received.

Notes:

1. The CKS value must be set so the SCL clock frequency is 100 kHz or less in Standard-mode or 400

kHz or less in Fast-mode. The high period of the SCL clock has a margin of error of +2 to -4 IIC in

Standard-mode, and +2 to -2 IIC in Fast-mode. Note that if the high period is shortened, the low

period is lengthened, so the frequency remains unchanged.

2. Do not set the CKS value to 0 to 2 regardless of the IIC frequency.

3. When IIC is 4 MHz or higher, do not set the CKS value to 3 or 4. The SCL clock frequency will

extend beyond the specified range.

4. The normal duty cycle of the SCL clock is 50%. When the CKS value is 5 in Fast-mode, it varies from

35% to 45%.

Table 24.3 I2CCCR Register Setting Values and SCL Frequencies

Bits CKS4 to

CKS0 Setting

Value (n)

SCL Frequency (When IIC = 4 MHz) (1)

Standard-mode Fast-mode

0 to 2 Do not set (2) Do not set (2)

3Do not set (3) 333 kHz (IIC/4n)

4Do not set (3) 250 kHz (IIC/4n)

5 100 kHz (IIC/8n) 400 kHz (IIC/2n) (4)

6 to 31 83 to 16 kHz (IIC/8n) 166 to 32 kHz (IIC/4n)

b7 b6 b5 b4 b1b2b3 Symbol

I2CCCR

Address

044404h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

I2C-bus Clock Control Register

CKS1

CKS2

CKS0

Transmit/Receive Clock

Frequency Control Bit

Clock Mode Select Bit

CKS3

CKS4

CLKMD

ACKD

ACKCLK

0: Standard-mode

1: Fast-mode

ACK Data Bit 0: ACK sent

1: NACK sent

ACK Clock Generating Bit 0: ACK clock not generated

1: ACK clock generated

The transmit/receive clock frequency

is given by IIC/8n [Hz] in Standard-

mode, or IIC/4n [Hz] in Fast-mode,

where n is a setting value.

However, when 00101b is set in

Fast-mode, the transmit/receive clock

frequency becomes IIC/2n [Hz]. Do

not set to 00000b to 00010b

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.4.2 CLKMD Bit

Set the CLKMD bit to select the SCL mode. Set this bit to 0 to select Standard-mode and 1 for Fast-

mode. To use the device under the Fast-mode I2C-bus specification (up to 400 kbit/s), set IIC to be

4 MHz or higher.

24.1.4.3 ACKD Bit

Set the ACKD bit to select the state of the MSDA pin with the ACK clock. When the ACKD bit is set to

0, the MSDA pin becomes low (acknowledged) by an ACK. When the ACKD bit is 1, the MSDA pin is

held high with the ACK clock.

Table 24.4 lists the MSDA pin state with the ACK clock.

24.1.4.4 ACKCLK Bit

Set the ACKCLK bit to select whether or not to generate an ACK handshake. When this bit is 1 (ACK

clock generated), an ACK clock pulse is generated after 1 byte of data is transmitted or received.

When this bit is 0 (ACK clock not generated), the ACK clock is not generated after 1 byte of data is

transmitted or received. In this case, the IR bit in the I2CIC register becomes 1 (I2C-bus interface

interrupt requested) on the last falling edge of the clock for data transmission or reception.

Table 24.4 MSDA Pin States with the ACK Clock

Received

Content DFS Bit ACKD Bit Slave Address MSDA Pin State

Slave

address

00Match Low (ACK)

No match High (NACK)

1 — High (NACK)

10—Low (ACK)

1 — High (NACK)

Data — 0—Low (ACK)

1 — High (NACK)

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.5 I2C-bus START and STOP Conditions Control Register (I2CSSCR)

Figure 24.8 I2CSSCR Register

The I2CSSCR register controls the detection and generation of START and STOP conditions.

24.1.5.1 Bits SSC4 to SSC0

Bits SSC4 to SSC0 select the parameters for detecting the START and STOP conditions by setting

the high period of SCL pin, set-up, and hold times. This parameter is set by referencing the I2C-bus

system clock (IIC). Therefore, it changes according to the XIN frequency and the setting of the I2C-

bus system clock select bits (i.e. bits ICK4 to ICK0 in registers I2CCR2 and I2CCR1). Do not set an

odd number or 00000b to bits SSC4 to SSC0. Detection of START and STOP conditions starts

immediately after setting the ICE bit in the I2CCR0 register to 1 (I2C-bus interface enabled). Table

24.11 lists the recommended values for bits SSC4 to SSC0.

24.1.5.2 SIP Bit

Set the SIP bit to select which of the edges of MSCL or MSDA pin generates the I2C-bus line

interrupt. Set this bit to 0 to select the falling edge, and 1 to select the rising edge.

24.1.5.3 SIS Bit

Set the SIS bit to select the input signal to be used as an I2C-bus line interrupt source. To select the

MSDA pin as an I2C-bus line interrupt source, set this bit to 0. To select the MSCL pin, set this bit to

24.1.5.4 STSPSEL Bit

Set the STSPSEL bit to select the set-up and hold times when START and STOP conditions are

generated. Set this bit to 0 to select short mode and 1 to select long mode. The STSPSEL bit must be

set to 1 (long mode) when the IIC frequency is higher than 4 MHz. Figure 24.16 shows the START

condition generation timing. Table 24.9 lists the set-up and hold times when START and STOP

conditions are generated.

I2C-bus START and STOP Conditions Control Register

Symbol

I2CSSCR

Address

044405h

Reset Value

0001 1010b

SSC3

SSC4

SIP

SIS

STSPSEL

I2C-bus line Interrupt Pin

Select Bit

0: Short mode

1: Long mode

START and STOP

Conditions Generating

Mode Select Bit

SSC0

START and STOP

Conditions Detection

Setting Bit

SSC1

SSC2

The conditions for detecting START

and STOP conditions (SCL open,

set-up, and hold times) are set with

these bits

I2C-bus line Interrupt Pin

Edge Select Bit

0: MSDA pin

1: MSCL pin

0: Falling edge

1: Rising edge

FunctionBit Symbol Bit Name RW

b6 b5 b4 b3 b2 b1 b0

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.6 I2C-bus Control Register 1 (I2CCR1)

Figure 24.9 I2CCR1 Register

The I2CCR1 register controls the I2C-bus interface.

24.1.6.1 STIE Bit

Set the STIE bit to enable an interrupt when detecting a STOP condition. When this bit is set to 1, the

I2C-bus interface interrupt is generated when detecting a STOP condition. Consequently, the STOP

bit in the I2CCR2 register becomes 1 (STOP condition detection interrupt requested) and the IR bit in

the I2CIC register becomes 1 (I2C-bus interface interrupt requested).

24.1.6.2 RIE Bit

Set the RIE bit to enable an interrupt when receiving the last bit of data when the ACKCLK bit in the

I2CCCR register is 1 (ACK clock generated). When the RIE bit is 1, the I2C-bus interface interrupt is

generated when the last bit (the eighth falling edge of the SCL) of data is received.

The I2C-bus interface interrupt is generated at the ACK bit transmission (the ninth falling edge of the

SCL) regardless of the RIE bit setting, therefore two I2C-bus interface interrupts are generated per

data when the RIE bit is 1. The source of the interrupt can be identified by reading the RIE bit. The

read value indicates the internal WAIT flag state. When the read value is 1, the last bit of data is the

interrupt source. When the read value is 0, the ACK bit is the interrupt source.

Set the RIE bit to 0 when the ACKCLK bit in the I2CCCR register is 0 (ACK clock not generated).

When the device is transmitting data or receiving a slave address, the I2C-bus interface interrupt is

generated only by the ACK bit (the ninth falling edge of the SCL) regardless of the RIE bit setting. In

both cases, the internal WAIT flag is 0.

I2C-bus Control Register 1 (1)

Symbol

I2CCR1

Address

044406h

Reset Value

0011 0000b

SDAO

ICK0

ICK1

I2C-bus System Clock

Select Bit (3)

Internal SDA Output

Monitor Bit

0: Low

1: High RO

b7 b6

0 0 : fIIC divided-by-2

0 1 : fIIC divided-by-4

1 0 : fIIC divided-by-8

1 1 : Do not use this combination

STIE STOP Condition Detection

Interrupt Enable Bit

0: Disabled

1: Enabled RW

RIE RW

Successful Receive

Interrupt Enable Bit (2)

0: Disabled

1: Enabled

FunctionBit Symbol Bit Name RW

SCLO Internal SCL Output

Monitor Bit RO

Notes:

1. Do not use a bit processing instruction with this register.

2. Set this bit to 0 when the ACKCLK bit is 0 (ACK clock is not generated).

3. These bits are enabled when bits ICK4 to ICK2 in the I2CCR2 register are 000b.

—

(b3-b2) Reserved Should be written with 0

0 0

b6 b5 b4 b3 b2 b1 b0

0: Low

1: High

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R32C/117 Group 24. Multi-master I2C-bus Interface

Figure 24.10 Interrupt Request Generation Timing in Receive Mode

Table 24.5 I2C-bus Interrupt Request Generation Timings and How to Resume Communication

I2C-bus Interface Interrupt

Generation Timing

Internal WAIT

Flag Resuming Transmission/Reception

Last bit of data (on eighth clock) 1 Write to the ACKD bit in the I2CCCR register

ACK bit (on ninth clock) 0 Write to the I2CTRSR register

(B) When the RIE bit is 1 (receive mode, ACK clock generated)

Set to 0 by an interrupt acceptance or by a program

Write 0 by a program

(A) When the RIE bit is 0 (receive mode, ACK clock generated)

ACKD bit in the

I2CCCR register

MSCL

ACK clock pulse

Set to 0 by an interrupt acceptance or by a program

MSDA

IRF bit in the

I2CSR register

Internal WAIT flag

IR bit in the

I2CIC register

Write signal to the

I2CTRSR register

8th clock 1st clock9th clock

7th bit 8th bit ACK bit 1st bit

7th clock

ACKD bit in the

I2CCCR register

MSCL

MSDA

IRF bit in the

I2CSR register

Internal WAIT flag

IR bit in the

I2CIC register

Write signal to the

I2CTRSR register

Write signal to the

I2CCCR register

ACK clock pulse

8th clock 1st clock9th clock7th clock

7th bit 8th bit 1st bit

Do not rewrite bits other than the ACKD bit when setting the I2CCCR register

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.6.3 Bits SDAO and SCLO

Bits SDAO and SCLO are read-only bits and used to monitor the logical values of the internal SDA

output signal and internal SCL output signal, respectively. Only set these bits to 0. Note that the

internal SDA and SCL output signals indicate output levels before being affected by external devices

and do not indicate MSDA and MSCL pin states.

24.1.6.4 Bits ICK1 and ICK0

Set bits ICK1 and ICK0 to select the frequency of the I2C-bus system clock (IIC). These bits are

enabled when bits ICK4 to ICK2 in the I2CCR2 register are 000b. Rewrite these bits when the ICE bit

in the I2CCR0 register is 0 (I2C-bus interface disabled). The frequency of the I2C-bus system clock

(IIC) can be selected from fIIC divided-by-2, -4, and -8 by setting these bits. fIIC divided-by-2.5, -3, -

5, and -6 are also available by setting bits ICK4 to ICK2 in the I2CCR2 register. However, bits ICK1

and ICK0 are disabled in this case.

Only set the values listed above.

Table 24.6 I2C-bus System Clock (IIC) Select Bit Settings

I2CCR2 Register I2CCR1 Register IIC

ICK4 bit ICK3 bit ICK2 bit ICK1 bit ICK0 bit

00 0

0 0 fIIC divided-by-2

0 1 fIIC divided-by-4

1 0 fIIC divided-by-8

0 0 1 0 0 fIIC divided-by-2.5

0 1 0 0 0 fIIC divided-by-3

0 1 1 0 0 fIIC divided-by-5

1 0 0 0 0 fIIC divided-by-6

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.7 I2C-bus Control Register 2 (I2CCR2)

Figure 24.11 I2CCR2 Register

The I2CCR2 register controls communication error detection. If the SCL clock stops during transmission

or reception, each device connected to the bus is halted suspending communication. To avoid this, the

multi-master I2C-bus interface supports a function to generate an I2C-bus interface interrupt when the

SCL clock is held high for a specified period of time during transmission or reception.

Figure 24.12 Timeout Detection Timing

I2C-bus Control Register 2

Symbol

I2CCR2

Address

044407h

Reset Value

0X00 0000b

ICK2

ICK3

ICK4

RWSTOP

0: I2C-bus interface interrupt not

requested

1: I2C-bus interface interrupt

requested

STOP Condition Detect

Interrupt Request Monitor

Bit

I2C-bus System Clock

Select Bit

b5b4b3

000:IIC = set by bits ICK1 and

ICK0 in the I2CCR1 register

001:

IIC = fIIC divided-by-2.5

010:

IIC = fIIC divided-by-3

011:

IIC = fIIC divided-by-5

100:

IIC = fIIC divided-by-6

Only set the values listed above

TOE Timeout Detector Enable

Bit

TOF

TOSEL

0: Timeout detector disabled

1: Timeout detector enabled

Timeout Detect Flag

Timeout Detect Period

Select Bit

0: Timeout not detected

1: Timeout detected

0: Long

1: Short

FunctionBit Symbol Bit Name RW

—

(b6) Reserved Should be written with 0

b6 b5 b4 b3 b2 b1 b0

BBSY bit in the

I2CSR register

MSCL

MSDA

TOF bit in the

I2CCR2 register

IR bit in the

I2CIC register

Timeout detection period

1st clock 2nd clock 3rd clock

1st bit 2nd bit 3rd bit

SCL clock stops

Internal counter

start signal

Internal

counter

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.7.1 TOE Bit

The TOE bit enables the timeout detector. When this bit is set to 1, the timeout detector is enabled,

and when the SCL clock is held high for a specified period of time while the BBSY bit in the I2CSR

The timeout detection period is determined by 1) the internal counter that uses IIC as a count

source, and 2) the TOSEL bit setting (selects the timeout detection period to be either long or short).

Refer to 24.1.7.3 “TOSEL bit” for details.

When a timeout is detected, set the ICE bit in the I2CCR0 register to 0 (I2C-bus interface disabled)

and initialize the I2C-bus interface.

24.1.7.2 TOF Bit

The TOF bit is a flag that indicates the state of a timeout detection. This bit is enabled when the TOE

bit is 1. When the TOF bit becomes 1 (timeout detected), the IR bit in the I2CIC register becomes 1

(I2C-bus interface interrupt requested) simultaneously.

24.1.7.3 TOSEL Bit

The TOSEL bit selects a long or short length for a timeout detection period. This bit is enabled when

the TOE bit is 1 (timeout detector enabled). Set this bit to 0 to select the long timeout period. In this

setting, the internal counter functions as a 16-bit counter. Set this bit to 1 to select the short timeout

period. In this setting, the internal counter functions as a 14-bit counter.

The internal counter increments using the I2C-bus system clock (IIC) as a count source.

Table 24.7 lists timeout detection periods.

24.1.7.4 Bits ICK4 to ICK2

Set bits ICK4 to ICK2 to select the frequency of the I2C-bus system clock (IIC). Rewrite these bits

when the ICE bit in the I2CCR0 register is 0 (I2C-bus interface disabled).

The frequency of the I2C-bus system clock (IIC) can be selected from fIIC divided-by-2.5, -3, -5, and

-6. When bits ICK4 to ICK2 are set to 000b, fIIC divided-by-2, -4, and -8 can also be selected by

setting bits ICK1 and ICK0 in the I2CCR1 register. Refer to Table 24.6.

24.1.7.5 STOP Bit

The STOP bit monitors the STOP condition detection interrupt. When the I2C-bus interface interrupt

is generated by the detection of a STOP condition, the STOP bit becomes 1. This bit is enabled when

the STIE bit in the I2CCR1 register is 1 (STOP condition detection interrupt is enabled). This bit is set

to 0 by a program. Writing 1 to this bit has no effect.

Table 24.7 Example Timeout Detection Periods

IIC Long Timeout Detection Period

(TOSEL = 0)

Short Timeout Detection Period

(TOSEL = 1)

4 MHz 16.4 ms 4.1 ms

2 MHz 32.8 ms 8.2 ms

1 MHz 65.6 ms 16.4 ms

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.8 I2C-bus Status Register (I2CSR)

Figure 24.13 I2CSR Register

The I2CSR register monitors the state of the I2C-bus interface. Write to this register only when using the

functions listed in Table 24.8, and only set the values that are listed. Note that the lower 6 bits are not

rewritten even when values from Table 24.8 are written to.

Table 24.8 I2CSR Register Settings and Functions

Values Written to the I2CSR Register Function

MST TRS BBSY IRF AL AAS ADZ LRB

X01111

Select slave-receive mode

0 1 Select slave-transmit mode

1 0 Select master-receive mode

1 1 Select master-transmit mode

00000

Select master-transmit mode and set the

device to be on STOP condition standby.

1Select master-transmit mode and set the

device to be on START condition standby.

I2C-bus Status Register

LRB Last Received Bit (1, 2) 0: Last received bit is 0

1: Last received bit is 1 RW

ADZ General Call Address

Detect Flag (1, 2)

0: General call address not detected

1: General call address detected RW

AAS Slave Address Match Flag

(1, 2)

0: Address not matched

1: Address matched RW

AL Arbitration Lost Detect Flag

(1, 2)

0: Arbitration lost not detected

1: Arbitration lost detected RW

IRF I2C-bus Interface Interrupt

Request Flag (3)

0: Requested

1: Not requested RO

BBSY Bus Busy Flag (2) 0: Bus is free

1: Bus is busy RW

TRS

MST

Transmit/Receive Switch

Bit

0: Slave mode

1: Master mode (1)

Master/Slave Select Bit

0: Receive mode

1: Transmit mode (1)

FunctionBit Symbol Bit Name RW

Notes:

1. Write 1111b to the lower 4 bits of this register to set the TRS or MST bit to 1 without generating a START or

STOP condition.

2. These bits are read-only when using them to check the status.

3. This bit is read-only. Only set this bit to 0.

b7 b6 b5 b4 b1b2b3 b0 Symbol

I2CSR

Address

044408h

Reset Value

0001 000Xb

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24.1.8.1 LRB Bit

The LRB bit stores the data of the last received bit. It is used to check whether an ACK is received.

When the ACKCLK bit in the I2CCCR register is 1 (ACK clock generated), the LRB bit becomes 0

when the ACK is received, and 1 when the ACK is not received. When the ACKCLK bit is 0 (ACK

clock not generated), the last bit of data is stored to the LRB bit. When a value is written to the

I2CTRSR register, the LRB bit becomes 0.

24.1.8.2 ADZ Bit

The ADZ bit is a flag that indicates that the general call address was received. When the DFS bit in

the I2CCR0 register is 0 (addressing format) in slave-receive mode, the ADZ bit becomes 1 when the

general call address is received.

The ADZ bit becomes 0 in any of the following cases:

• When a STOP or START condition is detected

• When the ICE bit in the I2CCR0 register is set to 0 (I2C-bus interface disabled)

• When the RST bit in the I2CCR0 register is written with 1 (I2C-bus interface reset)

24.1.8.3 AAS Bit

The AAS bit is a flag that indicates whether the received address matches its own slave address. The

AAS bit becomes 1 when the received address matches its own slave address in bits SAD6 to SAD0

in the I2CSAR register, when the DFS bit in the I2CCR0 register is 0 (addressing format) in slave-

receive mode, or when the received address is the general call address.

The AAS bit becomes 0 in any of the following cases:

• When data is written to the I2CTRSR register

• When the ICE bit in the I2CCR0 register is set to 0 (I2C-bus interface disabled)

• When the RST bit in the I2CCR0 register is written with 1 (I2C-bus interface reset)

24.1.8.4 AL Bit

The AL bit is a flag that indicates arbitration lost detection. In master transmit mode, if the MSDA pin

is changed to low by another device, then the AL bit becomes 1. Consequently, the TRS bit in the

I2CSR register becomes 0 (receive mode), and then the MST bit becomes 0 (slave mode) at the end

of the byte in which an arbitration lost is detected.

The AL bit becomes 0 in any of the following cases:

• When data is written to the I2CTRSR register

• When the ICE bit in the I2CCR0 register is set to 0 (I2C-bus interface disabled)

• When the RST bit in the I2CCR0 register is written with 1 (I2C-bus interface reset)

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24.1.8.5 IRF Bit

Set the IRF bit to generate the I2C-bus interface interrupt request signal. When the I2C-bus interface

interrupt source is generated, first the IRF bit becomes 0, then the I2C-bus interface interrupt is

generated on the falling edge of the IRF bit. Refer to Figure 24.10 for the timing.

The IRF bit becomes 0 in any of the following cases:

• When 1-byte data transmission is completed (including when an arbitration lost is detected)

• When 1-byte data reception is completed

• When the slave address is matched in addressing format in slave-receive mode

• When the general call address is received in addressing format in slave-receive mode

• When address data reception is completed in free data format in slave-receive mode

The IRF bit becomes 1 in any of the following cases:

• When data is written to the I2CTRSR register

• When data is written to the I2CCCR register (the RIE bit is 1, internal WAIT flag is 1)

• When the ICE bit in the I2CCR0 register is set to 0 (I2C-bus interface disabled)

• When the RST bit in the I2CCR0 register is written with 1 (I2C-bus interface reset)

24.1.8.6 BBSY Bit

The BBSY bit is a flag that indicates the availability of the I2C-bus. The BBSY bit becomes 1 when a

START condition is detected, and 0 when a STOP condition is detected. When the BBSY bit is 0, the

I2C-bus is not in use, and is available for the device to generate a START condition.

The detection of a START or STOP condition is dependent on the setting of bits SSC4 to SSC0 in the

I2CSSCR register.

The BBSY bit becomes 0 in any of the following cases:

• When a STOP condition is detected

• When the ICE bit in the I2CCR0 register is set to 0 (I2C-bus interface disabled)

• When the RST bit in the I2CCR0 register is written with 1 (I2C-bus interface reset)

24.1.8.7 TRS Bit

The TRS bit determines the direction of data communication. When this bit is set to 0, the device

enters receive mode and waits for data to be sent from another device. When this bit is set to 1, the

device enters transmit mode and transmits data and address to the SDA line synchronized with the

SCL clock.

The TRS bit automatically becomes 1 (transmit mode) when the received address matches its own

slave address and the received R/W bit is 1 (data requested) in addressing format in slave-receive

mode.

The TRS bit becomes 0 in any of the following cases:

• When this bit is set to 0

• When an arbitration lost is detected

• When a STOP condition is detected

• When the START condition redundancy prevention function is activated

• When a START condition is detected in slave mode

• When a NACK is received in slave mode

• When the ICE bit in the I2CCR0 register is set to 0 (I2C-bus interface disabled)

• When the RST bit in the I2CCR0 register is written with 1 (I2C-bus interface reset)

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.8.8 MST Bit

Set the MST bit to select master or slave mode. To enter slave mode, set this bit to 0. Communication

is initiated in synchronization with the SCL clock generated by the master device. Set this bit to 1 to

enter master mode. The device generates the SCL clock to initiate communication.

The MST bit becomes 0 in any of the following cases:

• When the MST bit is set to 0

• When an arbitration lost is detected, and transmission of the corresponding byte is completed

• When a STOP condition is detected

• When a START condition is detected

• When the START condition redundancy prevention function is enabled

• When the ICE bit in the I2CCR0 register is set to 0 (I2C-bus interface disabled)

• When the RST bit in the I2CCR0 register is written with 1 (I2C-bus interface reset)

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.1.9 I2C-bus Mode Register (I2CMR)

Figure 24.14 I2CMR Register

The I2CMR register selects signals for the I2C-bus interface and the clock source. Set the PRC1 bit in the

PRCR register to 1 (write enabled) before rewriting this register.

24.1.9.1 I2CEN Bit

The I2CEN bit switches between signals for UART2 and the I2C-bus interface. Set this bit to 1 to use

the following signals: MSDA, MSCL, the I2C-bus interface interrupt, and the I2C-bus line interrupt.

When this bit is set to 0, signals for UART2 are enabled.

24.1.9.2 Bits CLK2 to CLK0

Bits CLK2 to CLK0 select the clock source for the I2C-bus interface clock (fIIC). It is selected from f1

divided-by-2, f8 divided-by-2, f2n divided-by-2, f1, f8, or f2n.

The clock source selected for the I2C-bus interface (fIIC) is used as the clock source for the I2C-bus

system clock (IIC).

I2C-bus Mode Register (1)

I2CEN I2C-bus Interface/UART2

Switch Bit

0: UART2

1: I2C-bus interface RW

CLK0 RW

CLK1 RW

CLK2

I2C-bus Interface Clock

Source Select Bit

FunctionBit Symbol Bit Name RW

b7 b6 b5 b4 b1b2b3 b0 Symbol

I2CMR

Address

044410h

Reset Value

XXXX 0000b

b3 b2 b1

0 0 0 : f1 divided-by-2

0 0 1 : f8 divided-by-2

0 1 0 : f2n divided-by-2

0 1 1 : Do not use this combination

100:f1

101:f8

110:f2n

1 1 1 : Do not use this combination

Note:

1. Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting this register.

No register bits; should be written with 0 and read as undefined

value

—

(b7-b4)

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.2 Generating a START Condition

To enter a START condition standby state, write E0h to the I2CSR register while the ICE bit in the I2CCR0

standby, write a slave address to the I2CTRSR register to generate a START condition. Consequently, the

bit counter becomes 000b, 1 byte of the SCL clock is output, and the slave address is transmitted. Figure

24.15 shows how to generate a START condition.

Note that after a STOP condition is generated, writing to the I2CSR register is disabled for 1.5 cycles of

IIC after the BBSY bit becomes 0. To generate a START condition immediately after generating a STOP

condition, first write E0h to the I2CSR register, then confirm that bits TRS and MST in the I2CSR register

are 1. After that, write a slave address to the I2CTRSR register.

Figure 24.15 Generating a START Condition

The timing to generate a START condition differs between Standard-mode and Fast-mode. Figure 24.16

shows START condition generation timing. Table 24.9 lists the set-up and hold times when a START or

STOP condition is generated.

Figure 24.16 START Condition Generation Timing

Disable interrupts

Write E0h to the I2CSR register

Write a slave address to the

I2CTRSR register

Enable interrupts

Confirm the bus status

START condition standby

START condition trigger generated

Generating a START condition

End

0 (bus is free)

BBSY bit in the I2CSR register

1 (bus is busy)

Write signal to the I2CTRSR register

MSCL pin

MSDA pin

Set-up time Hold time

BBSY bit

setting time

BBSY bit in the I2CSR register Bus is free Bus is busy

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R32C/117 Group 24. Multi-master I2C-bus Interface

CLKMD: Bit in the I2CCCR register

STSPSEL: Bit in the I2CSSCR register

Number of IIC cycles in parentheses.

Table 24.9 Set-up and Hold Times When Generating a START or STOP Condition

Parameter SCL Mode Short Mode

(STSPSEL = 0)

Long Mode

(STSPSEL = 1)

Set-up time Standard-mode (CLKMD = 0) 5.0 µs (20) 13.0 µs (52)

Fast-mode (CLKMD = 1) 2.5 µs (10) 6.5 µs (26)

Hold time Standard-mode (CLKMD = 0) 5.0 µs (20) 13.0 µs (52)

Fast-mode (CLKMD = 1) 2.5 µs (10) 6.5 µs (26)

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.3 Generating a STOP Condition

To enter a STOP condition standby state, write C0h to the I2CSR register while the ICE bit in the I2CCR0

state, write dummy data to the I2CTRSR register to generate a STOP condition. Figure 24.17 shows how

to generate a STOP condition.

Figure 24.17 Generating a STOP Condition

The timing for generating a STOP condition differs between Standard-mode and Fast-mode. Figure 24.18

shows STOP condition generating timing. Table 24.9 lists the set-up and hold times when a START or

STOP condition is generated.

Figure 24.18 STOP Condition Generating Timing

Do not write the I2CSR or I2CTRSR register during the period after the standby setting until the BBSY bit

in the I2CSR register becomes 0. Doing so may cause a failure of a successful STOP condition

generation.

Furthermore, after the standby setting, the internal SCL output becomes low in the following case: after

the MSCL pin becomes high and when it becomes low before the BBSY bit becomes 0. In this case, low

output from the MSCL pin is stopped (clock line released) by generating a STOP condition, by setting the

ICE bit in the I2CCR0 register to 0 (I2C-bus interface disabled), or by setting the RST bit to 1 (I2C-bus

interface reset)

Disable interrupts

Write C0h to the I2CSR register

Write dummy data to the

I2CTRSR register

Enable interrupts

STOP condition standby

STOP condition trigger generated

Generating a STOP condition

End

Write signal to the I2CTRSR register

MSCL pin

MSDA pin

Set-up time Hold time

BBSY bit

setting time

BBSY bit in the I2CSR register Bus is freeBus is busy

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.4 START Condition Redundancy Prevention Function

A START condition is generated when the bus is free (confirmed with the BBSY bit in the I2CSR register).

However, before a START condition is generated, if a different master device generates another START

condition, the BBSY bit may become 1. In this case, the START condition redundancy prevention function

terminates the generation of its own START condition.

The START condition redundancy prevention functions as follows:

• The START condition standby setting is disabled (exits standby state)

• Writing to the I2CTRSR register is disabled (generation of the START condition trigger is disabled)

• Bits MST and TRS in the I2CSR register become 0 (enters slave-receive mode)

• The AL bit in the I2CSR register becomes 1 (arbitration lost is detected)

Figure 24.19 shows the operation of the START condition redundancy prevention function.

Figure 24.19 Example Operation of the START Condition Redundancy Prevention Function

The START condition redundancy prevention function is enabled from the falling edge of an SDA line in a

START condition until the slave address is completely received. This means, when registers I2CSR and

I2CTRSR are written during this period, then the START condition redundancy prevention function is

enabled. Figure 24.20 shows the duration.

Figure 24.20 Enabled Duration of the START Condition Redundancy Prevention Function

Example behavior of when a START condition from another device is generated while in a START condition standby state.

BBSY bit in the

I2CSR register

MSCL pin

MSDA pin

3. Another START condition generated by external

device

Bus is free

AL bit in the

I2CSR regiter

MST bit in the

I2CSR register

TRS bit in the

I2CSR register 1.5 cycles of IIC

2. START condition standby setting

1. Confirm the bus is free

2 3

4. START condition detected

The bus becomes busy at the same time the

START condition redundancy prevention function

is enabled (arbitration lost is generated).

Bus is busy

5. Enter slave-receive mode

BBSY bit in the

I2CSR register

MSCL

MSDA

1st clock

Valid duration of START condition redundancy prevention function

1st bit 2nd bit 8th bit ACK bit

2nd clock 8th clock ACK clock

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24.5 Detecting START and STOP Conditions

Figure 24.21 shows START condition detection, Figure 24.22 shows STOP condition detection, and Table

24.10 lists the parameters for detecting START and STOP conditions. The parameters to detect START

and STOP conditions are set with bits SSC4 to SSC0 in the I2CSSCR register. These parameters are

detectable only when the input signals of pins MSCL and MSDA meet all the conditions of the high period

of MSCL pin, set-up, and hold times in Table 24.10.

The BBSY bit in the I2CSR register becomes 1 when a START condition is detected, and 0 when a STOP

condition is detected. The timing for setting the BBSY bit differs between Standard-mode and Fast-mode.

Refer to Table 24.11 for BBSY bit setting time. Table 24.11 lists the recommended settings for bits SSC4

to SSC0 in Standard-mode.

Figure 24.21 Detecting a START Condition

Figure 24.22 Detecting a STOP Condition

MSCL pin

MSDA pin

BBSY bit in the I2CSR register

TRS bit in the I2CSR register

Bits BC2 to BC0 in the I2CCR0 register

High period

Set-up time Hold time

BBSY bit

setting time

(in slave mode)

000b

MSCL pin

MSDA pin

BBSY bit in the I2CSR register

TRS bit in the I2CSR register

Bits BC2 to BC0 in the I2CCR0 register

High period

Set-up time Hold time

BBSY bit

setting time

000b

0.5 cycles of IIC

MST bit in the I2CSR register

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Unit: IIC cycles

SSC value: Setting value of bits SSC4 to SSC0 in the I2CSSCR register. Do not set these bits to 0 or an

odd number.

Example times of when IIC = 4 MHz and the I2CSSCR register = 18h are in parentheses.

Number of IIC cycles in parentheses.

SSC recommended values: Decimal value of bits SSC4 to SSC0 in the I2CSSCR register.

Table 24.10 Parameters for Detecting START and STOP Conditions

Parameter Standard-mode Fast-mode

High period of MSCL pin + 1 cycle (6.25 µs) 4 cycles (1.0 µs)

Set-up time + 1 cycle < 4.0 µs (3.25 µs) 2 cycles (0.5 µs)

Hold time cycles < 4.0 µs (3.0 µs) 2 cycles (0.5 µs)

BBSY bit set/reset time + 2 cycles (3.375 µs) 3.5 cycles (0.875 µs)

Table 24.11 Recommended Values for Bits SSC4 to SSC0 in Standard-mode

IIC

SSC

Recom

mended

Value

Parameters for Detecting START and STOP Conditions

BBSY Bit Set/Reset

Time

High period of

MSCL pin Set-up time Hold time

5 MHz 30 6.2 µs (31) 3.2 µs (16) 3.0 µs (15) 4.125 µs (16.5)

4 MHz 26 6.75 µs (27) 3.5 µs (14) 3.25 µs (13) 3.625 µs (14.5)

24 6.25 µs (25) 3.25 µs (13) 3.0 µs (12) 3.375 µs (13.5)

2 MHz 12 6.5 µs (13) 3.5 µs (7) 3.0 µs (6) 3.75 µs (7.5)

10 5.5 µs (11) 3.0 µs (6) 2.5 µs (5) 3.25 µs (6.5)

1 MHz 4 5.0 µs (5) 3.0 µs (3) 2.0 µs (2) 3.5 µs (3.5)

SSC value

-------------------------

SSC value

-------------------------

SSC value - 1

---------------------------------

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24.6 Data Transmission and Reception

Examples of the data transmission and reception format for master-transmission or slave-reception in a

7-bit address format are shown in section 24.6.1 “Master Transmission” and 24.6.2 “Slave Reception”.

These examples assume communication starts after initialization using the parameters set in Table 24.12.

Table 24.12 Example of Initial Settings

Value Parameter Initial Setting

I2CSAR 02h Slave address 1

I2CCCR

85h

SCL frequency 100 kHz (IIC = 4 MHz)

Clock mode Standard-mode

ACK clock generation ACK clock generated

I2CCR2 00h Timeout Detector Disabled

I2CCR1

13h

STOP condition detection interrupt Enabled

Successful data receive interrupt Enabled

IIC fIIC divided-by-2

I2CSR 0Fh Communication mode Slave-receive mode

I2CSSCR

98h

SSC value (see Table 24.11) 24

START and STOP conditions generation

mode

Long mode

I2CCR0

08h

Number of bits to be transmitted or received 8 bits

I2C-bus interface Enabled (communication

enabled)

Data format Addressing format

I2CMR 09h I2C-bus interface/UART2 I2C-bus interface selected

I2C-bus interface clock source fIIC = f2n

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24.6.1 Master Transmission

The operation and procedures of master transmission are described in this section. Figure 24.23 shows

an example of master transmission operation. For (A) to (C) in the figure, see A to C in the descriptions

and procedures below. (1) to (3) show the program’s instructions. Arrows indicate that the procedure is

performed by the MCU automatically.

Figure 24.23 Example Operation of Master Transmission

A. Transmitting a slave address

(1) Confirm the BBSY bit in the I2CSR register is 0 (bus is free)

(2) Write E0h to the I2CSR register

 The device enters the START condition standby state

(3) Write an address of a receiver (slave address) to the upper 7 bits of the I2CTRSR register

 A START condition is generated

 The slave address is sent

B. Transmitting data (processed in the I2C-bus interrupt routine)

(1) Write transmit data to the I2CTRSR register

 Data is sent

To send multiple bytes of data, write them to the I2CTRSR register in succession

C. Completing master transmission (processed in the I2C-bus interrupt routine)

(1) Write C0h to the I2CSR register

 The device enters the STOP condition standby state

(2) Write dummy data to the I2CTRSR register

 A STOP condition is generated

In addition to the case where transmission is completed, procedure (C) is required when no ACK from the

slave device is received (when a NACK is received as shown in Figure 24.23).

MSCL pin

MSDA pin

IR bit in the

I2CIC register

S: START condition A: ACK R: Read m: Master outputs to SDA

P: STOP condition A: NACK W: Write s: Slave outputs to SDA

SSlave address

(7 bits) W A Data

(8 bits) AData

(8 bits) P

msmsm ms

(A) (B) (C)

STOP condition

(B)

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.6.2 Slave Reception

The operation and procedures of slave reception are described in this section. Figure 24.24 shows an

example of slave reception operation. For (A) to (D) in the figure, see A to D in the descriptions and

procedures below. (1) to (3) show the program’s instructions. Arrows indicate that the procedure is

performed by the MCU automatically.

Figure 24.24 Example Operation of Slave Reception

A. Receiving a slave address (performed by the MCU automatically)

 A START condition is detected

 A slave address is received

 An ACK is sent and the I2C-bus interface interrupt is generated in either of the following cases

-When the general call address is received (the ADZ bit in the I2CSR register is 1)

-When an address match is detected (the AAS bit in the I2CSR register is 1)

B. Starting slave reception (processed in the I2C-bus interrupt routine)

(1) Check the I2CSR register value. When the TRS bit is 0, start the slave reception.

(2) Write dummy data to the I2CTRSR register

 Data reception starts

C. Completing slave reception (processed in the I2C-bus interrupt routine)

(1) Read the received data from the I2CTRSR register

(2) Set the ACKD bit in the register to 1 (NACK) when the data is the last received data

(3) Set the ACKD bit in the register to 0 (ACK) when the data is not the last received data

 An ACK or NACK is sent and an I2C-bus interface interrupt is generated

D. Completing ACK transmission (processed in the I2C-bus interrupt routine)

(1) Write dummy data to the I2CTRSR register

 If the data is the last received data, a STOP condition is detected

 If not, data reception restarts

MSCL pin

MSDA pin

SSlave address

(7 bits) W A Data

(8 bits) AData

(8 bits) P

msmsm ms

IR bit in the

I2CIC register

S: START condition A: ACK R: Read m: Master outputs to SDA

P: STOP condition A: NACK W: Write s: Slave outputs to SDA

(A) (C)(B)

Slave reception completed

(D) (D)(C)

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.7 Notes on Using Multi-master I2C-bus Interface

24.7.1 Accessing Multi-master I2C-bus Interface-associated Registers

Notes on writing to and reading I2C-bus interface-associated registers.

• I2CTRSR register

Do not write to this register during data transmission or reception. Doing so resets the transmit/

receive counter and the register is unable to perform normal data transmission or reception.

• I2CCR0 register

This register becomes 000b when a START condition is detected or 1 byte of data transmission

or reception is completed. Do not write to or read this register at these two timings. Doing so may

change the register value to an unexpected value. Figures 24.26 and 24.27 show the bit counter

reset timings.

• I2CCCR register

Do not rewrite bits other than the ACKD bit during transmission or reception. Otherwise the I2C-

bus clock circuit is reset and a normal transmission or reception will not be performed as a result.

• I2CCR1 register

Rewrite bits ICK4 to ICK0 only when the ICE bit in the I2CCR0 register is 0 (I2C-bus interface

disabled). When the I2CCR1 register is read, the internal WAIT flag status is read from this

this register.

• I2CSR register

Do not use a bit processing instruction (read-modify-write instruction) since the value of each bit

in the I2CSR register changes depending on the communication state. Also, do not access this

may change the register value to an unexpected value. Figures 24.25 to 24.27 show the timing

of bits MST and TRS to change.

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R32C/117 Group 24. Multi-master I2C-bus Interface

Figure 24.25 Bit Resetting Timing (when a STOP condition is detected)

Figure 24.26 Bit Resetting Timing (when a START condition is detected)

Figure 24.27 Bit Setting/Resetting Timing (when data transmission/reception is completed)

MSCL pin

Bit reset signal

1.5 cycles of IIC

MSDA pin

BBSY bit in the

I2CSR register

Bits to be reset:

Bits MST and TRS in the I2CSR register

MSCL pin

Bit reset signal

MSDA pin

Bits to be reset:

Bits BC2 to BC0 in the I2CCR0 register

TRS bit in the I2CSR register (in slave mode)

BBSY bit in the

I2CSR register

MSCL pin

Bit reset signal

IRF bit in the

I2CSR register

Bits to be reset:

Bits BC2 to BC0 in the I2CCR0 register

MST bit in the I2CSR register (when arbitration lost is detected)

TRS bit in the I2CSR register (when a NACK is received in slave-transmit mode)

Bit reset signal

Bit to be set:

TRS bit in the I2CSR register (when the R/W bit of the first byte received is 1 in addressing format in slave-receive

mode)

two cycles of IIC

one cycle of IIC

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R32C/117 Group 24. Multi-master I2C-bus Interface

24.7.2 Generating a Repeated START condition

Use the following steps to generate a repeated START condition after transmitting 1-byte of data:

(1) Write E0h (the START condition standby state, and the MSDA pin is high) to the I2CSR register

(2) Wait until the MSDA pin becomes high

(3) Write a slave address to the I2CTRSR register to generate a START condition trigger

Figure 24.28 shows the repeated START condition generating timing.

Figure 24.28 Repeated START Condition Generating Timing

MSCL pin

MSDA pin

Write signal to the I2CSR register

(START condition standby)

Write signal to the I2CTRSR register

(START condition trigger generated)

Software wait

8th clock ACK clock

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Feb 18, 2013

R32C/117 Group 25. CAN Module

25. CAN Module

The R32C/117 Group implements one channel (CAN0) of the Controller Area Network (CAN) module that

complies with the ISO 11898-1 standard. The CAN module transmits and receives both formats of

messages, namely the standard identifier (11 bits) (identifier hereafter referred to as ID) and extended ID

(29 bits).

Tables 25.1 and 25.2 list the CAN module specifications, and Figure 25.1 shows the CAN module block

diagram.

Connect the CAN bus transceiver externally.

Table 25.1 CAN Module Specifications (1/2)

Item Specification

Protocol ISO 11898-1 compliant

Bit rate Maximum 1 Mbps

Message boxes 32 mailboxes:

Two selectable mailbox modes:

• Normal mailbox mode

All 32 mailboxes can be indivisually configured for transmission or reception

• FIFO mailbox mode:

24 mailboxes can be indivisually configured for transmission or reception.

4 of the remaining mailboxes can be configured for transmit FIFO and the other

4 mailboxes for receive FIFO

Reception • Data frames and remote frames can be received

• Selectable receiving ID format (standard ID only, extended ID only, or both IDs)

• Programmable one-shot reception function

• Selectable overwrite mode (message overwritten) or overrun mode (message

discarded)

• The reception complete interrupt can be enabled or disabled for each mailbox

Acceptance filtering 8 acceptance masks: 1 mask for every 4 mailboxes

The mask can be enabled or disabled for each mailbox

Transmission • Data frames and remote frames can be transmitted

• Selectable transmitting ID format (standard ID only, extended ID only, or both

IDs)

• Programmable one-shot transmission function

• Selectable ID priority transmit mode or mailbox number priority transmit mode

• Transmission request can be aborted (A completed abort operation can be

confirmed with a flag)

• The transmission complete interrupt can be enabled or disabled for each

mailbox

Mode transition for

bus-off recovery

Mode transition for recovering from the bus-off state can be selected:

• ISO 11898-1 compliant

• Automatic entry to CAN halt mode at bus-off entry

• Automatic entry to CAN halt mode at bus-off end

• Entry to CAN halt mode by a program

• Transition to the error-active state by a program

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R32C/117 Group 25. CAN Module

Table 25.2 CAN Module Specifications (2/2)

Item Specification

Error status monitoring • CAN bus errors (stuff error, form error, ACK error, CRC error, bit error, and ACK

delimiter error) can be monitored

• Transition to error states can be detected (error-warning, error-passive, bus-off

entry, and bus-off recovery)

• The error counters can be read

Time stamp function Time stamp function using a 16-bit counter

The reference clock can be selected among 1, 2, 4, and 8 bit times

Interrupt sources 6 types:

• Reception complete

• Transmission complete

• Receive FIFO

• Transmit FIFO

•Error

• Wake-up

CAN sleep mode Current consumption can be reduced by stopping the CAN clock

Software support units 3 software support units:

• Acceptance filter support

• Mailbox search support (receive mailbox search, transmit mailbox search, and

message lost search)

• Channel search support

CAN clock source Peripheral bus clock or main clock selectable

Test modes 3 test modes available for user evaluation:

• Listen only mode

• Self test mode 0 (external loop back)

• Self test mode 1 (internal loop back)

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R32C/117 Group 25. CAN Module

Figure 25.1 CAN Module Block Diagram

• CAN0IN/CAN0OUT: CAN I/O pins

• Protocol controller: Handles CAN protocol processing such as bus arbitration, bit timing at transmission

and reception, stuffing, error handling, etc.

• Message box: Consists of 32 mailboxes which can be individually configured as either a transmit or

receive mailbox. Each mailbox has its own ID, data length code, an 8-byte data field, and a time stamp.

• Acceptance filter: Filters received messages. Registers C0MKR0 to C0MKR7 are used for the filtering

process.

• Timer: Used for the time stamp function. The timer value when storing a message into a mailbox is

written as the time stamp value.

• Wake-up function: Generates a CAN0 wake-up interrupt request when a message is detected on the

CAN bus.

• Interrupt generator: Generates the following five types of interrupts:

- CAN0 reception complete interrupt

- CAN0 transmission complete interrupt

- CAN0 receive FIFO interrupt

- CAN0 transmit FIFO interrupt

- CAN0 error interrupt

• CAN SFRs: CAN-associated registers. Refer to 25.1 “CAN SFRs” for details.

CAN0IN/CAN0WU

CAN0 wake-up interrupt

CAN0OUT

fCANCLK

fCAN

Peripheral bus clock

Main clock

CAN0 reception complete interrupt

CAN0 transmission complete interrupt

CAN0 receive FIFO interrupt

CAN0 transmit FIFO interrupt

CAN0 error interrupt

CCLKS

BRP: Bit in the C0BCR register

CCLKS: Bit in the C0CLKR register

fCANCLK: CAN communication clock

fCAN: CAN system clock

Baud rate

prescaler (BRP)

Protocol

controller

CAN SFRs

Peripheral bus

Message box

Interrupt

generator

Acceptance filter

ID priority transmit

controller

Timer

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R32C/117 Group 25.  CAN Module
25.1 CAN SFRs
CAN-associated registers are shown in Figures 25.2 to 25.11, 25.13, 25.14, 25.16 to 25.20, 25.22, and
25.24 to 25.30.

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R32C/117 Group 25. CAN Module

25.1.1 CAN0 Control Register (C0CTLR)

Figure 25.2 C0CTLR Register

CAN0 Control Register

0 0

b7b8b15 b0 Symbol

C0CTLR

Address

47F41h-47F40h

Reset Value

0000 0000 0000 0101b

Notes:

1. When bits CANM and SLPM are changed, read the C0STR register to ensure that the mode has been

switched. Do not change bits CANM and SLPM until the mode has been switched.

2. Write to the SLPM bit in CAN reset mode or CAN halt mode. When rewriting the SLPM bit, set only this bit

to 0 or 1.

3. Write to bits BOM, MBM, IDFM, MLM, TPM, and TSPS in CAN reset mode.

4. Set the RBOC bit to 1 in bus-off state.

5. Bits RBOC and TSRC are automatically set back to 0 after being set to 1. They are read as 0.

6. Set the TSRC bit to 1 in CAN operation mode.

FunctionBit Symbol Bit Name RW

0: Mode other than CAN sleep mode

1: CAN sleep mode

CAN Sleep Mode Bit (1, 2)

CAN Operating Mode

Select Bit (1)

b1 b0

0 0 : CAN operation mode

0 1 : CAN reset mode

1 0 : CAN halt mode

1 1 : Do not use this combination

SLPM

CANM

Bus-off Recovery Mode

Select Bit (3)

BOM

b4 b3

0 0 : Normal mode

(ISO 11898-1 compliant)

0 1: Entry to CAN halt mode

automatically at bus-off entry

1 0 : Entry to CAN halt mode

automatically at bus-off end

1 1 : Entry to CAN halt mode

(during bus-off recovery period)

by a program request

0: Normal mailbox mode

1: FIFO mailbox mode

CAN Mailbox Mode

Select Bit (3)

ID Format Mode

Select Bit (3)

b10b9

0 0 : Standard ID mode

0 1 : Extended ID mode

1 0 : Mixed ID mode

1 1 : Do not use this combination

MBM

IDFM

Time Stamp Prescaler

Select Bit (3)

b15b14

0 0 : Every bit time

0 1 : Every 2-bit time

1 0 : Every 4-bit time

1 1 : Every 8-bit time

TSPS

0: Overwrite mode

1: Overrun mode

Message Lost Mode

Select Bit (3)

MLM RW

0: Not reset

1: Reset (5)

Time Stamp Counter

Reset Bit (6)

TSRC RW

0: Nothing occurred

1: Forced recovery from bus-off (5)

Forced Recovery From

Bus-off Bit (4)

RBOC RW

—

(b7-b6) Should be written with 0Reserved

Transmit Priority Mode

Select Bit (3)

TPM RW

0: ID priority transmit mode

1: Mailbox number priority transmit

mode

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R32C/117 Group 25. CAN Module

25.1.1.1 CANM Bit

Set the CANM bit to select one of the following modes for the CAN module: CAN operation mode, CAN

reset mode, or CAN halt mode. Refer to 25.2 “Operating Modes” for details.

Set the SLPM bit to 1 to select CAN sleep mode.

Do not set the CANM bit to 11b.

When the CAN module enters CAN halt mode according to the setting of the BOM bit, the CANM bit

automatically becomes 10b.

25.1.1.2 SLPM Bit

When the SLPM bit is set to 1, the CAN module enters CAN sleep mode.

When this bit is set to 0, the CAN module exits CAN sleep mode.

Refer to 25.2 “Operating Modes” for details.

25.1.1.3 BOM Bit

Set the BOM bit to select bus-off recovery mode.

When the BOM bit is 00b, the recovery from bus-off is ISO 11898-1 compliant, i.e. the CAN module

reenters CAN communication (error-active state) after detecting 11 consecutive recessive bits 128

times. A bus-off recovery interrupt request is generated when recovering from bus-off.

When the BOM bit is 01b, as soon as the CAN module enters the bus-off state, the CANM bit in the

C0CTLR register becomes 10b (CAN halt mode) and the CAN module enters CAN halt mode. No bus-

off recovery interrupt request is generated when recovering from bus-off and registers C0TECR and

C0RECR become 00h.

When the BOM bit is 10b, the CANM bit becomes 10b as soon as the CAN module enters the bus-off

state. The CAN module enters CAN halt mode after recovering from the bus-off state, i.e. after

detecting 11 consecutive recessive bits 128 times. A bus-off recovery interrupt request is generated

when recovering from bus-off and registers C0TECR and C0RECR become 00h.

When the BOM bit is 11b, the CAN module enters CAN halt mode by setting the CANM bit to 10b while

the CAN module is still in the bus-off state. No bus-off recovery interrupt request is generated when

recovering from bus-off and registers C0TECR and C0RECR become 00h. However, if the CAN

module recovers from bus-off after detecting 11 consecutive recessive bits 128 times before the CANM

bit is set to 10b, a bus-off recovery interrupt request is generated.

If the CPU requests an entry to CAN reset mode at the same time as the CAN module attempts to enter

CAN halt mode (at bus-off entry when the BOM bit is 01b, or at bus-off end

when the BOM bit is 10b),

then the CPU request to enter CAN reset mode has higher priority.

25.1.1.4 RBOC Bit

When the RBOC bit is set to 1 (forced recovery from bus-off) in the bus-off state, the CAN module

forcibly recovers from the bus-off state. This bit automatically becomes 0. The error state changes from

bus-off to error-active.

When the RBOC bit is set to 1, registers C0RECR and C0TECR become 00h and the BOST bit in the

C0STR register becomes 0 (CAN module is not in bus-off state). The other registers do not change. No

bus-off recovery interrupt request is generated by recovering from the bus-off state.

Use the RBOC bit only when the BOM bit is 00b (normal mode).

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R32C/117 Group 25. CAN Module

25.1.1.5 MBM Bit

When the MBM bit is 0 (normal mailbox mode), mailboxes [0] to [31] are configured as transmit or

receive mailboxes.

When this bit is 1 (FIFO mailbox mode), mailboxes [0] to [23] are configured as transmit or receive

mailboxes, mailboxes [24] to [27] are configured as transmit FIFO, and mailboxes [28] to [31] are as

receive FIFO.

Transmit data is written into mailbox [24] (mailbox [24] is a window mailbox for the transmit FIFO).

Receive data is read from mailbox [28] (mailbox [28] is a window mailbox for the receive FIFO).

Table 25.3 lists the mailbox configuration.

Note:

1. When the MBM bit is set to 1, note the following:

• Transmit FIFO is controlled by the C0TFCR register.

The C0MCTLj register for mailboxes [24] to [27] is disabled (j = 0 to 31).

Registers C0MCTL24 to C0MCTL27 cannot be used.

• Receive FIFO is controlled by the C0RFCR register.

The C0MCTLj register for mailboxes [28] to [31] is disabled.

Registers C0MCTL28 to C0MCTL31 cannot be used.

• Refer to the C0MIER register for the FIFO interrupts.

• The corresponding bits in the C0MKIVLR register for mailboxes [24] to [31] are disabled. Set 0 to

these bits.

• Transmit/receive FIFOs can be used for both data frames and remote frames.

25.1.1.6 IDFM Bit

Set the IDFM bit to specify the ID format.

When this bit is 00b, all mailboxes (including FIFO mailboxes) handle standard IDs only.

When this bit is 01b, all mailboxes (including FIFO mailboxes) handle extended IDs only.

When this bit is 10b, all mailboxes (including FIFO mailboxes) handle both standard IDs and extended

IDs. Standard IDs or extended IDs are specified by setting the IDE bit in the corresponding mailbox in

normal mailbox mode. In FIFO mailbox mode, the IDE bit in the corresponding mailbox is used for

mailboxes [0] to [23], the IDE bit in registers C0FIDCR0 and C0FIDCR1 is used for the receive FIFO,

and the IDE bit in mailbox [24] is used for the transmit FIFO.

Do not set 11b to the IDFM bit.

Table 25.3 Mailbox Configuration

Mailbox MBM Bit is 0

(Normal mailbox mode)

MBM Bit is 1 (1)

(FIFO mailbox mode)

Mailboxes [0] to [23] Normal mailbox Normal mailbox

Mailboxes [24] to [27] Transmit FIFO

Mailboxes [28] to [31] Receive FIFO

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R32C/117 Group 25. CAN Module

25.1.1.7 MLM Bit

Set the MLM bit to specify the operation when a new message is captured in an unread mailbox.

Overwrite mode or overrun mode can be selected. All mailboxes (including the receive FIFO) are set to

either overwrite mode or overrun mode.

When the MLM bit is 0, all mailboxes are set to overwrite mode and the new message overwrites the

old message.

When this bit is 1, all mailboxes are set to overrun mode and the new message is discarded.

25.1.1.8 TPM Bit

Set the TPM bit to specify the priority of modes when transmitting messages.

ID priority transmit mode or mailbox number priority transmit mode can be selected.

All mailboxes are set to either ID priority transmission or mailbox number priority transmission.

When the TPM bit is 0, ID priority transmit mode is selected and transmission priority complies with the

CAN bus arbitration rule, as specified in the ISO 11898-1 standard. In ID priority transmit mode,

mailboxes [0] to [31] (in normal mailbox mode), mailboxes [0] to [23] (in FIFO mailbox mode), and the

transmit FIFO are compared with the IDs of mailboxes configured for transmission. If two or more

mailbox IDs are the same, the mailbox with the smaller number has higher priority.

Only the next message to be transmitted from the transmit FIFO is included in the transmission

arbitration. If a transmit FIFO message is being transmitted, the next pending message within the

transmit FIFO is included in the transmission arbitration.

When the TPM bit is 1, mailbox number transmit mode is selected and the transmit mailbox with the

smallest mailbox number has the highest priority. In FIFO mailbox mode, the transmit FIFO has lower

priority than normal mailboxes (mailboxes [0] to [23]).

25.1.1.9 TSRC Bit

Set the TSRC bit to reset the time stamp counter.

When this bit is set to 1, the C0TSR register becomes 0000h. It automatically becomes 0.

25.1.1.10 TSPS Bit

Set the TSPS bit to select the prescaler for the time stamp.

The reference clock for the time stamp can be selected among 1, 2, 4, and 8 bit times.

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R32C/117 Group 25. CAN Module

25.1.2 CAN0 Clock Select Register (C0CLKR)

Figure 25.3 C0CLKR Register

25.1.2.1 CCLKS Bit

When the CCLKS bit is set to 0, the peripheral bus clock generated with the PLL frequency synthesizer

is used for the CAN clock source (fCAN).

When this bit is set to 1, the main clock input from the external XIN pin is used for fCAN instead of the

PLL frequency synthesizer.

b7 b6 b5 b4 b1b2b3 Symbol

C0CLKR

Address

47F47h

Reset Value

000X 0000b

FunctionBit Symbol Bit Name RW

CAN0 Clock Select Register

0: Peripheral bus clock

1: Main clock (2)

CAN Clock Source

Select Bit (1)

0 0 0 0

CCLKS

No register bit; should be written with 0 and read as 0

—

(b1)

—

(b2)

—

(b3)

Reserved

Should be written with 0

—

No register bits; should be written with 0 and read as 0

Notes:

1. Write to the CCLKS bit in CAN reset mode.

2. To set the CCLKS bit to 1, the frequency of the peripheral bus clock should be equal to or higher than

the frequency of the main clock.

—

(b6-b5)

—

(b7) Reserved Should be written with 0

—

(b4) Reserved Should be written with 0 and read as

undefined value

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R32C/117 Group 25. CAN Module

25.1.3 CAN0 Bit Configuration Register (C0BCR)

Figure 25.4 C0BCR Register

Refer to 25.3 “CAN Communication Speed Configuration” for the bit timing configuration.

Symbol

C0BCR

Address

47F46h-47F44h

Reset Value

00 0000h

FunctionBit Symbol Bit Name RW

CAN0 Bit Configuration Register (1, 2)

If the setting value is P (0 to 1023),

the baud rate prescaler divides fCAN

by P + 1

Prescaler Division Ratio

Set Bit (10 bits)

BRP RW

—

Time Segment 2 Control Bit RW

b18b17b16

0 0 0 : Do not use this combination

001:2 Tq

010:3 Tq

011:4 Tq

100:5 Tq

101:6 Tq

110:7 Tq

111:8 Tq

TSEG2

Resynchronization Jump

Width Control Bit

b21b20

00:1 Tq

01:2 Tq

10:3 Tq

11:4 Tq

SJW

b16b15 b8b23 b7 b0

Time Segment 1 Control Bit RW

b15b14b13b12

0 0 0 0 : Do not use this combination

0 0 0 1 : Do not use this combination

0 0 1 0 : Do not use this combination

0011:4 Tq

0100:5 Tq

0101:6 Tq

0110:7 Tq

0111:8 Tq

1000:9 Tq

1001:10 Tq

1010:11 Tq

1011:12 Tq

1100:13 Tq

1101:14 Tq

1110:15 Tq

1111:16 Tq

TSEG1

Notes:

1. Set the C0BCR register before entering CAN halt mode from CAN reset mode or CAN operation mode from

CAN reset mode. Once this register is set, it can be rewritten in CAN reset mode or CAN halt mode.

2. The C0BCR register consists of 24 bits. A 32-bit read/write access should be performed carefully as to not

rewrite the C0CLKR register.

—

(b10)

—

(b11)

—

(b19)

—

(b23-b22) No register bits; should be written with 0 and read as 0 —

No register bit; should be written with 0 and read as 0 —

No register bit; should be written with 0 and read as 0

Reserved Should be written with 0

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R32C/117 Group 25. CAN Module

25.1.3.1 BRP Bit

The BRP bit sets the frequency of the CAN communication clock (fCANCLK).

One fCANCLK cycle is measured as Time Quantum (Tq).

25.1.3.2 TSEG1 Bit

Set the TSEG1 bit to specify the total length of the propagation time segment (PROP_SEG) and phase

buffer segment 1 (PHASE_SEG1) with the value of Tq.

A value from 4 to 16 Tq can be set.

25.1.3.3 TSEG2 Bit

Set the TSEG2 bit to specify the length of phase buffer segment TSEG2 (PHASE_SEG2) with the value

of Tq.

A value from 2 to 8 Tq can be set.

Set the value smaller than that of the TSEG1 bit.

25.1.3.4 SJW Bit

Set the SJW bit to specify the resynchronization jump width with the value of Tq.

A value from 1 to 4 Tq can be set.

Set the value smaller than or equal to that of the TSEG2 bit.

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R32C/117 Group 25. CAN Module

25.1.4 CAN0 Mask Register k (C0MKRk) (k = 0 to 7)

Figure 25.5 Registers C0MKR0 to C0MKR7

Refer to 25.5 “Acceptance Filtering and Masking Function” for the masking function in FIFO mailbox

mode.

25.1.4.1 EID Bit

The EID bit is the filter mask bit corresponding to the CAN extended ID bit. This bit is used to receive

extended ID messages.

When the EID bit is 0, the corresponding EID bit in a received message is not compared.

When this bit is 1, the corresponding EID bit in a received message is compared.

25.1.4.2 SID Bit

The SID bit is the filter mask bit corresponding to the CAN standard ID bit. This bit is used to receive

both standard ID and extended ID messages.

When the SID bit is 0, the corresponding SID bit in a received message is not compared.

When this bit is 1, the corresponding SID bit in a received message is compared.

FunctionBit Symbol Bit Name RW

0: Corresponding EID bit is not

compared

1: Corresponding EID bit is compared

Extended ID BitEID

0: Corresponding SID bit is not

compared

1: Corresponding SID bit is compared

Standard ID BitSID RW

—

(b31-b29)

b31b28 b0b18b17

Address

47E03h-47E00h, 47E07h-47E04h

47E0Bh-47E08h, 47E0Fh-47E0Ch

47E13h-47E10h, 47E17h-47E14h

47E1Bh-47E18h, 47E1Fh-47E1Ch

CAN0 Mask Register k (k = 0 to 7) (1)

Symbol

C0MKR0, C0MKR1

C0MKR2, C0MKR3

C0MKR4, C0MKR5

C0MKR6, C0MKR7

Reset Value

Undefined

Note:

1. Write to registers C0MKR0 to C0MKR7 in CAN reset mode or CAN halt mode.

000

RWReserved Should be written with 0

R01UH0211EJ0120 Rev.1.20 Page 419 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

25.1.5 CAN0 FIFO Received ID Compare Register n

(C0FIDCR0 and C0FIDCR1) (n = 0, 1)

Figure 25.6 Registers C0FIDCR0 and C0FIDCR1

Registers C0FIDCR0 and C0FIDCR1 are enabled when the MBM bit in the C0CTLR register is set to 1

(FIFO mailbox mode). Bits EID, SID, RTR, and IDE in registers C0MB28 to C0MB31 are disabled.

Refer to 25.5 “Acceptance Filtering and Masking Function” for details on using these registers.

25.1.5.1 EID Bit

The EID bit sets the extended ID of data frames and remote frames. This bit is used to receive

extended ID messages.

25.1.5.2 SID Bit

The SID bit sets the standard ID of data frames and remote frames. This bit is used to receive both

standard ID and extended ID messages.

b31b28 b0b18b17 Address

47E23h-47E20h

47E27h-47E24h

FunctionBit Symbol Bit Name RW

CAN0 FIFO Received ID Compare Register n (n = 0, 1) (1)

0: Corresponding EID bit is 0

1: Corresponding EID bit is 1

Extended ID BitEID

0: Corresponding SID bit is 0

1: Corresponding SID bit is 1

Standard ID BitSID RW

Symbol

C0FIDCR0

C0FIDCR1

Reset Value

Undefined

RTR RW

0: Data frame

1: Remote frame

Remote Frame Request Bit

IDE RW

0: Standard ID

1: Extended ID

ID Extension Bit (2)

Notes:

1. Write to registers C0FIDCR0 and C0FIDCR1 in CAN reset mode or CAN halt mode.

2. The IDE bit is enabled when the IDFM bit in the C0CTLR register is 10b (mixed ID mode). When the IDFM

bit is either 00b (standard ID mode) or 01b (extended ID mode), the IDE bit should be written with 0.

—

(b29) RWReserved Should be written with 0

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R32C/117 Group 25. CAN Module

25.1.5.3 RTR Bit

The RTR bit sets the specified frame format of data frames or remote frames.

This bit specifies the following operations:

• When both RTR bits in registers C0FIDCR0 and C0FIDCR1 are set to 0, only data frames can be

received.

• When both RTR bits in registers C0FIDCR0 and C0FIDCR1 are set to 1, only remote frames can

be received.

• When the RTR bits in registers C0FIDCR0 and C0FIDCR1 are set with different values, both data

frames and remote frames can be received.

25.1.5.4 IDE Bit

The IDE bit sets the ID format of standard ID or extended ID.

This bit is enabled when the IDFM bit in the C0CTLR register is 10b (mixed ID mode).

When the IDFM bit is 10b, the IDE bit specifies the following operations:

• When both IDE bits in registers C0FIDCR0 and C0FIDCR1 are set to 0, only standard ID frames

can be received.

• When both IDE bits in registers C0FIDCR0 and C0FIDCR1 are set to 1, only extended ID frames

can be received.

• When the IDE bits in registers C0FIDCR0 and C0FIDCR1 are set with different values, both

standard ID and extended ID frames can be received.

R01UH0211EJ0120 Rev.1.20 Page 421 of 604

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R32C/117 Group 25. CAN Module

25.1.6 CAN0 Mask Invalid Register (C0MKIVLR)

Figure 25.7 C0MKIVLR Register

Each bit corresponds to the mailbox with the same number. When each bit is 1, the acceptance mask

for the mailbox corresponding to the bit number is disabled. In this case, a received message is stored

in the mailbox only if its ID matches bits SID and EID in the C0MBj register (j = 0 to 31).

Note:

1. Write to the C0MKIVLR register in CAN reset mode or CAN halt mode.

CAN0 Mask Invalid Register (1)

Symbol

C0MKIVLR

Address

47E2Bh-47E28h

Reset Value

Undefined

FunctionBit Name RWBit Name

b31

00000000

Bit Symbol

Reserved

—

(b23-b0) Mask Invalid Bit 0: Mask valid

1: Mask invalid RW

—

(b31-b24) Should be written with 0 RW

b0b31

FunctionBit Name RWBit Name

Bit Symbol

—

(b31-b0) Mask Invalid Bit 0: Mask valid

1: Mask invalid RW

Normal mailbox mode

FIFO mailbox mode

b24b23

R01UH0211EJ0120 Rev.1.20 Page 422 of 604

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R32C/117 Group 25. CAN Module

25.1.7 CAN0 Mailbox (C0MBj) (j = 0 to 31)

Table 25.4 lists the CAN0 mailbox memory mapping, and Table 25.5 lists the CAN data frame structure.

The reset value of the CAN0 mailbox is undefined.

j: Mailbox number (j = 0 to 31)

Table 25.4 CAN0 Mailbox Memory Mapping

Address Message Content

CAN0 Memory mapping

47C00h + j × 16 + 0 EID7 to EID0

47C00h + j × 16 + 1 EID15 to EID8

47C00h + j × 16 + 2 SID5 to SID0, EID17, EID16

47C00h + j × 16 + 3 IDE, RTR, SID10 to SID6

47C00h + j × 16 + 4 —

47C00h + j × 16 + 5 Data length code (DLC)

47C00h + j × 16 + 6 Data byte 0

47C00h + j × 16 + 7

47C00h + j × 16 + 13

Data byte 1

Data byte 7

47C00h + j × 16 + 14 Time stamp lower byte

47C00h + j × 16 + 15 Time stamp upper byte

Table 25.5 CAN Data Frame Structure

SID10 to

SID6

SID5 to

SID0

EID17 to

EID16

EID15 to

EID8

EID7 to

EID0

DLC3 to

DLC0 DATA0 DATA1 .......... DATA7

R01UH0211EJ0120 Rev.1.20 Page 423 of 604

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R32C/117 Group 25. CAN Module

Figure 25.8 C0MBj Register

CAN0 Mailbox Register j (j = 0 to 31) (1)

b15 b0

(b47) (b32)

b8b11

b31 b0

Address (2)

47C00h to 47DFFh

Symbol

C0MB0 to C0MB31

Reset Value

Undefined

b63 b0

(b111) (b48)

Setting RangeSymbol Name RW

DATA0 to

DATA7

b15 b0

(b127) (b112)

Setting RangeSymbol Name RW

TSL

TSH

Notes:

1. Write to the C0MBj register only when the associated C0MCTLj register is 00h and the corresponding mailbox

is not processing an abort request.

2. Refer to the memory mapping table for CAN0 mailbox on the previous page for detailed addresses.

3. If the mailbox has received a standard ID message, the EID bit in the mailbox is undefined.

4. The IDE bit is enabled when the IDFM bit in the C0CTLR register is 10b (mixed ID mode).

When the IDFM bit is either 00b (standard ID mod) or 01b (extended ID mode), it should be written with 0.

5. If the mailbox has received a message with n bytes less than 8 bytes, the values of DATAn to DATA7 in the

mailbox are undefined.

6. If the mailbox has received a remote frame, the previous values of DATA0 to DATA7 in the mailbox are retained.

Data Bytes 0 to 7 (5, 6) 00h to FFh

Time Stamp Lower Byte

Time Stamp Upper Byte

00h to FFh

FunctionBit Symbol Bit Name RW

0: Corresponding EID bit is 0

1: Corresponding EID bit is 1

Extended ID (3)

EID

0: Corresponding SID bit is 0

1: Corresponding SID bit is 1

Standard IDSID RW

RTR RW

0: Data frame

1: Remote frame

IDE RW

0: Standard ID

1: Extended ID

ID Extension Bit (4)

—

(b29)

Setting RangeBit Symbol Bit Name RW

—

(b7-b0)

DLC

—

(b15-b12)

RWData Length Code (5) 0h to Fh

Remote Frame Request Bit

0 0 0 0 0 0 0 0 0 0 0 0

RWReserved Should be written with 0

b17b18b28

R01UH0211EJ0120 Rev.1.20 Page 424 of 604

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R32C/117 Group 25. CAN Module

The previous value of each mailbox is retained unless a new message is received.

25.1.7.1 EID Bit

The EID bit sets the extended ID of data frames and remote frames. This bit is used to transmit or

receive extended ID messages.

25.1.7.2 SID Bit

The SID bit sets the standard ID of data frames and remote frames. This bit is used to transmit or

receive both standard ID and extended ID messages.

25.1.7.3 RTR Bit

The RTR bit sets the frame format of data frames or remote frames.

This bit specifies the following operations:

• The receive mailbox receives only frames with the format specified by the RTR bit.

• The transmit mailbox transmits according to the frame format specified by the RTR bit.

• The receive FIFO mailbox receives the data frame, remote frame, or both frames specified by the

RTR bit in registers C0FIDCR0 and C0FIDCR1.

• The transmit FIFO mailbox transmits the data frame or remote frame specified by the RTR bit in the

relevant transmitting message.

25.1.7.4 IDE Bit

The IDE bit sets the ID format of standard IDs or extended IDs.

This bit is enabled when the IDFM bit in the C0CTLR register is 10b (mixed ID mode).

When the IDFM bit is 10b, the IDE bit specifies the following operations:

• The receive mailbox receives only the ID format specified by the IDE bit.

• The transmit mailbox transmits according to the ID format specified by the IDE bit.

• The receive FIFO mailbox receives messages with the standard ID, extended ID, or both IDs

specified by the IDE bit in registers C0FIDCR0 and C0FIDCR1.

• The transmit FIFO mailbox transmits messages with the standard ID or extended ID specified by

the IDE bit in the relevant transmitting message.

R01UH0211EJ0120 Rev.1.20 Page 425 of 604

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R32C/117 Group 25. CAN Module

25.1.7.5 DLC

The DLC sets the number of data bytes to be transmitted in a data frame. When data is requested using

a remote frame, the number of data bytes to be requested is set.

When a data frame is received, the number of received data bytes is stored. When a remote frame is

received, the number of requested data bytes is stored.

Table 25.6 lists the data length corresponding to the DLC.

X: Any value

25.1.7.6 DATA0 to DATA7

DATA0 to DATA7 store the transmitted or received CAN message data. Transmission or reception

starts from DATA0. The bit order on the CAN bus is MSB first, and transmission or reception starts from

bit 7.

25.1.7.7 TSL and TSH

TSL and TSH store the counter value of the time stamp when received messages are stored in the

mailbox.

Table 25.6 Data Length Corresponding to the DLC

DLC[3] DLC[2] DLC[1] DLC[0] Data Length

0000 0 bytes

0001 1 byte

0010 2 bytes

0011 3 bytes

0100 4 bytes

0101 5 bytes

0110 6 bytes

0111 7 bytes

1XXX 8 bytes

R01UH0211EJ0120 Rev.1.20 Page 426 of 604

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R32C/117 Group 25. CAN Module

25.1.8 CAN0 Mailbox Interrupt Enable Register (C0MIER)

Figure 25.9 C0MIER Register

Interrupts can be individually enabled for each mailbox.

In normal mailbox mode (bits 0 to 31) and in FIFO mailbox mode (bits 0 to 23), each bit corresponds to

the mailbox with the same number. These bits enable or disable transmission/reception complete

interrupts for the corresponding mailboxes.

In FIFO mailbox mode, bits 24, 25, 28, and 29 specify whether transmit/receive FIFO interrupts are

enabled/disabled and timing when interrupt requests are generated.

“Buffer warning” indicates a state in which the third unread message is stored in the receive FIFO.

CAN0 Mailbox Interrupt Enable Register (1, 2)

Symbol

C0MIER

Address

47E2Fh-47E2Ch

Reset Value

Undefined

Notes:

1. Write to the C0MIER register only when the associated C0MCTLj register is 00h and the corresponding

mailbox is not processing a transmission or reception abort request (j = 0 to 31).

2. In FIFO mailbox mode, change the bits in the C0MIER register for the associated FIFO only when:

- The TFE bit in the C0TFCR register is 0 and the TFEST bit is 1, and

- The RFE bit in the C0RFCR register is 0 and the RFEST bit is 1.

3. No interrupt request is generated when the receive FIFO becomes buffer warning from full.

b0b31

FunctionBit Name RWBit NameBit Symbol

—

(b31-b0) Interrupt Enable Bit 0: Interrupt disabled

1: Interrupt enabled RW

Normal mailbox mode

FIFO mailbox mode

b0b31

00 00

FunctionBit Name RWBit NameBit Symbol

—

(b23-b0) Interrupt Enable Bit 0: Interrupt disabled

1: Interrupt enabled RW

—

(b24)

—

(b25)

Transmit FIFO Interrupt

Enable Bit

0: Interrupt disabled

1: Interrupt enabled RW

Transmit FIFO Interrupt

Generation Timing

Control Bit

Transmit FIFO interrupt request is

generated

0: Every time transmission is

completed

1: When transmit FIFO becomes

empty due to completion of

transmission

b24b23

Receive FIFO Interrupt

Enable Bit

—

(b27-b26) Reserved

—

(b28)

Should be written with 0 RW

0: Interrupt disabled

1: Interrupt enabled RW

—

(b29)

—

(b31-b30) Reserved

Receive FIFO interrupt request is

generated

0: Every time reception is completed

1: When receive FIFO becomes

buffer warning by completion of

reception (3)

Should be written with 0 RW

Receive FIFO Interrupt

Generation Timing

Control Bit

R01UH0211EJ0120 Rev.1.20 Page 427 of 604

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R32C/117 Group 25. CAN Module

25.1.9 CAN0 Message Control Register j (C0MCTLj) (j = 0 to 31)

Figure 25.10 C0MCTLj Register

Symbol

C0MCTL0 to C0MCTL31

Address

47F20h to 47F3Fh

Reset Value

00h

CAN0 Message Control Register j (j = 0 to 31) (1, 2)

NEWDATA

SENTDATA

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

INVALDATA

TRMACTIVE

MSGLOST

TRMABT

Reception Complete

Flag (3, 4)

0: No data has been received or

0 is written to the NEWDATA bit

1: A new message is being stored

or has been stored to the mailbox

When the TRMREQ bit is 0 and the RECREQ bit is 1

Reception-in-progress

Status Flag

0: Message valid

1: Message being updated

Message Lost Flag (3, 4)

0: Message is not overwritten or

overrun

1: Message is overwritten or overrun

When the TRMREQ bit is 1 and the RECREQ bit is 0

Transmission Complete

Flag (3, 4)

0: Transmission is not completed

(pending)

1: Transmission is completed

(successful)

Transmission-in-progress

Status Flag

0: Transmission is pending or

transmission is not requested

1: From acceptance of transmission

request to completion of

transmission, or error/arbitration

lost

Transmission Abort

Complete Flag (3, 4)

0: Transmission has started,

transmission abort failed because

transmission is completed, or

transmission abort is not requested

1: Transmission abort is completed

Notes:

1. Write to the C0MCTLj register in CAN operation mode or CAN halt mode.

2. Do not use registers C0MCTL24 to C0MCTL31 in FIFO mailbox mode.

3. It can only be set to 0. Writing 1 to this bit has not effect.

4. When writing 0 to bits NEWDATA, SENTDATA, MSGLOST, TRMABT, RECREQ, and TRMREQ by a program,

use the MOV instruction to ensure that only the specified bit is set to 0 and the other bits are set to 1.

5. To enter one-shot receive mode, write 1 to the ONESHOT bit at the same time as setting the RECREQ bit to 1.

To exit one-shot receive mode, write 0 to the ONESHOT bit after writing 0 to the RECREQ bit and confirming it

has been set to 0.

To enter one-shot transmit mode, write 1 to the ONESHOT bit at the same time as setting the TRMREQ bit to 1.

To exit one-shot transmit mode, write 0 to the ONESHOT bit after the message has been transmitted or aborted.

6. Do not set both the RECREQ and TRMREQ bits to 1.

7. When setting the RECREQ bit to 0, set bits MSGLOST, NEWDATA, RECREQ to 0 simultaneously.

—

(b3)

ONESHOT

—

(b5)

RECREQ

TRMREQ

—

No register bit; should be written with 0 and read as 0

One-shot Enable Bit (5)

0: One-shot reception or one-shot

transmission disabled

1: One-shot reception or one-shot

transmission enabled

No register bit; should be written with 0 and read as 0

Receive Mailbox

Set Bit (4, 6, 7)

Transmit Mailbox

Set Bit (4, 6)

0: Not configured for reception

1: Configured for reception

0: Not configured for transmission

1: Configured for transmission

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R32C/117 Group 25. CAN Module

25.1.9.1 NEWDATA Bit

The NEWDATA bit becomes 1 when a new message is being stored or has been stored to the mailbox.

The timing for setting this bit to 1 is simultaneous with the INVALDATA bit.

The NEWDATA bit is set to 0 by writing 0 by a program.

It cannot be set to 0 by a program while the related INVALDATA bit is 1.

25.1.9.2 SENTDATA Bit

The SENTDATA bit becomes 1 when data transmission from the corresponding mailbox is completed.

This bit is set to 0 by writing 0 by a program.

Set the TRMREQ bit to 0 before setting the SENTDATA bit to 0.

Bits SENTDATA and TRMREQ cannot be set to 0 simultaneously.

To transmit a new message from the corresponding mailbox, set the SENTDATA bit to 0.

25.1.9.3 INVALDATA Bit

After a message has been received, the INVALDATA bit becomes 1 while the received message is

being updated into the corresponding mailbox.

This bit becomes 0 immediately after the message has been stored. When the mailbox is read while

this bit is 1, the data is undefined.

25.1.9.4 TRMACTIVE Bit

The TRMACTIVE bit becomes 1 when the corresponding mailbox of the CAN module begins

transmitting a message.

This bit becomes 0 when the CAN module loses CAN bus arbitration, a CAN bus error occurs, or data

transmission is completed.

25.1.9.5 MSGLOST Bit

While the NEWDATA bit is 1, the MSGLOST bit becomes 1 when the mailbox is overwritten or overrun

by a newly received message. This bit becomes 1 at the end of the sixth bit of EOF.

This bit is set to 0 by writing 0 by a program.

In both overwrite and overrun modes, during five cycles of the peripheral bus clock following the sixth

bit of EOF, the MSGLOST bit does not become 0 even if it is set to 0 by a program.

25.1.9.6 TRMABT Bit

The TRMABT bit becomes 1 in the following cases:

• Following a transmission abort request, the transmission abort is completed before starting

transmission.

• Following a transmission abort request, the CAN module detects CAN bus arbitration lost or a CAN

bus error.

• In one-shot transmission mode (the RECREQ bit is 0, the TRMREQ bit is 1, and the ONESHOT bit

is 1), the CAN module detects CAN bus arbitration lost or a CAN bus error.

The TRMABT bit does not become 1 when data transmission is completed. In this case, the

SENTDATA bit becomes 1.

The TRMABT bit can be set to 0 by a program.

R01UH0211EJ0120 Rev.1.20 Page 429 of 604

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R32C/117 Group 25. CAN Module

25.1.9.7 ONESHOT Bit

The ONESHOT bit can be used in receive mode and transmit mode.

(1) One-shot Receive Mode

When the ONESHOT bit is set to 1 in receive mode (the RECREQ bit is 1 and the TRMREQ bit is

0), the mailbox receives a message only once. The mailbox does not behave as a receive mailbox

after having received a message once. The behavior of bits NEWDATA and INVALDATA is the

same as in normal reception mode. In one-shot receive mode, the MSGLOST bit does not become

To set the ONESHOT bit to 0, first write 0 to the RECREQ bit and ensure that it has been set to 0.

(2) One-shot Transmit Mode

When the ONESHOT bit is set to 1 in transmit mode (the RECREQ bit is 0 and the TRMREQ bit is

1), the CAN module transmits a message only once. The CAN module does not transmit the

message again if a CAN bus error or CAN bus arbitration lost occurs. When the transmission is

completed, the SENTDATA bit becomes 1. If the transmission cannot be completed due to a CAN

bus error or CAN bus arbitration lost, the TRMABT bit becomes 1.

Set the ONESHOT bit to 0 after the SENTDATA or TRMABT bit is set to 1.

25.1.9.8 RECREQ Bit

Set the RECREQ bit to select one of the receive modes shown in Table 25.11.

When the RECREQ bit is set to 1, the corresponding mailbox is configured to receive a data frame or a

remote frame.

When this bit is set to 0, the corresponding mailbox is not configured for reception of a data frame or a

remote frame.

Due to hardware protection, the RECREQ bit cannot be set to 0 by a program during the following period:

Hardware protection is started

• from the acceptance filter procedure (the beginning of the CRC field)

Hardware protection is released

• for the mailbox that is specified to receive the incoming message, after the received data is stored

into the mailbox or a CAN bus error occurs (i.e. a maximum period of hardware protection is from

the beginning of the CRC field to the end of the seventh bit of EOF)

• for the other mailboxes, after the acceptance filter procedure

• if no mailbox is specified to receive the message, after the acceptance filter procedure

When setting the RECREQ bit to 1, do not set 1 to the TRMREQ bit.

To change the configuration of a mailbox from transmit to receive, first abort the transmission and then

set bits SENTDATA and TRMABT to 0 before changing to receive.

25.1.9.9 TRMREQ Bit

The TRMREQ bit selects transmit modes shown in Table 25.11.

When this bit is set to 1, the corresponding mailbox is configured to transmit a data frame or a remote

frame.

When this bit is set to 0, the corresponding mailbox is not configured to transmit a data frame or a

remote frame.

If the TRMREQ bit is changed from 1 to 0 to cancel the corresponding transmission request, either the

TRMABT or SENTDATA bit is set to 1.

When setting the TRMREQ bit to 1, do not set the RECREQ bit to 1.

To change the configuration of a mailbox from receive to transmit, first abort the reception and then set

bits NEWDATA and MSGLOST to 0 before changing to transmit.

R01UH0211EJ0120 Rev.1.20 Page 430 of 604

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R32C/117 Group 25. CAN Module

25.1.10 CAN0 Receive FIFO Control Register (C0RFCR)

Figure 25.11 C0RFCR Register

b7 b6 b5 b4 b1b2b3 Symbol

C0RFCR

Address

47F48h

Reset Value

1000 0000b

Function

Bit Symbol Bit Name RW

CAN0 Receive FIFO Control Register (1)

0: Receive FIFO disabled

1: Receive FIFO enabled

Receive FIFO

Enable Bit (2)

RFE

0: No receive FIFO message lost

has occurred

1: Receive FIFO message lost

has occurred

Receive FIFO Message

Lost Flag (3)

RFMLF RW

0: Receive FIFO is not full

1: Receive FIFO is full

(4 unread messages)

Receive FIFO Full

Status Bit

RFFST RO

Receive FIFO

Unread Message Number

Status Bit

b3 b2 b1

0 0 0 : No unread messages

0 0 1 : 1 unread message

0 1 0 : 2 unread messages

0 1 1 : 3 unread messages

1 0 0 : 4 unread messages

101:Reserved

110:Reserved

111:Reserved

RFUST

0: Receive FIFO is not buffer warning

1: Receive FIFO is buffer warning

(3 unread messages)

Receive FIFO Buffer

Warning Status Bit

RFWST RO

0: Unread message in receive

FIFO

1: No unread message in receive

FIFO

Receive FIFO Empty

Status Bit

RFEST RO

Notes:

1. Write to the C0RFCR register in CAN operation mode or CAN halt mode.

2. When setting the RFE bit to 0, set the RFMLF bit to 0 as well.

3. It can only be set to 0. Writing 1 to this bit has no effect.

R01UH0211EJ0120 Rev.1.20 Page 431 of 604

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R32C/117 Group 25. CAN Module

25.1.10.1 RFE Bit

When the RFE bit is set to 1, the receive FIFO is enabled.

When this bit is set to 0, the receive FIFO is disabled for reception and becomes empty (the RFEST bit

is 1).

Do not set this bit to 1 in normal mailbox mode (the MBM bit in the C0CTLR register is 0).

Due to hardware protection, the RFE bit cannot be set to 0 by a program during the following period:

Hardware protection is started

• from the acceptance filter procedure (the beginning of the CRC field)

Hardware protection is released

• if the receive FIFO is specified to receive the incoming message, after the received data is stored

into the receive FIFO or a CAN bus error occurs (i.e. a maximum period of hardware protection is

from the beginning of the CRC field to the end of the seventh bit of EOF).

• if the receive FIFO is not specified to receive the message, after the acceptance filter procedure.

25.1.10.2 RFUST Bit

The RFUST bit indicates the number of unread messages in the receive FIFO.

The value of this bit is initialized to 000b when the RFE bit is set to 0.

25.1.10.3 RFMLF Bit

The RFMLF bit becomes 1 (receive FIFO message lost has occurred) when the receive FIFO receives

a new message and the receive FIFO is full. This bit becomes 1 at the end of the sixth bit of EOF.

The RFMLF bit is set to 0 by writing 0 by a program.

In both overwrite and overrun modes, this bit cannot be set to 0 (no receive FIFO message lost has

occurred)

by a program due to hardware protection during the five cycles of

the peripheral bus clock

following the sixth bit of

EOF, when the receive FIFO is full and determined to receive the message.

25.1.10.4 RFFST Bit

The RFFST bit becomes 1 (receive FIFO is full) when there are four unread messages in the receive

FIFO. This bit becomes 0 (receive FIFO is not full) when there are less than four unread messages in

the receive FIFO. This bit becomes 0 when the RFE bit is 0.

25.1.10.5 RFWST Bit

The RFWST bit becomes 1 (receive FIFO is buffer warning) when there are three unread messages in

the receive FIFO. This bit becomes 0 (receive FIFO is not buffer warning) when there are less than

three or equal to four unread messages in the receive FIFO. This bit becomes 0 when the RFE bit is 0.

25.1.10.6 RFEST Bit

The RFEST bit becomes 1 (no unread message in receive FIFO) when there are no unread messages

in the receive FIFO. This bit becomes 1 when the RFE bit is set to 0. The RFEST bit becomes 0

(unread message in receive FIFO) when there is one or more unread messages in the receive FIFO.

Figure 25.12 shows receive FIFO mailbox operation.

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R32C/117 Group 25. CAN Module

Figure 25.12 Receive FIFO Mailbox Operation (Bits 29 and 28 in C0MIER Register are 01b and 11b)

Frame 1

Frame 2

Frame 3

Frame 4

CAN bus

Internal bus

RFEST

RFWST

RFFST

CAN0 receive FIFO interrupt

C0RFPCR register

Receive FIFO mailbox

RFEST, RFWST, and RFFST: Bits in the C0RFCR register

Frame 1Frame 2Frame 3Frame 4

CAN0 receive FIFO interrupt

Bits 29 and 28 in the C0MIER register are 01b

Bits 29 and 28 in the C0MIER register are 11b

R01UH0211EJ0120 Rev.1.20 Page 433 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

25.1.11 CAN0 Receive FIFO Pointer Control Register (C0RFPCR)

Figure 25.13 C0RFPCR Register

When there are messages in the receive FIFO, write FFh to the C0RFPCR register by a program to

increment the CPU-side pointer for the receive FIFO to the next mailbox location.

Do not write to the C0RFPCR register when the RFE bit in the C0RFCR register is 0 (receive FIFO

disabled).

Both the CAN-side pointer and the CPU-side pointer increment when a new message is received and

the RFFST bit is 1 (receive FIFO is full) in overwrite mode. When the RFMLF bit is 1 in this condition,

the CPU-side pointer does not increment by writing to the C0RFPCR register by a program.

Function RW

b7 b0

CAN0 Receive FIFO Pointer Control Register

Symbol

C0RFPCR

Address

47F49h

Reset Value

Undefined

Setting Value

FFh

The CPU-side pointer for the receive FIFO increments by

writing FFh

R01UH0211EJ0120 Rev.1.20 Page 434 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

25.1.12 CAN0 Transmit FIFO Control Register (C0TFCR)

Figure 25.14 C0TFCR Register

25.1.12.1 TFE Bit

When the TFE bit is set to 1, the transmit FIFO is enabled.

When this bit is set to 0, the transmit FIFO becomes empty (TFEST bit is 1) and then unsent messages

from the transmit FIFO are lost as described below:

• If a message from the transmit FIFO is not scheduled for the next transmission or during

transmission.

• Following the completion of a transmission, a CAN bus error, CAN bus arbitration lost, or entry to

CAN halt mode if a message from the transmit FIFO is scheduled for the next transmission or

already during transmission.

Before setting the TFE bit to 1 again, ensure that the TFEST bit is 1.

After setting the TFE bit to 1, write transmit data to the C0MB24 register.

Do not set this bit to 1 in normal mailbox mode (MBM bit in the C0CTLR register is 0).

25.1.12.2 TFUST Bit

The TFUST bit indicates the number of unsent messages in the transmit FIFO.

After the TFE bit is set to 0, the value of the TFUST bit is initialized to 000b when transmission abort or

transmission is completed.

b7 b6 b5 b4 b1b2b3 Symbol

C0TFCR

Address

47F4Ah

Reset Value

1000 0000b

Bit Symbol Bit Name

CAN0 Transmit FIFO Control Register (1)

Transmit FIFO

Enable Bit

TFE

Transmit FIFO

Unsent Message Number

Status Bit

TFUST

Transmit FIFO Full

Status Bit

TFFST

Transmit FIFO Empty

Status Bit

TFEST

Note:

1. Write to the C0TFCR register in CAN operation mode or CAN halt mode.

Reserved

—

(b4)

—

(b5)

Function

0: Transmit FIFO disabled

1: Transmit FIFO enabled

0: Transmit FIFO is not full

1: Transmit FIFO is full

(4 unsent messages)

0: Unsent message in transmit FIFO

1: No unsent message in transmit

FIFO

Should be written with 0 and read as

undefined value

—

b3 b2 b1

0 0 0 : No unsent messages

0 0 1 : 1 unsent message

0 1 0 : 2 unsent messages

0 1 1 : 3 unsent messages

1 0 0 : 4 unsent messages

101:Reserved

110:Reserved

111:Reserved

No register bit; should be written with 0 and read as 0

R01UH0211EJ0120 Rev.1.20 Page 435 of 604

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R32C/117 Group 25. CAN Module

25.1.12.3 TFFST Bit

The TFFST bit becomes 1 (transmit FIFO is full) when there are four unsent messages in the transmit

FIFO. This bit becomes 0 (transmit FIFO is not full) when there are less than four unsent messages in

the transmit FIFO. This bit becomes 0 when a transmission from the transmit FIFO has been aborted.

25.1.12.4 TFEST Bit

The TFEST bit becomes 1 (no unsent message in transmit FIFO) when there are no unsent messages

in the transmit FIFO. This bit becomes 1 when transmission from the transmit FIFO has been aborted.

The TFEST bit becomes 0 (unsent message in transmit FIFO) when there is at least one unsent

messages in the transmit FIFO.

Figure 25.15 shows transmit FIFO mailbox operation.

Figure 25.15 Transmit FIFO Mailbox Operation (Bits 25 and 24 in C

MIER Register are 01b and 11b)

CAN0 transmit FIFO interrupt

Bits 25 and 24 in the C0MIER register are 01b

Bits 25 and 24 in the C0MIER register are 11b

Frame 1

Frame 2

Frame 3

Frame 4

CAN bus

Internal bus

TFEST

TFFST

C0TFPCR register

Transmit FIFO mailbox

Frame 1 Frame 2 Frame 3 Frame 4

TFEST and TFFST: Bits in the C0TFCR register

R01UH0211EJ0120 Rev.1.20 Page 436 of 604

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R32C/117 Group 25. CAN Module

25.1.13 CAN0 Transmit FIFO Pointer Control Register (C0TFPCR)

Figure 25.16 C0TFPCR Register

When the transmit FIFO is not full, write FFh to the C0TFPCR register by a program to increment the

CPU-side pointer for the transmit FIFO to the next mailbox location.

Do not write to the C0TFPCR register when the TFE bit in the C0TFCR register is 0 (transmit FIFO

disabled).

b7 b0

CAN0 Transmit FIFO Pointer Control Register

Symbol

C0TFPCR

Address

47F4Bh

Reset Value

Undefined

Function RW

Setting Value

FFh

The CPU-side pointer for the transmit FIFO increments by

writing FFh

R01UH0211EJ0120 Rev.1.20 Page 437 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

25.1.14 CAN0 Status Register (C0STR)

Figure 25.17 C0STR Register

Symbol

C0STR

Address

47F43h-47F42h

Reset Value

0000 0000 0000 0101b

FunctionBit Symbol Bit Name RW

CAN0 Status Register

0: Not in CAN reset mode

1: In CAN reset mode

CAN Reset Status FlagRSTST

0: Not in CAN halt mode

1: In CAN halt mode

CAN Halt Status FlagHLTST

0: Not in CAN sleep mode

1: In CAN sleep mode

CAN Sleep Status FlagSLPST

0: Not in error-passive state

1: In error-passive state

Error-passive Status FlagEPST

0: Not in bus-off state

1: In bus-off state

Bus-off Status FlagBOST

0: Bus idle or reception in progress

1: Transmission in progress or

in bus-off state

Transmit Status Flag

(transmitter)

TRMST

0: Bus idle or transmission in progress

1: Reception in progress

Receive Status Flag

(receiver)

RECST

0:No mailbox whose NEWDATA bit is

1:Mailbox whose NEWDATA bit is 1

NEWDATA Status FlagNDST

0: No mailbox whose SENTDATA bit

is 1

1: Mailbox whose SENTDATA bit is 1

SENTDATA Status FlagSDST

0: No message in receive FIFO

1: Message in receive FIFO

Receive FIFO

Status Flag

RFST

0: Transmit FIFO is full

1: Transmit FIFO is not full

Transmit FIFO

Status Flag

TFST

0: No mailbox whose MSGLOST bit

is 1

1: Mailbox whose MSGLOST bit is 1

Normal Mailbox Message

Lost Status Flag

NMLST

0: RFMLF bit is 0

1: RFMLF bit is 1

FIFO Mailbox Message

Lost Status Flag

FMLST

0: No mailbox whose TRMABT bit is

1: Mailbox whose TRMABT bit is 1

Transmission Abort

Status Flag

TABST

0: No error occurred

1: Error occurred

Error Status FlagEST

b7b8b15 b0

—

(b7) No register bit; the read value is 0 —

R01UH0211EJ0120 Rev.1.20 Page 438 of 604

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R32C/117 Group 25. CAN Module

25.1.14.1 RSTST Bit

The RSTST bit becomes 1 when the CAN module enters CAN reset mode.

This bit is 0 when the CAN module is not in CAN reset mode.

Even when the state is changed from CAN reset mode to CAN sleep mode, the RSTST bit remains 1.

25.1.14.2 HLTST Bit

The HLTST bit becomes 1 when the CAN module enters CAN halt mode.

This bit is 0 when the CAN module is not in CAN halt mode.

Even when the state is changed from CAN halt mode to CAN sleep mode, the HLTST bit remains 1.

25.1.14.3 SLPST Bit

The SLPST bit becomes 1 when the CAN module enters CAN sleep mode.

This bit is 0 when the CAN module is not in CAN sleep mode.

25.1.14.4 EPST Bit

The EPST bit becomes 1 when the value of the C0TECR or C0RECR register exceeds 127 and the

CAN module enters the error-passive state (128  TEC < 256 or 128  REC < 256). This bit is 0 when

the CAN module is not in the error-passive state.

TEC indicates the value of the transmit error counter (C0TECR register) and REC indicates the value of

the receive error counter (C0RECR register).

25.1.14.5 BOST Bit

The BOST bit becomes 1 when the value of the C0TECR register exceeds 255 and the CAN module

enters the bus-off state (TEC  256). This bit is 0 when the CAN module is not in the bus-off state.

25.1.14.6 TRMST Bit

The TRMST bit becomes 1 when the CAN module performs as a transmitter node or enters the bus-off

state.

This bit becomes 0 when the CAN module performs as a receiver node or enters the bus-idle state.

25.1.14.7 RECST Bit

The RECST bit becomes 1 when the CAN module performs as a receiver node.

This bit becomes 0 when the CAN module performs as a transmitter node or enters the bus-idle state.

25.1.14.8 NDST Bit

The NDST bit becomes 1 when at least one NEWDATA bit in the C0MCTLj register is 1 regardless of

the value of the C0MIER register (j = 0 to 31).

The NDST bit becomes 0 when all NEWDATA bits are 0.

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R32C/117 Group 25. CAN Module

25.1.14.9 SDST Bit

The SDST bit becomes 1 when at least one SENTDATA bit in the C0MCTLj register is 1 regardless of

the value of the C0MIER register (j = 0 to 31).

The SDST bit becomes 0 when all SENTDATA bits are 0.

25.1.14.10 RFST Bit

The RFST bit is 1 when there are messages in the receive FIFO.

This bit is 0 when the receive FIFO is empty.

This bit becomes 0 when normal mailbox mode is selected.

25.1.14.11 TFST Bit

The TFST bit is 1 when the transmit FIFO is not full.

This bit is 0 when the transmit FIFO is full.

This bit becomes 0 when normal mailbox mode is selected.

25.1.14.12 NMLST Bit

The NMLST bit becomes 1 when at least one MSGLOST bit in the C0MCTLj register is 1 regardless of

the value of the C0MIER register.

The NMLST bit becomes 0 when all MSGLOST bits are 0.

25.1.14.13 FMLST Bit

The FMLST bit becomes 1 when the RFMLF bit in the C0RFCR register is 1 regardless of the value of

the C0MIER register.

The FMLST bit becomes 0 when the RFMLF bit is 0.

25.1.14.14 TABST Bit

The TABST bit becomes 1 when at least one TRMABT bit in the C0MCTLj register is 1 regardless of the

value of the C0MIER register.

The TABST bit becomes 0 when all TRMABT bits are 0.

25.1.14.15 EST Bit

The EST bit becomes 1 when at least one error is detected by the C0EIFR register regardless of the

value of the C0EIER register.

This bit becomes 0 when no error is detected by the C0EIFR register.

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R32C/117 Group 25. CAN Module

25.1.15 CAN0 Mailbox Search Mode Register (C0MSMR)

Figure 25.18 C0MSMR Register

25.1.15.1 MBSM Bit

Set the MBSM bit to select the search mode for the mailbox search function.

When this bit is 00b, receive mailbox search mode is selected. In this mode, the search targets are the

NEWDATA bit in the C0MCTLj register for the normal mailbox and the RFEST bit in the C0RFCR

When the MBSM bit is 01b, transmit mailbox search mode is selected. In this mode, the search target is

the SENTDATA bit in the C0MCTLj register.

When the MBSM bit is 10b, message lost search mode is selected. In this mode, the search targets are

the MSGLOST bit in the C0MCTLj register for the normal mailbox and the RFMLF bit in the C0RFCR

When the MBSM bit is 11b, channel search mode is selected. In this mode, the search target is the

C0CSSR register.

Refer to 25.1.17 “CAN0 Channel Search Support Register (C0CSSR)”.

b7 b6 b5 b4 b1b2b3 Symbol

C0MSMR

Address

47F53h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

CAN0 Mailbox Search Mode Register (1)

Mailbox Search Mode

Select Bit

b1 b0

0 0 : Receive mailbox search mode

0 1 : Transmit mailbox search mode

1 0 : Message lost search mode

1 1 : Channel search mode

MBSM

(b15) (b8)

Note:

1. Write to the C0MSMR register in CAN operation mode or CAN halt mode.

—

(b7-b2) No register bits; should be written with 0 and read as 0 —

R01UH0211EJ0120 Rev.1.20 Page 441 of 604

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R32C/117 Group 25. CAN Module

25.1.16 CAN0 Mailbox Search Status Register (C0MSSR)

Figure 25.19 C0MSSR Register

b7 b6 b5 b4 b1b2b3 Symbol

C0MSSR

Address

47F52h

Reset Value

1000 0000b

FunctionBit Symbol Bit Name RW

CAN0 Mailbox Search Status Register

Output of search result in each search

mode

Output number: 0 to 31

Search Result Mailbox

Number Status Bit

MBNST

0: Search result found

1: No search result

Search Result Status BitSEST

—

(b6-b5) No register bits; the read value is 0 —

R01UH0211EJ0120 Rev.1.20 Page 442 of 604

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R32C/117 Group 25. CAN Module

25.1.16.1 MBNST Bit

The MBNST bit outputs the smallest mailbox number that is searched in each mode of the C0MSMR

The result searched in receive mailbox, transmit mailbox, and message lost search modes is updated

when:

• The NEWDATA, SENTDATA, or MSGLOST bit for the output mailbox is set to 0.

• The NEWDATA, SENTDATA, or MSGLOST bit for a higher-priority mailbox is set to 1.

In receive mailbox search and message lost search modes, the receive FIFO (mailbox [28]) is output

when there are messages in the receive FIFO, and there are no unread received messages or lost

messages in any of the normal mailboxes (mailboxes [0] to [23]).

In transmit mailbox search mode, the transmit FIFO (mailbox [24]) is not output.

Table 25.7 lists the operation of MBNST bit in FIFO mailbox mode.

In channel search mode, the MBNST bit outputs the corresponding channel number. After the C0MSSR

25.1.16.2 SEST Bit

The SEST bit becomes 1 when no corresponding mailbox is found after searching all mailboxes.

For example, in transmit mailbox search mode, the SEST bit becomes 1 when no SENTDATA bit for

mailboxes is 1. The SEST bit becomes 0 when at lease one SENTDATA bit is 1.

When the SEST bit is 1, the value of the MBNST bit is undefined.

Table 25.7 Operation of MBNST Bit in FIFO Mailbox Mode

MBSM Bit Mailbox [24]

(Transmit FIFO)

Mailbox [28]

(Receive FIFO)

00b

Mailbox [24] is not output Mailbox [28] is output when no NEWDATA bit for the normal

mailbox is set to 1 and there are messages in the receive

FIFO

01b Mailbox [28] is not output

10b

Mailbox [28] is output when no MSGLOST bit for the normal

mailbox is set to 1 and the RFMLF bit is set to 1 in the

receive FIFO

11b Mailbox [28] is not output

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R32C/117 Group 25. CAN Module

25.1.17 CAN0 Channel Search Support Register (C0CSSR)

Figure 25.20 C0CSSR Register

The bits in the C0CSSR register, which are set to 1, are encoded by an 8-to-3 priority encoder (the

lower bit position, the higher priority) and output to the MBNST bits in the C0MSSR register.

The value of the C0MSSR register is updated whenever the C0MSSR register is read.

Figure 25.21 shows the write and read of registers C0CSSR and C0MSSR.

Figure 25.21 Write and Read of Registers C0CSSR and C0MSSR

The value of the C0CSSR register is also updated whenever the C0MSSR register is read. When the

C0CSSR register is read, the value before the 8-to-3 priority encoder conversion is read.

Notes:

1. Write to the C0CSSR register only when the MBSM bit in the C0MSMR register is 11b (channel search

mode).

2. Write to the C0CSSR register in CAN operation mode or CAN halt mode.

CAN0 Channel Search Support Register (1, 2)

Symbol

C0CSSR

Address

47F51h

Function RW

Setting Value

Channel value

Reset Value

Undefined

b7 b0

When the value of the channel search is input, the channel

number is output to the CiMSSR register

CAN0

47F51h

47F52h

C0CSSR register

8-to-3 priority encoder

Search result: Channel no. 0 read

b7 b0

1st read

b6 b3

Search result: Channel no. 3 read

2nd read

Search result: Channel no. 6 read

3rd read

Search result: No corresponding channel no.

4th read

C0MSSR register

0 1 0 0 1 0 0 1

Address

0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 1

0 0 0 0 0 1 1 0

1 0 0

R01UH0211EJ0120 Rev.1.20 Page 444 of 604

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R32C/117 Group 25. CAN Module

25.1.18 CAN0 Acceptance Filter Support Register (C0AFSR)

Figure 25.22 C0AFSR Register

The acceptance filter support unit (ASU) can be used for data table (8 bits 256) search. In the data

table, all standard IDs created by the user are set to be enabled/disabled in bit units. When the

C0AFSR register is written with 16-bit unit data including the SID bit in the C0MBj register, in which a

received ID is stored, a decoded row (byte offset) position and column (bit) position for data table

search can be read (j = 0 to 31). The ASU can be used for standard (11-bit) IDs only.

The ASU is enabled in the following cases:

• When the ID to receive cannot be masked by the acceptance filter.

Example: IDs to receive: 078h, 087h, 111h

• When there are too many IDs to receive and software filtering time is expected to be shortened.

Figure 25.23 shows the write and read of C0AFSR register.

Figure 25.23 Write and Read of C0AFSR Register (j = 0 to 31)

b15 b0

CAN0 Acceptance Filter Support Register (1)

Symbol

C0AFSR

Address

47F57h-47F56h

Reset Value

Undefined

Function RW

Setting Value

Standard ID/

converted value

Note:

1. Write to the C0AFSR register in CAN operation mode or CAN halt mode.

After the standard ID of a received message is written,

the value converted for data table search can be read

b8 b7

b15 b8

When writing (1) SID10 SID9 SID8 SID7 SID6

3-to-8 decoder

SID5 SID4 SID3 SID2 SID1

b7 b0

Address

CAN0

47F56h

SID0

b15 b8

When reading SID10 SID9 SID8 SID7 SID6

b7 b0

47F56h

SID5 SID4 SID3

Column (bit) position in data table Row (byte offset) position in data table

Note:

1. Write the same value as the 16-bit unit data including the SID bit in the C0MBj register.

R01UH0211EJ0120 Rev.1.20 Page 445 of 604

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R32C/117 Group 25. CAN Module

25.1.19 CAN0 Error Interrupt Enable Register (C0EIER)

Figure 25.24 C0EIER Register

The C0EIER register is used to set the error interrupt enabled/disabled individually for each error

interrupt source in the C0EIFR register.

b7 b6 b5 b4 b1b2b3 Symbol

C0EIER

Address

47F4Ch

Reset Value

00h

FunctionBit Symbol Bit Name RW

CAN0 Error Interrupt Enable Register (1)

0: Bus error interrupt disabled

1: Bus error interrupt enabled

Bus Error Interrupt

Enable Bit

BEIE

0: Error warning interrupt disabled

1: Error warning interrupt enabled

Error Warning Interrupt

Enable Bit

EWIE

0: Error passive interrupt disabled

1: Error passive interrupt enabled

Error Passive Interrupt

Enable Bit

EPIE

0: Bus-off entry interrupt disabled

1: Bus-off entry interrupt enabled

Bus-off Entry Interrupt

Enable Bit

BOEIE

0: Bus-off recovery interrupt disabled

1: Bus-off recovery interrupt enabled

Bus-off Recovery Interrupt

Enable Bit

BORIE

0: Receive overrun interrupt disabled

1: Receive overrun interrupt enabled

Receive Overrun Interrupt

Enable Bit

ORIE

0: Overload frame transmit

interrupt disabled

1: Overload frame transmit

interrupt enabled

Overload Frame

Transmit Interrupt

Enable Bit

OLIE

0: Bus lock interrupt disabled

1: Bus lock interrupt enabled

Bus Lock Interrupt

Enable Bit

BLIE

Note:

1. Write to the C0EIER register in CAN reset mode.

R01UH0211EJ0120 Rev.1.20 Page 446 of 604

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R32C/117 Group 25. CAN Module

25.1.19.1 BEIE Bit

When the BEIE bit is 0, no error interrupt request is generated even if the BEIF bit in the C0EIFR

When the BEIE bit is 1, an error interrupt request is generated if the BEIF bit is set to 1.

25.1.19.2 EWIE Bit

When the EWIE bit is 0, no error interrupt request is generated even if the EWIF bit in the C0EIFR

When the EWIE bit is 1, an error interrupt request is generated if the EWIF bit is set to 1.

25.1.19.3 EPIE Bit

When the EPIE bit is 0, no error interrupt request is generated even if the EPIF bit in the C0EIFR

When the EPIE bit is 1, an error interrupt request is generated if the EPIF bit is set to 1.

25.1.19.4 BOEIE Bit

When the BOEIE bit is 0, no error interrupt request is generated even if the BOEIF bit in the C0EIFR

When the BOEIE bit is 1, an error interrupt request is generated if the BOEIF bit is set to 1.

25.1.19.5 BORIE Bit

When the BORIE bit is 0, an error interrupt request is not generated even if the BORIF bit in the

C0EIFR register is set to 1.

When the BORIE bit is 1, an error interrupt request is generated if the BORIF bit is set to 1.

25.1.19.6 ORIE Bit

When the ORIE bit is 0, no error interrupt request is generated even if the ORIF bit in the C0EIFR

When the ORIE bit is 1, an error interrupt request is generated if the ORIF bit is set to 1.

25.1.19.7 OLIE Bit

When the OLIE bit is 0, no error interrupt request is generated even if the OLIF bit in the C0EIFR

When the OLIE bit is 1, an error interrupt request is generated if the OLIF bit is set to 1.

25.1.19.8 BLIE Bit

When the BLIE bit is 0, no error interrupt request is generated even if the BLIF bit in the C0EIFR

When the BLIE bit is 1, an error interrupt request is generated if the BLIF bit is set to 1.

R01UH0211EJ0120 Rev.1.20 Page 447 of 604

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R32C/117 Group 25. CAN Module

25.1.20 CAN0 Error Interrupt Factor Judge Register (C0EIFR)

Figure 25.25 C0EIFR Register

If an event corresponding to each bit occurs, the corresponding bit in the C0EIFR register is set to 1

regardless of the setting of the C0EIER register.

To set each bit to 0, write 0 by a program. If the set timing occurs simultaneously with the clear timing by

the program, the bit becomes 1.

25.1.20.1 BEIF Bit

The BEIF bit becomes 1 when a bus error is detected.

25.1.20.2 EWIF Bit

The EWIF bit becomes 1 when the value of the receive error counter (REC) or transmit error counter

(TEC) exceeds 95.

This bit becomes 1 only when the REC or TEC initially exceeds 95. Thus, if 0 is written to the EWIF bit

by a program while the REC or TEC remains greater than 95, this bit does not become 1 until the REC

and the TEC go below 95 and then exceed 95 again.

b7 b6 b5 b4 b1b2b3 Symbol

C0EIFR

Address

47F4Dh

Reset Value

00h

FunctionBit Symbol Bit Name RW

CAN0 Error Interrupt Factor Judge Register (1)

0: No bus error detected

1: Bus error detected

Bus Error Detect FlagBEIF

0: No error warning detected

1: Error warning detected

Error Warning Detect FlagEWIF

0: No error passive detected

1: Error passive detected

Error Passive Detect FlagEPIF

0: No bus-off entry detected

1: Bus-off entry detected

Bus-off Entry Detect FlagBOEIF

0: No bus-off recovery detected

1: Bus-off recovery detected

Bus-off Recovery Detect

Flag

BORIF

0: No receive overrun detected

1: Receive overrun detected

Receive Overrun Detect

Flag

ORIF

0: No overload frame transmission

detected

1: Overload frame transmission

detected

Overload Frame

Transmission Detect Flag

OLIF

Note:

1. When writing 0 to these bits by a program, use the MOV instruction to ensure that only the specified bit is

set to 0 and the other bits are set to 1. Writing 1 to these bits has no effect.

0: No bus lock detected

1: Bus lock detected

Bus Lock Detect FlagBLIF

R01UH0211EJ0120 Rev.1.20 Page 448 of 604

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R32C/117 Group 25. CAN Module

25.1.20.3 EPIF Bit

The EPIF bit becomes 1 when the CAN error state enters the error-passive state (the REC or TEC

value exceeds 127).

This bit becomes 1 only when the REC or TEC initially exceeds 127. Thus, if 0 is written to the EPIF bit

by a program while the REC or TEC remains greater than 127, this bit does not become 1 until the REC

and the TEC go below 127 and then exceed 127 again.

25.1.20.4 BOEIF Bit

The BOEIF bit becomes 1 when the CAN error state enters the bus-off state (the TEC value exceeds

255).

This bit also becomes 1 when the BOM bit in the C0CTLR register is 01b (entry to CAN halt mode

automatically at bus-off entry) and the CAN module enters the bus-off state.

25.1.20.5 BORIF Bit

The BORIF bit becomes 1 when the CAN module recovers from the bus-off state normally by detecting

11 consecutive bits 128 times in the following conditions:

(1) When the BOM bit in the C0CTLR register is 00b

(2) When the BOM bit is 10b

(3) When the BOM bit is 11b

The BORIF bit does not become 1 if the CAN module recovers from the bus-off state in the following

conditions:

(1) When the CANM bit in the C0CTLR register is set to 01b (CAN reset mode)

(2) When the RBOC bit in the C0CTLR register is set to 1 (forced recovery from bus-off)

(3) When the BOM bit is 01b

(4) When the BOM bit is 11b and the CANM bit is set to 10b (CAN halt mode) before normal recovery

occurs

Table 25.8 lists the operation of bits BOEIF and BORIF according to BOM bit setting value.

25.1.20.6 ORIF Bit

The ORIF bit becomes 1 when a receive overrun occurs.

This bit does not become 1 in overwrite mode. In overwrite mode, a reception complete interrupt

request is generated if an overwrite condition occurs,

thus this bit does not become 1.

In normal mailbox mode, if an overrun occurs in any mailbox from [0] to [31] in overrun mode, this bit is

set to 1.

In FIFO mailbox mode, if an overrun occurs in any mailbox from [0] to [23] or the receive FIFO in

overrun mode, this bit becomes 1.

Table 25.8 Operation of Bits BOEIF and BORIF According to BOM Bit Setting Value

BOM Bit BOEIF Bit BORIF Bit

00b Becomes 1 when entering the

bus-off state

Becomes 1 when recovering from the bus-off state

01b Does not become 1

10b Becomes 1 when recovering from the bus-off state

11b Becomes 1 if normal bus-off recovery occurs before the

CANM bit is set to 10b (CAN halt mode)

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R32C/117 Group 25. CAN Module

25.1.20.7 OLIF Bit

The OLIF bit becomes 1 if the transmitting condition of an overload frame is detected when the CAN

module performs transmission or reception.

25.1.20.8 BLIF Bit

The BLIF bit becomes 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN

module is in CAN operation mode.

After the BLIF bit becomes 1, 32 consecutive dominant bits are detected again under either of the

following conditions:

• After this bit is set to 0 from 1, recessive bits are detected.

• After this bit is set to 0 from 1, the CAN module enters CAN reset mode or CAN halt mode and then

enters CAN operation mode again.

R01UH0211EJ0120 Rev.1.20 Page 450 of 604

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R32C/117 Group 25. CAN Module

25.1.21 CAN0 Receive Error Count Register (C0RECR)

Figure 25.26 C0RECR Register

The C0RECR register indicates the value of the receive error counter.

Refer to the CAN Specification (ISO 11898-1) for the increment/decrement conditions of the receive

error counter.

b7 b0

CAN0 Receive Error Count Register

Symbol

C0RECR

Address

47F4Eh

Reset Value

00h

Function RW

Counter Value

00h to FFh (1)

Note:

1. The value in the bus-off state is undefined.

Receive error count function

The C0RECR register increments or decrements the counter

value according to the error status of the CAN module during

reception

R01UH0211EJ0120 Rev.1.20 Page 451 of 604

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R32C/117 Group 25. CAN Module

25.1.22 CAN0 Transmit Error Count Register (C0TECR)

Figure 25.27 C0TECR Register

The C0TECR register indicates the value of the TEC error counter.

Refer to the CAN Specification (ISO 11898-1) for the increment/decrement conditions of the transmit

error counter.

b7 b0

CAN0 Transmit Error Count Register

Symbol

C0TECR

Address

47F4Fh

Reset Value

00h

Function RW

Counter Value

00h to FFh (1)

Note:

1. The value in the bus-off state is undefined.

Transmit error count function

The C0TECR register increments or decrements the counter

value according to the error status of the CAN module during

transmission

R01UH0211EJ0120 Rev.1.20 Page 452 of 604

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R32C/117 Group 25. CAN Module

25.1.23 CAN0 Error Code Store Register (C0ECSR)

Figure 25.28 C0ECSR Register

The C0ECSR register can be used to monitor whether an error has occurred on the CAN bus. Refer to

the CAN Specification (ISO 11898-1) to check the generation conditions of each error.

To set each bit except the EDPM bit to 0, write 0 by a program. If the timing at which each bit is set to 1

and the timing at which is written by a program are the same, the relevant bit is set to 1.

25.1.23.1 SEF Bit

The SEF bit becomes 1 when a stuff error is detected.

25.1.23.2 FEF Bit

The FEF bit becomes 1 when a form error is detected.

25.1.23.3 AEF Bit

The AEF bit becomes 1 when an ACK error is detected.

b7 b6 b5 b4 b1b2b3 Symbol

C0ECSR

Address

47F50h

Reset Value

00h

FunctionBit Symbol Bit Name RW

CAN0 Error Code Store Register

0: No stuff error detected

1: Stuff error detected

Stuff Error Flag (1, 2)

SEF

0: No form error detected

1: Form error detected

Form Error Flag (1, 2)

FEF

0: No ACK error detected

1: ACK error detected

ACK Error Flag (1, 2)

AEF

0: No CRC error detected

1: CRC error detected

CRC Error Flag (1, 2)

CEF

0: No bit error detected

1: Bit error (recessive) detected

Bit Error (recessive)

Flag (1, 2)

BE1F

0: No bit error detected

1: Bit error (dominant) detected

Bit Error (dominant)

Flag (1, 2)

BE0F

0: No ACK delimiter error detected

1: ACK delimiter error detected

ACK Delimiter Error Bit (1, 2)

ADEF

0: Output of first detected error code (4)

1: Output of accumulated error code

Error Display Mode

Select Bit (3)

EDPM

Notes:

1. Writing 1 to this bit has no effect.

2. When writing 0 to bits SEF, FEF, AEF, CEF, BE1F, BE0F, and ADEF by a program, use the MOV

instruction to ensure that only the specified bit is set to 0 and the other bits are set to 1.

3. Write to the EDPM bit in CAN reset mode or CAN halt mode.

4. If more than one error conditions are detected simultaneously, all corresponding bits are set to 1.

R01UH0211EJ0120 Rev.1.20 Page 453 of 604

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R32C/117 Group 25. CAN Module

25.1.23.4 CEF Bit

The CEF bit becomes 1 when a CRC error is detected.

25.1.23.5 BE1F Bit

The BE1F bit becomes 1 when a recessive bit error is detected.

25.1.23.6 BE0F Bit

The BE0F bit becomes 1 when a dominant bit error is detected.

25.1.23.7 ADEF Bit

The ADEF bit becomes 1 when a form error is detected with the ACK delimiter during transmission.

25.1.23.8 EDPM Bit

The EDPM bit selects the output mode of the C0ECSR register.

When this bit is set to 0, the C0ECSR register outputs the first error code.

When this bit is set to 1, the C0ECSR register outputs the accumulated error code.

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R32C/117 Group 25. CAN Module

25.1.24 CAN0 Time Stamp Register (C0TSR)

Figure 25.29 C0TSR Register

When the C0TSR register is read, the value of the time stamp counter (16-bit free-running counter) at

that moment is read.

The value of the time stamp counter reference clock is a multiple of 1 bit time, as configured by the

TSPS bit in the C0CTLR register.

The time stamp counter stops in CAN sleep mode and CAN halt mode, and is initialized in CAN reset

mode.

The time stamp counter value is stored to TSL and TSH in the C0MBj register when a received

message is stored in a receive mailbox (j = 0 to 31).

b15 b0

CAN0 Time Stamp Register (1)

Symbol

C0TSR

Address

47F55h-47F54h

Reset Value

0000h

Function RW

Counter Value

0000h to FFFFh

Note:

1. Read the C0TSR register in 16-bit units.

Free-running counter value for the time stamp function

b7b8

R01UH0211EJ0120 Rev.1.20 Page 455 of 604

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R32C/117 Group 25. CAN Module

25.1.25 CAN0 Test Control Register (C0TCR)

Figure 25.30 C0TCR Register

25.1.25.1 TSTE Bit

When the TSTE bit is set to 0, CAN test mode is disabled.

When this bit is set to 1, CAN test mode is enabled.

25.1.25.2 TSTM Bit

The TSTM bit selects the CAN test mode.

The details of each CAN test mode are described from the next page.

b7 b6 b5 b4 b1b2b3 Symbol

C0TCR

Address

47F58h

Reset Value

00h

FunctionBit Symbol Bit Name RW

CAN0 Test Control Register (1)

0: CAN test mode disabled

1: CAN test mode enabled

CAN Test Mode Enable Bit

CAN Test Mode Select Bit

b2 b1

0 0 : Other than CAN test mode

0 1 : Listen only mode

1 0 : Self test mode 0 (external loop

back)

1 1 : Self test mode 1 (internal loop

back)

00 0 0 0

TSTE

TSTM

Note:

1. Write to the C0TCR register only in CAN halt mode.

Reserved

—

(b7-b3) Should be written with 0

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R32C/117 Group 25. CAN Module

25.1.25.3 Listen Only Mode

The ISO 11898-1 recommends an optional bus monitoring mode. In listen only mode, the CAN node is

able to receive valid data frames and valid remote frames. It sends only recessive bits on the CAN bus

and the protocol controller is not required to send the ACK bit, overload flag, or active error flag.

Listen only mode can be used for baud rate detection.

Do not request transmission from any mailboxes in this mode.

Figure 25.31 shows the connection when listen only mode is selected.

Figure 25.31 Connection when Listen Only Mode is Selected

25.1.25.4 Self Test Mode 0 (External Loop Back)

Self test mode 0 is provided for CAN transceiver tests.

In this mode, the protocol controller treats its own transmitted messages as messages received via the

CAN transceiver and stores them into a receive mailbox. To be independent from external stimulation,

the protocol controller generates the ACK bit.

Connect the CAN0OUT/CAN0IN pins to the transceiver.

Figure 25.32 shows the connection when self test mode 0 is selected.

Figure 25.32 Connection when Self Test Mode 0 is Selected

CAN0OUT

internal

CAN0IN

internal

CAN0OUT CAN0IN

Recessive level

CAN0OUT

internal

CAN0IN

internal

CAN0OUT CAN0IN

CAN transceiver

ACK

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R32C/117 Group 25. CAN Module

25.1.25.5 Self Test Mode 1 (Internal Loop Back)

Self test mode 1 is provided for self test functions.

In this mode, the protocol controller treats its transmitted messages as received messages and stores

them into a receive mailbox. To be independent from external stimulation, the protocol controller

generates the ACK bit.

In self test mode 1, the protocol controller performs an internal feedback from the internal CAN0OUT

pin to the internal CAN0IN pin. The input value of the external CAN0IN pin is ignored. The external

CAN0OUT pin outputs only recessive bits. The CAN0OUT/CAN0IN pins do not need to be connected

to the CAN bus or any external device.

Figure 25.33 shows the connection when self test mode 1 is selected.

Figure 25.33 Connection when Self Test Mode 1 is Selected

CAN0OUT

internal

CAN0IN

internal

ACK

CAN0OUT CAN0IN

Recessive level

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R32C/117 Group 25. CAN Module

25.2 Operating Modes

The CAN module has the following four operating modes:

•CAN reset mode

• CAN halt mode

• CAN operation mode

• CAN sleep mode

Figure 25.34 shows the transition between CAN operating modes.

Figure 25.34 Transition between CAN Operating Modes

CPU reset

CANM, SLPM, BOM, and RBOC: Bits in the C0CTLR register

Notes:

1. The transition timing from the bus-off state to CAN halt mode depends on the setting of the BOM bit.

- When the BOM bit is 01b, the state transition timing is immediately after entering the bus-off state.

- When the BOM bit is 10b, the state transition timing is at the end of the bus-off state.

- When the BOM bit is 11b, the state transition timing is at the setting of the CANM bit to 10b (CAN halt mode).

2. Write only to the SLPM bit to exit/set CAN sleep mode.

CAN sleep mode (2) CAN reset mode CAN operation mode

CAN halt mode CAN operation mode

(bus-off state)

SLPM = 1

CANM

= 10b

CANM = 00b

SLPM = 0 when

CANM = 01b

SLPM = 0 when

CANM = 10b

When BOM bit is 00b or

11b (no halt request)

and 11 consecutive

recessive bits are

detected 128 times or

RBOC bit is 1.

CANM

= 01b

CANM

= 10b

TEC > 255

CANM = 10b (1)

CANM

= 00b

CANM

= 01b

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R32C/117 Group 25. CAN Module

25.2.1 CAN Reset Mode

CAN reset mode is provided for CAN communication configuration.

When the CANM bit in the C0CTLR register is set to 01b, the CAN module enters CAN reset. Then the

RSTST bit in the C0STR register becomes 1. Do not change the CANM bit until the RSTST bit

becomes 1.

Configure the C0BCR register before exiting CAN reset mode and entering any other mode.

The following registers are initialized to their reset values after entering CAN reset mode and their

initialized values are retained during CAN reset mode:

• C0MCTLj register (j = 0 to 31)

• C0STR register (except bits SLPST and TFST)

• C0EIFR register

• C0RECR register

• C0TECR register

• C0TSR register

• C0MSSR register

• C0MSMR register

• C0RFCR register

• C0TFCR register

• C0TCR register

• C0ECSR register (except EDPM bit)

The previous values of the following registers are retained after entering CAN reset mode:

• C0CLKR register

• C0CTLR register

• C0STR register (bits SLPST and TFST)

• C0MIER register

• C0EIER register

• C0BCR register

• C0CSSR register

• C0ECSR register (EDPM bit only)

• C0MBj register

• Registers C0MKR0 to C0MKR7

• Registers C0FIDCR0 and C0FIDCR1

• C0MKIVLR register

• C0AFSR register

• C0RFPCR register

• C0TFPCR register

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R32C/117 Group 25. CAN Module

25.2.2 CAN Halt Mode

CAN halt mode is used for mailbox configuration and test mode setting.

When the CANM bit in the C0CTLR register is set to 10b, CAN halt mode is selected. Then the HLTST

bit in the C0STR register becomes 1. Do not change the CANM bit until the HLTST bit becomes 1.

Refer to Table 25.9 “Operation in CAN Reset Mode and CAN Halt Mode” regarding the state transition

conditions when transmitting or receiving.

All registers except bits RSTST, HLTST, and SLPST in the C0STR register remain unchanged when the

CAN module enters CAN halt mode.

Do not change registers

CLKR,

CTLR (except bits CANM and SLPM),

and C0EIER in CAN halt

mode. The C0BCR register can be changed in CAN halt mode only when listen only mode is selected

to use with automatic bit rate detection.

BOM bit: Bit in the C0CTLR register

Notes:

1. If several messages are requested to be transmitted, mode transition occurs after the completion of

the first message transmission. When CAN reset mode is being requested during suspend

transmission, mode transition occurs when the bus is idle, the next transmission ends, or the CAN

module becomes a receiver.

2. If the CAN bus is locked at the dominant level, the program can detect this state by monitoring the

BLIF bit in the C0EIFR register.

3. If a CAN bus error occurs during reception after CAN halt mode is requested, the CAN mode transits

to CAN halt mode.

4. If a CAN bus error or arbitration lost occurs during transmission after CAN reset mode or CAN halt

mode is requested, the CAN mode transits to the requested CAN mode.

Table 25.9 Operation in CAN Reset Mode and CAN Halt Mode

Mode Receiver Transmitter Bus-off

CAN reset

mode

CAN module enters CAN reset

mode without waiting for the end

of message reception

CAN module enters CAN reset

mode after waiting for the end of

message transmission (1, 4)

CAN module enters CAN reset

mode without waiting for the end

of bus-off recovery

CAN halt

mode

CAN module enters CAN halt

mode after waiting for the end of

message reception (2, 3)

CAN module enters CAN halt

mode after waiting for the end of

message transmission (1, 4)

- When the BOM bit is 00b

A halt request from a program

will be acknowledged only

after bus-off recovery

- When the BOM bit is 01b

CAN module automatically

enters CAN halt mode without

waiting for the end of bus-off

recovery (regardless of a halt

request from a program)

- When the BOM bit is 10b

CAN module automatically

enters CAN halt mode after

waiting for the end of bus-off

recovery (regardless of a halt

request from a program)

- When the BOM bit is 11b

CAN module enters CAN halt

mode (without waiting for the

end of bus-off recovery) if a

halt is requested by a program

during bus-off

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R32C/117 Group 25. CAN Module

25.2.3 CAN Sleep Mode

CAN sleep mode is used for reducing current consumption by stopping the clock supply to the CAN

module. After a MCU reset, the CAN module starts from CAN sleep mode.

When the SLPM bit in the C0CTLR register is set to 1, the CAN module enters CAN sleep mode. Then

the SLPST bit in the C0STR register becomes 1. Do not change the value of the SLPM bit until the

SLPST bit becomes 1. Other registers remain unchanged when the MCU enters CAN sleep mode.

Write to the SLPM bit in CAN reset mode and CAN halt mode. Only the SLPM bit can be changed

during CAN sleep mode. Do not change other bits or registers than the CiCTLR register. Read

operations are still allowed.

When the SLPM bit is set to 0, the CAN module is released from CAN sleep mode. When the CAN

module exits CAN sleep mode, the other registers remain unchanged.

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R32C/117 Group 25. CAN Module

25.2.4 CAN Operation Mode (Excluding Bus-off State)

CAN operation mode is used for CAN communication.

When the CANM bit in the C0CTLR register is set to 00b, the CAN module enters CAN operation mode.

Then bits RSTST and HLTST in the C0STR register become 0. Do not change the value of the CANM

bit until these bits become 0.

When 11 consecutive recessive bits are detected after entering CAN operation mode, the CAN module

is in the following states:

• The CAN module becomes an active node on the network that enables transmission and reception

of CAN messages.

• Error monitoring of the CAN bus, such as receive and transmit error counters, is performed.

During CAN operation mode, the CAN module may be in one of the following three submodes,

depending on the status of the CAN bus:

• Idle mode: Transmission or reception is not being performed.

• Receive mode: A CAN message sent by another node is being received.

• Transmit mode: A CAN message is being transmitted. The CAN module may receive its own

message simultaneously when self test mode 0 (TSTM bits in the C0TCR register are 10b) or self

test mode 1 (TSTM bits are 11b) is selected.

Figure 25.35 shows the submode in CAN operation mode.

Figure 25.35 Submode in CAN Operation Mode

TRMST and RECST: Bits in the C0STR register

Transmit mode

TRMST is 1

RECST is 0

Idle mode

TRMST is 0

RECST is 0

Receive mode

TRMST is 0

RECST is 1

Transmission

starts

Lost in arbitration

Transmission

completed

Reception

completed

SOF

detected

R01UH0211EJ0120 Rev.1.20 Page 463 of 604

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R32C/117 Group 25. CAN Module

25.2.5 CAN Operation Mode (Bus-off State)

The CAN module enters the bus-off state according to the increment/decrement rules for the transmit/

error counters in the CAN Specifications.

The following cases apply when recovering from the bus-off state. When the CAN module is in the bus-

off state, the values of the associated registers, except registers C0STR, C0EIFR, C0RECR, C0TECR,

and C0TSR, remain unchanged.

(1) When the BOM bit in the C0CTLR register is 00b (normal mode)

The CAN module enters the error-active state after it has completed the recovery from the bus-off

state and CAN communication is enabled. The BORIF bit in the C0EIFR register becomes 1 (bus-

off recovery detected) at this time.

(2) When the RBOC bit in the C0CTLR register is set to 1 (forced recovery from bus-off)

The CAN module enters the error-active state when it is in the bus-off state and the RBOC bit is set

to 1. CAN communication is enabled again after 11 consecutive recessive bits are detected. The

BORIF bit does not become 1 at this time.

(3) When the BOM bit is 01b (entry to CAN halt mode automatically at bus-off entry)

The CAN module enters CAN halt mode when it reaches the bus-off state. The BORIF bit does not

become 1 at this time.

(4) When the BOM bit is 10b (entry to CAN halt mode automatically at bus-off end)

The CAN module enters CAN halt mode when it has completed the recovery from bus-off. The

BORIF bit becomes 1 at this time.

(5)

When the BOM bit is 11b (entry to CAN halt mode by a program) and the CANM bit in the

C0CTLR register

is set to 10b (CAN halt mode) during the bus-off state

The CAN module enters CAN halt mode when it is in the bus-off state and the CANM bit is set to

10b (CAN halt mode). The BORIF bit does not become 1 at this time.

If the CANM bit is not set to 10b during bus-off, the same behavior as (1) applies.

R01UH0211EJ0120 Rev.1.20 Page 464 of 604

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R32C/117 Group 25. CAN Module

25.3 CAN Communication Speed Configuration

The following description explains about the CAN communication speed configuration.

25.3.1 CAN Clock Configuration

This group has a CAN clock selector.

The CAN clock can be configured by setting the CCLKS bit in the C0CLKR register and the BRP bit in

the C0BCR register.

Figure 25.36 shows the block diagram of CAN clock generator.

Figure 25.36 Block Diagram of the CAN Clock Generator

25.3.2 Bit Timing Configuration

The bit time is a single bit time for transmitting/receiving a message and consists of the three segments

in the figure below.

Figure 25.37 shows the bit timing.

Figure 25.37 Bit Timing

BCD and PCD: Bits in the CCR register

CCLKS: Bit in the C0CLKR register

fCAN: CAN system clock

P: Setting value of the BRP bit in the C0BCR register, P = 0 to 1023

fCANCLK: CAN communication clock, fCANCLK = fCAN/(P+1)

P = 0 to 1023

Main clock

b = 2, 3, 4, 6 q = 2, 3, 4

fCAN fCANCLK

XIN PLL frequency

synthesizer 1/b 1/q

BCD PCD

CCLKS

Baud rate

prescaler

1/(P+1)

PLL clock Base clock

Peripheral

bus clock

Range of each segment: Bit time = 8 Tq to 25 Tq

SS = 1 Tq

TSEG1 = 4 Tq to 16 Tq

TSEG2 = 2 Tq to 8 Tq

SJW = 1 Tq to 4 Tq

Setting of TSEG1 and TSEG2: TSEG1 > TSEG2 > SJW

Sample point

Bit time

TSEG1 TSEG2

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R32C/117 Group 25. CAN Module

25.3.3 Bit rate

The bit rate depends on the CAN clock (fCAN), the divisor of the baud rate prescaler, and the number

of Tq of 1 bit time.

Note:

1. Divisor of the baud rate prescaler = P + 1 (P = 0 to 1023)

P: Setting value of the BRP bit in the C0BCR register

Table 25.10 lists bit rate examples.

Table 25.10 Bit Rate Examples

fCAN32 MHz24 MHz20 MHz16 MHz 8 MHz

Bit Rate No. of Tq P+1 No. of Tq P+1 No. of Tq P+1 No. of Tq P+1 No. of Tq P+1

1 Mbps8 Tq48 Tq310 Tq28 Tq28 Tq1

16 Tq 2 20 Tq 1 16 Tq 1

500 kbps8 Tq88 Tq610 Tq48 Tq48 Tq2

16 Tq 4 16 Tq 3 20 Tq 2 16 Tq 2 16 Tq 1

250 kbps 8 Tq 16 8 Tq 12 10 Tq 8 8 Tq 8 8 Tq 4

16 Tq 8 16 Tq 6 20 Tq 4 16 Tq 4 16 Tq 2

83.3 kbps 8 Tq 48 8 Tq 36 8 Tq 30 8 Tq 24 8 Tq 12

16 Tq 24 16 Tq 18 10 Tq 24 16 Tq 12 16 Tq 6

16 Tq 15

20 Tq 12

33.3 kbps 8 Tq 120 8 Tq 90 8 Tq 75 8 Tq 60 8 Tq 30

10 Tq 96 10 Tq 72 10 Tq 60 10 Tq 48 10 Tq 24

16 Tq 60 16 Tq 45 20 Tq 30 16 Tq 30 16 Tq 15

20 Tq 48 20 Tq 36 20 Tq 24 20 Tq 12

Bit rate bps fCAN

Baud rate prescaler division value 1 number of Tq of 1 bit time

----------------------------------------------------------------------------------------------------------------------------------------------------------------- fCANCLK

Number of Tq of 1 bit time

-----------------------------------------------------------------==

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R32C/117 Group 25. CAN Module

25.4 Mailbox and Mask Register Structure

There are 32 mailboxes with the same structure.

Figure 25.38 shows the structure of C0MBj register (j = 0 to 31).

Figure 25.38 Structure of C0MBj Register (j = 0 to 31)

There are eight mask registers with the same structure.

Figure 25.39 shows the structure of C0MKRk Register (k = 0 to 7).

Figure 25.39 Structure of C0MKRk Register (k = 0 to 7)

b7 b0

Address

CAN0

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16

IDE RTR SID10 SID9 SID8 SID7 SID6

DLC3 DLC2 DLC1 DLC0

DATA0

DATA1

DATA7

TSL

TSH

47C00h + j × 16 + 0

47C00h + j × 16 + 1

47C00h + j × 16 + 2

47C00h + j × 16 + 3

47C00h + j × 16 + 4

47C00h + j × 16 + 5

47C00h + j × 16 + 6

47C00h + j × 16 + 7

47C00h + j × 16 + 13

47C00h + j × 16 + 14

47C00h + j × 16 + 15

C0MBj

Address

CAN0

47E00h + k × 4 + 0

47E00h + k × 4 + 1

47E00h + k × 4 + 2

47E00h + k × 4 + 3

b7 b0

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16

SID10 SID9 SID8 SID7 SID6

C0MKRk

R01UH0211EJ0120 Rev.1.20 Page 467 of 604

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R32C/117 Group 25. CAN Module

There are two FIFO received ID compare registers with the same structure.

Figure 25.40 shows the structure of C0FIDCRn Register (n = 0, 1).

Figure 25.40 Structure of C0FIDCRn Register (n = 0, 1)

Address

CAN0

47E20h + n × 4 + 0

47E20h + n × 4 + 1

47E20h + n × 4 + 2

47E20h + n × 4 + 3

b7 b0

EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0

EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8

SID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16

IDE RTR SID10 SID9 SID8 SID7 SID6

C0FIDCRn

R01UH0211EJ0120 Rev.1.20 Page 468 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

25.5 Acceptance Filtering and Masking Function

Acceptance filtering allows the user to receive messages with a specified range of multiple IDs for

mailboxes.

Registers C0MKR0 to C0MKR7 can perform masking of the standard ID and the extended ID of 29 bits.

• The C0MKR0 register corresponds to mailboxes [0] to [3].

• The C0MKR1 register corresponds to mailboxes [4] to [7].

• The C0MKR2 register corresponds to mailboxes [8] to [11].

• The C0MKR3 register corresponds to mailboxes [12] to [15].

• The C0MKR4 register corresponds to mailboxes [16] to [19].

• The C0MKR5 register corresponds to mailboxes [20] to [23].

• The C0MKR6 register corresponds to mailboxes [24] to [27] in normal mailbox mode, and receive

FIFO mailboxes [28] to [31] in FIFO mailbox mode.

• The C0MKR7 register corresponds to mailboxes [28] to [31] in normal mailbox mode, and receive

FIFO mailboxes [28] to [31] in FIFO mailbox mode.

The C0MKIVLR register disables acceptance filtering individually for each mailbox.

The IDE bit in the C0MBj register is enabled when the IDFM bit in the C0CTLR register is 10b (mixed ID

mode) (j = 0 to 31).

The RTR bit in the C0MBj register selects a data frame or a remote frame.

In FIFO mailbox mode, normal mailboxes (mailboxes [0] to [23]) use the single corresponding register

among registers C0MKR0 to C0MKR5 for acceptance filtering. Receive FIFO mailboxes (mailboxes [28]

to [31]) use two registers C0MKR6 and C0MKR7 for acceptance filtering.

Also, the receive FIFO uses registers C0FIDCR0 and C0FIDCR1 for ID comparison. Bits EID, SID, RTR,

and IDE in registers C0MB28 to C0MB31 for the receive FIFO are disabled. As acceptance filtering

depends on the result of two ID-mask sets, two ranges of IDs can be received into the receive FIFO.

The C0MKIVLR register is disabled for the receive FIFO.

If both the settings for standard ID and extended ID are set in the IDE bits in registers C0FIDCR0 and

C0FIDCR1 individually, both ID formats are received.

If both setting of data frame and remote frame are set in the RTR bits in registers C0FIDCR0 and

C0FIDCR1 individually, both the data and remote frames are received.

When a combination of two ranges of IDs is not necessary, set the same mask value and the same ID into

both of the FIFO ID/mask register sets.

Figure 25.41 shows the mask registers and their corresponding mailboxes, and Figure 25.42 shows

acceptance filtering.

R01UH0211EJ0120 Rev.1.20 Page 469 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

Figure 25.41 Mask Registers and Their Corresponding Mailboxes

Normal Mailbox Mode FIFO Mailbox Mode

C0MKR0 register

C0MKR1 register

C0MKR2 register

C0MKR3 register

C0MKR4 register

C0MKR5 register

C0MKR6 register

C0MKR7 register

Mailbox [0]

Mailbox [1]

Mailbox [2]

Mailbox [3]

Mailbox [4]

Mailbox [5]

Mailbox [6]

Mailbox [7]

Mailbox [8]

Mailbox [9]

Mailbox [10]

Mailbox [11]

Mailbox [12]

Mailbox [13]

Mailbox [14]

Mailbox [15]

Mailbox [16]

Mailbox [17]

Mailbox [18]

Mailbox [19]

Mailbox [20]

Mailbox [21]

Mailbox [22]

Mailbox [23]

Mailbox [24]

Mailbox [25]

Mailbox [26]

Mailbox [27]

Mailbox [28]

Mailbox [29]

Mailbox [30]

Mailbox [31]

C0MKR6 register

C0MKR7 register

C0MKR0 register

C0MKR1 register

C0MKR2 register

C0MKR3 register

C0MKR4 register

C0MKR5 register

Mailbox [0]

Mailbox [1]

Mailbox [2]

Mailbox [3]

Mailbox [4]

Mailbox [5]

Mailbox [6]

Mailbox [7]

Mailbox [8]

Mailbox [9]

Mailbox [10]

Mailbox [11]

Mailbox [12]

Mailbox [13]

Mailbox [14]

Mailbox [15]

Mailbox [16]

Mailbox [17]

Mailbox [18]

Mailbox [19]

Mailbox [20]

Mailbox [21]

Mailbox [22]

Mailbox [23]

Mailbox [24]

Mailbox [25]

Mailbox [26]

Mailbox [27]

Mailbox [28]

Mailbox [29]

Mailbox [30]

Mailbox [31]

C0FIDCR0 register

C0FIDCR1 register

Receive

FIFO

Transmit

FIFO

R01UH0211EJ0120 Rev.1.20 Page 470 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

Figure 25.42 Acceptance Filtering (j = 0 to 31; k = 0 to 7)

ID value of

received message

Acceptance judge signal

ID setting value of the

C0MBj register (1)

Setting value of the

C0MKRk register

Setting value of

C0MKIVLR register (2)

Mask bit values

0: IDs not compared

1: IDs compared

Acceptance judge signal

0: Receiving message is ignored (not stored in

any mailbox)

1: Receiving message is stored in a mailbox

which matches the ID

Notes:

1. The values set in registers C0FIDCR0 and C0FIDCR1 are used in FIFO mailbox mode.

2. Invalid in FIFO mailboxes.

R01UH0211EJ0120 Rev.1.20 Page 471 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

25.6 Reception and Transmission

Table 25.11 lists the CAN communication mode configuration.

TRMREQ, RECREQ, and ONESHOT: Bits in the C0MCTLj register (j = 0 to 31)

When a mailbox is configured as a receive mailbox or a one-shot receive mailbox, note the following:

(1) Before a mailbox is configured as a receive mailbox or a one-shot receive mailbox, set the

C0MCTLj register to 00h (j = 0 to 31).

(2) A received message is stored into the first mailbox that matches the condition according to the

result of receive mode configuration and acceptance filtering. Upon deciding which mailbox stores

the received message, the mailbox with the smaller number has higher priority.

(3) When transmitting a message in CAN operation mode, the CAN module does not receive the

message even if its ID matches the ID of its own mailbox for reception. However, the CAN module

receives the message and returns an ACK in self test mode.

When a mailbox is configured as a transmit mailbox or a one-shot transmit mailbox, note the following:

(1) Before a mailbox is configured as a transmit mailbox or one-shot transmit mailbox, ensure that the

C0MCTLj register is 00h and that there is no pending abort process.

Table 25.11 Configuration for CAN Reception Mode and Transmission Mode

TRMREQ RECREQ ONESHOT Communication Mode of Mailbox

0 0 0 Mailbox disabled or transmission being aborted

001

Configurable only when transmission or reception from a mailbox

(programmed in one-shot mode) is aborted

0 1 0 Configured as a receive mailbox for a data frame or a remote frame

011

Configured as a one-shot receive mailbox for a data frame or a

remote frame

1 0 0 Configured as a transmit mailbox for a data frame or a remote frame

101

Configured as a one-shot transmit mailbox for a data frame or a

remote frame

110Do not set

111Do not set

R01UH0211EJ0120 Rev.1.20 Page 472 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

25.6.1 Reception

Figure 25.43 shows an operation example of data frame reception in overwrite mode.

This example shows the operation of overwriting the first message when the CAN module receives two

consecutive CAN messages that match the receiving conditions of the C0MCTL0 register.

Figure 25.43 Operation Example of Data Frame Reception in Overwrite Mode (j = 0 to 31)

(1) When an SOF is detected on the CAN bus, the RECST bit in the C0STR register becomes 1

(reception in progress) if the CAN module has no message ready to start transmission.

(2) The acceptance filter procedure starts at the beginning of the CRC field to select the receive

mailbox.

(3) After a message has been received, the NEWDATA bit in the C0MCTLj register for the receive

mailbox becomes 1 (new data being updated/stored in the mailbox) (j = 0 to 31). Simultaneously,

the INVALDATA bit in the C0MCTLj register becomes 1 (message is being updated), and then the

INVALDATA bit becomes 0 (message valid) again after the complete message is transferred to the

mailbox.

(4) When the interrupt enable bit in the C0MIER register for the receive mailbox is 1 (interrupt

enabled), the CAN0 reception complete interrupt request is generated. This interrupt occurs when

the INVALDATA bit becomes 0.

(5) After reading the message from the mailbox, the NEWDATA bit needs to be set to 0 by a program.

(6) In overwrite mode, if the next CAN message has been received into a mailbox whose NEWDATA

bit is still set to 1, the MSGLOST bit in the C0MCTLj register becomes 1 (message has been

overwritten). The new received message is transferred to the mailbox. The CAN0 reception

complete interrupt request is generated the same as in (4).

CAN bus

RECREQ

INVALDATA

NEWDATA

MSGLOST

CAN0

reception

complete

interrupt

RECST

RECREQ, INVALDATA, NEWDATA, and MSGLOST: Bits in the C0MCTLj register

RECST: Bit in the C0STR register

CAN0 error

interrupt

CRC ACK EOF IFS SOF CRC ACK EOF IFSSOF

Receive message in mailbox 0 Receive message in mailbox 0

Acceptance filtering Acceptance filtering

R01UH0211EJ0120 Rev.1.20 Page 473 of 604

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R32C/117 Group 25. CAN Module

Figure 25.44 shows an operation example of data frame reception in overrun mode.

This example shows the operation of overrunning the second message when the CAN module receives

two consecutive CAN messages that match the receiving conditions of the C0MCTL0 register.

Figure 25.44 Operation Example of Data Frame Reception in Overrun Mode (j = 0 to 31)

(1) to (5) are the same as overwrite mode.

(6) In overrun mode, if the next message has been received before the NEWDATA bit is set to 0, the

MSGLOST bit in the C0MCTLj register becomes 1 (message has been overrun) (j = 0 to 31). The

new received message is discarded and a CAN0 error interrupt request is generated if the

corresponding interrupt enable bit in the C0EIER register is 1 (interrupt enabled).

CAN bus

RECREQ

INVALDATA

NEWDATA

MSGLOST

CAN0

reception

complete

interrupt

RECST

RECREQ, INVALDATA, NEWDATA, and MSGLOST: Bits in the C0MCTLj register

RECST: Bit in the C0STR register

CAN0 error

interrupt

CRC ACK EOF IFS SOF CRC ACK EOF IFSSOF

Receive message in mailbox 0 Receive message in mailbox 0

Acceptance filtering Acceptance filtering

R01UH0211EJ0120 Rev.1.20 Page 474 of 604

Feb 18, 2013

R32C/117 Group 25. CAN Module

25.6.2 Transmission

Figure 25.45 shows an operation example of data frame transmission. This example shows an

operation of transmitting messages that have been set in registers C0MCTL0 and C0MCTL1.

Figure 25.45 Operation Example of Data Frame Transmission (j = 0 to 31)

(1) When the TRMREQ bit in the C0MCTLj register is set to 1 (transmit mailbox) in the bus-idle state,

the mailbox scan procedure starts to decide the highest-priority mailbox for transmission (j = 0 to

31). Once the transmit mailbox is decided, the TRMACTIVE bit in the C0MCTLj register becomes 1

(from when a transmission request is received until transmission is completed, or an error/

arbitration lost has occurred), the TRMST bit in the C0STR register becomes 1 (transmission in

progress), and the CAN module starts transmission. (1)

(2) If other TRMREQ bits are set, the transmission scan procedure starts with the CRC delimiter for

the next transmission.

(3) If transmission is completed without losing arbitration, the SENTDATA bit in the C0MCTLj register

becomes 1 (transmission completed) and the TRMACTIVE bit becomes 0 (transmission is

pending, or no transmission request). If the interrupt enable bit in the C0MIER register is 1

(interrupt enabled), the CAN0 transmission complete interrupt request is generated.

(4) When requesting the next transmission from the same mailbox, set bits SENDTDATA and

TRMREQ to 0, then

set the TRMREQ bit to 1

after checking that bits SENDTDATA and TRMREQ

have been set to 0.

Note:

1. If arbitration is lost after the CAN module starts transmission, the TRMACTIVE bit becomes 0.

The transmission scan procedure is performed again to search for the highest-priority transmit

mailbox from the beginning of the CRC delimiter. If an error occurs either during transmission or

following the loss of arbitration, the transmission scan procedure is performed again from the

start of the error delimiter to search for the highest-priority transmit mailbox.

CAN bus

TRMREQ

TRMACTIVE

SENTDATA

TRMREQ

TRMACTIVE

SENTDATA

TRMREQ, TRMACTIVE, and SENTDATA: Bits in the C0MCTLj register

TRMST: Bit in the C0STR register

CAN0

transmission

complete

interrupt

CRC IFS SOF CRC CRC

delimiter EOF IFSSOF

Transmit message in mailbox 0 Transmit message in mailbox 1

TRMST

Next transmission scan Next transmission scan

CRC CRC

delimiter EOF

Next transmission scan

Mailbox 0Mailbox 1

R01UH0211EJ0120 Rev.1.20 Page 475 of 604

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R32C/117 Group 25. CAN Module

25.7 CAN Interrupts

The CAN module provides the following CAN interrupts:

• CAN0 wakeup interrupt

• CAN0 reception complete interrupt

• CAN0 transmission complete interrupt

• CAN0 receive FIFO interrupt

•CAN0 transmit FIFO interrupt

• CAN0 error interrupt

There are eight types of interrupt sources for the CAN0 error interrupts. These sources can be

determined by checking the C0EIFR register.

•Bus error

• Error-warning

• Error-passive

• Bus-off entry

• Bus-off recovery

• Receive overrun

• Overload frame transmission

•Bus lock

R01UH0211EJ0120 Rev.1.20 Page 476 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

26. I/O Pins

Each pin of the MCU functions as a programmable I/O port, an I/O pin for integrated peripherals, or a bus

control pin. These functions can be switched by the function select registers or the processor mode

registers. This chapter particularly addresses the function select registers. For the use as a bus control pin,

refer to 7. “Processor Mode” and 9. “Bus”.

The pull-up resistors are enabled for every group of four pins. However, a pull-up resistor is separated from

other peripherals even if it is enabled, when a pin functions as an output pin.

Figure 26.1 shows a block diagram of typical I/O pin.

Figure 26.1 Typical I/O Pin Block Diagram (i = 0 to 15; j = 0 to 7)

The registers to control I/O pins are as follows: port Pi direction register (PDi register), output function select

registers, and pull-up control registers. The PDi register selects the input or output state of pins. The output

function select registers which select output function consist of bits PSEL2 to PSEL0, NOD, and ASEL. Bits

PSEL2 to PSEL0 select a function as a programmable I/O or peripheral output (except analog output). The

NOD bit selects the N-channel open drain output for a pin. The ASEL bit prevents the increase in power

consumption of input buffer caused by an intermediate potential when a pin functions as an analog I/O pin.

The pull-up control registers enable/disable the pull-up resistors.

To use a pin as an analog I/O pin, set the PDi_j bit to 0 (input), bits PSEL2 to PSEL0 to 000b, and the ASEL

bit to 1.

The input-only port P8_5 shares a pin with NMI and has no function select register or bit 5 in the PD8

select register and bit 1 in the PD14 register are reserved. Port P9 is protected from unexpected write

accesses by the PRC2 bit in the PRCR register (refer to 10. “Protection”).

Peripheral 1 output

000

001

010

011

100

101

110

111

PSEL2

PSEL1

PSEL0

Pi_j pin

Port output

PDi_j

ASEL

NOD

The use of pull-up resistor

selection

Peripheral 2 output

Peripheral 3 output

Peripheral 4 output

Peripheral 5 output

Peripheral 6 output

Peripheral 7 output

Peripherals 1 to 7 input

Port input

Analog I/O

R01UH0211EJ0120 Rev.1.20 Page 477 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

26.1 Port Pi Direction Register (PDi Register, i = 0 to 15)

The PDi register selects the input or output state of pins. Bits in this register correspond to respective

pins.

In memory expansion mode or microprocessor mode, this register cannot control pins being assigned bus

control signals (A0 to A23, D0 to D31, CS0 to CS3, WR/WR0, BC0, BC1/WR1, BC2/WR2, BC3/WR3, RD,

CLKOUT/BCLK, HLDA, HOLD, ALE, and RDY).

Figure 26.2 shows the PDi register.

No register bit is provided for port P8_5. For port P14_1 (or P9_1 in the 100-pin package), a reserved bit

is provided.

The PD9 register is protected from unexpected write accesses by setting the PRC2 bit in the PRCR

Figure 26.2 Registers PD0 to PD15

Port Pi Direction Register (i = 0 to 15) (1)

Symbol

PD0 to PD3

PD4 to PD7

PD8 (2)

PD9 (3, 4), PD10

PD11 (2, 5)

PD12, PD13 (5)

PD14 (2, 4, 5)

PD15 (5)

Address

03C2h, 03C3h, 03C6h, 03C7h

03CAh, 03CBh, 03CEh, 03CFh

03D2h

03D3h, 03D6h

03D7h

03DAh, 03DBh

03DEh

03DFh

Reset Value

0000 0000b

00X0 0000b

0000 0000b

XXX0 0000b

0000 0000b

X000 0000b

0000 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Port Pi_0 Direction Bit (4) 0: Input port

1: Output port

RWPort Pi_2 Direction Bit (4)

RWPort Pi_3 Direction Bit

RWPort Pi_4 Direction Bit

RWPort Pi_5 Direction Bit (2)

RWPort Pi_6 Direction Bit (2)

RWPort Pi_7 Direction Bit (2)

RWPort Pi_1 Direction Bit (4)

Notes:

1. In memory expansion mode or microprocessor mode, this register cannot control pins being assigned bus

control signals (A0 to A23, D0 to D31, CS0 to CS3, WR/WR0, BC0, BC1/WR1, BC2/WR2, BC3 WR3, RD,

CLKOUT/BCLK, HLDA, HOLD, ALE, and RDY).

2. The PD8_5 bit in the PD8 register, bits PD11_5 to PD11_7 in the PD11 register, and the PD14_7 bit in the

PD14 register are unavailable on this MCU. If necessary, set these bits to 0. The read value is undefined.

3. Set the PRC2 bit in the PRCR register to 1 (write enabled) just before rewriting the PD9 register. No

interrupt handling or DMA transfers should be inserted between these two instructions.

4. Bits PD9_0 to PD9_2 in the PD9 register in the 100-pin package and PD14_0 to PD14_2 in the PD14

5. In the 100-pin package, enabled bits in registers PD11 to PD15 should be written with 1 (output port).

0: Input port

1: Output port

0: Input port

1: Output port

0: Input port

1: Output port

0: Input port

1: Output port

0: Input port

1: Output port

0: Input port

1: Output port

0: Input port

1: Output port

PDi_0

PDi_1

PDi_2

PDi_3

PDi_4

PDi_5

PDi_6

PDi_7

R01UH0211EJ0120 Rev.1.20 Page 478 of 604

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R32C/117 Group 26. I/O Pins

26.2 Output Function Select Registers

When a programmable I/O port and peripheral output share a pin, these registers select the output

function of the pin. Regardless of the register settings, signals are input to all the connected peripherals.

An output function select register consists of bits PSEL2 to PSEL0, NOD, and ASEL. Bits PSEL2 to

PSEL0 select a function as programmable I/O or peripheral output (except analog output). The NOD bit

selects the N-channel open drain output. The ASEL bit prevents the increase in power consumption

caused by an intermediate potential generated when a pin functions as an analog I/O pin.

Table 26.1 shows the peripherals assigned to each PSEL2 to PSEL0 bit combination, and Figures 26.3 to

26.19 show the function select registers.

Note that ports P8_5 and P14_1 (or P9_1 in the 100-pin package) (input only) have no output function

select registers.

The P9_iS register is protected from unexpected write accesses by setting the PRC2 bit in the PRCR

Table 26.1 Peripheral Assignment

Bits PSEL2 to PSEL0 Peripherals

001b Timer

010b Three-phase motor control timers

011b UART

100b UART special function

101b Intelligent I/O groups 0 and 2, CAN channel 0

110b Intelligent I/O group 1

111b UART8

R01UH0211EJ0120 Rev.1.20 Page 479 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.3 Registers P0_0S to P0_7S

Port P0_i shares a pin with the AN0_i input for the A/D converter (i = 0 to 7).

To use it as a programmable I/O port, set the P0_iS register to 00h. To use it as an A/D converter input

pin, set this register to 80h and the PD0_i bit to 0 (port P0_i functions as an input port).

Symbol

P0_0S to P0_2S

P0_3S to P0_5S

P0_6S, P0_7S

Address

400A0h, 400A2h, 400A4h

400A6h, 400A8h, 400AAh

400ACh, 400AEh

Reset Value

0XXX X000b

Port P0_i Function Select Register (i = 0 to 7)

Port P0_i Output Function

Select Bit

b2 b1 b0

0 0 0 : I/O port P0_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : Do not use this combination

1 0 0 : Do not use this combination

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

0: Function other than AN0_i

1: AN0_i

Port P0_i Analog Function

Select Bit

No register bits; should be written with 0 and read as undefined

value —

PSEL0

PSEL1

PSEL2

—

(b6-b3)

ASEL

R01UH0211EJ0120 Rev.1.20 Page 480 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.4 Registers P1_0S to P1_7S

Port P1_i shares a pin with intelligent I/O groups 0 and 1 (IIO0 and IIO1) and the external interrupt inputs

(i = 0 to 7).

To use it as an output pin, set the PD1_i bit to 1 (port P1_i functions as an output port) and select a

function according to Figure 26.4. To use it as an input pin, set the PD1_i bit to 0 (port P1_i functions as

an input port).

Symbol

P1_0S to P1_2S

P1_3S to P1_5S

P1_6S, P1_7S

Address

400A1h, 400A3h, 400A5h

400A7h, 400A9h, 400ABh

400ADh, 400AFh

Reset Value

XXXX X000b

Port P1_i Function Select Register (i = 0 to 7)

Port P1_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P1_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : Do not use this combination

1 0 0 : Do not use this combination

1 0 1 : IIO0_i output

1 1 0 : IIO1_i output

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

No register bits; should be written with 0 and read as undefined

value —

P1_0

Port Setting Value of Bits PSEL2 to PSEL0

101b 110b 111b

IIO1_0 outputIIO0_0 output

P1_1

P1_2

P1_3

P1_4

P1_5

P1_6

P1_7

— (2)

IIO1_1 outputIIO0_1 output

IIO1_2 outputIIO0_2 output

IIO1_3 outputIIO0_3 output

IIO1_4 outputIIO0_4 output

IIO1_5 outputIIO0_5 output

IIO1_6 outputIIO0_6 output

IIO1_7 outputIIO0_7 output

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

PSEL0

PSEL1

PSEL2

—

(b7-b3)

001b

— (2)

010b

— (2)

011b

— (2)

100b

— (2)

P1_0

000b

P1_1

P1_2

P1_3

P1_4

P1_5

P1_6

P1_7

R01UH0211EJ0120 Rev.1.20 Page 481 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.5 Registers P2_0S to P2_7S

Port P2_i shares a pin with the AN2_i for the A/D converter (i = 0 to 7).

To use it as a programmable I/O port, set the P2_iS register to 00h. To use it as an A/D converter input

pin, set this register to 80h and the PD2_i bit to 0 (port P2_i functions as an input port).

Symbol

P2_0S to P2_2S

P2_3S to P2_5S

P2_6S, P2_7S

Address

400B0h, 400B2h, 400B4h

400B6h, 400B8h, 400BAh

400BCh, 400BEh

Reset Value

0XXX X000b

Port P2_i Function Select Register (i = 0 to 7)

Port P2_i Output Function

Select Bit

b2 b1 b0

0 0 0 : I/O port P2_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : Do not use this combination

1 0 0 : Do not use this combination

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

0: Function other than AN2_i

1: AN2_i

Port P2_i Analog Function

Select Bit

No register bits; should be written with 0 and read as undefined

value —

PSEL0

PSEL1

PSEL2

—

(b6-b3)

ASEL

R01UH0211EJ0120 Rev.1.20 Page 482 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.6 Registers P3_0S to P3_7S

Port P3_i shares a pin with the timer output and three-phase motor control output (i = 0 to 7).

To use it as an output pin, set the PD3_i bit to 1 (port P3_i functions as an output port) and select a

function according to Figure 26.6. To use it as an input pin, set the PD3_i bit to 0 (port P3_i functions as

an input port).

Symbol

P3_0S to P3_2S

P3_3S to P3_5S

P3_6S, P3_7S

Address

400B1h, 400B3h, 400B5h

400B7h, 400B9h, 400BBh

400BDh, 400BFh

Reset Value

XXXX X000b

Port P3_i Function Select Register (i = 0 to 7)

Port P3_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P3_i

0 0 1 : Timer output

0 1 0 : Three-phase motor control

output

0 1 1 : Do not use this combination

1 0 0 : Do not use this combination

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

No register bits; should be written with 0 and read as undefined

value —

P3_0

Port Setting Value of Bits PSEL2 to PSEL0

001b

TA0OUT output

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

TA1OUT output

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

TA3OUT output

PSEL0

PSEL1

PSEL2

—

(b7-b3)

— (2)

TA2OUT output

— (2)

TA4OUT output

— (2)

P3_0

000b

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

010b 011b 100b 101b 110b 111b

— (2)

R01UH0211EJ0120 Rev.1.20 Page 483 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.7 Registers P4_0S to P4_7S

Port P4_i shares a pin with the serial interface (UART3 and UART6) and intelligent I/O group 2 (IIO2) (i =

0 to 7).

To use it as an output pin, set the PD4_i bit to 1 (port P4_i functions as an output port) and select a

function according to Figure 26.7. To use it as an input pin, set the PD4_i bit to 0 (port P4_i functions as

an input port).

Ports P4_0 to P4_7 are 5 V tolerant inputs. To use them as I/O pins with 5 V tolerant input enabled, set

the NOD bit to 1.

Symbol

P4_0S to P4_2S

P4_3S to P4_5S

P4_6S, P4_7S

Address

400C0h, 400C2h, 400C4h

400C6h, 400C8h, 400CAh

400CCh, 400CEh

Reset Value

X0XX X000b

Port P4_i Function Select Register (i = 0 to 7)

Port P4_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P4_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : UART3/UART6 output

1 0 0 : UART3/UART6 special

function output

1 0 1 : IIO2 output

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

No register bit; should be written with 0 and read as undefined

value

P4_0

Port Setting Value of Bits PSEL2 to PSEL0

P4_1

P4_2

P4_3

P4_4

P4_5

P4_6

P4_7

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

PSEL0

PSEL1

PSEL2

—

(b7) —

—

(b5-b3)

NOD

No register bits; should be written with 0 and read as undefined

value —

N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output RW

011b

RTS6

CLK6 output

RTS3

CLK3 output

SCL3 output

TXD3

SDA3 output

SCL6 output

TXD6

SDA6 output

P4_0

000b

P4_1

P4_2

P4_3

P4_4

P4_5

P4_6

P4_7

100b

— (2)

STXD3

— (2)

STXD6

— (2)

110b 111b

— (2)

101b

— (2)

OUTC2_0

ISTXD2

IEOUT

— (2)

001b

— (2)

010b

— (2)

R01UH0211EJ0120 Rev.1.20 Page 484 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.8 Registers P5_0S to P5_7S

Port P5_i shares a pin with the serial interface (UART7) (i = 0 to 7).

To use it as an output pin, set the PD5_i bit to 1 (port P5_i functions as an output port) and select a

function according to Figure 26.8. To use it as an input pin, set the PD5_i bit to 0 (port P5_i functions as

an input port).

Ports P5_4 to P5_7 are 5 V tolerant inputs. To use them as I/O pins with 5 V tolerant input enabled, set

the NOD bit to 1.

Symbol

P5_0S, P5_1S

P5_2S, P5_3S

P5_4S, P5_5S

P5_6S, P5_7S

Address

400C1h, 400C3h

400C5h, 400C7h

400C9h, 400CBh

400CDh, 400CFh

Reset Value

XXXX X000b

X0XX X000b

Port P5_i Function Select Register (i = 0 to 7)

Port P5_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P5_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : UART7 output

1 0 0 : Do not use this combination

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Name RW

No register bit; should be written with 0 and read as undefined

value

Bit Symbol

PSEL0

PSEL1

PSEL2

—

(b7) —

—

(b5-b3)

— (b6)

(i = 0 to 3)

NOD

(i = 4 to 7)

No register bits; should be written with 0 and read as undefined

value —

N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output RW

No register bit; should be written with 0 and read as undefined

value —

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

P5_0

Port Setting Value of Bits PSEL2 to PSEL0

P5_1

P5_2

P5_3

P5_4

P5_5

P5_6

P5_7

P5_0

000b

P5_1

P5_2

P5_3

P5_4

P5_5

P5_6

P5_7

001b

— (2)

010b

— (2)

011b

TXD7

CLK7 output

— (2)

RTS7

100b

— (2)

101b

— (2)

110b

— (2)

111b

— (2)

R01UH0211EJ0120 Rev.1.20 Page 485 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.9 Registers P6_0S to P6_7S

Port P6_i shares a pin with the serial interface (UART0 and UART1) and intelligent I/O group 2 (IIO2) (i =

0 to 7).

To use it as an output pin, set the PD6_i bit to 1 (port P6_i functions as an output port) and select a

function according to Figure 26.9. To use it as an input pin, set the PD6_i bit to 0 (port P6_i functions as

an input port).

Ports P6_0 to P6_7 are 5 V tolerant inputs. To use them as I/O pins with 5 V tolerant input enabled, set

the NOD bit to 1.

Symbol

P6_0S to P6_2S

P6_3S to P6_5S

P6_6S, P6_7S

Address

400D0h, 400D2h, 400D4h

400D6h, 400D8h, 400DAh

400DCh, 400DEh

Reset Value

X0XX X000b

Port P6_i Function Select Register (i = 0 to 7)

Port P6_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P6_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : UART0/UART1 output

1 0 0 : UART0/UART1 special

function output

1 0 1 : IIO2 output

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

PSEL0

PSEL1

PSEL2

—

(b7)

No register bit; should be written with 0 and read as undefined

value —

NOD N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output RW

—

(b5-b3)

No register bits; should be written with 0 and read as undefined

value —

P6_0

Port Setting Value of Bits PSEL2 to PSEL0

P6_1

P6_2

P6_3

P6_4

P6_5

P6_6

P6_7

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

P6_0

000b

P6_1

P6_2

P6_3

P6_4

P6_5

P6_6

P6_7

001b 010b 011b 100b

— (2)

RTS0

CLK0 output

SCL0 output

RTS1

CLK1 output

SCL1 output

TXD1

SDA1 output

— (2)

STXD0

— (2)

STXD1

— (2)

TXD0

SDA0 output

110b 111b

— (2)

101b

— (2)

OUTC_1

ISCLK2 output

— (2)

R01UH0211EJ0120 Rev.1.20 Page 486 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.10 Registers P7_0S to P7_7S

Port P7_i shares a pin with the timer, three-phase motor control, serial interface (UART2, UART5, and

UART8), multi-master I2C-bus interface (MMI2C), intelligent I/O groups 1 and 2 (IIO1 and IIO2), and CAN

module (i = 0 to 7).

To use it as an output pin, set the PD7_i bit to 1 (port P7_i functions as an output port) and select a

function according to Figure 26.10. To use it as an input pin, set the PD7_i bit to 0 (port P7_i functions as

an input port).

Ports P7_0 to P7_7 are 5 V tolerant inputs. To use them as I/O pins with 5 V tolerant input enabled, set

the NOD bit to 1.

Symbol

P7_0S to P7_2S

P7_3S to P7_5S

P7_6S, P7_7S

Address

400D1h, 400D3h, 400D5h

400D7h, 400D9h, 400DBh

400DDh, 400DFh

Reset Value

X0XX X000b

Port P7_i Function Select Register (i = 0 to 7)

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

PSEL0

PSEL1

PSEL2

Port P7_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P7_i

0 0 1 : Timer output

0 1 0 : Three-phase motor control

output

0 1 1 : UART2/UART5/MMI2C

output

1 0 0 : UART2 special function

output

1 0 1 : IIO2/CAN0 output

1 1 0 : IIO1 output

1 1 1 : UART8 output

P7_0 P7_0

000b

Port Setting Value of Bits PSEL2 to PSEL0

010b 100b

P7_1 P7_1

P7_2 P7_2

P7_3 P7_3

P7_4 P7_4

P7_5 P7_5

P7_6 P7_6

P7_7 P7_7

— (2)

STXD2

— (2)

2. Do not use this combination.

Notes:

1. Refer to the following table for each pin setting.

—

(b5-b3)

No register bits; should be written with 0 and read as undefined

value —

—

(b7)

No register bit; should be written with 0 and read as undefined

value —

NOD N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output RW

001b

TA0OUT output

TA1OUT output

— (2)

TA2OUT output

— (2)

TA3OUT output

— (2)

011b

TXD2

SDA2 output

MSDA output

SCL2 output

MSCL output

CLK2 output

RTS2

— (2)

TXD5

SDA5 output

CLK5 output

101b

OUTC2_0

ISTXD2

IEOUT

OUTC2_2

— (2)

CAN0OUT

— (2)

110b

IIO1_6 output

IIO1_7 output

— (2)

IIO1_0 output

IIO1_1 output

IIO1_2 output

IIO1_3 output

IIO1_4 output

111b

— (2)

TXD8

CLK8 output

— (2)

RTS8

— (2)

R01UH0211EJ0120 Rev.1.20 Page 487 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.11 Registers P8_0S to P8_4S, P8_6S, and P8_7S

Port P8_i shares a pin with the timer, three-phase motor control, serial interface (UART5), intelligent I/O

group 1 (IIO1), CAN module, and external interrupt inputs (i = 0 to 4, 6, 7).

To use it as an output pin, set the PD8_i bit to 1 (port P8_i functions as an output port) and select a

function according to Figure 26.11. To use it as an input pin, set the PD8_i bit to 0 (port P8_i functions as

an input port).

Ports P8_0 to P8_3 are 5 V tolerant inputs. To use them as I/O pins with 5 V tolerant input enabled, set

the NOD bit to 1.

Port P8_i Function Select Register (i = 0 to 4, 6, 7)

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Symbol

P8_0S, P8_1S

P8_2S, P8_3S

P8_4S

P8_6S, P8_7S

Address

400E0h, 400E2h

400E4h, 400E6h

400E8h

400ECh, 400EEh

Reset Value

X0XX X000b

XXXX X000b

b2 b1 b0

0 0 0 : I/O port P8_i

0 0 1 : Timer output

0 1 0 : Three-phase motor control

output

0 1 1 : UART5 output

1 0 0 : UART5 special function

output

1 0 1 : CAN0 output

1 1 0 : IIO1 output

1 1 1 : Do not use this combination

Port P8_i Output Function

Select Bit (1)

PSEL0

PSEL1

PSEL2

No register bits; should be written with 0 and read as undefined

value

—

(b5-b3) —

—

(b7)

No register bit; should be written with 0 and read as undefined

value —

N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output RW

NOD

(i = 0 to 3)

— (b6)

(i = 4, 6, 7)

No register bit; should be written with 0 and read as undefined

value —

P8_0 P8_0

000b

Port Setting Value of Bits PSEL2 to PSEL0

010b 100b 101b

— (2)

P8_1 P8_1

P8_2 P8_2

P8_3 P8_3

P8_4 P8_4

P8_6 P8_6

P8_7 P8_7

— (2)

STXD5

— (2)

CAN0OUT

— (2)

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

001b

TA4OUT output

— (2)

011b

SCL5 output

RTS5

— (2)

110b

— (2)

IIO1_5 output

— (2)

111b

— (2)

R01UH0211EJ0120 Rev.1.20 Page 488 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.12 Registers P9_0S to P9_7S (144-pin package)

Port P9_i Function Select Register (i = 0 to 7) (1)

Port P9_i Output Function

Select Bit (2)

b2 b1 b0

0 0 0 : I/O port P9_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : UART3/UART4 output

1 0 0 : UART3/UART4 special

function output

1 0 1 : IIO2 output

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Notes:

1. Set the PRC2 bit in the PRCR register to 1 (write enabled) just before rewriting this register. No interrupt

handling or DMA transfers should be inserted between these two instructions.

2. Refer to the following table for each pin setting.

PSEL0

PSEL1

PSEL2

—

(b5-b3)

No register bits; should be written with 0 and read as undefined

value —

Symbol

P9_0S to P9_2S

P9_3S to P9_5S

P9_6S

P9_7S

Address

400E1h, 400E3h, 400E5h

400E7h, 400E9h, 400EBh

400EDh

400EFh

Reset Value

X0XX X000b

00XX X000b

X0XX X000b

NOD N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output RW

0: Function other than Analog pin

1: Analog pin

Port P9_i (i = 3 to 6)

Analog Functions Select Bit

— (b7)

(i = 0 to 2, 7)

ASEL

(i = 3 to 6)

No register bit; should be written with 0 and read as undefined

value —

P9_0

Port Setting Value of Bits PSEL2 to PSEL0

P9_1

P9_2

P9_3

P9_4

P9_5

P9_6

P9_7

3. Do not use this combination.

011b

CLK3 output

SCL3 output

TXD3

SDA3 output

RTS3

RTS4

CLK4 output

TXD4

SDA4 output

SCL4 output

P9_0

000b

P9_1

P9_2

P9_3

P9_4

P9_5

P9_6

P9_7

001b 010b

— (3)

100b

STXD3

— (3)

STXD4

101b

— (3)

OUTC2_0

ISTXD2

IEOUT

— (3)

110b

— (3)

111b

— (3)

R01UH0211EJ0120 Rev.1.20 Page 489 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.13 Registers P9_3S to P9_7S (100-pin package)

Port P9_i shares a pin with the serial interface (UART3 and UART4) and intelligent I/O group 2 (IIO2), (i =

0 to 7). Ports P9_3 to P9_6 also share a pin with the A/D converter I/O (ANEX0 and ANEX1) and D/A

converter output.

To use it as the A/D converter pin or the D/A converter pin, set the P9_iS register to 80h and the PD9_i bit

to 0 (port P9_i functions as an input port) irrespective of the I/O state.

To use it as an output pin for functions other than the A/D converter or the D/A converter, set the PD9_i bit

to 1 (port P9_i functions as an output port) and select a function according to Figure 26.12. To use it as an

input pin of functions other than the A/D converter or the D/A converter, set the PD9_i bit to 0 (port P9_i

functions as an input port).

When the NOD bit is set to 1, the corresponding pin functions as an N-channel open drain output.

Symbol

P9_3S to P9_5S

P9_6S

P9_7S

Address

400E7h, 400E9h, 400EBh

400EDh

400EFh

Reset Value

00XX X000b

X0XX X000b

Port P9_i Function Select Register (i = 3 to 7) (1)

Port P9_i Output Function

Select Bit (2)

b2 b1 b0

0 0 0 : I/O port P9_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : UART4 output

1 0 0 : UART4 special function

output

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Port Setting Value of Bits PSEL2 to PSEL0

P9_3

P9_4

P9_5

P9_6

P9_7

Notes:

1. Set the PRC2 bit in the PRCR register to 1 (write enabled) just before rewriting this register. No interrupt

handling or DMA transfers should be inserted between these two instructions.

2. Refer to the following table for each pin setting.

3. Do not use this combination.

PSEL0

PSEL1

PSEL2

—

(b5-b3)

No register bits; should be written with 0 and read as undefined

value —

— (b6)

(i = 3)

NOD

(i = 4 to 7)

N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output

0: Function other than Analog pin

1: Analog pin

Port P9_i (i = 3 to 6)

Analog Functions Select Bit

— (b7)

(i = 7)

ASEL

(i = 3 to 6)

No register bit; should be written with 0 and read as undefined

value —

Reserved Should be written with 0

011b

— (3)

RTS4

CLK4 output

TXD4

SDA4 output

SCL4 output

000b

P9_3

P9_4

P9_5

P9_6

P9_7

001b 010b

— (3)

111b

— (3)

110b

— (3)

101b

— (3)

100b

— (3)

STXD4

R01UH0211EJ0120 Rev.1.20 Page 490 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.14 Registers P10_0S to P10_7S

Port P10_i shares a pin with the AN_i input for the A/D converter and key input interrupts (i = 0 to 7).

To use it as a programmable I/O port, set the P10_iS register to 00h. To use it as an input pin (except for

the A/D converter), set the PD10_i bit to 0 (port P10_i functions as an input port). To use it as an input pin

for the A/D converter, set the P10_iS register to 80h and the PD10_i bit to 0 (port P10_i functions as an

input port).

Symbol

P10_0S to P10_2S

P10_3S to P10_5S

P10_6S, P10_7S

Address

400F0h, 400F2h, 400F4h

400F6h, 400F8h, 400FAh

400FCh, 400FEh

Reset Value

0XXX X000b

Port P10_i Function Select Register (i = 0 to 7)

Port P10_i Output Function

Select Bit

b2 b1 b0

0 0 0 : I/O port P10_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : Do not use this combination

1 0 0 : Do not use this combination

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

0: Function other than AN_i

1: AN_i

Port P10_i Analog

Functions Select Bit

No register bits; should be written with 0 and read as undefined

value —

PSEL0

PSEL1

PSEL2

—

(b6-b3)

ASEL

R01UH0211EJ0120 Rev.1.20 Page 491 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.15 Registers P11_0S to P11_4S

Port P11_i shares a pin with the serial interface (UART8) and intelligent I/O group 1 (IIO1) (i = 0 to 4).

To use it as an output pin, set the PD11_i bit to 1 (port P11_i functions as an output port) and select a

function according to Figure 26.15. To use it as an input pin, set the PD11_i bit to 0 (port P11_i functions

as an input port).

To use as an N-channel open drain output, set the NOD bit to 1.

Port P11_i Function Select Register (i = 0 to 4)

Port P11_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P11_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : UART8 output

1 0 0 : Do not use this combination

1 0 1 : Do not use this combination

1 1 0 : IIO1_i output

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

Notes:

1. Refer to the following table for each pin setting.

PSEL0

PSEL1

PSEL2

—

(b7) —

Symbol

P11_0S to P11_2S

P11_3S

P11_4S

Address

400F1h, 400F3h, 400F5h

400F7h

400F9h

Reset Value

X0XX X000b

XXXX X000b

No register bit; should be written with 0 and read as undefined

value

—

(b5-b3) —

No register bits; should be written with 0 and read as undefined

value

NOD

(i = 0 to 3)

— (b6)

(i = 4)

N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output RW

No register bit; should be written with 0 and read as undefined

value —

P11_0

Port Setting Value of Bits PSEL2 to PSEL0

011b 100b 101b 110b 111b

IIO1_0 output— (2)

P11_1

P11_2

P11_3

P11_4

TXD8

— (2)

RTS8

— (2)

IIO1_1 output— (2)

IIO1_2 output— (2)

IIO1_3 output— (2)

— (2)

2. Do not use this combination.

P11_0

000b

P11_1

P11_2

P11_3

P11_4

CLK8 output

001b 010b

— (2)

R01UH0211EJ0120 Rev.1.20 Page 492 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.16 Registers P12_0S to P12_7S

Port P12_i shares a pin with the serial interface (UART6) (i = 0 to 7).

To use it as an output pin, set the PD12_i bit to 1 (port P12_i functions as an output port) and select a

function according to Figure 26.16. To use it as an input pin, set the PD12_i bit to 0 (port P12_i functions

as an input port).

When the NOD bit is set to 1, the corresponding pin functions as an N-channel open drain output.

Symbol

P12_0S to P12_2S

P12_3S

P12_4S to P12_6S

P12_7S

Address

40100h, 40102h, 40104h

40106h

40108h, 4010Ah 4010Ch

4010Eh

Reset Value

X0XX X000b

XXXX X000b

Port P12_i Function Select Register (i = 0 to 7)

Port P12_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P12_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : UART6 output

1 0 0 : UART6 special function

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

No register bits; should be written with 0 and read as undefined

value —

PSEL0

PSEL1

PSEL2

—

(b5-b3)

P12_0

Port Setting Value of Bits PSEL2 to PSEL0

P12_1

P12_2

P12_3

P12_4

P12_5

P12_6

P12_7

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

No register bit; should be written with 0 and read as undefined

value —

—

(b7)

NOD

(i = 0 to 3)

— (b6)

(i = 4 to 7)

N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output

No register bits; should be written with 0 and read as undefined

value

—

P12_0

000b

P12_1

P12_2

P12_3

P12_4

P12_5

P12_6

P12_7

001b 010b

— (2)

— (2) — (2)

— (2)

100b 101b 110b 111b

— (2)

STXD6

— (2)

011b

— (2)

TXD6

SDA6 output

CLK6 output

SCL6 output

RTS6

— (2)

R01UH0211EJ0120 Rev.1.20 Page 493 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.17 Registers P13_0S to P13_7S

Port P13_i shares a pin with intelligent I/O group 2 (IIO2) (i = 0 to 7).

To use it as an output pin, set the PD13_i bit to 1 (port P13_i functions as an output port) and select a

function according to Figure 26.17. To use it as an input pin, set the PD13_i bit to 0 (port P13_i functions

as an input port).

Symbol

P13_0S to P13_2S

P13_3S to P13_5S

P13_6S, P13_7S

Address

40101h, 40103h, 40105h

40107h, 40109h, 4010Bh

4010Dh, 4010Fh

Reset Value

XXXX X000b

Port P13_i Function Select Register (i = 0 to 7)

Port P13_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P13_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : Do not use this combination

1 0 0 : Do not use this combination

1 0 1 : IIO2 output

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

No register bits; should be written with 0 and read as undefined

value —

P13_0

Port Setting Value of Bits PSEL2 to PSEL0

P13_1

P13_2

P13_3

P13_4

P13_5

P13_6

P13_7

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

PSEL0

PSEL1

PSEL2

—

(b7-b3)

P13_0

000b

P13_1

P13_2

P13_3

P13_4

P13_5

P13_6

P13_7

001b 010b 011b 100b 110b 111b

— (2)

101b

OUTC2_4

OUTC2_5

OUTC2_6

OUTC2_3

OUTC2_0

ISTXD2

IEOUT

OUTC2_2

OUTC2_1

ISCLK2 output

OUTC2_7

R01UH0211EJ0120 Rev.1.20 Page 494 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.18 Registers P14_3S to P14_6S

Port P14_i shares a pin with external interrupt inputs. Set the P14_iS register to 00h (I/O port) (i = 3 to 6).

Symbol

P14_3S to P14_5S

P14_6S

Address

40116h, 40118h, 4011Ah

4011Ch

Reset Value

XXXX X000b

Port P14_i Function Select Register (i = 3 to 6)

Port P14_i Output Function

Select Bit

b2 b1 b0

0 0 0 : I/O port P14_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

0 1 1 : Do not use this combination

1 0 0 : Do not use this combination

1 0 1 : Do not use this combination

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Symbol Bit Name RW

No register bits; should be written with 0 and read as undefined

value

PSEL0

PSEL1

PSEL2

—

(b7-b3) —

R01UH0211EJ0120 Rev.1.20 Page 495 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.19 Registers P15_0S to P15_7S

Port P15_i shares a pin with the serial interface (UART6 and UART7), intelligent I/O group 0 (IIO0), and

AN15_i input for the A/D converter (i = 0 to 7).

To use it as an output pin, set the PD15_i bit to 1 (port P15_i functions as an output port) and select a

function according to Figure 26.19. To use it as an input pin (except for the A/D converter), set the PD15_i

bit to 0 (port P15_i functions as an input port). To use it as an input pin for the A/D converter, set the

P15_iS register to 80h and the PD15_i bit to 0.

To use as an N-channel open drain output, set the NOD bit to 1.

Symbol

P15_0S to P15_2S

P15_3S to P15_5S

P15_6S, P15_7S

Address

40111h, 40113h, 40115h

40117h, 40119h, 4011Bh

4011Dh, 4011Fh

Reset Value

00XX X000b

Port P15_i Function Select Register (i = 0 to 7)

Port P15_i Output Function

Select Bit (1)

b2 b1 b0

0 0 0 : I/O port P15_i

0 0 1 : Do not use this combination

0 1 0 : Do not use this combination

011:UART6/UART7 output

1 0 0 : UART6 special function

1 0 1 : IIO0_i output

1 1 0 : Do not use this combination

1 1 1 : Do not use this combination

b7 b6 b5 b4 b1b2b3 b0

FunctionBit Name RW

0: Function other than AN15_i

1: AN15_i

Port P15_i Analog Function

Select Bit

P15_0

Port Setting Value of Bits PSEL2 to PSEL0

011b 100b 101b 110b 111b

P15_1

P15_2

P15_3

P15_4

P15_5

P15_6

P15_7

— (2)

STXD6

— (2)

Notes:

1. Refer to the following table for each pin setting.

2. Do not use this combination.

IIO0_0 output

IIO0_1 output

IIO0_2 output

IIO0_3 output

IIO0_4 output

IIO0_5 output

IIO0_6 output

IIO0_7 output

— (2)

TXD7

CLK7 output

— (2)

RTS7

TXD6

SDA6 output

SCL6 output

CLK6 output

RTS6

Bit Symbol

PSEL0

PSEL1

PSEL2

—

(b5-b3)

ASEL

—

NOD N-channel Open Drain

Output Select Bit

0: Push-pull output

1: N-channel open drain output RW

No register bits; should be written with 0 and read as undefined

value

P15_0

000b

P15_1

P15_2

P15_3

P15_4

P15_5

P15_6

P15_7

001b 010b

— (2)

R01UH0211EJ0120 Rev.1.20 Page 496 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

26.3 Input Function Select Registers

When a peripheral input is assigned to multiple pins, these registers select which input pin should be

connected to the peripheral.

Figures 26.20 to 26.23 show the input function select registers.

R01UH0211EJ0120 Rev.1.20 Page 497 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.20 IFS0 Register

Symbol

IFS0

Address

40098h

Reset Value

X000 0000b

FunctionBit Symbol Bit Name RW

Input Function Select Register 0

Timer A Input Pin Switch

Bit (1)

UART6 Input Pin Switch Bit

(3)

UART8 Input Pin Switch Bit

(4)

b7 b6 b5 b4 b1b2b3 b0

IFS00

IFS01

IFS02

IFS03

IFS04

IFS06 UART3 Input Pin Switch Bit

(6)

IFS05

Assign UART6 input to

b3 b2

00:Port P4

0 1 : Do not use this combination

10:Port P15

11:Port P12

Timer B Input Pin Switch

Bit (2)

UART7 Input Pin Switch Bit

(5)

—

(b7)

Assign timer A input to

0: Port P3

1: Port P7/port P8

Assign timer B input to

0: Port P6

1: Port P9

Assign UART8 input to

0: Port P7

1: Port P11

Assign UART7 input to

0: Port P5

1: Port P15

Assign UART3 input to

0: Port P4

1: Port P9

No register bit; should be written with 0 and read as undefined

value —

5. Refer to the following table for each pin setting of UART7. This bit should be set to 00b in the 100-pin package.

RXD7CLK7 input CTS7IFS05

P5_6P5_5 P5_7

P15_2P15_1 P15_3

4. Refer to the following table for each pin setting of UART8. This bit should be set to 00b in the 100-pin package.

RXD8CLK8 input CTS8IFS04

P7_5P7_4 P7_6

P11_2P11_1 P11_3

6. Refer to the following table for each pin setting of UART3. This bit should be set to 00b in the 100-pin package.

CLK3 input CTS3/SS3IFS06

P4_1 P4_0

P9_0 P9_3

SDA3 input/SRXD3

P4_3

P9_2

RXD3/SCL3 input

P4_2

P9_1

TA0OUT input TA1OUT input TA1IN TA2OUT input TA2IN TA3OUT input TA4OUT input TA4INIFS00

P3_0 P3_2 P3_3 P3_4 P3_5 P3_1 P3_6 P3_7

P7_0 P7_2 P7_3 P7_4 P7_5 P7_6 P8_0 P8_1

Notes:

1. Refer to the following table for each pin setting of timer A.

2. Refer to the following table for each pin setting of timer B. This bit should be set to 0 in the 100-pin package.

TB1INTB0IN TB2INIFS01

P6_1P6_0 P6_2

P9_1P9_0 P9_2

3. Refer to the following table for each pin setting of UART6. This bit should be set to 00b in the 100-pin package.

CLK6 input CTS6/SS6IFS03

P4_5 P4_4

P15_6 P15_7

1P12_1 P12_3

IFS02

SDA6 input/SRXD6

P4_7

P15_4

P12_0

RXD6/SCL6 input

P4_6

P15_5

P12_2

R01UH0211EJ0120 Rev.1.20 Page 498 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.21 IFS1 Register

Symbol

IFS1

Address

40099h

Reset Value

XXXX X0X0b

FunctionBit Symbol Bit Name RW

—

Input Function Select Register 1

Assign CAN0IN/CAN0WU input to

0: Port P7_7

1: Port P8_3

CAN0 Input Pin Switch Bit

No register bit; should be written with 0 and read as undefined

value

b7 b6 b5 b4 b1b2b3 b0

IFS10

—

(b1)

—

No register bits; should be written with 0 and read as undefined

value

—

(b7-b3)

Should be written with 0 RW

—

(b2) Reserved

R01UH0211EJ0120 Rev.1.20 Page 499 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.22 IFS2 Register

Symbol

IFS2

Address

4009Ah

Reset Value

0000 00X0b

FunctionBit Symbol Bit Name RW

Input Function Select Register 2

Assign IIO0 input to

0: Port P1

1: Port P15

Intelligent I/O Group 0 Input

Pin Switch Bit (1)

b7 b6 b5 b4 b1b2b3 b0

IFS20

Notes:

1. Refer to the following table for each pin setting of intelligent I/O group 0. This bit should be set to 0 in the

100-pin package.

2. Refer to the following table for each pin setting of intelligent I/O group 0 in two-phase pulse signal

processing mode.

IIO0_0 input IIO0_1 input IIO0_2 input IIO0_3 input IIO0_4 input IIO0_5 input IIO0_6 input IIO0_7 inputIFS20

1P15_0 P15_1 P15_2 P15_3 P15_4 P15_5 P15_6 P15_7

P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7

3. Refer to the following table for each pin setting of intelligent I/O group 1. This bit should not be set to 01b in

the 100-pin package.

UD0A UD0B UD0ZIFS23

P8_0 P8_1 P8_3 (INT1)

P7_6 P7_7 P8_2 (INT0)

IFS22

P3_0 P3_1 P8_3 (INT1)

P3_0 P3_1 P8_2 (INT0)

4. Refer to the following table for each pin setting of intelligent I/O group 1 in two-phase pulse signal

processing mode.

IIO1_0 input IIO1_1 input IIO1_2 input IIO1_3 input IIO1_4 input IIO1_5 input IIO1_6 input IIO1_7 input

P7_3 P7_4 P7_5 P7_6 P7_7 P8_1 P7_0 P7_1

P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 P1_6 P1_7

IFS25

IFS24

1 0

P11_0 P11_1 P11_2 P11_3

UD1A UD1BIFS27

P8_0 P8_1

P7_6 P7_7

IFS26

P3_0 P3_1

UD1Z

P8_3 (INT1)

P8_2 (INT0)

P8_3 (INT1)

P8_2 (INT0)

— — — —

No register bit; should be written with 0 and read as undefined

value

Intelligent I/O Group 0 Two-

phase Pulse Input Pin

Switch Bit (2)

Assign this input to

b3 b2

0 0 : Port P8 and INT1

0 1 : Port P7 and INT0

1 0 : Port P3 and INT1

1 1 : Port P3 and INT0

Intelligent I/O Group 1 Input

Pin Switch Bit (3)

Assign IIO1 input to

b5 b4

0 0 : Port P7/port P8

01:Port P11

10:Port P1

1 1 : Do not use this combination

Intelligent I/O Group 1 Two-

phase Pulse Input Pin

Switch Bit (4)

Assign this input to

b7 b6

0 0 : Port P8 and INT1

0 1 : Port P7 and INT0

1 0 : Port P3 and INT1

1 1 : Port P3 and INT0

—

(b1)

IFS22

IFS23

IFS24

IFS25

IFS26

IFS27

—

R01UH0211EJ0120 Rev.1.20 Page 500 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.23 IFS3 Register

Symbol

IFS3

Address

4009Bh

Reset Value

XXXX XX00b

FunctionBit Symbol Bit Name RW

Input Function Select Register 3

Note:

1. Refer to the following table for each pin setting of intelligent I/O group 2. This bit should be set to 00b or

11b in the 100-pin package.

—

No register bits; should be written with 0 and read as undefined

value

b7 b6 b5 b4 b1b2b3 b0

Intelligent I/O Group 2 Input

Pin Switch Bit (1)

ISCLK2 input ISRXD2/IEIN

P6_4 P7_1

IFS31

IFS30

1P6_4 P9_1

IFS30

—

(b7-b2)

IFS31

Assign IIO2 input to

b1 b0

0 0 : Port P6/port P7

0 1 : Port P6/port P9

10:Port P13

1 1 : Port P6/port P4

P13_6 P13_51

1P6_4 P4_2

R01UH0211EJ0120 Rev.1.20 Page 501 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

26.4 Pull-up Control Registers 0 to 4 (Registers PUR0 to PUR4)

Figures 26.24 to 26.28 show registers PUR0 to PUR4.

These registers enable/disable the pull-up resistors for every group of four pins. To enable the pull-up

resistors, set the corresponding bits in registers PUR0 to PUR4 to 1 (pull-up resistor enabled) and the

respective bits in the direction register to 0 (input).

In memory expansion mode or microprocessor mode, set 0 (pull-up resistor disabled) to the pull-up

control bits for ports P0 to P5, and P11 to P13, operating as bus control pins. The pull-up resistors are

enabled for ports P0, P1, and P11 to P13 when these pins function as input ports in these modes.

Figure 26.24 PUR0 Register

Pull-up Control Register 0 (1)

Symbol

PUR0

Address

03F0h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

P1_4 to P1_7 Pull-up

Control Bit

P0_0 to P0_3 Pull-up

Control Bit

Control pull-up setting for

corresponding ports

0: Pull-up resistor disabled

1: Pull-up resistor enabled

P0_4 to P0_7 Pull-up

Control Bit

P1_0 to P1_3 Pull-up

Control Bit

P3_0 to P3_3 Pull-up

Control Bit

P2_0 to P2_3 Pull-up

Control Bit

P2_4 to P2_7 Pull-up

Control Bit

P3_4 to P3_7 Pull-up

Control Bit

Note:

1. In memory expansion mode or microprocessor mode, each bit in the PUR0 register should be set to 0 since

ports P0 to P3 are used as bus control pins. However, the pull-up resistors are enabled for ports P0 and P1

when these pins function as I/O ports with 8-bit bus or multiplexed bus format.

PU00

PU01

PU02

PU03

PU04

PU05

PU06

PU07

R01UH0211EJ0120 Rev.1.20 Page 502 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.25 PUR1 Register

Figure 26.26 PUR2 Register

Pull-up Control Register 1 (1)

Symbol

PUR1

Address

03F1h

Reset Value

XXXX X0XXb

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Control pull-up setting for

corresponding ports

0: Pull-up resistor disabled

1: Pull-up resistor enabled

P5_0 to P5_3 Pull-up

Control Bit

Note:

1. In memory expansion mode or microprocessor mode, each bit in the PUR1 register should be set to 0 since

the port P5 functions as a bus control pin.

—

No register bits; should be written with 0 and read as undefined

value

PU12

—

(b7-b3)

—

No register bits; should be written with 0 and read as undefined

value

—

(b1-b0)

Pull-up Control Register 2

Symbol

PUR2

Address

03F2h

Reset Value

000X XXXXb

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Control pull-up setting for

corresponding ports

0: Pull-up resistor disabled

1: Pull-up resistor enabled

P9_0 to P9_3 Pull-up

Control Bit (2)

P8_4 to P8_7 Pull-up

Control Bit (1)

Notes:

1. Port P8_5 has no pull-up resistor.

2. Ports P9_0 and P9_2 have no pull-up resistor in the 100-pin package.

PU25

PU26

—

(b4-b0)

No register bits; should be written with 0 and read as undefined

value —

PU27 RW

P9_4 to P9_7 Pull-up

Control Bit

R01UH0211EJ0120 Rev.1.20 Page 503 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.27 PUR3 Register

Figure 26.28 PUR4 Register

Pull-up Control Register 3

Symbol

PUR3

Address

03F3h

Reset Value

0000 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

P11_4 Pull-up Control Bit (1,

P10_0 to P10_3 Pull-up

Control Bit

Control pull-up setting for

corresponding ports

0: Pull-up resistor disabled

1: Pull-up resistor enabled

P10_4 to P10_7 Pull-up

Control Bit

P11_0 to P11_3 Pull-up

Control Bit (1, 2)

P13_0 to P13_3 Pull-up

Control Bit (1, 2)

P12_0 to P12_3 Pull-up

Control Bit (1, 2)

P12_4 to P12_7 Pull-up

Control Bit (1, 2)

P13_4 to P13_7 Pull-up

Control Bit (1, 2)

Notes:

1. Ports P11 to P13 are not available in the 100-pin package. Bits PU32 to PU37 should be set to 0.

2. In memory expansion mode or microprocessor mode, bits PU32 to PU37 should be set to 0 since ports P11

to P13 function as bus control pins. However, the pull-up resistors are enabled for ports P11 to P13 when

these pins function as I/O ports with 8-/16-bit bus or multiplexed bus format.

PU30

PU31

PU32

PU33

PU34

PU35

PU36

PU37

Pull-up Control Register 4 (1)

Symbol

PUR4

Address

03F4h

Reset Value

XXXX 0000b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

P14_1 and P14_3 Pull-up

Control Bit

Control pull-up setting for

corresponding ports

0: Pull-up resistor disabled

1: Pull-up resistor enabled

P14_4 to P14_6 Pull-up

Control Bit

P15_0 to P15_3 Pull-up

Control Bit

P15_4 to P15_7 Pull-up

Control Bit

PU40

PU41

PU42

PU43

—

(b7-b4) —

No register bits; should be written with 0 and read as undefined

value

Note:

1. This register should be set to 00h in the 100-pin package.

R01UH0211EJ0120 Rev.1.20 Page 504 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

26.5 Port Control Register (PCR Register)

Figure 26.29 shows the PCR register.

This register selects an output mode for port P1 between push-pull output and pseudo-N-channel open

drain output. When the PCR0 bit is set to 1, the P-channel transistor in the output buffer is turned off. Note

that port P1 cannot be a perfect open drain output due to remaining parasitic diode. The absolute

maximum rating of the input voltage is, therefore, -0.3 V to VCC + 0.3 V (refer to Figure 26.30).

In memory expansion mode or microprocessor mode, when port P1 is used for the data bus, the PCR0 bit

should be set to 0. However, when port P1 is used as a programmable I/O port or an I/O pin for the

peripheral functions, the output mode can be selected by setting the PCR0 bit even in these operating

modes.

Figure 26.29 PCR Register

Figure 26.30 Port P1 Output Buffer Configuration

Port Control Register

Symbol

PCR

Address

03FFh

Reset Value

0XXX XXX0b

RWFunctionBit Symbol Bit Name

b7 b6 b5 b4 b1b2b3 b0

Port P1 Output Format

Control Bit (1)

0: Push-pull output

1: Pseudo-N-channel open drain

output (2)

—

No register bits; should be written with 0 and read as undefined

value

Notes:

1. In memory expansion mode or microprocessor mode, this bit should be set to 0 since port P1 is used for the

data bus. However, when it is used as an I/O port or an I/O pin for the peripheral functions, the PCR0 bit can

select an output format between push-pull output and pseudo-N-channel open drain output.

2. This function is designated not to make port P1 a full open drain, but to turn off the P-channel transistor in the

CMOS output buffer. Therefore, the absolute maximum rating of the input voltage is -0.3 V to VCC + 0.3 V.

3. This bit should not be set to 1 in the 100-pin package.

PCR0

—

(b6-b1)

Ports P9_0, P9_2, P11 to

P15 Enable Bit (3)

0: Ports P9_0, P9_2, P11 to P15

disabled

1: Ports P9_0, P9_2, P11 to P15

enabled

PCE

PCR0 bit

PD1_i bit

P1_i bit

Parasitic diode

P1_i I/O pin

i = 0 to 7

R01UH0211EJ0120 Rev.1.20 Page 505 of 604
Feb 18, 2013
R32C/117 Group 26.  I/O Pins
26.6 Configuring Unused Pins
Tables 26.2 and 26.3, and Figure 26.32 show examples of configuring unused pins on the board.
Notes:
1. Unused pins should be wired within 2 cm of the MCU.
2. When configuring the pins as output ports to leave them open, note that ports as inputs remain
unchanged from when the reset is released until the mode transition is completed. During this
transition, the power supply current may increase due to an undefined voltage level of the pins. In
addition, the direction register value may change due to noise or program runaway caused by the
noise. To avoid these situations, reconfigure the direction register regularly by software, which may
achieve higher program reliability.
3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only.
4. In the 100-pin package, set FFh to the following addresses: 03D7h, 03DAh, 03DBh, 03DEh, and
03DFh.
5. Select a resistance value that is appropriate for the system. A range from 10 to 100 k is
recommended.
6. This setting is applicable when an external clock is applied to the XIN pin.
Table 26.2 Unused Pin Configuration in Single-chip Mode (1)
Pin Name Setting
Ports P0 to P15 (excluding ports 
P8_5, and P9_1 (in the 100-pin 
package) or P14_1 (in the 144-pin 
package)) (2, 3, 4)
Configure as input ports so that each pin is connected to VSS via its 
own resistor; (5) or configure as output ports to leave the pins open
P9_1 (in the 100-pin package) Connect the pin to VSS via a resistor (5)
P14_1 (in the 144-pin package) Connect the pin to VSS via a resistor (5)
XOUT (6) Leave pin open
NMI (P8_5) Connect the pin to VCC via a resistor (5)
AVCC Connect the pin to VCC
AVSS, VREF Connect the pin to VSS
NSD Connect the pin to VCC via a resistor of 1 to 4.7 k

R01UH0211EJ0120 Rev.1.20 Page 506 of 604

Feb 18, 2013

R32C/117 Group 26. I/O Pins

Notes:

1. Unused pins should be wired within 2 cm of the MCU.

2. When configuring the pins as output ports to leave them open, note that ports as inputs remain

unchanged from when the reset is released until the mode transition is completed. During this

transition, the power supply current may increase due to an undefined voltage level of the pins. In

addition, the direction register value may change due to noise or program runaway caused by the

noise. To avoid these situations, reconfigure the direction register regularly by software, which may

achieve higher program reliability.

5. Select a resistance value that is appropriate for the system. A range from 10 to 100 k is

recommended.

6. This setting is applicable when an external clock is applied to the XIN pin.

Table 26.3 Unused Pin Configuration in Memory Expansion Mode or Microprocessor Mode (1)

Pin Name Setting

Ports P1, P6 to P15 (excluding

ports P8_5, and P9_1 (in the 100-

pin package) or P14_1 (in the 144-

pin package)) (2, 3, 4)

Configure as input ports so that each pin is connected to VSS via its

own resistor; (5) or configure as output ports to leave the pins open

P9_1 (in the 100-pin package) Connect the pin to VSS via a resistor (5)

P14_1 (in the 144-pin package) Connect the pin to VSS via a resistor (5)

BC0 to BC3, WR0 to WR3, ALE,

HLDA, XOUT (6), BCLK

Leave the pins open

HOLD, RDY Connect the pins to VCC via a resistor (5)

NMI (P8_5) Connect the pin to VCC via a resistor (5)

AVCC Connect the pin to VCC

AVSS, VREF Connect the pins to VSS

NSD Connect the pin to VCC via a resistor of 1 to 4.7 k

3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only.

4. In the 100-pin package, set FFh to the following addresses: 03D7h, 03DAh, 03DBh, 03DEh, and

03DFh.

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Feb 18, 2013

R32C/117 Group 26. I/O Pins

Figure 26.31 Pull-up/Pull-down Resistors

Figure 26.32 Unused Pin Configuration

Pull-up/pull-down resistors

IIL

IIH

The figure shows the equivalent circuit of an input pin.

The equivalent input resistors (RP and RN) are calculated using input power

current (IIL and IIH).

Example: When VCC = 5.0 V, IIH = IIL = 5 µA,

Since the voltage (VIH) defined as high is more than 0.8 VCC,

the resistance value R should satisfy the following expression:

R//RP : RN = 0.2 : 0.8

That is,

Specifically,

Example: When VCC = 5.0 V, IIH = IIL = 5 µA,

The maximum pull-up resistor R is approximately 330 k.

The actual resistance value is the calculated value with some margins.

RRP = RN == 1 M

5.0

5 × 10-6

R = 2RPRN

8RP - 2RN

R = = 333333

2 × 106 × 106

8 × 106 - 2 × 106

MCU

Ports P0

to P15

(excluding

port P8_5)

(1)

(Input mode)

(Output mode)

NMI (P8_5)

XOUT

AVCC

NSD

AVSS

VREF

In single-chip mode VSS

Open

(Input mode)

MCU

Ports P1,

P6 to P15

(excluding

port P8_5)

(1)

(Input mode)

(Output mode)

NMI (P8_5)

BC0 to BC3

ALE

AVCC

AVSS

VREF

In memory expansion mode or

microprocessor mode

Open

(Input mode)

HLDA

XOUT

BCLK

HOLD

RDY

Note:

1. Ports P11 to P15 are in the 144-pin package only.

VSS

VCC

Open

VCC

1 to 4.7 k

Open VCC

WR0 to WR3

VCC

NSD

1 to 4.7 k

VCC

R01UH0211EJ0120 Rev.1.20 Page 508 of 604

Feb 18, 2013

R32C/117 Group 27. Flash Memory

27. Flash Memory

27.1 Overview

The flash memory can be programmed in the following three modes: CPU rewrite mode, standard serial I/

O mode, and parallel I/O mode.

Table 27.1 lists specifications of the flash memory and Table 27.2 shows the overview of each rewrite

mode.

Figure 27.1 shows the on-chip flash memory structure.

The on-chip flash memory contains program area to store user programs, and data area/data flash to

store the result of user programs. The program area consists of blocks 0 to 17, and data area/data flash

consists of blocks A and B.

Each block can be individually protected (locked) from programming or erasing by setting the lock bit.

Table 27.1 Flash Memory Specifications

Item Specification

Rewrite modes CPU rewrite mode, standard serial I/O mode, parallel I/O mode

Structure Block architecture. Refer to Figure 27.1

Program operation 8-byte basis

Erase operation 1-block basis

Program and erase control method Software commands

Protection types Lock bit protect, ROM code protect, ID code protect

Software commands 9

Table 27.2 Flash Memory Rewrite Mode Overview

Rewrite Mode CPU Rewrite Mode Standard Serial I/O Mode Parallel I/O Mode

Function CPU executes a software

command to rewrite the flash

memory

EW0 mode:

Rewritable in areas other

than the on-chip flash

memory

EW1 mode:

Rewritable in areas other

than specified blocks to be

rewritten

A dedicated serial

programmer rewrites the flash

memory

Standard serial I/O mode 1:

Synchronous serial I/O

selected

Standard serial I/O mode 2:

UART selected

A dedicated parallel

programmer rewrites the

flash memory

CPU operating

mode

Single-chip mode,

Memory expansion mode

(EW0 mode)

Standard serial I/O mode Parallel I/O mode

Programmer — Serial programmer Parallel programmer

On-board

programming

Supported Supported Not supported

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R32C/117 Group 27. Flash Memory

Figure 27.1 On-chip Flash Memory Block Diagram

Block B : 4 Kbytes

Block 8 : 64 Kbytes

Block 7 : 64 Kbytes

Block 6 : 64 Kbytes

Block 5 : 64 Kbytes

Block 4 : 64 Kbytes

Block 9 : 64 Kbytes

Block 2 : 32 Kbytes

Block 1 : 32 Kbytes

Block 0 : 32 Kbytes

FFF80000h

FFF90000h

FFFA0000h

FFFB0000h

FFFC0000h

FFFD0000h

FFFE0000h

FFFF0000h

FFFF8000h

FFFFFFFFh

FFFF7FFFh

FFFEFFFFh

FFFDFFFFh

FFFCFFFFh

FFFBFFFFh

FFFAFFFFh

FFF9FFFFh

FFF8FFFFh

00060000h

00060FFFh

Block 3 : 32 Kbytes

FFFE8000h

FFFE7FFFh

Block A : 4 Kbytes

00061000h

00061FFFh

Block 12 : 64 Kbytes

Block 11 : 64 Kbytes

Block 10 : 64 Kbytes

Block 13 : 64 Kbytes

FFF40000h

FFF50000h

FFF60000h

FFF70000h

FFF7FFFFh

FFF6FFFFh

FFF5FFFFh

FFF4FFFFh

Block 16 : 64 Kbytes

Block 15 : 64 Kbytes

Block 14 : 64 Kbytes

Block 17 : 64 Kbytes

FFF00000h

FFF10000h

FFF20000h

FFF30000h

FFF3FFFFh

FFF2FFFFh

FFF1FFFFh

FFF0FFFFh

768 KB

version

1 MB

version

640 KB

version

512 KB

version

384 KB

version

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Feb 18, 2013

R32C/117 Group 27. Flash Memory

27.2 Flash Memory Protection

There are three types of protection as shown in Table 27.3. Lock bit protection is intended to prevent

accidental write or erase by program runaway. ROM code protection and ID code protection are intended

to prevent read or write by a third party.

27.2.1 Lock Bit Protection

This protection can be used in all three rewrite modes. When the lock bit protection is enabled, all

blocks whose lock bits are set to 0 (locked) are protected against programming and erasing.

To set the lock bit to 0, the lock bit program command must be issued.

To temporarily disable the protection of all protected blocks, disable the lock bit protection itself by

setting the LBD bit in the FMR1 register to 1 (lock bit protection disabled). The protection of a protected

block is disabled permanently and its lock bit becomes 1 (unlocked) if the block is erased.

27.2.2 ROM Code Protection

This protection can only be used in parallel I/O mode. When the ROM code protection is enabled, the

entire flash memory is protected against reading and writing.

To disable the protection, erase all the blocks whose protect bits are set to 0 (protected).

Each block has two protect bits. Setting any protect bit to 0 by a software command enables the

protection for the entire flash memory. Table 27.4 lists protect bit addresses.

Table 27.3 Protection Types and Characteristics

Protection Type Lock Bit Protection ROM Code Protection ID Code Protection

Protected

operations

Erase, write Read, write Read, erase, write

Protection

available in

CPU rewrite mode

Standard serial I/O mode

Parallel I/O mode

Parallel I/O mode Standard serial I/O mode

Protection

available for

Individual blocks Entire flash memory Entire flash memory

Protection

settings

Setting 0 to the lock bit of

block to be protected

Setting the protect bit of any

block to 0

Writing the program which

has set an ID code to

specified address

Protection

disabled by

Setting the LBD bit in the

FMR register to 1 (lock bit

protection disabled), or by

erasing the blocks whose

lock bits are set to 0 to

permanently disable the

protection

Erasing all blocks whose

protect bits are set to 0

Sending a proper ID code

from the serial programmer

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R32C/117 Group 27. Flash Memory

27.2.3 ID Code Protection

This protection can only be used in standard serial I/O mode. A command from the serial programmer

is to be accepted when the 7-byte ID code sent from the serial programmer matches the ID code

programmed in the flash memory. However, when the reset vector is FFFFFFFFh, the ID code check is

skipped because the flash memory is considered to be blank. When the reset vector is FFFFFFFFh and

the ROM code protection is enabled, only the block erase command is accepted.

The ID codes sent from the serial programmer are consecutively numbered as ID1, ID2, ..., and ID7. ID

codes programmed in the flash memory, also numbered as ID1, ID2, ..., and ID7, are assigned to

addresses FFFFFFE8h, FFFFFFE9h, ..., and FFFFFFEEh as shown in Figure 27.2. The ID code

protection is enabled when a program which has an ID code set in the corresponding address is written

to the flash memory.

In the high speed version (64 MHz version), the following two ASCII code combinations are specified as

reserved ID codes: “ALeRASE” and “Protect”. Refer to Table 27.5, 27.2.4 “Forcible Erase Function”,

and 27.2.5 “Standard Serial I/O Mode Disable Function” for details.

Table 27.4 Protect Bit Addresses

Block Protect Bit 0 Protect Bit 1

Block B 00060100h 00060300h

Block A 00061100h 00061300h

Block 17 FFF00100h FFF00300h

Block 16 FFF10100h FFF10300h

Block 15 FFF20100h FFF20300h

Block 14 FFF30100h FFF30300h

Block 13 FFF40100h FFF40300h

Block 12 FFF50100h FFF50300h

Block 11 FFF60100h FFF60300h

Block 10 FFF70100h FFF70300h

Block 9 FFF80100h FFF80300h

Block 8 FFF90100h FFF90300h

Block 7 FFFA0100h FFFA0300h

Block 6 FFFB0100h FFFB0300h

Block 5 FFFC0100h FFFC0300h

Block 4 FFFD0100h FFFD0300h

Block 3 FFFE0100h FFFE0300h

Block 2 FFFE8100h FFFE8300h

Block 1 FFFF0100h FFFF0300h

Block 0 FFFF8100h FFFF8300h

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Feb 18, 2013

R32C/117 Group 27. Flash Memory

Figure 27.2 Addresses for ID Code Stored

27.2.4 Forcible Erase Function

The forcible erase function is available in standard serial I/O mode in the high speed version (64 MHz

version). It is not available in the normal speed version (50 MHz version). With this function, all blocks

of the flash memory are forcibly erased when ID codes sent from the serial programmer matches the

ASCII code corresponding to the following sequential ASCII-glyphs: “A”, “L”, “e”, “R”, “A”, “S”, and “E”.

However, the function is ignored when the ROM code protection is activated and ID codes other than

“ALeRASE” are programmed in the flash memory.

Table 27.5 Reserved ID Codes

ID Code ID1 ID2 ID3 ID4 ID5 ID6 ID7

ALeRASE Glyph AL eRASE

ASCII code 41h 4Ch 65h 52h 41h 53h 45h

Protect Glyph P r o t e c t

ASCII code 50h 72h 6Fh 74h 65h 63h 74h

Table 27.6 Operational Conditions for Forcible Erase Function

ID Codes Sent From

the Serial Programmer

ID Codes Programmed in

the Flash Memory

ROM Code

Protection Function

“ALeRASE”

“ALeRASE” — Erase all blocks of the flash memory

Any codes other than

“ALeRASE” or ”Protect”

Inactivated

Activated Check ID codes (resulted in unmatched

codes)

Any codes other than

“ALeRASE”

“ALeRASE” — Check ID codes (resulted in unmatched

codes)

Any codes other than

“ALeRASE” or ”Protect” —Check ID codes

Reserved

NMI interrupt vector

Reset vectorFFFFFFFFh to FFFFFFFCh

FFFFFFFBh to FFFFFFF8h

FFFFFFF7h to FFFFFFF4h

Watchdog timer interrupt vectorFFFFFFF3h to FFFFFFF0h

ReservedFFFFFFEFh to FFFFFFECh

ID4FFFFFFEBh to FFFFFFE8h

BRK instruction interrupt vector

Overflow interrupt vector

Undefined instruction vector

FFFFFFE7h to FFFFFFE4h

FFFFFFE3h to FFFFFFE0h

FFFFFFDFh to FFFFFFDCh

4 bytes

ID3

ID7 ID6

ID2 ID1

ID5

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R32C/117 Group 27. Flash Memory

27.2.5 Standard Serial I/O Mode Disable Function

The standard serial I/O mode disable function is available in the high speed version (64 MHz version) It

is not available in the normal speed version (50 MHz version). With the standard serial I/O mode

disable function, the flash memory in standard serial I/O mode is inaccessible from the CPU when ID

code programmed in the flash memory are ASCII codes corresponding to the following sequential

ASCII-glyphs: “P”, “r”, “o”, “t”, “e”, “c”, and “t”.

When the ROM code protection is activated and ID codes corresponding to “Protect” are programmed,

the serial programmer cannot deactivate the ROM code protection. In this case, the flash memory is not

accessible from the outside of MCU, except that the parallel programmer can delete the flash memory.

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R32C/117 Group 27. Flash Memory

27.3 CPU Rewrite Mode

In CPU rewrite mode, the CPU executes software commands to rewrite the flash memory. The CPU

accesses the flash memory not via the CPU buses, but via the dedicated flash memory rewrite buses

(refer to Figure 27.3).

Figure 27.3 Flash Memory Access Path in CPU Rewrite Mode

Bus setting for flash memory rewrite should be performed by registers FEBC0 and FEBC3. Refer to

27.3.2 “Flash Memory Rewrite Bus Timing” and 28. “Electrical Characteristics” for the appropriate bus

setting. Note that registers FEBC0 and FEBC3 share respective addresses with registers EBC0 and

EBC3. That is, a rewrite of these registers affects the external bus setting. Set registers EBC0 and EBC3

again after rewriting the registers FEBC0 and FEBC3.

CPU

Flash Memory

BIU

Flash memory rewrite data bus (16-bit)

Flash memory rewrite address bus (20-bit)

CPU address bus (26-bit)

CPU data bus (64-bit)

Flash memory access

path in normal

operating mode

Flash memory access

path in CPU rewrite

mode

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Feb 18, 2013

R32C/117 Group 27. Flash Memory

The CPU rewrite mode contains modes EW0 and EW1 as shown in Table 27.7.

Note:

1. The CS0 space and CS3 space have limited availability in memory expansion mode. Refer to 27.3.1

“CPU Operating Mode and Flash Memory Rewrite” for details.

To select CPU rewrite mode, the FEW bit in the FMCR register should be set to 1. Then, EW0 mode/EW1

mode can be selected by setting the EWM bit in the FMR0 register.

Registers FMCR and FMR0 are protected by registers PRR and FPR0, respectively.

Figures 27.4 to 27.12 show associated registers.

Table 27.7 EW0 and EW1 Modes

Item EW0 Mode EW1 Mode

CPU operating modes Single-chip mode

Memory expansion mode (1)

Single-chip mode

Rewrite program

executable spaces

Spaces other than the on-chip flash

memory

Internal spaces other than specified

blocks to be rewritten, internal RAM

Restrictions on

software commands

None • Do not execute either the program

command or the block erase command

for blocks where the rewrite control

programs are written to

• Do not execute the enter read status

• Execute the enter read lock bit status

mode command in RAM

• Execute the enter read protect bit

status mode command in RAM

Mode after program/

erase operation

Read status register mode Read array mode

CPU state during

program/erase

operation

Operating In a hold state (I/O ports maintain the

state before the command was

executed)

Flash memory state

detection by

• Reading the FMSR0 register by a

program

• Executing the enter read status

• Reading the FMSR0 register by a

program

Other restrictions None • Disable interrupts (except NMI) and

DMA transfer during program/erase

operation

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R32C/117 Group 27. Flash Memory

Figure 27.4 FMCR Register

b7 b6 b5 b4 b1b2b3 Symbol

FMCR

Address

0006h

Reset Value

0000 0001b

FunctionBit Symbol Bit Name RW

Flash Memory Control Register (1)

Notes:

1. Set the PRR register to AAh (write enabled) before rewriting this register.

2. Do not set this bit to 1 when the MRS bit in the VRCR register is 1 (main regulator stopped).

Should be written with 0Reserved

CPU Rewrite Mode Setting

Bit (2)

0: Normal operating mode

1: CPU rewrite mode

Should be written with 1Reserved

0000001

FEW

—

(b0)

—

(b6-b1)

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R32C/117 Group 27. Flash Memory

Figure 27.5 Registers FEBC0 and FEBC3

Symbol

FEBC0, FEBC3

Address

001Dh-001Ch, 0011h-0010h

Reset Value

0000h

FunctionBit Symbol Bit Name RW

Flash Memory Rewrite Bus Control Register i (i = 0, 3) (1 )

RD Pulse Width Setting Bit

0 1 0 1 0

b15 b8 b7 b0

FWR0

FWR1

FWR2

FWR3

b3 b2 b1 b0

0000:wr = 1

0001:

wr = 2

0101:

wr = 3

0110:

wr = 4

1010:

wr = 5

1011:

wr = 6

1111:

wr = 7

Only use the combinations listed

above

Address Setup Before WR

Setting Bit

b9 b8

00:suw = 0

01:

suw = 1

10:

suw = 2

11:

suw = 3

RWWR Pulse Width Setting Bit

b11 b10

00:ww = 1

01:

ww = 2

10:

ww = 3

11:

ww = 4

Multiplied Cycle Setting Bit

b7 b6

0 0 : Do not use this combination

0 1 : Do not use this combination

10:

mpy = 3

11:

mpy = 4

Reserved

—

(b15)

—

(b14)

Should be written with 0 RW

Should be written with 1 RW

MPY0

MPY1

FSUW0

FSUW1

FWW0

FWW1

—

(b13) Reserved Should be written with 0 RW

Reserved

—

(b5) Should be written with 0 RW

—

(b12) Reserved Should be written with 1

Note:

1. Set the PRR register to AAh (write enabled) before rewriting this register.

0: No pulse width extension

1: Pulse width extension selected

RD Pulse Width Extension

Select Bit

FWR4 RW

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R32C/117 Group 27. Flash Memory

Figure 27.6 FPR0 Register

Figure 27.7 FMR0 Register

b7 b6 b5 b4 b1b2b3 Symbol

FPR0

Address

40008h

Reset Value

0000 0000b

FunctionBit Symbol Bit Name RW

Flash Register Protection Unlock Register 0

For registers FMR0 and FMR1,

0: Write disabled

1: Write enabled

Protection Unlock Bit

000000

PR0

—

(b7-b1) RWShould be written with 0Reserved

b7 b6 b5 b4 b1b2b3 Symbol

FMR0

Address

40000h

Reset Value

0X01 XX00b

FunctionBit Symbol Bit Name RW

Read Ready Flag RO

Flash Memory Control Register 0 (1, 2)

Notes:

1. Set the PR0 bit in the FPR0 register to 1 (write enabled) before rewriting this register.

2. This register is reset after exiting wait mode or stop mode.

3. After entering read lock bit status mode, the lock bit status is reflected to bit 6 of read data when reading

any even address in the corresponding block.

4. The LBS bit reflects the lock bit status when issuing the read lock bit status command.

0: EW0 mode

1: EW1 mode

Rewrite Mode Select Bit

EWM

LBM

LBS

RRDY

FCA

—

(b5)

—

(b6)

—

(b7)

0: Read via data bus (3)

1: Read by the LBS bit (4)

Lock Bit Read Mode

Setting Bit

0: Locked

1: Unlocked

Lock Bit Status Flag (4)

0: Busy

1: Ready

0: Final command accept ready

1: Final command accept busy

Final Command Accept

Busy Flag

RWShould be written with 0Reserved

ROThis bit is read as undefined valueReserved

RWShould be written with 0Reserved

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R32C/117 Group 27. Flash Memory

Figure 27.8 FMR1 Register

Figure 27.9 FMSR0 Register

b7 b6 b5 b4 b1b2b3 Symbol

FMR1

Address

40009h

Reset Value

0000 0010b

FunctionBit Symbol Bit Name RW

Flash Memory Control Register 1 (1)

0 0 0 0 0

—

(b2)

LBD

—

(b7-b4)

0: Reset

1: Reset released

Reset Release Bit

—

(b0) RWShould be written with 0Reserved

RWShould be written with 0Reserved

0: Lock bit protection enabled

1: Lock bit protection disabled

Lock Bit Protect Disable Bit

Should be written with 0Reserved RW

Note:

1. Set the PR0 bit in the FPR0 register to 1 (write enabled) before rewriting this register.

b7 b6 b5 b4 b1b2b3 Symbol

FMSR0

Address

40001h

Reset Value

1000 0000b

FunctionBit Symbol Bit Name RW

Flash Memory Status Register 0

These bits are read as undefined

value

Reserved

—

(b3-b0)

WERR

EERR

—

(b6)

RDY

0: No program error

1: Program error occurred

Program Error Flag

ROThis bit is read as undefined valueReserved

0: No erase error

1: Erase error occurred (1)

Erase Error Flag

0: Busy

1: Ready

Ready Flag

Note:

1. If an erase error has occurred, issue the clear status register command first, then reissue the block erase

command repeatedly until no more erase errors occur. After that, execute three more block erase

operations.

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R32C/117 Group 27. Flash Memory

Figure 27.10 FBPM0 Register

Figure 27.11 FBPM1 Register

b7 b6 b5 b4 b1b2b3 Symbol

FBPM0

Address

4000Ah

Reset Value

??X? ????b (1)

FunctionBit Symbol Bit Name RW

Block Protect Bit Monitor Register 0 (1)

0: Protected

1: Protection unlocked

Block 0 Protect Bit Monitor

Flag

BP0

0: Protected

1: Protection unlocked

Block 1 Protect Bit Monitor

Flag

BP1

0: Protected

1: Protection unlocked

Block 2 Protect Bit Monitor

Flag

BP2

0: Protected

1: Protection unlocked

Block 3 Protect Bit Monitor

Flag

BP3

0: Protected

1: Protection unlocked

Block 4 Protect Bit Monitor

Flag

BP4

0: Protected

1: Protection unlocked

Block 5 Protect Bit Monitor

Flag

BP5

0: Protected

1: Protection unlocked

Block 6 Protect Bit Monitor

Flag

BP6

ROThis bit is read as undefined valueReserved

—

(b5)

Note:

1. This register is updated only once after reset is released. The protect bit status at that time is applied as

reset value.

b7 b6 b5 b4 b1b2b3 Symbol

FBPM1

Address

4000Bh

Reset Value

XXX? ????b (1)

FunctionBit Symbol Bit Name RW

Block Protect Bit Monitor Register 1 (1)

0: Protected

1: Protection unlocked

Block 7 Protect Bit Monitor

Flag

BP7

0: Protected

1: Protection unlocked

Block 8 Protect Bit Monitor

Flag

BP8

0: Protected

1: Protection unlocked

Block B Protect Bit Monitor

Flag

BPB

These bits are read as undefined

value

Reserved

—

(b7-b5)

Note:

1. This register is updated only once after reset is released. The protect bit status at that time is applied as the

reset value.

0: Protected

1: Protection unlocked

Block 9 Protect Bit Monitor

Flag

BP9

0: Protected

1: Protection unlocked

Block A Protect Bit Monitor

Flag

BPA

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R32C/117 Group 27. Flash Memory

Figure 27.12 FBPM2 Register

b7 b6 b5 b4 b1b2b3 Symbol

FBPM2

Address

40011h

Reset Value

???? ????b (1)

FunctionBit Symbol Bit Name RW

Block Protect Bit Monitor Register 2 (1)

0: Protected

1: Protection unlocked

Block 10 Protect Bit

Monitor Flag

BP10

0: Protected

1: Protection unlocked

Block 11 Protect Bit

Monitor Flag

BP11

0: Protected

1: Protection unlocked

Block 13 Protect Bit

Monitor Flag

BP13

0: Protected

1: Protection unlocked

Block 14 Protect Bit

Monitor Flag

BP14

0: Protected

1: Protection unlocked

Block 15 Protect Bit

Monitor Flag

BP15

Note:

1. This register is updated only once after reset is released. The protect bit status at that time is applied as the

reset value.

0: Protected

1: Protection unlocked

Block 12 Protect Bit

Monitor Flag

BP12

0: Protected

1: Protection unlocked

Block 16 Protect Bit

Monitor Flag

BP16

0: Protected

1: Protection unlocked

Block 17 Protect Bit

Monitor Flag

BP17

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R32C/117 Group 27. Flash Memory

27.3.1 CPU Operating Mode and Flash Memory Rewrite

Registers used to set the bus timing of rewriting the flash memory vary with the CPU operating modes.

Do not change the 00h reset value of registers CB01, CB12, and CB23 when using single-chip mode.

The bus setting for both the program area and data area can be performed using the FEBC0 register.

In cases other than the above, when the CPU operation is performed in memory expansion mode more

than once, set registers CB01, CB12, and CB23 according to each setting range as shown in Table

27.8. The bus setting for program area and data area can be performed by the FEBC0 register and

FEBC3 register, respectively.

Note that registers FEBC0 and FEBC3 in memory expansion mode share respective addresses with

registers EBC0 and EBC3. That is, when the FEBCi register (i = 0, 3) is set for the flash memory

rewrite, the setting value for the EBCi register is accordingly changed. This may cause external devices

allocated to the CS0 space and/or CS3 space in CPU rewrite mode to become inaccessible.

Table 27.8 lists the details of bus setting for the flash memory rewrite in each CPU operating mode.

Table 27.8 CPU Operating Mode and Flash Memory Rewrite

Item CPU Operating Mode

Single-chip mode Memory expansion mode

CB01 register Hold the reset value 00h Setting range: 02h to F8h

Set a value equal to or greater than that of the

CB12 register

CB12 register Hold the reset value 00h Setting range: 02h to F8h

Set a value equal to or greater than that of the

CB23 register and equal to or less than that of the

CB01 register

CB23 register Hold the reset value 00h Setting range: 02h to F8h

Set a value equal to or less than that of the CB12

Bus setting for program area FEBC0 register FEBC0 register

Bus setting for data area FEBC0 register FEBC3 register

State of CS0 space and CS3

space after the FEBCi

N/A • Separate bus format

• 16-bit bus width

•RDY ignored

Restrictions for the use of

CS0 space and CS3 space

None • HOLD is ignored

• In CPU rewrite mode, external devices become

inaccessible to data with the bus format set for

CS0 space and/or CS3 space as multiplexed bus

• The change in bus timing may cause external

devices in the CS0 space and/or CS3 space to

become inaccessible

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R32C/117 Group 27. Flash Memory

27.3.2 Flash Memory Rewrite Bus Timing

As mentioned in 27.3.1, the bus setting for the flash memory rewrite is performed by setting the FEBC0

and/or FEBC3 registers. This section specifically describes the setting of registers FEBC0 and FEBC3.

The reference clock is the base clock set with bits BCD1 and BCD0 in the CCR register. Time duration

including tsu, tw, tc, and th are specified by the number of base clock cycles.

Tables 27.9 to 27.11 show the correlation of the read cycle and setting of bits MPY1, MPY0, and FWR4

to FWR0, according to peripheral bus clock divide ratios. Tables 27.12 to 27.14 show the correlation of

the write cycle and setting of bits MPY1, MPY0, FSUW1, FSUW0, FWW1, and FWW0. Associated

read/write timings are illustrated in Figures 27.13 and 27.14, respectively.

Read/write cycle timing is selected from the tables below to meet the timing requirements in the CPU

rewrite mode described in the electrical characteristics.

Figure 27.13 Read Timing

Table 27.9 Read Cycle and Bit Settings: MPY1, MPY0, and FWR4 to FWR0, When Peripheral Bus

Clock is Divided by 2 (unit: cycles)

FWR3 to FWR0

Bit Settings

FWR4

Bit

Settings

MPY1 and MPY0 Bit Settings

10b 11b

mpy = 3 mpy = 4

tsu(S-R),

tsu(A-R) tw(R) tcRth(R-S),

th(R-A)

tsu(S-R),

tsu(A-R) tw(R) tcRth(R-S),

th(R-A)

0000b wr = 1 0 43406560

1 65606560

0001b wr = 2 0 8 7 8 0109100

1 8 7 8 0109100

0101b wr = 3 0 1091001413140

1 12 11 12 0 14 13 14 0

0110b wr = 4 0 14 13 14 0 18 17 18 0

1 14 13 14 0 18 17 18 0

1010b wr = 5 0 16 15 16 0 22 21 22 0

1 18 17 18 0 22 21 22 0

1011b wr = 6 0 20 19 20 0 26 25 26 0

1 20 19 20 0 26 25 26 0

1111b wr = 7 0 22 21 22 0 30 29 30 0

1 24 23 24 0 30 29 30 0

Chip select

Address

h(R-S)

w(R)

su(S-R)

h(R-A)

su(A-R)

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R32C/117 Group 27. Flash Memory

Table 27.10 Read Cycle and Bit Settings: MPY1, MPY0, and FWR4 to FWR0, When Peripheral Bus

Clock is Divided by 3 (unit: cycles)

FWR3 to FWR0

Bit Settings

FWR4

Bit

Settings

MPY1 and MPY0 Bit Settings

10b 11b

mpy = 3 mpy = 4

tsu(S-R),

tsu(A-R) tw(R) tcRth(R-S),

th(R-A)

tsu(S-R),

tsu(A-R) tw(R) tcRth(R-S),

th(R-A)

0000b wr = 1 0 6 4.5 6 0 6 4.5 6 0

1 6 4.5 6 0 6 4.5 6 0

0001b wr = 2 0 9 7.5 9 0 9 7.5 9 0

1 9 7.5 9 0 12 10.5 12 0

0101b wr = 3 0 12 10.5 12 0 15 13.5 15 0

1 12 10.5 12 0 15 13.5 15 0

0110b wr = 4 0 15 13.5 15 0 18 16.5 18 0

1 15 13.5 15 0 18 16.5 18 0

1010b wr = 5 0 18 16.5 18 0 21 19.5 21 0

1 18 16.5 18 0 24 22.5 24 0

1011b wr = 6 0 21 19.5 21 0 27 25.5 27 0

1 21 19.5 21 0 27 25.5 27 0

1111b wr = 7 0 24 22.5 24 0 30 28.5 30 0

1 24 22.5 24 0 30 28.5 30 0

Table 27.11 Read Cycle and Bit Settings: MPY1, MPY0, and FWR4 to FWR0, When Peripheral Bus

Clock is Divided by 4 (unit: cycles)

FWR3 to FWR0

Bit Settings

FWR4

Bit

Settings

MPY1 and MPY0 Bit Settings

10b 11b

mpy = 3 mpy = 4

tsu(S-R),

tsu(A-R) tw(R) tcRth(R-S),

th(R-A)

tsu(S-R),

tsu(A-R) tw(R) tcRth(R-S),

th(R-A)

0000b wr = 1 0 42408680

1 86808680

0001b wr = 2 0 8 6 8 01210120

1 8 6 8 01210120

0101b wr = 3 0 12 10 12 0 16 14 16 0

1 12 10 12 0 16 14 16 0

0110b wr = 4 0 16 14 16 0 20 18 20 0

1 16 14 16 0 20 18 20 0

1010b wr = 5 0 16 14 16 0 24 22 24 0

1 20 18 20 0 24 22 24 0

1011b wr = 6 0 20 18 20 0 28 26 28 0

1 20 18 20 0 28 26 28 0

1111b wr = 7 0 24 22 24 0 32 30 32 0

1 24 22 24 0 32 30 32 0

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R32C/117 Group 27. Flash Memory

Figure 27.14 Write Timing

Table 27.12 Write Cycle and Bit Settings: MPY1, MPY0, FSUW1, FSUW0, FWW1, and FWW0, When

Peripheral Bus Clock is Divided by 2 (unit: cycles)

FSUW1 and

FSUW0

Bit Settings

FWW1 and

FWW0

Bit Settings

MPY1 and MPY0 Bit Settings

10b 11b

mpy = 3 mpy = 4

tsu(S-W),

tsu(A-W) tw(W) tcWth(W-S),

th(W-A)

tsu(S-W),

tsu(A-W) tw(W) tcWth(W-S),

th(W-A)

00b suw = 0

00b ww = 1 13621461

01b ww = 2 168118101

10b ww = 3 1 9 12 2 1 12 14 1

11b ww = 4 112141 116181

01b suw = 1

00b ww = 1 438154101

01b ww = 2 4612258141

10b ww = 3 4 9 14 1 5 12 18 1

11b ww = 4 412182 516221

10b suw = 2

00b ww = 1 7312294141

01b ww = 2 7614198181

10b ww = 3 7 9 18 2 9 12 22 1

11b ww = 4 712201 916261

11b suw = 3

00b ww = 1 10 314113 4181

01b ww = 2 10 618213 8221

10b ww = 3 10 9 20 1 13 12 26 1

11b ww = 4 10 12 24 2 13 16 30 1

Chip select

Address

h(W-S)

w(W)

su(S-W)

h(W-A)

su(A-W)

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R32C/117 Group 27. Flash Memory

Table 27.13 Write Cycle and Bit Settings: MPY1, MPY0, FSUW1, FSUW0, FWW1, and FWW0, When

Peripheral Bus Clock is Divided by 3 (unit: cycles)

FSUW1 and

FSUW0

Bit Settings

FWW1 and

FWW0

Bit Settings

MPY1 and MPY0 Bit Settings

10b 11b

mpy = 3 mpy = 4

tsu(S-W),

tsu(A-W) tw(W) tcWth(W-S),

th(W-A)

tsu(S-W),

tsu(A-W) tw(W) tcWth(W-S),

th(W-A)

00b suw = 0

00b ww = 1 13621461

01b ww = 2 169218123

10b ww = 3 19122112152

11b ww = 4 112152 116181

01b suw = 1

00b ww = 1 439263123

01b ww = 2 4612267152

10b ww = 3 49152611181

11b ww = 4 412182 615243

10b suw = 2

00b ww = 1 7312294152

01b ww = 2 7615298181

10b ww = 3 79182912243

11b ww = 4 712212 916272

11b suw = 3

00b ww = 1 10 3 15 2 13 4 18 1

01b ww = 2 10 6 18 2 13 8 24 3

10b ww = 3 10 9 21 2 13 12 27 2

11b ww = 4 10 12 24 2 13 16 30 1

Table 27.14 Write Cycle and Bit Settings: MPY1, MPY0, FSUW1, FSUW0, FWW1, and FWW0, When

Peripheral Bus Clock is Divided by 4 (unit: cycles)

FSUW1 and

FSUW0

Bit Settings

FWW1 and

FWW0

Bit Settings

MPY1 and MPY0 Bit Settings

10b 11b

mpy = 3 mpy = 4

tsu(S-W),

tsu(A-W) tw(W) tcWth(W-S),

th(W-A)

tsu(S-W),

tsu(A-W) tw(W) tcWth(W-S),

th(W-A)

00b suw = 0

00b ww = 1 13841483

01b ww = 2 168118123

10b ww = 3 1 9 12 2 1 12 16 3

11b ww = 4 112163 116203

01b suw = 1

00b ww = 1 438154123

01b ww = 2 4612258163

10b ww = 3 4 9 16 3 5 12 20 3

11b ww = 4 412204 516243

10b suw = 2

00b ww = 1 8212294163

01b ww = 2 8516398203

10b ww = 3 8 8 20 4 9 12 24 3

11b ww = 4 811201 916283

11b suw = 3

00b ww = 1 10 316313 4203

01b ww = 2 10 620413 8243

10b ww = 3 10 9 20 1 13 12 28 3

11b ww = 4 10 12 24 2 13 16 32 3

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R32C/117 Group 27. Flash Memory

27.3.3 Software Commands

In CPU rewrite mode, software commands enable program and erase operations for the flash memory.

Writing commands and reading/writing data should be performed in 16-bit units.

Table 27.15 lists the software commands.

WA: Even address to be written

WD: 16-bit data to be written

BA: Even address within a specific block

PBA: Protect bit address (refer to Table 27.4)

Notes:

1. This command cannot be executed in EW1 mode.

2. The program is performed in 64-bit (4-word) units. A sequence of commands consists of commands

from the second to fifth. The upper 29 bits of the address WA should be fixed and the lower 3 bits of

respective commands from the second to fifth should be set to 000b, 010b, 100b, and 110b for the

addresses 0h, 2h, 4h, and 6h, or 8h, Ah, Ch, and Eh.

3. This command should be executed in RAM.

Table 27.15 Software Commands

Command First Command Cycle Second Command Cycle

Address Data Address Data

Enter read array mode FFFFF800h 00FFh — —

Enter read status register mode (1) FFFFF800h 0070h — —

Clear status register FFFFF800h 0050h — —

Program (2) FFFFF800h 0043h WA WD

Block erase FFFFF800h 0020h BA 00D0h

Lock bit program FFFFF800h 0077h BA 00D0h

Read lock bit status FFFFF800h 0071h BA 00D0h

Enter read lock bit status mode (3) FFFFF800h 0071h — —

Protect bit program FFFFF800h 0067h PBA 00D0h

Enter read protect bit status mode (3) FFFFF800h 0061h — —

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R32C/117 Group 27. Flash Memory

27.3.4 Mode Transition

CPU rewrite mode supports four flash memory operating modes:

• Read array mode

• Read status register mode

• Read lock bit status mode

• Read protect bit status mode

When reading the flash memory in these modes, the memory data, the status register value, the state

of the lock bit in the read block, and the state of the protect bit are individually read. Details are listed in

Tables 27.16 to 27.18.

In these operating modes, program or erase operation can be performed by software commands. After

an operation is completed, the flash memory module automatically enters read array mode (in EW1

mode) or read status register mode (in EW0 mode).

Table 27.16 Status Register

Bit Bit Symbol Bit Name Definition

b15-b8 — Disabled bit — —

b7 SR7 Sequencer status BUSY READY

b6 — Reserved bit — —

b5 SR5 Erase status Successfully

completed Error

b4 SR4 Program status Successfully

completed Error

b3 — Reserved bit — —

b2 — Reserved bit — —

b1 — Reserved bit — —

b0 — Reserved bit — —

Table 27.17 Lock Bit Status

Bit Bit Symbol Bit Name Definition

b15-b7 — Disabled bit — —

b6 LBS Lock bit status Locked Unlocked

b5-b0 — Disabled bit — —

Table 27.18 Protect Bit Status

Bit Bit Symbol Bit Name Definition

b15-b7 — Disabled bit — —

b6 PBS Protect bit status Protected Unprotected

b5-b0 — Disabled bit — —

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R32C/117 Group 27. Flash Memory

27.3.5 Issuing Software Commands

This section describes how to issue software commands.

These commands should be issued while the RDY bit in the FMSR0 register is 1 (ready).

27.3.5.1 Enter Read Array Mode Command

Execute this command to enter read array mode.

When 00FFh is written to address FFFFF800h, the flash memory enters read array mode. In this mode,

the value stored to a given address in memory can be read.

In EW1 mode, the flash memory is always in read array mode.

27.3.5.2 Enter Read Status Register Mode

Execute this command to enter read status register mode.

When 0070h is written to address FFFFF800h, the status register value is read in any address of the

flash memory.

Do not issue this command in EW1 mode.

27.3.5.3 Clear Status Register

Execute this command to reset the status register in the flash memory.

When 0050h is written to address FFFFF800h, bits SR5 and SR4 in the status register become 0

(successfully completed) (refer to Table 27.16). Consequently, bits EERR and WERR in the FMSR0

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R32C/117 Group 27. Flash Memory

27.3.5.4 Program Command

Execute this command to program the flash memory in 8-byte (4-word) units.

To start automatic programming (program and program-verify operations), write 0043h to address

FFFFF800h, then write data to addresses 8n + 0 to 8n + 6. Verify that the FCA bit in the FMR0 register

is 0 just before executing the final command.

To monitor the automatic program operation, read the RDY bit in the FMSR0 register. This bit becomes

0 (busy) when the operation is in progress and 1 (ready) when the operation is completed.

The operation result can be verified by the WERR bit in the FMSR0 register (refer to 27.3.6 “Status

Check”).

Do not write additional data to an address that is already programmed.

Figure 27.15 Program Command Execution Flowchart

Program

Write command 0043h to address FFFFF800h

Write corresponding data to address 8n + 0

Write corresponding data to address 8n + 2

Write corresponding data to address 8n + 4

Write corresponding data to address 8n + 6

RDY bit in the FMSR0 register is 1?

Check status

End

Yes

FCA bit in the FMR0 register is 0? No

Yes

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R32C/117 Group 27. Flash Memory

27.3.5.5 Block Erase Command

Execute this command to erase a specified block in the flash memory.

To start automatic erasing of a specified block (erase and erase-verify operations), write 0020h to

address FFFFF800h, verify that the FCA bit in the FMR0 register is 0, then write 00D0h to an even

address in the corresponding block.

To monitor the automatic erase operation, read the RDY bit in the FMSR0 register. This bit becomes 0

(busy) when the operation is in progress and 1 (ready) when the operation is completed.

The operation result can be verified by the EERR bit in the FMSR0 register (refer to 27.3.6 “Status

Check”).

Figure 27.16 Block Erase Command Execution Flowchart

Block erase

Write the first command 0020h to address FFFFF800h

Write the second command 00D0h to an even address

in the corresponding block

RDY bit in the FMSR0 register is 1?

Check status

End

Yes

FCA bit in the FMR0 register is 0? No

Yes

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R32C/117 Group 27. Flash Memory

27.3.5.6 Lock Bit Program Command

Execute this command to lock a specified block in the flash memory.

To lock the block, write 0077h to address FFFFF800h, verify that the FCA bit in the FMR0 register is 0,

then write 00D0h to an even address in the corresponding block. Then the lock bit of the block

becomes 0 (locked).

To monitor the lock bit program, read the RDY bit in the FMSR0 register. This bit becomes 0 (busy)

when the operation is in progress and 1 (ready) when the operation is completed.

The state of the lock bit can be verified by the read lock bit status command if the LBM bit in the FMR0

0 (read via data bus), enter read lock bit status mode (refer to 27.3.5.8 “Enter Read Lock Bit Status

Mode Command”).

Figure 27.17 Lock Bit Program Command Execution Flowchart

Lock bit program

Write the first command 0077h to address FFFFF800h

Write the second command 00D0h to an even address

in the corresponding block

RDY bit in the FMSR0 register is 1?

Check status

End

Yes

FCA bit in the FMR0 register is 0? No

Yes

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R32C/117 Group 27. Flash Memory

27.3.5.7 Read Lock Bit Status Command

Execute this command to verify if a specified block in the flash memory is locked. This command can

be used when the LBM bit in the FMR0 register is 1 (read by the LBS bit).

The LBS bit in the FMSR0 register reflects the lock bit status of the specified block when the following is

performed: first write 0071h to address FFFFF800h and verify that the FCA bit in the FMR0 register

becomes 0. Then write 00D0h to an even address of the corresponding block.

Read the LBS bit after the RDY bit in the FMSR0 register becomes 1 (ready).

Figure 27.18 Read Lock Bit Status Command Execution Flowchart

27.3.5.8 Enter Read Lock Bit Status Mode Command

Execute this command to enter read lock bit status mode. This command is enabled when the LBM bit

in the FMR0 register is 0 (read via data bus).

To read the lock bit status of the read block, write 0071h to address FFFFF800h (refer to Table 27.17).

The status is read in any address of the flash memory.

Execute this command in RAM.

Read lock bit status

Write the first command 0071h to address FFFFF800h

Write the second command 00D0h to an even address

in the corresponding block

RDY bit in the FMSR0 register is 1?

End

Yes

Read LBS bit in the FMR0 register

FCA bit in the FMR0 register is 0? No

Yes

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R32C/117 Group 27. Flash Memory

27.3.5.9 Protect Bit Program Command

Execute this command to protect a specific block in the flash memory. ROM code protection is enabled

by setting one of the protect bits of the block to 0.

To set the protect bit of the designated block to 0 (protected), write 0067h to address FFFFF800h, verify

that the FCA bit in the FMR0 register is 0, and then write 00D0h to the protect bit of the corresponding

block (refer to Table 27.4).

To monitor the protect bit program, read the RDY bit in the FMSR0 register. This bit becomes 0 (busy)

when the operation is in progress and 1 (ready) when the operation is completed.

To verify the state of protect bit, enter read protect bit status mode (refer to 27.3.5.10 “Enter Read

Protect Bit Status Mode Command”), then read the flash memory.

Figure 27.19 Protect Bit Program Command Execution Flowchart

27.3.5.10 Enter Read Protect Bit Status Mode Command

Execute this command to enter read protect bit status mode.

To read the protect bit status of the read block, write 0061h to address FFFFF800h (refer to Table

27.18). The status is read from any address in the flash memory.

Execute this command in RAM.

Protect bit program

Write the first command 0067h to address FFFFF800h

Write the second command 00D0h to the corresponding bit

address

RDY bit in the FMSR0 register is 1?

Check status

End

Yes

FCA bit in the FMR0 register is 0? No

Yes

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R32C/117 Group 27. Flash Memory

27.3.6 Status Check

To verify if a software command is successfully executed, read the EERR or WERR bit in the FMSR0

Table 27.19 lists status and errors indicated by these bits and Figure 27.20 shows the flowchart of the

status check.

Figure 27.20 Status Check Flowchart

When an error occurs, execute the clear status register command and then handle the error.

If erase errors or program errors occur frequently even though the program is correct, the corresponding

block may be disabled.

Table 27.19 Status and Errors

FMSR0 Register

(Status Register) Error Source of Error

EERR bit

(SR5 bit)

WERR bit

(SR4 bit)

Command sequence error • Data other than 00D0h or 00FFh (command to

cancel) was written as the last command of two

commands

• An unavailable address was specified by an

address specifying command

Erase error • Attempted to erase a locked block

• Corresponding block was not erased properly

Program error • Attempted to program a locked block

• Data was not programmed properly

• Lock bit was not programmed properly

• Protect bit was not programmed properly

00No error

Check status

WERR bit in the FMSR0 is 1?

No error

Yes No

EERR bit in the FMSR0 is 1?

WERR bit in the FMSR0 is 1?

Yes YesNo No

Program errorErase errorCommand sequence error

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R32C/117 Group 27. Flash Memory

27.4 Standard Serial I/O Mode

In standard serial I/O mode, an R32C/117 Group compatible serial programmer can be used to rewrite the

flash memory while the MCU is mounted on a board.

For further information on the serial programmer, contact your serial programmer manufacturer and refer

to the user’s manual included with the serial programmer for instructions.

As shown in Table 27.20, this mode provides two types of transmit/receive mode: Standard serial I/O

mode 1 which uses a synchronous serial interface, and standard serial I/O mode 2 which uses UART.

Table 27.21 lists the pin definitions and functions in standard serial I/O mode. Figures 27.21 and 27.22

show examples of a circuit application in standard serial I/O modes 1 and 2, respectively. Refer to the

serial programmer user manual to handle pins controlled by the serial programmer.

Table 27.20 Standard Serial I/O Mode Specifications

Item Standard Serial I/O Mode 1 Standard Serial I/O Mode 2

Transmit/receive mode Synchronous serial I/O UART

Transmit/receive bit rate High Low

Serial interface to be used UART1 UART1

Pin settings CNVSS High High

CE (P5_0) High High

EPM (P5_5) Low Low

SCLK (P6_5) In reset: Low

In transmission/reception:

Transmit/receive clock

In reset: Low

In transmission/reception: Unused

Pin functions

BUSY (P6_4) BUSY signal Monitor to check program

operation

RXD (P6_6) Serial data input Serial data input

TXD (P6_7) Serial data output Serial data output

R01UH0211EJ0120 Rev.1.20 Page 537 of 604

Feb 18, 2013

R32C/117 Group 27. Flash Memory

Note:

1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only.

Table 27.21 Pin Definitions and Functions in Standard Serial I/O Mode

Pin Name Function I/O Description

VCC, VSS Power supply input IApplicable as follows: VCC = guaranteed voltage for program/

erase operations, VSS = 0 V

VDC1, VDC0 Connecting pins for

decoupling

capacitor

—

A decoupling capacitor for internal voltage should be connected

between VDC0 and VDC1

CNVSS CNVSS I This pin should be connected to VCC via a resistor

RESET Reset input IReset input pin. While the RESET pin is driven low, at least 20

clock cycles should be input at the XIN pin

XIN Main clock input I A ceramic resonator or a crystal oscillator should be connected

between pins XIN and XOUT. An external clock should be input at

XIN while leaving XOUT open

XOUT Main clock output O

NSD Debug port I/O This pin should be connected to VCC via a resistor of 1 to 4.7 k

AVCC, AVSS Analog power

supply IAVCC and AVSS should be connected to VCC and VSS,

respectively

VREF Reference voltage

input IReference voltage input for the A/D converter and D/A converter

P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_7,

P3_0 to P3_7,

P4_0 to P4_7

Input port

High or low should be input, or the ports should be left open

P5_0 CE input I High should be input

P5_1 to P5_4 Input port I High or low should be input, or the ports should be left open

P5_5 EPM input I Low should be input

P5_6, P5_7,

P6_0 to P6_3

Input port IHigh or low should be input, or the ports should be left open

P6_4 BUSY output OStandard serial I/O mode 1: BUSY output pin

Standard serial I/O mode 2: Program operation monitor

P6_5 SCLK input IStandard serial I/O mode 1: Serial clock input pin

Standard serial I/O mode 2: Low should be input

P6_6 Data input RXD I Serial data input pin

P6_7 Data output TXD O Serial data output pin

P7_0 to P7_7,

P8_0 to P8_4

Input port IHigh or low should be input, or the ports should be left open

P8_5 NMI input I This pin should be connected to VCC via a resistor

P8_6, P8_7,

P9_0 to P9_7,

P10_0 to P10_7,

P11_0 to P11_4,

P12_0 to P12_7,

P13_0 to P13_7,

P14_1,

P14_3 to P14_6,

P15_0 to P15_7

(1)

Input port

High or low should be input, or the ports should be left open

R01UH0211EJ0120 Rev.1.20 Page 538 of 604

Feb 18, 2013

R32C/117 Group 27. Flash Memory

Figure 27.21 Circuit Application in Standard Serial I/O Mode 1

MCU

SCLK (P6_5)

TXD (P6_7)

RXD (P6_6)

BUSY (P6_4)

RESET

CE (P5_0)

EPM (P5_5)

CNVSS

NMI

BUSY output

Clock input

Data input

Data output

VCC VCC

VCC

Reset input

User reset signal

VCC

Notes:

1. Control pins and external circuitry vary with the serial programmer. Refer to the user’s manual included with

the serial programmer.

2. In this example, a selector controls the voltage applied to the CNVSS pin to switch between single-chip

mode and standard serial I/O mode 1.

3. If the user reset signal becomes low while the MCU is communicating with the serial programmer, cut off the

connection between the user reset signal and the RESET pin by, for example, a jumper selector.

R01UH0211EJ0120 Rev.1.20 Page 539 of 604

Feb 18, 2013

R32C/117 Group 27. Flash Memory

Figure 27.22 Circuit Application in Standard Serial I/O Mode 2

27.5 Parallel I/O mode

In parallel I/O mode, an R32C/117 Group compatible parallel programmer can be used to rewrite the flash

memory.

For further information on the parallel programmer, contact your parallel programmer manufacturer and

refer to the user’s manual included with your parallel programmer for instructions.

MCU

SCLK (P6_5)

TXD (P6_7)

RXD (P6_6)

BUSY (P6_4)

RESET

CE (P5_0)

EPM (P5_5)

CNVSS

NMI

Monitor output

Data input

Data output

VCC

Notes:

1. Control pins and external circuitry vary with the serial programmer. Refer to the user’s manual included with

the serial programmer.

2. In this example, a selector controls the voltage applied to the CNVSS pin to switch between single-chip

mode and standard serial I/O mode 2.

3. If the user reset signal becomes low while the MCU is communicating with the serial programmer, cut off the

connection between the user reset signal and the RESET pin by, for example, a jumper selector.

User reset signal

R01UH0211EJ0120 Rev.1.20 Page 540 of 604

Feb 18, 2013

R32C/117 Group 27. Flash Memory

27.6 Notes on Flash Memory Rewriting

27.6.1 Note on Power Supply

• Keep the supply voltage constant within the range specified in the electrical characteristics while a

rewrite operation on the flash memory is in progress. If the supply voltage goes beyond the

guaranteed value, the device cannot be guaranteed.

27.6.2 Note on Hardware Reset

• Do not perform a hardware reset while a rewrite operation on the flash memory is in progress.

27.6.3 Note on Flash Memory Protection

• If an ID code written in an assigned address has an error, any read/write operation on the flash

memory in standard serial I/O mode is disabled.

27.6.4 Notes on Programming

• Do not set the FEW bit in the FMCR register to 1 (CPU rewrite mode) in low speed mode or low

power mode.

• The program, block erase, lock bit program, and protect bit program are interrupted by an NMI, a

watchdog timer interrupt, an oscillator stop detection interrupt, or a low voltage detection interrupt.

If any of the software commands above are interrupted, erase the corresponding block and then

execute the same command again. If the block erase command is interrupted, the lock bit and

protect bit values become undefined. Therefore, disable the lock bit, and then execute the block

erase command again.

27.6.5 Notes on Interrupts

• EW0 mode

• To use interrupts assigned to the relocatable vector table, the vector table should be addressed in

RAM space.

• When an NMI, watchdog timer interrupt, oscillator stop detection interrupt, or low voltage detection

interrupt occurs, the flash memory module automatically enters read array mode. Therefore, these

interrupts are enabled even during a rewrite operation. However, the rewrite operation in progress

is aborted by the interrupts and registers FMR0 and FRSR0 are reset. When the interrupt handler

has ended, set the LBD bit in the FMR1 register to 1 (lock bit protection disabled) to re-execute the

rewrite operation.

• Instructions BRK, INTO, and UND, which refer to data on the flash memory, cannot be used in this

mode.

• EW1 mode

• Interrupts assigned to the relocatable vector table should not be accepted during program or block

erase operation.

• The watchdog timer interrupt should not be generated.

• When an NMI, watchdog timer interrupt, oscillator stop detection interrupt, or low voltage detection

interrupt occurs, the flash memory module automatically enters read array mode. Therefore, these

interrupts are enabled even during a rewrite operation. However, the rewrite operation in progress

is aborted by the interrupts and registers FMR0 and FRSR0 are reset. When the interrupt handler

has ended, set the EWM bit in the FMR0 register to 1 (EW1 mode) and the LBD bit in the FMR1

R01UH0211EJ0120 Rev.1.20 Page 541 of 604

Feb 18, 2013

R32C/117 Group 27. Flash Memory

27.6.6 Notes on Rewrite Control Program

• EW0 mode

• If the supply voltage drops during the rewrite operation of blocks having the rewrite control

program, the rewrite control program may not be successfully rewritten, and the rewrite operation

itself may not be performed. In this case, perform the rewrite operation by serial programmer or

parallel programmer.

• EW1 mode

• Do not rewrite blocks having the rewrite control program.

27.6.7 Notes on Number of Program/Erase Cycles and Software Command

Execution Time

• The time to execute software commands (program, block erase, lock bit program, and protect bit

program) increases as the number of program/erase cycles increases. If the number of program/

erase cycles exceeds the endurance value specified in the electrical characteristics, it may take an

unpredictable amount of time to execute the software commands. The wait time for executing

software commands should be set much longer than the execution time specified in the electrical

characteristics.

27.6.8 Other Notes

• The minimum values of program/erase cycles specified in the electrical characteristics are the

maximum values that can guarantee the initial performance of the flash memory. The program/

erase operation may still be performed even if the number of program/erase cycles exceeds the

guaranteed values.

• Chips repeatedly programmed and erased for debugging should not be used for commercial

products.

R01UH0211EJ0120 Rev.1.20 Page 542 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

28. Electrical Characteristics

Notes:

1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

Table 28.1 Absolute Maximum Ratings (1)

Symbol Characteristic Condition Value Unit

VCC Supply voltage VCC = AVCC -0.3 to 6.0 V

AVCC Analog supply voltage VCC = AVCC -0.3 to 6.0 V

VIInput

voltage

XIN, RESET, CNVSS, NSD, VREF

P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P5_0 to P5_3, P8_4 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0toP11_4, P12_0toP12_7,

P13_0 to P13_7, P14_1,

P14_3 to P14_6, P15_0 to P15_7 (2)

-0.3 to VCC + 0.3 V

P4_0 to P4_7, P5_4 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_3

-0.3 to 6.0 V

VOOutput

voltage

XOUT, P0_0 to P0_7, P1_0 to P1_7,

P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0toP11_4, P12_0toP12_7,

P13_0 to P13_7, P14_3 to P14_6,

P15_0 to P15_7 (2)

-0.3 to VCC + 0.3 V

PdPower consumption Ta = 25°C 500 mW

— Operating temperature range -40 to 85 °C

Tstg Storage temperature range -65 to 150 °C

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R32C/117 Group 28. Electrical Characteristics

Notes:

1. The device is operationally guaranteed under these operating conditions.

2. VIH and VIL for P8_7 are specified for P8_7 as a programmable port. These values are not applicable

for P8_7 as XCIN.

3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

Table 28.2 Operating Conditions (1/5) (1)

Symbol Characteristic Value Unit

Min. Typ. Max.

VCC Digital supply voltage 3.0 5.0 5.5 V

AVCC Analog supply voltage VCC V

VREF Reference voltage 3.0 VCC V

VSS Digital ground voltage 0V

AVSS Analog ground voltage 0V

dVCC/dt VCC ramp up rate (VCC < 2.0 V) 0.05 V/ms

VIH High level

input

voltage

XIN, RESET, CNVSS, NSD, P2_0 to P2_7,

P3_0 to P3_7, P5_0 to P5_3, P8_4 to P8_7 (2),

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P14_1, P14_3 to P14_6,

P15_0 to P15_7 (3)

0.8 × VCC VCC V

P4_0 to P4_7, P5_4 to P5_7, P6_0 to P6_7,

P7_0 to P7_7, P8_0 to P8_3 0.8 × VCC 6.0 V

P0_0 to P0_7,

P1_0 to P1_7,

P12_0 to P12_7,

P13_0 to P13_7

(3)

in single-chip mode 0.8 × VCC VCC V

in memory expansion mode

or microprocessor mode 0.5 × VCC VCC V

VIL Low level

input

voltage

XIN, RESET, CNVSS, NSD, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7 (2),

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P14_1, P14_3 to P14_6,

P15_0 to P15_7 (3)

00.2 × VCC V

P0_0 to P0_7,

P1_0 to P1_7,

P12_0 to P12_7,

P13_0 to P13_7

(3)

in single-chip mode 00.2 × VCC V

in memory expansion mode

or microprocessor mode 00.16 × VCC V

Topr Operating

temperature

range

N version -20 85 °C

D version -40 85 °C

P version -40 85 °C

R01UH0211EJ0120 Rev.1.20 Page 544 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Notes:

1. The device is operationally guaranteed under these operating conditions.

2. This value should be met with due consideration to the following conditions: operating temperature,

DC bias, aging, etc.

Table 28.3 Operating Conditions (2/5)

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted) (1)

Symbol Characteristic Value (2)

Unit

Min. Typ. Max.

CVDC Decoupling capacitance for voltage

regulator

Inter-pin voltage: 1.5 V 2.4 10.0 µF

R01UH0211EJ0120 Rev.1.20 Page 545 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Notes:

1. The device is operationally guaranteed under these operating conditions.

2. The following conditions should be satisfied:

• The sum of IOL(peak) of ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 is 80 mA or less.

• The sum of IOL(peak) of ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 is 80 mA or less.

• The sum of IOH(peak) of ports P0, P1, P2, and P11 is -40 mA or less.

• The sum of IOH(peak) of ports P8_6, P8_7, P9, P10, P14, and P15 is -40 mA or less.

• The sum of IOH(peak) of ports P3, P4, P5, P12, and P13 is -40 mA or less.

• The sum of IOH(peak) of ports P6, P7, and P8_0 to P8_4 is -40 mA or less.

3. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

4. Average value within 100 ms.

Table 28.4 Operating Conditions (3/5)

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted) (1)

Symbol Characteristic Value Unit

Min. Typ. Max.

IOH(peak) High level

peak

output

current (2)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (3)

-10.0 mA

IOH(avg) High level

average

output

current (4)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (3)

-5.0 mA

IOL(peak) Low level

peak

output

current (2)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (3)

10.0 mA

IOL(avg) Low level

average

output

current (4)

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (3)

5.0 mA

R01UH0211EJ0120 Rev.1.20 Page 546 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Note:

1. The device is operationally guaranteed under these operating conditions.

Figure 28.1 Clock Cycle Time

Table 28.5 Operating Conditions (4/5)

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted) (1)

Symbol Characteristic Value Unit

Min. Typ. Max.

f(XIN) Main clock oscillator frequency 416MHz

f(XRef) Reference clock frequency 24MHz

f(PLL) PLL clock oscillator frequency 96 128 MHz

f(Base) Base clock frequency High speed version 64 MHz

Normal speed version 50 MHz

tc(Base) Base clock cycle time High speed version 15.625 ns

Normal speed version 20 ns

f(CPU) CPU operating frequency High speed version 64 MHz

Normal speed version 50 MHz

tc(CPU) CPU clock cycle time High speed version 15.625 ns

Normal speed version 20 ns

f(BCLK) Peripheral bus clock operating

frequency

High speed version 32 MHz

Normal speed version 25 MHz

tc(BCLK) Peripheral bus clock cycle time High speed version 31.25 ns

Normal speed version 40 ns

f(PER) Peripheral clock source frequency 32 MHz

f(XCIN) Sub clock oscillator frequency 32.768 62.5 kHz

Base clock

(internal signal)

c(Base)

Peripheral bus clock

(internal signal)

c(BCLK)

CPU clock

(internal signal)

c(CPU)

R01UH0211EJ0120 Rev.1.20 Page 547 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Note:

1. The device is operationally guaranteed under these operating conditions.

Figure 28.2 Ripple Waveform

Table 28.6 Operating Conditions (5/5)

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted) (1)

Symbol Characteristic Value Unit

Min. Typ. Max.

Vr(VCC) Allowable ripple voltage VCC = 5.0 V 0.5 Vp-p

VCC = 3.0 V 0.3 Vp-p

dVr(VCC)/dt Ripple voltage gradient VCC = 5.0 V ±0.3 V/ms

VCC = 3.0 V ±0.3 V/ms

fr(VCC) Allowable ripple frequency 10 kHz

VCC

1 / fr(VCC)

Vr(VCC)

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Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Notes:

1. Program/erase definition

This value represents the number of erasures per block.

When the number of program/erase cycles is n, each block can be erased n times.

For example, if a 4-word write is performed in 512 different addresses in the 4-Kbyte block A and

then the block is erased, this is counted as a single program/erase operation.

However, the same address cannot be written to more than once per erasure (overwrite disabled).

2. Data retention includes periods when no supply voltage is applied and no clock is provided.

3. Contact a Renesas Electronics sales office for data retention times other than the above condition.

Table 28.7 Electrical Characteristics of RAM

(VCC = 3.0 to 5.5 V, VSS =0V, and Ta=T

opr, unless otherwise noted)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Typ. Max.

VRDR RAM data retention voltage In stop mode 2.0 V

Table 28.8 Electrical Characteristics of Flash Memory

(VCC = 3.0 to 5.5 V, VSS =0V, and Ta=T

opr, unless otherwise noted)

Symbol Characteristic Value Unit

Min. Typ. Max.

—Program/erase cycles (1) Program area 1000 Cycles

Data area 10000 Cycles

— 4-word program time Program area 150 900 µs

Data area 300 1700 µs

— Lock bit program time Program area 70 500 µs

Data area 140 1000 µs

— Block erasure time 4-Kbyte block 0.12 3.0 s

32-Kbyte block 0.17 3.0 s

64-Kbyte block 0.20 3.0 s

—Data retention (2) Ta = 55°C (3) 10 Years

R01UH0211EJ0120 Rev.1.20 Page 549 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Figure 28.3 Power Supply Circuit Timing

Table 28.9 Power Supply Circuit Timing Characteristics

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Typ. Max.

td(P-R) Internal power supply start-up stabilization

time after the main power supply is turned on 2ms

Table 28.10 Electrical Characteristics of Voltage Regulator for Internal Logic

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Symbol Characteristics Measurement

Condition

Value Unit

Min. Typ. Max.

VVDC1 Output voltage 1.5 V

Table 28.11 Electrical Characteristics of Low Voltage Detector

(VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Symbol Characteristics Measurement

Condition

Value Unit

Min. Typ. Max.

Vdet Detected voltage error ±0.3 V

Vdet(R)-Vdet(F) Hysteresis width 0 V

—Self-consuming current VCC = 5.0 V, low voltage

detector enabled 4µA

td(E-A) Operation start time of low voltage detector 150 µs

d(P-R)

VCC

PLL oscillator-

output waveform

Internal power supply start-up

stabilization time after the main

power supply is turned on

Recommended

operating voltage

d(P-R)

Supply voltage for

internal logic

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R32C/117 Group 28. Electrical Characteristics

Note:

1. This value is applicable only when the main clock oscillation is stable.

Note:

1. The recovery time from stop mode does not include the main clock oscillation stabilization time. The

CPU starts operating before the oscillator is stabilized.

Figure 28.4 Clock Circuit Timing

Table 28.12 Electrical Characteristics of Oscillator

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Symbol Characteristics Measurement

Condition

Value Unit

Min. Typ. Max.

fSO(PLL) PLL clock self-oscillation frequency 35 50 65 MHz

tLOCK(PLL) PLL lock time (1) 1ms

tjitter(p-p) PLL jitter period (p-p) 2.0 ns

f(OCO) On-chip oscillator frequency 62.5 125 250 kHz

Table 28.13 Electrical Characteristics of Clock Circuitry

(VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Symbol Characteristics Measurement

Condition

Value Unit

Min. Typ. Max.

trec(WAIT) Recovery time from wait mode to low power mode 225 µs

trec(STOP) Recovery time from stop mode (1) 225 µs

rec(STOP)

Interrupt for exiting

stop mode

CPU clock

Main clock oscillator

output

On-chip oscillator

output

Sub clock oscillator

output

On-chip oscillator

output

rec(WAIT)

Interrupt for exiting

wait mode

CPU clock

Recovery time from stop mode

rec(STOP)

Recovery time from wait mode

to low power mode

rec(WAIT)

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R32C/117 Group 28. Electrical Characteristics

Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted)

Figure 28.5 Flash Memory CPU Rewrite Mode Timing

Table 28.14 Flash Memory CPU Rewrite Mode Timing

Symbol Characteristics Value Unit

Min. Max.

tcR Read cycle time 200 ns

tsu(S-R) Chip-select setup time before read 200 ns

th(R-S) Chip-select hold time after read 0ns

tsu(A-R) Address setup time before read 200 ns

th(R-A) Address hold time after read 0ns

tw(R) Read pulse width 100 ns

tcW Write cycle time 200 ns

tsu(S-W) Chip-select setup time before write 0ns

th(W-S) Chip-select hold time after write 30 ns

tsu(A-W) Address setup time before write 0ns

th(W-A) Address hold time after write 30 ns

tw(W) Write pulse width 50 ns

Chip select

Address

h(R-S)

Read cycle

w(R)

su(S-R)

h(R-A)

su(A-R)

Write cycle

Chip select

Address

h(W-S)

w(W)

su(S-W)

h(W-A)

su(A-W)

R01UH0211EJ0120 Rev.1.20 Page 552 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Note:

1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

Table 28.15 Electrical Characteristics (1/3)

(VCC = 4.2 to 5.5 V, VSS =0V, T

a=T

opr, and f(CPU) = 64 MHz, unless otherwise noted)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Typ. Max.

VOH High

level

output

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0toP10_7, P11_0toP11_4,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (1)

IOH = -5 mA VCC - 2.0 VCC V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0toP10_7, P11_0toP11_4,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (1)

IOH = -200 µA VCC - 0.3 VCC V

VOL Low

level

output

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0toP10_7, P11_0toP11_4,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (1)

IOL = 5 mA 2.0 V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0toP10_7, P11_0toP11_4,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (1)

IOL = 200 µA 0.45 V

R01UH0211EJ0120 Rev.1.20 Page 553 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Notes:

1. Pins INT6 to INT8 are available in the 144-pin package only.

2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

Table 28.16 Electrical Characteristics (2/3)

(VCC = 4.2 to 5.5 V, VSS =0V, T

a=T

opr, and f(CPU) = 64 MHz, unless otherwise noted)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Typ. Max.

VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,

TA0IN to TA4IN, TA0OUT to TA4OUT,

TB0IN to TB5IN, CTS0 to CTS8,

CLK0 to CLK8, RXD0 to RXD8,

SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,

SRXD0 to SRXD6, ADTRG, IIO0_0 to IIO0_7,

IIO1_0 to IIO1_7, UD0A, UD0B, UD1A,

UD1B, ISCLK2, ISRXD2, IEIN, MSCL,

MSDA, CAN0IN, CAN0WU (1)

0.2 1.0 V

RESET 0.2 1.8 V

IIH High level

input

current

XIN, RESET, CNVSS, NSD,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

P15_0 to P15_7 (2)

VI = 5 V 5.0 µA

IIL Low level

input

current

XIN, RESET, CNVSS, NSD,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

P15_0 to P15_7 (2)

VI = 0 V -5.0 µA

RPULLUP Pull-up

resistor

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

P15_0 to P15_7 (2)

VI = 0 V 30 50 170 k

RfXIN Feedback

resistor

XIN 1.5 M

RfXCIN Feedback

resistor

XCIN 15 M

R01UH0211EJ0120 Rev.1.20 Page 554 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Table 28.17 Electrical Characteristics (3/3)

(VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Symbol Characterist

ic Measurement Condition Value Unit

Min. Typ. Max.

ICC Power supply

current

In single-chip mode,

output pins are left open

and others are

connected to VSS

XIN-XOUT

Drive strength: low

XCIN-XCOUT

Drive strength: low

f(CPU) =64MHz, f

(BCLK) =32MHz,

f(XIN) =8MHz,

Active: XIN, PLL,

Stopped: XCIN, OCO

45 60 mA

f(CPU) = 50 MHz, f(BCLK) = 25 MHz,

f(XIN) =8MHz,

Active: XIN, PLL,

Stopped: XCIN, OCO

35 50 mA

f(CPU) = fSO(PLL)/24 MHz,

Active: PLL (self-oscillation),

Stopped: XIN, XCIN, OCO

12 mA

f(CPU) = f(BCLK) = f(XIN)/256 MHz,

f(XIN) =8MHz,

Active: XIN,

Stopped: PLL, XCIN, OCO

1.2 mA

f(CPU) = f(BCLK) = 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown

220 µA

f(CPU) = f(BCLK) = f(OCO)/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown

230 µA

f(CPU) = f(BCLK) = f(XIN)/256 MHz,

f(XIN) =8MHz,

Active: XIN,

Stopped: PLL, XCIN, OCO,

Ta = 25°C, Wait mode

960 1600 µA

f(CPU) = f(BCLK) = 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown,

Ta = 25°C, Wait mode

8140µA

f(CPU) = f(BCLK) = f(OCO)/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown,

Ta = 25°C, Wait mode

10 150 µA

Stopped: all clocks,

Main regulator: shutdown,

Ta = 25°C

570µA

R01UH0211EJ0120 Rev.1.20 Page 555 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Note:

1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.

Table 28.18 A/D Conversion Characteristics (VCC =AV

CC =V

REF =4.2to5.5V, V

SS =AV

SS =0V,

Ta=T

opr, and f(BCLK) = 32 MHz, unless otherwise noted)

Symbol Characteristic Measurement Condition Value Unit

Min. Typ. Max.

—Resolution VREF = VCC 10 Bits

—

Absolute error VREF = VCC = 5 V AN_0toAN_7,

AN0_0toAN0_7,

AN2_0toAN2_7,

AN15_0 to AN15_7,

ANEX0, ANEX1 (1)

±3 LSB

External op-amp

connection mode ±7 LSB

INL Integral non-linearity

error

VREF = VCC = 5 V AN_0toAN_7,

AN0_0toAN0_7,

AN2_0toAN2_7,

AN15_0 to AN15_7,

ANEX0, ANEX1 (1)

±3 LSB

External op-amp

connection mode ±7 LSB

DNL Differential non-linearity

error ±1 LSB

—Offset error ±3 LSB

— Gain error ±3 LSB

RLADDER Resistor ladder VREF = VCC 420k

tCONV Conversion time

(10 bits)

AD = 16 MHz, with sample and hold

function 2.06 µs

AD = 16 MHz, without sample and hold

function 3.69 µs

tCONV Conversion time

(8 bits)

AD = 16 MHz, with sample and hold

function 1.75 µs

AD = 16 MHz, without sample and hold

function 3.06 µs

tSAMP Sampling time AD = 16 MHz 0.188 µs

VIA Analog input voltage 0VREF V

AD Operating clock

frequency

Without sample and hold function 0.25 16 MHz

With sample and hold function 1 16 MHz

R01UH0211EJ0120 Rev.1.20 Page 556 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Note:

1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The

resistor ladder for the A/D converter is not considered.

Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.

Table 28.19 D/A Conversion Characteristics (VCC =AV

CC =V

REF =4.2to5.5V, V

SS =AV

SS =0V,

and Ta=T

opr, unless otherwise noted)

Symbol Characteristic Measurement Condition Value Unit

Min. Typ. Max.

— Resolution 8Bits

— Absolute precision 1.0 %

tSSettling time 3µs

ROOutput resistance 41020k



IVREF Reference input current See Note 1 1.5 mA

R01UH0211EJ0120 Rev.1.20 Page 557 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Table 28.20 External Clock Input

Symbol Characteristic Value Unit

Min. Max.

tc(X) External clock input period 62.5 250 ns

tw(XH) External clock input high level pulse width 25 ns

tw(XL) External clock input low level pulse width 25 ns

tr(X) External clock input rise time 5ns

tf(X) External clock input fall time 5ns

tw / tcExternal clock input duty 40 60 %

Table 28.21 External Bus Timing

Symbol Characteristic Value Unit

Min. Max.

tsu(D-R) Data setup time before read 40 ns

th(R-D) Data hold time after read 0ns

tdis(R-D) Data disable time after read 0.5 × tc(Base) + 10 ns

R01UH0211EJ0120 Rev.1.20 Page 558 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Table 28.22 Timer A Input (counting input in event counter mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TA) TAiIN input clock cycle time 200 ns

tw(TAH) TAiIN input high level pulse width 80 ns

tw(TAL) TAiIN input low level pulse width 80 ns

Table 28.23 Timer A Input (gating input in timer mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TA) TAiIN input clock cycle time 400 ns

tw(TAH) TAiIN input high level pulse width 180 ns

tw(TAL) TAiIN input low level pulse width 180 ns

Table 28.24 Timer A Input (external trigger input in one-shot timer mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TA) TAiIN input clock cycle time 200 ns

tw(TAH) TAiIN input high level pulse width 80 ns

tw(TAL) TAiIN input low level pulse width 80 ns

Table 28.25 Timer A Input (external trigger input in pulse-width modulation mode)

Symbol Characteristic Value Unit

Min. Max.

tw(TAH) TAiIN input high level pulse width 80 ns

tw(TAL) TAiIN input low level pulse width 80 ns

Table 28.26 Timer A Input (increment/decrement switching input in event counter mode)

Symbol Characteristic Value Unit

Min. Max.

tc(UP) TAiOUT input clock cycle time 2000 ns

tw(UPH) TAiOUT input high level pulse width 1000 ns

tw(UPL) TAiOUT input low level pulse width 1000 ns

tsu(UP-TIN) TAiOUT input setup time 400 ns

th(TIN-UP) TAiOUT input hold time 400 ns

R01UH0211EJ0120 Rev.1.20 Page 559 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Table 28.27 Timer B Input (counting input in event counter mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TB) TBiIN input clock cycle time (one edge counting) 200 ns

tw(TBH) TBiIN input high level pulse width (one edge counting) 80 ns

tw(TBL) TBiIN input low level pulse width (one edge counting) 80 ns

tc(TB) TBiIN input clock cycle time (both edges counting) 200 ns

tw(TBH) TBiIN input high level pulse width (both edges counting) 80 ns

tw(TBL) TBiIN input low level pulse width (both edges counting) 80 ns

Table 28.28 Timer B Input (pulse period measure mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TB) TBiIN input clock cycle time 400 ns

tw(TBH) TBiIN input high level pulse width 180 ns

tw(TBL) TBiIN input low level pulse width 180 ns

Table 28.29 Timer B Input (pulse-width measure mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TB) TBiIN input clock cycle time 400 ns

tw(TBH) TBiIN input high level pulse width 180 ns

tw(TBL) TBiIN input low level pulse width 180 ns

R01UH0211EJ0120 Rev.1.20 Page 560 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Table 28.30 Serial Interface

Symbol Characteristic Value Unit

Min. Max.

tc(CK) CLKi input clock cycle time 200 ns

tw(CKH) CLKi input high level pulse width 80 ns

tw(CKL) CLKi input low level pulse width 80 ns

tsu(D-C) RXDi input setup time 80 ns

th(C-D) RXDi input hold time 90 ns

Table 28.31 A/D Trigger Input

Symbol Characteristic Value Unit

Min. Max.

tw(ADH) ADTRG input high level pulse width

Hardware trigger input high level pulse width ns

tw(ADL) ADTRG input low level pulse width

Hardware trigger input high level pulse width 125 ns

Table 28.32 External Interrupt INTi Input

Symbol Characteristic Value Unit

Min. Max.

tw(INH) INTi input high level pulse width Edge sensitive 250 ns

Level sensitive tc(CPU) + 200 ns

tw(INL) INTi input low level pulse width Edge sensitive 250 ns

Level sensitive tc(CPU) + 200 ns

Table 28.33 Intelligent I/O

Symbol Characteristic Value Unit

Min. Max.

tc(ISCLK2) ISCLK2 input clock cycle time 600 ns

tw(ISCLK2H) ISCLK2 input high level pulse width 270 ns

tw(ISCLK2L) ISCLK2 input low level pulse width 270 ns

tsu(RXD-ISCLK2) ISRXD2 input setup time 150 ns

th(ISCLK2-RXD) ISRXD2 input hold time 100 ns

AD

----------

R01UH0211EJ0120 Rev.1.20 Page 561 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Timing Requirements (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Note:

1. The value is calculated by the following formulas based on a value SSC by setting bits SSC4 to

SSC0 in the I2CSSCR register:

th(SDA-SCL)S = SSC ÷ 2 × tc(IIC) + 40 [ns]

tsu(SCL-SDA)P = (SSC ÷ 2 + 1) × tc(IIC) + 40 [ns]

tw(SDAH)P = (SSC + 1) × tc(IIC) + 40 [ns]

Table 28.34 Multi-master I2C-bus Interface

Symbol Characteristic

Value

UnitStandard-mode Fast-mode

Min. Max. Min. Max.

tw(SCLH) MSCL input high level pulse width 600 600 ns

tw(SCLL) MSCL input low level pulse width 600 600 ns

tr(SCL) MSCL input rise time 1000 300 ns

tf(SCL) MSCL input fall time 300 300 ns

tr(SDA) MSDA input rise time 1000 300 ns

tf(SDA) MSDA input fall time 300 300 ns

th(SDA-SCL)S MSCL high level hold time after

START condition/repeated START

condition

(1) 2 × tc(IIC) + 40 ns

tsu(SCL-SDA)P MSCL high level setup time for

repeated START condition/STOP

condition

(1) 2 × tc(IIC) + 40 ns

tw(SDAH)P MSDA high level pulse width after

STOP condition (1) 4 × tc(IIC) + 40 ns

tsu(SDA-SCL) MSDA input setup time 100 100 ns

th(SCL-SDA) MSDA input hold time 00ns

R01UH0211EJ0120 Rev.1.20 Page 562 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Note:

1. The value is calculated using the formulas below based on the base clock cycles (tc(Base)) and

respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the

calculation results in a negative value, modify the value to be set. For details on how to set values,

refer to 9.3.5 “External Bus Timing”.

tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]

tw(R) = Tw(R) × tc(Base) - 10 [ns]

tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]

tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]

Table 28.35 External Bus Timing (separate bus)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

tsu(S-R) Chip-select setup time before

read

Refer to

Figure 28.6

(1) ns

th(R-S) Chip-select hold time after read tc(Base) - 15 ns

tsu(A-R) Address setup time before read (1) ns

th(R-A) Address hold time after read tc(Base) - 15 ns

tw(R) Read pulse width (1) ns

tsu(S-W) Chip-select setup time before

write (1) ns

th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 15 ns

tsu(A-W) Address setup time before write (1) ns

th(W-A) Address hold time after write 1.5 × tc(Base) - 15 ns

tw(W) Write pulse width (1) ns

tsu(D-W) Data setup time before write (1) ns

th(W-D) Data hold time after write 0ns

R01UH0211EJ0120 Rev.1.20 Page 563 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Note:

1. The value is calculated using the formulas below based on the base clock cycles (tc(Base)) and

respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the

calculation results in a negative value, modify the value to be set. For details on how to set values,

refer to 9.3.5 “External Bus Timing”.

tsu(S-ALE) = tsu(A-ALE) = tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]

tw(R) = Tw(R) × tc(Base) -10 [ns]

tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]

Table 28.36 External Bus Timing (multiplexed bus)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

tsu(S-ALE) Chip-select setup time before

ALE

Refer to

Figure 28.6

(1) ns

th(R-S) Chip-select hold time after read 1.5 × tc(Base) - 15 ns

tsu(A-ALE) Address setup time before ALE (1) ns

th(ALE-A) Address hold time after ALE 0.5 × tc(Base) - 5 ns

th(R-A) Address hold time after read 1.5 × tc(Base) - 15 ns

td(ALE-R) ALE-read delay time 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns

tw(ALE) ALE pulse width (1) ns

tdis(R-A) Address disable time after read 8ns

tw(R) Read pulse width (1) ns

th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 15 ns

th(W-A) Address hold time after write 1.5 × tc(Base) - 15 ns

td(ALE-W) ALE-write delay time 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns

tw(W) Write pulse width (1) ns

tsu(D-W) Data setup time before write (1) ns

th(W-D) Data hold time after write 0.5 × tc(Base) ns

R01UH0211EJ0120 Rev.1.20 Page 564 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =5V

Switching Characteristics (VCC = 4.2 to 5.5 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Note:

1. External circuits are required to satisfy the I2C-bus specification.

Table 28.37 Serial Interface

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

td(C-Q) TXDi output delay time Refer to

Figure 28.6

80 ns

th(C-Q) TXDi output hold time 0ns

Table 28.38 Intelligent I/O

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

td(ISCLK2-TXD) ISTXD2 output delay time Refer to

Figure 28.6

180 ns

th(ISCLK2-RXD) ISTXD2 output hold time 0ns

Table 28.39 Multi-master I2C-bus Interface (standard-mode)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

tf(SCL) MSCL output fall time

Refer to

Figure 28.6

2ns

tf(SDA) MSDA output fall time 2ns

td(SDA-SCL)S MSCL output delay time after START

condition/repeated START condition 20 × tc(IIC) - 120 52 × tc(IIC) - 40 ns

td(SCL-SDA)P Repeated START condition/STOP

condition output delay time after

MSCL becomes high

20 × tc(IIC) + 40 52 × tc(IIC) + 120 ns

td(SCL-SDA) MSDA output delay time 2 × tc(IIC) + 40 3 × tc(IIC) + 120 ns

Table 28.40 Multi-master I2C-bus Interface (fast-mode)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

tf(SCL) MSCL output fall time

Refer to

Figure 28.6

2 (1) ns

tf(SDA) MSDA output fall time 2 (1) ns

td(SDA-SCL)S MSCL output delay time after START

condition/repeated START condition 10 × tc(IIC) - 120 26 × tc(IIC) - 40 ns

td(SCL-SDA)P Repeated START condition/STOP

condition output delay time after

MSCL becomes high

10 × tc(IIC) + 40 26 × tc(IIC) + 120 ns

td(SCL-SDA) MSDA output delay time 2 × tc(IIC) + 40 3 × tc(IIC) + 120 ns

R01UH0211EJ0120 Rev.1.20 Page 565 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Note:

1. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

Table 28.41 Electrical Characteristics (1/3) (VCC = 3.0 to 3.6 V, VSS =0V, T

a=T

opr, and

f(CPU) = 64 MHz, unless otherwise noted)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Typ. Max.

VOH High

level

output

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0toP10_7, P11_0toP11_4,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (1)

IOH = -1 mA VCC - 0.6 VCC V

VOL Low

level

output

voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0toP10_7, P11_0toP11_4,

P12_0 to P12_7, P13_0 to P13_7,

P14_3 to P14_6, P15_0 to P15_7 (1)

IOL = 1 mA 0.5 V

R01UH0211EJ0120 Rev.1.20 Page 566 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Notes:

1. Pins INT6 to INT8 are available in the 144-pin package only.

2. Ports P9_0, P9_2, and P11 to P15 are available in the 144-pin package only. Port P9_1 is designated

as input pin in the 100-pin package.

Table 28.42 Electrical Characteristics (2/3) (VCC = 3.0 to 3.6 V, VSS =0V, T

a=T

opr, and

f(CPU) = 64 MHz, unless otherwise noted)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Typ. Max.

VT+ - VT- Hysteresis HOLD, RDY, NMI, INT0 to INT8, KI0 to KI3,

TA0IN to TA4IN, TA0OUT to TA4OUT,

TB0IN to TB5IN, CTS0 to CTS8,

CLK0 to CLK8, RXD0 to RXD8,

SCL0 to SCL6, SDA0 to SDA6, SS0 to SS6,

SRXD0toSRXD6,

ADTRG,

IIO0_0 to IIO0_7, IIO1_0 to IIO1_7, UD0A,

UD0B, UD1A, UD1B, ISCLK2, ISRXD2,

IEIN, MSCL, MSDA, CAN0IN, CAN0WU (1)

0.2 1.0 V

RESET 0.2 1.8 V

IIH High level

input

current

XIN, RESET, CNVSS, NSD,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

P15_0 to P15_7 (2)

VI = 3.3 V 4.0 µA

IIL Low level

input

current

XIN, RESET, CNVSS, NSD,

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

P15_0 to P15_7 (2)

VI = 0 V -4.0 µA

RPULLUP Pull-up

resistor

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P5_0 to P5_3, P8_4, P8_6,

P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_4, P12_0 to P12_7,

P13_0 to P13_7, P14_1, P14_3 to P14_6,

P15_0 to P15_7 (2)

VI = 0 V 50 100 500 k

RfXIN Feedback

resistor

XIN 3M



RfXCIN Feedback

resistor

XCIN 25 M

R01UH0211EJ0120 Rev.1.20 Page 567 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Table 28.43 Electrical Characteristics (3/3)

(VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Symbol Characte

ristic Measurement Condition Value Unit

Min. Typ. Max.

ICC Power

supply

current

In single-chip mode,

output pins are left open

and others are

connected to VSS

XIN-XOUT

Drive strength: low

XCIN-XCOUT

Drive strength: low

f(CPU) =64MHz, f

(BCLK) =32MHz,

f(XIN) =8MHz,

Active: XIN, PLL,

Stopped: XCIN, OCO

40 55 mA

f(CPU) = 50 MHz, f(BCLK) = 25 MHz,

f(XIN) =8MHz,

Active: XIN, PLL,

Stopped: XCIN, OCO

32 45 mA

f(CPU) = fSO(PLL)/24 MHz,

Active: PLL (self-oscillation),

Stopped: XIN, XCIN, OCO

9mA

f(CPU) = f(BCLK) = f(XIN)/256 MHz,

f(XIN) =8MHz,

Active: XIN,

Stopped: PLL, XCIN, OCO

670 µA

f(CPU) = f(BCLK) = 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown

180 µA

f(CPU) = f(BCLK) = f(OCO)/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown

190 µA

f(CPU) = f(BCLK) = f(XIN)/256 MHz,

f(XIN) =8MHz,

Active: XIN,

Stopped: PLL, XCIN, OCO,

Ta = 25°C, Wait mode

500 900 µA

f(CPU) = f(BCLK) = 32.768 kHz,

Active: XCIN,

Stopped: XIN, PLL, OCO,

Main regulator: shutdown,

Ta = 25°C, Wait mode

8 140 µA

f(CPU) = f(BCLK) = f(OCO)/4 kHz,

Active: OCO,

Stopped: XIN, PLL, XCIN,

Main regulator: shutdown,

Ta = 25°C, Wait mode

10 150 µA

Stopped: all clocks,

Main regulator: shutdown,

Ta = 25°C

570µA

R01UH0211EJ0120 Rev.1.20 Page 568 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Note:

1. Pins AN15_0 to AN15_7 are available in the 144-pin package only.

Table 28.44 A/D Conversion Characteristics (VCC =AV

CC =V

REF =3.0to3.6V, V

SS =AV

SS =0V,

Ta=T

opr, and f(BCLK) = 32 MHz, unless otherwise noted)

Symbol Characteristic Measurement Condition Value Unit

Min. Typ. Max.

—Resolution VREF = VCC 10 Bits

—

Absolute error VREF = VCC = 3.3 V AN_0toAN_7,

AN0_0toAN0_7,

AN2_0toAN2_7,

AN15_0 to AN15_7,

ANEX0, ANEX1 (1)

±5 LSB

External op-amp

connection mode ±7 LSB

INL Integral non-linearity

error

VREF = VCC = 3.3 V AN_0toAN_7,

AN0_0toAN0_7,

AN2_0toAN2_7,

AN15_0 to AN15_7,

ANEX0, ANEX1 (1)

±5 LSB

External op-amp

connection mode ±7 LSB

DNL Differential non-

linearity error

VREF = VCC = 3.3 V ±1 LSB

—Offset error ±3 LSB

— Gain error ±3 LSB

RLADDER Resistor ladder VREF = VCC 420k

tCONV Conversion time

(10 bits)

AD = 10 MHz,

with sample and hold function 3.3 µs

tCONV Conversion time

(8 bits)

AD = 10 MHz,

with sample and hold function 2.8 µs

tSAMP Sampling time AD = 10 MHz 0.3 µs

VIA Analog input voltage 0VREF V

AD Operating clock

frequency

Without sample and hold function 0.25 10 MHz

With sample and hold function 1 10 MHz

R01UH0211EJ0120 Rev.1.20 Page 569 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Note:

1. One D/A converter is used. The DAi register (i = 0, 1) of the other unused converter is set to 00h. The

resistor ladder for the A/D converter is not considered.

Even when the VCUT bit in the AD0CON1 register is set to 0 (VREF disconnected), IVREF is supplied.

Table 28.45 D/A Conversion Characteristics (VCC =AV

CC =V

REF =3.0to3.6V, V

SS =AV

SS =0V,

and Ta=T

opr, unless otherwise noted)

Symbol Characteristic Measurement Condition Value Unit

Min. Typ. Max.

— Resolution 8Bits

— Absolute precision 1.0 %

tSSettling time 3µs

ROOutput resistance 41020k



IVREF Reference input current See Note 1 1.0 mA

R01UH0211EJ0120 Rev.1.20 Page 570 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Table 28.46 External Clock Input

Symbol Characteristic Value Unit

Min. Max.

tc(X) External clock input period 62.5 250 ns

tw(XH) External clock input high level pulse width 25 ns

tw(XL) External clock input low level pulse width 25 ns

tr(X) External clock input rise time 5ns

tf(X) External clock input fall time 5ns

tw / tcExternal clock input duty 40 60 %

Table 28.47 External Bus Timing

Symbol Characteristic Value Unit

Min. Max.

tsu(D-R) Data setup time before read 40 ns

th(R-D) Data hold time after read 0ns

tdis(R-D) Data disable time after read 0.5 × tc(Base) + 10 ns

R01UH0211EJ0120 Rev.1.20 Page 571 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Table 28.48 Timer A Input (counting input in event counter mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TA) TAiIN input clock cycle time 200 ns

tw(TAH) TAiIN input high level pulse width 80 ns

tw(TAL) TAiIN input low level pulse width 80 ns

Table 28.49 Timer A Input (gating input in timer mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TA) TAiIN input clock cycle time 400 ns

tw(TAH) TAiIN input high level pulse width 180 ns

tw(TAL) TAiIN input low level pulse width 180 ns

Table 28.50 Timer A Input (external trigger input in one-shot timer mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TA) TAiIN input clock cycle time 200 ns

tw(TAH) TAiIN input high level pulse width 80 ns

tw(TAL) TAiIN input low level pulse width 80 ns

Table 28.51 Timer A Input (external trigger input in pulse-width modulation mode)

Symbol Characteristic Value Unit

Min. Max.

tw(TAH) TAiIN input high level pulse width 80 ns

tw(TAL) TAiIN input low level pulse width 80 ns

Table 28.52 Timer A Input (increment/decrement switching input in event counter mode)

Symbol Characteristic Value Unit

Min. Max.

tc(UP) TAiOUT input clock cycle time 2000 ns

tw(UPH) TAiOUT input high level pulse width 1000 ns

tw(UPL) TAiOUT input low level pulse width 1000 ns

tsu(UP-TIN) TAiOUT input setup time 400 ns

th(TIN-UP) TAiOUT input hold time 400 ns

R01UH0211EJ0120 Rev.1.20 Page 572 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Table 28.53 Timer B Input (counting input in event counter mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TB) TBiIN input clock cycle time (one edge counting) 200 ns

tw(TBH) TBiIN input high level pulse width (one edge counting) 80 ns

tw(TBL) TBiIN input low level pulse width (one edge counting) 80 ns

tc(TB) TBiIN input clock cycle time (both edges counting) 200 ns

tw(TBH) TBiIN input high level pulse width (both edges counting) 80 ns

tw(TBL) TBiIN input low level pulse width (both edges counting) 80 ns

Table 28.54 Timer B Input (pulse period measure mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TB) TBiIN input clock cycle time 400 ns

tw(TBH) TBiIN input high level pulse width 180 ns

tw(TBL) TBiIN input low level pulse width 180 ns

Table 28.55 Timer B Input (pulse-width measure mode)

Symbol Characteristic Value Unit

Min. Max.

tc(TB) TBiIN input clock cycle time 400 ns

tw(TBH) TBiIN input high level pulse width 180 ns

tw(TBL) TBiIN input low level pulse width 180 ns

R01UH0211EJ0120 Rev.1.20 Page 573 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Table 28.56 Serial Interface

Symbol Characteristic Value Unit

Min. Max.

tc(CK) CLKi input clock cycle time 200 ns

tw(CKH) CLKi input high level pulse width 80 ns

tw(CKL) CLKi input low level pulse width 80 ns

tsu(D-C) RXDi input setup time 80 ns

th(C-D) RXDi input hold time 90 ns

Table 28.57 A/D Trigger Input

Symbol Characteristic Value Unit

Min. Max.

tw(ADH) ADTRG input high level pulse width

Hardware trigger input high level pulse width ns

tw(ADL) ADTRG input low level pulse width

Hardware trigger input high level pulse width 125 ns

Table 28.58 External Interrupt INTi Input

Symbol Characteristic Value Unit

Min. Max.

tw(INH) INTi input high level pulse width Edge sensitive 250 ns

Level sensitive tc(CPU) + 200 ns

tw(INL) INTi input low level pulse width Edge sensitive 250 ns

Level sensitive tc(CPU) + 200 ns

Table 28.59 Intelligent I/O

Symbol Characteristic Value Unit

Min. Max.

tc(ISCLK2) ISCLK2 input clock cycle time 600 ns

tw(ISCLK2H) ISCLK2 input high level pulse width 270 ns

tw(ISCLK2L) ISCLK2 input low level pulse width 270 ns

tsu(RXD-ISCLK2) ISRXD2 input setup time 150 ns

th(ISCLK2-RXD) ISRXD2 input hold time 100 ns

AD

----------

R01UH0211EJ0120 Rev.1.20 Page 574 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Timing Requirements (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Note:

1. The value is calculated using the formulas below based on a value SSC set by bits SSC4 to SSC0 in

the I2CSSCR register:

th(SDA-SCL)S = SSC ÷ 2 × tc(IIC) + 40 [ns]

tsu(SCL-SDA)P = (SSC ÷ 2 + 1) × tc(IIC) + 40 [ns]

tw(SDAH)P = (SSC + 1) × tc(IIC) + 40 [ns]

Table 28.60 Multi-master I2C-bus Interface

Symbol Characteristic

Value

UnitStandard-mode Fast-mode

Min. Max. Min. Max.

tw(SCLH) MSCL input high level pulse width 600 600 ns

tw(SCLL) MSCL input low level pulse width 600 600 ns

tr(SCL) MSCL input rise time 1000 300 ns

tf(SCL) MSCL input fall time 300 300 ns

tr(SDA) MSDA input rise time 1000 300 ns

tf(SDA) MSDA input fall time 300 300 ns

th(SDA-SCL)S MSCL high level hold time after

START condition/repeated START

condition

(1) 2 × tc(IIC) + 40 ns

tsu(SCL-SDA)P MSCL high level setup time for

repeated START condition/STOP

condition

(1) 2 × tc(IIC) + 40 ns

tw(SDAH)P MSDA high level pulse width after

STOP condition (1) 4 × tc(IIC) + 40 ns

tsu(SDA-SCL) MSDA input setup time 100 100 ns

th(SCL-SDA) MSDA input hold time 00ns

R01UH0211EJ0120 Rev.1.20 Page 575 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Note:

1. The value is calculated using the formulas below based on the base clock cycles (tc(Base)) and

respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the

calculation results in a negative value, modify the value to be set. For details on how to set values,

refer to 9.3.5 “External Bus Timing”.

tsu(S-R) = tsu(A-R) = Tsu(A-R) × tc(Base) - 15 [ns]

tw(R) = Tw(R) × tc(Base) - 10 [ns]

tsu(S-W) = tsu(A-W) = Tsu(A-W) × tc(Base) - 15 [ns]

tw(W) = tsu(D-W) = Tw(W) × tc(Base) - 10 [ns]

Table 28.61 External Bus Timing (separate bus)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

tsu(S-R) Chip-select setup time before

read

Refer to

Figure 28.6

(1) ns

th(R-S) Chip-select hold time after read tc(Base) - 15 ns

tsu(A-R) Address setup time before read (1) ns

th(R-A) Address hold time after read tc(Base) - 15 ns

tw(R) Read pulse width (1) ns

tsu(S-W) Chip-select setup time before

write (1) ns

th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 15 ns

tsu(A-W) Address setup time before write (1) ns

th(W-A) Address hold time after write 1.5 × tc(Base) - 15 ns

tw(W) Write pulse width (1) ns

tsu(D-W) Data setup time before write (1) ns

th(W-D) Data hold time after write 0ns

R01UH0211EJ0120 Rev.1.20 Page 576 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Note:

1. The value is calculated using the formulas below based on the base clock cycles (tc(Base)) and

respective cycles of Tsu(A-R), Tw(R), Tsu(A-W), and Tw(W) set by registers EBC0 to EBC3. If the

calculation results in a negative value, modify the value to be set. For details on how to set values,

refer to 9.3.5 “External Bus Timing”.

tsu(S-ALE) = tsu(A-ALE) = (Tsu(A-R) - 0.5) × tc(Base) -15 [ns]

tw(ALE) = (Tsu(A-R) - 0.5) × tc(Base) - 20 [ns]

tw(R) = Tw(R) × tc(Base) -10 [ns]

tw(W) = tsu(D-W) = Tw(W) × tc(Base) -10 [ns]

Table 28.62 External Bus Timing (multiplexed bus)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

tsu(S-ALE) Chip-select setup time before

ALE

Refer to

Figure 28.6

(1) ns

th(R-S) Chip-select hold time after read 1.5 × tc(Base) - 15 ns

tsu(A-ALE) Address setup time before ALE (1) ns

th(ALE-A) Address hold time after ALE 0.5 × tc(Base) - 5 ns

th(R-A) Address hold time after read 1.5 × tc(Base) - 15 ns

td(ALE-R) ALE-read delay time 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns

tw(ALE) ALE pulse width (1) ns

tdis(R-A) Address disable time after read 8ns

tw(R) Read pulse width (1) ns

th(W-S) Chip-select hold time after write 1.5 × tc(Base) - 15 ns

th(W-A) Address hold time after write 1.5 × tc(Base) - 15 ns

td(ALE-W) ALE-write delay time 0.5 × tc(Base) - 5 0.5 × tc(Base) + 10 ns

tw(W) Write pulse width (1) ns

tsu(D-W) Data setup time before write (1) ns

th(W-D) Data hold time after write 0.5 × tc(Base) ns

R01UH0211EJ0120 Rev.1.20 Page 577 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

VCC =3.3V

Switching Characteristics (VCC = 3.0 to 3.6 V, VSS = 0 V, and Ta=T

opr, unless otherwise noted)

Note:

1. External circuits are required to satisfy the I2C-bus specification.

Table 28.63 Serial Interface

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

td(C-Q) TXDi output delay time Refer to

Figure 28.6

80 ns

th(C-Q) TXDi output hold time 0ns

Table 28.64 Intelligent I/O

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

td(ISCLK2-TXD) ISTXD2 output delay time Refer to

Figure 28.6

180 ns

th(ISCLK2-RXD) ISTXD2 output hold time 0ns

Table 28.65 Multi-master I2C-bus Interface (Standard-mode)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

tf(SCL) MSCL output fall time

Refer to

Figure 28.6

2ns

tf(SDA) MSDA output fall time 2ns

td(SDA-SCL)S MSCL output delay time after START

condition/repeated START condition 20 × tc(IIC) - 120 52 × tc(IIC) - 40 ns

td(SCL-SDA)P Repeated START condition/STOP

condition output delay time after

MSCL becomes high

20 × tc(IIC) + 40 52 × tc(IIC) + 120 ns

td(SCL-SDA) MSDA output delay time 2 ×tc(IIC) + 40 3 × tc(IIC) + 120 ns

Table 28.66 Multi-master I2C-bus Interface (Fast-mode)

Symbol Characteristic Measurement

Condition

Value Unit

Min. Max.

tf(SCL) MSCL output fall time

Refer to

Figure 28.6

2 (1) ns

tf(SDA) MSDA output fall time 2 (1) ns

td(SDA-SCL)S MSCL output delay time after START

condition/repeated START condition 10 × tc(IIC) - 120 26 × tc(IIC) - 40 ns

td(SCL-SDA)P Repeated START condition/STOP

condition output delay time after

MSCL becomes high

10 × tc(IIC) + 40 26 × tc(IIC) + 120 ns

td(SCL-SDA) MSDA output delay time 2 × tc(IIC) + 40 3 × tc(IIC) + 120 ns

R01UH0211EJ0120 Rev.1.20 Page 578 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Figure 28.6 Switching Characteristic Measurement Circuit

Figure 28.7 External Clock Input Timing

30 pF

Pin to be

measured

MCU

XIN

w(XH) t

w(XL)

r(X) t

f(X)

c(X)

R01UH0211EJ0120 Rev.1.20 Page 579 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Figure 28.8 External Bus Timing for Separate Bus

CS0 to CS3

A23 to A0, BC0 to BC3

D31 to D0

h(R-D)

h(R-S)

External bus timing (separate bus)

Read cycle

w(R)

su(S-R)

h(R-A)

su(A-R)

Write cycle

CS0 to CS3

A23 to A0, BC0 to BC3

WR, WR0 to WR3

D31 to D0

su(D-W) t

h(W-D)

su(D-R)

h(W-S)

w(W)

su(S-W)

h(W-A)

su(A-W)

Measurement conditions

Criterion for

input voltage

Criterion for

output voltage

2.5 V

0.8 V

2.0 V

0.8 V

1.5 V

0.5 V

2.4 V

0.5 V

Item V = 4.2 to 5.5 V

V = 3.0 to 3.6 V

R01UH0211EJ0120 Rev.1.20 Page 580 of 604

Feb 18, 2013

R32C/117 Group 28. Electrical Characteristics

Figure 28.9 External Bus Timing for Multiplexed Bus

CS0 to CS3

A23 to A8, BC0 to BC3

D31 to D8

h(R-D)

h(R-S)

External bus timing (multiplexed bus)

Read cycle

w(R)

su(S-ALE)

h(R-A)

su(A-ALE)

Write cycle

WR, WR0 to WR3

su(D-R)

Measurement conditions

Criterion for

input voltage

Criterion for

output voltage

2.5 V

0.8 V

2.0 V

0.8 V

1.5 V

0.5 V

2.4 V

0.5 V

Item

ALE

w(ALE)

Address

su(A-ALE)

A15/D15 to A0/D0,

BC0/D0, BC2/D1 Data

h(ALE-A)

d(ALE-R)

h(R-D)

su(D-R)

CS0 to CS3

A23 to A8, BC0 to BC3

D31 to D8

h(W-D)

h(W-S)

w(W)

su(S-ALE)

h(W-A)

su(A-ALE)

su(D-W)

ALE

w(ALE)

Address

su(A-ALE)

A15/D15 to A0/D0,

BC0/D0, BC2/D1 Data

h(ALE-A)

d(ALE-W)

h(W-D)

su(D-W)

dis(R-A)

dis(R-D)

V = 4.2 to 5.5 V

CC V = 3.0 to 3.6 V

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R32C/117 Group 28. Electrical Characteristics

Figure 28.10 Timing of Peripherals

TAiIN input

TAiOUT input

c(TA)

w(TAH) t

w(TAL)

c(UP)

w(UPH) t

w(UPL)

TAiIN input (in falling edge counting)

TAiOUT input (input for increment/

decrement switching)

In event counter mode

TAiIN input (in rising edge counting)

h(TIN-UP)

TBiIN input

ADTRG input

c(TB)

w(TBH) t

w(TBL)

w(ADL)

CLKi

c(CK)

w(CKH) t

w(CKL)

TXDi

d(C-Q) t

h(C-Q)

RXDi

su(D-C) t

h(C-D)

INTi input

w(INL) t

w(INH)

NMI input

Two CPU clock cycles +

300 ns or more

Two CPU clock cycles +

300 ns or more

su(UP-TIN)

w(ADH)

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R32C/117 Group 28. Electrical Characteristics

Figure 28.11 Timing of Multi-master I2C-bus Interface

MSCL

h(SDA-SCL)S

MSDA (input)

MSCL

w(SCLH) t

w(SCLL)

c(SCL)

r(SCL) t

f(SCL)

MSDA

r(SDA) t

f(SDA)

su(SCL-SDA)P

h(SDA-SCL)S

su(SCL-SDA)P

MSDA (output)

MSCL

d(SDA-SCL)S t

d(SCL-SDA)P

d(SDA-SCL)S

d(SCL-SDA)P

MSCL

MSDA (input)

su(SDA-SCL) t

h(SCL-SDA)

MSCL

MSDA (output)

d(SCL-SDA)

w(SDAH)P

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R32C/117 Group 29. Usage Notes

29. Usage Notes

29.1 Notes on Board Designing

29.1.1 Power Supply Pins

The board should be designed so there is no potential difference between pins with the same name.

Note the following points:

• Connect all VSS pins to the same GND. Traces for the pins should be as wide as physically

possible so the same voltage can be applied to every VSS pin.

• Connect all VCC pins to the same power supply. Traces for the pins should be as wide as

physically possible so the same voltage can be applied to every VCC pin.

Insert a capacitor between each VCC pin and the VSS pin to prevent operation errors due to noise. The

capacitor should be beneficially effective at high and low frequencies and should have a capacitance of

approximately 0.1 µF. The traces for the capacitor and the power supply pins should be as short and

wide as physically possible.

29.1.2 Supply Voltage

The device is operationally guaranteed under operating conditions specified in electrical

characteristics.

Drive the RESET pin low before the supply voltage becomes lower than the recommended value.

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R32C/117 Group 29. Usage Notes

29.2 Notes on Register Setting

29.2.1 Registers with Write-only Bits

Read-modify-write instructions cannot be used when setting a register containing write-only bits. Read-

modify-write instructions read a value of an address, modify the value, and write the modified value to

the same address. Table 29.1 lists read-modify-write instructions, and Table 29.2 lists registers

containing write-only bits. To set a new value by modifying the previous one, write the previous value

into RAM as well as to the register, change the contents of the RAM and then transfer the new value to

the register by the MOV instruction.

Table 29.1 Read-modify-write Instructions

Function Mnemonic

Transfer MOVDir

Bit processing BCLR, BMCnd, BNOT, BSET, BTSTC, and BTSTS

Shifting ROLC, RORC, ROT, SHA, and SHL

Arithmetic operation ABS, ADC, ADCF, ADD, ADSF, DEC, DIV, DIVU, DIVX, EXTS, EXTZ, INC, MUL,

MULU, NEG, SBB, and SUB

Decimal operation DADC, DADD, DSBB, and DSUB

Floating-point operation ADDF, DIVF, MULF, and SUBF

Logical operation AND, NOT, OR, and XOR

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R32C/117 Group 29. Usage Notes

Note:

1. The register has write-only bits in one-shot timer mode and pulse-width modulation mode.

Table 29.2 Registers with Write-only Bits

Module Register Symbol Address

Watchdog timer Watchdog timer start register WDTS 04404Eh

Timer A Timer A0 register (1) TA0 0347h-0346h

Timer A1 register (1) TA1 0349h-0348h

Timer A2 register (1) TA2 034Bh-034Ah

Timer A3 register (1) TA3 034Dh-034Ch

Timer A4 register (1) TA4 034Fh-034Eh

Increment/decrement select register UDF 0344h

Three-phase motor Timer B2 interrupt generating frequency set counter ICTB2 030Dh

control timers Timer A1-1 register TA11 0303h-0302h

Timer A2-1 register TA21 0305h-0304h

Timer A4-1 register TA41 0307h-0306h

Dead time timer DTT 030Ch

Serial interface UART0 bit rate register U0BRG 0369h

UART1 bit rate register U1BRG 02E9h

UART2 bit rate register U2BRG 0339h

UART3 bit rate register U3BRG 0329h

UART4 bit rate register U4BRG 02F9h

UART5 bit rate register U5BRG 01C9h

UART6 bit rate register U6BRG 01D9h

UART7 bit rate register U7BRG 01E1h

UART8 bit rate register U8BRG 01E9h

UART0 transmit buffer register U0TB 036Bh-036Ah

UART1 transmit buffer register U1TB 02EBh-02EAh

UART2 transmit buffer register U2TB 033Bh-033Ah

UART3 transmit buffer register U3TB 032Bh-032Ah

UART4 transmit buffer register U4TB 02FBh-02FAh

UART5 transmit buffer register U5TB 01CBh-01CAh

UART6 transmit buffer register U6TB 01DBh-01DAh

UART7 transmit buffer register U7TB 01E3h-01E2h

UART8 transmit buffer register U8TB 01EBh-01EAh

Intelligent I/O Group 2 SIO transmit buffer register G2TB 016Dh-016Ch

CAN module CAN0 receive FIFO pointer control register C0RFPCR 047F49h

CAN0 transmit FIFO pointer control register C0TFPCR 047F4Bh

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R32C/117 Group 29. Usage Notes

29.3 Notes on Clock Generator

29.3.1 Sub Clock

29.3.1.1 Oscillator Constant Matching

The constant matching of the sub clock oscillator should be evaluated in both cases when the drive

strength is high and low.

Contact the oscillator manufacturer for details on the oscillation circuit constant matching.

29.3.2 Power Control

Do not switch the base clock source until the oscillation of the clock to be used has stabilized. However,

this does not apply to the on-chip oscillator since it starts running immediately after the CM31 bit in the

CM3 register is set to 1.

To switch the base clock source from the PLL clock to a low speed clock, use the MOV.L or OR.L

instruction to set the BCS bit in the CCR register to 1.

• Program example in assembly language

OR.L #80h, 0004h

• Program example in C language

asm("OR.L #80h, 0004h");

29.3.2.1 Stop Mode

• To exit stop mode using a reset, apply a low signal to the RESET pin until the main clock oscillation

stabilizes.

29.3.2.2 Suggestions for Power Saving

The following are suggestions to reduce power consumption when programming or designing systems.

• I/O pins:

If inputs are floating, both transistors may be conducting. Set unassigned pins to input mode and

connect each of them to VSS via a resistor, or set them to output mode and leave them open.

• A/D converter:

When not performing the A/D conversion, set the VCUT bit in the AD0CON1 register to 0 (VREF

disconnected). To perform the A/D conversion, set the VCUT bit to 1 (VREF connected) and wait at

least 1 µs before starting conversion.

• D/A converter:

When not performing the D/A conversion, set the DAiE bit in the DACON register (i = 0, 1) to 0

(output disabled) and the DAi register to 00h.

• Peripheral clock stop:

When entering wait mode, power consumption can be reduced by setting the CM02 bit in the CM0

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R32C/117 Group 29. Usage Notes

29.4 Notes on Bus

29.4.1 Notes on Designing a System

When a flash memory rewrite is performed in CPU rewrite mode using memory expansion mode, the

use of CS0 space and CS3 space has the following restrictions:

• If the FEBC0 and/or FEBC3 registers are set in CPU rewrite mode, the bus timing for the

corresponding space changes. This may cause external devices to become inaccessible

depending on the register settings.

Devices required to be accessed in CPU rewrite mode should be allocated in CS1 space and/or CS2

space.

29.4.2 Notes on Register Settings

29.4.2.1 Chip Select Boundary Select Registers

When not using memory expansion mode, do not change values after a reset for registers CB01,

CB12, and CB23.

When using memory expansion mode, set all of these registers to a value within the specified range

whether or not each chip select space is used.

29.4.2.2 External Bus Control Registers

Registers EBC0 and EBC3 share respective addresses with registers FEBC0 and FEBC3. If the

FEBC0 and/or FEBC3 registers are set while the flash memory is being rewritten, set the EBC0 and/

or EBC3 registers again after rewriting the flash memory.

• If the FEBC0 and/or FEBC3 registers are set in CPU rewrite mode, the bus format for the

corresponding space functions as separate bus. Any external devices connected in multiplexed

bus format become inaccessible.

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R32C/117 Group 29. Usage Notes

29.5 Notes on Interrupts

29.5.1 ISP Setting

The interrupt stack pointer (ISP) is initialized to 00000000h after a reset. Set a value to the ISP before

an interrupt is accepted, otherwise the program may go out of control. A multiple of 4 should be set to

the ISP, which enables faster interrupt sequence due to less memory access.

When using NMI, in particular, since this interrupt cannot be disabled, set the PM24 bit in the PM2

29.5.2 NMI

• NMI cannot be disabled once the PM24 bit in the PM2 register is set to 1 (NMI enabled). This bit

setting should be done only when using NMI.

• When the PM24 bit in the PM2 register is 1 (NMI enabled), the P8_5 bit in the P8 register is

enabled just for monitoring the NMI pin state. It is not enabled as a general port.

29.5.3 External Interrupts