SPICE Device Model Si6562DQ Vishay Siliconix N- and P-Channel 20-V (D-S) MOSFET CHARACTERISTICS * N- and P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The model subcircuit schematic is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71553 25-Feb-99 www.vishay.com 1 SPICE Device Model Si6562DQ Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit Static Gate Threshold Voltage VGS(th) a On-State Drain Current ID(on) a Drain-Source On-State Resistance rDS(on) Forward Transconductancea gfs Diode Forward Voltagea VSD Dynamic VDS = V, VGS, ID = 250 A N-Ch 0.89 VDS = V, VGS, ID = -250 A P-Ch 0.95 VDS 5 V, VGS = 4.5 V N-Ch 119 VDS -5 V, VGS = -4.5 V P-Ch 74 VGS = 4.5 V, ID = 4.5 A N-Ch 0.022 VGS = -4.5 V, ID = 3.5 A P-Ch 0.040 VGS = 2.5 V, ID = 3.9 A N-Ch 0.028 VGS = -2.5 V, ID = 2.7 A P-Ch 0.056 VDS = 10 V, ID = 4.5 A N-Ch 20 VDS = -10 V, ID = -3.5 A P-Ch 12 IS = 1.25 A, VGS = 0 V N-Ch 0.65 IS = -1.25 V, VGS = 0 V P-Ch -0.72 V A S V b Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time N-Channel VDS = 15 V, VGS = 4.5 V, ID = 4.5 A P-Channel VDS = -15 V, VGS = -4.5 V, ID = -3.5 A N-Ch 13 P-Ch 14.6 N-Ch 3 P-Ch 3.5 N-Ch 3.3 P-Ch 3.5 N-Ch 7 P-Ch 29 40 tr N-Channel VDD = 10 V, RL = 10 ID 1 A, VGEN = 10 V, RG = 6 N-Ch P-Ch 35 td(off) P-Channel VDD = -10 V, RL = 10 ID -1 A, VGEN = -4.5 V, RG = 6 N-Ch 51 P-Ch 37 N-Ch 17 tf trr P-Ch 50 IF = A, IS = 1.25A, di/dt = 100 A/s N-Ch 31 IF = A, IS = -1.25A, di/dt = 100 A/s P-Ch 59 nC ns Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width 300 s, duty cycle 2%. www.vishay.com 2 Document Number: 71553 25-Feb-99 SPICE Device Model Si6562DQ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) N-CHANNEL MOSFET Document Number: 71553 25-Feb-99 www.vishay.com 3 SPICE Device Model Si6562DQ Vishay Siliconix P-CHANNEL MOSFET www.vishay.com 4 Document Number: 71553 25-Feb-99