R01DS0053EJ0200 Rev. 2.00 Page 1 of 187
Oct 25, 2013
RL78/G14
RENESAS MCU
True Low Power Platform (as low as 66 A/MHz, and 0.60 A for RTC + LVD), 1.6 V to 5.5 V
operation, 16 to 256 Kbyte Flash, 44 DMIPS at 32 MHz, for General Purpose Applications
Datasheet
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 1.6 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.24 A, (LVD enabled): 0.32 A
• Halt (RTC + LVD): 0.60 A
• Snooze: 0.70 mA (UART), 1.20 mA (ADC)
• Operating: 66 A/MHz
16-bit RL78 CPU Core
• Delivers 44 DMIPS at maximum operating frequency of
32 MHz
• Instruction execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC architecture (Harvard) with 3-stage pipeline
• Multiply signed & unsigned: 16 x 16 to 32-bit result in 1
clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Code Flash Memory
• Density: 16 KB to 256 KB
• Block size: 1KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with secure boot swap function and
flash shield window function
Data Flash Memory
• Data flash with background operation
• Data flash size: 4 KB to 8 KB size options
• Erase cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
RAM
• 2.5 KB to 24 KB size options
• Supports operands or instructions
• Back-up retention in all modes
High-speed On-chip Oscillator
• 32 MHz with +/- 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (-20°C to 85°C)
• Pre-configured settings: 64 MHz,48 MHz,32 MHz,
24 MHz, 16 MHz, 12 MHz, 8 MHz, 6MHz, 4 MHz,
3 MHz, 2 MHz, and 1 MHz
• 64 MHz, 48 MHz for timer RD
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
General Purpose I/O
• 5 V tolerant, high-current (up to 20 mA per pin)
• Open-drain, on-chip pull-up resistor
Data Transfer Controller (DTC)
• 39 sources & 24 different settings
• Transfer data: 8 bits/16 bits
• Normal mode and repeat mode
Event Link Controller (ELC)
• Reduce interrupt intervention
• Link 26 events to specified peripheral function
Multiple Communication Interfaces
• Up to 8 x I2C master
• Up to 2 x I2C multi-master
• Up to 8 x CSI/SPI (7-, 8-bit)
• Up to 4 x UART (7-, 8-, 9-bit)
• Up to 1 x LIN
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Motor control timer (3 ph - complementary mode)
• Timer with encoder function: 16-bit, 1 channel
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval timer: 12-bit, 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Rich Analog
• ADC: Up to 20 channels, 10-bit resolution, 2.1 s
conversion time
• Supports 1.6 V
• 2 x window comparators, with ELC connection
• D/A converter: 2 channels, 8-bit resolution
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock stop/frequency detection
• ADC self-test
• I/O port read back function (echo)
Operating Ambient Temperature
• Standard: -40°C to + 85°C
• Extended: -40°C to + 105°C
Package Type and Pin Count
From 4 mm x 4 mm to 14 mm x 20 mm
QFP: 32, 44, 48, 52, 64, 80,100
QFN: 32, 40, 48
SSOP: 30
LGA: 36, 64
R01DS0053EJ0200
Rev. 2.00
Oct 25, 2013
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 2 of 187
Oct 25, 2013
ROM, RAM capacities
Note 1. This is about 4.5 KB when the self-programming function and data flash function are used.
Note 2. This is about 23 KB when the self-programming function and data flash function are used.
Flash ROM Data flash RAM RL78/G14
30 pins 32 pins 36 pins 40 pins
192 KB 8 KB 20 KB — — — R5F104EH
128 KB 8 KB 16 KB R5F104AG R5F104BG R5F104CG R5F104EG
96 KB 8 KB 12 KB R5F104AF R5F104BF R5F104CF R5F104EF
64 KB 4 KB 5.5 KB Note 1 R5F104AE R5F104BE R5F104CE R5F104EE
48 KB 4 KB 5.5 KB Note 1 R5F104AD R5F104BD R5F104CD R5F104ED
32 KB 4 KB 4 KB R5F104AC R5F104BC R5F104CC R5F104EC
16 KB 4 KB 2.5 KB R5F104AA R5F104BA R5F104CA R5F104EA
Flash ROM Data flash RAM RL78/G14
44 pins 48 pins 52 pins 64 pins
256 KB 8 KB 24 KB Note 2 R5F104FJ R5F104GJ R5F104JJ R5F104LJ
192 KB 8 KB 20 KB R5F104FH R5F104GH R5F104JH R5F104LH
128 KB 8 KB 16 KB R5F104FG R5F104GG R5F104JG R5F104LG
96 KB 8 KB 12 KB R5F104FF R5F104GF R5F104JF R5F104LF
64 KB 4 KB 5.5 KB Note 1 R5F104FE R5F104GE R5F104JE R5F104LE
48 KB 4 KB 5.5 KB Note 1 R5F104FD R5F104GD R5F104JD R5F104LD
32 KB 4 KB 4 KB R5F104FC R5F104GC R5F104JC R5F104LC
16 KB 4 KB 2.5 KB R5F104FA R5F104GA — —
Flash ROM Data flash RAM RL78/G14
80 pins 100 pins
256 KB 8 KB 24 KB Note 2 R5F104MJ R5F104PJ
192 KB 8 KB 20 KB R5F104MH R5F104PH
128 KB 8 KB 16 KB R5F104MG R5F104PG
96 KB 8 KB 12 KB R5F104MF R5F104PF
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 3 of 187
Oct 25, 2013
1.2 Ordering Information
Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14
Note Products only for “A: Consumer applications (TA = -40 to +85 C)”
Fields of application:
A: Consumer applications, TA = -40 to +85 C
D: Industrial applications, TA = -40 to +85 C
G: Industrial applications, TA = -40 to +105 C
Packaging specification
#U0: Tray (HWQFN, WFLGA, FLGA)
#V0: Tray (LFQFP , LQFP , LSSO P)
#W0:Embossed Tape (HWQFN, WFLGA, FLGA)
#X0: Embossed Tape (LFQFP, LQFP, LSSOP)
R 5 F 1 0 4 L E A x x x F B # V 0
Package type:
SP:LSSOP, 0.65 mm pit ch
FP:LQFP, 0.80 mm pitch
FA:LQFP, 0.65 mm pitch
FB:LFQFP, 0.50 mm pitch
NA:HWQFN, 0.50 mm pitch
LA: WFLGA, 0.50 m m pit chNote
LA: FLGA, 0.50 mm pitchNote
ROM number (Omitted with blank products)
ROM capacity:
A: 16 KB
C: 32 KB
D: 48 KB
E: 64 KB
F: 96 KB
G: 128 KB
H: 192 KB
J: 256 KB
Pin count:
A: 30-pin
B: 32-pin
C: 36-pinNote
E: 40-pin
F: 44-pin
G: 48-pin
J: 52-pin
L: 64-pin
M: 80-pin
P: 100-pin
RL78/G14
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Part No.
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 4 of 187
Oct 25, 2013
Note For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
(1/5)
Pin
count Package Fields of
Application
Note Ordering Part Number
30 pins 30-pin pla s t i c LS SOP
(7.62 mm (300), 0.65 mm pitch) A R5F104AAASP#V0, R5F104 ACASP#V0, R5F104ADASP#V0, R5F104AEASP#V0,
R5F104AFASP#V0, R5F104AGASP#V 0
R5F104AAASP#X0, R5F104ACASP#X0, R5F104ADASP#X0, R5F104AEASP#X0,
R5F104AFASP#X0, R5F104AGASP#X 0
D R5F104AADSP#V0, R5F104ACDSP#V0, R5F104ADDSP#V0, R5F104AEDSP#V0,
R5F104AFDSP#V0, R5F104AGDSP#V0
R5F104AADSP#X0, R5F104ACDSP#X0, R5F104ADDSP#X0, R5F104AEDSP#X0,
R5F104AFDSP#X0, R5F104AGDSP#X0
G R5F104AAGS P#V0, R5F104ACGSP#V0, R5F104ADGSP#V0, R5F104A EGSP#V0,
R5F104AFGSP#V0, R5F104AGGSP#V0
R5F104AAGSP#X0, R5F104ACGSP#X0, R5F104ADGSP#X0, R5F104AEGSP#X0,
R5F104AFGSP#X0, R5F104AGGSP#X0
32 pins 32-pin pla s t i c HWQFN
(5 5 mm, 0.5 mm pitch) A R5F104BAANA#U0, R5F104BCANA#U0, R5F104BDANA#U0, R5F104BEANA#U0,
R5F104BFANA#U0, R5F104BGANA#U0
R5F104BAANA#W0, R5F104BCANA#W0, R5F104BDANA#W0, R5F104BEANA#W0,
R5F104BFANA#W0, R5F104BGANA#W0
D R5F104BADNA#U0, R5F104BCDNA#U0, R5F104BDDNA#U0, R5F104BEDNA#U0,
R5F104BFDNA#U0, R5F104BGDNA#U0
R5F104BADNA#W0, R5F104BCDNA#W0, R5F104BDDNA#W0 , R5F104BEDNA#W0,
R5F104BFDNA#W0, R5F104BGDNA#W0
G R5F104BAGNA#U 0, R5F104BCGNA#U0, R5F104BDGNA#U0, R5F104BEGNA#U0,
R5F104BFGNA#U0, R5F104BGGNA#U0
R5F104BAGNA#W0, R5F104BCGNA #W0, R5F104BDGNA#W0, R5F104BEGNA#W0,
R5F104BFGNA#W0, R5F104BGGNA#W0
32-pin plas t i c LQ F P
(7 7, 0.8 mm pitch) A R5F104BAAFP#V0, R5F104BCAFP#V0, R5F104BDAFP#V0, R5F104BEAFP#V0,
R5F104BFAFP#V0, R5F104BGAFP#V0
R5F104BAAFP#X0, R5F104BCAFP#X0, R5F104BDAFP#X0, R5F104BEAFP#X0,
R5F104BFAFP#X0, R5F104BGAFP#X0
D R5F104BADFP#V0, R5F104BCDFP#V0, R5F104BDDFP#V0, R5F104BEDFP#V0,
R5F104BFDFP#V0, R5F104BGDFP#V0
R5F104BADFP#X0, R5F104BCDFP#X0, R5F104 BDDFP#X0, R5F104BEDFP#X0,
R5F104BFDFP#X0, R5F104BGDFP#X0
G R5F104BAGFP#V0, R5F104BCGFP#V0, R5F104BDGFP#V0, R5F104BEGFP#V0,
R5F104BFGFP#V0, R5F104BGGFP#V0
R5F104BAGFP#X0, R5F104BCGFP#X0, R5F104BDGFP#X0, R5F104BEGFP#X0,
R5F104BFGFP#X0, R5F104BGGFP#X0
36 pins 36-pin pla s t i c WFLGA
(4 4 mm, 0.5 mm pitch) A R5F104CAALA#U0, R5F104CCALA#U0, R5F104CDALA#U0, R5F104CEALA#U0,
R5F104CFALA#U0, R5F104CGALA#U0
R5F104CAALA#W0, R5F104CCALA#W0, R5F104CDALA#W0, R5F104CEALA#W0,
R5F104CFALA#W0, R5F104CGALA#W0
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 5 of 187
Oct 25, 2013
Note For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
(2/5)
Pin
count Package Fields of
Application
Note Ordering Part Number
40 pins 40-pin pla s t i c HWQFN
(6 6 mm, 0.5 mm pitch) A R5F104EAANA#U0, R5F104ECANA#U0, R5F104EDANA#U0, R5F104EEANA#U0,
R5F104EFANA#U0, R5F104EGANA#U0, R5F104EHA NA#U0
R5F104EAANA#W0, R5F104ECANA#W0, R5F104EDANA#W0, R5F104EEANA#W0,
R5F104EFANA#W0, R5F104EGANA#W0, R5F104EHANA#W0
D R5F104EADNA#U0, R5F104ECDNA#U0, R5F104EDDNA#U0, R5F104EEDNA#U0,
R5F104EFDNA#U0, R5F104EGDNA#U0, R5F104EHDNA#U0
R5F104EADNA#W0, R5F104ECDNA#W0, R5F104EDDNA#W0 , R5F104EEDNA#W0,
R5F104EFDNA#W0, R5F104EGDNA#W0, R5F104EHDNA#W0
G R5F104EAGNA#U 0, R5F104ECGNA#U0, R5F104EDGNA#U0, R5F104EEGNA#U0,
R5F104EFGNA#U0, R5F104EGGNA#U0, R5F104EHGNA #U0
R5F104EAGNA#W0, R5F104ECGNA#W0, R5F104EDGNA#W0, R5F104EEGNA#W0,
R5F104EFGNA#W0, R5F104EGGNA#W0, R5F104EHG NA#W0
44 pins 44-pin pla s t i c LQ F P
(10 10, 0.8 mm pitch) A R5F104FAAFP#V0, R5F104FCAFP#V0, R5F104FDAFP#V0, R5F104FEAFP#V0,
R5F104FFAFP#V0, R5F104FGAFP#V0, R5F104FHAFP#V0, R5F104FJAFP#V0
R5F104FAAFP#X0, R5F104FCAFP#X0, R5F104FDAFP#X0, R5F104FEAFP#X0,
R5F104FFAFP#X0, R5F104FGAFP#X0, R5F104FHAFP#X0, R5F104FJAFP#X0
D R5F104FADFP#V0, R5F104FCDFP#V0, R5F104FDDFP#V0, R5F104FEDFP#V0,
R5F104FFDFP#V0, R5F104FGDFP#V0, R5F104FHDFP#V0, R5F104FJDFP#V0
R5F104FADFP#X0, R5F104FCDFP#X0, R5F104FDDFP#X0, R5F104FEDFP#X0,
R5F104FFDFP#X0, R5F104FGDFP#X0, R5F104FHDFP#X0, R5F104FJDFP#X0
G R5F104FAGFP#V0, R5F104FCGFP#V0, R5F104FDGFP#V0, R5F104FEGFP#V0,
R5F104FFGFP#V0, R5F104FGGFP#V0, R5F104FHGFP#V0, R5F104FJGFP#V0
R5F104FAGFP#X0, R5F104FCGFP#X0, R5F104FDGFP#X0, R5F104FEGFP#X0,
R5F104FFGFP#X0, R5F104FGGFP#X0, R5F104FHGFP#X0, R5F104FJGFP#X0
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 6 of 187
Oct 25, 2013
Note For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
(3/5)
Pin
count Package Fields of
Application
Note Ordering Part Number
48 pins 48-pin pla s t i c LFQFP
(7 7 mm, 0.5 mm pitch) A R5F104GAAFB#V0, R5F104GCAFB#V0, R5F104GDAFB#V0, R5F104GEAFB#V0,
R5F104GFAFB#V0, R5F104GGAFB#V0, R5F104GHAFB#V0, R5F104GJAFB#V0
R5F104GAAFB#X0, R5F104GCAFB#X0, R5F104GDAFB#X0, R5F104GEAFB#X0,
R5F104GFAFB#X0, R5F104GGAFB#X0, R5F104GHAFB#X0, R5F104GJAFB#X0
D R5F104GADFB#V0, R5F104GCDFB#V0, R5F104GDDFB#V0, R5F104GEDFB#V0,
R5F104GFDFB#V0, R5F104GGDFB#V0, R5F104GHDFB#V0, R5F104GJDFB#V0
R5F104GADFB#X0, R5F104GCDFB#X0, R5F10 4GDDFB#X0, R5F104GEDFB#X0,
R5F104GFDFB#X0, R5F104GGDFB#X0, R5F104GHDFB#X0, R5F104GJDFB#X0
G R5F104GAGFB#V0, R5F104GCGFB#V0, R5F104GDGFB#V0, R5F104GEGFB#V0,
R5F104GFGFB#V0, R5F104GGGFB#V0, R5F104GHGFB#V0, R5F104GJGFB#V0
R5F104GAGFB#X0, R5F104GCGFB#X0, R5F104GDGFB#X0, R5F104GEGFB#X0,
R5F104GFGFB#X0, R5F104GGGFB#X0, R5F104GHGFB#X0, R5F104GJGFB#X0
48-pin plastic HWQFN
(7 7 mm, 0.5 mm pitch) A R5F104GAANA#U0, R5F104GCANA#U0, R5F104GDANA#U0, R5F104GEANA#U0,
R5F104GFANA#U0, R5F104GGANA#U0, R5F104G HANA#U0, R5F104GJANA#U0
R5F104GAANA#W0, R5F104GCANA#W0, R5F104GDANA#W0, R5F104GEANA#W0,
R5F104GFANA#W0, R5F104GGANA#W0, R5F104GHANA#W0, R5F104GJANA#W0
D R5F104GADNA#U0, R5F104GCDNA#U0, R5F104GDDNA#U0, R5F104GEDNA #U0,
R5F104GFDNA#U0, R5F104GGDNA#U0, R5F104GHDNA#U0, R5F104GJDNA#U0
R5F104GADNA#W0, R5F104GCDNA#W0, R5F104GDDNA#W0, R5F104GEDNA#W0,
R5F104GFDNA#W0, R5F104GGDNA#W0, R5F104GHDNA#W0, R5F104GJDNA#W0
G R5F104GAGNA#U0, R5F104GCGNA#U0, R5F104GDGNA#U0, R5F104GEGNA#U0,
R5F104GFGNA#U0, R5F104GGGNA#U0, R5F104GHGNA#U0, R5F104GJGNA#U0
R5F104GAGNA# W0, R5F 104GCGNA#W0, R5F104 GDGNA#W0, R5F1 04GEGNA#W0,
R5F104GFGNA#W0, R5F104GGGNA#W0, R5F104G HGNA#W0, R5F104 GJGNA#W0
52 pins 52-pin pla s t i c LQ F P
(10 10 mm, 0.65 mm pitch) A R5F104JCAFA#V0, R5F104JDAFA#V0, R5F104JEAFA#V0, R5F104JFAFA#V0,
R5F104JGAFA#V0, R5F104JHAFA#V0, R5F104JJAFA#V0
R5F104JCAFA#X0, R5F104JDAFA#X0, R5F104 JEAF A#X0, R5F104JFAFA#X0,
R5F104JGAFA#X0, R5F104JHAFA#X0, R5F104JJAFA#X0
D R5F104JCDFA#V0, R5F104JDDFA#V0, R5F104JEDFA#V0, R5F104JFDFA#V0,
R5F104JGDFA#V0, R5F104JHDFA#V0, R5F104JJDFA#V0
R5F104JCDFA#X0, R5F104JDDFA#X0, R5F104JEDFA#X0, R5F104JFDFA#X0,
R5F104JGDFA#X0, R5F104JHDFA#X0, R5F104JJDFA#X0
G R5F104JCGFA#V0, R5F104JDGFA#V0, R5F104JEGFA#V0, R5F104JFGFA#V0,
R5F104JGGFA#V0, R5F104JHGFA#V0, R5F104JJGFA#V0
R5F104JCGFA#X0, R5F104JDGFA#X0, R5F104JEGFA#X0, R5F104JFGFA#X0,
R5F104JGGFA#X0, R5F104JHGFA#X0, R5F104JJGFA#X0
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 7 of 187
Oct 25, 2013
Note For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
(4/5)
Pin count Package Fields of
Application
Note Ordering Part Number
64 pins 64-pin plastic LQFP
(12 12 mm, 0.65 mm pitch) A R5F104LCAFA#V0, R5F104LDAFA#V0, R5F104LEAFA#V0, R5F104LFAFA#V0,
R5F104LGAFA#V0, R5F104LHAFA#V0, R5F104LJAF A#V0
R5F104LCAFA#X0, R5F104LDAFA#X0, R5F104LEAFA#X0, R5F104LFAFA#X0,
R5F104LGAFA#X0, R5F104LHAFA#X0, R5F104LJAF A#X0
D R5F104LCDFA#V0, R5F104LDDFA#V0, R5F104LEDFA#V0, R5F104LFDF A#V0,
R5F104LGDFA#V0, R5F104LHDFA#V0, R5F104LJDFA#V0
R5F104LCDFA#X0, R5F104LDDFA#X0, R5F104LEDFA#X0, R5F104LFDFA#X0,
R5F104LGDFA#X0, R5F104LHDFA#X0, R5F104LJDFA#X0
G R5F104LCGF A#V0, R5F104LDGFA#V0, R5F104LEGFA#V0, R5F104LFGFA#V0,
R5F104LGGFA#V0, R5F104LHGFA#V0, R5F104LJGFA#V0
R5F104LCGFA#X0, R5F104LDGFA#X0, R5F104LEGFA#X0, R5F104LFGFA#X0,
R5F104LGGFA#X0, R5F104LHGFA#X0, R5F104LJGFA#X0
64-pin plastic LFQFP
(10 10 mm, 0.5 mm pitch) A R5F104LCAFB#V0, R5F104LDAFB#V0, R5F104LEAFB#V0, R5F104LFAFB#V0,
R5F104LGAFB#V0, R5F104LHAFB#V0, R5F104LJAFB#V0
R5F104LCAFB#X0, R5F104LDAFB#X0, R5F104LEAFB#X0, R5F104LFAFB#X0,
R5F104LGAFB#X0, R5F104LHAFB#X0, R5F104LJAFB#X0
D R5F104LCDFB#V0, R5F104LDDFB#V0, R5F104LEDFB#V0, R5F104LFDFB#V0,
R5F104LGDFB#V0, R5F104LHDFB#V0, R5F104LJDFB#V0
R5F104LCDFB#X0, R5F104LDDFB#X0, R5F104LEDFB#X0, R5F104LFDFB#X0,
R5F104LGDFB#X0, R5F104LHDFB#X0, R5F104LJDFB#X0
G R5F104LCGFB #V0, R5F104LDGFB#V0, R5F104LEGFB#V0, R5F104LFGFB#V0,
R5F104LGGFB#V0, R5F104LHGFB#V0, R5F104LJGFB#V0
R5F104LCGFB#X0, R5F104LDGFB#X0, R5F104LEGFB#X0, R5F104LFGFB#X0,
R5F104LGGFB#X0, R5F104LHGFB#X0, R5F104LJGFB#X0
64-pin plastic FLGA
(5 5 mm, 0.5 mm pitch) A R5F104LCALA#U0, R5F104LDALA#U0, R5F104LEALA#U0, R5F104LFALA#U0,
R5F104LGALA#U0, R5F104LHALA#U0, R5F104LJALA#U0
R5F104LCALA#W0, R5F104LDALA#W0, R5F104LEALA#W0, R5F104LFALA#W0,
R5F104LGALA#W0, R5F104LHALA#W0, R5F104LJALA#W0
64-pin plastic LQFP
(14 14 mm, 0.8 mm pitch) A R5F104LCAFP#V0, R5F104LDAFP#V0, R5F104LEAFP#V0, R5F104LFAFP#V0,
R5F104LGAFP#V0, R5F104LHAFP#V0, R5F104LJAFP#V0
R5F104LCAFP#X0, R5F104LDAFP#X0, R5F104LEAFP#X0, R5F104LFAFP#X0,
R5F104LGAFP#X0, R5F104LHAFP#X0, R5F104LJAFP#X0
D R5F104LCDFP#V0, R5F104LDDFP#V0, R5F104LEDFP#V0, R5F104LFDFP#V0,
R5F104LGDFP#V0, R5F104LHDFP#V0, R5F104LJDFP#V0
R5F104LCDFP#X0, R5F104LDDFP#X0, R5F104LEDFP#X0, R5F104LFDFP#X0,
R5F104LGDFP#X0, R5F104LHDFP#X0, R5F104LJDFP#X0
G R5F104LCGFP #V0, R5F104LDGFP#V0, R5F104LEGFP#V0, R5F104LFGFP#V0,
R5F104LGGFP#V0, R5F104LHGFP#V0, R5F104LJGFP#V0
R5F104LCGFP#X0, R5F104LDGFP#X0, R5F104LEGFP#X0, R5F104LFGFP#X0,
R5F104LGGFP#X0, R5F104LHGFP#X0, R5F104LJGFP#X0
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 8 of 187
Oct 25, 2013
Note For the fields of application, refer to Figure 1 - 1 Part Number, Memory Size, and Package of RL78/G14.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part
numbers, refer to the target product page of the Renesas Electronics website.
(5/5)
Pin count Package Fields of
Application
NoteNote Ordering Part Number
80 pins 80-pin plastic LFQFP
(12 12 mm, 0.5 mm pitch) A R5F104MFAFB#V0, R5F104MGAFB#V0, R5F104MHAFB#V0, R5F104MJAFB#V0
R5F104MFAFB#X0, R5F104MGAFB#X0, R5F104MHAFB#X0, R5F104MJAFB#X0
D R5F104MFDFB#V0, R5F104MGDFB#V0, R5F104MHDFB#V0, R5F104MJDFB#V0
R5F104MFDFB#X0, R5F104MGDFB#X0, R5F104 MHDFB #X0, R5F104MJDFB#X0
G R5F104MFGFB#V0, R5F104MGGFB#V0, R5F104MHGFB#V0, R5F104MJGFB#V0
R5F104MFGFB#X0, R5F104MGGFB#X0, R5F104MHGFB#X0, R5F104MJGFB#X0
80-pin plastic LQFP
(14 14 mm, 0.65 mm pitch) A R5F104MFAFA#V0, R5F104MGAFA#V0, R5F104MHAFA#V0, R5F104MJAFA#V0
R5F104MFAFA#X0, R5F104MGAFA#X0, R5F104MHAFA#X0, R5F104MJAFA#X0
D R5F104MFDFA#V0, R5F104MGDFA#V0, R5F104MHDFA#V0, R5F104MJDFA#V0
R5F104MFDFA#X0, R5F104MGDFA#X0, R5F104MHDFA#X0, R5F104MJDFA#X0
G R5F104MFGFA#V0, R5F104MGGF A#V0, R5F104MHGFA#V0, R5F104MJGFA#V0
R5F104MFGFA#X0, R5F104MGGFA#X0, R5F104MHGFA#X0, R5F104MJGFA#X0
100 pins 100-pin plastic LFQFP
(14 14 mm, 0.5 mm pitch) A R5F104PFAFB#V0, R5F104PGAFB#V0, R5F104PHAFB#V0, R5F104PJAFB#V0
R5F104PFAFB#X0, R5F104PGAFB#X0, R5F104PHAFB#X0, R5F104PJAFB#X0
D R5F104PFDFB#V0, R5F104PGDFB#V0, R5F104PHDFB#V0, R5F104PJDFB#V0
R5F104PFDFB#X0, R5F104PGDFB#X0, R5F104PHDFB#X0, R5F104PJDFB#X0
G R5F104PFGFB #V0, R5F104PGGFB#V0, R5F104PHGFB#V0, R5F104PJGFB#V0
R5F104PFGFB#X0, R5F104PGGFB #X0, R5F104PHGFB#X0, R5F104PJGFB#X0
100-pin plastic LQFP
(14 20 mm, 0.65 mm pitch) A R5F104PFAFA#V0, R5F104PGAFA#V0, R5F104PHAFA#V0, R5F104PJAFA#V0
R5F104PFAFA#X0, R5F104PGAFA#X0, R5F104PHAFA#X0, R5F104PJAFA#X0
D R5F104PFDFA#V0, R5F104PGDFA#V0, R5F104PHDFA#V0, R5F104PJDFA#V0
R5F104PFDFA#X0, R5F104PGDFA#X0, R5F104PHDFA#X0, R5F104PJDFA#X0
G R5F104PFGFA#V0, R5F104PGGFA#V0, R5F104PHGFA#V0, R5F104PJGFA#V0
R5F104PFGFA#X0, R5F104PGGFA#X0, R5F104PHGFA#X0, R5F104PJGFA#X0
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 9 of 187
Oct 25, 2013
1.3 Pin Configuration (Top View)
1.3.1 30-pin products
• 30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P21/ANI1/AVREFM
P22/ANI2/ANO0 Note
P23/ANI3
P147/ANI18/VCOUT1 Note
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/SCK00/SCL00/TRJO0
P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0
P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0 Note
P40/TOOL0
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P60/SCLA0
P61/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0/SSI00/(TRJIO0)
P20/ANI0/AVREFP
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 10 of 187
Oct 25, 2013
1.3.2 32-pin products
• 32-pin plastic HWQFN (5 5 mm, 0.5 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
Remark 3. It is recommended to connect an exposed die pad to VSS.
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/SCK00/SCL00/TRJO0
P70
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P62/SSI00
P61/SDAA0
P60/SCLA0
exposed die pad
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32 1
P147/ANI18/VCOUT1Note
P23/ANI3/ANO1Note
P22/ANI2/ANO0Note
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0
P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)
2345678
242322 21 20 19 1817
P40/TOOL0
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
RESET
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RXD0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P12/SO11/TRDIOB1/IVREF1Note
P11/SI11/SDA11/TRDIOC1
P10/SCK11/SCL11/TRDIOD1
P120/ANI19/VCOUT0Note
P21/ANI1/AVREFM
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 11 of 187
Oct 25, 2013
• 32-pin plastic LQFP (7 7 mm, 0.8 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/SCK00/SCL00/TRJO0
P70
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P62/SSI00
P61/SDAA0
P60/SCLA0
16
15
14
13
12
11
10
9
25
26
27
28
29
30
31
32 1
P147/ANI18/VCOUT1 Note
P23/ANI3/ANO1 Note
P22/ANI2/ANO0 Note
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1/TRGCLKB/TRJIO0
P00/ANI17/TI00/TxD1/TRGCLKA/(TRJO0)
2345678
242322 21 20 19 1817
P40/TOOL0
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
RESET
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TxD0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0 Note/(RxD0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P12/SO11/TRDIOB1/IVREF1 Note
P11/SI11/SDA11/TRDIOC1
P10/SCK11/SCL11/TRDIOD1
P120/ANI19/VCOUT0 Note
P21/ANI1/AVREFM
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 12 of 187
Oct 25, 2013
1.3.3 36-pin products
• 36-pin plastic WFLGA (4 × 4 mm, 0.5 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
ABCDEF
6P60/SCLA0 VDD P121/X1 P122/X2/EXCLK P137/INTP0 P40/TOOL0 6
5P62/SSI00 P61/SDAA0 VSS REGC RESET P120/ANI19/
VCOUT0 Note 5
4P72/SO21 P71/SI21/
SDA21 P14/RxD2/SI20/
SDA20/TRDIOD0/
(SCLA0)
P31/TI03/TO03/
INTP4/PCLBUZ0/
(TRJIO0)
P00/TI00/TxD1/
TRGCLKA/
(TRJO0)
P01/TO00/
RxD1/TRGCLKB/
TRJIO0 4
3
P50/INTP1/
SI00/RxD0/
TOOLRxD/
SDA00/TRGIOA/
(TRJO0)
P70/SCK21/
SCL21 P15/PCLBUZ1/
SCK20/SCL20/
TRDIOB0/
(SDAA0)
P22/ANI2/
ANO0 Note P20/ANI0/
AVREFP
P21/ANI1/
AVREFM 3
2
P30/INTP3/
SCK00/SCL00/
TRJO0
P16/TI01/TO01/
INTP5/TRDIOC0/
IVREF0 Note/
(RXD0)
P12/SO11/
TRDIOB1/
IVREF1 Note
P11/SI11/
SDA11/
TRDIOC1
P24/ANI4 P23/ANI3/
ANO1 Note 2
1
P51/INTP2/
SO00/TxD0/
TOOLTxD/
TRGIOB
P17/TI02/TO02/
TRDIOA0/
TRDCLK/
IVCMP0 Note/
(TXD0)
P13/TxD2/
SO20/TRDIOA1/
IVCMP1 Note
P10/SCK11/
SCL11/
TRDIOD1
P147/ANI18/
VCOUT1 Note P25/ANI5
1
ABCDEF
Top View Bottom View
6
5
4
3
2
1
INDEX MARK
ABCDEF F EDCBA
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 13 of 187
Oct 25, 2013
1.3.4 40-pin products
• 40-pin plastic HWQFN (6 6 mm, 0.5 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
Remark 3. It is recommended to connect an exposed die pad to VSS.
20
19
18
17
16
15
14
13
12
11
31
32
33
34
35
36
37
38
39
40
exposed die pad
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1Note
P22/ANI2/ANO0Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1/TRGCLKB/TRJIO0
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0Note
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P62/SSI00
P61/SDAA0
P60/SCLA0
12345678910
3029 28 27 2625 24 23 22 21
VDD
VSS
REGC
P121/X1
P137/INTP0
P123/XT1
P124/XT2/EXCLKS
RESET
P40/TOOL0
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0Note/(TXD0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0Note/(RXD0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P12/SO11/TRDIOB1/IVREF1Note
P11/SI11/SDA11/TRDIOC1
P10/SCK11/SCL11/TRDIOD1
P147/ANI18/VCOUT1 Note
P122/X2/EXCLK
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 14 of 187
Oct 25, 2013
1.3.5 44-pin products
• 44-pin plastic LQFP (10 × 10 mm, 0.8 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1Note
P22/ANI2/ANO0Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1/TRGCLKB/TRJIO0
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P120/ANI19/VCOUT0Note
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0/(TRJIO0)
P63
P62/SSI00
P61/SDAA0
P60/SCLA0
333231 3029 28 27 26 25 24
1234567891011
23
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0 Note/(TXD0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0Note/(RXD0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P12/SO11/TRDIOB1/IVREF1Note
P11/SI11/SDA11/TRDIOC1
P10/SCK11/SCL11/TRDIOD1
P146
P147/ANI18/VCOUT1Note
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 15 of 187
Oct 25, 2013
1.3.6 48-pin products
• 48-pin plastic LFQFP (7 7 mm, 0.5 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
P147/ANI18/VCOUT1Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P120/ANI19/VCOUT0 Note
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
123456789101112
36 35 34 33 32 31 30 29 28 27 26 25
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3/SO01
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63
P62/SSI00
P61/SDAA0
P60/SCLA0 P140/PCLBUZ0/INTP6
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P01/TO00/RxD1/TRGCLKB/TRJIO0
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0Note
P23/ANI3/ANO1Note
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 16 of 187
Oct 25, 2013
• 48-pin plastic HWQFN (7 7 mm, 0.5 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
Remark 3. It is recommended to connect an exposed die pad to VSS.
P147/ANI18/VCOUT1Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1Note
P13/TxD2/SO20/TRDIOA1/IVCMP1Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P120/ANI19/VCOUT0 Note
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
123456789101112
36 35 34 33 32 31 30 29 28 27 26 25
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3/SO01
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63
P62/SSI00
P61/SDAA0
P60/SCLA0 P140/PCLBUZ0/INTP6
P00/TI00/TxD1/TRGCLKA/(TRJO0)
P01/TO00/RxD1/TRGCLKB/TRJIO0
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0Note
P23/ANI3/ANO1Note
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
exposed die pad
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 17 of 187
Oct 25, 2013
1.3.7 52-pin products
• 52-pin plastic LQFP (10 10 mm, 0.65 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3/SO01
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63
P62/SSI00
P61/SDAA0
P60/SCLA0
26
25
24
23
22
21
20
19
18
17
16
15
14
40
41
42
43
44
45
46
47
48
49
50
51
52
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1Note
P22/ANI2/ANO0Note
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P03/ANI16/RxD1
P02/ANI17/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P140/PCLBUZ0/INTP6
RESET
P41/(TRJIO0)
P40/TOOL0
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
VDD
P147/ANI18/VCOUT1Note
P146
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1 Note
P13/TxD2/SO20/TRDIOA1/IVCMP1 Note
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/PCLBUZ1/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0Note/(RXD0)
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0Note/(TXD0)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
12345678910 131211
39 38 37 36 35 34 33 32 31 30 272829
P120/ANI19/VCOUT0 Note
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 18 of 187
Oct 25, 2013
1.3.8 64-pin products
• 64-pin plastic LQFP (14 14 mm, 0.8 mm pitch)
• 64-pin plastic LQFP (12 12 mm, 0.65 mm pitch)
• 64-pin plastic LFQFP (10 10 mm, 0.5 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution 1. Make EVSS0 pin the same potential as VSS pin.
Caution 2. Make VDD pin the potential that is higher than EVDD0 pin.
Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to
separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 19 of 187
Oct 25, 2013
• 64-pin plastic FLGA (5 5 mm, 0.5 mm pitch)
Note Mounted on the 96 KB or more code flash memory products.
Caution 1. Make EVSS0 pin the same potential as VSS pin.
Caution 2. Make VDD pin the potential that is higher than EVDD0 pin.
Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to
separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
Remark 4. It is recommended to connect an exposed die pad to VSS.
ABCDEFGH
8EVDD0 EVSS0 P121/X1 P122/X2/
EXCLK P137/INTP0 P123/XT1 P124/XT2/
EXCLKS P120/ANI19/
VCOUT0 Note 8
7P60/SCLA0 VDD VSS REGC RESET P01/TO00/
TRGCLKB/
TRJIO0
P00/TI00/
TRGCLKA/
(TRJO0)
P140/
PCLBUZ0/
INTP6 7
6P61/SDAA0 P62/SSI00 P63 P40/TOOL0 P41/(TRJIO0) P43/(INTP9) P02/ANI17/
SO10/TxD1 P141/
PCLBUZ1/
INTP7 6
5
P77/KR7/
INTP11/(TXD2) P31/TI03/
TO03/INTP4/
(PCLBUZ0)/
(TRJIO0)
P53/(INTP2) P42/(INTP8) P03/ANI16/
SI10/RxD1/
SDA10
P04/SCK10/
SCL10 P130 P20/ANI0/
AVREFP 5
4
P75/KR5/
INTP9/
SCK01/
SCL01
P76/KR6/
INTP10/
(RXD2)
P52/(INTP1) P54/(INTP3) P16/TI01/
TO01/INTP5/
TRDIOC0/
IVREF0 Note/
(SI00)/(RXD0)
P21/ANI1/
AVREFM
P22/ANI2/
ANO0 Note P23/ANI3/
ANO1 Note
4
3
P70/KR0/
SCK21/
SCL21
P73/KR3/
SO01 P74/KR4/
INTP8/SI01/
SDA01
P17/TI02/TO02/
TRDIOA0/
TRDCLK/
IVCMP0 Note/
(SO00)/(TXD0)
P15/SCK20/
SCL20/
TRDIOB0/
(SDAA0)
P12/SO11/
TRDIOB1/
IVREF1 Note/
(INTP5)
P24/ANI4 P26/ANI6
3
2
P30/INTP3/
RTC1HZ/
SCK00/
SCL00/TRJO0
P72/KR2/
SO21 P71/KR1/
SI21/SDA21 P06/(INTP11)/
(TRJIO0) P14/RxD2/
SI20/SDA20/
TRDIOD0/
(SCLA0)
P11/SI11/
SDA11/
TRDIOC1
P25/ANI5 P27/ANI7
2
1
P05/(INTP10) P50/INTP1/
SI00/RxD0/
TOOLRxD/
SDA00/
TRGIOA/
(TRJO0)
P51/INTP2/
SO00/TxD0/
TOOLTxD/
TRGIOB
P55/
(PCLBUZ1)/
(SCK00)/
(INTP4)
P13/TxD2/
SO20/
TRDIOA1/
IVCMP1 Note
P10/SCK11/
SCL11/
TRDIOD1
P146 P147/ANI18/
VCOUT1 Note
1
ABCDEFGH
1
HGFEDCBA
2
3
4
5
6
7
8
A B CDE F GH
Top View Bottom View
INDEX MARK
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 20 of 187
Oct 25, 2013
1.3.9 80-pin products
• 80-pin plastic LQFP (14 14 mm, 0.65 mm pitch)
• 80-pin plastic LFQFP (12 12 mm, 0.5 mm pitch)
Caution 1. Make EVSS0 pin the same potential as VSS pin.
Caution 2. Make VDD pin the potential that is higher than EVDD0 pin.
Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to
separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1
P22/ANI2/ANO0
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
P142/SCK30/SCL30
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
P05
P06/(TRJIO0)
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RxD2)
P77/KR7/INTP11/(TxD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63/SDAA1
P62/SSI00/SCLA1
P61/SDAA0
P60/SCLA0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 1011121314151617181920
60 5958 57 56 55 54 5352 51 50 49 48 4746 45 44 43 42 41
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19/VCOUT0
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01/(INTP9)
P42/(INTP8)
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
P153/ANI11
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
P146
P111
P110/(INTP11)
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RxD0)
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0/(SO00)/(TxD0)
P55/(PCLBUZ1)/(SCK00)/(INTP4)
P54/SCK31/SCL31/(INTP3)
P53/SI31/SDA31/(INTP2)
P52/SO31/(INTP1)
P51/INTP2/SO00/TxD0/TOOLTxD/TRGIOB
P50/INTP1/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 21 of 187
Oct 25, 2013
1.3.10 100-pin products
• 100-pin plastic LFQFP (14 14 mm, 0.5 mm pitch)
Caution 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
Caution 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).
Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate power s to the V DD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1
pins to separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
1 2 3 4 5 6 7 8 9 1011121314151617181920
P142/SCK30/SCL30
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19/VCOUT0
P47/INTP2
P46/INTP1
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
21 22 23 24 25
EVSS0
VDD
EVDD0
P60/SCLA0
P61/SDAA0
P81/(SI10)/(RxD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVSS1
P05
P06/(TRJIO0)
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RxD2)
P77/KR7/INTP11/(TxD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P63/SDAA1
P62/SSI00/SCLA1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
45
46
47
48
49
50
75 74 73 72 71 70 69 6867 66 65 64 63 6261 60 59 58 57
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
P146/(INTP4)
P111
P110/(INTP11)
P101
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RxD0)
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0/(SO00)/(TxD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3/ANO1
P22/ANI2/ANO0
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00/TRGCLKB/TRJIO0
P00/TI00/TRGCLKA/(TRJO0)
P145
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P151/ANI9 81
P152/ANI10 80
P153/ANI11 79
P154/ANI12 78
P155/ANI13 77
P156/ANI14 76 56
P52/SO31
55
P51/SO00/TxD0/TOOLTxD/TRGIOB
54
P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
53
EVDD1
52
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
51
P87/(INTP9)
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TxD1)
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 22 of 187
Oct 25, 2013
• 100-pin plastic LQFP (14 20 mm, 0.65 mm pitch)
Caution 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
Caution 2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).
Caution 3. Connect the REGC pin to VSS pin via a capacitor (0.47 to 1 F).
Remark 1. For pin identification, see 1.4 Pin Identification.
Remark 2. When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced,
it is recommended to supply separate power s to the V DD, EVDD0 and EVDD1 pins and connect the VSS, EVSS0 and EVSS1
pins to separate ground lines.
Remark 3. Functions in parentheses in the above figure can be assigned via settings in the periphe ral I/O re direction register 0, 1
(PIOR0, 1).
P146/(INTP4)
P111
P110/(INTP11)
P101
P10/SCK11/SCL11/TRDIOD1
P11/SI11/SDA11/TRDIOC1
P12/SO11/TRDIOB1/IVREF1/(INTP5)
P13/TxD2/SO20/TRDIOA1/IVCMP1
P14/RxD2/SI20/SDA20/TRDIOD0/(SCLA0)
P15/SCK20/SCL20/TRDIOB0/(SDAA0)
P16/TI01/TO01/INTP5/TRDIOC0/IVREF0/(SI00)/(RxD0)
P17/TI02/TO02/TRDIOA0/TRDCLK/IVCMP0/(SO00)/(TxD0)
P57/(INTP3)
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
P51/SO00/TxD0/TOOLTxD/TRGIOB
P50/SI00/RxD0/TOOLRxD/SDA00/TRGIOA/(TRJO0)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1920 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 7574 73 72 71 70 69 68 67 66 65 64 63 6261 60 59 58 57 56 55 54 53 52 51
P60/SCLA0
P61/SDAA0
P62/SSI00/SCLA1
P63/SDAA1
P31/TI03/TO03/INTP4/(PCLBUZ0)/(TRJIO0)
P64/TI10/TO10
P65/TI11/TO11
P66/TI12/TO12
P67/TI13/TO13
P77/KR7/INTP11/(TxD2)
P76/KR6/INTP10/(RxD2)
P75/KR5/INTP9
P74/KR4/INTP8
P73/KR3
P72/KR2/SO21
P71/KR1/SI21/SDA21
P70/KR0/SCK21/SCL21
P06/(TRJIO0)
P05
EVSS1
P80/(SCK10)/(SCL10)
P81/(SI10)/(RxD1)/(SDA10)
P82/(SO10)/(TxD1)
P83
P84/(INTP6)
P85/(INTP7)
P86/(INTP8)
P87/(INTP9)
P30/INTP3/RTC1HZ/SCK00/SCL00/TRJO0
EVDD1
P140/PCLBUZ0/INTP6
P141/PCLBUZ1/INTP7
P142/SCK30/SCL30
P143/SI30/RxD3/SDA30
P144/SO30/TxD3
P145
P00/TI00/TRGCLKA/(TRJO0)
P01/TO00/TRGCLKB/TRJIO0
P02/ANI17/SO10/TxD1
P03/ANI16/SI10/RxD1/SDA10
P04/SCK10/SCL10
P102
P130
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2/ANO0
P23/ANI3/ANO1
P24/ANI4
P25/ANI5
P26/ANI6
P27/ANI7
P150/ANI8
P151/ANI9
P152/ANI10
P153/ANI11
P154/ANI12
P155/ANI13
P156/ANI14
P100/ANI20/(INTP10)
P147/ANI18/VCOUT1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P120/ANI19/VCOUT0
P47/INTP2
P46/INTP1
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42
P41/(TRJIO0)
P40/TOOL0
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
VSS
EVSS0
VDD
EVDD0
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 23 of 187
Oct 25, 2013
1.4 Pin Identification
ANI0 to ANI14,: Analog input
ANI16 to ANI20
ANO0, ANO1: Analog output
AVREFM: A/D converter reference
potential ( side) input
AVREFP: A/D converter reference
potential (+ side) input
EVDD0, EVDD1: Power supply for port
EVSS0, EVSS1: Ground for port
EXCLK: External clock input
(main system clock)
EXCLKS: External clock input
(subsystem clock)
INTP0 to INTP11: External interrupt input
IVCMP0, IVCMP1: Comparator input
IVREF0, IVREF1: Comparator reference input
KR0 to KR7: Key return
P00 to P06: Port 0
P10 to P17: Port 1
P20 to P27: Port 2
P30, P31: Port 3
P40 to P47: Port 4
P50 to P57: Port 5
P60 to P67: Port 6
P70 to P77: Port 7
P80 to P87: Port 8
P100 to P102: Port 10
P110, P111: Port 11
P120 to P124: Port 12
P130, P137: Port 13
P140 to P147: Port 14
P150 to P156: Port 15
PCLBUZ0, PCLBUZ1: Programmable clock
output/buzzer output
REGC: Regulator capacitance
RESET: Reset
RTC1HZ: Real-time clock correction
clock
(1 Hz) output
RxD0 to RxD3: Receive data
SCK00, SCK01, SCK10,: Serial clock input/output
SCK11, SCK20, SCK21,
SCK30, SCK31
SCLA0, SCLA1,: Serial clock input/output
SCL00, SCL01, SCL10, SCL11,:
Serial clock output
SCL20, SCL21, SCL30,
SCL31
SDAA0, SDAA1, SDA00,: Serial data input/output
SDA01, SDA10, SDA11,
SDA20, SDA21, SDA30,
SDA31
SI00, SI01, SI10, SI11,: Serial data input
SI20, SI21, SI30, SI31
SO00, SO01, SO10,: Serial data output
SO11, SO20, SO21,
SO30, SO31
SSI00: Serial interface chip select input
TI00 to TI03,: Timer input
TI10 to TI13
TO00 to TO03,: Timer output
TO10 to TO13, TRJO0
TOOL0: Data input/output for tool
TOOLRxD, TOOLTxD: Data input/output for external device
TRDCLK, TRGCLKA,: Timer external input clock
TRGCLKB
TRDIOA0, TRDIOB0,: Timer input/output
TRDIOC0, TRDIOD0,
TRDIOA1, TRDIOB1,
TRDIOC1, TRDIOD1,
TRGIOA, TRGIOB, TRJIO0
TxD0 to TxD3: Transmit data
VCOUT0, VCOUT1: Comparator output
VDD: Power supply
VSS: Ground
X1, X2: Crystal oscillator (main system clock)
XT1, XT2: Crystal oscillator (subsystem clock)
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 24 of 187
Oct 25, 2013
1.5 Block Diagram
1.5.1 30-pin products
Note Mounted on the 96 KB or more code flash memory products.
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P01
TxD1/P00
SCL00/P30
SDA00/P50
TI02/TO02/P17
TI03/TO03/P31
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL)
4ANI0 /P20 to
ANI3/P23
SCK11/P10
SO11/P12
SI11/P11
SCL11/P10
SDA11/P11
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
VSS TOOLRxD/P50,
TOOLTxD/P51
VDD
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
INTP5/P16
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
RxD2/P14
TxD2/P13
SCL20/P15
SDA20/P14
SCK20/P15
SO20/P13
SI20/P14
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 toTRDIOD1/P10
3
TIMER RJ TRJIO0/P01
TRJO0/P30
SSI00/P31
ch0
TIMER ARRAY
UNIT (4ch)
ch1
ch2
ch3
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
CSI11
IIC00
IIC11
TO00/P01
RxD0/P50 (LINSEL)
SERIAL ARRAY
UNIT1 (2ch)
UART2
CSI20
IIC20
PORT 1 P10 to P17
8
PORT 2 P20 to P23
4
PORT 3 P30, P31
2
PORT 0 P00, P01
2
PORT 5 P50, P51
2
PORT 6 P60, P61
2
PORT 4 P40
P120
PORT 12 P121, P122
P137
PORT 13
P147PORT 14
A/D CONVERTER ANI16/P01, ANI17/P00
ANI18/P147, ANI19/P120
4
AVREFP/P20
AVREFM/P21
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
X2/EXCLK/P122
X1/P121
RESET
2
2
ANO0/P22
D/A CONVERTER Note
COMPARATOR Note
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
2
CODE FLASH MEMORY
DATA FLASH MEMORY
PCLBUZ0/P31,
PCLBUZ1/P15
2
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
MULTIPLI E R &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 25 of 187
Oct 25, 2013
1.5.2 32-pin products
Note Mounted on the 96 KB or more code flash memory products.
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P01
TxD1/P00
SCL00/P30
SDA00/P50
TI02/TO02/P17
TI03/TO03/P31
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL )
4ANI0 /P20 to
ANI3/P23
SCK11/P10
SO11/P12
SI11/P11
SCL11/P10
SDA11/P11
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
VSS TOOLRxD/P50,
TOOLTxD/P51
VDD
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
INTP5/P16
RxD2/P14
TxD2/P13
SCL20/P15
SDA20/P14
SCK20/P15
SO20/P13
SI20/P14
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 toTRDIOD1/P10
3
TIMER RJ TRJIO0/P01
TRJO0/P30
SSI00/P62
ch0
TIMER ARRAY
UNIT (4ch)
ch1
ch2
ch3
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
CSI11
IIC00
IIC11
TO00/P01
RxD0/P50 (LINSEL)
SERIAL ARRAY
UNIT1 (2ch)
UART2
CSI20
IIC20
PORT 1 P10 to P17
8
PORT 2 P20 to P23
4
PORT 3 P30, P31
2
PORT 0 P00, P01
2
PORT 5 P50, P51
2
PORT 6 P60 to P62
3
P120
PORT 12 P121, P122
P137
PORT 13
P147PORT 14
A/D CONVERTER ANI16/P01, ANI17/P00
ANI18/P147, ANI19/P120
4
AVREFP/P20
AVREFM/P21
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
X2/EXCLK/P122
X1/P121
RESET
2
2
ANO0/P22
D/A CONVERTER Note
COMPARATOR Note
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
2
ANO1/P23
PORT 4 P40
PORT 7 P70
CODE FLASH MEMORY
DATA FLASH MEMORY
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
PCLBUZ0/P31,
PCLBUZ1/P15
2
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 26 of 187
Oct 25, 2013
1.5.3 36-pin products
Note Mounted on the 96 KB or more code flash memory products.
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P01
TxD1/P00
SCL00/P30
SDA00/P50
TI02/TO02/P17
TI03/TO03/P31
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL )
6ANI0 /P20 to
ANI5/P25
SCK11/P10
SO11/P12
SI11/P11
SCL11/P10
SDA11/P11
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
VSS TOOLRxD/P50,
TOOLTxD/P51
VDD
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
INTP5/P16
RxD2/P14
TxD2/P13
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 toTRDIOD1/P10
3
TIMER RJ TRJIO0/P01
TRJO0/P30
SSI00/P62
ch0
TIMER ARRAY
UNIT (4ch)
ch1
ch2
ch3
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
CSI11
IIC00
IIC11
TO00/P01
RxD0/P50 (LINSEL)
SERIAL ARRAY
UNIT1 (2ch)
UART2
PORT 1 P10 to P17
8
PORT 2 P20 to P25
6
PORT 3 P30, P31
2
PORT 0 P00, P01
2
PORT 5 P50, P51
2
PORT 6
P120
PORT 12 P121, P122
P137
PORT 13
P147PORT 14
A/D CONVERTER ANI18/P147, ANI19/P120
2
AVREFP/P20
AVREFM/P21
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
X2/EXCLK/P122
X1/P121
RESET
2
2
ANO0/P22
D/A CONVERTER Note
COMPARATOR Note
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
2
ANO1/P23
PORT 4 P40
PORT 7 P70 to P72
P60 to P62
3
3
SCK20/P15
SO20/P13
SI20/P14 CSI20
SCL20/P15
SDA20/P14 IIC20
SCK21/P70
SO21/P72
SI21/P71 CSI21
SCL21/P70
SDA21/P71 IIC21
CODE FLASH MEMORY
DATA FLASH MEMORY
BUZZER OUTPUT PCLBUZ0/P31,
PCLBUZ1/P15
CLOCK OUTPUT
CONTROL
2
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 27 of 187
Oct 25, 2013
1.5.4 40-pin products
Note Mounted on the 96 KB or more code flash memory products.
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P01
TxD1/P00
SCL00/P30
SDA00/P50
TI02/TO02/P17
TI03/TO03/P31
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL )
SCK11/P10
SO11/P12
SI11/P11
SCL11/P10
SDA11/P11
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
VSS TOOLRxD/P50,
TOOLTxD/P51
VDD
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
INTP5/P16
RxD2/P14
TxD2/P13
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 toTRDIOD1/P10
3
TIMER RJ TRJIO0/P01
TRJO0/P30
SSI00/P62
ch0
TIMER ARRAY
UNIT (4ch)
ch1
ch2
ch3
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
CSI11
IIC00
IIC11
TO00/P01
RxD0/P50 (LINSEL)
SERIAL ARRAY
UNIT1 (2ch)
UART2
PORT 1 P10 to P17
8
PORT 2 P20 to P26
7
PORT 3 P30, P31
2
PORT 0 P00, P01
2
PORT 5 P50, P51
2
PORT 6
P120
PORT 12 P121 to P124
P137
PORT 13
P147PORT 14
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
2
2
ANO0/P22
D/A CONVERTER Note
COMPARATOR Note
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
4
ANO1/P23
PORT 4 P40
PORT 7 P70 to P73
P60 to P62
3
4
SCK20/P15
SO20/P13
SI20/P14 CSI20
SCL20/P15
SDA20/P14 IIC20
SCK21/P70
SO21/P72
SI21/P71 CSI21
SCL21/P70
SDA21/P71 IIC21
7ANI0 /P20 to
ANI6/P26
A/D CONVERTER ANI18/P147, ANI19/P1202
AVREFP/P20
AVREFM/P21
KEY RETURN KR0/P70 to
KR3/P73
4
X1/P121
RESET
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
CODE FLASH MEMORY
DATA FLASH MEMORY
BUZZER OUTPUT PCLBUZ0/P31,
PCLBUZ1/P15
CLOCK OUTPUT
CONTROL
2
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 28 of 187
Oct 25, 2013
1.5.5 44-pin products
Note Mounted on the 96 KB or more code flash memory products.
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P01
TxD1/P00
SCL00/P30
SDA00/P50
TI02/TO02/P17
TI03/TO03/P31
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL )
SCK11/P10
SO11/P12
SI11/P11
SCL11/P10
SDA11/P11
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
VSS TOOLRxD/P50,
TOOLTxD/P51
VDD
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
INTP5/P16
RxD2/P14
TxD2/P13
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 toTRDIOD1/P10
3
TIMER RJ TRJIO0/P01
TRJO0/P30
SSI00/P62
ch0
TIMER ARRAY
UNIT (4ch)
ch1
ch2
ch3
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
CSI11
IIC00
IIC11
TO00/P01
RxD0/P50 (LINSEL)
SERIAL ARRAY
UNIT1 (2ch)
UART2
PORT 1 P10 to P17
8
PORT 2 P20 to P27
8
PORT 3 P30, P31
2
PORT 0 P00, P01
2
PORT 5 P50, P51
2
PORT 6
P120
PORT 12 P121 to P124
P137
PORT 13
PORT 14
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
2
2
ANO0/P22
D/A CONVERTER Note
COMPARATOR Note
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
4
ANO1/P23
PORT 4 P40, P41
PORT 7 P70 to P73
P60 to P63
4
4
SCK20/P15
SO20/P13
SI20/P14 CSI20
SCL20/P15
SDA20/P14 IIC20
SCK21/P70
SO21/P72
SI21/P71 CSI21
SCL21/P70
SDA21/P71 IIC21
8ANI0 /P20 to
ANI7/P27
A/D CONVERTER ANI18/P147, ANI19/P1202
AVREFP/P20
AVREFM/P21
KEY RETURN KR0/P70 to
KR3/P73
4
X1/P121
RESET
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
2
P146, P147
2
CODE FLASH MEMORY
DATA FLASH MEMORY
BUZZER OUTPUT PCLBUZ0/P31,
PCLBUZ1/P15
CLOCK OUTPUT
CONTROL
2
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 29 of 187
Oct 25, 2013
1.5.6 48-pin products
Note Mounted on the 96 KB or more code flash memory products.
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P01
TxD1/P00
TI02/TO02/P17
TI03/TO03/P31
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
VSS TOOLRxD/P50,
TOOLTxD/P51
VDD
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 toTRDIOD1/P10
3
TIMER RJ TRJIO0/P01
TRJO0/P30
SSI00/P62
ch0
TIMER ARRAY
UNIT (4ch)
ch1
ch2
ch3
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
TO00/P01
RxD0/P50 (LINSEL)
PORT 1 P10 to P17
8
PORT 2 P20 to P27
8
PORT 3 P30, P31
2
PORT 0 P00, P01
2
PORT 5 P50, P51
2
PORT 6
P120
PORT 12 P121 to P124
P137
PORT 13
PORT 14
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
ANO0/P22
D/A CONVERTER Note
COMPARATOR Note
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
4
ANO1/P23
PORT 4 P40, P41
PORT 7 P70 to P75
P60 to P63
4
6
8ANI0 /P20 to
ANI7/P27
A/D CONVERTER ANI18/P147, ANI19/P1202
AVREFP/P20
AVREFM/P21
X1/P121
RESET
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
2
P140,
P146, P147
3
SCL00/P30
SDA00/P50 IIC00
SCL01/P75
SDA01/P74 IIC01
SCL11/P10
SDA11/P11 IIC11
SCK11/P10
SO11/P12
SI11/P11 CSI11
SCK01/P75
SO01/P73
SI01/P74 CSI01
RxD2/P14
TxD2/P13
SERIAL ARRAY
UNIT1 (2ch)
UART2
SCK20/P15
SO20/P13
SI20/P14 CSI20
SCL20/P15
SDA20/P14 IIC20
SCK21/P70
SO21/P72
SI21/P71 CSI21
SCL21/P70
SDA21/P71 IIC21
P130
KEY RETURN KR0/P70 to
KR5/P75
6
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL )
2
2
INTP5/P16
INTP6/P140
2INTP8/P74,
INTP9/P75
CODE FLASH MEMORY
DATA FLASH MEMORY
BUZZER OUTPUT PCLBUZ0/P140,
PCLBUZ1/P15
CLOCK OUTPUT
CONTROL
2
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 30 of 187
Oct 25, 2013
1.5.7 52-pin products
Note Mounted on the 96 KB or more code flash memory products.
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P03
TxD1/P02
TI02/TO02/P17
TI03/TO03/P31
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
VSS TOOLRxD/P50,
TOOLTxD/P51
VDD
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 toTRDIOD1/P10
3
TIMER RJ TRJIO0/P01
TRJO0/P30
SSI00/P62
ch0
TIMER ARRAY
UNIT (4ch)
ch1
ch2
ch3
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
TO00/P01
RxD0/P50 (LINSEL)
PORT 1 P10 to P17
8
PORT 2 P20 to P27
8
PORT 3 P30, P31
2
PORT 0 P00 to P03
4
PORT 5 P50, P51
2
PORT 6
P120
PORT 12 P121 to P124
P137
PORT 13
PORT 14
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
ANO0/P22
D/A CONVERTER Note
COMPARATOR Note
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
4
ANO1/P23
PORT 4 P40, P41
PORT 7 P70 to P77
P60 to P63
4
8
8ANI0 /P20 to
ANI7/P27
A/D CONVERTER ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
4
AVREFP/P20
AVREFM/P21
X1/P121
RESET
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
2
P140,
P146, P147
3
SCL00/P30
SDA00/P50 IIC00
SCL01/P75
SDA01/P74 IIC01
SCL11/P10
SDA11/P11 IIC11
SCK11/P10
SO11/P12
SI11/P11 CSI11
SCK01/P75
SO01/P73
SI01/P74 CSI01
RxD2/P14
TxD2/P13
SERIAL ARRAY
UNIT1 (2ch)
UART2
SCK20/P15
SO20/P13
SI20/P14 CSI20
SCL20/P15
SDA20/P14 IIC20
SCK21/P70
SO21/P72
SI21/P71 CSI21
SCL21/P70
SDA21/P71 IIC21
P130
KEY RETURN KR0/P70 to
KR7/P77
8
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL )
2
2
INTP5/P16
INTP6/P140
4INTP8/P74 to
INTP11/P77
CODE FLASH MEMORY
DATA FLASH MEMORY
BUZZER OUTPUT PCLBUZ0/P140,
PCLBUZ1/P15
CLOCK OUTPUT
CONTROL
2
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
MULTIPLIE R &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 31 of 187
Oct 25, 2013
1.5.8 64-pin products
Note Mounted on the 96 KB or more code flash memory products.
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P03
TxD1/P02
TI02/TO02/P17
TI03/TO03/P31
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 toTRDIOD1/P10
3
TIMER RJ TRJIO0/P01
TRJO0/P30
SSI00/P62
ch0
TIMER ARRAY
UNIT (4ch)
ch1
ch2
ch3
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
TO00/P01
RxD0/P50 (LINSEL)
PORT 1 P10 to P17
8
PORT 2 P20 to P27
8
PORT 3 P30, P31
2
PORT 0 P00 to P06
7
PORT 5 P50 to P55
6
PORT 6
P120
PORT 12 P121 to P124
P137
PORT 13
PORT 14
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
ANO0/P22
D/A CONVERTER Note
COMPARATOR Note
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
4
ANO1/P23
PORT 4 P40 to P43
PORT 7 P70 to P77
P60 to P63
4
8
8ANI0 /P20 to
ANI7/P27
A/D CONVERTER ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
4
AVREFP/P20
AVREFM/P21
X1/P121
RESET
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
4
P140, P141,
P146, P147
4
SCL00/P30
SDA00/P50 IIC00
SCL01/P75
SDA01/P74 IIC01
SCL11/P10
SDA11/P11 IIC11
SCK11/P10
SO11/P12
SI11/P11 CSI11
SCK01/P75
SO01/P73
SI01/P74 CSI01
RxD2/P14
TxD2/P13
SERIAL ARRAY
UNIT1 (2ch)
UART2
SCK20/P15
SO20/P13
SI20/P14 CSI20
SCL20/P15
SDA20/P14 IIC20
SCK21/P70
SO21/P72
SI21/P71 CSI21
SCL21/P70
SDA21/P71 IIC21
P130
KEY RETURN KR0/P70 to
KR7/P77
8
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL )
2
2
INTP5/P16
INTP6/P140,
INTP7/P141
4INTP8/P74 to
INTP11/P77
SCK10/P04
SO10/P02
SI10/P03 CSI10
SCL10/P04
SDA10/P03 IIC10 SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
VDD,
EVDD0 VSS,
EVSS0
TOOLRxD/P50,
TOOLTxD/P51
2
CODE FLASH MEMORY
DATA FLASH MEMORY
BUZZER OUTPUT PCLBUZ0/P140,
PCLBUZ1/P141
CLOCK OUTPUT
CONTROL
2
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
MULTIPLIE R &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 32 of 187
Oct 25, 2013
1.5.9 80-pin products
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
RAM
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
RxD0/P50
TxD0/P51
UART1
RxD1/P03
TxD1/P02
TI02/TO02/P17
TI03/TO03/P31
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 to TRDI OD1/P10
3
SSI00/P62
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
TO00/P01
RxD0/P50 (LINSEL)
PORT 1 P10 to P17
8
PORT 2 P20 to P27
8
PORT 3 P30, P31
2
PORT 0 P00 to P06
7
PORT 5 P50 to P55
6
PORT 6
P120
PORT 12 P1 21 to P124
P137
PORT 13
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
ANO0/P22
D/A CONVERTER
COMPARATOR
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
4
ANO1/P23
PORT 4 P40 to P45
P60 to P67
8
X1/P121
RESET
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
6
SCL00/P30
SDA00/P50 IIC00
SCL01/P43
SDA01/P44 IIC01
SCL11/P10
SDA11/P11 IIC11
SCK11/P10
SO11/P12
SI11/P11 CSI11
SCK01/P43
SO01/P45
SI01/P44 CSI01
SERIAL ARRAY
UNIT1 (4ch)
P130
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P50,
INTP2/P51
RxD0/P50 (LINSEL)
2
2
INTP5/P16
INTP6/P140,
INTP7/P141
4INTP8/P74 to
INTP11/P77
SCK10/P04
SO10/P02
SI10/P03 CSI10
SCL10/P04
SDA10/P03 IIC10
VDD,
EVDD0 VSS,
EVSS0
TOOLRxD/P50,
TOOLTxD/P51
2
RxD2/P14
TxD2/P13 UART2
RxD3/P143
TxD3/P144 UART3
SCK20/P15
SO20/P13
SI20/P14 CSI20
SCL20/P15
SDA20/P14 IIC20
SCL21/P70
SDA21/P71 IIC21
SCK21/P70
SO21/P72
SI21/P71 CSI21
SCK30/P142
SO30/P144
SI30/P143 CSI30
SCK31/P54
SO31/P52
SI31/P53 CSI31
SCL30/P142
SDA30/P143 IIC30
SCL31/P54
SDA31/P53 IIC31
ch0
TIMER ARRAY
UNIT0 (4ch)
ch1
ch2
ch3
ch0
TIMER ARRAY
UNIT1 (4ch)
ch1
ch2
ch3
TI10/TO10/P64
TI11/TO11/P65
TI12/TO12/P66
TI13/TO13/P67
A/D CONVERTER
AVREFP/P20
AVREFM/P21
8 ANI0/P20 to ANI7/P27
ANI8/P150 to ANI11/P153
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
5
TIMER RJ TRJIO0/P01
TRJO0/P30
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
BUZZER OUTPUT PCLBUZ0/P140,
PCLBUZ1/P141
CLOCK OUTPUT
CONTROL
2
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
SDAA1/P63
SCLA1/P62
SERIAL
INTERFACE IICA1
PORT 7 P70 to P778
PORT 10 P100
PORT 11 P110, P111
2
PORT 14 P140 to P144,
P146, P147
7
PORT 15 P150 to P1534
KEY RETURN KR0/P70 to
KR7/P77
8
CODE FLASH MEMORY
DATA FLASH MEMORY
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 33 of 187
Oct 25, 2013
1.5.10 100-pin products
RAM
RxD0/P50
TxD0/P51
UART1
RxD1/P03
TxD1/P02
TI02/TO02/P17
TI03/TO03/P31
TI00/P00
CSI00
SCK00/P30
SO00/P51
SI00/P50
TI01/TO01/P16
TRDIOA0/TRDCLK/P17
TRDIOB0/P15, TRDIOC0/P16,
TRDIOD0/P14
4TRDIOA1/P13 to TRDI OD1/P10
3
SSI00/P62
TIMER RD (2ch)
ch0
ch1
SERIAL ARRAY
UNIT0 (4ch)
UART0
LINSEL
TO00/P01
RxD0/P50 (LINSEL)
PORT 1 P10 to P17
8
PORT 2 P20 to P27
8
PORT 3 P30, P31
2
PORT 0 P00 to P06
7
PORT 5 P50 to P57
8
PORT 6
PORT 4 P40 to P47
P60 to P67
8
8
SCL00/P30
SDA00/P50 IIC00
SCL01/P43
SDA01/P44 IIC01
SCL11/P10
SDA11/P11 IIC11
SCK11/P10
SO11/P12
SI11/P11 CSI11
SCK01/P43
SO01/P45
SI01/P44 CSI01
SERIAL ARRAY
UNIT1 (4ch)
SCK10/P04
SO10/P02
SI10/P03 CSI10
SCL10/P04
SDA10/P03 IIC10
TOOLRxD/P50,
TOOLTxD/P51
RxD2/P14
TxD2/P13 UART2
RxD3/P143
TxD3/P144 UART3
SCK20/P15
SO20/P13
SI20/P14 CSI20
SCL20/P15
SDA20/P14 IIC20
SCL21/P70
SDA21/P71 IIC21
SCK21/P70
SO21/P72
SI21/P71 CSI21
SCK30/P142
SO30/P144
SI30/P143 CSI30
SCK31/P54
SO31/P52
SI31/P53 CSI31
SCL30/P142
SDA30/P143 IIC30
SCL31/P54
SDA31/P53 IIC31
ch0
TIMER ARRAY
UNIT0 (4ch)
ch1
ch2
ch3
ch0
TIMER ARRAY
UNIT1 (4ch)
ch1
ch2
ch3
TI10/TO10/P64
TI11/TO11/P65
TI12/TO12/P66
TI13/TO13/P67
TIMER RJ TRJIO0/P01
TRJO0/P30
TIMER RG
TRGIOA/P50,
TRGIOB/P51
2
2TRGCLKA/P00,
TRGCLKB/P01
BUZZER OUTPUT PCLBUZ0/P140,
PCLBUZ1/P141
CLOCK OUTPUT
CONTROL
2
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
SDAA1/P63
SCLA1/P62
SERIAL
INTERFACE IICA1
VSS,
EVSS0,
EVSS1
VDD,
EVDD0,
EVDD1
VOLTAGE
REGULATOR REGC
INTERRUPT
CONTROL
SYSTEM
CONTROL
HIGH-SPEED
ON-CHIP
OSCILLATOR
P120
PORT 12 P1 21 to P124
P137
PORT 13
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
RESET CONTROL
TOOL0/P40
ON-CHIP DEBUG
ANO0/P22
D/A CONVERTER
COMPARATOR
(2ch)
COMPARATOR0 IVCMP0/P17
IVREF0/P16
VCOUT0/P120
COMPARATOR1 IVCMP1/P13
IVREF1/P12
VCOUT1/P147
4
ANO1/P23
X1/P121
RESET
X2/EXCLK/P122
XT1/P123
XT2/EXCLKS/P124
P130
INTP0/P137
INTP3/P30,
INTP4/P31
INTP1/P47,
INTP2/P46
RxD0/P50 (LINSEL)
2
2
INTP5/P16
INTP6/P140,
INTP7/P141
4INTP8/P74 to
INTP11/P77
2
PORT 10 P100 to P102
PORT 11 P110, P1112
PORT 14 P140 to P1478
PORT 15 P150 to P1567
KEY RETURN KR0/P70 to
KR7/P77
8
3
PORT 7 P70 to P778
PORT 8 P80 to P878
CODE FLASH MEMORY
DATA FLASH MEMORY
BCD
ADJUSTMENT
DATA TRANSFER
CONTROL
EVENT LINK
CONTROLLER
WINDOW
WATCHDOG
TIMER
12- BIT INTERVAL
TIMER
REAL-TIME
CLOCK
LOW-SPEED
ON-CHIP
OSCILLATOR
RTC1HZ/P30
A/D CONVERTER
AVREFP/P20
AVREFM/P21
8ANI0/P20 to ANI7/P27
ANI8/P150 to ANI14/P156
7
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
5
MULTIPLIER &
DIVIDER,
MULITIPLY-
ACCUMULATOR
RL78 CPU CORE
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 34 of 187
Oct 25, 2013
1.6 Outline of Functions
[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 16 KB to 64 KB)]
Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H. (1/2)
Note In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used.
Item
30-pin 32-pin 36-pin 40-pin
R5F104Ax
(x = A, C to E) R5F104Bx
(x = A, C to E) R5F104Cx
(x = A, C to E) R5F104Ex
(x = A, C to E)
Code flash memory (KB) 16 to 64 16 to 64 16 to 64 16 to 64
Data flash memory (KB) 4444
RAM (KB) 2.5 to 5.5 Note 2. 5 to 5. 5 Note 2.5 to 5.5 Note 2.5 to 5.5 Note
Address space 1 MB
Main system
clock High-speed system
clock X1 (crystal/ceramic) oscillation, exter nal main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-volt age main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock — XT1 (crystal) oscillation,
external subsystem
clock input (EXCLKS)
32.768 kHz
Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction executio n time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
— 30.5 s (Subsystem
clock: fSUB = 32.768 kHz
operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits ÷ 16 bit s, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 26 28 32 36
CMOS I/O 21 22 26 28
CMOS input3335
CMOS output————
N-ch open-drain I/O (6
V tolerance) 2333
Timer 16-bit timer 8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer 1 channel
Real-time clock (RTC) 1 channel
12-bit interval timer 1 channel
T i mer output T imer outputs: 13 channels
PWM outputs: 9 chann els
RTC output — 1
•1 Hz
(subsystem clock: fSUB
= 32.768 kHz)
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 35 of 187
Oct 25, 2013
(2/2)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Item
30-pin 32-pin 36-pin 40-pin
R5F104Ax
(x = A, C to E) R5F104Bx
(x = A, C to E) R5F104Cx
(x = A, C to E) R5F104Ex
(x = A, C to E)
Clock output/buzzer output 2222
[30-pin, 32-pin, 36-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
[40-pin product s]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 8 channels 8 channels 8 channels 9 channels
Serial interface [30-pin, 32-pin products]
• CSI: 1 channel/UA RT (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
[36-pin, 40-pin products]
• CSI: 1 channel/UA RT (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
I2C bus 1 channel 1 channel 1 channel 1 channel
Data transfer controller (DTC) 28 sources 29 sources
Event link controller (ELC) Event input: 19
Event trigger out put: 7 Event input: 20
Event trigger outp ut: 7
Vectored interrupt
sources Internal 24 24 24 24
External 6667
Key interrupt ——— 4
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage det ector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM pari ty error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector 1.63 V to 4.06 V (14 st ages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 5.5 V
Operating ambient temperature TA = 40 to +85 °C
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 36 of 187
Oct 25, 2013
[30-pin, 32-pin, 36-pin, 40-pin products (code flash memory 96 KB to 256 KB)]
Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H. (1/2)
Item
30-pin 32-pin 36-pin 40-pin
R5F104Ax
(x = F, G) R5F104Bx
(x = F, G) R5F104Cx
(x = F, G) R5F104Ex
(x = F to H)
Code flash memory (KB) 96 to 128 96 to 128 96 to 128 96 to 192
Data flash memory (KB) 8888
RAM (KB) 12 to 16 12 to 16 1 2 to 16 12 to 20
Address space 1 MB
Main system
clock High-speed system
clock X1 (crystal/ceramic) oscillation, exter nal main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-volt age main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock — XT1 (crystal) oscillation,
external subsystem
clock input (EXCLKS)
32.768 kHz
Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction executio n time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
— 30.5 s (Subsystem
clock: fSUB = 32.768 kHz
operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits ÷ 16 bit s, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 26 28 32 36
CMOS I/O 21 22 26 28
CMOS input3335
CMOS output————
N-ch open-drain I/O (6
V tolerance) 2333
Timer 16-bit timer 8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer 1 channel
Real-time clock (RTC) 1 channel
12-bit interval timer 1 channel
T i mer output T imer outputs: 13 channels
PWM outputs: 9 chann els
RTC output — 1
•1 Hz
(subsystem clock: fSUB
= 32.768 kHz)
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 37 of 187
Oct 25, 2013
(2/2)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not is issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Item
30-pin 32-pin 36-pin 40-pin
R5F104Ax
(x = F, G) R5F104Bx
(x = F, G) R5F104Cx
(x = F, G) R5F104Ex
(x = F to H)
Clock output/buzzer output 2222
[30-pin, 32-pin, 36-pin products]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
[40-pin product s]
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 8 channels 8 channels 8 channels 9 channels
D/A converter 1 channel 2 channels
Comparator 2 channels
Serial interface [30-pin, 32-pin products]
• CSI: 1 channel/UA RT (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
[36-pin, 40-pin products]
• CSI: 1 channel/UA RT (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
I2C bus 1 channel 1 channel 1 channel 1 channel
Data transfer controller (DTC) 30 sources 31 sources
Event link controller (ELC) Event input: 21
Event trigger out put: 8 Event input: 21, Event trigger output: 9 Event input: 22
Event trigger outp ut: 9
Vectored interrupt
sources Internal 24 24 24 24
External 6667
Key interrupt — — — 4
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage det ector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM pari ty error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector 1.63 V to 4.06 V (14 st ages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 5.5 V
Operating ambient temperature TA = 40 to +85 °C
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 38 of 187
Oct 25, 2013
[44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 16 KB to 64 KB)]
Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H. (1/2)
Note In the case of the 5.5 KB, this is about 4.5 KB when the self-programming function and data flash function are used.
Item 44-pin 48-pin 52-pin 64-pin
R5F104Fx
(x = A, C to E) R5F104Gx
(x = A, C to E) R5F104Jx
(x = C to E) R5F104Lx
(x = C to E)
Code flash memory (KB) 16 to 64 16 to 64 32 to 64 32 to 64
Data flash memory (KB) 4 4 4 4
RAM (KB) 2.5 to 5.5 Note 2.5 to 5.5 Note 4 to 5.5 Note 4 to 5.5 Note
Address space 1 MB
Main system
clock High-speed system
clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: V
DD
= 2.7 to 5.5 V, 1 to 8 MHz: V
DD
= 1.8 to 2.7 V, 1 to 4 MHz: V
DD
= 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz
Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O portTotal 40444858
CMOS I/O 31 34 38 48
CMOS input 5 5 5 5
CMOS output — 1 1 1
N-ch open-drain I/O
(6 V tolerance) 4444
Timer 16-bit timer 8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer 1 channel
Real-time clock
(RTC) 1 channel
12-bit interval timer 1 channel
Timer output Timer outputs: 13 channels
PWM outputs: 9 channels
RTC output 1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 39 of 187
Oct 25, 2013
(2/2)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Item 44-pin 48-pin 52-pin 64-pin
R5F104Fx
(x = A, C to E) R5F104Gx
(x = A, C to E) R5F104Jx
(x = C to E) R5F104Lx
(x = C to E)
Clock output/buzzer output 2 2 2 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 10 channels 10 channels 12 channels 12 channels
Serial interface [44-pin products]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[48-pin, 52-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[64-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
I2C bus 1 channel 1 channel 1 channel 1 channel
Data transfer controller (DTC) 29 sources 30 sources 31 sources
Event link controller (ELC) Event input: 20
Event trigger output: 7
Vectored
interrupt sources Internal 24 24 24 24
External 7 101213
Key interrupt 4 6 8 8
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector 1.63 V to 4.06 V (14 stages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 5.5 V
Operating ambient temperature TA = 40 to +85 °C
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 40 of 187
Oct 25, 2013
[44-pin, 48-pin, 52-pin, 64-pin products (code flash memory 96 KB to 256 KB)]
Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H. (1/2)
Note In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used.
Item 44-pin 48-pin 52-pin 64-pin
R5F104Fx
(x = F to H, J) R5F104Gx
(x = F to H, J) R5F104Jx
(x = F to H, J) R5F104Lx
(x = F to H, J)
Code flash memory (KB) 96 to 256 96 to 256 96 to 256 96 to 256
Data flash memory (KB) 8 8 8 8
RAM (KB) 12 to 24 Note 12 to 24 Note 12 to 24 Note 12 to 24 Note
Address space 1 MB
Main system
clock High-speed system
clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: V
DD
= 2.7 to 5.5 V, 1 to 8 MHz: V
DD
= 1.8 to 2.7 V, 1 to 4 MHz: V
DD
= 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz
Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O portTotal 40444858
CMOS I/O 31 34 38 48
CMOS input 5 5 5 5
CMOS output — 1 1 1
N-ch open-drain I/O
(6 V tolerance) 4444
Timer 16-bit timer 8 channels
(TAU: 4 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer 1 channel
Real-time clock
(RTC) 1 channel
12-bit interval timer 1 channel
Timer output Timer outputs: 14 channels
PWM outputs: 9 channels
RTC output 1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 41 of 187
Oct 25, 2013
(2/2)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Item 44-pin 48-pin 52-pin 64-pin
R5F104Fx
(x = F to H, J) R5F104Gx
(x = F to H, J) R5F104Jx
(x = F to H, J) R5F104Lx
(x = F to H, J)
Clock output/buzzer output 2 2 2 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 10 channels 10 channels 12 channels 12 channels
D/A converter 2 channels
Comparator 2 channels
Serial interface [44-pin products]
• CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[48-pin, 52-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
[64-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
I2C bus 1 channel 1 channel 1 channel 1 channel
Data transfer controller (DTC) 31 sources 32 sources 33 sources
Event link controller (ELC) Event input: 22
Event trigger output: 9
Vectored
interrupt sources Internal 24 24 24 24
External 7 101213
Key interrupt 4 6 8 8
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector 1.63 V to 4.06 V (14 stages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 5.5 V
Operating ambient temperature TA = 40 to +85 °C
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 42 of 187
Oct 25, 2013
[80-pin, 100-pin products (code flash memory 96 KB to 256 KB)]
Caution This outline describes the functions at the time when Peripheral I/O redirection register 0, 1
(PIOR0, 1) are set to 00H. (1/2)
Note In the case of the 24 KB, this is about 23 KB when the self-programming function and data flash function are used.
Item 80-pin 100-pin
R5F104Mx
(x = F to H, J) R5F104Px
(x = F to H, J)
Code flash memory (KB) 96 to 256 96 to 256
Data flash memory (KB) 8 8
RAM (KB) 12 to 24 Note 12 to 24 Note
Address space 1 MB
Main system
clock High-speed system
clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: V
DD
= 2.7 to 5.5 V, 1 to 8 MHz: V
DD
= 1.8 to 2.7 V, 1 to 4 MHz: V
DD
= 1.6 to 1.8 V
High-speed on-chip
oscillator clock (fIH)HS (high-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (high-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock XT1 (crystal) oscillation, external subsystem clock input (EXCLKS) 32.768 kHz
Low-speed on-chip oscillator clock 15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks)
Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator clock: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits 8 bits, 16 bits 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)
• Multiplication and Accumulation (16 bits 16 bits + 32 bits)
• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
I/O port Total 74 92
CMOS I/O 64 82
CMOS input 5 5
CMOS output 1 1
N-ch open-drain I/O
(6 V tolerance) 44
Timer 16-bit timer 12 channels
(TAU: 8 channels, Timer RJ: 1 channel, Timer RD: 2 channels, Timer RG: 1 channel)
Watchdog timer 1 channel
Real-time clock
(RTC) 1 channel
12-bit interval timer 1 channel
Timer output Timer outputs: 18 channels
PWM outputs: 12 channels
RTC output 1
• 1 Hz (subsystem clock: fSUB = 32.768 kHz)
RL78/G14 1. OUTLINE
R01DS0053EJ0200 Rev. 2.00 Page 43 of 187
Oct 25, 2013
(2/2)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution is not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Item 80-pin 100-pin
R5F104Mx
(x = F to H, J) R5F104Px
(x = F to H, J)
Clock output/buzzer output 2 2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter 17 channels 20 channels
D/A converter 2 channels 2 channels
Comparator 2 channels 2 channels
Serial interface [80-pin, 100-pin products]
• CSI: 2 channels/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
• CSI: 2 channels/UART: 1 channel/simplified I2C: 2 channels
I2C bus 2 channels 2 channels
Data transfer controller (DTC) 39 sources 39 sources
Event link controller (ELC) Event input: 26
Event trigger output: 9
Vectored
interrupt sources Internal 32 32
External 13 13
Key interrupt 8 8
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
Voltage detector 1.63 V to 4.06 V (14 stages)
On-chip debug function Provided
Power supply voltage VDD = 1.6 to 5.5 V
Operating ambient temperature TA = 40 to +85 °C
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 44 of 187
Oct 25, 2013
2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
This chapter describes the electrical specifications for the products “A: Consumer applications (TA = -40 to +85 C)” and
“D: Industrial applications (TA = -40 to +85 C)”.
Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and pr oduct reliability therefore cannot be gu aranteed. Rene sas Electronics is not
liable for probl ems occurring when the on-chip debug functi on is used.
Caution 2. With product s not provi ded with an EV DD0, EVDD1, EVSS0, or EV SS1 pin, replace EVDD0 and EVDD1 with
VDD, or replace EVSS0 and EVSS1 with VSS.
Caution 3. The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 45 of 187
Oct 25, 2013
2.1 Absolute Maximum Ratings
Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Note 2. Must be 6.5 V or lower.
Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the prod uct must be used under conditions that ensure that th e absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
Absolute Maximum Ratings (1/2)
Parameter Symbols Conditions Ratings Unit
Supply voltage VDD -0.5 to +6.5 V
EVDD0, EVDD1 EVDD0 = EVDD1 -0.5 to +6.5 V
EVSS0, EVSS1 EVSS0 = EVSS1 -0.5 to +0.3 V
REGC pin input voltage VIREGC REGC -0.3 to +2.8
and -0.3 to VDD +0.3 Note 1 V
Input voltage VI1 P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P100 to P102,
P110, P111, P120, P140 to P147
-0.3 to EVDD0 +0.3
and -0.3 to VDD +0.3 Note 2 V
VI2 P60 to P63 (N-ch open-drain) -0.3 to +6.5 V
VI3 P20 to P27, P121 to P124, P137,
P150 to P156, EXCLK, EXCLKS, RESET -0.3 to VDD +0.3 Note 2 V
Output voltage VO1 P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P100 to P102,
P110, P111, P120, P130, P140 to P147
-0.3 to EVDD0 +0.3
and -0.3 to VDD +0.3 Note 2 V
VO2 P20 to P27, P150 to P156 -0.3 to VDD +0.3 Note 2 V
Analog input voltage VAI1 ANI16 to ANI20 -0.3 to EVDD0 +0.3
and -0.3 to AVREF(+) +0.3 Notes 2, 3 V
VAI2 ANI0 to ANI14 -0.3 to VDD +0.3
and -0.3 to AVREF(+) +0.3 Notes 2, 3 V
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 46 of 187
Oct 25, 2013
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the prod uct must be used under conditions that ensure that th e absolute maximum
ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Absolute Maximum Ratings (2/2)
Parameter Symbols Conditions Ratings Unit
Output current, high IOH1 Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120, P130,
P140 to P147
-40 mA
Total of all
pins
-170 mA
P00 to P04, P40 to P47, P102, P120, P130,
P140 to P145 -70 mA
P05, P06, P10 to P17, P30, P31, P50 to P57,
P64 to P67, P70 to P77, P80 to P87, P100, P101,
P110, P111, P146, P147
-100 mA
IOH2 Per pin P20 to P27, P150 to P156 -0.5 mA
Total of all
pins -2 mA
Output current, low IOL1 Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120, P130,
P140 to P147
40 mA
Total of all
pins
170 mA
P00 to P04, P40 to P47, P102, P120, P130,
P140 to P145 70 mA
P05, P06, P10 to P17, P30, P31, P50 to P57,
P60 to P67, P70 to P77, P80 to P87, P100, P101,
P110, P111, P146, P147
100 mA
IOL2 Per pin P20 to P27, P150 to P156 1 mA
Total of all
pins 5mA
Operating ambient
temperature TAIn normal operation mode -40 to +85 C
In flash memory programming mode
Storage temperature Tstg -65 to +150 C
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Oct 25, 2013
2.2 Oscillator Characteristics
2.2.1 X1, XT1 characteristics
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillat ion stabilization time of the OSTC r egister and th e oscillation s tabili zation time s elect
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, refer to 5. 4 System Clock Osc illator i n the RL78/G1 4 User’s Manual
Hardware.
2.2.2 On-chip oscillator characteristics
Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H) and bits 0 to 2 of the
HOCODIV register.
Note 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
(TA = -40 to +85 °C, 1. 6 V VDD 5.5 V, VSS = 0 V)
Resonator Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation frequency (fX) Note Ceramic resonator/
crystal resonator 2.7 V VDD 5.5 V 1.0 20.0 MHz
2.4 V VDD <2.7 V 1.0 16.0
1.8 V VDD < 2.4 V 1.0 8.0
1.6 V VDD < 1.8 V 1.0 4.0
XT1 clock oscillation frequency (fXT) Note Crystal resonator 32 32.768 35 kHz
(TA = -40 to +85 C, 1.6 V VDD 5.5 V, VSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator clock frequency
Notes 1, 2 fIH 132MHz
High-speed on-chip oscillator clock frequency
accuracy
-20 to +85 C 1.8 V VDD 5.5 V -1.0 +1.0 %
1.6 V VDD < 1.8 V -5.0 +5.0 %
-40 to -20 C 1.8 V VDD < 5.5 V -1.5 +1.5 %
1.6 V VDD < 1.8 V -5.5 +5.5 %
Low-speed on-chip oscillator clock frequency fIL 15 kHz
Low-speed on-chip oscillator clock frequency
accuracy -15 +15 %
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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2.3 DC Characteristics
2.3.1 Pin characteristics
Note 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to
an output pin.
Note 2. However, do not exceed the total current value.
Note 3. Specification under conditions where the duty factor 70%.
The output current value that has cha nged to the duty factor 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01) -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Note 4. -100 mA for industrial applications (R5F104xxDxx).
Caution P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 t o P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144
do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current, high Note 1 IOH1 Per pin for P00 to P06,
P10 to P17, P30, P31,
P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P130, P140 to P147
1.6 V EVDD0 5.5 V -10.0
Note 2 mA
Total of P00 to P04, P40 to P47,
P102, P120, P130, P140 to P145
(When duty 70% Note 3)
4.0 V EVDD0 5.5 V -55.0 mA
2.7 V EVDD0 < 4.0 V -10.0 mA
1.8 V EVDD0 < 2.7 V -5.0 mA
1.6 V EVDD0 < 1.8 V -2.5 mA
Total of P05, P06, P10 to P17,
P30, P31, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100, P101, P110,
P111, P146, P147
(When duty 70% Note 3)
4.0 V EVDD0 5.5 V -80.0 mA
2.7 V EVDD0 < 4.0 V -19.0 mA
1.8 V EVDD0 < 2.7 V -10.0 mA
1.6 V EVDD0 < 1.8 V -5.0 mA
Total of all pins
(When duty 70% Note 3)1.6 V EVDD0 5.5 V -135.0
Note 4 mA
IOH2 Per pin for P20 to P27,
P150 to P156 1.6 V VDD 5.5 V -0.1
Note 2 mA
Total of all pins
(When duty 70% Note 3)1.6 V VDD 5.5 V -1.5 mA
(1/5)
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Note 1. Value of current at which the device operation is gu aranteed even if the current flows from an output pin to the EVSS0,
EVSS1, and VSS pins.
Note 2. However, do not exceed the total current value.
Note 3. Specification under conditions where the duty factor 70%.
The output current value that has cha nged to the duty factor 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current, low Note 1 IOL1 Per pin for P00 to P06,
P10 to P17, P30, P31,
P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P130, P140 to P147
20.0
Note 2 mA
Per pin for P60 to P63 15.0
Note 2 mA
Total of P00 to P04, P40 to P47,
P102, P120, P130, P140 to P145
(When duty 70% Note 3)
4.0 V EVDD0 5.5 V 70.0 mA
2.7 V EVDD0 < 4.0 V 15.0 mA
1.8 V EVDD0 < 2.7 V 9.0 mA
1.6 V EVDD0 < 1.8 V 4.5 mA
Total of P05, P06, P10 to P17,
P30, P31, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P100, P101, P110,
P111, P146, P147
(When duty 70% Note 3)
4.0 V EVDD0 5.5 V 80.0 mA
2.7 V EVDD0 < 4.0 V 35.0 mA
1.8 V EVDD0 < 2.7 V 20.0 mA
1.6 V EVDD0 < 1.8 V 10.0 mA
Total of all pins
(When duty 70% Note 3)150.0 mA
IOL2 Per pin for P20 to P27,
P150 to P156 0.4
Note 2 mA
Total of all pins
(When duty 70% Note 3)1.6 V VDD 5.5 V 5.0 mA
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Caution The maximum value of V IH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71,
P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P1 10,
P111, P120, P140 to P147
Normal input buffer 0.8 EVDD0 EVDD0 V
VIH2 P01, P03, P04, P10, P14 to P17,
P30, P43, P44, P50, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V EVDD0 5.5 V 2.2 EVDD0 V
TTL input buffer
3.3 V EVDD0 < 4.0 V 2.0 EVDD0 V
TTL input buffer
1.6 V EVDD0 < 3.3 V 1.5 EVDD0 V
VIH3 P20 to P27, P150 to P156 0.7 VDD VDD V
VIH4 P60 to P63 0.7 EVDD0 6.0 V
VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V
Input voltage, low VIL1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P1 10,
P111, P120, P140 to P147
Normal input buffer 0 0.2 EVDD0 V
VIL2 P01, P03, P04, P10, P14 to P17,
P30, P43, P44, P50, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V EVDD0 5.5 V 00.8V
TTL input buffer
3.3 V EVDD0 < 4.0 V 00.5V
TTL input buffer
1.6 V EVDD0 < 3.3 V 00.32V
VIL3 P20 to P27, P150 to P156 0 0.3 VDD V
VIL4 P60 to P63 0 0.3 EVDD0 V
VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V
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Caution P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P 74, P80 to P82, P142 to P144 do not
output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output voltage, high VOH1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P1 10,
P111, P120, P130, P140 to P147
4.0 V EVDD0 5.5 V,
IOH1 = -10.0 mA EVDD0 - 1.5 V
4.0 V EVDD0 5.5 V,
IOH1 = -3.0 mA EVDD0 - 0.7 V
1.8 V EVDD0 5.5 V,
IOH1 = -1.5 mA EVDD0 - 0.5 V
1.6 V EVDD0 < 1.8 V,
IOH1 = -1.0 mA EVDD0 - 0.5 V
VOH2 P20 to P27, P150 to P156 1.6 V VDD 5.5 V,
IOH2 = -100 AVDD - 0.5 V
Output voltage, low VOL1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P1 10,
P111, P120, P130,
P140 to P147
4.0 V EVDD0 5.5 V,
IOL1 = 20.0 mA 1.3 V
4.0 V EVDD0 5.5 V,
IOL1 = 8.5 mA 0.7 V
2.7 V EVDD0 5.5 V,
IOL1 = 3.0 mA 0.6 V
2.7 V EVDD0 5.5 V,
IOL1 = 1.5 mA 0.4 V
1.8 V EVDD0 5.5 V,
IOL1 = 0.6 mA 0.4 V
1.6 V EVDD0 5.5 V,
IOL1 = 0.3 mA 0.4 V
VOL2 P20 to P27, P150 to P156 1.6 V VDD 5.5 V,
IOL2 = 400 A0.4 V
VOL3 P60 to P63 4.0 V EVDD0 5.5 V,
IOL3 = 15.0 mA 2.0 V
4.0 V EVDD0 5.5 V,
IOL3 = 5.0 mA 0.4 V
2.7 V EVDD0 5.5 V,
IOL3 = 3.0 mA 0.4 V
1.8 V EVDD0 5.5 V,
IOL3 = 2.0 mA 0.4 V
1.6 V EVDD0 5.5 V,
IOL3 = 1.0 mA 0.4 V
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high ILIH1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
VI = EVDD0 1A
ILIH2 P20 to P27, P137, P150 to P156,
RESET
VI = VDD 1A
ILIH3 P121 to P124
(X1, X2, EXCLK, XT1, XT2,
EXCLKS)
VI = VDD In input port or
external clock
input
1A
In resonator
connection 10 A
Input leakage
current, low ILIL1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
VI = EVSS0 -1 A
ILIL2 P20 to P27, P137, P150 to P156,
RESET
VI = VSS -1 A
ILIL3 P121 to P124
(X1, X2, EXCLK, XT1, XT2,
EXCLKS)
VI = VSS In input port or
external clock
input
-1 A
In resonator
connection -10 A
On-chip pull-up
resistance RUP00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
VI = EVSS0, In input port 10 20 100 k
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2.3.2 Supply current characteristics
(Notes and Remarks are listed on the next page.)
(1) Flash ROM: 16 to 64 KB of 30- to 64-pin products
(TA = -40 to +8 5 C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V)
Parameter Symbol
Conditions MIN. TYP. MAX. Unit
Supply
current
Note 1
IDD1 Operating
mode HS (high-speed main)
mode Note 5 fHOCO = 64 MHz,
fIH = 32 MHz Note 3 Basic
operation VDD = 5.0 V 2.4 mA
VDD = 3.0 V 2.4
fHOCO = 32 MHz,
fIH = 32 MHz Note 3 Basic
operation VDD = 5.0 V 2.1
VDD = 3.0 V 2.1
HS (high-speed main)
mode Note 5 fHOCO = 64 MHz,
fIH = 32 MHz Note 3 Normal
operation VDD = 5.0 V 5.2 8.7 mA
VDD = 3.0 V 5.2 8.7
fHOCO = 32 MHz,
fIH = 32 MHz Note 3 Normal
operation VDD = 5.0 V 4.8 8.1
VDD = 3.0 V 4.8 8.1
fHOCO = 48 MHz,
fIH = 24 MHz Note 3 Normal
operation VDD = 5.0 V 4.1 6.9
VDD = 3.0 V 4.1 6.9
fHOCO = 24 MHz,
fIH = 24 MHz Note 3 Normal
operation VDD = 5.0 V 3.8 6.3
VDD = 3.0 V 3.8 6.3
fHOCO = 16 MHz,
fIH = 16 MHz Note 3 Normal
operation VDD = 5.0 V 2.8 4.6
VDD = 3.0 V 2.8 4.6
LS (low-speed main)
mode Note 5 fHOCO = 8 MHz,
fIH = 8 MHz Note 3 Normal
operation VDD = 3.0 V 1.3 2.0 mA
VDD = 2.0 V 1.3 2.0
L V (low-volt age main)
mode Note 5 fHOCO = 4 MHz,
fIH = 4 MHz Note 3 Normal
operation VDD = 3.0 V 1.3 1.8 mA
VDD = 2.0 V 1.3 1.8
HS (high-speed main)
mode Note 5 fMX = 20 MHz Note 2,
VDD = 5.0 V Normal
operation Square wave input 3.3 5.3 mA
Resonator connection 3.5 5.5
fMX = 20 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 3.3 5.3
Resonator connection 3.5 5.5
fMX = 10 MHz Note 2,
VDD = 5.0 V Normal
operation Square wave input 2.0 3.1
Resonator connection 2.1 3.2
fMX = 10 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 2.0 3.1
Resonator connection 2.1 3.2
LS (low-speed main)
mode Note 5 fMX = 8 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 1.2 1.9 mA
Resonator connection 1.2 2.0
fMX = 8 MHz Note 2,
VDD = 2.0 V Normal
operation Square wave input 1.2 1.9
Resonator connection 1.2 2.0
Subsystem clock
operation fSUB = 32.768 kHz Note 4
TA = -40 CNormal
operation Square wave input 4.7 6.1 A
Resonator connection 4.7 6.1
fSUB = 32.768 kHz Note 4
TA = +25 CNormal
operation Square wave input 4.7 6.1
Resonator connection 4.7 6.1
fSUB = 32.768 kHz Note 4
TA = +50 CNormal
operation Square wave input 4.8 6.7
Resonator connection 4.8 6.7
fSUB = 32.768 kHz Note 4
TA = +70 CNormal
operation Square wave input 4.8 7.5
Resonator connection 4.8 7.5
fSUB = 32.768 kHz Note 4
TA = +85 CNormal
operation Square wave input 5.4 8.9
Resonator connection 5.4 8.9
(1/2)
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Note 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
Note 2. When high-speed on-chip oscillator and subsystem clock are stopped.
Note 3. When high-speed system clock and subsystem clock are stopped.
Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power
consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog
timer.
Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 55 of 187
Oct 25, 2013
(Notes and Remarks are listed on the next page.)
(1) Flash ROM: 16 to 64 KB of 30- to 64-pin products
(TA = -40 to +8 5 C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1 IDD2
Note 2 HAL T mode HS (high-speed main)
mode Note 7 fHOCO = 64 MHz,
fIH = 32 MHz Note 4 VDD = 5.0 V 0.80 3.09 mA
VDD = 3.0 V 0.80 3.09
fHOCO = 32 MHz,
fIH = 32 MHz Note 4 VDD = 5.0 V 0.54 2.40
VDD = 3.0 V 0.54 2.40
fHOCO = 48 MHz,
fIH = 24 MHz Note 4 VDD = 5.0 V 0.62 2.40
VDD = 3.0 V 0.62 2.40
fHOCO = 24 MHz,
fIH = 24 MHz Note 4 VDD = 5.0 V 0.44 1.83
VDD = 3.0 V 0.44 1.83
fHOCO = 16 MHz,
fIH = 16 MHz Note 4 VDD = 5.0 V 0.40 1.38
VDD = 3.0 V 0.40 1.38
LS (low-speed main)
mode Note 7 fHOCO = 8 MHz,
fIH = 8 MHz Note 4 VDD = 3.0 V 260 710 A
VDD = 2.0 V 260 710
LV (low-voltage main)
mode Note 7 fHOCO = 4 MHz,
fIH = 4 MHz Note 4 VDD = 3.0 V 420 700 A
VDD = 2.0 V 420 700
HS (high-speed main)
mode Note 7 fMX = 20 MHz Note 3,
VDD = 5.0 V Square wave input 0.28 1.55 mA
Resonator connection 0.49 1.74
fMX = 20 MHz Note 3,
VDD = 3.0 V Square wave input 0.28 1.55
Resonator connection 0.49 1.74
fMX = 10 MHz Note 3,
VDD = 5.0 V Square wave input 0.19 0.86
Resonator connection 0.30 0.93
fMX = 10 MHz Note 3,
VDD = 3.0 V Square wave input 0.19 0.86
Resonator connection 0.30 0.93
LS (low-speed main)
mode Note 7 fMX = 8 MHz Note 3,
VDD = 3.0 V Square wave input 95 550 A
Resonator connection 145 590
fMX = 8 MHz Note 3,
VDD = 2.0 V Square wave input 95 550
Resonator connection 145 590
Subsystem clock
operation fSUB = 32.768 kHz Note 5,
TA = -40 CSquare wave input 0.25 0.57 A
Resonator connection 0.44 0.76
fSUB = 32.768 kHz Note 5,
TA = +25 CSquare wave input 0.30 0.57
Resonator connection 0.49 0.76
fSUB = 32.768 kHz Note 5,
TA = +50 CSquare wave input 0.36 1.17
Resonator connection 0.59 1.36
fSUB = 32.768 kHz Note 5,
TA = +70 CSquare wave input 0.49 1.97
Resonator connection 0.72 2.16
fSUB = 32.768 kHz Note 5,
TA = +85 CSquare wave input 0.97 3.37
Resonator connection 1.16 3.56
IDD3
Note 6 STOP mode
Note 8 TA = -40 C0.18 0.51 A
TA = +25 C0.24 0.51
TA = +50 C0.29 1.10
TA = +70 C0.41 1.90
TA = +85 C0.90 3.30
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Note 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
Note 2. During HALT instruction execution by flash memory.
Note 3. When high-speed on-chip oscillator and subsystem clock are stopped.
Note 4. When high-speed system clock and subsystem clock are stopped.
Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low
current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current
flowing into the 12-bit interval timer and watchdog timer.
Note 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
Note 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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(Notes and Remarks are listed on the next page.)
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current
Note 1
IDD1 Operating
mode HS (high-speed main)
mode Note 5 fHOCO = 64 MHz,
fIH = 32 MHz Note 3 Basic
operation VDD = 5.0 V 2.6 mA
VDD = 3.0 V 2.6
fHOCO = 32 MHz,
fIH = 32 MHz Note 3 Basic
operation VDD = 5.0 V 2.3
VDD = 3.0 V 2.3
HS (high-speed main)
mode Note 5 fHOCO = 64 MHz,
fIH = 32 MHz Note 3 Normal
operation VDD = 5.0 V 5.8 10.2 mA
VDD = 3.0 V 5.8 10.2
fHOCO = 32 MHz,
fIH = 32 MHz Note 3 Normal
operation VDD = 5.0 V 5.4 9.6
VDD = 3.0 V 5.4 9.6
fHOCO = 48 MHz,
fIH = 24 MHz Note 3 Normal
operation VDD = 5.0 V 4.5 7.8
VDD = 3.0 V 4.5 7.8
fHOCO = 24 MHz,
fIH = 24 MHz Note 3 Normal
operation VDD = 5.0 V 4.2 7.4
VDD = 3.0 V 4.2 7.4
fHOCO = 16 MHz,
fIH = 16 MHz Note 3 Normal
operation VDD = 5.0 V 3.1 5.3
VDD = 3.0 V 3.1 5.3
LS (low-speed main)
mode Note 5 fHOCO = 8 MHz,
fIH = 8 MHz Note 3 Normal
operation VDD = 3.0 V 1.4 2.3 mA
VDD = 2.0 V 1.4 2.3
LV (low-voltage main)
mode Note 5 fHOCO = 4 MHz,
fIH = 4 MHz Note 3 Normal
operation VDD = 3.0 V 1.4 1.9 mA
VDD = 2.0 V 1.4 1.9
HS (high-speed main)
mode Note 5 fMX = 20 MHz Note 2,
VDD = 5.0 V Normal
operation Square wave input 3.7 6.2 mA
Resonator connection 3.9 6.4
fMX = 20 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 3.7 6.2
Resonator connection 3.9 6.4
fMX = 10 MHz Note 2,
VDD = 5.0 V Normal
operation Square wave input 2.2 3.6
Resonator connection 2.3 3.7
fMX = 10 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 2.2 3.6
Resonator connection 2.3 3.7
LS (low-speed main)
mode Note 5 fMX = 8 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 1.3 2.2 mA
Resonator connection 1.3 2.3
fMX = 8 MHz Note 2,
VDD = 2.0 V Normal
operation Square wave input 1.3 2.2
Resonator connection 1.3 2.3
Subsystem clock
operation fSUB = 32.768 kHz Note 4
TA = -40 CNormal
operation Square wave input 5.0 7.1 A
Resonator connection 5.0 7.1
fSUB = 32.768 kHz Note 4
TA = +25 CNormal
operation Square wave input 5.0 7.1
Resonator connection 5.0 7.1
fSUB = 32.768 kHz Note 4
TA = +50 CNormal
operation Square wave input 5.1 8.8
Resonator connection 5.1 8.8
fSUB = 32.768 kHz Note 4
TA = +70 CNormal
operation Square wave inpu t 5.5 10.5
Resonator connection 5.5 10.5
fSUB = 32.768 kHz Note 4
TA = +85 CNormal
operation Square wave inpu t 6.5 14.5
Resonator connection 6.5 14.5
(1/2)
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Note 1. Total current flowing into VDD, EVDD0, and EVDD1, including the inp ut leakage current flowing when the level of the input
pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter,
comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
Note 2. When high-speed on-chip oscillator and subsystem clock are stopped.
Note 3. When high-speed system clock and subsystem clock are stopped.
Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power
consumption oscillation). However, not including the current flowing into the 12-bit interval timer and watchdog timer.
Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25 °C
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 59 of 187
Oct 25, 2013
(Notes and Remarks are listed on the next page.)
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current Note 1 IDD2
Note 2 HALT mode HS (high-speed main)
mode Note 7 fHOCO = 64 MHz,
fIH = 32 MHz Note 4 VDD = 5.0 V 0.88 3.32 mA
VDD = 3.0 V 0.88 3.32
fHOCO = 32 MHz,
fIH = 32 MHz Note 4 VDD = 5.0 V 0.62 2.63
VDD = 3.0 V 0.62 2.63
fHOCO = 48 MHz,
fIH = 24 MHz Note 4 VDD = 5.0 V 0.68 2.57
VDD = 3.0 V 0.68 2.57
fHOCO = 24 MHz,
fIH = 24 MHz Note 4 VDD = 5.0 V 0.50 2.00
VDD = 3.0 V 0.50 2.00
fHOCO = 16 MHz,
fIH = 16 MHz Note 4 VDD = 5.0 V 0.44 1.49
VDD = 3.0 V 0.44 1.49
LS (low-speed main)
mode Note 7 fHOCO = 8 MHz,
fIH = 8 MHz Note 4 VDD = 3.0 V 290 800 A
VDD = 2.0 V 290 800
LV (low-voltage main)
mode Note 7 fHOCO = 4 MHz,
fIH = 4 MHz Note 4 VDD = 3.0 V 440 755 A
VDD = 2.0 V 440 755
HS (high-speed main)
mode Note 7 fMX = 20 MHz Note 3,
VDD = 5.0 V Square wave input 0.31 1.63 mA
Resonator connection 0.50 1.85
fMX = 20 MHz Note 3,
VDD = 3.0 V Square wave input 0.31 1.63
Resonator connection 0.50 1.85
fMX = 10 MHz Note 3,
VDD = 5.0 V Square wave input 0.21 0.89
Resonator connection 0.30 0.97
fMX = 10 MHz Note 3,
VDD = 3.0 V Square wave input 0.21 0.89
Resonator connection 0.30 0.97
LS (low-speed main)
mode Note 7 fMX = 8 MHz Note 3,
VDD = 3.0 V Square wave input 110 580 A
Resonator connection 160 630
fMX = 8 MHz Note 3,
VDD = 2.0 V Square wave input 110 580
Resonator connection 160 630
Subsystem clock
operation fSUB = 32.768 kHz Note 5,
TA = -40 CSquare wave input 0.28 0.66 A
Resonator connection 0.47 0.85
fSUB = 32.768 kHz Note 5,
TA = +25 CSquare wave input 0.34 0.66
Resonator connection 0.53 0.85
fSUB = 32.768 kHz Note 5,
TA = +50 CSquare wave input 0.37 2.35
Resonator connection 0.56 2.54
fSUB = 32.768 kHz Note 5,
TA = +70 CSquare wave input 0.61 4.08
Resonator connection 0.80 4.27
fSUB = 32.768 kHz Note 5,
TA = +85 CSquare wave input 1.55 8.09
Resonator connection 1.74 8.28
IDD3
Note 6 STOP mode
Note 8 TA = -40 C0.19 0.57 A
TA = +25 C0.25 0.57
TA = +50 C0.33 2.26
TA = +70 C0.52 3.99
TA = +85 C1.46 8.00
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Note 1. Total current flowing into VDD, EVDD0, and EVDD1, including the inp ut leakage current flowing when the level of the input
pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter,
comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
Note 2. During HALT instruction execution by flash memory.
Note 3. When high-speed on-chip oscillator and subsystem clock are stopped.
Note 4. When high-speed system clock and subsystem clock are stopped.
Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low
current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current
flowing into the 12-bit interval timer and watchdog timer.
Note 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
Note 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 61 of 187
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Note 1. Current flowing to VDD.
Note 2. When high speed on-chip oscillator and high-speed system clock are stopped.
Note 3. Current flowing only to the real-time clock (RTC) (excluding the oper ating curr ent of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and
IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock.
Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the lo w-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
(3) Peripheral Functions (Common to all products)
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-speed on-chip
oscillator operating current IFIL Note 1 0.20 A
RTC operating current IRTC Notes 1, 2, 3 0.02 A
12-bit interval timer
operating current IIT Notes 1, 2, 4 0.02 A
Watchdog timer operating
current IWDT Notes 1, 2, 5 fIL = 15 kHz 0.22 A
A/D converter operating
current IADC Notes 1, 6 When conv er si o n at m ax i m um
speed Normal mode,
AVREFP = VDD = 5.0 V 1.3 1.7 mA
Low voltage mode,
AVREFP = VDD = 3.0 V 0.5 0.7 mA
A/D converter reference
voltage current IADREF Note 1 75.0 A
Temperature sensor
operating current ITMPS Note 1 75.0 A
D/A converter operating
current IDAC Notes 1, 11, 13 Per D/A converter channel 1.5 mA
Comparator operating
current ICMP Notes 1, 12, 13 VDD = 5.0 V,
Regulator output vo ltage = 2.1 V Window mode 12.5 A
Comparator high-speed mode 6.5 A
Comparator low-speed mode 1.7 A
VDD = 5.0 V,
Regulator output vo ltage = 1.8 V Window mode 8.0 A
Comparator high-speed mode 4.0 A
Comparator low-speed mode 1.3 A
LVD operating current ILVD Notes 1, 7 0.08 A
Self-programming operat ing
current IFSP Notes 1, 9 2.50 12.20 mA
BGO operating current IBGO Notes 1, 8 2.50 12.20 mA
SNOOZE operating current ISNOZ Note 1 ADC operat ion The mode is performed Note 10 0.50 0.60 mA
The A/D conversion
operations are performed,
Low voltage mode,
AVREFP = VDD = 3.0 V
1.20 1.44
CSI/UART operation 0.70 0.84
DTC operation 3.10
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Note 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, I DD2 or IDD3 and IWDT when the wat chdog timer is in
operation.
Note 6. Current flowing only to the A/D converter. The supply cur rent of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC when the A/D converter operates in an operation mode or the HALT mode.
Note 7. Current flowing only to the L VD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVD when the LVD circuit is in operation.
Note 8. Current flowing during programming of the data flash.
Note 9. Current flowing during self-programming.
Note 10. For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/G14 User’s Manual Hardware.
Note 11. Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IDAC when the D/A converter operates in an operation mode or the HALT mode.
Note 12. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or
IDD3 and ICMP when the comparator circuit is in operation.
Note 13. A comparator and D/A converter are provided in products with 96 KB or more code flash memory.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK: CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25 C
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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2.4 AC Characteristics
Note The following conditions are required for low voltage interface when EVDD0 < VDD
1.8 V EVDD0 < 2.7 V: MIN. 125 ns
1.6 V EVDD0 < 1.8 V: MIN. 250 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode registe r mn ( TMRmn). m: Un it nu mber (m = 0, 1), n: Chann el
number (n = 0 to 3))
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle
(minimum instruction
execution time)
TCY Main system
clock (fMAIN)
operation
HS (high-speed main)
mode 2.7 V VDD 5.5 V 0.03125 1 s
2.4 V VDD < 2.7 V 0.0625 1 s
LS (low-speed main)
mode 1.8 V VDD 5.5 V 0.125 1 s
L V (low-volt age main)
mode 1.6 V VDD 5.5 V 0.25 1 s
Subsystem clock (fSUB) operation 1.8 V VDD 5.5 V 28.5 30.5 31.3 s
In the self-
programming
mode
HS (high-speed main)
mode 2.7 V VDD 5.5 V 0.03125 1 s
2.4 V VDD < 2.7 V 0.0625 1 s
LS (low-speed main)
mode 1.8 V VDD 5.5 V 0.125 1 s
L V (low-volt age main)
mode 1.8 V VDD 5.5 V 0.25 1 s
External system cl ock
frequency fEX 2.7 V VDD 5.5 V 1.0 20.0 MHz
2.4 V VDD 2.7 V 1.0 16.0 MHz
1.8 V VDD < 2.4 V 1.0 8.0 MHz
1.6 V VDD < 1.8 V 1.0 4.0 MHz
fEXS 32 35 kHz
External system cl ock
input high-level width,
low-level width
tEXH,
tEXL
2.7 V VDD 5.5 V 24 ns
2.4 V VDD 2.7 V 30 ns
1.8 V VDD < 2.4 V 60 ns
1.6 V VDD < 1.8 V 120 ns
tEXHS,
tEXLS 13.7 s
TI00 to TI03, TI10 to
TI13 input high-level
width, low-level width
tTIH, tTIL 1/fMCK + 10
Note ns
Timer RJ input cycle fCTRJIO 2.7 V EVDD0 5.5 V 100 ns
1.8 V EVDD0 < 2.7 V 300 ns
1.6 V EVDD0 < 1.8 V 500 ns
Timer RJ input high-
level width, low-level
width
tTJIH,
tTJIL
TRJIO 2.7 V EVDD0 5.5 V 40 ns
1.8 V EVDD0 < 2.7 V 120 ns
1.6 V EVDD0 < 1.8 V 200 ns
(1/2)
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Items Symbol Conditions MIN. TYP. MAX. Unit
Timer RD input high-level
width, low-level width tTDIH,
tTDIL
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 3/fCLK ns
T imer RD forced cutof f signal
input low-level width tTDSIL P130/INTP0 2MHz < fCLK 32 MHz 1 s
fCLK 2 MHz 1/fCLK + 1
Timer RG input high-level
width, low-level width tTGIH,
tTGIL
TRGIOA, TRGIOB 2.5/fCLK ns
TO00 to TO03,
TO10 to TO13,
TRJIO0, TRJO0,
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRGIOA, TRGIOB
output frequency
fTO HS (high-speed main) mode 4.0 V EVDD0 5.5 V 16 MHz
2.7 V EVDD0 < 4.0 V 8 MHz
1.8 V EVDD0 < 2.7 V 4 MHz
1.6 V EVDD0 < 1.8 V 2 MHz
LS (low-speed main) mode 1.8 V EVDD0 5.5 V 4 MHz
1.6 V EVDD0 < 1.8 V 2 MHz
LV (low-voltage main) mode 1.6 V EVDD0 5.5 V 2MHz
PCLBUZ0, PCLBUZ1 output
frequency fPCL HS (high-speed main) mode 4.0 V EVDD0 5.5 V 16 MHz
2.7 V EVDD0 < 4.0 V 8 MHz
1.8 V EVDD0 < 2.7 V 4 MHz
1.6 V EVDD0 < 1.8 V 2 MHz
LS (low-speed main) mode 1.8 V EVDD0 5.5 V 4 MHz
1.6 V EVDD0 < 1.8 V 2 MHz
LV (low-voltage main) mode 1.8 V EVDD0 5.5 V 4 MHz
1.6 V EVDD0 < 1.8 V 2 MHz
Interrupt input high-level
width, low-level width tINTH,
tINTL
INTP0 1.6 V VDD 5.5 V 1 s
INTP1 to INTP11 1.6 V EVDD0 5.5 V 1 s
Key interrupt input low-level
width tKR KR0 to KR7 1.8 V EVDD0 5.5 V 250 ns
1.6 V EVDD0 < 1.8 V 1 s
RESET low-level width tRSL 10 s
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode )
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
2.4
0.03125
0.0625
0.05
Cycle time TCY [µs]
Supply voltage VDD [V]
During self-programming
When high-speed system clock is selected
When the high-speed on-chip oscillator clock is selected
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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TCY vs VDD (LS (low-spee d main) mode)
TCY vs VDD (LV (low-voltage main) mode)
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 5.5
0.01
Cycle time TCY [µs]
Supply voltage VDD [V]
1.8 6.0
0.125
During self-programming
When high-speed system clock is selected
When the high-speed on-chip oscillator clock is selected
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0
0.01
Cycle time TCY [µs]
Supply voltage VDD [V]
1.6 6.0
1.8 5.5
0.25
During self-programming
When high-speed system clock is selected
When the high-speed on-chip oscillator clock is selected
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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AC Timing Test Points
External System Clock Timing
TI/TO T iming
VIH/VOH
VIL/VOL
VIH/VOH
Test points VIL/VOL
EXCLK/EXCLKS
1/fEX
1/fEXS
tEXL
tEXLS tEXH
tEXHS
tTIL tTIH
1/fTO
TI00 to TI03, TI10 to TI13
TO00 to TO03, TO10 to TO13,
TRJIO0, TRJO0,
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRGIOA , TRGIOB
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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tTJIL
TRJIO
tTJIH
tTDIL
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1
tTDIH
tTDSIL
INTP0
tTGIL
TRGIOA , TR GIOB
tTGIH
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Interrupt Request Input Timing
Key Interrupt Input Timing
RESET Input Timing
INTP0 to INTP11
tINTL tINTH
tKR
KR0 to KR7
tRSL
RESET
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2.5 Peripheral Functions Characteristics
AC Timing Test Points
2.5.1 Serial array unit
Note 1. Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2. The following conditions are required for low voltage interface when EVDD0 VDD.
2.4 V EVDD0 2.7 V: MAX. 2.6 Mbps
1.8 V EVDD0 2.4 V: MAX. 1.3 Mbps
1.6 V EVDD0 1.8 V: MAX. 0.6 Mbps
Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
(1) During communication at same potential (UART mode)
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
Mode LS (low-speed main)
Mode
LV (low-voltage m ain)
Mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate
Note 1 2.4 V EVDD0 5.5 V fMCK/6 Note 2 fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
5.3 1.3 0.6 Mbps
1.8 V EVDD0 5.5 V fMCK/6 Note 2 fMCK/6 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
5.3 1.3 0.6 Mbps
1.7 V EVDD0 5.5 V fMCK/6 Note 2 fMCK/6 Note 2 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
5.3 1.3 0.6 Mbps
1.6 V EVDD0 5.5 V — fMCK/6 Note 2 fMCK/6 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 3
— 1.3 0.6 Mbps
VIH/VOH
VIL/VOL
VIH/VOH
Test points VIL/VOL
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UART mode connection diagram (during communication at same potential)
UART mode bit width (during communication at same potential) (reference)
Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
RL78 microcont roller
TxDq
RxDq
User’s device
Rx
Tx
Baud rate error tolerance
TxDq
RxDq
High-/Low-bit width
1/Transfer rate
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. This value is valid only when CSI00’s peripheral I/O redirect function is not used.
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only )
(TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditi ons HS (high-speed
main) mode LS (low-speed
main) mode LV (low-voltage
main) mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 2/fCLK 4.0 V EVDD0 5.5 V 62.5 250 500 ns
2.7 V EVDD0 5.5 V 83.3 250 500 ns
SCKp high-/low-level
width tKH1,
tKL1
4.0 V EVDD0 5.5 V tKCY1/2 - 7 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V EVDD0 5.5 V tKCY1/2 - 10 tKCY1/2 - 50 tKCY1/2 - 50 ns
SIp setup time (t o SCKp↑)
Note 1 tSIK1 4.0 V EVDD0 5.5 V 23 110 110 ns
2.7 V EVDD0 5.5 V 33 110 110 ns
SIp hold time (from
SCKp↑) Note 2 tKSI1 2.7 V EVDD0 5.5 V 10 10 10 ns
Delay time fr om SCK p↓ to
SOp output Note 3 tKSO1 C = 20 pF Note 4 10 10 10 ns
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(3) D uring communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode LS (l ow-speed main)
mode LV (low-voltage
main) mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 4/fCLK 2.7 V EVDD0 5.5 V 125 500 1000 ns
2.4 V EVDD0 5.5 V 250 500 1000 ns
1.8 V EVDD0 5.5 V 500 500 1000 ns
1.7 V EVDD0 5.5 V 1000 1000 1000 ns
1.6 V EVDD0 5.5 V — 1000 1000 ns
SCKp high-/low-level
width tKH1,
tKL1 4.0 V EVDD0 5.5 V tKCY1/2 - 12 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V EVDD0 5.5 V tKCY1/2 - 18 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.4 V EVDD0 5.5 V tKCY1/2 - 38 tKCY1/2 - 50 tKCY1/2 - 50 ns
1.8 V EVDD0 5.5 V tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns
1.7 V EVDD0 5.5 V tKCY1/2 - 100 tKCY1/2 - 100 tKCY1/2 - 100 ns
1.6 V EVDD0 5.5 V —t
KCY1/2 - 100 tKCY1/2 - 100 ns
SIp setup time
(to SCKp↑) Note 1 tSIK1 4.0 V EVDD0 5.5 V 44 110 110 ns
2.7 V EVDD0 5.5 V 44 110 110 ns
2.4 V EVDD0 5.5 V 75 110 110 ns
1.8 V EVDD0 5.5 V 110 110 110 ns
1.7 V EVDD0 5.5 V 220 220 220 ns
1.6 V EVDD0 5.5 V —220220ns
SIp hold ti m e
(from SCKp↑) Note 2 tKSI1 1.7 V EVDD0 5.5 V 19 19 19 ns
1.6 V EVDD0 5.5 V —1919ns
Delay time from
SCKp↓ to SOp output
Note 3
tKSO1 1.7 V EVDD0 5.5 V
C = 30 pF Note 4 25 25 25 ns
1.6 V EVDD0 5.5 V
C = 30 pF Note 4 —2525ns
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SOp output lines.
Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
(4) D uring communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions
HS (high-speed main)
mode LS (low-speed main)
mode LV (low-voltage main)
mode
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle
time Note 5 tKCY2 4.0 V EVDD0 5.5 V 20 MHz fMCK 8/fMCK ——ns
fMCK 20 MHz 6/fMCK 6/fMCK 6/fMCK ns
2.7 V EVDD0 5.5 V 16 MHz fMCK 8/fMCK ——ns
fMCK 16 MHz 6/fMCK 6/fMCK 6/fMCK ns
2.4 V EVDD0 5.5 V 6/fMCK
and 500 6/fMCK
and 500 6/fMCK
and 500 ns
1.8 V EVDD0 5.5 V 6/fMCK
and 750 6/fMCK
and 750 6/fMCK
and 750 ns
1.7 V EVDD0 5.5 V 6/fMCK
and 1500 6/fMCK
and 1500 6/fMCK
and 1500 ns
1.6 V EVDD0 5.5 V —6/f
MCK
and 1500 6/fMCK
and 1500 ns
SCKp high-/
low-level width tKH2,
tKL2 4.0 V EVDD0 5.5 V tKCY2/2 - 7 tKCY2/2 - 7 tKCY2/2 - 7 ns
2.7 V EVDD0 5.5 V tKCY2/2 - 8 tKCY2/2 - 8 tKCY2/2 - 8 ns
1.8 V EVDD0 5.5 V tKCY2/2 - 18 tKCY2/2 - 18 tKCY2/2 - 18 ns
1.7 V EVDD0 5.5 V tKCY2/2 - 66 tKCY2/2 - 66 tKCY2/2 - 66 ns
1.6 V EVDD0 5.5 V —t
KCY2/2 - 66 tKCY2/2 - 66 ns
SIp setup time
(to SCKp↑)
Note 1
tSIK2 2.7 V EVDD0 5.5 V 1/fMCK + 20 1/fMCK + 30 1/fMCK + 30 ns
1.8 V EVDD0 5.5 V 1/fMCK + 30 1/fMCK + 30 1/fMCK + 30 ns
1.7 V EVDD0 5.5 V 1/fMCK + 40 1/fMCK + 40 1/fMCK + 40 ns
1.6 V EVDD0 5.5 V —1/f
MCK + 40 1/fMCK + 40 ns
SIp hold ti m e
(from SCKp↑)
Note 2
tKSI2 1.8 V EVDD0 5.5 V 1/fMCK + 31 1/fMCK + 31 1/fMCK + 31 ns
1.7 V EVDD0 5.5 V 1/fMCK + 250 1/fMCK + 250 1/fMCK + 250 ns
1.6 V EVDD0 5.5 V —1/f
MCK + 250 1/fMCK + 250 ns
Delay time
from SCKp↓ to
SOp output
Note 3
tKSO2 C = 30 pF Note 4 2.7 V EVDD0 5.5 V 2/fMCK
+ 44 2/fMCK
+ 110 2/fMCK
+ 110 ns
2.4 V EVDD0 5.5 V 2/fMCK
+ 75 2/fMCK
+ 110 2/fMCK
+ 110 ns
1.8 V EVDD0 5.5 V 2/fMCK
+ 100 2/fMCK
+ 110 2/fMCK
+ 110 ns
1.7 V EVDD0 5.5 V 2/fMCK
+ 220 2/fMCK
+ 220 2/fMCK
+ 220 ns
1.6 V EVDD0 5. 5 V —2/f
MCK
+ 220 2/fMCK
+ 220 ns
(1/2)
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Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5)
CSI mode connection diagram (during communication at same potential)
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
(4) D uring communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main)
mode LV (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SSI00 setup time tSSIK DAPmn = 0 2.7 V EVDD0 5.5 V 120 120 120 ns
1.8 V EVDD0 5.5 V 200 200 200 ns
1.7 V EVDD0 5.5 V 400 400 400 ns
1.6 V EVDD0 5.5 V — 400 400 ns
DAPmn = 1 2.7 V EVDD0 5.5 V 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 ns
1.8 V EVDD0 5.5 V 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 ns
1.7 V EVDD0 5.5 V 1/fMCK + 400 1/fMCK + 400 1/fMCK + 400 ns
1.6 V EVDD0 5.5 V —1/f
MCK + 400 1/fMCK + 400 ns
SSI00 hold time tKSSI DAPmn = 0 2.7 V EVDD0 5.5 V 1/fMCK + 120 1/fMCK + 120 1/fMCK + 120 ns
1.8 V EVDD0 5.5 V 1/fMCK + 200 1/fMCK + 200 1/fMCK + 200 ns
1.7 V EVDD0 5.5 V 1/fMCK + 400 1/fMCK + 400 1/fMCK + 400 ns
1.6 V EVDD0 5.5 V —1/f
MCK + 400 1/fMCK + 400 ns
DAPmn = 1 2.7 V EVDD0 5.5 V 120 120 120 ns
1.8 V EVDD0 5.5 V 200 200 200 ns
1.7 V EVDD0 5.5 V 400 400 400 ns
1.6 V EVDD0 5.5 V — 400 400 ns
SCKp
SOp
User's device
SCK
SI
SIp SO
RL78 microcontroller
SCK00
SO00 User's device
SCK
SI
SI00 SO
SSI00 SSO
RL78 microcont roller
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CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
SIp
SOp
tKCY1, 2
Input data
Output data
SCKp
tKL1, 2 tKH1, 2
SSI00
(CSI00 only)
tSIK1, 2 tKSI1, 2
tKSO1, 2
tSSIK tKSSI
Input data
Output data
tKCY1, 2
tKH1, 2
tSIK1, 2 tKSI1, 2
tKSO1, 2
tSSIK tKSSI
SIp
SOp
SCKp
SSI00
(CSI00 only)
tKL1, 2
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(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
(5) During communication at same potential (simplified I2C mode)
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main)
mode LV (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLr clock frequency fSCL 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1000 Note 1 400 Note 1 400 Note 1 kHz
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
400 Note 1 400 Note 1 400 Note 1 kHz
1.8 V EVDD0 2.7 V,
Cb = 100 pF, Rb = 5 k
300 Note 1 300 Note 1 300 Note 1 kHz
1.7 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
250 Note 1 250 Note 1 250 Note 1 kHz
1.6 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
—250 Note 1 250 Note 1 kHz
Hold time
when SCLr = “L” tLOW 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
475 1150 1150 ns
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
1150 1150 1150 ns
1.8 V EVDD0 2.7 V,
Cb = 100 pF, Rb = 5 k
1550 1550 1550 ns
1.7 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
1850 1850 1850 ns
1.6 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
— 1850 1850 ns
Hold time
when SCLr = “H” tHIGH 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
475 1150 1150 ns
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
1150 1150 1150 ns
1.8 V EVDD0 2.7 V,
Cb = 100 pF, Rb = 5 k
1550 1550 1550 ns
1.7 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
1850 1850 1850 ns
1.6 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
— 1850 1850 ns
(1/2)
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Note 1. The value must also be equal to or less than fMCK/4.
Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD
tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by
using port input mode register g (PIMg) and port output mode register h (POMh).
(Remarks are listed on the next page.)
(5) During communication at same potential (simplified I2C mode)
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main)
mode LV (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Data setup time
(reception) tSU: DAT 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 85 Note 2 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 ns
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 1/fMCK + 145 Note 2 ns
1.8 V EVDD0 2.7 V,
Cb = 100 pF, Rb = 5 k
1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 1/fMCK + 230 Note 2 ns
1.7 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 ns
1.6 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
—1/fMCK + 290 Note 2 1/fMCK + 290 Note 2 ns
Data hold time
(transmission) tHD: DAT 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
030503050305ns
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
035503550355ns
1.8 V EVDD0 2.7 V,
Cb = 100 pF, Rb = 5 k
040504050405ns
1.7 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
040504050405ns
1.6 V EVDD0 1.8 V,
Cb = 100 pF, Rb = 5 k
— 0 405 0 405 ns
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Simplified I2C mode connection diagram (during communication at same potential)
Simplified I2C mode serial transfer timing (during co mmunication at same potential)
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 3 to 5, 14),
h: POM number (h = 0, 1, 3 to 5, 7, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
RL78 microcont roller
SDAr
SCLr
User’s device
SDA
SCL
VDD
Rb
SDAr
SCLr
1/fSCL
tLOW tHIGH
tSU: DATtHD: DAT
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Note 1. Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2. Use it with EVDD0 Vb.
Note 3. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V EVDD0 2.7 V: MAX. 2.6 Mbps
1.8 V EVDD0 2.4 V: MAX. 1.3 Mbps
Note 4. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
LS (low-speed main) mode: 8 MHz (1.8 V VDD 5.5 V)
LV (low-voltage main) mode: 4 MHz (1.6 V VDD 5.5 V)
Caution Select the TTL in put buffer for the RxDq pin and the N-ch op en drain output (VDD tolerance (When 30- to 52-p in
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
Remark 1. Vb [V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR 0) is
1.
(6) Communicatio n at di fferent potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main)
mode LV (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer
rate reception 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 4
5.3 1.3 0.6 Mbps
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V fMCK/6 Note 1 fMCK/6 Note 1 fMCK/6 Note 1 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 4
5.3 1.3 0.6 Mbps
1.8 V EVDD0 3.3 V,
1.6 V Vb 2.0 V fMCK/6
Notes 1, 2, 3 fMCK/6
Notes 1, 2 fMCK/6
Notes 1, 2 bps
Theoretical value of the
maximum transfer rate
fMCK = fCLK Note 4
5.3 1.3 0.6 Mbps
(1/2)
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 82 of 187
Oct 25, 2013
Note 1.
The smaller maximum transfer rate derived by using f
MCK
/6 or the following expression is the valid maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V and 2.7 V Vb 4.0 V
Note 2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Note 3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V and 2.3 V Vb 2.7 V
Note 4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
Note 5. Use it with EVDD0 Vb.
(6) Communicatio n at di fferent potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main)
mode L V (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer
rate transmission 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V Note 1 Note 1 Note 1 bps
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 1.4 k,
Vb = 2.7 V
2.8 Note 2 2.8 Note 2 2.8 Note 2 Mbps
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V Note 3 Note 3 Note 3 bps
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 2.7 k,
Vb = 2.3 V
1.2 Note 4 1.2 Note 4 1.2 Note 4 Mbps
1.8 V EVDD0 3.3 V,
1.6 V Vb 2.0 V
Notes 5, 6 Notes 5, 6 Notes 5, 6 bps
Theoretical value of the
maximum transfer rate
Cb = 50 pF, Rb = 5.5 k,
Vb = 1.6 V
0.43 Note 7 0.43 Note 7 0.43 Note 7 Mbps
Maximum transfer rat e =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
2.2
Vb
{-Cb Rb In (1 - )}
2.2
Vb
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
2.0
Vb
{-Cb Rb In (1 - )}
2.0
Vb
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
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R01DS0053EJ0200 Rev. 2.00 Page 83 of 187
Oct 25, 2013
Note 6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 1.8 V EVDD0 < 3.3 V and 1.6 V Vb 2.0 V
Note 7. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL in put buffer for the RxDq pin and the N-ch op en drain output (VDD tolerance (When 30- to 52-p in
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
(Remarks are listed on the next page.)
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
1.5
Vb
{-Cb Rb In (1 - )}
1.5
Vb
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
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Oct 25, 2013
UART mode connection diagra m (du r ing commu nic a tio n at different potential)
UART mode bit width (during communication at different potential) (reference)
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR 0) is
1.
RL78 microcont roller
TxDq
RxDq
User’s device
Rx
Tx
Vb
Rb
Baud rate error tolerance
High-/Low -bit width
1/Transfer rate
Baud rate error tolerance
High-bit width
Low-bit width
1/Transfer rate
TxDq
RxDq
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 85 of 187
Oct 25, 2013
(Notes, Caution, and Remarks are listed on the next page.)
(7) C ommunication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only )
(TA = -40 to +8 5 C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode LS (low-speed main)
mode LV (low-voltage
main) mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 2/fCLK 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
200 1150 1150 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
300 1150 1150 ns
SCKp high-level
width tKH1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKCY1/2 - 120 tKCY1/2 - 120 tKCY1/2 - 120 ns
SCKp low-level
width tKL1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
tKCY1/2 - 7 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
tKCY1/2 - 10 tKCY1/2 - 50 tKCY1/2 - 50 ns
SIp setup time
(to SCKp↑) Note 1 tSIK1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
58 479 479 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
121 479 479 ns
SIp hold ti m e
(from SC Kp↑) Note 1 tKSI1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
10 10 10 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
10 10 10 ns
Delay time from
SCKpto SOp
output Note 1
tKSO1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
60 60 60 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
130 130 130 ns
(1/2)
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Note 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
Remark 1. Rb[]: Communication line ( SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM and POM number (g = 3, 5)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number
(mn = 00))
Remark 4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.
(7) C ommunication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only )
(TA = -40 to +8 5 C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main )
mode L V (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
(to SCKp) Note 2 tSIK1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
23 110 110 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
33 110 110 ns
SIp hold ti m e
(from SC Kp) Note 2 tKSI1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
10 10 10 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
10 10 10 ns
Delay time from SCKp↑
to SOp output Note 2 tKSO1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
10 10 10 ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
10 10 10 ns
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Oct 25, 2013
Note Use it with EVDD0 Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +8 5 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode LS (low-speed main)
mode LV (low-voltage
main) mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time tKCY1 tKCY1 4/fCLK 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
300 1150 1150 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
500 1150 1150 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note,
Cb = 30 pF, Rb = 5.5 k
1150 1150 1150 ns
SCKp high-level
width tKH1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 75 tKCY1/2 - 75 tKCY1/2 - 75 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 170 tKCY1/2 - 170 tKCY1/2 - 170 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 458 tKCY1/2 - 458 tKCY1/2 - 458 ns
SCKp low-level
width tKL1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 12 tKCY1/2 - 50 tKCY1/2 - 50 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 18 tKCY1/2 - 50 tKCY1/2 - 50 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 50 tKCY1/2 - 50 tKCY1/2 - 50 ns
(1/3)
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Oct 25, 2013
Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Note 2. Use it with EVDD0 Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +8 5 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/3)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main)
mode LV (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
(to SCKp↑) Note 1 tSIK1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
81 479 479 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
177 479 479 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
479 479 479 ns
SIp hold ti m e
(from SC Kp↑) Note 1 tKSI1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
19 19 19 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
19 19 19 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
19 19 19 ns
Delay time from SCKp↓
to SOp output Note 1 tKSO1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
100 100 100 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
195 195 195 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
483 483 483 ns
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R01DS0053EJ0200 Rev. 2.00 Page 89 of 187
Oct 25, 2013
Note 1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. Use it with EVDD0 Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +8 5 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/3)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main)
mode LV (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SIp setup time
(to SCKp↓) Note 1 tSIK1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
44 110 110 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
44 110 110 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
110 110 110 ns
SIp hold ti m e
(from SC Kp↓) Note 1 tKSI1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
19 19 19 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
19 19 19 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
19 19 19 ns
Delay time from SCKp↑
to SOp output Note 1 tKSO1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
25 25 25 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
25 25 25 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 30 pF, Rb = 5.5 k
25 25 25 ns
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 90 of 187
Oct 25, 2013
CSI mode connection diagram (during communication at d ifferent potential
Remark 1. Rb[]: Communication lin e (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
Remark 4. CSI01 of 48- , 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other C SI for
communication at different potential.
SCKp
SOp
User’s device
SCK
SI
SIp SO
Vb
Rb
<Master> Vb
Rb
RL78 microcontroller
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
R01DS0053EJ0200 Rev. 2.00 Page 91 of 187
Oct 25, 2013
CSI mode serial transfer timing (master mode) (during communicatio n at di ffe re nt potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (master mode) (during communicatio n at di ffe re nt potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 2. CSI01 of 48- , 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other C SI for
communication at different potential.
Input data
SIp
SOp
tKCY1
tKL1 tKH1
tSIK1 tKSI1
tKSO1
Output data
SCKp
Input data
Output data
SIp
SOp
SCKp
tKCY1
tKH1 tKL1
tSIK1 tKSI1
tKSO1
RL78/G14 2. ELECTRICAL SPECIFICATIONS (A, D: TA = -40 to +85 C)
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Oct 25, 2013
(Notes, Cautions, and Remarks are listed on the next page.)
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = -40 to +8 5 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode LS (low-speed
main) mode LV (low-voltage
main) mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time
Note 1 tKCY2 4.0 V EVDD0 5. 5 V,
2.7 V Vb 4.0 V 24 MHz fMCK 14/fMCK ——ns
20 MHz fMCK 24 MHz 12/fMCK ——ns
8 MHz fMCK 20 MHz 10/fMCK ——ns
4 MHz fMCK 8 MHz 8/fMCK 16/fMCK —ns
fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V 24 MHz fMCK 20/fMCK ——ns
20 MHz fMCK 24 MHz 16/fMCK ——ns
16 MHz fMCK 20 MHz 14/fMCK ——ns
8 MHz fMCK 16 MHz 12/fMCK ——ns
4 MHz fMCK 8 MHz 8/fMCK 16/fMCK —ns
fMCK 4 MHz 6/fMCK 10/fMCK 10/fMCK ns
1.8 V EVDD0 3.3 V,
1.6 V Vb 2.0 V
Note 2
24 MHz fMCK 48/fMCK ——ns
20 MHz fMCK 24 MHz 36/fMCK ——ns
16 MHz fMCK 20 MHz 32/fMCK ——ns
8 MHz fMCK 16 MHz 26/fMCK ——ns
4 MHz fMCK 8 MHz 16/fMCK 16/fMCK —ns
fMCK 4 MHz 10/fMCK 10/fMCK 10/fMCK ns
SCKp high-/
low-level width tKH2,
tKL2
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V tKCY2/2
- 12 tKCY2/2
- 50 tKCY2/2
- 50 ns
2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V tKCY2/2
- 18 tKCY2/2
- 50 tKCY2/2
- 50 ns
1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Note 2 tKCY2/2
- 50 tKCY2/2
- 50 tKCY2/2
- 50 ns
SIp setup time
(to SCKp↑) Note 3 tSIK2 4.0 V EVDD0 5.5 V, 2. 7 V Vb 4.0 V 1/fMCK
+ 20 1/fMCK
+ 30 1/fMCK
+ 30 ns
2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V 1/fMCK
+ 20 1/fMCK
+ 30 1/fMCK
+ 30 ns
1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Note 2 1/fMCK
+ 30 1/fMCK
+ 30 1/fMCK
+ 30 ns
SIp hold t i m e
(from SC Kp↑)
Note 4
tKSI2 1/fMCK
+ 31 1/fMCK
+ 31 1/fMCK
+ 31 ns
Delay time from
SCKp to SOp
output Note 5
tKSO2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2/fMCK
+ 120 2/fMCK
+ 573 2/fMCK
+ 573 ns
2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2/fMCK
+ 214 2/fMCK
+ 573 2/fMCK
+ 573 ns
1.8 V EVDD0 3.3 V, 1.6 V Vb 2.0 V Note 2,
Cb = 30 pF, Rv = 5.5 k
2/fMCK
+ 573 2/fMCK
+ 573 2/fMCK
+ 573 ns
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Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Note 2. Use it with EVDD0 Vb.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input b uffer for the SIp pin and SCKp pin, and the N- ch open drain output (VDD tolerance (Wh en
30- to 52-pin prod ucts)/EVDD tolerance (when 64- to 100-pin prod ucts)) mode for the SOp p in b y using p ort inpu t
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13))
Remark 4. CSI01 of 48- , 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
SCKp
SOp
User’s device
SCK
SI
SIp SO
Vb
Rb
<Slave>
RL78 microcontroller
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CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 2. CSI01 of 48- , 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other CSI for
communication at different potential.
Also, communication at different potential cannot be performed dur ing clock synchronous serial communication with the
slave select function.
SIp
SOp
SCKp
Input data
Output data
tKCY2
tKH2tKL2
tSIK2 tKSI2
tKSO2
Input data
Output data
SIp
SOp
SCKp
tKCY2
tKL2tKH2
tSIK2 tKSI2
tKSO2
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(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +8 5 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main )
mode L V (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLr clock frequency fSCL 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1000 Note 1 300 Note 1 300 Note 1 kHz
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1000 Note 1 300 Note 1 300 Note 1 kHz
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
400 Note 1 300 Note 1 300 Note 1 kHz
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
400 Note 1 300 Note 1 300 Note 1 kHz
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
300 Note 1 300 Note 1 300 Note 1 kHz
Hold time when SCLr = “L” tLOW 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
475 1550 1550 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
475 1550 1550 ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1150 1550 1550 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1150 1550 1550 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
1550 1550 1550 ns
Hold time when SCLr = “H” tHIGH 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
245 610 610 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
200 610 610 ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
675 610 610 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
600 610 610 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
610 610 610 ns
(1/2)
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Note 1. The value must also be equal to or less than fMCK/4.
Note 2. Use it with EVDD0 Vb.
Note 3. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD
tolerance (When 64- to 100 -pin products)) mode for the SDAr pin and the N-ch ope n drain output ( VDD tolerance
(When 30- to 52-pin produc ts)/EVDD tolerance (When 64- to 100-pin products)) mode for the SCLr pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +8 5 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main)
mode LV (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Data setup time
(reception) tSU:DAT 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 135 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 1/fMCK + 190 Note 3 ns
Data hold time
(transmission) tHD:DAT 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
0 305 0 305 0 305 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
0 305 0 305 0 305 ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
0 355 0 355 0 355 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
0 355 0 355 0 355 ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V Note 2,
Cb = 100 pF, Rb = 5.5 k
0 405 0 405 0 405 ns
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Simplified I2C mode connection diagram (dur ing communic a tion at different potential)
Simplified I2C mode serial transfer timing (during communication at different potential)
Remark 1. Rb[]: Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 30, 31), g: PIM, POM number (g = 0, 1, 3 to 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 00, 01, 02, 10, 12, 13)
RL78 microcont roller
SDAr
SCLr
User’s device
SDA
SCL
Vb
Rb
Vb
Rb
SDAr
SCLr
1/fSCL
tLOW tHIGH
tSU: DATtHD: DAT
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2.5.2 Serial interface IICA
(Notes, Cautions, and Remarks are listed on the next page.)
(1) I2C standard mode
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main )
mode L V (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock
frequency fSCL S tand ard mode:
fCLK 1 MHz 2.7 V EVDD0 5.5 V 0 100 0 100 0 100 kHz
1.8 V EVDD0 5.5 V 0 100 0 100 0 100 kHz
1.7 V EVDD0 5.5 V 0 100 0 100 0 100 kHz
1.6 V EVDD0 5.5 V — 0 100 0 100 kHz
Setup time of
restart condition tSU: STA 2.7 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.8 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.7 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.6 V EVDD0 5.5 V — 4.7 4.7 s
Hold time Note 1 tHD: STA 2.7 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.8 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.7 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.6 V EVDD0 5.5 V — 4.0 4.0 s
Hold time when
SCLA0 = “L” tLOW 2.7 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.8 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.7 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.6 V EVDD0 5.5 V — 4.7 4.7 s
Hold time when
SCLA0 = “H” tHIGH 2.7 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.8 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.7 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.6 V EVDD0 5.5 V — 4.0 4.0 s
(1/2)
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Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is in serted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
(1) I2C standard mode
(TA = -40 to +8 5 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main)
mode LS (low-speed main )
mode L V (low-voltage main)
mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Data setup time (reception) tSU: DAT 2.7 V EVDD0 5.5 V 250 250 250 ns
1.8 V EVDD0 5.5 V 250 250 250 ns
1.7 V EVDD0 5.5 V 250 250 250 ns
1.6 V EVDD0 5.5 V — 250 250 ns
Data hold time (transmission)
Note 2 tHD: DAT 2.7 V EVDD0 5.5 V 0 3.45 0 3.45 0 3.45 s
1.8 V EVDD0 5.5 V 0 3.45 0 3.45 0 3.45 s
1.7 V EVDD0 5.5 V 0 3.45 0 3.45 0 3.45 s
1.6 V EVDD0 5.5 V — 03.4503.45s
Setup time of stop condition tSU: STO 2.7 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.8 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.7 V EVDD0 5.5 V 4.0 4.0 4.0 s
1.6 V EVDD0 5.5 V — 4.0 4.0 s
Bus-free time tBUF 2.7 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.8 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.7 V EVDD0 5.5 V 4.7 4.7 4.7 s
1.6 V EVDD0 5.5 V — 4.7 4.7 s
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Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is in serted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Fast mode: Cb = 320 pF, Rb = 1.1 k
(2) I2C fast mode
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode LS (low-speed
main) mode LV (low-voltage
main) mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode:
fCLK 3.5 MHz 2.7 V EVDD0 5.5 V 0 400 0 400 0 400 kHz
1.8 V EVDD0 5.5 V 0 400 0 400 0 400 kHz
Setup time of restart
condition tSU: STA 2.7 V EVDD0 5.5 V 0.6 0.6 0.6 s
1.8 V EVDD0 5.5 V 0.6 0.6 0.6 s
Hold time Note 1 tHD: STA 2.7 V EVDD0 5.5 V 0.6 0.6 0.6 s
1.8 V EVDD0 5.5 V 0.6 0.6 0.6 s
Hold time when SCLA0 = “L” tLOW 2.7 V EVDD0 5.5 V 1.3 1.3 1.3 s
1.8 V EVDD0 5.5 V 1.3 1.3 1.3 s
Hold time when SCLA0 = “H” tHIGH 2.7 V EVDD0 5.5 V 0.6 0.6 0.6 s
1.8 V EVDD0 5.5 V 0.6 0.6 0.6 s
Data setup time (reception) tSU: DA T 2.7 V EVDD0 5.5 V 100 100 100 ns
1.8 V EVDD0 5.5 V 100 100 100 ns
Data hold time (transmission)
Note 2 tHD: DAT 2.7 V EVDD0 5.5 V 0 0.9 0 0.9 0 0.9 s
1.8 V EVDD0 5.5 V 0 0.9 0 0.9 0 0.9 s
Setup time of stop condition tSU: STO 2.7 V EVDD0 5.5 V 0.6 0.6 0.6 s
1.8 V EVDD0 5.5 V 0.6 0.6 0.6 s
Bus-free time tBUF 2.7 V EVDD0 5.5 V 1.3 1.3 1 .3 s
1.8 V EVDD0 5.5 V 1.3 1.3 1.3 s
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Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is in serted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Note 3. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Fast mode plus: Cb = 120 pF, Rb = 1.1 k
IICA serial transfer timing
Remark n = 0, 1
(3) I2C fast mode plus
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed
main) mode LS (low-speed
main) mode LV (low-voltage
main) mode Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode plus:
fCLK 10 MHz 2.7 V EVDD0 5.5 V 0 1000 — — kHz
Setup time of restart
condition tSU: STA 2.7 V EVDD0 5.5 V 0.26 — — s
Hold time Note 1 tHD: STA 2.7 V EVDD0 5.5 V 0.26 — — s
Hold time when SCLA0 = “L” tLOW 2.7 V EVDD0 5.5 V 0.5 — — s
Hold time when SCLA0 = “H” tHIGH 2.7 V EVDD0 5.5 V 0.26 — — s
Data setup time (reception) tSU: DA T 2.7 V EVDD0 5.5 V 50 — — ns
Data hold time (transmission)
Note 2 tHD: DAT 2.7 V EVDD0 5.5 V 0 0.45 — — s
Setup time of stop condition tSU: STO 2.7 V EVDD0 5.5 V 0.26 — — s
Bus-free time tBUF 2.7 V EVDD0 5.5 V 0.5 — — s
tSU: DAT
tHD: STA
Restart
condition
SCLAn
SDAAn
tLOW
tHIGH tSU: STA tHD: STA tSU: STO
Stop
condition
Stop
condition Start
condition
tHD: DAT
tBUF
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2.6 Analog Characteristics
2.6.1 A/D converter characteristics
Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4. Values when the conversion time is set to 57 s (min.) and 95 s (max.).
Note 5. Refer to 2.6.2
Temperature sensor cha rac ter i stics /inter na l refe ren c e vo ltage characte ristic
.
Classification of A/D converter characteristics
Reference Voltage
Input channel Reference voltage (+) = AVREFP
Reference voltage (-) = AVREFM
Reference voltage (+) = VDD
Reference volt age (-) = VSS
Reference voltage (+) = VBGR
Reference voltage (-)= AVREFM
ANI0 to ANI14 Refer to 2.6.1 (1).Refer to 2.6.1 (3). Refer to 2.6.1 (4).
ANI16 to ANI20 Refer to 2.6.1 (2).
Internal reference voltage
Temperature sensor output voltage Refer to 2.6.1 (1).—
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), t arget pin: ANI2 to ANI14, internal reference voltage, and temperature sensor
output voltage
(TA = -40 to +85 C, 1.6 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference volt age (-)
= AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution
AVREFP = VDD Note 3 1.8 V AVREFP 5.5 V 1.2 3.5 LSB
1.6 V AVREFP 5.5 V Note 4 1.2 7.0 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI2 to ANI14 3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
1.8 V VDD 5.5 V 17 3 9 s
1.6 V VDD 5.5 V 57 9 5 s
10-bit resolution
Target pin: Internal reference voltage,
and temperature sensor output vol tage
(HS (high-speed main) mode)
3.6 V VDD 5.5 V 2.375 39 s
2.7 V VDD 5.5 V 3.5625 39 s
2.4 V VDD 5.5 V 17 3 9 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution
AVREFP = VDD Note 3 1.8 V AVREFP 5.5 V 0.25 %FSR
1.6 V AVREFP 5.5 V Note 4 0.50 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution
AVREFP = VDD Note 3 1.8 V AVREFP 5.5 V 0.25 %FSR
1.6 V AVREFP 5.5 V Note 4 0.50 %FSR
Integral linearity error Note 1 ILE 10-bit resolution
AVREFP = VDD Note 3 1.8 V AVREFP 5.5 V 2.5 LSB
1.6 V AVREFP 5.5 V Note 4 5.0 LSB
Differential linear ity error Note 1 DLE 10-bit resolution
AVREFP = VDD Note 3 1.8 V AVREFP 5.5 V 1.5 LSB
1.6 V AVREFP 5.5 V Note 4 2.0 LSB
Analog input voltage V AIN ANI2 to ANI14 0 A V REFP V
Internal reference voltage
(2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Note 5 V
Temperature sensor output voltage
(2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 5 V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3. When EVDD0 AVREFP VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4. When AVREFP < EVDD0 VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
Note 5. When the conversion time is set to 57 s (min.) and 95 s (max.).
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI20
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, 1.6 V AVREFP VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V,
Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 1.8 V AVREFP 5.5 V 1.2 5.0 LSB
1.6 V AVREFP 5.5 V Note 5 1.2 8.5 LSB
Conversion time tCONV 10-bit resolution
Target ANI pin: ANI16 to ANI20 3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
1.8 V VDD 5.5 V 17 3 9 s
1.6 V VDD 5.5 V 57 9 5 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 1.8 V AVREFP 5.5 V 0.35 %FSR
1.6 V AVREFP 5.5 V Note 5 0.60 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 1.8 V AVREFP 5.5 V 0.35 %FSR
1.6 V AVREFP 5.5 V Note 5 0.60 %FSR
Integral linearity error Note 1 ILE 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 1.8 V AVREFP 5.5 V 3.5 LSB
1.6 V AVREFP 5.5 V Note 5 6.0 LSB
Differential linearity error Note 1 DLE 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 1.8 V AVREFP 5.5 V 2.0 LSB
1.6 V AVREFP 5.5 V Note 5 2.5 LSB
Analog input voltage VAIN ANI16 to ANI20 0 AVREFP
and
EVDD0
V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3. When the conversion time is set to 57 s (min.) and 95 s (max.).
Note 4. Refer to 2.6.2
Temperature sensor cha rac ter i stics /inter na l refe ren c e vo ltage characte ristic
.
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference volt age (-) = V SS (ADREFM = 0),
target pin: ANI0 to ANI14, ANI16 to ANI2 0, internal reference voltage, and temperature sensor output
voltage
(TA = -40 to +85 °C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD,
Reference voltage (-) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution 1.8 V VDD 5.5 V 1.2 7.0 LSB
1.6 V VDD 5.5 V Note 3 1.2 10.5 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI0 to ANI14, ANI16 to ANI20 3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
1.8 V VDD 5.5 V 17 39 s
1.6 V VDD 5.5 V 57 95 s
10-bit resolution
Target pin: internal reference voltag e, and
temperature sensor output voltage
(HS (high-speed main) mode)
3.6 V VDD 5.5 V 2.375 39 s
2.7 V VDD 5.5 V 3.5625 39 s
2.4 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution 1.8 V VDD 5.5 V 0.60 %FSR
1.6 V VDD 5.5 V Note 3 0.85 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution 1.8 V VDD 5.5 V 0.60 %FSR
1.6 V VDD 5.5 V Note 3 0.85 %FSR
Integral linearity error Note 1 ILE 10-bit resolution 1.8 V VDD 5.5 V 4.0 LSB
1.6 V VDD 5.5 V Note 3 6.5 LSB
Differential linearity error
Note 1 DLE 10-bit reso lution 1.8 V VDD 5.5 V 2.0 LSB
1.6 V VDD 5.5 V Note 3 2.5 LSB
Analog input voltage VAIN ANI0 to ANI14 0 VDD V
ANI16 to ANI20 0 EVDD0 V
Internal reference vo ltage
(2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Note 4 V
Temperature sensor output voltage
(2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3. Refer to 2.6.2
Temperature sensor cha rac ter i stics /inter na l refe ren c e vo ltage characte ristic
.
Note 4. When reference voltage (-) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (-) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (-) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (-) = AVREFM.
(4)
When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-)
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 to ANI14, ANI16 to ANI20
(TA = -40 to +85 °C, 2.4 V VDD 5.5 V, 1.6 V EVDD = EVDD1 VDD, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage
(+) = VBGR Note 3, Reference voltage (-) = AVREFM = 0 V Note 4, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Conversion time tCONV 8-bit resolution 2.4 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 8-bit resolution 2.4 V VDD 5.5 V 0.60 % FSR
Integral linearity error Note 1 ILE 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB
Differential linearity error Note 1 DLE 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB
Analog input voltage VAIN 0VBGR Note 3 V
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2.6.2
Temperature sensor characteristics/internal reference voltage characteristic
2.6.3 D/A converter characteristics
(TA = -40 to +85 °C, 2. 4 V VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25 C1.05 V
Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that depends on the
temperature -3.6 mV/C
Operation stabilization wait time tAMP 5s
(TA = -40 to +85 C, 1.6 V EVSS0 = EVSS1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8bit
Overall error AINL Rload = 4 M1.8 V VDD 5.5 V 2.5 LSB
Rload = 8 M1.8 V VDD 5.5 V 2.5 LSB
Settling time tSET Cload = 20 pF 2.7 V VDD 5.5 V 3 s
1.6 V VDD < 2.7 V 6 s
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2.6.4 Comparator
Note Not usable in LS (low-speed main) mode, LV (low-voltage main) mode, sub-clock operation, or STOP mode.
2.6.5 POR circuit characteristics
Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
external reset pin before the voltage falls below the operating voltage range shown in 2.4 AC Characteristics.
Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
(TA = -40 to +85 C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage range Ivref 0EV
DD0 - 1.4 V
Ivcmp -0.3 EVDD0 + 0.3 V
Output delay td VDD = 3.0 V
Input slew rate > 50 mV/sComparator hig h-spee d mode,
standard mode 1.2 s
Comparator high-speed mode,
window mode 2.0 s
Comparator low-speed mode,
standard mode 3.0 5.0 s
High-electric-potential
reference volta ge VTW+ Comparator high-speed mode, window mode 0.76 VDD V
Low-electric-potential
reference volta ge VTW- Comparator high-speed mode, window mode 0.24 VDD V
Operation stabilization
wait time tCMP 100 s
Internal reference voltage
Note VBGR 2.4 V VDD 5.5 V, HS (high-speed main) mode 1.38 1.45 1.50 V
(TA = -40 to +85 C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOR Power supply rise time 1.47 1.51 1.55 V
VPDR Power supply fall time Note 1 1.46 1.50 1.54 V
Minimum pulse width Note 2 TPW 300 s
TPW
VPOR
VPDR or 0.7 V
Supply voltage (VDD)
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2.6.6 LVD circuit characteristics
(1) LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = -40 to +85 C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection
voltage Supply voltage level VLVD0 Power supply rise time 3.98 4.06 4.14 V
Power supply fall time 3.90 3.98 4.06 V
VLVD1 Power supply rise time 3.68 3.75 3.82 V
Power supply fall time 3.60 3.67 3.74 V
VLVD2 Power supply rise time 3.07 3.13 3.19 V
Power supply fall time 3.00 3.06 3.12 V
VLVD3 Power supply rise time 2.96 3.02 3.08 V
Power supply fall time 2.90 2.96 3.02 V
VLVD4 Power supply rise time 2.86 2.92 2.97 V
Power supply fall time 2.80 2.86 2.91 V
VLVD5 Power supply rise time 2.76 2.81 2.87 V
Power supply fall time 2.70 2.75 2.81 V
VLVD6 Power supply rise time 2.66 2.71 2.76 V
Power supply fall time 2.60 2.65 2.70 V
VLVD7 Power supply rise time 2.56 2.61 2.66 V
Power supply fall time 2.50 2.55 2.60 V
VLVD8 Power supply rise time 2.45 2.50 2.55 V
Power supply fall time 2.40 2.45 2.50 V
VLVD9 Power supply rise time 2.05 2.09 2.13 V
Power supply fall time 2.00 2.04 2.08 V
VLVD10 Power supply rise time 1.94 1.98 2.02 V
Power supply fall time 1.90 1.94 1.98 V
VLVD11 Power supply rise time 1.84 1.88 1.91 V
Power supply fall time 1.80 1.84 1.87 V
VLVD12 Power supply rise time 1.74 1.77 1.81 V
Power supply fall time 1.70 1.73 1.77 V
VLVD13 Power supply rise time 1.64 1.67 1.70 V
Power supply fall time 1.60 1.63 1.66 V
Minimum pulse width tLW 300 s
Detection delay time 300 s
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2.6.7 Power supply voltage rising slope characteristics
Caution Make sure to keep the intern al reset state by the LVD circuit or an external rese t until V DD reaches the op erating
voltage range shown in 2.4 AC Characteristics.
(2) LVD Detection Voltage of Interrupt & Reset Mode
(TA = -40 to +85 C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Interrupt and
reset mode VLVDA0 VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage 1.60 1.63 1.66 V
VLVDA1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.74 1.77 1.81 V
Falling interrupt voltage 1.70 1.73 1.77 V
VLVDA2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 1.84 1.88 1.91 V
Falling interrupt voltage 1.80 1.84 1.87 V
VLVDA3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 2.86 2.92 2.97 V
Falling interrupt voltage 2.80 2.86 2.91 V
VLVDB0 VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage 1.80 1.84 1.87 V
VLVDB1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 1.94 1.98 2.02 V
Falling interrupt voltage 1.90 1.94 1.98 V
VLVDB2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.05 2.09 2.13 V
Falling interrupt voltage 2.00 2.04 2.08 V
VLVDB3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.07 3.13 3.19 V
Falling interrupt voltage 3.00 3.06 3.12 V
VLVDC0 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage 2.40 2.45 2.50 V
VLVDC1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.56 2.61 2.66 V
Falling interrupt voltage 2.50 2.55 2.60 V
VLVDC2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.66 2.71 2.76 V
Falling interrupt voltage 2.60 2.65 2.70 V
VLVDC3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.68 3.75 3.82 V
Falling interrupt voltage 3.60 3.67 3.74 V
VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.70 2.75 2.81 V
VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.86 2.92 2.97 V
Falling interrupt voltage 2.80 2.86 2.91 V
VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.96 3.02 3.08 V
Falling interrupt voltage 2.90 2.96 3.02 V
VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.98 4.06 4.14 V
Falling interrupt voltage 3.90 3.98 4.06 V
(TA = -40 to +85 C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Power supply voltage rising slope SVDD 54 V/ms
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2.7 Dat a Memory STOP Mode Low Supply Voltage Data Retention Characteristics
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is
effected, but data is not retained when a POR reset is effected.
2.8 Flash Memory Programming Characteristics
Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
Note 2. When using flash memory programmer and Renesas Electronics self-programming library
Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
2.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = -40 to +85 C, VSS = 0V))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply
voltage VDDDR 1.46 Note 5.5 V
(TA = -40 to +85 C, 1.8 V VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
System clock frequency fCLK 1.8 V VDD 5.5 V 1 32 MHz
Number of code flash rewrites
Notes 1, 2, 3 Cerwr Retained for 20 years TA = 85 C1,000 Times
Number of data flash rewrites
Notes 1, 2, 3 Retained for 1 year TA = 25 C 1,000,000
Retained for 5 years TA = 85 C 100,000
Retained for 20 years TA = 85 C 10,000
(TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate During serial programming 115,200 1,000,000 bps
VDD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
Operation mode
VDDDR
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2.10 Timing for Switching Flash Memory Programming Modes
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the external reset ends).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the external resets end.
tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD: How long to keep the TOOL0 pin at the low level from when the external resets end
(excluding the processing time of the firmware to control the flash memory)
(TA = -40 to +85 C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
How long from when an external reset ends until the
initial communication settings are specified tSUINIT POR and LVD reset must end
before the external reset ends. 100 ms
How long from when the TOOL0 pin is placed at the
low level until an external reset ends tSU POR and LVD reset must end
before the external reset ends. 10 s
How long the TOOL0 pin must be kept at the low
level after an external reset ends
(excluding the processing time of the firmware to
control the flash memory)
tHD POR and LVD reset must end
before the external reset ends. 1ms
RESET
TOOL0
<1> <2> <3>
tSU
<4>
tSUINIT
723 µs + tHD
processing
time
00H reception
(TOOLRxD, TOOLTxD m ode)
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3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
This chapter describes the electrical specifi cations for the products “G: Industrial applications (TA = -40 to +105 C)”.
Caution 1. The RL78 microcontrollers have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass production,
because the guaranteed number of rewritable times of the flash memory may be exceeded when this
function is used, and pr oduct reliability therefore cannot be gu aranteed. Rene sas Electronics is not
liable for probl ems occurring when the on-chip debug functi on is used.
Caution 2. With product s not provi ded with an EV DD0, EVDD1, EVSS0, or EV SS1 pin, replace EVDD0 and EVDD1 with
VDD, or replace EVSS0 and EVSS1 with VSS.
Caution 3. The pins mounted depend on the product. Refer to 1.3.1 30-pin products to 1.3.10 100-pin products.
Caution 4. Pleas e contact Renesas Electronics s ales o ffice for deratin g of oper ation under TA = +85 to +105 °C .
Derating is the systematic reduction of load for the sake of improved reliability.
There are following differences between the products “G: Industrial applications (TA = -40 to + 105 C)” and the products
“A: Consumer applications, and D: Industrial applications”.
Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to + 105 °C) are different from those of
the products “A: Consumer applications, and D: Industrial applications”. For details, refer to 3.1 to 3.10.
Parameter A: Consumer applications, D: Industrial applications G: Industrial applications
Operating ambient temperature TA = -40 to +85 CTA = -40 to +105 C
Operating mode
Operating voltage range HS (high-speed main) mode:
2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V VDD 5.5 V@1 MHz to 4 MHz
HS (high-speed main) mode only:
2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
High-speed on-chip oscillator
clock accuracy 1.8 V VDD 5.5 V:
±1.0% @ TA = -20 to +85 C
±1.5% @ TA = -40 to -20 C
1.6 V VDD < 1.8 V:
±5.0% @ TA = -20 to +85 C
±5.5% @ TA = -40 to -20 C
2.4 V VDD 5.5 V:
±2.0% @ TA = +85 to +105 C
±1.0% @ TA = -20 to +85 C
±1.5% @ TA = -40 to -20 C
Serial array unit UART
CSI: fCLK/2 (16 Mbps supported), fCLK/4
Simplified I2C communication
UART
CSI: fCLK/4
Simplified I2C communication
IICA Standard mode
Fast mode
Fast mode plus
Standard mode
Fast mode
Voltage detector • Rising: 1.67 V to 4.06 V (14 stages)
• Falling: 1.63 V to 3.98 V (14 stages) • Rising: 2.61 V to 4.06 V (8 stages)
• Falling: 2.55 V to 3.98 V (8 stages)
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3.1 Absolute Maximum Ratings
Note 1. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value regulates the absolute maximum rating of the
REGC pin. Do not use this pin with voltage applied to it.
Note 2. Must be 6.5 V or lower.
Note 3. Do not exceed AVREF (+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the prod uct must be used under conditions that ensure that th e absolute maximum
ratings are not exceeded.
Remark 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Remark 2. AVREF (+): + side reference voltage of the A/D converter.
Remark 3. VSS: Reference voltage
Absolute Maximum Ratings (1/2)
Parameter Symbols Conditions Ratings Unit
Supply voltage VDD -0.5 to +6.5 V
EVDD0, EVDD1 EVDD0 = EVDD1 -0.5 to +6.5 V
EVSS0, EVSS1 EVSS0 = EVSS1 -0.5 to +0.3 V
REGC pin input voltage VIREGC REGC -0.3 to +2.8
and -0.3 to VDD +0.3 Note 1 V
Input voltage VI1 P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P100 to P102,
P110, P111, P120, P140 to P147
-0.3 to EVDD0 +0.3
and -0.3 to VDD +0.3 Note 2 V
VI2 P60 to P63 (N-ch open-drain) -0.3 to +6.5 V
VI3 P20 to P27, P121 to P124, P137,
P150 to P156, EXCLK, EXCLKS, RESET -0.3 to VDD +0.3 Note 2 V
Output voltage VO1 P00 to P06, P10 to P17, P30, P31,
P40 to P47, P50 to P57, P60 to P67,
P70 to P77, P80 to P87, P100 to P102,
P110, P111, P120, P130, P140 to P147
-0.3 to EVDD0 +0.3
and -0.3 to VDD +0.3 Note 2 V
VO2 P20 to P27, P150 to P156 -0.3 to VDD +0.3 Note 2 V
Analog input voltage VAI1 ANI16 to ANI20 -0.3 to EVDD0 +0.3
and -0.3 to AVREF(+) +0.3 Notes 2, 3 V
VAI2 ANI0 to ANI14 -0.3 to VDD +0.3
and -0.3 to AVREF(+) +0.3 Notes 2, 3 V
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Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter.
That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical
damage, and therefore the prod uct must be used under conditions that ensure that th e absolute maximum
ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
Absolute Maximum Ratings (2/2)
Parameter Symbols Conditions Ratings Unit
Output current, high IOH1 Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120, P130,
P140 to P147
-40 mA
Total of all
pins
-170 mA
P00 to P04, P40 to P47, P102, P120, P130,
P140 to P145 -70 mA
P05, P06, P10 to P17, P30, P31, P50 to P57,
P64 to P67, P70 to P77, P80 to P87, P100, P101,
P110, P111, P146, P147
-100 mA
IOH2 Per pin P20 to P27, P150 to P156 -0.5 mA
Total of all
pins -2 mA
Output current, low IOL1 Per pin P00 to P06, P10 to P17, P30, P31, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P100 to P102, P110, P111, P120, P130,
P140 to P147
40 mA
Total of all
pins
170 mA
P00 to P04, P40 to P47, P102, P120, P130,
P140 to P145 70 mA
P05, P06, P10 to P17, P30, P31, P50 to P57,
P60 to P67, P70 to P77, P80 to P87, P100, P101,
P110, P111, P146, P147
100 mA
IOL2 Per pin P20 to P27, P150 to P156 1 mA
Total of all
pins 5mA
Operating ambient
temperature TAIn normal operation mode -40 to +105 C
In flash memory programming mode
Storage temperature Tstg -65 to +150 C
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3.2 Oscillator Characteristics
3.2.1 X1, XT1 characteristics
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution time.
Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the oscillator
characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock
oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user.
Determine the oscillat ion stabilization time of the OSTC r egister and th e oscillation s tabili zation time s elect
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, refer to 5 .4 System Cloc k Oscillato r in the RL 78/G14 User’s Manual
Hardware.
3.2.2 On-chip oscillator characteristics
Note 1. High-speed on-chip oscillator frequency is selected with bits 0 to 4 of the option byte (000C2H) and bits 0 to 2 of the
HOCODIV register.
Note 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time.
(TA = -40 to +105 °C, 2.4 V VDD 5.5 V, VSS = 0 V)
Resonator Resonator Conditions MIN. TYP. MAX. Unit
X1 clock oscillation frequency (fX) Note Ceramic resonator/
crystal resonator 2.7 V VDD 5.5 V 1.0 20.0 MHz
2.4 V VDD <2.7 V 1.0 16.0
XT1 clock oscillation frequency (fXT) Note Crystal resonator 32 32.768 35 kHz
(TA = -40 to +105 C, 2.4 V VDD 5.5 V, VSS = 0 V)
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator clock frequency
Notes 1, 2 fIH 132MHz
High-speed on-chip oscillator clock frequency
accuracy -20 to +85 C2.4 V VDD 5.5 V -1.0 +1.0 %
-40 to -20 C2.4 V VDD 5.5 V -1.5 +1.5 %
+85 to +105 C2.4 V VDD 5.5 V -2.0 +2.0 %
Low-speed on-chip oscillator clock frequency fIL 15 kHz
Low-speed on-chip oscillator clock frequency
accuracy -15 +15 %
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3.3 DC Characteristics
3.3.1 Pin characteristics
Note 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0, EVDD1, VDD pins to
an output pin.
Note 2. However, do not exceed the total current value.
Note 3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = -10.0 mA
Total output current of pins = (-10.0 × 0.7)/(80 × 0.01) -8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 t o P45, P50 to P55, P71, P74, P80 to P82, and P142 to P144
do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current, high Note 1 IOH1 Per pin for P00 to P06,
P10 to P17, P30, P31,
P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P130, P140 to P147
2.4 V EVDD0 5.5 V -3.0
Note 2 mA
Total of P00 to P04, P40 to P47,
P102, P120, P130, P140 to P145
(When duty 70% Note 3)
4.0 V EVDD0 5.5 V -30.0 mA
2.7 V EVDD0 < 4.0 V -10.0 mA
2.4 V EVDD0 < 2.7 V -5.0 mA
Total of P05, P06, P10 to P17,
P30, P31, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100, P101, P110,
P111, P146, P147
(When duty 70% Note 3)
4.0 V EVDD0 5.5 V -30.0 mA
2.7 V EVDD0 < 4.0 V -19.0 mA
2.4 V EVDD0 < 2.7 V -10.0 mA
Total of all pins
(When duty 70% Note 3)2.4 V EVDD0 5.5 V -60.0 mA
IOH2 Per pin for P20 to P27,
P150 to P156 2.4 V VDD 5.5 V -0.1
Note 2 mA
Total of all pins
(When duty 70% Note 3)2.4 V VDD 5.5 V -1.5 mA
(1/5)
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Note 1. Value of current at which the device operation is guaranteed even if the current flows from an output pin to the EVSS0,
EVSS1, and VSS pins.
Note 2. However, do not exceed the total current value.
Note 3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor 70% the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output current, low Note 1 IOL1 Per pin for P00 to P06,
P10 to P17, P30, P31,
P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P130, P140 to P147
8.5
Note 2 mA
Per pin for P60 to P63 15.0
Note 2 mA
Total of P00 to P04, P40 to P47,
P102, P120, P130, P140 to P145
(When duty 70% Note 3)
4.0 V EVDD0 5.5 V 40.0 mA
2.7 V EVDD0 < 4.0 V 15.0 mA
2.4 V EVDD0 < 2.7 V 9.0 mA
Total of P05, P06, P10 to P17,
P30, P31, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P100, P101, P110,
P111, P146, P147
(When duty 70% Note 3)
4.0 V EVDD0 5.5 V 40.0 mA
2.7 V EVDD0 < 4.0 V 35.0 mA
2.4 V EVDD0 < 2.7 V 20.0 mA
Total of all pins
(When duty 70% Note 3)80.0 mA
IOL2 Per pin for P20 to P27,
P150 to P156 0.4
Note 2 mA
Total of all pins
(When duty 70% Note 3)2.4 V VDD 5.5 V 5.0 mA
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Caution The maximum value of V IH of pins P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71,
P74, P80 to P82, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P1 10,
P111, P120, P140 to P147
Normal input buffer 0.8 EVDD0 EVDD0 V
VIH2 P01, P03, P04, P10, P14 to P17,
P30, P43, P44, P50, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V EVDD0 5.5 V 2.2 EVDD0 V
TTL input buffer
3.3 V EVDD0 < 4.0 V 2.0 EVDD0 V
TTL input buffer
2.4 V EVDD0 < 3.3 V 1.5 EVDD0 V
VIH3 P20 to P27, P150 to P156 0.7 VDD VDD V
VIH4 P60 to P63 0.7 EVDD0 6.0 V
VIH5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0.8 VDD VDD V
Input voltage, low VIL1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P1 10,
P111, P120, P140 to P147
Normal input buffer 0 0.2 EVDD0 V
VIL2 P01, P03, P04, P10, P14 to P17,
P30, P43, P44, P50, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V EVDD0 5.5 V 00.8V
TTL input buffer
3.3 V EVDD0 < 4.0 V 00.5V
TTL input buffer
2.4 V EVDD0 < 3.3 V 00.32V
VIL3 P20 to P27, P150 to P156 0 0.3 VDD V
VIL4 P60 to P63 0 0.3 EVDD0 V
VIL5 P121 to P124, P137, EXCLK, EXCLKS, RESET 0 0.2 VDD V
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Caution P00, P02 to P04, P10, P11, P13 to P15, P17, P30, P43 to P45, P50 to P55, P71, P 74, P80 to P82, P142 to P144 do not
output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Output voltage, high VOH1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P1 10,
P111, P120, P130, P140 to P147
4.0 V EVDD0 5.5 V,
IOH1 = -3.0 mA EVDD0 - 0.7 V
2.7 V EVDD0 5.5 V,
IOH1 = -2.0 mA EVDD0 - 0.6 V
2.4 V EVDD0 5.5 V,
IOH1 = -1.5 mA EVDD0 - 0.5 V
VOH2 P20 to P27, P150 to P156 2.4 V VDD 5.5 V,
IOH2 = -100 AVDD - 0.5 V
Output voltage, low VOL1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P1 10,
P111, P120, P130,
P140 to P147
4.0 V EVDD0 5.5 V,
IOL1 = 8.5 mA 0.7 V
2.7 V EVDD0 5.5 V,
IOL1 = 3.0 mA 0.6 V
2.7 V EVDD0 5.5 V,
IOL1 = 1.5 mA 0.4 V
2.4 V EVDD0 5.5 V,
IOL1 = 0.6 mA 0.4 V
VOL2 P20 to P27, P150 to P156 2.4 V VDD 5.5 V,
IOL2 = 400 A0.4 V
VOL3 P60 to P63 4.0 V EVDD0 5.5 V,
IOL3 = 15.0 mA 2.0 V
4.0 V EVDD0 5.5 V,
IOL3 = 5.0 mA 0.4 V
2.7 V EVDD0 5.5 V,
IOL3 = 3.0 mA 0.4 V
2.4 V EVDD0 5.5 V,
IOL3 = 2.0 mA 0.4 V
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Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high ILIH1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
VI = EVDD0 1A
ILIH2 P20 to P27, P137, P150 to P156,
RESET
VI = VDD 1A
ILIH3 P121 to P124
(X1, X2, EXCLK, XT1, XT2,
EXCLKS)
VI = VDD In input port or
external clock
input
1A
In resonator
connection 10 A
Input leakage
current, low ILIL1 P00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
VI = EVSS0 -1 A
ILIL2 P20 to P27, P137, P150 to P156,
RESET
VI = VSS -1 A
ILIL3 P121 to P124
(X1, X2, EXCLK, XT1, XT2,
EXCLKS)
VI = VSS In input port or
external clock
input
-1 A
In resonator
connection -10 A
On-chip pull-up
resistance RUP00 to P06, P10 to P17, P30,
P31, P40 to P47, P50 to P57,
P64 to P67, P70 to P77,
P80 to P87, P100 to P102, P110,
P111, P120, P140 to P147
VI = EVSS0, In input port 10 20 100 k
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3.3.2 Supply current characteristics
(Notes and Remarks are listed on the next page.)
(1) Flash ROM: 16 to 64 KB of 30- to 64-pin products
(TA = -40 to +1 05 C, 2.4 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V)
Parameter Symbol
Conditions MIN. TYP. MAX. Unit
Supply
current
Note 1
IDD1 Operating
mode HS (high-speed main)
mode Note 5 fHOCO = 64 MHz,
fIH = 32 MHz Note 3 Basic
operation VDD = 5.0 V 2.4 mA
VDD = 3.0 V 2.4
fHOCO = 32 MHz,
fIH = 32 MHz Note 3 Basic
operation VDD = 5.0 V 2.1
VDD = 3.0 V 2.1
HS (high-speed main)
mode Note 5 fHOCO = 64 MHz,
fIH = 32 MHz Note 3 Normal
operation VDD = 5.0 V 5.2 9.3 mA
VDD = 3.0 V 5.2 9.3
fHOCO = 32 MHz,
fIH = 32 MHz Note 3 Normal
operation VDD = 5.0 V 4.8 8.7
VDD = 3.0 V 4.8 8.7
fHOCO = 48 MHz,
fIH = 24 MHz Note 3 Normal
operation VDD = 5.0 V 4.1 7.3
VDD = 3.0 V 4.1 7.3
fHOCO = 24 MHz,
fIH = 24 MHz Note 3 Normal
operation VDD = 5.0 V 3.8 6.7
VDD = 3.0 V 3.8 6.7
fHOCO = 16 MHz,
fIH = 16 MHz Note 3 Normal
operation VDD = 5.0 V 2.8 4.9
VDD = 3.0 V 2.8 4.9
HS (high-speed main)
mode Note 5 fMX = 20 MHz Note 2,
VDD = 5.0 V Normal
operation Square wave input 3.3 5.7 mA
Resonator connection 3.5 5.8
fMX = 20 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 3.3 5.7
Resonator connection 3.5 5.8
fMX = 10 MHz Note 2,
VDD = 5.0 V Normal
operation Square wave input 2.0 3.4
Resonator connection 2.1 3.5
fMX = 10 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 2.0 3.4
Resonator connection 2.1 3.5
Subsystem clock
operation fSUB = 32.768 kHz Note 4
TA = -40 CNormal
operation Square wave input 4.7 6.1 A
Resonator connection 4.7 6.1
fSUB = 32.768 kHz Note 4
TA = +25 CNormal
operation Square wave input 4.7 6.1
Resonator connection 4.7 6.1
fSUB = 32.768 kHz Note 4
TA = +50 CNormal
operation Square wave input 4.8 6.7
Resonator connection 4.8 6.7
fSUB = 32.768 kHz Note 4
TA = +70 CNormal
operation Square wave input 4.8 7.5
Resonator connection 4.8 7.5
fSUB = 32.768 kHz Note 4
TA = +85 CNormal
operation Square wave input 5.4 8.9
Resonator connection 5.4 8.9
fSUB = 32.768 kHz Note 4
TA = +105 CNormal
operation Square wave input 7.2 21.0
Resonator connection 7.3 21.1
(1/2)
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Note 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
Note 2. When high-speed on-chip oscillator and subsystem clock are stopped.
Note 3. When high-speed system clock and subsystem clock are stopped.
Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power
consumption oscillation). However, not including the current flowing into the RTC, 12-bit interval timer, and watchdog
timer.
Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
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(Notes and Remarks are listed on the next page.)
(1) Flash ROM: 16 to 64 KB of 30- to 64-pin products
(TA = -40 to +1 05 C, 2.4 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1 IDD2
Note 2 HALT mode HS (high-speed main)
mode Note 7 fHOCO = 64 MHz,
fIH = 32 MHz Note 4 VDD = 5.0 V 0.80 4.36 mA
VDD = 3.0 V 0.80 4.36
fHOCO = 32 MHz,
fIH = 32 MHz Note 4 VDD = 5.0 V 0.54 3.67
VDD = 3.0 V 0.54 3.67
fHOCO = 48 MHz,
fIH = 24 MHz Note 4 VDD = 5.0 V 0.62 3.42
VDD = 3.0 V 0.62 3.42
fHOCO = 24 MHz,
fIH = 24 MHz Note 4 VDD = 5.0 V 0.44 2.85
VDD = 3.0 V 0.44 2.85
fHOCO = 16 MHz,
fIH = 16 MHz Note 4 VDD = 5.0 V 0.40 2.08
VDD = 3.0 V 0.40 2.08
HS (high-speed main)
mode Note 7 fMX = 20 MHz Note 3,
VDD = 5.0 V Square wave input 0.28 2.45 mA
Resonator connection 0.49 2.57
fMX = 20 MHz Note 3,
VDD = 3.0 V Square wave input 0.28 2.45
Resonator connection 0.49 2.57
fMX = 10 MHz Note 3,
VDD = 5.0 V Square wave input 0.19 1.28
Resonator connection 0.30 1.36
fMX = 10 MHz Note 3,
VDD = 3.0 V Square wave input 0.19 1.28
Resonator connection 0.30 1.36
Subsystem clock
operation fSUB = 32.768 kHz Note 5,
TA = -40 CSquare wave input 0.25 0.57 A
Resonator connection 0.44 0.76
fSUB = 32.768 kHz Note 5,
TA = +25 CSquare wave input 0.30 0.57
Resonator connection 0.49 0.76
fSUB = 32.768 kHz Note 5,
TA = +50 CSquare wave input 0.36 1.17
Resonator connection 0.59 1.36
fSUB = 32.768 kHz Note 5,
TA = +70 CSquare wave input 0.49 1.97
Resonator connection 0.72 2.16
fSUB = 32.768 kHz Note 5,
TA = +85 CSquare wave input 0.97 3.37
Resonator connection 1.16 3.56
fSUB = 32.768 kHz Note 5,
TA = +105 CSquare wave input 3.20 17.10
Resonator connection 3.40 17.50
IDD3
Note 6 STOP mode
Note 8 TA = -40 C0.18 0.51 A
TA = +25 C0.24 0.51
TA = +50 C0.29 1.10
TA = +70 C0.41 1.90
TA = +85 C0.90 3.30
TA = +105 C 3.10 17.00
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
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Note 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is
fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current.
However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors and the current flowing during data flash rewrite.
Note 2. During HALT instruction execution by flash memory.
Note 3. When high-speed on-chip oscillator and subsystem clock are stopped.
Note 4. When high-speed system clock and subsystem clock are stopped.
Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low
current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current
flowing into the 12-bit interval timer and watchdog timer.
Note 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
Note 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C
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(Notes and Remarks are listed on the next page.)
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current
Note 1
IDD1 Operating
mode HS (high-speed main)
mode Note 5 fHOCO = 64 MHz,
fIH = 32 MHz Note 3 Basic
operation VDD = 5.0 V 2.6 mA
VDD = 3.0 V 2.6
fHOCO = 32 MHz,
fIH = 32 MHz Note 3 Basic
operation VDD = 5.0 V 2.3
VDD = 3.0 V 2.3
HS (high-speed main)
mode Note 5 fHOCO = 64 MHz,
fIH = 32 MHz Note 3 Normal
operation VDD = 5.0 V 5.8 10.9 mA
VDD = 3.0 V 5.8 10.9
fHOCO = 32 MHz,
fIH = 32 MHz Note 3 Normal
operation VDD = 5.0 V 5.4 10.3
VDD = 3.0 V 5.4 10.3
fHOCO = 48 MHz,
fIH = 24 MHz Note 3 Normal
operation VDD = 5.0 V 4.5 8.2
VDD = 3.0 V 4.5 8.2
fHOCO = 24 MHz,
fIH = 24 MHz Note 3 Normal
operation VDD = 5.0 V 4.2 7.8
VDD = 3.0 V 4.2 7.8
fHOCO = 16 MHz,
fIH = 16 MHz Note 3 Normal
operation VDD = 5.0 V 3.1 5.6
VDD = 3.0 V 3.1 5.6
HS (high-speed main)
mode Note 5 fMX = 20 MHz Note 2,
VDD = 5.0 V Normal
operation Square wave input 3.7 6.6 mA
Resonator connection 3.9 6.7
fMX = 20 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 3.7 6.6
Resonator connection 3.9 6.7
fMX = 10 MHz Note 2,
VDD = 5.0 V Normal
operation Square wave input 2.2 3.9
Resonator connection 2.3 4.0
fMX = 10 MHz Note 2,
VDD = 3.0 V Normal
operation Square wave input 2.2 3.9
Resonator connection 2.3 4.0
Subsystem clock
operation fSUB = 32.768 kHz Note 4
TA = -40 CNormal
operation Square wave input 5.0 7.1 A
Resonator connection 5.0 7.1
fSUB = 32.768 kHz Note 4
TA = +25 CNormal
operation Square wave input 5.0 7.1
Resonator connection 5.0 7.1
fSUB = 32.768 kHz Note 4
TA = +50 CNormal
operation Square wave input 5.1 8.8
Resonator connection 5.1 8.8
fSUB = 32.768 kHz Note 4
TA = +70 CNormal
operation Square wave inpu t 5.5 10.5
Resonator connection 5.5 10.5
fSUB = 32.768 kHz Note 4
TA = +85 CNormal
operation Square wave inpu t 6.5 14.5
Resonator connection 6.5 14.5
fSUB = 32.768 kHz Note 4
TA = +105 CNormal
operation Square wave input 13.0 58.0
Resonator connection 13.0 58.0
(1/2)
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Note 1. Total current flowing into VDD, EVDD0, and EVDD1, including the inp ut leakage current flowing when the level of the input
pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter,
comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
Note 2. When high-speed on-chip oscillator and subsystem clock are stopped.
Note 3. When high-speed system clock and subsystem clock are stopped.
Note 4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1 (Ultra-low power
consumption oscillation). However, not including the current flowing into the 12-bit interval timer and watchdog timer.
Note 5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25 °C
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
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(Notes and Remarks are listed on the next page.)
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply
current Note 1 IDD2
Note 2 HALT mode HS (high-speed main)
mode Note 7 fHOCO = 64 MHz,
fIH = 32 MHz Note 4 VDD = 5.0 V 0.88 4.86 mA
VDD = 3.0 V 0.88 4.86
fHOCO = 32 MHz,
fIH = 32 MHz Note 4 VDD = 5.0 V 0.62 4.17
VDD = 3.0 V 0.62 4.17
fHOCO = 48 MHz,
fIH = 24 MHz Note 4 VDD = 5.0 V 0.68 3.82
VDD = 3.0 V 0.68 3.82
fHOCO = 24 MHz,
fIH = 24 MHz Note 4 VDD = 5.0 V 0.50 3.25
VDD = 3.0 V 0.50 3.25
fHOCO = 16 MHz,
fIH = 16 MHz Note 4 VDD = 5.0 V 0.44 2.28
VDD = 3.0 V 0.44 2.28
HS (high-speed main)
mode Note 7 fMX = 20 MHz Note 3,
VDD = 5.0 V Square wave in pu t 0.37 2.65 mA
Resonator connection 0.50 2.77
fMX = 20 MHz Note 3,
VDD = 3.0 V Square wave in pu t 0.37 2.65
Resonator connection 0.50 2.77
fMX = 10 MHz Note 3,
VDD = 5.0 V Square wave in pu t 0.21 1.36
Resonator connection 0.30 1.46
fMX = 10 MHz Note 3,
VDD = 3.0 V Square wave in pu t 0.21 1.36
Resonator connection 0.30 1.46
Subsystem clock
operation fSUB = 32.768 kHz Note 5,
TA = -40 CSquare wa ve input 0.28 0.66 A
Resonator connection 0.47 0.85
fSUB = 32.768 kHz Note 5,
TA = +25 CSquare w a ve in pu t 0.34 0.66
Resonator connection 0.53 0.85
fSUB = 32.768 kHz Note 5,
TA = +50 CSquare w a ve in pu t 0.37 2.35
Resonator connection 0.56 2.54
fSUB = 32.768 kHz Note 5,
TA = +70 CSquare w a ve in pu t 0.61 4.08
Resonator connection 0.80 4.27
fSUB = 32.768 kHz Note 5,
TA = +85 CSquare w a ve in pu t 1.55 8.09
Resonator connection 1.74 8.28
fSUB = 32.768 kHz Note 5,
TA = +105 CSquare wave input 6.00 51.00
Resonator connection 6.00 51.00
IDD3
Note 6 STOP mode
Note 8 TA = -40 C0.19 0.57 A
TA = +25 C0.25 0.57
TA = +50 C0.33 2.26
TA = +70 C0.52 3.99
TA = +85 C1.46 8.00
TA = +105 C5.50 50.00
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 128 of 187
Oct 25, 2013
Note 1. Total current flowing into VDD, EVDD0, and EVDD1, including the inp ut leakage current flowing when the level of the input
pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the MAX. column include the
peripheral operation current. However, not including the current flowing into the A/D converter, D/A converter,
comparator, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
Note 2. During HALT instruction execution by flash memory.
Note 3. When high-speed on-chip oscillator and subsystem clock are stopped.
Note 4. When high-speed system clock and subsystem clock are stopped.
Note 5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and setting ultra-low
current consumption (AMPHS1 = 1). The current flowing into the RTC is included. However, not including the current
flowing into the 12-bit interval timer and watchdog timer.
Note 6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
Note 7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
Note 8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remark 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency)
Remark 2. fHOCO: High-speed on-chip oscillator clock frequency (64 MHz max.)
Remark 3. fIH: High-speed on-chip oscillator clock frequency (32 MHz max.)
Remark 4. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 5. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA = 25 °C
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Note 1. Current flowing to VDD.
Note 2. When high speed on-chip oscillator and high-speed system clock are stopped.
Note 3. Current flowing only to the real-time clock (RTC) (excluding th e oper ating curr ent of the low-speed on -chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and
IRTC, when the real-time clock operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added. IDD2 subsystem clock operation includes the operational current of the real-time clock.
Note 4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip oscillator and
the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IIT,
when the 12-bit interval timer operates in operation mode or HALT mode. When the low-speed on-chip oscillator is
selected, IFIL should be added.
(3) Peripheral Functions (Common to all products)
(TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-speed on-chip
oscillator operating current IFIL Note 1 0.20 A
RTC operating current IRTC Notes 1, 2, 3 0.02 A
12-bit interval timer
operating current IIT Notes 1, 2, 4 0.02 A
Watchdog timer operating
current IWDT Notes 1, 2, 5 fIL = 15 kHz 0.22 A
A/D converter operating
current IADC Notes 1, 6 When conv ersion at max i m um
speed Normal mode,
AVREFP = VDD = 5.0 V 1.3 1.7 mA
Low voltage mode,
AVREFP = VDD = 3.0 V 0.5 0.7 mA
A/D converter reference
voltage current IADREF Note 1 75.0 A
Temperature sensor
operating current ITMPS Note 1 75.0 A
D/A converter operating
current IDAC Notes 1, 11, 13 Per D/A converter channel 1.5 mA
Comparator operati ng
current ICMP Notes 1, 12, 13 VDD = 5.0 V,
Regulator output voltage = 2.1 V Window mode 12.5 A
Comparator high-speed mode 6.5 A
Comparator low-speed mode 1.7 A
VDD = 5.0 V,
Regulator output voltage = 1.8 V Window mode 8.0 A
Comparator high-speed mode 4.0 A
Comparator low-speed mode 1.3 A
LVD operating current ILVD Notes 1, 7 0.08 A
Self-programming operating
current IFSP Notes 1, 9 2.50 12.20 mA
BGO operating current IBGO Notes 1, 8 2.50 12.20 mA
SNOOZE operating current ISNOZ Note 1 ADC operation The mode is performed Note 10 0.50 1.10 mA
The A/D conversion
operations are performed,
Low voltage mode,
AVREFP = VDD = 3.0 V
1.20 2.04
CSI/UART operation 0.70 1.54
DTC operation 3.10
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Note 5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip oscillator).
The supply current of the RL78 microcontrollers is the sum of IDD1, I DD2 or IDD3 and IWDT when the watchdog timer is in
operation.
Note 6. Current flowing only to the A/D converter. The supply cur rent of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IADC when the A/D converter operates in an operation mode or the HALT mode.
Note 7. Current flowing only to the L VD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and
ILVD when the LVD circuit is in operation.
Note 8. Current flowing during programming of the data flash.
Note 9. Current flowing during self-programming.
Note 10. For shift time to the SNOOZE mode, see 23.3.3 SNOOZE mode in the RL78/G14 User’s Manual Hardware.
Note 11. Current flowing only to the D/A converter. The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and
IDAC when the D/A converter operates in an operation mode or the HALT mode.
Note 12. Current flowing only to the comparator circuit. The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2, or
IDD3 and ICMP when the comparator circuit is in operation.
Note 13. A comparator and D/A converter are provided in products with 96 KB or more code flash memory.
Remark 1. fIL: Low-speed on-chip oscillator clock frequency
Remark 2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
Remark 3. fCLK: CPU/peripheral hardware clock frequency
Remark 4. Temperature condition of the TYP. value is TA = 25 C
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3.4 AC Characteristics
Note The following conditions are required for low voltage interface when EVDD0 < VDD
2.4 V EVDD0 < 2.7 V: MIN. 125 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of timer mode registe r mn ( TMRmn). m: Un it nu mber (m = 0, 1), n: Chann el
number (n = 0 to 3))
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items Symbol Conditions MIN. TYP. MAX. Unit
Instruction cycle
(minimum instruction
execution time)
TCY Main system
clock (fMAIN)
operation
HS (high-speed main)
mode 2.7 V VDD 5.5 V 0.03125 1 s
2.4 V VDD < 2.7 V 0.0625 1 s
Subsystem clock (fSUB) operation 2.4 V VDD 5.5 V 28.5 30.5 31.3 s
In the self-
programming
mode
HS (high-speed main)
mode 2.7 V VDD 5.5 V 0.03125 1 s
2.4 V VDD < 2.7 V 0.0625 1 s
External system cl ock
frequency fEX 2.7 V VDD 5.5 V 1.0 20.0 MHz
2.4 V VDD 2.7 V 1.0 16.0 MHz
fEXS 32 35 kHz
External system cl ock
input high-level width,
low-level width
tEXH,
tEXL
2.7 V VDD 5.5 V 24 ns
2.4 V VDD 2.7 V 30 ns
tEXHS,
tEXLS 13.7 s
TI00 to TI03, TI10 to
TI13 input high-level
width, low-level width
tTIH, tTIL 1/fMCK + 10
Note ns
Timer RJ input cycle fCTRJIO 2.7 V EVDD0 5.5 V 100 ns
2.4 V EVDD0 < 2.7 V 300 ns
Timer RJ input high-
level width, low-level
width
tTJIH,
tTJIL
TRJIO 2.7 V EVDD0 5.5 V 40 ns
2.4 V EVDD0 < 2.7 V 120 ns
(1/2)
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(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Items Symbol Conditions MIN. TYP. MAX. Unit
Timer RD input high-level
width, low-level width tTDIH,
tTDIL
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 3/fCLK ns
T imer RD forced cutof f signal
input low-level width tTDSIL P130/INTP0 2MHz < fCLK 32 MHz 1 s
fCLK 2 MHz 1/fCLK + 1
Timer RG input high-level
width, low-level width tTGIH,
tTGIL
TRGIOA, TRGIOB 2.5/fCLK ns
TO00 to TO03,
TO10 to TO13,
TRJIO0, TRJO0,
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRGIOA, TRGIOB
output frequency
fTO HS (high-speed main) mode 4.0 V EVDD0 5.5 V 16 MHz
2.7 V EVDD0 < 4.0 V 8 MHz
2.4 V EVDD0 < 2.7 V 4 MHz
PCLBUZ0, PCLBUZ1 output
frequency fPCL HS (high-speed main) mode 4.0 V EVDD0 5.5 V 16 MHz
2.7 V EVDD0 < 4.0 V 8 MHz
2.4 V EVDD0 < 2.7 V 4 MHz
Interrupt input high-level
width, low-level width tINTH,
tINTL
INTP0 2.4 V VDD 5.5 V 1 s
INTP1 to INTP11 2.4 V EVDD0 5.5 V 1 s
Key interrupt input low-level
width tKR KR0 to KR7 2.4 V EVDD0 5.5 V 250 ns
RESET low-level width tRSL 10 s
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Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode )
1.0
0.1
0
10
1.0 2.0 3.0 4.0 5.0 6.0
5.5
2.7
0.01
2.4
0.03125
0.0625
0.05
Cycle time TCY [µs]
Supply voltage V DD [V]
During self-programming
When high-speed system clock is selected
When the high-speed on-chip oscillator clock is selected
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Oct 25, 2013
AC Timing Test Points
External System Clock Timing
TI/TO T iming
VIH/VOH
VIL/VOL
VIH/VOH
Test points VIL/VOL
EXCLK/EXCLKS
1/fEX
1/fEXS
tEXL
tEXLS tEXH
tEXHS
tTIL tTIH
1/fTO
TI00 to TI03, TI10 to TI13
TO00 to TO03, TO10 to TO13,
TRJIO0, TRJO0,
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1,
TRGIOA , TRGIOB
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tTJIL
TRJIO
tTJIH
tTDIL
TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1
tTDIH
tTDSIL
INTP0
tTGIL
TRGIOA , TR GIOB
tTGIH
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Interrupt Request Input Timing
Key Interrupt Input Timing
RESET Input Timing
INTP0 to INTP11
tINTL tINTH
tKR
KR0 to KR7
tRSL
RESET
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3.5 Peripheral Functions Characteristics
AC Timing Test Points
3.5.1 Serial array unit
Note 1. Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2. The following conditions are required for low voltage interface when EVDD0 VDD.
2.4 V EVDD0 2.7 V: MAX. 1.3 Mbps
Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input
mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
UART mode bit width (during communication at same potential) (reference)
Remark 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(1) During communication at same potential (UART mode)
(TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) Mode Unit
MIN. MAX.
Transfer rate Note 1 2.4 V EVDD0 5.5 V fMCK/12 Note 2 bps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3 2.6 Mbps
VIH/VOH
VIL/VOL
VIH/VOH
Test points VIL/VOL
RL78 microcontroller
TxDq
RxDq
User’s device
Rx
Tx
Baud rate error tolerance
TxDq
RxDq
High-/Low-bit width
1/Transfer rate
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(2) D uring communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main)
mode Unit
MIN. MAX.
SCKp cycle time tKCY1 tKCY1 4/fCLK 2.7 V EVDD0 5.5 V 250 ns
2.4 V EVDD0 5.5 V 500 ns
SCKp high-/low-level width tKH1, tKL1 4.0 V EVDD0 5.5 V tKCY1/2 - 24 ns
2.7 V EVDD0 5.5 V tKCY1/2 - 36 ns
2.4 V EVDD0 5.5 V tKCY1/2 - 76 ns
SIp setup time (to SCKp↑) Note 1 tSIK1 4.0 V EVDD0 5.5 V 66 ns
2.7 V EVDD0 5.5 V 66 ns
2.4 V EVDD0 5.5 V 113 ns
SIp hold time (from SCKp↑) Note 2 tKSI1 38 ns
Delay time from SCKp↓ to SOp output Note 3 tKSO1 C = 30 pF Note 4 50 ns
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Note 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. C is the load capacitance of the SOp output lines.
Note 5. The maximum transfer rate when using the SNOOZE mode is 1 Mbps.
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 3 to 5, 14)
Remark 2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(3) D uring communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCKp cycle time Note 5 tKCY2 4.0 V EVDD0 5.5 V 20 MHz fMCK 16/fMCK ns
fMCK 20 MHz 12/fMCK ns
2.7 V EVDD0 5.5 V 16 MHz fMCK 16/fMCK ns
fMCK 16 MHz 12/fMCK ns
2.4 V EVDD0 5.5 V 12/fMCK and 1000 ns
SCKp high-/low-level width tKH2, tKL2 4.0 V EVDD0 5.5 V tKCY2/2 - 14 ns
2.7 V EVDD0 5.5 V tKCY2/2 - 16 ns
2.4 V EVDD0 5.5 V tKCY2/2 - 36 ns
SIp setup time (to SCKp↑) Note 1 tSIK2 2.7 V EVDD0 5.5 V 1/fMCK + 40 ns
2.4 V EVDD0 5.5 V 1/fMCK + 60 ns
SIp hold time (from SCKp↑) Note 2 tKSI2 1/fMCK + 62 ns
Delay time from SCKp↓ to SOp output Note 3 tKSO2 C = 30 pF Note 4 2.7 V EVDD0 5.5 V 2/fMCK + 66 ns
2.4 V EVDD0 5.5 V 2/fMCK + 113 ns
(1/2)
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Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using
port input mode register g (PIMg) and port output mode register g (POMg).
Remark p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0), g: PIM number (g = 3, 5)
CSI mode connection diagram (during communication at same potential)
CSI mode connection diagram (during communication at same potential)
(Slave Transmission of slave select input function (CSI00))
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
(3) D uring communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SSI00 setup time tSSIK DAPmn = 0 2.7 V EVDD0 5.5 V 240 ns
2.4 V EVDD0 5.5 V 400 ns
DAPmn = 1 2.7 V EVDD0 5.5 V 1/fMCK + 240 ns
2.4 V EVDD0 5.5 V 1/fMCK + 400 ns
SSI00 hold time tKSSI DAPmn = 0 2.7 V EVDD0 5.5 V 1/fMCK + 240 ns
2.4 V EVDD0 5.5 V 1/fMCK + 400 ns
DAPmn = 1 2.7 V EVDD0 5.5 V 240 ns
2.4 V EVDD0 5.5 V 400 ns
SCKp
SOp
User's device
SCK
SI
SIp SO
RL78 microcontroller
SCK00
SO00 User's device
SCK
SI
SI00 SO
SSI00 SSO
RL78 microcont roller
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Oct 25, 2013
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
Remark 2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
SIp
SOp
tKCY1, 2
Input data
Output data
SCKp
tKL1, 2 tKH1, 2
SSI00
(CSI00 only)
tSIK1, 2 tKSI1, 2
tKSO1, 2
tSSIK tKSSI
Input data
Output data
tKCY1, 2
tKH1, 2
tSIK1, 2 tKSI1, 2
tKSO1, 2
tSSIK tKSSI
SIp
SOp
SCKp
SSI00
(CSI00 only)
tKL1, 2
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Note 1. The value must also be equal to or less than fMCK/4.
Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD
tolerance (When 64- to 100-pin products)) mode for the SDAr pin and the normal output mode for the SCLr pin by
using port input mode register g (PIMg) and port output mode register h (POMh).
(Remarks are listed on the next page.)
(4) During communication at same potential (simplified I2C mode)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCLr clock frequency fSCL 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1 kHz
2.4 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
100 Note 1 kHz
Hold time when SCLr = “L” tLOW 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1200 ns
2.4V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
4600 ns
Hold time when SCLr = “H” tHIGH 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1200 ns
2.4 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
4600 ns
Data setup time (reception) tSU: DAT 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 220 Note 2 ns
2.4V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
1/fMCK + 580 Note 2 ns
Data hold time (transmission) tHD: DAT 2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
0 770 ns
2.4 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
0 1420 ns
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Simplified I2C mode connection diagram (during communication at same potential)
Simplified I2C mode serial transfer timing (during co mmunication at same potential)
Remark 1. Rb[]: Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 3 to 5, 14),
h: POM number (h = 0, 1, 3 to 5, 7, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
RL78 microcont roller
SDAr
SCLr
User’s device
SDA
SCL
VDD
Rb
SDAr
SCLr
1/fSCL
tLOW tHIGH
tSU: DATtHD: DAT
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Note 1. Transfer rate in the SNOOZE mode is 4800 bps only.
However, the SNOOZE mode cannot be used when FRQSEL4 = 1.
Note 2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V EVDD0 2.7 V: MAX. 1.3 Mbps
Note 3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode: 32 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
Caution Select the TTL in put buffer for the RxDq pin and the N-ch op en drain output (VDD tolerance (When 30- to 52-p in
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
Remark 1. Vb [V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 ( PIOR0) is
1.
(5) Communicatio n at di fferent potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
T ransfer rate reception 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V fMCK/12 Note 1 bps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3 2.6 Mbps
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V fMCK/12 Note 1 bps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3 2.6 Mbps
2.4 V EVDD0 3.3 V,
1.6 V Vb 2.0 V fMCK/12 Notes 1, 2 bps
Theoretical value of the maximum transfer rate
fMCK = fCLK Note 3 2.6 Mbps
(1/2)
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Oct 25, 2013
Note 1.
The smaller maximum transfer rate derived by using f
MCK
/12 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V and 2.7 V Vb 4.0 V
Note 2. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
Note 3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V and 2.3 V Vb 2.7 V
Note 4. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
(5) Communicatio n at di fferent potential (1.8 V, 2.5 V, 3 V) (UART mode)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
T ransfer rate transmission 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V Note 1 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 1.4 k,
Vb = 2.7 V
2.6 Note 2 Mbps
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V Note 3 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 2.7 k,
Vb = 2.3 V
1.2 Note 4 Mbps
2.4 V EVDD0 3.3 V,
1.6 V Vb 2.0 V Note 5 bps
Theoretical value of the maximum transfer rate
Cb = 50 pF, Rb = 5.5 k,
Vb = 1.6 V
0.43 Note 6 Mbps
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
2.2
Vb
{-Cb Rb In (1 - )}
2.2
Vb
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
2.0
Vb
{-Cb Rb In (1 - )}
2.0
Vb
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
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Oct 25, 2013
Note 5. The smaller maximum transfer rate derived by using fMCK/12 or the f ollowing expression is the valid maximum transfer
rate.
Expression for calculating the transfer rate when 2.4 V EVDD0 < 3.3 V and 1.6 V Vb 2.0 V
Note 6. This value as an example is calculated when the conditions described in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL in put buffer for the RxDq pin and the N-ch op en drain output (VDD tolerance (When 30- to 52-p in
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the TxDq pin by using port input mode
register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL
input buffer selected.
(Remarks are listed on the next page.)
Maximum transfer rate =
1
[bps]
Baud rate error (theoretical value) =
1
Transfer rate 2 -
{-Cb Rb In (1 - )} 3
1.5
Vb
{-Cb Rb In (1 - )}
1.5
Vb
( ) Number of transferred bits
1
Transfer rate
100 [%]
* This value is the theoretical value of the relative difference between the transmission and reception sides.
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Oct 25, 2013
UART mode connection diagra m (du r ing commu nic a tio n at different potential)
UART mode bit width (during communication at different potential) (reference)
Remark 1. Rb[]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
Remark 2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
Remark 4. UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 ( PIOR0) is
1.
RL78 microcont roller
TxDq
RxDq
User’s device
Rx
Tx
Vb
Rb
Baud rate error tolerance
High-/Low -bit width
1/Transfer rate
Baud rate error tolerance
High-bit width
Low-bit width
1/Transfer rate
TxDq
RxDq
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Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCKp cycle time tKCY1 tKCY1 4/fCLK 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
600 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1000 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
2300 ns
SCKp high-level width tKH1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 150 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 340 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 916 ns
SCKp low-level width tKL1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
tKCY1/2 - 24 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
tKCY1/2 - 36 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
tKCY1/2 - 100 ns
(1/3)
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Note When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/3)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SIp setup time (to SCKp↑) Note tSIK1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
162 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
354 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
958 ns
SIp hold time (from SCKp↑) Note tKSI1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
38 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
38 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
38 ns
Delay time from SCKp↓ to SOp output Note tKSO1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
200 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
390 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
966 ns
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Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When 30- to 52-pin
products)/EVDD tolerance (When 64- to 100-pin products)) mode for the SOp pin and SCKp pin by using port
input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics
with TTL input buffer selected.
(Remarks are listed on the next page.)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/3)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SIp setup time (to SCKp↓) Note tSIK1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
88 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
88 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
220 ns
SIp hold time (from SCKp↓) Note tKSI1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
38 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
38 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
38 ns
Delay time from SCKp↑ to SOp output Note tKSO1 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
50 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
50 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
50 ns
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CSI mode connection diagram (during communication at d ifferent potential
Remark 5. Rb[]: Communication lin e (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 6. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 7. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
Remark 8. CSI01 of 48- , 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other C SI for
communication at different potential.
SCKp
SOp
User’s device
SCK
SI
SIp SO
Vb
Rb
<Master> Vb
Rb
RL78 microcontroller
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CSI mode serial transfer timing (master mode) (during communicatio n at di ffe re nt potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (master mode) (during communicatio n at di ffe re nt potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 2. CSI01 of 48- , 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other C SI for
communication at different potential.
Input data
SIp
SOp
tKCY1
tKL1 tKH1
tSIK1 tKSI1
tKSO1
Output data
SCKp
Input data
Output data
SIp
SOp
SCKp
tKCY1
tKH1 tKL1
tSIK1 tKSI1
tKSO1
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(Notes, Cautions, and Remarks are listed on the next page.)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCKp cycle time Note 1 tKCY2 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V 24 MHz fMCK 28/fMCK ns
20 MHz fMCK 24 MHz 24/fMCK ns
8 MHz fMCK 20 MHz 20/fMCK ns
4 MHz fMCK 8 MHz 16/fMCK ns
fMCK 4 MHz 12/fMCK ns
2.7 V EVDD0 4.0 V,
2.3 V Vb 2.7 V 24 MHz fMCK 40/fMCK ns
20 MHz fMCK 24 MHz 32/fMCK ns
16 MHz fMCK 20 MHz 28/fMCK ns
8 MHz fMCK 16 MHz 24/fMCK ns
4 MHz fMCK 8 MHz 16/fMCK ns
fMCK 4 MHz 12/fMCK ns
2.4 V EVDD0 3.3 V,
1.6 V Vb 2.0 V 24 MHz fMCK 96/fMCK ns
20 MHz fMCK 24 MHz 72/fMCK ns
16 MHz fMCK 20 MHz 64/fMCK ns
8 MHz fMCK 16 MHz 52/fMCK ns
4 MHz fMCK 8 MHz 32/fMCK ns
fMCK 4 MHz 20/fMCK ns
SCKp high-/low-level
width tKH2, t KL2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V tKCY2/2 - 24 ns
2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 - 36 ns
2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V tKCY2/2 - 100 ns
SIp setup time
(to SCKp↑) Note 2 tSIK2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V 1/fMCK + 40 ns
2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V 1/fMCK + 40 ns
2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V 1/fMCK + 60 ns
SIp hold time
(from SC Kp↑) Note 3 tKSI2 1/fMCK + 62 ns
Delay time from SCKp
to SOp output Note 4 tKSO2 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2/fMCK + 240 ns
2.7 V EVDD0 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2/fMCK + 428 ns
2.4 V EVDD0 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rv = 5.5 k
2/fMCK + 1146 ns
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Note 1. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Note 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from SCKp↓” when
DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Note 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes “from
SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input b uffer for the SIp pin and SCKp pin, and the N- ch open drain output (VDD tolerance (Wh en
30- to 52-pin prod ucts)/EVDD tolerance (when 64- to 100-pin prod ucts)) mode for the SOp p in b y using p ort inpu t
mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC characteristics with
TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
Remark 1. Rb[]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance,
Vb[V]: Communication line voltage
Remark 2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13))
Remark 4. CSI01 of 48- , 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other C SI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
SCKp
SOp
User’s device
SCK
SI
SIp SO
Vb
Rb
<Slave>
RL78 microcontroller
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CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Remark 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
g: PIM and POM number (g = 0, 1, 3 to 5, 14)
Remark 2. CSI01 of 48- , 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential. Use other C SI for
communication at different potential.
Also, communication at different potential cannot be performed during clock synchronous serial communication with the
slave select function.
SIp
SOp
SCKp
Input data
Output data
tKCY2
tKH2tKL2
tSIK2 tKSI2
tKSO2
Input data
Output data
SIp
SOp
SCKp
tKCY2
tKL2tKH2
tSIK2 tKSI2
tKSO2
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(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
SCLr clock frequency fSCL 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1 kHz
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
400 Note 1 kHz
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
100 Note 1 kHz
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
100 Note 1 kHz
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
100 Note 1 kHz
Hold time when SCLr = “L” tLOW 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1200 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1200 ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
4600 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
4600 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
4650 ns
Hold time when SCLr = “H” tHIGH 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
620 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
500 ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
2700 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
2400 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
1830 ns
(1/2)
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Note 1. The value must also be equal to or less than fMCK/4.
Note 2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (When 30- to 52-pin products)/EVDD
tolerance (When 64- to 100 -pin products)) mode for the SDAr pin and the N-ch ope n drain output ( VDD tolerance
(When 30- to 52-pin produc ts)/EVDD tolerance (When 64- to 100-pin products)) mode for the SCLr pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the DC
characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5. 5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol Conditions HS (high-speed main) mode Unit
MIN. MAX.
Data setup time (reception) tSU:DAT 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 340 Note 2 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 340 Note 2 ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1/fMCK + 760 Note 2 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1/fMCK + 760 Note 2 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
1/fMCK + 570 Note 2 ns
Data hold time (transmission) tHD:DAT 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
0 770 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
0 770 ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
0 1420 ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
0 1420 ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
0 1215 ns
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Simplified I2C mode connection diagram (dur ing communic a tion at different potential)
Simplified I2C mode serial transfer timing (during communication at different potential)
Remark 1. Rb[]: Communication line ( SDAr, SCLr ) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load capacitance,
Vb[V]: Communication line voltage
Remark 2. r: IIC number (r = 00, 01, 10, 11, 20, 30, 31), g: PIM, POM number (g = 0, 1, 3 to 5, 14)
Remark 3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1),
n: Channel number (n = 0, 2), mn = 00, 01, 02, 10, 12, 13)
RL78 microcont roller
SDAr
SCLr
User’s device
SDA
SCL
Vb
Rb
Vb
Rb
SDAr
SCLr
1/fSCL
tLOW tHIGH
tSU: DATtHD: DAT
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3.5.2 Serial interface IICA
Note 1. The first clock pulse is generated after this period when the start/restart condition is detected.
Note 2. The maximum value (MAX.) of tHD: DAT is during normal transfer and a wait state is in serted in the ACK (acknowledge)
timing.
Caution The values in the above table are applied even when bit 2 (PIOR02) in the peripheral I/O redirection register 0
(PIOR0) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in the redirect
destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up resistor) at
that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
Fast mode: Cb = 320 pF, Rb = 1.1 k
IICA serial transfer timing
Remark n = 0, 1
(TA = -40 to +1 05 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions HS (high-speed main) mode Unit
Standard mode Fast mode
MIN. MAX. MIN. MAX.
SCLA0 clock frequency fSCL Fast mode: fCLK 3.5 MHz — — 0 400 kHz
Standard mode: fCLK 1 MHz 0 100 — — kHz
Setup time of restart condition tSU: STA 4.7 0.6 s
Hold time Note 1 tHD: STA 4.0 0.6 s
Hold time when SCLA0 = “L” tLOW 4.7 1.3 s
Hold time when SCLA0 = “H” tHIGH 4.0 0.6 s
Data setup time (reception) tSU: DAT 250 100 ns
Data hold time (transmission) Note 2 tHD: DAT 03.45 0 0.9s
Setup time of stop condition tSU: STO 4.0 0.6 s
Bus-free time tBUF 4.7 1.3 s
tSU: DAT
tHD: STA
Restart
condition
SCLAn
SDAAn
tLOW
tHIGH tSU: STA tHD: STA tSU: STO
Stop
condition
Stop
condition Start
condition
tHD: DAT
tBUF
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3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4. Refer to 3.6.2
Temperature sensor cha rac ter i stics /inter na l refe ren c e vo ltage characte ristic
.
Classification of A/D converter characteristics
Reference Voltage
Input channel Reference voltage (+) = AVREFP
Reference voltage (-) = AVREFM
Reference voltage (+) = VDD
Reference voltage (-) = VSS
Reference voltage (+) = VBGR
Reference voltage (-)= AVREFM
ANI0 to ANI1 4 Refer to 3.6.1 (1).Refer to 3.6.1 (3). Refer to 3.6.1 (4).
ANI16 to ANI20 Refer to 3.6.1 (2).
Internal reference voltage
Temperature sensor output voltage Refer to 3.6.1 (1).—
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), t arget pin: ANI2 to ANI14, internal reference voltage, and temperature sensor
output voltage
(TA = -40 to +105 C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP,
Reference voltage (-) = AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution
AVREFP = VDD Note 3 2.4 V AVREFP 5.5 V 1.2 3.5 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI2 to ANI14 3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
2.4 V VDD 5.5 V 17 39 s
10-bit resolution
Target pin: Internal reference voltage,
and temperature sensor output
voltage (HS (high-speed main) mode)
3.6 V VDD 5.5 V 2.375 39 s
2.7 V VDD 5.5 V 3.5625 39 s
2.4 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution
AVREFP = VDD Note 3 2.4 V AVREFP 5.5 V 0.25 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution
AVREFP = VDD Note 3 2.4 V AVREFP 5.5 V 0.25 %FSR
Integral linearity error Note 1 ILE 10-bit resolution
AVREFP = VDD Note 3 2.4 V AVREFP 5.5 V 2.5 LSB
Differential linearity error Note 1 DLE 10-bit resolution
AVREFP = VDD Note 3 2.4 V AVREFP 5.5 V 1.5 LSB
Analog input voltage VAIN ANI2 to ANI14 0 AVREFP V
Internal reference vo ltage output
(2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Note 4 V
Temperature sensor output voltage
(2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 4 V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (%FSR) to the full-scale value.
Note 3. When EVDD0 AVREFP VDD, the MAX. values are as follows.
Overall error: Add ±1.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.05%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±0.5 LSB to the MAX. value when AVREFP = VDD.
Note 4. When AVREFP < EVDD0 VDD, the MAX. values are as follows.
Overall error: Add ±4.0 LSB to the MAX. value when AVREFP = VDD.
Zero-scale error/Full-scale error: Add ±0.20%FSR to the MAX. value when AVREFP = VDD.
Integral linearity error/ Differential linearity error: Add ±2.0 LSB to the MAX. value when AVREFP = VDD.
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (-) =
AVREFM/ANI1 (ADREFM = 1), target pin: ANI16 to ANI20
(TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, 2.4 V AVREFP VDD 5.5 V,
VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 2.4 V AVREFP 5.5 V 1.2 5.0 LSB
Conversion time tCONV 10-bit resolution
Target ANI pin: ANI16 to ANI20 3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
2.4 V VDD 5.5 V 17 3 9 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 2.4 V AVREFP 5.5 V 0.35 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 2.4 V AVREFP 5.5 V 0.35 %FSR
Integral linearity error Note 1 ILE 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 2.4 V AVREFP 5.5 V 3.5 LSB
Differential linearity error Note 1 DLE 10-bit resolution
EVDD0 AVREFP = VDD Notes 3, 4 2.4 V AVREFP 5.5 V 2.0 LSB
Analog input voltage VAIN ANI16 to ANI20 0 AVREFP
and
EVDD0
V
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Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3. Refer to 3.6.2
Temperature sensor cha rac ter i stics /inter na l refe ren c e vo ltage characte ristic
.
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference volt age (-) = V SS (ADREFM = 0),
target pin: ANI0 to ANI14, ANI16 to ANI2 0, internal reference voltage, and temperature sensor output
voltage
(TA = -40 to +105 °C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference vo lt age (+ ) = VDD,
Reference voltage (-) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 810bit
Overall error Note 1 AINL 10-bit resolution 2.4 V VDD 5.5 V 1.2 7.0 LSB
Conversion time tCONV 10-bit resolution
Target pin: ANI0 to ANI14, ANI16 to ANI20 3.6 V VDD 5.5 V 2.125 39 s
2.7 V VDD 5.5 V 3.1875 39 s
2.4 V VDD 5.5 V 17 39 s
10-bit resolution
Target pin: internal reference voltag e, and
temperature sensor output voltage
(HS (high-speed main) mode)
3.6 V VDD 5.5 V 2.375 39 s
2.7 V VDD 5.5 V 3.5625 39 s
2.4 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR
Full-scale error Notes 1, 2 EFS 10-bit resolution 2.4 V VDD 5.5 V 0.60 %FSR
Integral linearity error Note 1 ILE 10-bit resolution 2.4 V VDD 5.5 V 4.0 LSB
Differential linearity error
Note 1 DLE 10-bit resolution 2.4 V VDD 5.5 V 2.0 LSB
Analog input voltage VAIN ANI0 to ANI14 0 VDD V
ANI16 to ANI20 0 EVDD0 V
Internal reference vo ltage
(2.4 V VDD 5.5 V, HS (high-speed main) mode) VBGR Note 3 V
Temperature sensor output voltage
(2.4 V VDD 5.5 V, HS (high-speed main) mode) VTMPS25 Note 3 V
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 163 of 187
Oct 25, 2013
Note 1. Excludes quantization error (±1/2 LSB).
Note 2. This value is indicated as a ratio (% FSR) to the full-scale value.
Note 3. Refer to 3.6.2
Temperature sensor cha rac ter i stics /inter na l refe ren c e vo ltage characte ristic
.
Note 4. When reference voltage (-) = VSS, the MAX. values are as follows.
Zero-scale error: Add ±0.35%FSR to the MAX. value when reference voltage (-) = AVREFM.
Integral linearity error: Add ±0.5 LSB to the MAX. value when reference voltage (-) = AVREFM.
Differential linearity error: Add ±0.2 LSB to the MAX. value when reference voltage (-) = AVREFM.
(4)
When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (-)
= AVREFM/ANI1 (ADREFM = 1), target pin: ANI0, ANI2 to ANI14, ANI16 to ANI20
(TA = -40 to +105 °C, 2.4 V VDD 5.5 V, 1.6 V EVDD = EVDD1 VDD, VSS = EVSS0 = EVSS1 = 0 V,
Reference voltage (+) = VBGR Note 3, Reference voltage (-) = AVREFM = 0 V Note 4, HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Conversion time tCONV 8-bit resolution 2.4 V VDD 5.5 V 17 39 s
Zero-scale error Notes 1, 2 EZS 8-bit resolution 2.4 V VDD 5.5 V 0.60 % FSR
Integral linearity error Note 1 ILE 8-bit resolution 2.4 V VDD 5.5 V 2.0 LSB
Differential linearity error Note 1 DLE 8-bit resolution 2.4 V VDD 5.5 V 1.0 LSB
Analog input voltage VAIN 0VBGR Note 3 V
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 164 of 187
Oct 25, 2013
3.6.2
Temperature sensor characteristics/internal reference voltage characteristic
3.6.3 D/A converter characteristics
(TA = -40 to +105 °C, 2.4 V VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, HS (high-sp ee d ma in) m ode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25 C1.05 V
Internal reference voltage VBGR Setting ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that depends on the
temperature -3.6 mV/C
Operation stabilization wait time tAMP 5s
(TA = -40 to +105 C, 2.4 V EVSS0 = EVSS1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8bit
Overall error AINL Rload = 4 M2.4 V VDD 5.5 V 2.5 LSB
Rload = 8 M2.4 V VDD 5.5 V 2.5 LSB
Settling time tSET Cload = 20 pF 2.7 V VDD 5.5 V 3 s
2.4 V VDD < 2.7 V 6 s
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 165 of 187
Oct 25, 2013
3.6.4 Comparator
Note Not usable in sub-clock operation or STOP mode.
3.6.5 POR circuit characteristics
Note 1. However, when the operating voltage falls while the LVD is off, enter STOP mode, or enable the reset status using the
external reset pin before the voltage falls below the operating voltage range shown in 3.4 AC Characteristics.
Note 2. Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time required for a
POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is entered or the main
system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock operation status control register
(CSC).
(TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage range Ivref 0EV
DD0 - 1.4 V
Ivcmp -0.3 EVDD0 + 0.3 V
Output delay td VDD = 3.0 V
Input slew rate > 50 mV/sComparator high-speed mode,
standard mode 1.2 s
Comparator high-speed mode,
window mode 2.0 s
Comparator low-speed mode,
standard mode 3.0 5.0 s
High-electric-potential
reference voltage VTW+ Comparator high-speed mode, window mode 0.76 VDD V
Low-electric-potential
reference voltage VTW- Comparator high-speed mode, window mode 0.24 VDD V
Operation stabilization
wait time tCMP 100 s
Internal reference voltage
Note VBGR 2.4 V VDD 5.5 V, HS (high-speed main) mode 1.38 1.45 1.50 V
(TA = -40 to +105 C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOR Power supply rise time 1.45 1.51 1.57 V
VPDR Power supply fall time Note 1 1.44 1.50 1.56 V
Minimum pulse width Note 2 TPW 300 s
TPW
VPOR
VPDR or 0.7 V
Supply voltage (VDD)
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 166 of 187
Oct 25, 2013
3.6.6 LVD circuit characteristics
(1) LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = -40 to +105 C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage Supply voltage level VLVD0 Power supply rise time 3.90 4.06 4.22 V
Power supply fall time 3.83 3.98 4.13 V
VLVD1 Power supply rise time 3.60 3.75 3.90 V
Power supply fall time 3.53 3.67 3.81 V
VLVD2 Power supply rise time 3.01 3.13 3.25 V
Power supply fall time 2.94 3.06 3.18 V
VLVD3 Power supply rise time 2.90 3.02 3.14 V
Power supply fall time 2.85 2.96 3.07 V
VLVD4 Power supply rise time 2.81 2.92 3.03 V
Power supply fall time 2.75 2.86 2.97 V
VLVD5 Power supply rise time 2.70 2.81 2.92 V
Power supply fall time 2.64 2.75 2.86 V
VLVD6 Power supply rise time 2.61 2.71 2.81 V
Power supply fall time 2.55 2.65 2.75 V
VLVD7 Power supply rise time 2.51 2.61 2.71 V
Power supply fall time 2.45 2.55 2.65 V
Minimum pulse width tLW 300 s
Detection delay time 300 s
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 167 of 187
Oct 25, 2013
3.6.7 Power supply voltage rising slope characteristics
Caution Make sure to keep the intern al reset state by the LVD circuit or an external rese t until V DD reaches the op erating
voltage range shown in 3.4 AC Characteristics.
(2) LVD Detection Voltage of Interrupt & Reset Mode
(TA = -40 to +105 C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Interrupt and
reset mode
VLVDD0 VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage 2.64 2.75 2.86 V
VLVDD1 LVIS1, LVIS0 = 1, 0 Rising release reset voltage 2.81 2.92 3.03 V
Falling interrupt voltage 2.75 2.86 2.97 V
VLVDD2 LVIS1, LVIS0 = 0, 1 Rising release reset voltage 2.90 3.02 3.14 V
Falling interrupt voltage 2.85 2.96 3.07 V
VLVDD3 LVIS1, LVIS0 = 0, 0 Rising release reset voltage 3.90 4.06 4.22 V
Falling interrupt voltage 3.83 3.98 4.13 V
(TA = -40 to +105 C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Power supply voltage rising slope SVDD 54 V/ms
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 168 of 187
Oct 25, 2013
3.7 Dat a Memory STOP Mode Low Supply Voltage Data Retention Characteristics
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is
effected, but data is not retained when a POR reset is effected.
3.8 Flash Memory Programming Characteristics
Note 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite.
Note 2. When using flash memory programmer and Renesas Electronics self-programming library
Note 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics
Corporation.
3.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = -40 to +105 C, VSS = 0V))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply
voltage VDDDR 1.44 Note 5.5 V
(TA = -40 to +105 C, 2.4 V VDD 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
System clock frequency fCLK 2.4 V VDD 5.5 V 1 32 MHz
Number of code flash rewrites
Notes 1, 2, 3 Cerwr Retained for 20 years TA = 85 C 1,000 Times
Number of data flash rewrites
Notes 1, 2, 3 Retained for 1 year TA = 25 C 1,000,000
Retained for 5 years TA = 85 C 100,000
Retained for 20 years TA = 85 C 10,000
(TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate During serial programming 115,200 1,000,000 bps
VDD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
Operation mode
VDDDR
RL78/G14 3. ELECTRICAL SPECIFICATIONS (G: TA = -40 to +105 C)
R01DS0053EJ0200 Rev. 2.00 Page 169 of 187
Oct 25, 2013
3.10 Timing for Switching Flash Memory Programming Modes
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the external reset ends).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from
when the external resets end.
tSU: How long from when the TOOL0 pin is placed at the low level until a pin reset ends
tHD: How long to keep the TOOL0 pin at the low level from when the external resets end
(excluding the processing time of the firmware to control the flash memory)
(TA = -40 to +105 C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
How long from when an external reset ends until the
initial communication settings are specified tSUINIT POR and LVD reset must end
before the external reset ends. 100 ms
How long from when the TOOL0 pin is placed at the
low level until an external reset ends tSU POR and LVD reset must end
before the external reset ends. 10 s
How long the TOOL0 pin must be kept at the low
level after an external reset ends
(excluding the processing time of the firmware to
control the flash memory)
tHD POR and LVD reset must end
before the external reset ends. 1ms
RESET
TOOL0
<1> <2> <3>
tSU
<4>
tSUINIT
723 µs + tHD
processing
time
00H reception
(TOOLRxD, TOOLTxD m ode)
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 170 of 187
Oct 25, 2013
4. PACKAGE DRAWINGS
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 171 of 187
Oct 25, 2013
4.1 30-pin products
R5F104AAASP, R5F104ACASP, R5F104ADASP, R5F104AEASP, R5F104AF ASP, R5F104AGASP
R5F104AADSP, R5F104ACDSP, R5F104ADDSP, R5F104 AEDSP, R5F104AFDSP, R5F1 04AGDSP
R5F104AAGSP, R5F104ACGSP, R5F104ADGSP, R5F104AEGSP, R5F104AFGSP, R5F104AGGSP
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18
S
S
H
J
T
I
G
D
E
F
CB
K
PL
U
NITEM
B
C
I
L
M
N
A
K
D
E
F
G
H
J
P
30 16
115
A
detail of lead end
M
M
T
MILLIMETERS
0.65 (T.P.)
0.45 MAX.
0.13
0.5
6.1p0.2
0.10
9.85p0.15
0.17p0.03
0.1p0.05
0.24
1.3p0.1
8.1p0.2
1.2
0.08
0.07
1.0p0.2
3o5o
3o
0.25
0.6p0.15
U
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 172 of 187
Oct 25, 2013
4.2 32-pin products
R5F104BAANA, R5F104BCANA, R5F104BDANA, R5F104BEANA, R5F104BFANA, R5F104BGANA
R5F104BADNA, R5F104BCDNA, R5F104BDDNA, R5F104BEDNA, R5F1 04BFDNA, R5F1 04BGDNA
R5F104BAGNA, R5F104BCGNA, R5F104BDGNA, R5F1 04BEGNA, R5F104BFGNA, R5F104BGGNA
2012 Renesas Electronics Corporation. All rights reserved.
S
y
e
Lp
SxbA B
M
A
D
E
24
16
17
8
9
1
32
A
S
B
A
S
D2
E2
25
DETAIL OF A PART
EXPOSED DIE PAD
ITEM D2 E2
A
MIN NOM MAX
3.45 3.50
EXPOSED
DIE PAD
VARIATIONS
3.55
MIN NOM MAX
3.45 3.50 3.55
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-HWQFN32-5x5-0.50 PWQN0032KB-A P32K8-50-3B4-4 0.06
D
E
A
b
e
Lp 0.40
0.50
5.00
5.00
0.75
0.25
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.70
0.18
0.80
0.30
0.30 0.50
x0.05
4.95
4.95
5.05
5.05
y0.05
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 173 of 187
Oct 25, 2013
R5F104BAAFP, R5F104BCAFP, R5F104BDAFP, R5F104BEAFP, R5F104BFAFP, R5F104BGAFP
R5F104BADFP, R5F104BCDFP, R5F104BDDFP, R5F104BEDFP, R5F104BFDFP, R5F104BGDFP
R5F104BAGFP, R5F104BCGF P, R5F104BDGFP, R5F104BEGFP, R5F104BFGFP, R5F104BGGFP
0.145±0.055
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
7.00±0.10
7.00±0.10
9.00±0.20
9.00±0.20
1.70 MAX.
0.10±0.10
1.40
c
θ
e
x
y
0.80
0.20
0.10
L0.50±0.20
0° to 8°
0.37±0.05
b
NOTE
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
y
e
xb M
θ
L
c
HD
HE
A1
A2
A
D
E
detail of lead end
8
16
1
32 9
17
25
24
2
1
3
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP32-7x7-0.80 PLQP0032GB-A P32GA-80-GBT-1 0.2
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 174 of 187
Oct 25, 2013
4.3 36-pin products
R5F104CAALA, R5F104CCALA, R5F104CDALA, R5F104CEALA, R5F104CFALA, R5F104CGALA
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023
ITEM DIMENSIONS
D
E
w
e
A
b
x
y
y1
ZD
ZE
4.00p0.10
4.00p0.10
0.05
0.20
0.69p0.07
0.08
0.50
0.24p0.05
(UNIT:mm)
0.20
0.75
0.75
S
y1 S A
S
y
Sx32x b A B
M
e
SwB
ZD
ZE
INDEX MARK
B
C
A
SwA
D
E
E
1
2
E
FDCBA
3
4
5
6
CDDETAIL DETAIL EDETAIL
b
0.34p0.05 0.55
0.70 p0.05
0.55 p0.05
0.70 p0.05
0.55 p0.05
0.75
F
F
0.75
0.55 0.55
R0.17p0.05 R0.17 p0.05
R0.12 p0.05 R0.12 p0.05
R0.275p0.05
R0.35p0.05
0.75
0.55p0.05
0.70p0.05
0.55
0.75
0.55p0.05
0.70p0.05
(LAND PAD)
(APERTURE OF
SOLDER RESIST)
D
2.90
2.90
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 175 of 187
Oct 25, 2013
4.4 40-pin products
R5F104EAANA, R5F104ECANA, R5F104EDANA, R5F104EEANA, R5F104EFANA, R5F104EGANA,
R5F104EHANA
R5F104EADNA, R5F104ECDNA, R5F104EDDNA, R5F104EEDNA, R5F1 04EFDNA, R5F1 04EGDNA,
R5F104EHDNA
R5F104EAGNA, R5F104ECGNA, R5F104EDGNA, R5F1 04EEGNA, R5F104EFGNA, R5F104EGGNA,
R5F104EHGNA
2012 Renesas Electronics Corporation. All rights reserved.
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-4 0.09
DETAIL OF A PART
S
y
e
Lp
SxbA B
M
A
D
E
30
20
21
10
11
1
40
A
S
B
A
S
D2
E2
31
EXPOSED DIE PAD
ITEM D2 E2
A
MIN NOM MAX
4.45 4.50
EXPOSED
DIE PAD
VARIATIONS
4.55
MIN NOM MAX
4.45 4.50 4.55
D
E
A
b
e
Lp 0.40
0.50
6.00
6.00
0.75
0.25
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.70
0.18
0.80
0.30
0.30 0.50
x0.05
5.95
5.95
6.05
6.05
y0.05
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 176 of 187
Oct 25, 2013
4.5 44-pin products
R5F104FAAFP, R5F104FCAFP, R5F104FDAFP, R5F104FEAFP, R5F104FFAFP, R5F104 FGAFP,
R5F104FHAFP, R5F104FJAFP
R5F104FADFP, R5F104FCDFP, R5F104 FDDFP, R5F104FEDFP, R5F104FFDFP, R5F104FGDFP,
R5F104FHDFP, R5F104FJDFP
R5F104F AGFP, R5F104FCGFP, R5F104FDGFP, R5F104FEGFP, R5F104FFGFP, R5F104FGGFP,
R5F104FHGFP, R5F104FJGFP
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP44-10x10-0.80 PLQP0044GC-A P44GB-80-UES-2 0.36
S
y
e
Sxb M
Q
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S0.145 0.055
0.045
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
10.00p0.20
10.00p0.20
12.00p0.20
12.00p0.20
1.60 MAX.
0.10p0.05
1.40p0.05
0.25
c
Q
e
x
y
ZD
ZE
0.80
0.20
0.10
1.00
1.00
L
Lp
L1
0.50
0.60p0.15
1.00p0.20
3o5o
3o
NOTE
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
detail of lead end
0.370.08
0.07
b
11
22
1
44 12
23
34
33
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 177 of 187
Oct 25, 2013
4.6 48-pin products
R5F104GAAFB, R5F104GCAFB, R5F104GDAFB, R5F104GEAFB, R5F104GFAFB, R5F104GGAFB,
R5F104GHAFB, R5F104GJAFB
R5F104GADFB, R5F104GCDFB, R5F104GDDFB, R5F104GEDFB, R5F104GFDFB, R5F104GGDFB,
R5F104GHDFB, R5F104GJDFB
R5F104GAGFB, R5F104GCGFB, R5F104GDGFB, R5F104GEGFB, R5F104GFGFB, R5F104GGGFB,
R5F104GHGFB, R5F104GJGFB
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16
S
y
e
Sxb M
Q
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.145 0.055
0.045
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
7.00p0.20
7.00p0.20
9.00p0.20
9.00p0.20
1.60 MAX.
0.10p0.05
1.40p0.05
0.25
c
Q
e
x
y
ZD
ZE
0.50
0.08
0.08
0.75
0.75
L
Lp
L1
0.50
0.60p0.15
1.00p0.20
3o5o
3o
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
detail of lead end
0.22p0.05
b
12
24
1
48 13
25
37
36
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 178 of 187
Oct 25, 2013
R5F104GAANA, R5F104GCANA, R5F104GDANA, R5F104GEANA, R5F104GFANA, R5F104GGANA,
R5F104GHANA, R5F104GJANA
R5F104GADNA, R5F104GCDNA, R5F104GDDNA, R5F104GEDNA, R5F104GFDNA, R5F104GGDNA,
R5F104GHDNA, R5F104GJDNA
R5F104GAGNA, R5F104GCGNA, R5F104GDGNA, R5F104GEGNA, R5F104GFGNA, R5F104GGGNA,
R5F104GHGNA, R5F104GJGNA
DETAIL OF A PART
S
y
e
Lp
SxbA B
M
A
D
E
36
37 24
25
12
13
1
48
A
S
B
A
S
D2
E2
EXPOSED DIE PAD
ITEM D2 E2
A
MIN NOM MAX
5.45 5.50
EXPOSED
DIE PAD
VARIATIONS
5.55
MIN NOM MAX
5.45 5.50 5.55
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A
P48K8-50-5B4-5 0.13
D
E
A
b
e
Lp 0.40
0.50
7.00
7.00
0.75
0.25
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.70
0.18
0.80
0.30
0.30 0.50
x0.05
6.95
6.95
7.05
7.05
y0.05
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 179 of 187
Oct 25, 2013
4.7 52-pin products
R5F104JCAFA, R5F104JDAFA, R5F104JEAFA, R5F10 4JFAFA, R5F104JGAFA, R5F104JHAFA, R5F104JJAFA
R5F104JCDFA, R5F104JDDFA, R5F104JEDFA, R5F104JFDFA, R5F104JGDFA, R5F104JHDFA, R5F104JJDFA
R5F104JCGFA, R5F104JDGFA, R5F104JEGFA, R5F104JFGF A, R5F104JGGFA, R5F104JHGFA, R5F104JJGFA
y
e
xb M
θ
L
c
HD
HE
A1
A2
A
D
E
0.145±0.055
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
10.00±0.10
10.00±0.10
12.00±0.20
12.00±0.20
1.70 MAX.
0.10±0.05
1.40
c
θ
e
x
y
0.65
0.13
0.10
L0.50±0.15
0° to 8°
detail of lead end
0.32±0.05
b
13
26
1
52 14
27
40
39
2
1
3
NOTE
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP52-10x10-0.65 PLQP0052JA-A P52GB-65-GBS-1 0.3
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 180 of 187
Oct 25, 2013
4.8 64-pin products
R5F104LCAFA, R5F104LDAFA, R5F104LEAFA, R5F104LFAFA, R5F104LGAFA, R5F104LHAFA, R5F104LJAFA
R5F104LCDFA, R5F104LDDFA, R5F104LEDFA, R5F104LFDFA, R5F104LGDFA, R5F104LHDFA, R5F104LJDF A
R5F104LCGFA, R5F104LDGFA, R5F104LEGFA, R5F104LFGFA, R5F104LGGFA, R5F104LHGFA, R5F104 LJGFA
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP64-12x12-0.65 PLQP0064JA-A P64GK-65-UET-2 0.51
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
detail of lead end
Q
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
16
32
1
64 17
33
49
48
S
y
e
Sxb M
A3
S
0.145 0.055
0.045
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
12.00p0.20
12.00p0.20
14.00p0.20
14.00p0.20
1.60 MAX.
0.10p0.05
1.40p0.05
0.25
c
Q
e
x
y
ZD
ZE
0.65
0.13
0.10
1.125
1.125
L
Lp
L1
0.50
0.60p0.15
1.00p0.20
3o5o
3o
0.320.08
0.07
b
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 181 of 187
Oct 25, 2013
R5F104LCAFB, R5F104LDAFB, R5F104LEAFB, R5F104LFAFB, R5F104LGAFB, R5F104LHAFB,
R5F104LJAFB
R5F104LCDFB, R5F104LDDFB, R5F 104LEDFB, R5F104LFDFB, R5F10 4LGDFB, R5F104LHDFB,
R5F104LJDFB
R5F104LCGFB, R5F104LDGFB, R5F104LEGFB, R5F104 LFGFB, R5F104LGGFB, R5F104LHGFB ,
R5F104LJGFB
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LFQFP64-10x10-0.50 PLQP0064KF-A P64GB-50-UEU-2 0.35
S
y
e
Sxb M
Q
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.145 0.055
0.045
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
10.00p0.20
10.00p0.20
12.00p0.20
12.00p0.20
1.60 MAX.
0.10p0.05
1.40p0.05
0.25
c
Q
e
x
y
ZD
ZE
0.50
0.08
0.08
1.25
1.25
L
Lp
L1
0.50
0.60p0.15
1.00p0.20
3o5o
3o
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
detail of lead end
0.22p0.05
b
16
32
1
64 17
33
49
48
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 182 of 187
Oct 25, 2013
R5F104LCALA, R5F104LDALA, R5F104LEALA, R5F104LFALA, R5F104LGALA, R5F104LHALA, R5F104LJALA
64-PIN PLASTIC FLGA (5x5)
E
w
5.00o0.10
0.20
y
0.20
0.08
y1
ZD 0.75
0.05x
D 5.00o0.10
A 0.69o0.07
b0.25o0.04
P64FC-50-AN5
ZE 0.75
S
BSw
S
y
y1
e0.50
INDEX MARK
wSA ZD
ZE
A
b
S
A
B
e
xS
8
7
6
5
4
3
2
1
BCDEFGH A
C
D
CDDETAIL DETAIL EDETAIL
M
60x A B
ITEM DIMENSIONS
(UNIT:mm)
3.90
3.90
b
0.34o0.03 0.55
0.70o0.03
0.55o0.04
0.70o0.03
0.55o0.04
0.75 0.75
0.55 0.55
R0.17o0.015 R0.17o0.015
R0.125o0.02 R0.125o0.02
R0.275o0.02
R0.35o0.015
0.75
0.55o0.04
0.70o0.03
0.55
0.75
0.55o0.04
0.70o0.03
(LAND PAD)
(APERTURE OF
SOLDER RESIST)
E
E
D
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 183 of 187
Oct 25, 2013
R5F104LCAFP, R5F10 4LDAFP, R5F104LEAFP, R5F104LFAFP, R5F104L GAFP, R5F104LHAFP, R5F104LJAFP
R5F104LCDFP, R5F104LDDFP, R5F104LEDFP, R5F104LFDFP, R5F104 LGDFP, R5F104LHDFP, R5F 104LJDFP
R5F104LCGFP, R5F104LDGFP, R5F104LEGF P, R5F104LFGFP, R5F104LGGFP, R5F104LHGFP, R5F104LJGFP
y
e
xb M
HD
HE
A1
A2
A
D
E
0.125
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
14.00±0.10
14.00±0.10
16.00±0.20
16.00±0.20
1.70 MAX.
0.10±0.10
1.40
c
θ
L0.50±0.20
0° to 8°
detail of lead end
0.37
b
16
32
1
64 17
33
49
48
2
1
3
−0.02
+0.05
−0.05
+0.08
θ
L
c
NOTE
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP64-14x14-0.80 PLQP0064GA-A P64GC-80-GBW-1 0.7
0.80
0.20
0.10
e
x
y
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 184 of 187
Oct 25, 2013
4.9 80-pin products
R5F104MFAFB, R5F104MGAFB, R5F104MHAFB, R5F104MJAFB
R5F104MFDFB, R5F104MGDFB, R5F104MHDFB, R5F104MJDFB
R5F104MFGFB, R5F104MGGFB, R5F104MHGFB, R5F104MJGFB
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LFQFP80-12x12-0.50 PLQP0080KE-A P80GK-50-8EU-2 0.53
S
y
e
Sxb M
Q
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.145 0.055
0.045
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
12.00p0.20
12.00p0.20
14.00p0.20
14.00p0.20
1.60 MAX.
0.10p0.05
1.40p0.05
0.25
c
Q
e
x
y
ZD
ZE
0.50
0.08
0.08
1.25
1.25
L
Lp
L1
0.50
0.60p0.15
1.00p0.20
3o5o
3o
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
detail of lead end
0.22p0.05
b
20
40
1
80 21
41
61
60
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 185 of 187
Oct 25, 2013
R5F104MFAFA, R5F104MGAFA, R5F104MHAFA, R5F104MJAFA
R5F104MFDFA, R5F104MGDFA, R5F104MHDFA, R5F104MJDFA
R5F104MFGFA, R5F104MGGFA, R5F104MHGFA, R5F104MJGFA
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP80-14x14-0.65 PLQP0080JB-E P80GC-65-UBT-2 0.69
D
E
HD
HE
A
A2
bp
c
Lp
Q
x
L1
0.13
0.886
14.00
14.00
17.20
17.20
1.40
0.10
Referance
Symbol Min Nom Max
Dimension in Millimeters
A1 0.05
1.35
0.26
1.70
0.20
1.45
0.38
13.80
13.80
17.00
17.00
14.20
14.20
17.40
17.40
0.10 0.20
e0.65
0.736 1.036
1.60
0n8n
A3 0.25
0.125
0.32
0.145
L0.80
1.40 1.80
ZD 0.825
ZE 0.825
3n
y
S
y
e
Sxbp M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
E
A3
S
detail of lead end
20
40
1
80 21
41
D
A
B
AB
61
60
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 186 of 187
Oct 25, 2013
4.10 100-pin products
R5F104PFAFB, R5F104PGAFB, R5F104PHAFB, R5F104PJAFB
R5F104PFDFB, R5F104PGDFB, R5F104PHDFB, R5F104PJDFB
R5F104PFGFB, R5F104PGGFB, R5F104PHGFB, R5F104PJGFB
S
y
e
Sxb M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.145
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
14.00p0.20
14.00p0.20
16.00p0.20
16.00p0.20
1.60 MAX.
0.10p0.05
1.40p
0.05
0.25
c
e
x
y
ZD
ZE
0.50
0.08
0.08
1.00
1.00
L
Lp
L1
0.50
0.60p0.15
1.00p0.20
3o3o
5o
detail of lead end
0.22
0.055
0.045
b
25
50
1
100 26
51
75
76
p0.05
A
B
AB
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LFQFP100-14x14-0.50 PLQP0100KE-A P100GC-50-GBR-1 0.69
RL78/G14 4. PACKAGE DRAWINGS
R01DS0053EJ0200 Rev. 2.00 Page 187 of 187
Oct 25, 2013
R5F104PFAFA, R5F104PGAFA, R5F104PHAFA, R5F104PJAFA
R5F104PFDFA, R5F104PGDFA, R5F104PHDFA, R5F104PJDFA
R5F104PFGFA, R5F104PGGFA, R5F104PHGFA, R5F104PJGFA
B
S
y
e
Sxb M
L
c
Lp
HD
HE
ZD
ZE
L1
A1
A2
A
D
E
A3
S
0.145
(UNIT:mm)
ITEM DIMENSIONS
D
E
HD
HE
A
A1
A2
A3
20.00 0.20
14.00 0.20
22.00 0.20
16.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.07
0.08
0.055
0.045
0.25
c
e
x
y
ZD
ZE
0.65
0.13
0.10
0.575
0.825
L
Lp
L1
0.50
0.60 0.15
5
3
1.00 0.20
3
detail of lead end
0.32
b
30
50
1
100 31
51
81
80
A
AB
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LQFP100-14x20-0.65 PLQP0100JC-A P100GF-65-GBN-1 0.92
C - 1
RL78/G14 Datasheet
Rev. Date Description
Page Summary
0.01 Feb 10, 2011 — First Edition issued
0.02 May 01, 2011 1 to 2 1.1 Features revised
3 1.2 Ordering Information revised
4 to 13 1.3 Pin Configuration (Top View) revised
14 1.4 Pin Identificatio n revised
15 to 17 1.5.1 30-pin products to 1.5.3 36-pin products revised
23 to 26 1.6 Outline of Fun c tions revised
0.03 Jul 28, 2011 1 1.1 Features revised
1.00 Feb 21, 2012 1 to 40 1. OUTLINE revised
41 to 97 2. ELECTRICAL SPECIFICATIONS added
2.00 Oct 25, 2013 1 Modification of 1.1 Features
3 to 8 Modification of 1.2 Ordering Information
9 to 22 Modification of package type in 1.3 Pin Configuration (Top View)
34 to 43 Modification of description of subsystem clock in 1.6 Outline of Functions
34 to 43 Modification of description of timer output in 1.6 Outline of Functions
34 to 43 Modificati on of er ror of data transfer controller in 1.6 Outline of Functions
34 to 43 Modificati on of er ror of event link controller in 1.6 Outline of Functions
45, 46 Modification of description of Tables in 2.1 Absolute Maximum Ratings
47 Modification of Tables, notes, cautions, and remarks in 2.2 Oscillator
Characteristics
48 Modification of error of conditions of high level input voltage in 2.3.1 Pin
characteristics
49 Modification of error of conditions of low level output voltage in 2.3.1 Pin
characteristics
53 to 62 Modification of Notes and Remarks in 2.3.2 Su pply current characteristics
65, 66 Addition of Minimum Instruction Execution Time during Main System Clock
Operation
67 to 69 Addition of AC Timing Test Points
70 to 97 Addition of LS mode and LV mode characteristics in 2.5.1 Serial array unit
98 to 101 Addition of LS mode and LV mode characteristics in 2.5.2 Serial interface IICA
102 to 105 Addition of characteristics about conversion of internal reference voltage and
temperature sensor in 2.6.1 A/D converter characteristics
107 Addition of characteristic in 2.6.4 Comparator
107 Deletion of detection delay in 2.6.5 POR circui t characteristics
109 Modification of 2.6.7 Power supply voltage rising slope characteristics
110 Modification of 2.7 Data Memory STOP Mode Low Supply Voltage Data
Retention Characteristics
110 Addition of characteristic in 2.8 Flash Memory Programming Characteristics
111 Addition of description in 2.10 Timing for Switching Flash Memory Programming
Modes
REVISION HIST ORY
REVISION HIST ORY RL78/G14 Datasheet
C - 2
2.00 Oct 25, 2013 112 to 169 Addition of CHAPTER 3 ELECTRICAL SPECIFICATIONS
171 to 187 Modificati on of 4.1 30-pin products to 4.10 100-pin products
Rev. Date Description
Page Summary
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries
including the United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
All trademarks and registered trademarks are the property of their respective owners.
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, et c., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up o r pull-down circuitry. Each unused pin should b e
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequat e. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive m aterial. All test and measuremen t
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and exter nal interface, as a rule, s witch on the external power supply after s witching on the in ternal
power supply. When s witching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence m ust be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device an d accord ing to related specifications govern ing the device.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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R
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2880 Scott Boulevard Santa Clara
,
CA 95050-2554
,
U.S.A
.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-651-700, Fax: +44-1628-651-804
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre Singapore 339949
Tel: +65-6213-0200, Fax: +65-6213-0300
Renesas Electronics Mala
y
sia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petalin
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Jaya, Selan
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or Darul Ehsan, Malaysi
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Tel: +60-3-7955-9390
,
Fax: +60-3-7955-951
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Renesas Electronics Korea Co.
,
Ltd
.
11F., Samik Lavied' or Bld
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., 720-2 Yeoksam-Don
g
, Kan
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nam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737
,
Fax: +82-2-558-514
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