Rev 1
December 2005 1/46
1
CR14
Low Cost ISO14443 type-B Contactless Coupler Chip
with Anti-Collision and CRC Management
Features summary
■Single 5V ±500mV Supply Voltage
■SO16N package
■Contactless Communication
– ISO14443 type-B protocol
– 13.56MHz Carrier Frequency using an
Exter nal Oscillator
– 106 Kbit/s Data Rate
– 36 Byte Input/Output Frame Register
– Supports Frame Answer with/without SOF/
EOF
– CRC Generation and Check
– Automated ST Anti-Collision Exchange
■I²C Communication
– Two Wire I²C Serial Interface
– Supports 400kHz Protocol
– 3 Chip Enable Pins
– Up to 8 CR14 Conn e cte d on the Sam e Bus
16
1
SO16 (MQ)
150 mils width
www.st.com
CR14
2/46
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Oscillator (OSC1, OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Antenna Output Driver (RFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Antenna Input Filter (RFIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Transmitter Reference Voltage (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 Power Supply (VCC, GND, GND_RF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 CR14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Parameter Register (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Input/Output Frame Register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Slot Marker Register (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4 CR14 I²C protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 I²C Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 I²C Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 I²C Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 I²C Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5 I²C Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 CR14 I²C Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 CR14 I²C Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Applying the I²C protocol to the CR14 registers . . . . . . . . . . . . . . . . . . . . 22
5.1 I²C Parameter Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 I²C Input/Output Frame Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 I²C Slot Marker Register Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.4 Addresses above Location 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CR14
3/46
6 CR14 ISO14443 type-B Radio Frequency data transfer . . . . . . . . . . . . . . 26
6.1 Output RF Data Transfer from the CR14 to the PICC (Request Frame) . . . . 26
6.2 Transmission Format of Request Frame Characters . . . . . . . . . . . . . . . . . . 27
6.3 Request Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4 Request End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.5 Input RF Data Transfer from the PICC to the CR14 (Answer Frame) . . . . . . 28
6.6 Transmission Format of Answer Frame Characters . . . . . . . . . . . . . . . . . . . 29
6.7 Answer Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.8 Answer End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.9 Transmission Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.10 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Tag access using the CR14 coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1 Standard TAG Command Access Description . . . . . . . . . . . . . . . . . . . . . . . 31
7.2 Anti-Collision TAG Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Appendix A ISO14443 type B CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CR14
4/46
List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. CR14 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Parameter Register Bits Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Input/Output Frame Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Slot Marker Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. CR14 Request Frame Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. I²C AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10. I²C Input Parameters(1,2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. I²C DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12. I²C AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 13. RFOUT AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 14. RFIN AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 15. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 16. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CR14
5/46
List of figures
Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Logic Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. SO Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. CR14 Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I²C Bus . . . . . . . . . . . . . . . . . 11
Figure 6. I²C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. CR14 I²C Write Mode Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. I²C Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. CR14 I²C Read Modes Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Host-to-CR14 Transfer: I²C Write to Parameter Register . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. CR14-to-Host Transfer: I²C Random Address Read from Parameter Register . . . . . . . . . 22
Figure 12. CR14-to-Host Transfer: I²C Current Address Read from Parameter Register . . . . . . . . . . 22
Figure 13. Host-to-CR14 Transfer: I²C Write to Input/Output Frame Register for ISO14443B . . . . . . 23
Figure 14. CR14-to-Host Transf er: I²C Random Address Read from Input/Output Frame
Register for ISO14443B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 15. CR14-to-Host Transfer: I²C Current Address Read from I/O Frame Register
for ISO14443B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 16. Host-to-CR14 Transfer: I²C Write to Slot Marker Register . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17. CR14-to-Host Transfer: I²C Random Address Read from Slot Marker Register . . . . . . . . 25
Figure 18. CR14-to-Host Transfer: I²C Current Address Read from Slot Marker Register . . . . . . . . . 25
Figure 19. Wave Transmitted using ASK Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 20. CR14 Request Frame Character Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 21. Request Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 22. Request End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23. Wave Received using BPSK Sub-carrier Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24. Answer Start Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 25. Answer End Of Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 26. Example of a Complete Transmission Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 27. CRC Transmission Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 28. Standard TAG Command: Request Frame Transmission . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 29. Standard TAG Command: Answer Frame Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 30. Standard TAG Command: Complete TAG Access Description . . . . . . . . . . . . . . . . . . . . . 32
Figure 31. Anti-Collision ST short range memory Sequence (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 32. Anti-Collision ST short range memory Sequence Continued . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 33. I²C AC Testing I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 34. I²C AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 35. CR14 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 36. SO16 Narrow - 16 lead Plasti c Small Outline, 150 mils body width, Package Outline. . . . 42
1 Summar y description CR14
6/46
1 Summary description
The CR14 is a contactless coupler that is compliant with the short range ISO14443 type-B
standard. It is con trolled using the two wire I ²C bus.
The CR14 generates a 13.56MHz signal on an external antenna. Transmitted data are
modulated using Amplitude Shift Keying (ASK). Received data are demodulated from the PICC
(Proximity integrated Coupling Card) load variation signal, induced on the anten na, using Bit
Phase Shift Keying (BPSK) of a 847kHz sub-carrier. The Transmitted ASK wave is 10%
modulated. The D ata transfer rate between the CR14 and the PICC is 106 Kbit /s in bo th
transmission and reception modes.
The CR14 f ollo ws the ISO14443 type -B recommendation f or Radio f requency pow er and signa l
interface.
The CR14 is specifically designed for short range applications that ne ed disposable and
reusable products.
The CR14 includes an automated anti-collision mechanism that allows it to detect and select
any ST short range memories that are present at the same time within its range. The anti-
collision mechanism is based on the STMicroelectronics probabilistic scanning method.
The CR14 prov ides a complete analog inte rface, compliant with the ISO14443 type-B
recommendations for Radio-Frequency power and signal interfacing. With it, any ISO1 4443
type-B PICC pr oducts can be po w ered and ha ve their data tran smission controlle d via a simple
antenna.
The CR14 is fabricated in STMicroelectronics High Endurance Single Poly-silicon CMOS
technology.
The CR14 is organized as 4 different blocks (see Figure 2):
●The I²C bus controller. It handles the serial connecti on with the application host. It is
compliant with the 400kHz I² C bus specification, and controls the read/write access to all
the CR14 registers.
●The RAM buff er. It is bi-directional. . It stores all the request frame Bytes to be transmitted
to the PICC, and all the received Bytes sent by the PICC on the answer frame.
●The transmitter. It powers the PICCs by generating a 13.56MHz signal on an external
antenna. The resulting field is 10% modulated using ASK (amplitude shift keying) for
outgoing data.
●The receiver. It demodulates the signal generated on the ante nna by th e load variation of
the PICC. The resulting signal is decoded by a 847kHz BPSK (binary phase shift keying)
sub-carrier de co de r.
The CR14 is designed to be conn ected to a digita l host (Microcontr oller or ASIC). This host has
to manage the entire communication protocol in both tr ansmit and receive modes, through the
I²C serial bus.
CR14 1 Summar y description
7/46
Figure 1. Logic Diagram
Table 1. Signal Names
RFOUT Antenna Output Driv er
RFIN Antenna Input Filter
OSC1 Oscillator Input
OSC2 Oscillator Output
E0, E1, E2 Chip Enable Inputs
SDA I²C Bi-Directional Data
SCL I²C Clock
VCC Power Supply
GND Ground
VREF Transmitter Reference Voltage
GND_RF Ground for RF circuitry
ai12059
RFOUT
CR14
RFIN
OSC1
SCL
SDA
E0
E1
E2
GND GND_RF
VCC VREF
Antenna
OSC2
1 Summar y description CR14
8/46
Figure 2. Logic Block Diagram
Figure 3. SO Pin Connections
AI12060
RFOUT
CR14
RFIN
OSC1
SCL
SDA
E0
E1
E2
GND GND_RF
VCC VREF
Antenna
TransmitterReceiver
I²C Bus Controller
RAM Buffer
OSC2
1
AI10911
2
3
4
16
15
14
13
GND
E1 OSC2
OSC1
RFIN
VREF
GND_RFE0
SO16
5
6
7
8
12
11
10
9SDAGND SCL
GND_RF
E2
GND
RFOUT
VCC
CR14 2 Signal descri ption
9/46
2 Signal description
See Figure 1: Logic Diagram , and Table 1: Signal Names, for an overview of the signals
connected to this device.
2.1 Oscillator (OSC1, OSC2)
The OSC1 and OSC2 pins are internally connected to the on-chip oscillator circuit. The OSC1
pin is th e inpu t pin , the O SC2 is t he o ut put p i n. For correct operation of the CR14, it is req uir ed
to connect a 13.56MHz quartz crystal across OSC1 and OSC2. If an external clock is used, it
must be connected to OSC1 and OSC2 must be left open.
2.2 Antenna Output Driver (RFOUT)
The Antenna Output Driver pin, RFOUT, generates the modulated 13.56MHz signal on the
antenna. Care must be taken as it will not withstand a short-circuit.
RFOUT has to be connected to the antenna circuitry as shown in Figure 4: CR1 4 Application
Schematic The LRC antenn a circ uitr y must be conn e cte d across the RFOUT pin and GND.
2.3 Antenna Input Filter (RFIN)
The antenna inpu t filter of the CR14, RFIN, has to be connected to the e xternal antenna through
an adapter circuit, as shown in Figure 4.
The input filter demodulates the signal generated on the antenna by the lo ad variation of the
PICC. The resulting signal is then decoded by the 847kHz BPSK decoder.
2.4 Transmitter Reference Voltage (VREF)
The Transmitter Ref erence Voltage input, VREF, provides a reference voltage used by the output
driver for ASK modulation.
The Transmitter Reference Voltage input should be connected to an external capacitor, as
shown in Figure 4.
2.5 Serial Clock (SCL)
The SCL input pin is used to strobe all I²C data in and out of the CR14. In applications where
this line is used by slave devices t o synchronize the bus to a slower clock, the master must
have an open drain output, and a pull-up resistor must be connected from the Serial Clock
(SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated).
In most applications, thoug h, this me th od of synchronization is not employed , and so the pull-
up resistor is not necessary, provided that the master has a push-pull (rather than open drain)
output.
2 Signal description CR14
10/46
2.6 Serial Data (SDA)
The SDA signal is bi-directional. It is used to transfer I²C data in and out of the CR14. It is an
open drain output that ma y be wir e-OR’ed with other open drain or open collector signals on th e
bus. A pull-up resistor must be connected from Serial data (SDA) to VCC. (Figure 5 indicates
how the value of the pull-up resistor can be calculated).
2.7 Chip Enable (E0, E1, E2)
The Chip Enable inputs E0, E1, E2 are used to set and reset the value on the three least
significant bits (b3, b2, b1) of the 7-bit I²C Device Select Code. They are used for hardwired
addressing, allowing up to eight CR14 devices to be addressed on the same I²C bus. These
inputs may be driven dynamically or tied to VCC or GND to establish the Device Select Code
(note that th e V IL and VIH levels for the inputs are CMOS compatible, not TTL compatible).
When left open, E0, E1 and E2 are internally read at the logic level 0 due to the internal pull-
down resistors connected to each inputs.
2.8 Power Supply (VCC, GND, GND_RF)
Power is supplied to the CR14 using the VCC, GND and GND_RF pins.
VCC is the Power Supply pin that supplies the power (+5V) for all CR14 operations.
The GND and GND_RF pins are ground connections . They must be connected toge ther.
Decoupling capacitors should be connected between the VCC Supply Voltage pin, the GND
Ground pin and the GND_REF Gr ound pin to filter the power line, as shown in Figure 4.
Figure 4. CR14 Application Schematic
VREF
1 RFIN
2 E0
3 E1
4 E2
5 GND_RF
6 GND
7 GND
8 SDA 9
SCL 10
GND 11
OSC2 12
OSC1 13
GND_RF 14
RFOUT 15
VCC 16
U1
CR14
X1
13.56MHz
C1 7pF50V
C2 7pF50V
C3
22nF50V
C8
100pF50V
C8'
8pF50V
C7
120pF50V C7'
33pF50V
VCC
VCC
C6
100nF50V
+ C4
22uF 10V
FL4 0R
FL5 0R
FL6 0R
FL7
WURTH 742-792-042
R7
0R
R8
0R
R1
OPT ANT1
ANT2
E0 E1 E2
SCL SDA
1
2
3
4
J1
R2
0R
R3
OPT
R4
0R
R5
OPT
R6
0R
VCC
D1
1N4148 (OPTIONAL)
C5
10pF50V
AI12061
CR14 2 Signal descri ption
11/46
Figure 5. Maximum RL Value versus Bus Capacitance (CBUS) for an I²C Bus
AI01665
VCC
CBUS
SDA
RL
MASTER
RL
SCL CBUS
100
0
4
8
12
16
20
CBUS (pF)
Maximum RP value (kΩ)
10 1000
fc = 400kHz
fc = 100kHz
3 CR14 registers CR14
12/46
3 CR14 registers
The CR14 chip coupler contains six v o latile regist ers . It is entir ely controlled, at both dig ital and
analog level, using the three registers listed below an d shown in Table 2:
●Parameter Register
●Input/Output Frame Register
●Slot Marker Register
The other 3 reg isters are loca ted at addre sses 02h, 04h a nd 05h. They are “ST Reserve d”, and
must not be used in end-user applications.
In the I²C protocol, all data Bytes are tra nsmitted Most Significant Byte first, with each Byte
transmitted Most significant bit first.
Table 2. CR14 Control Registers
Address Length Access Purpose
00h Parameter Register 1 Byte W Set parameter register
R Read parameter register
01h Input/output Frame
Register 36 Bytes WStore and send request frame to the PICC .
Wait for PICC answer frame
R Transfer PICC answered fr ame data to Host
02h ST Reserv ed NA WST Reserved, must not be used.
R
03h Slot Marker Register 1 Byte WLaunch the automated anti-collision
process from Slot_0 to Slot_15
R Return data FFh
04h ST Reser ved NA R and W ST Reserved. Must not be used
05h ST Reser ved NA R and W ST Reserved. Must not be used
CR14 3 CR14 registers
13/46
3.1 Parameter Register (00h)
The Parameter Register is an 8-bit vo latile register used to conf igure the CR14, and thus, to
customiz e t he circui t behavior. The P ar a met er Re giste r is located at the I² C a ddress 00h and it
is accessib le in I²C Read and Write modes. Its default value, 00h, puts the CR14 in standard
ISO14443 type-B configuration.
Table 3. Parameter Register Bits Description
3.2 Input/Output Frame Register (01h)
The Input/Output Frame Register is a 36-Byte buffer that is accessed serially from Byte 0
through to Byte 35 (se e Table 4). It is located at the I²C address 01h.
The Input/Output Frame Register is the buffer in which the CR14 stores the data Bytes of the
request fr ame to be sent to the PICC . It au tomatically stores the data Bytes of the ans wer fr ame
received from the PICC. The first Byte (Byt e 0) of the Input/Output Frame Register is used to
store the frame length for both transmission and reception.
When accessed in I²C Write mode , the register stores the request frame Bytes that are t o be
transmitted to the PICC. Byte 0 must be set with the request frame length (in Bytes) and the
frame is stored from Byte 1 onwards. At the end of the transmission, the 16-bit CRC is
automatically added. After the transmission, the CR14 wait f o r the PICC to send back an
answer frame. When correctly decoded, the PICC answer frame Bytes are stored in the Input/
Output Frame Regist er from Byte 1 onw ards. Byte 0 stores the number of Byte s receiv ed from
the PICC.
When accessed in I²C Read mode, the Input/Output Register sends bac k the last PICC answer
frame Bytes, if any, with Byte 0 tr a nsmitte d f ir st. Th e 16- bit CRC is no t stor ed , and it is n ot sen t
back on the I²C bus.
Bit Control Value Description
b0Frame Standard 0 ISO14443 type-B frame management
1RFU(1)
1. RFU = Reserved for Future Use.
b1RFU 0 Not used
b2Answer Frame Format 0 Answer PICC Frames are delimited by SOF and EOF
1 Answer PICC Frames do not provide SOF and EOF delimiters
b3ASK Modulation Depth 0 10 % ASK modulation depth mode
1RFU
b4Carrier Frequency 0 13.56MHz carrier on RF OUT is OFF
1 13.56MHz carrier on RF OUT is ON
b5tWDG
Answer delay watchdog
b5=0, b6=0: Watchdog time-out = 500µs to be used for read
b5=0, b6=1: Watchdog time-out = 5ms to be used for read
b5=1, b6=0: Watchdog time-out = 10ms to be used for write
b5=1, b6=1: Watchdog time-out = 309ms to be used for MCU timings
b6
b7RFU 0 Not used
3 CR14 registers CR14
14/46
The Input/Out put Frame Register is set to all 00h between transmission and reception. I f there
is no answer from the PICC, Byte 0 is set to 00h. In the case of a CRC error, Byte 0 is set to
FFh, and the dat a Bytes are discarded and not appended in the registe r.
The CR14 Input/Output Frame Register is so designed as to generate all the ST short range
memory command frames. It can also generate all standardized ISO14443 type-B command
frames like REQB, SLOT-MARKER, ATTRIB, HALT, and get all the answers like ATQB, or
answer to ATTRIB. All ISO 14443 type-B compliant PICCs can be ac cessed by the CR14
prov ided that their data fr ame e xchange is not longer th an 35 Bytes in bo th request and ans w er.
Table 4. Input/Output Frame Register Des cription
3.3 Slot Marker Register (03h)
The slot Marke r Register is located at the I²C address 03h. It is used to trigger an automated
anti-collision sequence between the CR14 and any ST short range memory present in the
electromagnetic field. With one I²C access, the CR14 launches a complete stream of
commands starting from PCALL16(), SLOT_MARKER(1), SLOT_MARKER(2) up to
SLOT_MARKER(15), and stores all the identified Chip_IDs into the Input/Output Frame
Register (I²C address 01h).
This automated anti-collision sequence simplifies the host software development and reduces
the time needed to interrogate the 16 slots of the STMicroelectronics anti-collision mechanism.
When accessed in I²C Write mode , the Slot Mark er Registe r starts generating the sequence of
anti-collision commands. After each command, the CR14 wait for the ST short range memory
ans wer fr ame which contains the Chip_ ID. The v alidity of the ans w er is check ed and stor ed into
the corresponding Status Slot Bit (Byte 1 and Byte 2 as described in Table 6). If the answer is
correct, the Status Slot Bit is set to ‘1’ and the Chip_ID is stored into the corresponding
Slot_Register. If no answer is detected, the Status Slot Bit is set to ‘0’, and the corresponding
Slot_Register is set to 00 h. If a CRC error is detecte d, the Status Slot Bit is set to ‘0’, and the
corresponding Slot_Register is set to FFh.
Each time the Slot Marker Register is accesse d in I²C Write mode, Byte 0 of the Input/Output
Frame Register is set to 18, Bytes 1 and 2 provide Status Bits Slot information, and Bytes 3 to
18 store the corre sp o nd ing C hip _I D or er ro r co de.
The Slot Marker Register cannot be accessed in I²C Read mode. All the anti-collision data can
be accessed by reading the Input/Output Frame Register at the I²C address 01h.
Byte 0 Byte 1 Byte 2 Byte 3 ... Byte 34 Byte 35
Frame Length First data Byte Second data Byte Last data Byte
<------------- Request and Answer Frame Bytes exchanged on the RF ------------->
00h No Byte transmitted
FFh CRC Error
xxh Number of transmitted Bytes
CR14 3 CR14 registers
15/46
Table 5. Slot Marker Register Description
b7b6b5b4b3b2b1b0
Byte 0 Number of stored Bytes: fixed to 18
Byte 1 Status Slot
Bit 7 Status Slot
Bit 6 Status Slot
Bit 5 Status Slot
Bit 4 Status Slot
Bit 3 Status Slot
Bit 2 Status Slot
Bit 1 Status Slot
Bit 0
Byte 2 Status Slot
Bit 15 Status Slot
Bit 14 Status Slot
Bit 13 Status Slot
Bit 12 Status Slot
Bit 11 Status Slot
Bit 10 Status Slot
Bit 9 Status Slot
Bit 8
Byte 3 Slot_Register 0 = Chip_ID value detected in Slot 0
Byte 4 Slot_Register 1 = Chip_ID value detected in Slot 1
Byte 5 Slot_Register 2 = Chip_ID value detected in Slot 2
Byte 6 Slot_Register 3 = Chip_ID value detected in Slot 3
Byte n .....
Byte 17 Slot_Register 14 = Chip_ID value detected in Slot 14
Byte 18 Slot_Register 15 = Chip_ID value detected in Slot 15
Status bit value description:
1: No error detected. The Chip_ID stored in the Slot register is valid.
0: Error detected
– Slot register = 00h: No answer frame detected from ST short range memory
– Slot register = FFh: Answer Frame detected with CRC error. Collision may have occurred
4 CR14 I²C protocol description CR14
16/46
4 CR14 I²C protocol description
The CR14 is compatible with the I²C serial bus memory standard, which is a two-wire serial
interface that uses a bi-directional data bus and serial clock.
The CR14 has a pre-programmed, 4-bit identification code, ’1010’ (as shown in Table 6), that
corresponds to the I²C bus definition. With this code and the three Chip Enable inputs (E2, E1,
E0) up to eight CR14 devices can be connected to the I²C bus, and selecte d individually.
The CR14 beha ve s as a slav e de vice in the I²C prot ocol, with all CR14 operations synch ronized
to the ser ial clock.
I²C Read and Write operations are initiated by a START condition, generated by the bus
master.
The START co ndition is f ollo we d b y the De vice Select Co de and b y a Read/Write bit (R /W). It is
terminated by an acknowledge bit. The Device Select Code consists of seven bits (as shown in
Table 6):
●the Device Code (first four bits)
●plus three bits correspon ding to the states of the th ree Chip Enab le inputs , E2, E1 and E0,
respectively
When data is written to the CR14, the device inserts an acknowledge bit (9th bit) after the bus
master’s 8-bit transmission.
When the b us mast er reads data , it also ac kno wledge s the receipt of the data Byte b y inserting
an acknowledge bit (9th bit).
Data tr ansf er s are terminated b y a STOP condition a fter an ACK f or Write , or afte r a NoACK for
Read.
The CR14 supports the I²C protocol, as summarized in Figure 6.
Any device that sends data on to the b us , is define d as a transmit ter, and any device that reads
the data, as a receiver.
The device that controls the data transf er is known as the master, and the other, as the sla v e. A
data transfer can only be initiated by the master, which also provides the serial clock f or
synchronization. The CR14 is always a slave device in all I²C communications. All data are
transmitted Most Significant Bit (MSB) first.
Table 6. Device Select Code
Device Code Chip Enable RW
b7 b6 b5 b4 b3 b2 b1 b0
CR14 Select 1 0 1 0 E2 E1 E0 RW
CR14 4 CR14 I²C protocol description
17/46
4.1 I²C Start Condition
START is identified by a High-to-Low transition of the Serial Data line, SDA, while the Serial
Clock, SCL, is stable in the High state . A START condition must precede any data transfer
command.
The CR14 continuously monitors the SDA and SCL lines for a START condition (except during
Radio Frequency data exchanges), and will not respond unless one is sent.
4.2 I²C Stop Condition
STOP is identified by a Low-to-High transition of the Serial Data line, SDA, while the Serial
Clock, SCL, is stable in the High state.
A STOP condition terminates co mmunications between the CR14 and the bus master.
A STOP condition at the end of an I²C Read command, after (and only after) a NoACK, forces
the CR14 into its stand-by state.
A STOP condition at the end of an I²C Write command triggers the Radio Frequency data
exchange between the CR14 and the PICC.
4.3 I²C Acknowledge Bit (ACK)
An acknowledge bit is used to indicate a successful data transfer on the I²C bus.
The bus transmitter, either master or slave, releases the Serial Data line, SDA, after sending 8
bits of data. During the 9th clock pulse the receiver pulls the SDA line Low to acknowledge the
receipt of the 8 data bits.
4.4 I²C Data Input
During data input, the CR1 4 samples the SDA bus signal on the rising edge of the Serial Cloc k,
SCL. F or correct de vice ope ration, the SD A signa l must be stab le during the Low- to-High Serial
Clock transition, and the data must change only when the SCL line is Low
4 CR14 I²C protocol description CR14
18/46
Figure 6. I²C Bus Protocol
4.5 I²C Memory Addressing
To start up communication with the CR14, the bus master must initiate a START condition.
Then, the bus master sends 8 bits (with the mo st signif ica nt bit first) on th e Serial Data line,
SDA. These bits consist of the Device Select Code (7 bits) plus a RW bit.
According to the I²C bus definition, the seve n most significant bits of the Device Select Code
are the Device Type Identifier. For the CR14, these bits are defined as shown in Table 6.
The 8th bit is the Read/Write bit (RW). It is set to ‘1’ for I²C Read, and to ‘0’ for I²C Write
operations.
If the data sent by the bus master matches the Device Select Code of a CR14 device, the
corresponding device returns an acknowledg ment on the SDA bus during the 9th bit time.
The CR14 devices whose Device Select Codes do not correspond to the data sent, gener ate a
No-ACK. They deselect themselves from the bus and go into stand-by mode.
SCL
SDA
SCL
SDA
SDA
START
CONDITION SDA
INPUT SDA
CHANGE
AI00792
STOP
CONDITION
123 789
MSB ACK
START
CONDITION
SCL 123 789
MSB ACK
STOP
CONDITION
CR14 4 CR14 I²C protocol description
19/46
4.6 CR14 I²C Write Operations
The bus master sends a START condition, followed by a Device Select Code and the R/W bit
set to ’0’. The CR14 that correspond s to the Device Select Code, acknowledges and waits for
the bus master to send the Byte address of the register that is to be written to. After receipt of
the address, the CR14 returns anothe r ACK, and w aits for the bus master to send the data
Bytes that are to be written.
In the CR14 I²C Write mode, the bus master may sends one or more data Bytes depending on
the selected register.
The CR14 replies with an ACK after each data Byte received. The bus master terminates the
transfer by generating a STOP cond itio n.
The STOP condition at the end of a Write access to the Input/Output Frame Register causes
the Radio Frequency data exchange between the CR14 and the PICC to be started.
During the Radio Frequency data exchan ge, the CR14 disconnects itself from the I²C bus. The
time (tRFEX) needed to complete the e xchange is no t fix ed as it depends on the PICC command
format. To know when the exchange is complete, the bus master uses an ACK polling
sequence as shown in Figure 8. It consists of the following:
●Initial condition: a Radio Frequency data exchange is in progress.
●Step 1: the master issues a START condition followed by the first Byte of the new
instru ction (D evice Select Code plus R/W bit).
●Step 2: if the CR14 is b usy, no ACK is returned and the master goes bac k to Step 1. If th e
CR14 has completed the Radio Frequency data exchange, it responds with an ACK,
indicating that it is rea dy to rece ive the second part of the next inst ruction (the first Byt e of
this instruction being sent during Step 1).
Figure 7. CR14 I²C Write Mode Sequence
AI12062
STOP
DATA N
ACK ACK
START
CR14 WRITE
DEV SEL BYTE ADDR DATA 1 DATA 2 DATA 3
ACK ACK ACK ACK
R/W
BUS Master
BUS Slave
4 CR14 I²C protocol description CR14
20/46
Figure 8. I²C Polling Flowchart using ACK
Radio Frequency
data exchange
in progress
START Condition
DEVICE SELECT
CODE with R/W=1
ACK
returned
Next
operation is
addressing
the CR14
ReSTART
STOP STOP
Proceed to READ
Operation
YES
NO
First byte of instruction
with R/W = 1 already
decoded by the CR14
NO YES
ai12063
CR14 4 CR14 I²C protocol description
21/46
4.7 CR14 I²C Read Operations
To send a Read command, the bus master sends a START condition, followed by a Device
Select Code and the R/W bit set to ’1’.
The CR14 that corre sponds to the Device Select Code ac kno wledges and outpu ts the first dat a
Byte of the addre ssed register.
To select a specific register, a dummy Write command must first be issued, giving an address
Byte but no data Bytes, as shown in the bottom half of Figure 9. This causes the new address
to be stored in the internal address pointer, f or use by the Read command that immediately
follows the dummy Write command.
In the I²C Read mode, the CR14 may read one or more data Bytes depending on the selected
register. The bus master has to generate an ACK after each data Byte to read all the register
data in a continuous stream. Only the last data Byte should not be followed by an ACK. The
master then terminates the transfer with a STOP condition, as shown in Figure 9.
After reading each Byte, the CR14 waits for the master to send an ACK during the 9th bit time.
If the master does not return an ACK within this time, the CR14 terminates the da ta transfer
and switches to stand-by mode.
Figure 9. CR14 I²C Read Modes Sequences
START
CR14 READ
DEV SEL
DATA 1 DATA 2 DATA 3
AI12064
STOP
DATA N
ACK
ACK ACK
R/W ACK NoACK
BUS Master
BUS Slave
ACK
DATA 4
START
CR14 READ
DEV SEL ADDRESS
ACK
BUS Master
BUS Slave
R/W
ACK
DEV SEL
DATA 1
STOP
DATA N
ACK
ACK
R/W ACK NoACK
DATA 2
Re-START
I²C CURRENT ADDRESS READ
I²C RANDOM ADDRESS READ
5 Applying the I²C protocol to the CR14 registers CR14
22/46
5 Applying the I²C protocol to the CR14 registers
5.1 I²C Parameter Register Protocol
Figure 10 shows how new data is written to the Parameter Register. The new value becomes
active after the I²C STOP condition.
Figure 11 shows how to read th e Param eter Register contents. The CR14 sends and re-sends
the Parameter Register contents until it receives a NoAC K from the I²C Host.
The CR14 supports the I²C Current Address and Random Address Read modes. The Current
Address Read m ode can be used if t he pre vious command w as issued to th e register where th e
Read is to take place.
Figure 10. Host-to-CR14 Transfer: I²C Write to Parameter Registe r
Figure 11. CR14-to- Hos t Transfer: I²C Random Address Read from Parameter Register
Figure 12. CR14-to-Host Transfer: I²C Current Address Read fr om Parameter Register
S
T
A
R
T
1010XXX 00h data
S
T
O
P
ACK
ACKACK
Register Byte
Value
Parameter Register
Address
Device Select
Code
Bus Master
CR14 Write
Bus Slave
ai12038
R/W
S
T
A
R
T
1010XXX 00h data
S
T
O
P
ACK
ACK
ACK Register Byte
Value
Parameter Register
Address
Device Select
Code
Bus Master
CR14 Read
Bus Slave
ai12039
R
E
S
T
A
R
T
1010XXX
R/W
Device Select
Code
R/W NoACK
data
S
T
O
P
ACK
Register Byte
Value
Bus Master
CR14 Read
Bus Slave
ai12040
S
T
A
R
T
1010XXX
Device Select
Code
R/W NoACK
CR14 5 Applying the I²C protocol to the CR14 registers
23/46
5.2 I²C Input/Output Frame Register Protocol
Figure 13 sho ws ho w to store a PICC request f rame com mand of N Bytes into the Input/Output
Frame Register.
After the I²C STOP condition, the request frame is RF transmitted in the IS O14443 type-B
format. The CR14 then waits for the PICC answer frame which will also be stored in the Input/
Output Frame Register. The request frame is over-written by the answer frame.
Figure 14 shows how to read an N-Byte PICC answer frame.
The two CRC Bytes generated by the PICC are not stored.
The CR14 continu es to output data Bytes until a NoACK has been generated by the I²C Host,
and received by the CR14. After all 36 Bytes have been output, the CR14 “rolls over”, and
starts outputting from the start of the Input/Output Frame Register again.
The CR14 supports the I²C Current Address and Random Address Read modes. The Current
Address Read m ode can be used if t he pre vious command w as issued to th e register where th e
Read is to take place.
Figure 13. Host-to-CR14 Transfer: I²C Write to Input/Output Frame Register for ISO14443B
Figure 14. CR14-to- Hos t Transfer: I²C Random Address Read from Input/Output Frame
Register for ISO14443B
S
T
A
R
T
1 0 1 0 XXX 01h N
S
T
O
P
ACK
ACKACK
Request Frame
Length N
Input/Output
Register
Address
Device
Select
Code
Bus
Master
CR14
Write
Bus
Slave
ai12041
R/W
Data 1 Data 2
PICC
Command
Parameter
PICC
Command
Code
Data N
PICC
Command
Parameter
PICC
Command
Parameter
ACK
ACKACKACK
S
T
A
R
T
1010XXX 01h N
S
T
O
P
ACK
ACKACK Received
Frame
Length
Input/Output
Register
Address
Device
Select
Code
Bus
Master
CR14
Read
Bus
Slave
ai12042
R/W
Data1 Data 2
Answer
Frame
Data
Answer
Frame
Data
Data N
Answer
Frame
Data
Answer
Frame
Data
NoACK
ACKACKACK
R
E
S
T
A
R
T
101 0XXX
Device
Select
Code
R/W
ACK
5 Applying the I²C protocol to the CR14 registers CR14
24/46
Figure 15. CR14-to-Host Transfer: I² C Cur r ent Address Read from I/O Frame Register
for ISO14443B
5.3 I²C Slot Marker Register Protocol
An I²C Write command to the Slot Marker Register generates an automated sixteen-command
loop (See Figure 16 for a description of the command).
All the answers from the ST short range me mory devices that are detected, are written in the
Input/Output Frame Register.
Read from the I²C Slot Marker Register is not supported by the CR14. If the I²C Host tries to
read the Slot Marker Register , the CR14 will return the data v alue FFh in both Random Address
and Current Address Read modes until NoACK is generated by the I²C Host.
The result of the det ection sequence is stored in the Input/Output Frame Register. This
Register can be read by the host by using I²C Random Address Read.
Figure 16. Host-t o-CR14 Transfer: I²C Write to Slot Marker Register
S
T
A
R
T
1010XXX N
S
T
O
P
ACK
ACK
Answer Frame
Data
Device
Select
Code
Bus Master
CR14 Write
Bus Slave
ai12043
R/W
Data 1 Data 2
Answer Frame
Data
Answer Frame
Data
Data N
Answer Frame
Data
Received
Frame Length
ACKACK NoACKACK
03h
S
T
O
P
ACK
Slot Marker
Register
Address
Bus Master
CR14 Write
Bus Slave
ai12044
S
T
A
R
T
1010XXX
Device Select
Code
R/W
ACK
CR14 5 Applying the I²C protocol to the CR14 registers
25/46
Figure 17. CR14-to-Host Transfer: I²C Random Ad dress Read from Slot Marker Registe r
Figure 18. CR14-to-Host Transfer: I²C Curr ent Address Read from Slot Marker Register
5.4 Addresses above Location 06h
In I²C Write mode, when the CR14 receives the 8-bit register address, and the address is abov e
location 06h, the d evice does not ac kno wledge ( NoACK) and deselects itself from the bus. The
Serial Data line, SDA, stays at logic ‘1’ (pull-up resistor), and the I²C Host receives a NoACK
during the 9th bit time. The SDA line stays High until the STOP condition is issued.
In the I²C Current and Random Address Read modes, when the CR14 receiv es the 8-bit
register address, and the address is above location 06h, the device does not acknowledge the
Device Select Code after the START condition, and deselects itself from the bus.
S
T
A
R
T
1010XXX 00h FFh
S
T
O
P
ACK
ACK
ACK
Slot Marker
Register
Address
Device Select
Code
Bus Master
CR14 Read
Bus Slave
ai12045
R
E
S
T
A
R
T
1010XXX
R/W
Device Select
Code
R/W NoACK
FFh
S
T
O
P
ACK
Bus Master
CR14 Read
Bus Slave
ai12047
S
T
A
R
T
1010XXX
Device Select
Code
R/W NoACK
6 CR14 ISO14443 type-B Radio Frequency data transfer CR14
26/46
6 CR14 ISO14443 type-B Radio Frequency data
transfer
6.1 Output RF Data Transfer from the CR14 to the PICC (Request
Frame)
The CR14 output buffer is controlled by the 13.56MHz clock signal generated by the external
oscillator and by the request frame generator. The CR14 can be directly connected to an
external matching circuit to generate a 13.56MHz sinusoidal carrier frequency on its antenna.
The current driv en into the a ntenna co il is directly ge nerat ed b y the CR14 RFOUT o utput driv er.
If the ante nna is correctly tuned, it emits an H-field of a large enough magnitude to power a
contactless PICC f rom a short distance. The energy r eceived on th e PICC antenna is con verted
to a Power Supply Voltage by a regulator, and turned into data bits by the ASK demodulator.
The CR14 amplitude mod ulates the 13.56MHz w ave by 10% as represented in Figure 19. The
data transfer rate is 106 kbit/s.
Figure 19. Wave Transmitted using ASK Modulation
DATA BIT TRANSMITTED
BY THE CR14
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED BY THE RFOUT
DRIVER
Transfer time for one data bit is 1/106 kHz AI12048
10% ASK MODULATION
OF THE 13.56MHz WAVE,
GENERATED ON THE CR14
ANTENNA
CR14 6 CR14 ISO14443 type-B Radio Frequency data transfer
27/46
6.2 Tr ansmission Format of Request Frame Characters
The CR14 transmit s charact ers of 10 bits , wit h the Least Sign ificant Bit (b 0) transmitted first, as
shown in Figure 20.
Several 10-bit characters, preceded by the Start Of Frame (SOF) and followed by the End Of
Frame (EOF), constitute a Request Frame, as shown in Figure 26.
A Request Frame includes the SOF, instructions, addresses, data, CRC and the EOF as
defined in the ISO14443 type-B.
Each bit duration is called an Elementary Time Unit (ETU). One ETU is equal to 9.44µs (1/
106kHz).
Figure 20. CR14 Request Frame Character Format
Table 7. CR14 Request Frame Character Format
6.3 Request Start Of Frame
The Start Of Frame (SOF) de scribed in Figure 21 consists of:
●a falling edge,
●followed by ten Elementary Time Units (ETU) each containin g a logical ‘0’
●followed by a sing le rising edge
●followed by two ETUs, each containing a logical ‘1’.
Figure 21. Request Start Of Frame
Bit Description Value
b0Start bit used to synchronize the transmission b0 = 0
b1 to b8Information Byte (instruction, address or data) Information Byte is sent Least
Significant Bit first
b9Stop bit used to indicate the end of the character b9 = 1
1
ETU Start
'0' LSB MSB Stop
'1'
Information Byte
b0 b1 b2 b3 b4 b5 b6 b7 b8 b9
ai12049
b0b1b2b3b4b5b6b7b8b9b10 b11
ETU000000000011
ai12050
6 CR14 ISO14443 type-B Radio Frequency data transfer CR14
28/46
6.4 Request End Of Frame
The End Of Frame (EOF) shown in Figure 22 consists of:
●a falling edge,
●followed by ten Elementary Time Units (ETU) containing each a logical ‘0’,
●followed by a sing le rising edge.
Figure 22. Request End Of Frame
6.5 Input RF Data Transfer from the PICC to the CR14 (Answer
Frame)
The CR14 uses the ISO14443 type-B retro-modulation scheme which is demod ula te d an d
decoded by the RFIN circuitry.
The modulation is obtained by modifying the PICC current consumption (load modulation). This
load modulation induces an H-field variation, by coupling, that is detected by the CR14 RFIN
input as a voltage variation on the ant enna. The RFIN input demodulates this variation and
decodes the information received from the PICC.
Data must be transmitted using a 847kHz, BPSK modulated sub-carrier frequency, fS, as
shown in Figure 23, and as specified in ISO14443 type-B. In BPSK, all data state transitions
(from ‘0’ to ‘1’ or from ‘1’ to ‘0’) are encoded by phase shift keying the sub-carrier.
Figure 23. Wave Received using BPSK Sub-carrier Modulation
b0b1b2b3b4b5b6b7b8b9
ETU0000000000
ai09252
VDYN
VRFIN
t
VOFFSET
1/106kHz
1/847kHz
phase shift
VRET
Load modulation effect on
the H-Field received on the
CR14 RFIN input pad
PICC data bit to be transmitted
to the CR14.
847kHz BPSK, resulting signal
generated by the PICC for the
load modulation.
ai12051
CR14 6 CR14 ISO14443 type-B Radio Frequency data transfer
29/46
6.6 Tr ansmission Format of Answer Frame Characters
The PICC should use the same character format as that used for output data tr ansfer (see
Figure 20).
An Answer Frame includes the SOF, data, CRC and the EOF, as illustrated in Figure 26. The
data transfer rate is 106 kbit/s.
The CR14 will also accept Answer Frames that do not contain the SOF and EOF delimiters,
provided that these Frames are correctly set in the Parameter Register. (See Figure 26).
6.7 Answer Start Of Frame
The PICC SOF must be compliant with the ISO1 4443 type-B, and is sho wn in Figure 24
●Ten or eleven Elementary Time Units (ETU) each containing a logical ‘0’,
●Two ETUs containing a logical ‘1’.
Figure 24. Answer Start Of Frame
6.8 Answer End Of Frame
The PICC EOF must be compliant with the ISO1 4443 type-B, and is sho wn in Figure 25:
●Ten or eleven Elementary Time Units (ETU) each containing a logical ‘0’,
●Two ETUs containing a logical ‘1’
Figure 25. Answer End Of Fram e
b0b1b2b3b4b5b6b7b8b9b10 b11
ETU000000000011
ai09254
b12
1
b0b1b2b3b4b5b6b7b8b9b10 b11
ETU000000000011
ai09254
b12
1
6 CR14 ISO14443 type-B Radio Frequency data transfer CR14
30/46
6.9 Transmission Frame
The Request Frame transmission must be followed by a minimum delay, t0 (see Table 13), in
which no ASK or BPSK modulation occurs, before the Answer Frame can be transmitted. t0 is
the minimu m ti me required by the CR14 to switch from transmission mode to reception mode,
and should be inserted after each fr ame . Aft er t0, the 13.56MHz carrier frequency is mo dulated
by the PICC at 847kHz for a minimum time of t1 (see Table 13) to allow the CR14 to
synchronize. After t1, the first phase transition generated by the PICC represents the start bit
(‘0’) of the Answer SOF (or the start bit ‘0’ of the first data character in non SOF/EOF mode).
Figure 26. Example of a Complete Transmission Frame
6.10 CRC
The 16-bit CRC used by the CR14 follows the ISO14443 type B recommendation. For further
information, please see Appendix A on page 44.
The two CRC Bytes are present in all Request and Answer Frames, just before the EOF. The
CRC is calculated on all the Bytes between the SOF and the CRC Bytes.
Upon tr ansmission of a Request fro m the CR14, the PICC v erifies that the CRC v alue is v alid. If
it is invalid, it discards the frame and does not answer the CR14.
Upon reception of an Answer from the PICC, the CR14 verifies that the CRC value is valid. If it
is invalid, it stores the value FFh in the Input/Output Frame Register.
The CRC is transmitted Least Significant Byte first. Each Byte is transmitted Least Significant
Bit first.
Figure 27. CRC Transmission Rules
SOF Cmd Data CRC CRC EOF
12 bits
at 106Kb/s 10 bits 10 bits10 bits 10 bits 10 bits
Sent by
the CR14
t0
64/fs Min t1
80/fs Min
Sync
fs = 847.5kHz
SOF Data CRC CRC EOF
12 or 13
bits 10 bits 12 or 13
bits
10 bits 10 bits
tWDG
Case of Answer Frame with SOF & EOF
Sent by the PICC
Sync Data Data CRC
tWDG
Case of Answer Frame without SOF & EOF Data CRC
t0
64/fs Min t1
80/fs Min 10 bits 10 bits 10 bits10 bits 10 bits
Output Data Transfer using ASK Modulation Input Data Transfer using 847kHz BPSK Modulation
ai12052
tDR
LSByte MSByte
CRC 16 (8 bits) CRC 16 (8 bits)
LSBit MSBit LSBit MSBit
ai09256
CR14 7 Tag access using the CR14 coupler
31/46
7 Tag access using the CR14 coupler
In all the following I²C comma nds , the last three bits of the Device Select Code ca n be replaced
by any of the thre e-bit binary values (000, 001 , 010, 011, 100, 101, 110, 11 1). These v alues are
linked to the logic levels applied to the E2, E1 and E0 pads of the CR14.
7.1 Standard TAG Command Access Description
Standard PICC comma nds, like Read and Write, are generated by the CR14 using the Input/
Output Frame Register.
When the host needs to send a standard frame command to the PICC, it first has to internally
generate the complete frame, with the command code followed by the command parameters.
Only the tw o CRC Bytes should not be g enerated, as the CR14 automatica lly adds them during
the RF transmission.
When the frame is ready, the host has to write the request frame into the Input/Output Frame
Register using the I²C write command specified in Figure 13 on page 23. After the I²C STOP
condition, th e CR14 inserts the I²C Bytes in the r equire d I SO ch ar a cter format ( Figure 20) and
starts to transmit the request frame to the PICC. Once the RF transmission is over, the CR14
waits for the PICC to send an answer frame.
If the PICC ans wers, the char acters receiv ed (Figure 26) are demodulated, deco ded and stored
into the Inpu t/Output Frame Register, as specified in Table 4. During the entire RF
transmission, the CR14 disconnects itself from the I²C bus . On reception of the PICC EOF, the
CR14 chec ks the CRC and reconnects itself t o the I²C bus.
The host can then ge t the PICC ans w er fr ame by issuing an Input/ Output Frame Registe r Read
on the I²C bus, as specified in Figures 14 and 15.
If no answer from the PICC is detected after a time-out delay, fixed in the Parameter Register
(bits b5 and b6), the Input/Output Frame Register is set as specified in Table 4.
Figure 28. Stan dard TAG Command: Request Fr ame Transmission
S
T
A
R
T
Device
Select
Code
Input/
Output
Register
Address
Request
Frame
Length
TAG
Cmd
Code Param Param Param S
T
O
P
SOF EOFData 1 DataData 2 Data N CRC CRC
CR14
SOF TAG
Cmd
Code Param Param Param SR14
EOF
CRC CRC
I²C
RF
ai12053
Data 1 DataData 2 Data N01h N
7 Tag access using the CR14 coupler CR14
32/46
Figure 29. St andard TAG Command: Answer Frame Reception
Figure 30. Stan dard TAG Command: Complete TAG Access Description
7.2 Anti-Collision TAG Sequence
The CR14 can identify an ST short range memory using a proprietary anti-collision system.
Issuing an I²C Write command to the Slot Marker Register (Figure 16) causes the CR14 TO
automatically generate a 16-slot anti-collision sequence, and to store the identified Chip_ID in
the Input/Output Frame Register, as specified in Table 5.
After receiving the Slot Marker Register I²C Write command, the CR14 generates an RF
PCALL16 command followed by fifteen SLOT_MARKER commands, from SLOT_MARKER(1)
to SLOT_MARKER(15). After e ach command, the CR14 w aits for a tag ans w er. If the answer is
correctly decoded, the corresponding Chip_ID is stored in the Input/Output Frame Register. If
there is no answer, or if the answer is wrong (with a CRC error, for example), the CR14 stores
an error code i n the Input/Output Frame Register. At the end of the sequence, the host has to
read the Input/Output Frame Register to retrieve all the identified Chip_IDs.
S
T
A
R
T
Device
Select
Code
Input/
Output
Register
Address
Answer
Frame
Length TAG
Data
S
T
O
P
SOF EOFData 1 DataData 2 Data P CRC CRC
TAG
SOF TAG
Data TAG
Data TAG
Data TAG
Data TAG
EOF
TAG
CRC TAG
CRC
I²C
RF
ai09261
Data 1 DataData 2 Data P01h P
TAG
Data TAG
Data TAG
Data
Device
Select
Code
Write
I/O
Register
Address
Request
Frame
Length
Request
Frame
Bytes
I²C
START STOP
CRC
Request
Frame
Characters
SOF EOF
CRC
TAG
Answer Frame
Characters
SOF EOF
T0
<--> T1
<-->
Device
Select
Code
Read
Answer
Frame
Length
Request
Frame
Bytes
START STOP
RF
ai09262
CR14 7 Tag access using the CR14 coupler
33/46
Figure 31. Anti-Collision ST short range memory Sequence (1)
03hI²C
S
T
A
R
T
Device
Select
Code
Slot
Marker
Register
Address
S
T
O
P
SOFSlot 0 06h 04h CRC CRC EOF SOF
t0
<--> t1
<--> Chip_ID CRC CRC EOF
CR14
SOF PCALL 16 TAG
Command CRC CRC CR14
EOF TAG
SOF TAG
Chip_ID TAG
CRC TAG
CRC TAG
EOF
RF
I²C
SOFSlot 1 16h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
I²C
SOFSlot 2 26h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
I²C
SOFSlot 3 36h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
I²C
SOFSlot 4 46h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
I²C
SOFSlot 5 56h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
I²C
SOFSlot 6 66h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
I²C
SOFSlot 7 76h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
I²C
SOFSlot 8 86h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
I²C
SOFSlot 9 96h CRC CRC EOF SOFt0
<--> t1
<--> Chip_ID CRC CRC EOFRF...
CR14
SOF Slot Marker
Command CRC CRC CR14
EOF TAG
SOF TAG
Chip_ID TAG
CRC TAG
CRC TAG
EOF
ai12054
7 Tag access using the CR14 coupler CR14
34/46
Figure 32. Anti-Collision ST short range memory Sequence Continued
I²C
SOFSlot 10 96h CRC CRC EOF SOF
t0
<--> t1
<-->
Chip_ID CRC CRC EOFRF ...
I²C
SOFSlot 11 56h CRC CRC EOF SOF
t0
<--> t1
<-->
Chip_ID CRC CRC EOFRF ...
I²C
SOFSlot 12 66h CRC CRC EOF SOF
t0
<--> t1
<-->
Chip_ID CRC CRC EOF
RF ...
I²C
SOFSlot 13 76h CRC CRC EOF SOF
t0
<--> t1
<-->
Chip_ID CRC CRC EOFRF ...
I²C
SOFSlot 14 86h CRC CRC EOF SOF
t0
<--> t1
<-->
Chip_ID CRC CRC EOF
RF ...
I²C
SOFSlot 15 96h CRC CRC EOF SOF
t0
<--> t1
<-->
Chip_ID CRC CRC EOF
RF ...
01h
I²C ...
S
T
A
R
T
Device
Select
Code
I/O
Register
Address
R
E
S
T
A
R
T
Device
Select
Code
Answer
Frame
Length
Slot 0
Chip_ID
Answer
Status12h Status Chip_ID Chip_IDChip_ID Chip_ID Chip_ID Chip_IDChip_ID Chip_ID Chip_ID
Status
Slot Bits
b0 to b7
Status
Slot Bits
b8 to b15
Slot 1
Chip_ID
Answer
Slot 2
Chip_ID
Answer
Slot 3
Chip_ID
Answer
Slot 4
Chip_ID
Answer
Slot 5
Chip_ID
Answer
Slot 6
Chip_ID
Answer
Slot 7
Chip_ID
Answer
Slot 8
Chip_ID
Answer
RF
I²C ... Chip_IDChip_ID Chip_ID Chip_ID Chip_IDChip_ID Chip_ID
RF ai09264
Slot 9
Chip_ID
Answer
Slot 10
Chip_ID
Answer
Slot 11
Chip_ID
Answer
Slot 12
Chip_ID
Answer
Slot 13
Chip_ID
Answer
Slot 14
Chip_ID
Answer
Slot 15
Chip_ID
Answer
S
T
O
P
CR14 8 Maximum rating
35/46
8 Maximum rating
Stressing the device above the rating listed in the Absolute Maxim um Rat ing s table may cause
permanent damage to the device. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. These are stress ratings only and operation of
the device at these or any other condit ions above those indicated in the Operating sections of
this specification is not implied. Refer also to the STMicroelectronics SURE Program and other
relevant quality do cuments.
Table 8. Absolute Maximum Ratings
Symbol Parameter Value Unit
TSTG Storage Temperature –65 to 150 °C
VIO Input or Output range (SDA) –0.3 to 6.5 V
VIO Input or Output range (others pads) –0.3 to Vcc+0.3 V
VCC Supply Voltage –0.3 to 6.5 V
POUT Output Power on Antenna Output Driver (RFOUT)100 mW
VESD Electrostatic Discharge Voltage (Human Body model) (1)
1. MIL-STD-883C, 3015.7 (100pF, 1500Ω).
4000 V
Electrostatic Discharge Voltage (Machine model) (2)
2. EIAJ IC-121 (Condition C) (200pF, 0Ω)
500 V
9 DC and AC parameters CR14
36/46
9 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the de vice . The par ameters in th e DC and A C Cha racteristic tab les that f ollow
are derived from tests performed under the Measurement Conditions summarized in the
relevant tables. Designers should check that the operating conditions in their circuit mat ch the
measurement conditions when relying on the quoted parameters.
Table 9. I²C AC Measurement Conditions
Figure 33. I²C AC Testing I/ O Waveform
Table 10. I²C Input Parameters(1,2)
1. Sampled only, not 100% tested.
2. TA = 25 °C, f = 400kHz.
Parameter Min. Max. Unit
VCC Supply Voltage 4.5 5.5 V
Ambient Operating Temperature (TA)–20 85 °C
Input Rise and Fall Times 50 ns
Input Pulse Voltages 0.2VCC 0.8VCC V
Input and Output Timing Reference Voltages 0.3VCC 0.7VCC V
Symbol Parameter Test Condition Min. Max. Unit
CIN Input Capacitance (SDA) 8 pF
CIN Input Capacitance (SCL, E0, E1, E2)) 6 pF
tNS Low Pass Filter Input Time Constant (SCL & SDA
Inputs) 100 400 ns
AI09235
0.8VCC
0.2VCC
0.7VCC
0.3VCC
CR14 9 DC and AC parameters
37/46
Table 11. I²C DC Characteri stics
Symbol Parameter Test Condition Min. Max. Unit
ILI Input Leakage Current
(SCL, SDA, E0, E1, E2) 0V ≤ VIN ≤ VCC ±2 µA
ILO Output Leakage Current
(SCL, SDA, E0, E1, E2) 0V ≤ VOUT ≤ VCC, SDA in Hi-Z ±2 µA
ICC Supply Current
VCC = 5V, fC = 400kHz
(rise/fall time < 30ns), RF OFF 6mA
VCC = 5V, fC = 400kHz (rise/fall time <
30ns), RF ON 20 mA
ICC1 Supply Current (Stand-by) VIN = VSS or VCC, VCC = 5V, RF OFF 5mA
VIL
Input Low Voltag e (SCL,
SDA) –0.3 0.3VCC V
Input Low Voltage (E0, E1,
E2) –0.3 0.3VCC V
VIH
Input High Voltage (SCL,
SDA) 0.7VCC VCC + 1 V
Input High Voltage (E0, E1,
E2) 0.7VCC VCC + 1 V
VOL Output Low Voltage (SDA) IOL = 3mA, VCC = 5V 0.4 V
9 DC and AC parameters CR14
38/46
Figure 34. I²C AC Waveforms
tCHCL CLCH
tDLCL
tCHDX
START
CONDITION
tDXCX
tCLDX
tCHDH
tDHDL
SDA
INPUT SDA
CHANGE STOP &
BUS FREE
SCL
SDA IN
SCL
SDA OUT DATA VALID
tCLQV tCLQX
DATA OUTPUT
SCL
SDA IN
tCHDH
tRFEX
tCHDX
STOP
CONDITION CR14 command execution START
CONDITION ai12055
CR14 9 DC and AC parameters
39/46
Table 12. I²C AC Characteristics
Symbol Alt. Parameter
Fast I²C
400 kHz I²C
100 kHz Unit
Min Max Min Max
tCH1CH2(1)
1. Sampled only, not 100% tested.
tRClock Rise Time 300 1000 ns
tCL1CL2(1) tFClock Fall Time 300 300 ns
tDH1DH2(1) tRSDA Rise Time 20 300 20 1000 ns
tDL1DL2(1) tFSDA Fall Time 20 300 20 300 ns
tCHDX (2)
2. For a reSTART condition, or following a write cycle.
tSU:STA Clock High to Input Transition 600 4700 ns
tCHCL tHIGH Clock Pulse Width High 600 4000 ns
tDLCL tHD:STA Input Low to Cloc k Lo w (START) 600 4000 ns
tCLDX tHD:DAT Clock Low to Input Transition 0 0 µs
tCLCH tLOW Clock Pulse Width Low 1.3 4.7 µs
tDXCX tSU:DAT Input Transition to Clock Transition 100 250 ns
tCHDH tSU:STO Clock High to Input High (STOP) 600 4000 ns
tDHDL tBUF Input High to Input Low (Bus Free) 1.3 4.7 µs
tCLQV tAA Clock Low to Data Out Valid 1000 3500 ns
tCLQX tDH Data Out Hold Time After Clock Low 200 200 ns
fCfSCL Clock Frequency 400 100 k Hz
9 DC and AC parameters CR14
40/46
Figure 35. CR14 Synchronous Timing
tRFSBL
tRFF
tRFR
BA
tPOR
VRFOUT
fCC
RFOUT ASK Modulated Signal
1 0 1 EOFDATA FRAME transmitted by the CR14 in ASK
847kHz SOF 1 1 0 DATA 1 0 DATA 1 0
FRAME transmitted by the PICC in BPSK
tDR tDR
t0t1tDA tDA
0
START tRFSBL
tRFSBL tRFSBL
tRFSBL
tRFSBL
tJIT tJIT tJIT tJIT tJIT
Data jitter on FRAME transmitted by the CR14 in ASK
ai12056
FRAME transmission between the reader and the contactless device
CR14 9 DC and AC parameters
41/46
Table 13. RFOUT AC Characteristics
1. Data specified in the table above are estimated or target values. All values can be updated during product
qualification.
Table 14. RFIN AC Characteristics
1. Data specified in the table above are estimated or target values. All values can be updated during product
qualification.
Symbol Parameter Condition Min. Max. Unit
fCC External Oscillator Frequency VCC = 5V 13.553 13.567 MHz
MICARRIER Carrier Modulation Index MI=(A-B)/(A+B) 10 14 %
tRFR,t
RFF 10% Rise and Fall time 0.5 1.5 µs
tRFSBL Pulse Width on RFOUT 1 ETU = 128/fCC 9.44 µs
tJIT ASK modulation bit jitter CR14 to PICC -0.5 0.5 µs
t0Antenna Reversal delay Min = 64/fS75 µs
t1Synchronization delay Min = 80 /fS94 µs
tWDG Answer delay watchdog (b5=0, b6=0) Request EOF
rising edge to
first Answer
start bit
500 µs
tWDG Answer delay watchdog (b5=0, b6=1) 5ms
tWDG Answer delay watchdog (b5=1, b6=0) 10 ms
tWDG Answer delay watchdog (b5=1, b6=1) 309 ms
tDR Time Between Request characters CR14 to PICC 9.44 µs
PARFOUT output power 90 mW
tPOR CR14 Power-On delay 20 ms
Symbol Parameter Condition Min. Max. Unit
tRFSBL PICC Pulse Width 1 ETU = 128/fCC 9.44 µs
fSPICC Sub-carrier Frequency fCC/16 847.5 KHz
tDA Time Between Answer characters PICC to CR14 1, 2, 3 ETU
VDYN RFIN Dynamic Voltage Level VDYN Max for VOFFSET =
VCC/2 0.5 VCC/2 V
VOFFSET RFIN Offset Voltage Level 23V
VRET RFIN Retro-modulation Level 120 mV
10 Package mechanical CR14
42/46
10 Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK®
pac kages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Inte rconnect is mark ed on the pac kag e and on th e inner bo x lab el, in compliance
with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK spe cifications are av ailable at: www.st.com.
Figure 36. SO16 Narrow - 16 lead Plastic Small Outline, 150 mils body width, Package
Outline
1. Drawing is not to scale.
Table 15. SO16 Narrow - 16 lead Plastic Smal l Outline, 150 mils body width,
Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.60 0.063
a 0°8° 0°8°
B 0.35 0.46 0.014 0.018
C 0.19 0.25 0.007 0.010
CP 0.10 0.004
D 9.80 10.00 0.386 0.394
e1.27 – – 0.050 – –
E 3.80 4.00 0.150 0.157
L 0.40 1.27 0.016 0.050
N16 16
SO-b
E
N
CP
Be
A2
D
C
LA1 α
H
A
1
CR14 11 Part numbering
43/46
11 Part numbering
Table 16. Ordering Inf ormation Scheme
Fo r a list of available options (speed, package, etc.) or for further information on any aspect of
this device, please contact your nearest ST Sales Office.
Example: CR14 – MQ / XXX
Device Type
CR14
Package
MQ = SO16 Narrow (150 mils width)
MQP = SO16 Narrow (150 mils width) ECOPACK®
Customer Code
XXX = Given by the issuer
11 Part number ing CR14
44/46
Appendix A ISO14443 type B CRC calculation
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>
#define BYTEunsigned char
#define USHORTunsigned short
unsigned short UpdateCrc(BYTE ch, USHORT *lpwCrc)
{ch = (ch^(BYTE)((*lpwCrc) & 0x00FF));
ch = (ch^(ch<<4));
*lpwCrc = (*lpwCrc >> 8)^((USHORT)ch <<
8)^((USHORT)ch<<3)^((USHORT)ch>>4);
return(*lpwCrc);
}
void ComputeCrc(char *Data, int Length, BYTE *TransmitFirst, BYTE
*TransmitSecond)
{
BYTE chBlock; USHORTt wCrc;
wCrc = 0xFFFF; // ISO 3309
do {
chBlock = *Data++;
UpdateCrc(chBlock, &wCrc);
} while (--Length);
wCrc = ~wCrc; // ISO 3309
*TransmitFirst = (BYTE) (wCrc & 0xFF);
*TransmitSecond = (BYTE) ((wCrc >> 8) & 0xFF);
return;
}
int main(void)
{
BYTE BuffCRC_B[10] = {0x0A, 0x12, 0x34, 0x56}, First, Second, i;
printf("Crc-16 G(x) = x^16 + x^12 + x^5 + 1");
printf("CRC_B of [ ");
for(i=0; i<4; i++)
printf("%02X ",BuffCRC_B[i]);
ComputeCrc(BuffCRC_B, 4, &First, &Second);
printf("] Transmitted: %02X then %02X.", First, Second);
return(0);
}
CR14 12 Re vision history
45/46
12 Revision history
Table 17. Document Revision History
Date Version Revision Details
16-Dec-2005 1 Initial release.
CR14
46/46
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of su ch information nor for an y infringement of pat ents or other rights of third parties whi ch may result from its us e. No license is gra nted
by implicat ion or ot herwi se un der any pa tent or paten t right s of ST Microel ect ronics . Spec ifica tio ns mentio ned i n this pu blicat ion are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components i n life support devices or systems wi thout express written approval of STMicroelectr onics.
The ST logo is a registered trademark of STMicroelectronics.
All other na mes are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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