PCM1739E/2KG4 - Texas Instruments

24-Bit, 192kHz Sampling,

Enhanced Multi-Level, Delta-Sigma, Audio

DIGITAL-TO-ANALOG CONVERTER

49%

FPO PCM1739

DESCRIPTION

The PCM1739 is a CMOS, monolithic, integrated

circuit which includes stereo 24-bit audio digital-to-

analog converters and support circuitry in a small

SSOP-28 package. The data converters utilize Burr-

Brown’s enhanced multi-level delta-sigma architec-

ture, which employs 4th-order noise shaping and

8-level amplitude quantization to achieve excellent

dynamic performance and improved tolerance to clock

jitter. The PCM1739 accepts industry-standard audio

data formats with 16- or 24-bit data, providing easy

interfacing to audio DSP and decoder chips. Sampling

rates up to 192kHz are supported.

FEATURES

●24-BIT RESOLUTION

●

ANALOG PERFORMANCE (VCC = +5V):

Dynamic Range: 106dB typ

SNR: 105dB typ

THD+N: 0.0015% typ

Full-Scale Output: 3.1Vp-p typ

●

4x/8x OVERSAMPLING DIGITAL FILTER:

Passband: 0.454fS

Stopband: 0.546fS

Stopband Attenuation: –82dB

Passband Ripple: ±0.002dB

●SAMPLING FREQUENCY: 10kHz to 192kHz

●SYSTEM CLOCK: 128f

, 192f

, 256f

, 384f

512f

, or 768f

with Auto Detect

●ACCEPTS 24- or 16-BIT AUDIO DATA

●DATA FORMATS: Standard, I

●MODE CONTROLS

Digital De-Emphasis

Soft Mute

Zero Flags for Each Output

●

DUAL SUPPLY OPERATION:

+5V Analog, +3.3V Digital

●

5V TOLERANT DIGITAL INPUTS

●

SMALL SSOP-28 PACKAGE

APPLICATIONS

●A/V RECEIVERS

●DVD AUDIO AND MOVIE PLAYERS

●DVD ADD-ON CARDS FOR ENTERTAINMENT

PCs

●HDTV RECEIVERS

●CAR AUDIO SYSTEMS

●

OTHER APPLICATIONS REQUIRING

24-BIT AUDIO

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

For most current data sheet and other product

information, visit www.burr-brown.com

PCM1739

SBAS133

PCM1739

SPECIFICATIONS

All specifications at TA = +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted.

PCM1739E

PARAMETER CONDITIONS MIN TYP MAX UNITS

RESOLUTION 24 Bits

DATA FORMAT

Audio Data Interface Formats User Selectable Standard/I2S

Audio Data Bit Length User Selectable 16 or 24 Bits

Audio Data Format MSB-First, Binary Two's Complement

System Clock Frequency 128, 192, 256, 384, 512, 768fS

Sampling Frequency (fS) 10 200 kHz

DIGITAL INPUT/OUTPUT

Logic Family TTL-Compatible

Input Logic Level

VIH 2.0 VDC

VIL 0.8 VDC

Input Logic Current

IIH VIN = VDD 0.1 µA

IIL VIN = 0V –0.1 µA

IIH(1) VIN = VDD 65 100 µA

IIL(1) VIN = 0V –0.1 µA

Output Logic Level

VOH(2) IOH = –2mA 2.4 VDC

VOL(2) IOL = +2mA 1.0 VDC

VOH(3) IOH = –4mA 2.4 VDC

VOL(3) IOL = +4mA 1.0 VDC

DYNAMIC PERFORMANCE(4)

THD+N, VOUT = 0dB fS = 44.1kHz, 384fS0.0015 0.0035 %

fS = 96kHz, 256fS0.0020 0.0050 %

fS = 192kHz, 128fS0.25 0.0060 %

VOUT = –60dB fS = 44.1kHz 0.6 0.8 %

fS = 96kHz 0.7 1.0 %

fS = 192kHz 0.8 1.2 %

Dynamic Range EIAJ, A-Weighted, fS = 44.1kHz 102 106 dB

A-Weighted, fS = 96kHz 100 105 dB

A-Weighted, fS = 192kHz 98 104 dB

Signal-to-Noise Ratio(5) EIAJ, A-Weighted, fS = 44.1kHz 100 105 dB

A-Weighted, fS = 96kHz 100 104 dB

A-Weighted, fS = 192kHz 100 104 dB

Channel Separation fS = 44.1kHz 100 104 dB

fS = 96kHz 98 103 dB

fS = 192kHz 96 102 dB

DC ACCURACY

Gain Error ±1.0 ±3.0 % of FSR

Gain Mismatch, Channel-to-Channel ±1.0 ±3.0 % of FSR

Bipolar Zero Error VOUT = 0.5VCC at BPZ ±30 ±60 mV

ANALOG OUTPUT

Output Voltage Full Scale (–0dB) 62% of VCC Vp-p

Center Voltage 50% of VCC VDC

Load Impedance AC Load 5 kΩ

DIGITAL FILTER PERFORMANCE

Filter Characteristics

Passband ±0.002dB 0.454fSHz

–3dB 0.490fSHz

Stopband 0.546fs Hz

Passband Ripple ±0.002 dB

Stopband Attenuation Stopband = 0.546fS–75 dB

Stopband = 0.567fS–82 dB

Delay Time 34/fSsec

De-Emphasis Error ±0.1 dB

ANALOG FILTER PERFORMANCE

Frequency Response At 20kHz –0.03 dB

At 44kHz –0.20 dB

Cut-Off Frequency –3dB 190 kHz

3PCM1739

SPECIFICATIONS (cont.)

All specifications at +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

Power Supply Voltage, VDD .............................................................. +4.0V

VCC .............................................................. +6.5V

Input Current (except power supply pins) ....................................... ±10mA

Supply Voltage Difference ................................................................ ±0.1V

GND Voltage Difference ................................................................... ±0.1V

Digital Input Voltage........................................................... –0.2V to +5.5V

Digital Output Voltage .............................................. –0.2V to (VDD + 0.2V)

Power Dissipation .......................................................................... 650mW

Operating Temperature Range ............................................. 0°C to +70°C

Storage Temperature...................................................... –55°C to +125°C

Lead Temperature (soldering, 5s) ................................................ +260°C

Package Temperature (IR reflow, 10s) .......................................... +235°C

ABSOLUTE MAXIMUM RATINGS

PACKAGE SPECIFIED

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

PACKAGE PACKAGE NUMBER RANGE MARKING NUMBER(1) MEDIA

PCM1739E 28-Lead SSOP 324 0°C to +70°C PCM1739E PCM1739E Rails

" " " " " PCM1739E/2K Tape and Reel

NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces

of “PCM1739E/2K” will get a single 2000-piece Tape and Reel.

PACKAGE/ORDERING INFORMATION

PCM1739E

PARAMETER CONDITONS MIN TYP MAX UNITS

POWER SUPPLY REQUIREMENTS

Voltage Range

VDD +3.0 +3.3 +3.6 VDC

VCC +4.5 +5.0 +5.5 VDC

Supply Current

IDD(6) VDD = 3.3V

fS = 44.1 kHz 8.5 12.0 mA

fS = 96kHz, 256fS16.5 mA

fS = 192kHz, 128fS19.5 mA

ICC VCC = 5.0V

fS = 44.1kHz 13.0 18.0 mA

fS = 96kHz, 256fS14.0 mA

fS = 192kHz, 128fS14.5 mA

Power Dissipation VDD = 3.3V, VCC = 5.0V

fS = 44.1kHz 93 130 mW

fS = 96kHz, 256fS124 mW

fS = 192kHz, 128fS137 mW

TEMPERATURE RANGE

Operation 070°C

Storage –55 +125 °C

Thermal Resistance

JA 100 °C/W

NOTES: (1) Pins 8, 9, 26, 27, 28 (TEST1, IBIT, DEM0 DEM1, FORM). (2) Pins 23, 24 (ZEROL, ZEROR). (3) Pin 4 (CLKO). (4) Analog performance specs are

tested with Shibasoku #725 THD Meter 400Hz HPF, 30kHz LPF on, average mode with 20kHz bandwidth limiting. The load connected to the analog output is 5kΩ

or larger, AC-coupled. (5) SNR is tested with Infinite Zero Detection off. (6) CLKO is disabled.

PCM1739

PIN NAME TYPE DESCRIPTION

1 LRCK IN Left/Right Word Clock(1)

2 DATA IN Data In for Left and Right Channels(1)

3 BCLK IN Bit Clock(1)

4 CLKO OUT System Clock Output

5 SCLK IN System Clock Input(1)

SS — Digital Ground

DD — Digital Supply, +3.3V.

8 TEST1 IN

Test Pin. Must be connected to VDD(2).

9 IBIT IN Audio Data Word Length Select

(2)

10 VCCR — Analog Supply for Right Channel, +5V.

11 GNDR — Analog Ground for Right Channel

12 VCOMR — Common for Right Channel

13 VOUTR OUT Analog Output for Right Channel

14 GNDA — Analog Ground

15 VCCA — Analog Supply, +5V.

16 VOUTL OUT Analog Ouput for Left Channel

17 VCOML — Common for Left Channel

18 GNDL — Analog Ground for Left Channel

19 VCCL — Analog Supply for Left Channel, +5V.

20 FILT IN 4x/8x Interpolation Filter Select

(2)

21 MUTE IN Digital Mute for Left and Right Channels

(2)

22 RSTB IN Reset, Active Low

(1)

23 ZEROL OUT Zero Flag for Left Channel

24 ZEROR OUT Zero Flag for Right Channel

25 NC — No Connect

26 DEM0 IN De-Emphasis Filter Select 0

(2)

27 DEM1 IN De-Emphasis Filter Select 1

(2)

28 FORM IN Audio Data Format Select

(2)

NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant.

(2) Schmitt-Trigger input, 5V tolerant.

PIN ASSIGNMENTS

BLOCK DIAGRAM

Top View SSOP

PIN CONFIGURATION

LRCK

DATA

BCLK

CLKO

SCLK

VSS

VDD

TEST1

IBIT

VCCR

GNDR

VCOMR

VOUTR

GNDA

FORM

DEM1

DEM0

ZEROR

ZEROL

RSTB

MUTE

FILT

VCCL

GNDL

VCOML

VOUTL

VCCA

PCM1739E

Audio

Serial

I/F

DAC

4x/8x

Oversampling

Digital Filter

with

Function

Controller

Enhanced

Multi-level

Delta-Sigma

Modulator

Output Amp and

Low-Pass Filter

Output Amp and

Low-Pass Filter

BCK

LRCK

DATA

Mode

Control

I/F

System Clock

Manager

Zero Detect Power Supply

TEST

IBIT

RSTB

FORM

DEM1

DEM0

MUTE

FILT

COM

OUT

COM

OUT

ZEROL

ZEROR

SCLK

System Clock

CLKO

GNDA

GNDL

GNDR

PCM1739

5PCM1739

TYPICAL PERFORMANCE CURVES

All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.

DIGITAL FILTER

Digital Filter (De-Emphasis Off, fS = 44.1kHz)

DIGITAL FILTER

De-Emphasis Error

0 0.5 1 1.5 2 2.5 3 3.5 4

–20

–40

–60

–80

–100

–120

–140

–160

Amplitude (dB)

FREQUENCY RESPONSE

Frequency (x fS)

PASSBAND RIPPLE

Frequency (x f

)

Amplitude (dB)

0.003

0.002

0.001

–0.001

–0.002

–0.003 0 0.1 0.2 0.3 0.4 0.5

DE-EMPHASIS FREQUENCY RESPONSE (f

= 32kHz)

02468101214

Frequency (kHz)

–2

–4

–6

–8

–10

Level (dB)

DE-EMPHASIS FREQUENCY RESPONSE (f

= 48kHz)

0246810121416182022

Frequency (kHz)

–2

–4

–6

–8

–10

Level (dB)

DE-EMPHASIS FREQUENCY RESPONSE (f

= 44.1kHz)

02468101214161820

Frequency (kHz)

–2

–4

–6

–8

–10

Level (dB)

DE-EMPHASIS ERROR (f

= 32kHz)

02468101214

Frequency (kHz)

0.5

0.3

0.1

–0.1

–0.3

–0.5

0.5

0.3

0.1

–0.1

–0.3

–0.5

0.5

0.3

0.1

–0.1

–0.3

–0.5

Level (dB)

DE-EMPHASIS ERR0R (f

= 48kHz)

0246810121416182022

Frequency (kHz)

Level (dB)

DE-EMPHASIS ERROR (f

= 44.1kHz)

02468101214161820

Frequency (kHz)

Level (dB)

PCM1739

TYPICAL PERFORMANCE CURVES (cont.)

All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.

ANALOG DYNAMIC PERFORMANCE

Supply Voltage Characteristics

Temperature Characteristics

TOTAL HARMONIC DISTORTION + NOISE vs V

= 3.3V)

(V)

THD+N (%)

0.1

0.01

0.001

0.0001 4.0 4.5 5.0 5.5 6.0

44.1kHz, 384f

192kHz, 128f

–60dB

0dB

192kHz, 128f

DYNAMIC RANGE vs V

= 3.3V)

(V)

Dynamic Range (dB)

110

108

106

104

102

100

96 4.0 4.5 5.0 5.5 6.0

192kHz, 128f

44.1kHz, 384f

SIGNAL-TO-NOISE RATIO vs V

= 3.3V)

(V)

SNR (dB)

110

108

106

104

102

100

96 4.0 4.5 5.0 5.5 6.0

192kHz, 128f

44.1kHz, 384f

CHANNEL SEPARATION vs V

(V)

Channel Separation (dB)

110

108

106

104

102

100

96 4.0 4.5 5.0 5.5 6.0

192kHz, 128f

44.1kHz, 384f

TOTAL HARMONIC DISTORTION + NOISE

vs TEMPERATURE

(V)

THD+N (%)

0.1

0.01

0.001

0.0001 4.0 4.5 5.0 5.5 6.0

44.1kHz, 384f

192kHz, 128f

–60dB

0dB

192kHz, 128f

DYNAMIC RANGE vs TEMPERATURE

(VDD = 3.3V)

Temperature (°C)

Dynamic Range (dB)

110

108

106

104

102

100

96–25 0 25 50 75 100

192kHz, 128fS

44.1kHz, 384fS

7PCM1739

TYPICAL PERFORMANCE CURVES (cont.)

All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 20-bit input data, unless otherwise noted.

Temperature Characteristics (cont.)

CHANNEL SEPARATION vs TEMPERATURE

= 3.3V)

Temperature (°C)

Channel Separation (dB)

110

108

106

104

102

100

96–25 0 25 50 75 100

192kHz, 128f

44.1kHz, 384f

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

= 3.3V)

Temperature (°C)

SNR (dB)

110

108

106

104

102

100

96–25 0 25 50 10075

192kHz, 128f

44.1kHz, 384f

PCM1739

FIGURE 1. System Clock Input Timing.

SYSTEM CLOCK AND RESET

FUNCTIONS

SYSTEM CLOCK INPUT

The PCM1739 requires a system clock for operating the

digital interpolation filters and multi-level delta-sigma modu-

lators. The system clock is applied at the SCLK input (pin

5). Table I shows examples of system clock frequencies for

common audio sampling rates.

Figure 1 shows the timing requirements for the system clock

input. For optimal performance, it is important to use a clock

source with low phase jitter and noise. Burr-Brown’s

PLL1700 multi-clock generator is an excellent choice for

providing the PCM1739 system clock.

SYSTEM CLOCK OUTPUT

A buffered version of the system clock input is available at

the CLKO output (pin 4). CLKO operates at the same

frequency as the system clock, SCLK.

POWER-ON AND EXTERNAL RESET FUNCTIONS

The PCM1739 includes a power-on reset function. Figure 2

shows the operation of this function. The system clock input

at SCLK should be active for at least one clock period prior

to VDD = 2.0V. With the system clock active and VDD >

2.0V, the power-on reset function will be enabled. The

initialization sequence requires 1024 system clocks from the

time VDD > 2.0V. The PCM1739 also includes an external

reset capability using the RSTB input (pin 22). This allows

an external controller or master reset circuit to force the

PCM1739 to initialize to its reset default state. For normal

operation, RSTB should be set to a logic ‘1’.

Figure 3 shows the external reset operation and timing. The

RSTB pin is set to logic ‘0’ for a minimum of 20ns. The

RSTB pin is then set to a logic ‘1’ state, which starts the

initialization sequence, which lasts for 1024 system clock

periods.

The external reset is especially useful in applications where

there is a delay between PCM1739 power up and system

clock activation. In this case, the RSTB pin should be held

at a logic ‘0’ level until the system clock has been activated.

SYSTEM CLOCK FREQUENCY, fSCLK, (MHZ)

SAMPLING

FREQUENCY (f

) 128f

192f

256f

384f

512f

768f

16kHz — — 4.0960 6.1440 8.1920 12.2880

32kHz — — 8.1920 12.2880 16.3840 24.5760

44.1kHz — — 11.2896 16.9344 22.5792 33.8688

48kHz — — 12.2880 18.4320 24.5760 36.8640

88.2kHz — — 22.5792 33.8688 45.1584 See Note 1

96kHz 12.2880 18.4320 24.5760 36.8640 49.1520 See Note 1

176.4kHz 24.5792 33.8688 See Note 2 See Note 2 See Note 2 See Note 2

192kHz 24.5760 36.8640 See Note 2 See Note 2 See Note 2 See Note 2

NOTES: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock rate is not supported for the given sampling frequencies.

TABLE I. System Clock Rates for Common Audio Sampling Frequencies.

SCLK

System Clock Pulse Width High t

SCLKH

: 7ns min

System Clock Pulse Width Low t

SCLKL

: 7ns min

2.0V

0.8V

“H”

“L”

SCLK

9PCM1739

FIGURE 2. Power-On Reset Timing.

FIGURE 3. External Reset Timing.

AUDIO SERIAL INTERFACE

The audio serial interface for the PCM1739 is comprised

of a 3-wire synchronous serial port. It includes LRCK (pin

1), BCLK (pin 3), and DATA (pin 2). BCLK is the serial

audio bit clock, and is used to clock the serial data present

on DATA into the audio interface’s serial shift registers.

Serial data is clocked into the PCM1739 on the rising edge

of BCLK. LRCK is the serial audio left/right word clock.

It is used to latch serial data into the serial audio interface’s

internal registers.

Both LRCK and BCLK must be synchronous to the system

clock. Ideally, it is recommended that LRCK and BCLK

be derived from the system clock input or output, SCLK or

CLKO. The left/right clock, LRCK, is operated at the

sampling frequency (fS). The bit clock, BCK, may be

operated at 48 or 64 times the sampling frequency.

AUDIO DATA FORMATS AND TIMING

The PCM1739 supports industry-standard audio data for-

mats, including Standard and I2S. The audio data word

length may be either 24 or 16 bits. Data format and word

length are selected using the FORM and IBIT pins, as

described in the Mode Controls section of this data sheet.

All formats require Binary Two’s Complement, MSB-first

audio data. The data formats are shown in Figure 4, while

Figure 5 shows a detailed timing diagram for the serial

audio interface.

MODE CONTROLS

This section describes the mode control pins used to configure

the operating mode of the PCM1739.

AUDIO DATA FORMAT

The data format used by the audio serial interface is selected

using the FORM input (pin 28). The formats available

include Standard and I2S. Table II shows the FORM pin

configuration.

TABLE II. Audio Data Format Selection.

FORM DATA FORMAT

L Standard

AUDIO DATA WORD LENGTH

The data word length used by the audio serial interface is

selected using the IBIT input (pin 9). The word length may

be either 24 or 16 bits. Table III shows the IBIT pin

configuration.

IBIT DATA WORD LENGTH

L 24 Bits

H 16 Bits

TABLE III. Audio Data Word Length Selection.

1024 system clocks

Reset Reset Removal

= V

Internal Reset

2.4V

2.0V

1.6V

System Clock

(SCLK)

1024 system clocks

Reset Reset Removal

System Clock

(SCLK)

Internal Reset

RSTB

RST(1)

NOTE: (1) t

RST

= 20ns min.

PCM1739

FIGURE 4. Audio Data Input Formats.

16-Bit Right-Justified

DATA

(2) 16- or 24-Bit I

S Data Format; Lch = LOW, Rch = HIGH

(1) Standard Data Format; Lch = HIGH, Rch = LOW

1/f

Lch Rch

LRCK

BCLK

(= 48f

or 64f

)

1/f

Lch Rch

LRCK

BCLK

(= 48f

or 64f

)

12 3 22 23 24 123 22 23 24

14 15 16 14 15 16

123

DATA

22 23 24 22 23 24

12345

DATA

24-Bit Right-Justified

14 15 16

123

22 23 24

12345

LSBMSB LSBMSB

11 PCM1739

SYMBOL PARAMETER MIN MAX UNITS

tBCY BCK Pulse Cycle Time 48 or 64fS(1)

tBCH BCK High Level Time 35 ns

tBCL BCK Low Level Time 35 ns

tBL BCK Rising Edge to LRCK Edge 10 ns

tLB LRCK Falling Edge to BCK Rising Edge 10 ns

tDS DIN Set Up Time 10 ns

tDH DIN Hold Time 10 ns

NOTE: (1) fS is the sampling frequency.

FIGURE 5. Audio Interface Timing.

FILT OVERSAMPLING RATE

L8x

H 4x ( Required for 192kHz operation)

TABLE IV. Digital Filter Oversampling Rate Selection.

MUTE SOFT MUTE STATUS

L Disabled

H Enabled

TABLE V. Soft Mute Selection.

DEM1 DEM0 DE-EMPHASIS FUNCTION

L L OFF

L H 32kHz De-Emphasis Filter

H L 44.1kHz De-Emphasis Filter

H H 48kHz De-Emphasis Filter

TABLE VI. Digital De-Emphasis.

4x/8x DIGITAL INTERPOLATION

The PCM1739’s digital filter may be configured for either

4x or 8x oversampling. The 8x oversampling setting is

utilized for sampling frequencies up to 96kHz, while 4x

oversampling is utilized for 192kHz operation. The FILT

input (pin 20) is used to select the oversampling rate of the

digital filter. Table IV shows the FILT pin configuration.

SOFT MUTE

The Soft Mute function provides for quiet muting of the

DAC outputs, VOUTL (pin 16) and VOUTR (pin 13). This is

done by ramping an internal digital attenuator from unity

gain to digital mute (all 0’s input to the digital filter). The

MUTE input (pin 21) is used to enable and disable the Soft

Mute function. Table V shows the MUTE pin configuration.

DIGITAL DE-EMPHASIS

The PCM1739 provides a De-emphasis function for sam-

pling rates equal to 32kHz, 44.1kHz or 48kHz. It is incorpo-

rated into the digital filter of the PCM1739. The De-empha-

sis function is required for proper playback of early audio

compact disks (CDs), which were mastered with signal

emphasis for higher frequencies in the audio band. This was

done to improve the poor high frequency performance of

early CD players. Plots of the de-emphasis filter and error

functions for 32kHz, 44.1kHz, and 48kHz are shown in the

Typical Performance Curves section of this data sheet.

The DEM0 (pin 26) and DEM1 (pin 27) inputs of the

PCM1739 are used to enable and disable the digital de-

emphasis function. Table VI shows the DEM0 and DEM1

pin configurations.

ANALOG OUTPUTS

The PCM1739 includes two independent output channels;

VOUTL (pin 16) and VOUTR (pin 13). These are unbalanced

outputs, each capable of driving 3.1Vp-p typical into a 5kΩ,

AC-coupled load (VCC = +5V). The internal output ampli-

fiers for VOUTL and VOUTR are DC biased to a DC common-

mode (or bipolar zero) voltage, equal to VCC/2.

The output amplifiers include an RC continuous time filter,

which helps to reduce the out-of-band noise energy present

at the DAC outputs due to the noise shaping characteristics

of the PCM1739’s delta-sigma D/A converters. The fre-

LRCK

BCLK

DATA

50% of V

BCH

BCL

BCY

PCM1739

FIGURE 6. Output Filter Frequency Response.

1 10 100 1k 10k 100k 10M1M

–20

–40

–60

–80

–100

Level (dB)

Log Frequency (Hz)

quency response of this filter is shown in Figure 6. By itself,

this filter is not enough to attenuate the out-of-band noise to

an acceptable level for most applications. An external low-

pass filter is required to provide sufficient out-of-band noise

rejection. Further discussion of DAC post filter circuits is

provided in the Applications Information section of this data

sheet.

FIGURE 7. Biasing External Circuits Using the VCOML and VCOMR Pins.

VCOML AND VCOMR OUTPUTS

Two unbuffered, DC common-mode voltage output pins,

VCOML (pin 17) and VCOMR (pin 12), are brought out for

decoupling purposes. These pins are normally biased to a

DC voltage level equal to VCC/2. These pins may be used to

bias external circuits, but they must be connected to high

impedance nodes. Figure 7 shows examples of the proper use

of the VCOML and VCOMR pins for external biasing applica-

tions.

ZERO FLAG OUTPUTS

The PCM1739 includes circuitry for detecting an all zero

data condition for the data input pin, DATA. Zero detection

for each output channel is independent from the other. If the

data for a given channel remains at a ‘0’ level for 1024

sample periods (or LRCK clock periods), a Zero Detect

condition exists for the that channel. Given that a Zero

Detect condition exists, the Zero Flag pin(s) for the corre-

sponding channel(s) will be set to a logic ‘1’ state. The zero

flag outputs include ZEROL (pin 23) and ZEROR (pin 24).

These pins can be used to operate external mute circuits, or

used as status indicators for audio signal processor,

microcontroller, or other digitally-controlled functions.

1/2

OPA2353

OPA337

C1VCC

10µF

VOUTx

VCOMx

PCM1739

Filtered

Output

x = L or R

VCC

PCM1739

VCOMx+10µF

x = L or R

Buffered

VCOM

(b) Using a Voltage Follower to Buffer VCOM when Biasing Multiple Nodes

25kΩSense

Out

25kΩ

VOUTx

VCOMx

V+

V–

10µF

+IN

–IN

x = L or R

Ref

To Low-Pass

Filter Stage

PCM1739

INA134

(a) Using VCOM To Bias A Single-Supply Filter Stage

VCC

49.9kΩ

13 PCM1739

FIGURE 8. Basic Connection Diagram.

APPLICATIONS INFORMATION

CONNECTION DIAGRAM

A basic connection diagram with the necessary power sup-

ply bypassing and decoupling components is shown in

Figure 8. Burr-Brown recommends using the component

values shown in Figure 8 for all designs.

The use of series resistors (22Ω to 100Ω) is recommended

for the SCLK, LRCK, BCLK, and DATA inputs. The series

resistor combines with the stray PCB and device input

capacitance to form a low-pass filter, which reduces high

frequency noise emissions and helps to dampen glitches and

ringing present on clock and data lines.

POWER SUPPLIES AND GROUNDING

The PCM1739 requires a +5V analog supply and a +3.3V

digital supply. The +5V supply is used to power the DAC

analog and output filter circuitry, while the +3.3V supply is

used to power the digital filter and logic circuitry. For best

performance, the +3.3V supply should be derived from the

+5V supply using a linear regulator, shown in Figure 8.

Burr-Brown’s REG1117-3.3 is an ideal choice for this appli-

cation.

Proper power supply bypassing is shown in Figure 8. The

bypass capacitors should be located as close as possible to

the PCM1739 package. The 1µF and 10µF capacitors should

be tantalum or aluminum electrolytic, while the 0.1µF ca-

pacitors are ceramic (X7R type is recommended for surface

mount applications).

D/A OUTPUT CIRCUITS

Delta-sigma D/A converters utilize noise-shaping techniques

to improve in-band Signal-to-Noise (SNR) performance at

the expense of generating increased out-of-band noise above

the Nyquist Frequency, or fS/2. The out-of-band noise must

be low-pass filtered in order to provide optimal converter

performance. This is accomplished by a combination of on-

chip and external low pass filtering.

Figures 7a and 9 show the recommended external low pass

active filter circuits for dual and single-supply applications.

These circuits are 2nd-order filters using the Multiple Feed-

back (MFB) circuit arrangement, which reduces sensitivity to

passive component variations over frequency and tempera-

ture. For more information regarding MFB active filter design,

please refer to Burr-Brown Applications Bulletin AB-034.

LRCK

DATA

BCLK

CLKO

SCLK

TEST1

IBIT

GNDR

COM

OUT

GNDA

FORM

DEM1

DEM0

ZEROR

ZEROL

RSTB

MUTE

FILT

GNDL

COM

OUT

+3.3V

Regulator

S(1)

From

Mode Control

Logic

Zero Flag

Outputs

From Host Or

Master Reset

From

Mode Control

Logic

Output

Filter

Circuits

+5V

Analog

, C

= 10

F Tantalum or Aluminum Electrolytic

, C

= 0.1

F Ceramic

, C

= 1

F Tanatlum or Aluminum Electrolytic

, C

= 1-10

F Aluminum Electrolytic

NOTE: (1) R

= 20Ω to 100Ω.

PCM1739

From/To

Audio

Source

From

Mode Control

Logic

PCM1739

FIGURE 10. Recommended PCB Layout.

PCM1739

DGND

Return Path for Digital Signals

Analog

Ground

Digital

Ground

AGND

Output

Circuits

DIGITAL SECTION ANALOG SECTION

Digital Logic

and

Audio

Processor

Digital Power

DGND

Analog Power

+5VA +V

AGND

REG

–V

PCM1739

DGND Output

Circuits

RF Choke or Ferrite Bead

Common

Ground

AGND

DIGITAL SECTION ANALOG SECTION

Power Supplies

+5V +V

AGND

REG

–V

FIGURE 9. Dual Supply Filter Circuit.

Since the overall system performance is defined by the

quality of the D/A converters and their associated analog

output circuitry, high quality audio op amps are recom-

mended for the active filters. Burr-Brown’s OPA2134 and

OPA2353 dual op amps are shown in Figures 7a and 9, and

are recommended for use with the PCM1739.

PCB LAYOUT GUIDELINES

A typical PCB floor plan for the PCM1739 is shown in

Figure 10. A ground plane is recommended, with the analog

and digital sections being isolated from one another using a

split or cut in the circuit board. The PCM1739 should be

oriented with the digital I/O pins facing the ground plane

split/cut, allowing for direct connection of the digital audio

interface and control signals originating from the digital

section of the board.

Separate power supplies are recommended for the digital

and analog sections of the board. This prevents the switching

noise present on the digital supply from contaminating the

analog power supply and degrading the dynamic perfor-

mance of the PCM1739. In cases where a common +5V

supply must be used for the analog and digital sections, an

R1R3R4

R2C1

VIN VOUT

OPA2134

AV ≈ –

FIGURE 11. Single-Supply PCB Layout.

15 PCM1739

FIGURE 12. Eight-Level Delta-Sigma Modulator.

FIGURE 14. Jitter Sensitivity.FIGURE 13. Quantization Noise Spectrum.

0 100 200 300 400 500 600

125

120

115

110

105

100

Dynamic Range (dB)

Jitter (ps)

CLOCK JITTER

012345678

–20

–40

–60

–80

–100

–120

–140

–160

–180

Amplitude (dB)

Frequency (fS)

–1

8-Level Quantizer

–1

–

–1

or 8f

64f

inductance (RF choke, ferrite bead) should be placed be-

tween the analog and digital +5V supply connections to

avoid coupling of the digital switching noise into the analog

circuitry. Figure 11 shows the recommended approach for

single-supply applications

THEORY OF OPERATION

The delta-sigma section of PCM1739 is based on a 8-level

amplitude quantizer and a 4th-order noise shaper. This

section converts the oversampled input data to 8-level delta-

sigma format.

A block diagram of the 8-level delta-sigma modulator is

shown in Figure 12. This 8-level delta-sigma modulator has

the advantage of stability and clock jitter sensitivity over the

typical one-bit (2-level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modu-

lator and the interpolation filter is 64fS for all system clock

combinations (128, 192, 256, 384, 512, 768fS).

The theoretical quantization noise performance of the

8-level delta-sigma modulator is shown in Figure 13. The

enhanced multi-level delta-sigma architecture also has ad-

vantages for input clock jitter sensitivity due to the multi-

level quantizer, with the simulated jitter sensitivity shown in

Figure 14.

KEY PERFORMANCE

PARAMETERS AND MEASUREMENT

This section provides information on how to measure key

dynamic performance parameters for the PCM1739. In all

cases, an Audio Precision System Two Cascade or equiva-

lent audio measurement system is utilized to perform the

testing.

TOTAL HARMONIC DISTORTION + NOISE

Total Harmonic Distortion + Noise (THD+N) is a signifi-

cant figure of merit for audio D/A converters since it takes

into account both harmonic distortion and all noise sources

within a specified measurement bandwidth. The true rms

value of the distortion and noise is referred to as THD+N.

PCM1739

FIGURE 15. Test Setup for THD+N Measurement.

FIGURE 16. Test Set-Up for Dynamic Range and SNR Measurements.

For the PCM1739, THD+N is measured with a full scale,

1kHz digital sine wave as the test stimulus at the input of

the DAC. The digital generator is set to 24-bit audio word

length and a sampling frequency of 44.1kHz, 96kHz, or

192kHz. The digital generator output is taken from the

unbalanced S/PDIF connector of the measurement system.

The S/PDIF data is transmitted via a coaxial cable to the

digital audio receiver on the DEM-DAI1739 demo board.

The receiver is then configured to output 24-bit data in

either I2S or left-justified data format. The DAC audio

interface format is programmed to match the receiver

output format. The analog output is then taken from the

DAC post filter and connected to the analog analyzer input

of the measurment system. The analog input is band lim-

ited using filters resident in the analyzer. The resulting

THD+N is measured by the analyzer and displayed by the

measurement system.

DYNAMIC RANGE

Dynamic range is specified as A-Weighted, THD+N mea-

sured with a –60dBFS, 1kHz digital sine wave stimulus at

the input of the D/A converter. This measurement is de-

signed to give a good indicator of how the DAC will perform

given a low-level input signal.

The measurement setup for the dynamic range measurement

is shown in Figure 15, and is similar to the THD+N test

setup discussed previously. The differences include the

bandlimit filter selection, the additional A-Weighting filter,

and the –60dBFS input level.

IDLE CHANNEL SIGNAL-TO-NOISE RATIO

The SNR test provides a measure of the noise floor of the

D/A converter. The input to the D/A is all 0’s data, and the

D/A converter’s Infinite Zero Detect Mute function must

be disabled (default condition at power up for the PCM1739).

This ensures that the delta-sigma modulator output is con-

nected to the output amplifier circuit so that idle tones (if

present) can be observed and effect the SNR measurement.

The dither function of the digital generator must also be

disabled to ensure an all ‘0’s data stream at the input of the

D/A converter.

The measurement setup for SNR is identical to that used for

dynamic range, with the exception of the input signal level.

(see the notes provided in Figure 16).

S/PDIF

Receiver

Evaluation Board

–3dB

= 54kHz or 108kHz

PCM1739

DEM-DAI1739

2nd-Order

Low-Pass

Filter

Notch FilterBand Limit

HPF = 22Hz

LPF = 30kHz f

= 1kHzRMS Mode0dBFS,

1kHz Sine Wave

S/PDIF

Output

Analyzer

and

Display

20kHz

Apogee

Filter

Digital

Generator

S/PDIF

Receiver

Evaluation Board

PCM1739

(1)

DEM-DAI1739

2nd-Order

Low-Pass

Filter

Notch FilterBand Limit

HPF = 22Hz

LPF = 22kHz f

= 1kHz

–3dB

= 54kHz or 108kHz

0% Full Scale,

Dither Off (SNR) or

–60dBFS,

1kHz Sine Wave

(Dynamic Range)

S/PDIF

Output

A-Weight

Filter

(2)

RMS Mode

Analyzer

and

Display

Digital

Generator

NOTES: (1) Infinite Zero Detect Mute disabled.

(2) Results without A-Weighting will be

approximately 3dB worse.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

PCM1739E ACTIVE SSOP DB 28 47 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PCM1739E/2K ACTIVE SSOP DB 28 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PCM1739E/2KG4 ACTIVE SSOP DB 28 2000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PCM1739EG4 ACTIVE SSOP DB 28 47 Green (RoHS &

no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 4-Nov-2005

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

PCM1739E/2K SSOP DB 28 2000 330.0 17.4 8.5 10.8 2.4 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jun-2008

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

PCM1739E/2K SSOP DB 28 2000 336.6 336.6 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jun-2008

Pack Materials-Page 2

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