DS90C363, DS90CF364
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SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link–65 MHz,
+3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link–65 MHz
Check for Samples: DS90C363,DS90CF364
1FEATURES DESCRIPTION
The DS90C363 transmitter converts 21 bits of
23• 20 to 65 MHz shift clock support CMOS/TTL data into three LVDS (Low Voltage
• Programmable Transmitter (DS90C363) strobe Differential Signaling) data streams. A phase-locked
select (Rising or Falling edge strobe) transmit clock is transmitted in parallel with the data
• Single 3.3V supply streams over a fourth LVDS link. Every cycle of the
transmit clock 21 bits of input data are sampled and
• Chipset (TX + RX) power consumption < 250 transmitted. The DS90CF364 receiver converts the
mW (typ) LVDS data streams back into 21 bits of CMOS/TTL
• Power-down mode (< 0.5 mW total) data. At a transmit clock frequency of 65 MHz, 18 bits
• Single pixel per clock XGA (1024×768) ready of RGB data and 3 bits of LCD timing and control
data (FPLINE, FPFRAME, DRDY) are transmitted at
• Supports VGA, SVGA, XGA and higher a rate of 455 Mbps per LVDS data channel. Using a
addressability 65 MHz clock, the data throughput is 170 Mbyte/sec.
• Up to 170 Megabyte/sec bandwidth The Transmitter is offered with programmable edge
• Up to 1.3 Gbps throughput data strobes for convenient interface with a variety of
graphics controllers. The Transmitter can be
• Narrow bus reduces cable size and cost programmed for Rising edge strobe or Falling edge
• 290 mV swing LVDS devices for low EMI strobe through a dedicated pin. A Rising edge
• PLL requires no external components Transmitter will inter-operate with a Falling edge
Receiver (DS90CF364) without any translation logic.
• Low profile 48-lead TSSOP package
• Falling edge data strobe Receiver This chipset is an ideal means to solve EMI and
cable size problems associated with wide, high speed
• Compatible with TIA/EIA-644 LVDS standard TTL interfaces.
• ESD rating > 7 kV
• Operating Temperature: −40°C to +85°C
Block Diagrams
Figure 1. Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2TRI-STATE is a registered trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1999–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS90C363, DS90CF364
SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
www.ti.com
Figure 2. DS90C363 Figure 3. DS90CF364
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
Supply Voltage (VCC)−0.3V to +4V
CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V)
CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V)
LVDS Driver Output Voltage −0.3V to (VCC + 0.3V)
LVDS Output Short Circuit Duration Continuous
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 4 seconds) +260°C
DS90C363 1.98 W
Maximum Package Power Dissipation Capacity at 25°C (TSSOP
Package) DS90CF364 1.89 W
DS90C363 16 mW/°C above +25°C
Package Derating DS90CF364 15 mW/°C above +25°C
ESD Rating HBM, 1.5 kΩ, 100 pF > 7 kV
(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to
imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Recommended Operating Conditions Min Nom Max Unit
Supply Voltage (VCC) 3.0 3.3 3.6 V
Operating Free Air Temperature (TA)−40 +25 +85 °C
Receiver Input Range 0 2.4 V
Supply Noise Voltage (VCC) 100 mVPP
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SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
CMOS/TTL DC SPECIFICATIONS
VIH High Level Input Voltage 2.0 VCC V
VIL Low Level Input Voltage GND 0.8 V
VOH High Level Output Voltage IOH =−0.4 mA 2.7 3.3 V
VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 V
VCL Input Clamp Voltage ICL =−18 mA −0.79 −1.5 V
IIN Input Current VIN = VCC, GND, 2.5V or 0.4V ±5.1 ±10 µA
IOS Output Short Circuit Current VOUT = 0V −60 −120 mA
LVDS DC SPECIFICATIONS
VOD Differential Output Voltage RL= 100Ω250 345 450 mV
ΔVOD Change in VOD between 35 mV
complimentary output states
VOS Offset Voltage (1) 1.125 1.25 1.375 V
ΔVOS Change in V OS between 35 mV
complimentary output states
IOS Output Short Circuit Current VOUT = 0V, RL= 100Ω −3.5 −5 mA
IOZ Output TRI-STATE®Current PWR DWN = 0V, VOUT = 0V or VCC ±1 ±10 µA
VTH Differential Input High Threshold VCM = +1.2V +100 mV
VTL Differential Input Low Threshold −100 mV
IIN Input Current VIN = +2.4V, VCC = 3.6V ±10 µA
VIN = 0V, VCC = 3.6V ±10 µA
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current, Worst RL= 100Ω, f = 32.5 MHz 31 45 mA
Case CL= 5 pF, f = 37.5 MHz 32 50 mA
Worst Case Pattern f = 65 MHz 42 55 mA
(Figure 4 Figure 6 ),
TA=−40°C to +85°C
ICCTG Transmitter Supply Current, 16 RL= 100Ω, f = 32.5 MHz 23 35 mA
Grayscale CL= 5 pF, f = 37.5 MHz 28 40 mA
16 Grayscale Pattern f = 65 MHz 31 45 mA
(Figure 5 Figure 6 ),
TA=−40°C to +85°C
ICCTZ Transmitter Supply Current, Power PWR DWN = Low, 10 55 µA
Down Driver Outputs in TRI-STATE®under
Power Down Mode
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current, Worst CL= 8 pF, Worst f = 32.5 MHz 49 65 mA
Case Case Pattern f = 37.5 MHz 53 70 mA
(Figure 4 Figure 7 ),f = 65 MHz 78 105 mA
TA=−40°C to +85°C
ICCRG Receiver Supply Current, 16 CL= 8 pF, 16 f = 32.5 MHz 28 45 mA
Grayscale Grayscale Pattern f = 37.5 MHz 30 47 mA
(Figure 5 Figure 7 ),f = 65 MHz 43 60 mA
TA=−40°C to +85°C
ICCRZ Receiver Supply Current, Power PWR DWN = Low, Receiver Outputs 10 55 µA
Down Stay Low during Power Down Mode
(1) VOS previously referred as VCM.
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SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
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Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol Parameter Min Typ Max Unit
LLHT LVDS Low-to-High Transition Time (Figure 6 )0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time (Figure 6 )0.75 1.5 ns
TCIT TxCLK IN Transition Time (Figure 8 )5 ns
TCCS TxOUT Channel-to-Channel Skew (Figure 9 )250 ps
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 20 )f = 65 MHz −0.4 0 0.3 ns
TPPos1 Transmitter Output Pulse Position for Bit 1 1.8 2.2 2.5 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 4.0 4.4 4.7 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 6.2 6.6 6.9 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.4 8.8 9.1 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.6 11.0 11.3 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.8 13.2 13.5 ns
TCIP TxCLK IN Period (Figure 10)15 T 50 ns
TCIH TxCLK IN High Time (Figure 10)0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (Figure 10)0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN (Figure 10 )f = 65 MHz 2.5 ns
THTC TxIN Hold to TxCLK IN (Figure 10 )0 ns
TCCD TxCLK IN to TxCLK OUT Delay at 25°C, VCC = 3.3V (Figure 12 )3.0 3.7 5.5 ns
TPLLS Transmitter Phase Lock Loop Set (Figure 14 )10 ms
TPDD Transmitter Power Down Delay (Figure 18 )100 ns
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol Parameter Min Typ Max Unit
CLHT CMOS/TTL Low-to-High Transition Time (Figure 7 )2.2 5.0 ns
CHLT CMOS/TTL High-to-Low Transition Time (Figure 7 )2.2 5.0 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 21 )f = 65 MHz 0.7 1.1 1.4 ns
RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns
RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns
RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns
RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns
RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns
RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns
RSKM RxIN Skew Margin (1) (Figure 22 )f = 65 MHz 400 ps
RCOP RxCLK OUT Period (Figure 11)15 T 50 ns
RCOH RxCLK OUT High Time (Figure 11 )f = 65 MHz 7.3 8.6 ns
RCOL RxCLK OUT Low Time (Figure 11)f = 65 MHz 3.45 4.9 ns
RSRC RxOUT Setup to RxCLK OUT (Figure 11 )f = 65 MHz 2.5 6.9 ns
RHRC RxOUT Hold to RxCLK OUT (Figure 11 )f = 65 MHz 2.5 5.7 ns
RCCD RxCLK IN to RxCLK OUT Delay at 25°C, VCC = 3.3V (Figure 13 )5.0 7.1 9.0 ns
RPLLS Receiver Phase Lock Loop Set (Figure 15 )10 ms
RPDD Receiver Power Down Delay (Figure 19 )1 µs
(1) Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter
pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows
for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
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f
f / 16
f / 8
f / 4
f / 2
Steady State, Low
Steady State, Low
f / 16
f / 8
f / 4
f / 2
Steady State, Low
Steady State, Low
f / 16
f / 8
f / 4
f / 2
Steady State, Low
Steady State, Low
Steady State, High
Steady State, High
Steady State, High
TxCLK IN / RxCLK OUT
TxIN0 / RxOUT0
TxIN1 / RxOUT1
TxIN2 / RxOUT2
TxIN3 / RxOUT3
TxIN4 / RxOUT4
TxIN5 / RxOUT5
TxIN6 / RxOUT6
TxIN7 / RxOUT7
TxIN8 / RxOUT8
TxIN9 / RxOUT9
TxIN10 / RxOUT10
TxIN11 / RxOUT11
TxIN12 / RxOUT12
TxIN13 / RxOUT13
TxIN14 / RxOUT14
TxIN15 / RxOUT15
TxIN16 / RxOUT16
TxIN17 / RxOUT17
TxIN18 / RxOUT18
TxIN19 / RxOUT19
TxIN20 / RxOUT20
Dot Clk
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
HSYNC
VSYNC
ENA
Device Pin Name Signal Signal Pattern Signal Frequency
DS90C363, DS90CF364
www.ti.com
SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
AC Timing Diagrams
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
B. Figure 4 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Figure 4. “Worst Case” Test Pattern
A. The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
B. The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
C. Figure 4 and Figure 5 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
D. Recommended pin to signal mapping. Customer may choose to define differently.
Figure 5. “16 Grayscale” Test Pattern
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AC Timing Diagrams (continued)
Figure 6. DS90C363 (Transmitter) LVDS Output Load and Transition Times
Figure 7. DS90CF364 (Receiver) CMOS/TTL Output Load and Transition Times
Figure 8. DS90C363 (Transmitter) Input Clock Transition Time
Measurements at Vdiff=0V
TCCS measured between earliest and latest LVDS edges
TxCLK Differential Low →High Edge
Figure 9. DS90C363 (Transmitter) Channel-to-Channel Skew
Figure 10. DS90C363 (Transmitter) Setup/Hold and High/Low Times
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SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
AC Timing Diagrams (continued)
Figure 11. DS90CF364 (Receiver) Setup/Hold and High/Low Times
Figure 12. DS90C363 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
Figure 13. DS90CF364 (Receiver) Clock In to Clock Out Delay
Figure 14. DS90C363 (Transmitter) Phase Lock Loop Set Time
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AC Timing Diagrams (continued)
Figure 15. DS90CF364 (Receiver) Phase Lock Loop Set Time
Figure 16. Seven Bits of LVDS in One Clock Cycle
Figure 17. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
Figure 18. Transmitter Power Down Delay
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SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
AC Timing Diagrams (continued)
Figure 19. Receiver Power Down Delay
Figure 20. Transmitter LVDS Output Pulse Position Measurement
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AC Timing Diagrams (continued)
Figure 21. Receiver LVDS Input Strobe Position
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
ISI is dependent on interconnect length; may be zero.
Figure 22. Receiver LVDS Input Skew Margin
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SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
PIN DESCRIPTIONS
DS90C363 Pin Descriptions — FPD Link Transmitter
Pin Name I/O No. Description
TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME and DRDY
(also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+ O 3 Positive LVDS differentiaI data output.
TxOUT−O 3 Negative LVDS differential data output.
FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
R_FB I 1 Programmable strobe select.
RTxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT−O 1 Negative LVDS differential clock output.
PWR DWN I 1 TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down.
VCC I 3 Power supply pins for TTL inputs.
GND I 4 Ground pins for TTL inputs.
PLL V CC I 1 Power supply pin for PLL.
PLL GND I 2 Ground pins for PLL.
LVDS V CC I 1 Power supply pin for LVDS outputs.
LVDS GND I 3 Ground pins for LVDS outputs.
DS90CF364 Pin Descriptions — FPD Link Receiver
Pin Name I/O No. Description
RxIN+ I 3 Positive LVDS differentiaI data inputs.
RxIN−I 3 Negative LVDS differential data inputs.
RxOUT O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN−I 1 Negative LVDS differential clock input.
FPSHIFT OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
PWR DWN I 1 TTL level input. When asserted (low input) the receiver outputs are low.
VCC I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL V CC I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS V CC I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.
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SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
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Pin Diagrams
Figure 23. DS90C363 Figure 24. DS90CF364
See Package Number DGG (R-PDSO-G48) See Package Number DGG (R-PDSO-G48)
Truth Table
Table 1. Programmable Transmitter
Pin Condition Strobe Status
R_FB R_FB = VCC Rising edge strobe
R_FB R_FB = GND Falling edge strobe
APPLICATIONS INFORMATION
The DS90C363 and DS90CF364 are backward compatible with the existing 5V FPD Link transmitter/receiver pair
(DS90CF563 and DS90CF564). To upgrade from a 5V to a 3.3V system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to the VCC, LVDS VCC and PLL V CC of both the
transmitter and receiver devices. This change may enable the removal of a 5V supply from the system, and
power may be supplied from an existing 3V power source.
2. The DS90C363 (transmitter) incorporates a rise/fall strobe select pin. This select function is on pin 14,
formerly a VCC connection on the 5V products. When the rise/fall strobe select pin is connected to V CC, the
part is configured with a rising edge strobe. In a system currently using a 5V rising edge strobe transmitter
(DS90CR563), no layout changes are required to accommodate the new rise/fall select pin on the 3.3V
transmitter. The VCC signal may remain at pin 14, and the device will be configured with a rising edge strobe.
–When converting from a 5V falling edge transmitter (DS90CF563) to the 3V transmitter a minimal
board layout change is necessary. The 3.3V transmitter will not be configured with a falling edge strobe
if VCC remains connected to the select pin. To guarantee the 3.3V transmitter functions with a falling edge
strobe pin 14 should be connected to ground OR left unconnected. When not connected (left open) and
internal pull-down resistor ties pin 14 to ground, thus configuring the transmitter with a falling edge strobe.
3. The DS90C363 transmitter input and control inputs accept 3.3V TTL/CMOS levels. They are not 5V tolerant.
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SNLS123C –SEPTEMBER 1999–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS90C363MTD NRND TSSOP DGG 48 38 Non-RoHS
& Green Call TI Call TI DS90C363MTD
>B
DS90C363MTD/NOPB NRND TSSOP DGG 48 38 RoHS & Green SN Level-2-260C-1 YEAR DS90C363MTD
>B
DS90C363MTDX/NOPB NRND TSSOP DGG 48 1000 RoHS & Green SN Level-2-260C-1 YEAR DS90C363MTD
>B
DS90CF364MTD/NOPB ACTIVE TSSOP DGG 48 38 RoHS & Green SN Level-2-260C-1 YEAR -40 to 85 DS90CF364MTD
>B
DS90CF364MTDX/NOPB ACTIVE TSSOP DGG 48 1000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 85 DS90CF364MTD
>B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS90C363MTDX/NOPB TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1
DS90CF364MTDX/NOPB TSSOP DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS90C363MTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0
DS90CF364MTDX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
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Pack Materials-Page 2
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PACKAGE OUTLINE
C
8.3
7.9 TYP
1.2
1.0
46X 0.5
48X 0.27
0.17
2X
11.5
(0.15) TYP
0 - 8 0.15
0.05
0.25
GAGE PLANE
0.75
0.50
A
12.6
12.4
NOTE 3
B6.2
6.0
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
148
0.08 C A B
25
24
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.350
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EXAMPLE BOARD LAYOUT
(7.5)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
48X (1.5)
48X (0.3)
46X (0.5)
(R0.05)
TYP
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
24 25
48
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(7.5)
46X (0.5)
48X (0.3)
48X (1.5)
(R0.05) TYP
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
24 25
48
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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