MRF1513NT1
1
RF Device Data
Freescale Semiconductor
RF Power Field Effect Transistor
N-Channel Enhancement-Mode Lateral MOSFET
Designed for broadband commercial and industrial applications with frequen-
cies to 520 MHz. The high gain and broadband performance of this device
make it ideal for large-signal, common source amplifier applications in 7.5 volt
portable and 12.5 volt mobile FM equipment.
•Specified Performance @ 520 MHz, 12.5 Volts
Output Power — 3 Watts
Power Gain — 15 dB
Efficiency — 65%
•Capable of Handling 20:1 VSWR, @ 15.5 Vdc,
520 MHz, 2 dB Overdrive
Features
•Excellent Thermal Stability
•Characterized with Series Equivalent Large-Signal
Impedance Parameters
•N Suffix Indicates Lead-Free Terminations. RoHS Compliant.
•In Tape and Reel. T1 Suffix = 1,000 Units per 12 mm,
7 Inch Reel.
Table 1. Maximum Ratings
Rating Symbol Value Unit
Drain-Source Voltage VDSS -0.5, +40 Vdc
Gate- Source Voltage VGS ±20 Vdc
Drain Current — Continuous ID2 Adc
Total Device Dissipation @ TC = 25°C (1)
Derate above 25°C
PD31.25
0.25
W
W/°C
Storage Temperature Range Tstg - 65 to +150 °C
Operating Junction Temperature TJ150 °C
Table 2. Thermal Characteristics
Characteristic Symbol Value (2) Unit
Thermal Resistance, Junction to Case RθJC 4°C/W
Table 3. Moisture Sensitivity Level
Test Methodology Rating Package Peak Temperature Unit
Per JESD 22- A113, IPC/JEDEC J- STD- 020 1 260 °C
1. Calculated based on the formula PD =
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
NOTE - CAUTION - MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
Document Number: MRF1513N
Rev. 11, 6/2008
Freescale Semiconductor
Technical Data
MRF1513NT1
520 MHz, 3 W, 12.5 V
LATERAL N-CHANNEL
BROADBAND
RF POWER MOSFET
CASE 466- 03, STYLE 1
PLD- 1.5
PLASTIC
G
D
S
TJ–TC
RθJC
Freescale Semiconductor, Inc., 2008. All rights reserved.
2
RF Device Data
Freescale Semiconductor
MRF1513NT1
Table 4. Electrical Characteristics (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Off Characteristics
Zero Gate Voltage Drain Current
(VDS = 40 Vdc, VGS = 0 Vdc)
IDSS — — 1 µAdc
Gate- Source Leakage Current
(VGS = 10 Vdc, VDS = 0 Vdc)
IGSS — — 1 µAdc
On Characteristics
Gate Threshold Voltage
(VDS = 12.5 Vdc, ID = 60 µA)
VGS(th) 1 1.7 2.1 Vdc
Drain- Source On- Voltage
(VGS = 10 Vdc, ID = 500 mAdc)
VDS(on) — 0.65 — Vdc
Dynamic Characteristics
Input Capacitance
(VDS = 12.5 Vdc, VGS = 0, f = 1 MHz)
Ciss — 33 — pF
Output Capacitance
(VDS = 12.5 Vdc, VGS = 0, f = 1 MHz)
Coss — 16.5 — pF
Reverse Transfer Capacitance
(VDS = 12.5 Vdc, VGS = 0, f = 1 MHz)
Crss — 2.2 — pF
Functional Tests (In Freescale Test Fixture)
Common-Source Amplifier Power Gain
(VDD = 12.5 Vdc, Pout = 3 Watts, IDQ = 50 mA, f = 520 MHz)
Gps — 15 — dB
Drain Efficiency
(VDD = 12.5 Vdc, Pout = 3 Watts, IDQ = 50 mA, f = 520 MHz)
η— 65 — %
MRF1513NT1
3
RF Device Data
Freescale Semiconductor
N1
Figure 1. 450 - 520 MHz Broadband Test Circuit
VDD
C7 R4
C8
C6
R3
RF
INPUT
RF
OUTPUT
Z3 Z4
Z7
C1
C4
C13
DUT
Z8 Z9 Z10
Z5 Z6
L1
N2
C17
B2
+
C11C10
B1, B2 Short Ferrite Beads, Fair Rite Products
#2743021446
C1, C13 240 pF, 100 mil Chip Capacitors
C2, C3, C4, C10,
C11, C12 0 to 20 pF Trimmer Capacitors
C5, C6, C17 120 pF, 100 mil Chip Capacitors
C7, C14 10 mF, 50 V Electrolytic Capacitors
C8, C15 1,200 pF, 100 mil Chip Capacitors
C9, C16 0.1 mF, 100 mil Chip Capacitors
L1 55.5 nH, 5 Turn, Coilcraft
N1, N2 Type N Flange Mounts
R1, R3 15 Ω Chip Resistors (0805)
R2 1 kΩ, 1/8 W Resistor
R4 33 kΩ, 1/8 W Resistor
Z1 0.236″ x 0.080″ Microstrip
Z2 0.981″ x 0.080″ Microstrip
Z3 0.240″ x 0.080″ Microstrip
Z4 0.098″ x 0.080″ Microstrip
Z5 0.192″ x 0.080″ Microstrip
Z6, Z7 0.260″ x 0.223″ Microstrip
Z8 0.705″ x 0.080″ Microstrip
Z9 0.342″ x 0.080″ Microstrip
Z10 0.347″ x 0.080″ Microstrip
Z11 0.846″ x 0.080″ Microstrip
Board Glass Teflon, 31 mils, 2 oz. Copper
Z2
C3
R1
C5
VGG
C14
+
C9 B1
R2
C15C16
Z1
C2
Z11
C12
TYPICAL CHARACTERISTICS, 450 - 520 MHz
Pout, OUTPUT POWER (WATTS)
IRL, INPUT RETURN LOSS (dB)
−5
−15
−20
−10
10
0
5
Figure 2. Output Power versus Input Power
Pin, INPUT POWER (WATTS)
1
Figure 3. Input Return Loss
versus Output Power
0.10
P
out, OUTPUT POWER (WATTS)
0
3
0.05
2
520 MHz
470 MHz
500 MHz
0.15 0.20
0
5
450 MHz
520 MHz
470 MHz
500 MHz
450 MHz
4
234
VDD = 12.5 Vdc
VDD = 12.5 Vdc
4
RF Device Data
Freescale Semiconductor
MRF1513NT1
TYPICAL CHARACTERISTICS, 450 - 520 MHz
2
Pout, OUTPUT POWER (WATTS)
50
0
Eff, DRAIN EFFICIENCY (%)
30
60
40
31
500 MHz
520 MHz 470 MHz
Eff, DRAIN EFFICIENCY (%)
Figure 4. Gain versus Output Power
Pout, OUTPUT POWER (WATTS)
11
10
14
Figure 5. Drain Efficiency versus Output Power
1
GAIN (dB)
0
Figure 6. Output Power versus Biasing Current
6
IDQ, BIASING CURRENT (mA)
1
Figure 7. Drain Efficiency versus
Biasing Current
70
IDQ, BIASING CURRENT (mA)
45
Figure 8. Output Power versus Supply Voltage
8
VDD, SUPPLY VOLTAGE (VOLTS)
0
Figure 9. Drain Efficiency versus Supply Voltage
VDD, SUPPLY VOLTAGE (VOLTS)
20
12
11 8
0
40
60
60
4000
5
100 600
80
2
3
12
16
200
50
5
13
P
out, OUTPUT POWER (WATTS)
200 600400100
P
out, OUTPUT POWER (WATTS)
9151610 91011 16
65
55
1
2
Eff, DRAIN EFFICIENCY (%)
50
70
500 MHz
520 MHz
470 MHz
450 MHz
450 MHz
500 MHz
520 MHz
470 MHz
450 MHz
500 MHz
520 MHz
470 MHz
450 MHz
500 MHz
520 MHz
470 MHz
450 MHz
500 MHz
520 MHz
470 MHz
450 MHz
VDD = 12.5 Vdc
Pin = 20.3 dBm
Pin = 20.3 dBm
IDQ = 50 mA
VDD = 12.5 Vdc
Pin = 20.3 dBm
Pin = 20.3 dBm
IDQ = 50 mA
VDD = 12.5 Vdc
234
15
45
20
70
VDD = 12.5 Vdc
500
4
5
500
40
1412 13
3
4
1513 14
300 300
30
MRF1513NT1
5
RF Device Data
Freescale Semiconductor
Figure 10. 400 - 470 MHz Broadband Test Circuit
VDD
C7 R4
C8
C6
R3
RF
INPUT
RF
OUTPUT
Z2 Z3 Z4
Z7
C1
C3
C12
DUT
Z8 Z10
Z5 Z6
L1
Z9 N2
C16
B2
N1
+
C11
B1, B2 Short Ferrite Bead, Fair Rite Products
#2743021446
C1, C12 330 pF, 100 mil Chip Capacitors
C2, C3, C4,
C10, C11 1 to 20 pF Trimmer Capacitors
C5, C6, C16 120 pF, 100 mil Chip Capacitors
C7, C13 10 µF, 50 V Electrolytic Capacitors
C8, C14 1,200 pF, 100 mil Chip Capacitors
C9, C15 0.1 mF, 100 mil Chip Capacitors
L1 55.5 nH, 5 Turn, Coilcraft
N1, N2 Type N Flange Mounts
R1 15 Ω Chip Resistor (0805)
R2 1 kΩ, 1/8 W Resistor
R3 15 Ω Chip Resistor (0805)
R4 33 kΩ, 1/8 W Resistor
Z1 0.253″ x 0.080″ Microstrip
Z2 0.958″ x 0.080″ Microstrip
Z3 0.247″ x 0.080″ Microstrip
Z4 0.193″ x 0.080″ Microstrip
Z5 0.132″ x 0.080″ Microstrip
Z6, Z7 0.260″ x 0.223″ Microstrip
Z8 0.494″ x 0.080″ Microstrip
Z9 0.941″ x 0.080″ Microstrip
Z10 0.452″ x 0.080″ Microstrip
Board Glass Teflon, 31 mils, 2 oz. Copper
Z1
C2
C10
R1
C5
VGG
C13
+
C9 B1
R2
C14C15
C4
TYPICAL CHARACTERISTICS, 400 - 470 MHz
Pout, OUTPUT POWER (WATTS)
IRL, INPUT RETURN LOSS (dB)
−5
−15
−20
−10
20
0
1
Figure 11. Output Power versus Input Power
Pin, INPUT POWER (WATTS)
2
Figure 12. Input Return Loss
versus Output Power
P
out, OUTPUT POWER (WATTS)
0 0.080.02
1
440 MHz
470 MHz
0.06 0.120.04
0
5
400 MHz
3
470 MHz
400 MHz
440 MHz
0.10
3
4
45
VDD = 12.5 Vdc
VDD = 12.5 Vdc
6
RF Device Data
Freescale Semiconductor
MRF1513NT1
TYPICAL CHARACTERISTICS, 400 - 470 MHz
440 MHz
2
Pout, OUTPUT POWER (WATTS)
50
0
70
04
Eff, DRAIN EFFICIENCY (%)
30
60
40
31
Eff, DRAIN EFFICIENCY (%)
Figure 13. Gain versus Output Power
Pout, OUTPUT POWER (WATTS)
13
12
16
Figure 14. Drain Efficiency versus Output
Power
2
GAIN (dB)
0
Figure 15. Output Power versus
Biasing Current
6
IDQ, BIASING CURRENT (mA)
1
Figure 16. Drain Efficiency versus
Biasing Current
70
IDQ, BIASING CURRENT (mA)
45
Figure 17. Output Power versus
Supply Voltage
8
VDD, SUPPLY VOLTAGE (VOLTS)
0
Figure 18. Drain Efficiency versus
Supply Voltage
VDD, SUPPLY VOLTAGE (VOLTS)
30
12
12 8
0
60
70
60
4000
5
100 600
80
2
3
14
18
200
50
5
15
P
out, OUTPUT POWER (WATTS)
200 600400300
P
out, OUTPUT POWER (WATTS)
1391611 91011 16
31
65
55
1
3
Eff, DRAIN EFFICIENCY (%)
470 MHz
440 MHz
400 MHz
470 MHz
440 MHz
400 MHz
470 MHz
440 MHz
400 MHz
470 MHz
440 MHz
400 MHz
470 MHz
440 MHz
400 MHz 470 MHz
400 MHz
VDD = 12.5 Vdc
Pin = 18.7 dBm
Pin = 18.7 dBm
IDQ = 50 mA
VDD = 12.5 Vdc
Pin = 18.7 dBm
Pin = 18.7 dBm
IDQ = 50 mA
17
20
10
5
500
5
4
500
40
10 14 15
2
4
50
40
20
1513 14
VDD = 12.5 Vdc
VDD = 12.5 Vdc
4
100 300
MRF1513NT1
7
RF Device Data
Freescale Semiconductor
Figure 19. 135 - 175 MHz Broadband Test Circuit
VDD
C7 R4
C8
C6
R3
RF
INPUT
RF
OUTPUT
Z2
Z6
C1
C13
DUT
Z8 Z9 Z10
Z4 Z5
L4
N2
C17
B2
N1
+
C11
C4
B1, B2 Short Ferrite Beads, Fair Rite Products
#2743021446
C1, C13 330 pF, 100 mil Chip Capacitors
C2, C4, C10, C12 0 to 20 pF Trimmer Capacitors
C3 12 pF, 100 mil Chip Capacitor
C5 130 pF, 100 mil Chip Capacitor
C6, C17 120 pF, 100 mil Chip Capacitors
C7, C14 10 µF, 50 V Electrolytic Capacitors
C8, C15 1,000 pF, 100 mil Chip Capacitors
C9, C16 0.1 µF, 100 mil Chip Capacitors
C11 18 pF, 100 mil Chip Capacitor
L1 26 nH, 4 Turn, Coilcraft
L2 8 nH, 3 Turn, Coilcraft
L3 55.5 nH, 5 Turn, Coilcraft
L4 33 nH, 5 Turn, Coilcraft
N1, N2 Type N Flange Mounts
R1 15 W Chip Resistor (0805)
R2 56 W, 1/8 W Chip Resistor
R3 10 W, 1/8 W Chip Resistor
R4 33 kW, 1/8 W Chip Resistor
Z1 0.115″ x 0.080″ Microstrip
Z2 0.230″ x 0.080″ Microstrip
Z3 1.034″ x 0.080″ Microstrip
Z4 0.202″ x 0.080″ Microstrip
Z5, Z6 0.260″ x 0.223″ Microstrip
Z7 1.088″ x 0.080″ Microstrip
Z8 0.149″ x 0.080″ Microstrip
Z9 0.171″ x 0.080″ Microstrip
Z10 0.095″ x 0.080″ Microstrip
Board Glass Teflon, 31 mils, 2 oz. Copper
Z1
VGG
C14
+
C9 B1
R2
C15C16
L3
C12
L1
C10
R1
C5
Z3
C2
C3
Z7 L2
TYPICAL CHARACTERISTICS, 135 - 175 MHz
Pout, OUTPUT POWER (WATTS)
IRL, INPUT RETURN LOSS (dB)
−5
−15
−20
−10
20
0
1
Figure 20. Output Power versus Input Power
Pin, INPUT POWER (WATTS)
1
Figure 21. Input Return Loss
versus Output Power
0.10
P
out, OUTPUT POWER (WATTS)
0
3
0.15
2
135 MHz
175 MHz
0.200.05
0
5
155 MHz
3
135 MHz
175 MHz
155 MHz
4
45
VDD = 12.5 Vdc VDD = 12.5 Vdc
8
RF Device Data
Freescale Semiconductor
MRF1513NT1
TYPICAL CHARACTERISTICS, 135 - 175 MHz
155 MHz
Pout, OUTPUT POWER (WATTS)
50
0
0
Eff, DRAIN EFFICIENCY (%)
30
60
40
3
Eff, DRAIN EFFICIENCY (%)
Figure 22. Gain versus Output Power
Pout, OUTPUT POWER (WATTS)
13
12
17
Figure 23. Drain Efficiency versus Output
Power
2
GAIN (dB)
0
Figure 24. Output Power versus
Biasing Current
6
IDQ, BIASING CURRENT (mA)
Figure 25. Drain Efficiency versus
Biasing Current
80
IDQ, BIASING CURRENT (mA)
Figure 26. Output Power versus
Supply Voltage
8
VDD, SUPPLY VOLTAGE (VOLTS)
0
Figure 27. Drain Efficiency versus
Supply Voltage
VDD, SUPPLY VOLTAGE (VOLTS)
20
9
13 8
0
40
60
60
4000
5
300 600
80
2
4
3
14
18
200
50
4
16
P
out, OUTPUT POWER (WATTS)
200 600400100
P
out, OUTPUT POWER (WATTS)
1291611 1211 13 16
31
65
55
2
1
Eff, DRAIN EFFICIENCY (%)
50
70
155 MHz
135 MHz
175 MHz
20
10
135 MHz
175 MHz
155 MHz
135 MHz
175 MHz
155 MHz
135 MHz
175 MHz
155 MHz
135 MHz
175 MHz 155 MHz
135 MHz 175 MHz
VDD = 12.5 Vdc
Pin = 19.5 dBm
Pin = 19.5 dBm
IDQ = 50 mA
VDD = 12.5 Vdc
Pin = 19.5 dBm
Pin = 19.5 dBm
IDQ = 50 mA
5
15
4152
70
5
500 500
10 1514
4
3
10 14 15
VDD = 12.5 Vdc
VDD = 12.5 Vdc
300 100
70
75
30
MRF1513NT1
9
RF Device Data
Freescale Semiconductor
TYPICAL CHARACTERISTICS
210
108
TJ, JUNCTION TEMPERATURE (°C)
This above graph displays calculated MTTF in hours x ampere2
drain current. Life tests at elevated temperatures have correlated to
better than ±10% of the theoretical prediction for metal failure. Divide
MTTF factor by ID2 for MTTF in a particular application.
107
106
MTTF FACTOR (HOURS X AMPS2)
90 110 130 150 170 190100 120 140 160 180 200
Figure 28. MTTF Factor versus Junction Temperature
10
RF Device Data
Freescale Semiconductor
MRF1513NT1
Zin = Complex conjugate of source
impedance with parallel 15 Ω
resistor and 130 pF capacitor in
series with gate. (See Figure 19).
ZOL* = Complex conjugate of the load
impedance at given output power,
voltage, frequency, and ηD > 50 %.
Note: ZOL* was chosen based on tradeoffs between gain, drain efficiency, and device stability.
Figure 29. Series Equivalent Input and Output Impedance
Zin = Complex conjugate of source
impedance with parallel 15 Ω
resistor and 130 pF capacitor in
series with gate. (See Figure 10).
ZOL* = Complex conjugate of the load
impedance at given output power,
voltage, frequency, and ηD > 50 %.
f
MHz
Zin
Ω
ZOL*
Ω
450 4.64 +j5.82 13.11 +j2.15
Zin = Complex conjugate of source
impedance with parallel 15 Ω
resistor and 120 pF capacitor in
series with gate. (See Figure 1).
ZOL* = Complex conjugate of the load
impedance at given output power,
voltage, frequency, and ηD > 50 %.
VDD = 12.5 V, IDQ = 50 mA, Pout = 3 W
470 5.42 +j6.34 12.16 +j3.26
500 5.96 +j5.45 11.03 +j5.42
520 4.28 +j4.94 10.99 +j7.18
f
MHz
Zin
Ω
ZOL*
Ω
400 4.72 +j4.38 12.57 +j1.88
VDD = 12.5 V, IDQ = 50 mA, Pout = 3 W
440 4.88 +j6.34 11.21 +j5.87
470 3.22 +j5.24 9.82 +j8.63
f
MHz
Zin
Ω
ZOL*
Ω
135 16.55 +j1.82 22.01 +j10.32
VDD = 12.5 V, IDQ = 50 mA, Pout = 3 W
155 15.59 +j5.38 22.03 +j8.07
175 15.55 +j9.43 22.08 +j6.85
Zo = 10 Ω
ZOL*
Zin
f = 175 MHz
135
135
f = 175 MHz
f = 400 MHz
470
f = 400 MHz
470
ZOL*
Zin
Zo = 10 Ω
f = 520 MHz
Zin
450
f = 520 MHz
450
ZOL*
Zin ZOL*
Input
Matching
Network
Device
Under Test
Output
Matching
Network
MRF1513NT1
11
RF Device Data
Freescale Semiconductor
Table 5. Common Source Scattering Parameters (VDD = 12.5 Vdc)
IDQ = 50 mA
f
S11 S21 S12 S22
f
MHz |S11|∠φ |S21|∠φ |S12|∠φ |S22|∠φ
50 0.93 -94 22.09 125 0.044 33 0.77 -81
100 0.81 -131 12.78 101 0.052 6 0.61 -115
200 0.76 -153 6.31 81 0.047 -10 0.59 - 135
300 0.76 -160 3.92 69 0.044 -19 0.64 - 142
400 0.77 -164 2.74 60 0.040 -26 0.70 - 147
500 0.79 -167 1.99 54 0.036 -31 0.75 - 151
600 0.80 -169 1.55 48 0.034 -37 0.80 - 155
700 0.81 -171 1.25 44 0.028 -40 0.82 - 158
800 0.82 -172 1.02 38 0.027 -42 0.86 - 161
900 0.83 -173 0.85 35 0.017 -42 0.88 - 163
1000 0.84 -175 0.70 29 0.018 -49 0.91 -166
IDQ = 500 mA
f
S11 S21 S12 S22
f
MHz |S11|∠φ |S21|∠φ |S12|∠φ |S22|∠φ
50 0.84 -127 32.57 112 0.025 17 0.64 -130
100 0.80 -152 17.23 97 0.025 13 0.64 -153
200 0.78 - 166 8.62 85 0.025 -9 0.65 -163
300 0.78 - 171 5.58 79 0.023 -9 0.67 -166
400 0.78 - 173 4.08 72 0.022 -9 0.69 -166
500 0.78 - 175 3.14 68 0.020 -10 0.71 -167
600 0.79 - 176 2.55 63 0.022 -15 0.74 -168
700 0.79 - 177 2.14 60 0.019 -20 0.76 -168
800 0.80 - 178 1.80 54 0.018 -31 0.79 -170
900 0.81 - 178 1.54 51 0.015 -25 0.80 -170
1000 0.82 -179 1.31 46 0.012 -36 0.81 -172
IDQ = 1 A
f
S11 S21 S12 S22
f
MHz |S11|∠φ |S21|∠φ |S12|∠φ |S22|∠φ
50 0.84 -129 32.57 111 0.023 24 0.61 -137
100 0.80 - 153 17.04 97 0.024 13 0.64 -156
200 0.78 - 167 8.52 85 0.023 5 0.65 -165
300 0.77 - 172 5.53 79 0.020 -7 0.67 -167
400 0.77 - 174 4.06 73 0.020 -11 0.69 - 167
500 0.78 - 175 3.13 69 0.021 -9 0.72 -167
600 0.78 - 177 2.54 64 0.017 -26 0.74 -168
700 0.78 - 177 2.13 60 0.017 -14 0.75 -168
800 0.79 - 178 1.81 55 0.015 -23 0.78 -170
900 0.80 - 178 1.54 51 0.013 -31 0.79 -170
1000 0.80 -179 1.30 46 0.011 -17 0.80 -172
12
RF Device Data
Freescale Semiconductor
MRF1513NT1
APPLICATIONS INFORMATION
DESIGN CONSIDERATIONS
This device is a common-source, RF power, N-Channel
enhancement mode, Lateral Metal-Oxide Semiconductor
Field-Effect Transistor (MOSFET). Freescale Application
Note AN211A, “FETs in Theory and Practice”, is suggested
reading for those not familiar with the construction and char-
acteristics of FETs.
This surface mount packaged device was designed pri-
marily for VHF and UHF portable power amplifier applica-
tions. Manufacturability is improved by utilizing the tape and
reel capability for fully automated pick and placement of
parts. However, care should be taken in the design process
to insure proper heat sinking of the device.
The major advantages of Lateral RF power MOSFETs in-
clude high gain, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mis-
matched loads without suffering damage.
MOSFET CAPACITANCES
The physical structure of a MOSFET results in capacitors
between all three terminals. The metal oxide gate structure
determines the capacitors from gate - to - drain (Cgd), and
gate- to - source (Cgs). The PN junction formed during fab-
rication of the RF MOSFET results in a junction capacitance
from drain-to-source (Cds). These capacitances are charac-
terized as input (Ciss), output (Coss) and reverse transfer
(Crss) capacitances on data sheets. The relationships be-
tween the inter-terminal capacitances and those given on
data sheets are shown below. The Ciss can be specified in
two ways:
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate.
In the latter case, the numbers are lower. However, neither
method represents the actual operating conditions in RF ap-
plications.
Drain
Cds
Source
Gate
Cgd
Cgs
Ciss = Cgd + Cgs
Coss = Cgd + Cds
Crss = Cgd
DRAIN CHARACTERISTICS
One critical figure of merit for a FET is its static resistance
in the full-on condition. This on-resistance, RDS(on), occurs
in the linear region of the output characteristic and is speci-
fied at a specific gate- source voltage and drain current. The
drain-source voltage under these conditions is termed
VDS(on). For MOSFETs, VDS(on) has a positive temperature
coefficient at high temperatures because it contributes to the
power dissipation within the device.
BVDSS values for this device are higher than normally re-
quired for typical applications. Measurement of BVDSS is not
recommended and may result in possible damage to the de-
vice.
GATE CHARACTERISTICS
The gate of the RF MOSFET is a polysilicon material, and
is electrically isolated from the source by a layer of oxide.
The DC input resistance is very high - on the order of 109 Ω
— resulting in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage to
the gate greater than the gate-to-source threshold voltage,
VGS(th).
Gate Voltage Rating — Never exceed the gate voltage
rating. Exceeding the rated VGS can result in permanent
damage to the oxide layer in the gate region.
Gate Termination — The gates of these devices are es-
sentially capacitors. Circuits that leave the gate open- cir-
cuited or floating should be avoided. These conditions can
result in turn-on of the devices due to voltage build-up on
the input capacitor due to leakage currents or pickup.
Gate Protection — These devices do not have an internal
monolithic zener diode from gate- to - source. If gate protec-
tion is required, an external zener diode is recommended.
Using a resistor to keep the gate-to-source impedance low
also helps dampen transients and serves another important
function. Voltage transients on the drain can be coupled to
the gate through the parasitic gate-drain capacitance. If the
gate- to - source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
may be large enough to exceed the gate-threshold voltage
and turn the device on.
DC BIAS
Since this device is an enhancement mode FET, drain cur-
rent flows only when the gate is at a higher potential than the
source. RF power FETs operate optimally with a quiescent
drain current (IDQ), whose value is application dependent.
This device was characterized at IDQ = 50 mA, which is the
suggested value of bias current for typical applications. For
special applications such as linear amplification, IDQ may
have to be selected to optimize the critical parameters.
The gate is a dc open circuit and draws no current. There-
fore, the gate bias circuit may generally be just a simple re-
sistive divider network. Some special applications may
require a more elaborate bias system.
GAIN CONTROL
Power output of this device may be controlled to some de-
gree with a low power dc control signal applied to the gate,
thus facilitating applications such as manual gain control,
ALC/AGC and modulation systems. This characteristic is
very dependent on frequency and load line.
MRF1513NT1
13
RF Device Data
Freescale Semiconductor
MOUNTING
The specified maximum thermal resistance of 4°C/W as-
sumes a majority of the 0.065″ x 0.180″ source contact on
the back side of the package is in good contact with an ap-
propriate heat sink. As with all RF power devices, the goal of
the thermal design should be to minimize the temperature at
the back side of the package. Refer to Freescale Application
Note AN4005/D, “Thermal Management and Mounting Meth-
od for the PLD-1.5 RF Power Surface Mount Package” for
additional information.
AMPLIFIER DESIGN
Impedance matching networks similar to those used with
bipolar transistors are suitable for this device. For examples
see Freescale Application Note AN721, “Impedance
Matching Networks Applied to RF Power Transistors.”
Large-signal impedances are provided, and will yield a good
first pass approximation.
Since RF power MOSFETs are triode devices, they are not
unilateral. This coupled with the very high gain of this device
yields a device capable of self oscillation. Stability may be
achieved by techniques such as drain loading, input shunt
resistive loading, or output to input feedback. The RF test fix-
ture implements a parallel resistor and capacitor in series
with the gate, and has a load line selected for a higher effi-
ciency, lower gain, and more stable operating region.
Two-port stability analysis with this device’s
S-parameters provides a useful tool for selection of loading
or feedback circuitry to assure stable operation. See Free-
scale Application Note AN215A, “RF Small-Signal Design
Using Two- Port Parameters” for a discussion of two port
network theory and stability.
14
RF Device Data
Freescale Semiconductor
MRF1513NT1
PACKAGE DIMENSIONS
0.115
2.92
0.020
0.51
0.115
2.92
mm
inches
0.095
2.41
0.146
3.71
SOLDER FOOTPRINT
CASE 466-03
ISSUE D
NOTES:
1. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1984.
2. CONTROLLING DIMENSION: INCH
3. RESIN BLEED/FLASH ALLOWABLE IN ZONE V, W,
AND X.
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.255 0.265 6.48 6.73
B0.225 0.235 5.72 5.97
C0.065 0.072 1.65 1.83
D0.130 0.150 3.30 3.81
E0.021 0.026 0.53 0.66
F0.026 0.044 0.66 1.12
G0.050 0.070 1.27 1.78
H0.045 0.063 1.14 1.60
K0.273 0.285 6.93 7.24
L0.245 0.255 6.22 6.48
N0.230 0.240 5.84 6.10
P0.000 0.008 0.00 0.20
Q0.055 0.063 1.40 1.60
R0.200 0.210 5.08 5.33
S0.006 0.012 0.15 0.31
U0.006 0.012 0.15 0.31
ZONE V 0.000 0.021 0.00 0.53
ZONE W 0.000 0.010 0.00 0.25
ZONE X 0.000 0.010 0.00 0.25
STYLE 1:
PIN 1. DRAIN
2. GATE
3. SOURCE
4. SOURCE
J0.160 0.180 4.06 4.57
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
A
BD
F
L
R
3
4
21
K
N
ZONE V
ZONE W
ZONE X
GS
H
U
_
10 DRAFT
P
CE
0.35 (0.89) X 45 5
"
YY
Q
VIEW Y- Y
__
4
2
1
3
PLD-1.5
PLASTIC
MRF1513NT1
15
RF Device Data
Freescale Semiconductor
PRODUCT DOCUMENTATION
Refer to the following documents to aid your design process.
Application Notes
•AN211A: Field Effect Transistors in Theory and Practice
•AN215A: RF Small-Signal Design Using Two-Port Parameters
•AN721: Impedance Matching Networks Applied to RF Power Transistors
•AN4005: Thermal Management and Mounting Method for the PLD 1.5 RF Power Surface Mount Package
Engineering Bulletins
•EB212: Using Data Sheet Impedances for RF LDMOS Devices
REVISION HISTORY
The following table summarizes revisions to this document.
Revision Date Description
10 Feb. 2008 •Changed DC Bias IDQ value from 150 to 50 to match Functional Test IDQ specification, p. 12
•Added Product Documentation and Revision History, p. 15
11 June 2008 •Corrected specified performance values for power gain and efficiency on p. 1 to match typical
performance values in the functional test table on p. 2
16
RF Device Data
Freescale Semiconductor
MRF1513NT1
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