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TMS320C6745, TMS320C6747
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor
1.1 Features
1Bit Multiplies, Four 16 x 16-Bit Multiplies, or
• Software Support Eight 8 x 8-Bit Multiplies per Clock Cycle,
– TI DSP/BIOS™ and Complex Multiples
– Chip Support Library and DSP Library – Instruction Packing Reduces Code Size
• 375- and 456-MHz TMS320C674x VLIW DSP – All Instructions Conditional
• C674x Instruction Set Features – Hardware Support for Modulo Loop
– Superset of the C67x+ and C64x+ ISAs Operation
– Up to 3648 MIPS and 2736 MFLOPS C674x – Protected Mode Operation
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – Exceptions Support for Error Detection and
– 8-Bit Overflow Protection Program Redirection
– Bit-Field Extract, Set, Clear • 128KB of RAM Shared Memory (TMS320C6747
– Normalization, Saturation, Bit-Counting Only)
– Compact 16-Bit Instructions • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
• C674x Two-Level Cache Memory Architecture • Two External Memory Interfaces:
– 32KB of L1P Program RAM/Cache – EMIFA
– 32KB of L1D Data RAM/Cache • NOR (8- or 16-Bit-Wide Data)
– 256KB of L2 Unified Mapped RAM/Cache • NAND (8- or 16-Bit-Wide Data)
– Flexible RAM/Cache Partition (L1 and L2) • 16-Bit SDRAM with 128-MB Address Space
• Enhanced Direct Memory Access Controller 3 (TMS320C6747 Only)
(EDMA3): – EMIFB
– 2 Transfer Controllers • 32-Bit or 16-Bit SDRAM with 256-MB
– 32 Independent DMA Channels Address Space (TMS320C6747)
– 8 Quick DMA Channels • 16-Bit SDRAM with 128-MB Address Space
(TMS320C6745)
– Programmable Transfer Burst Size • Three Configurable 16550-Type UART Modules:
• TMS320C674x Fixed- and Floating-Point VLIW
DSP Core – UART0 with Modem Control Signals
– Load-Store Architecture with Nonaligned – Autoflow Control Signals (CTS, RTS) on UART0
Support Only
– 64 General-Purpose Registers (32-Bit) – 16-Byte FIFO
– Six ALU (32- and 40-Bit) Functional Units – 16x or 13x Oversampling Option
• Supports 32-Bit Integer, SP (IEEE Single • LCD Controller (TMS320C6747 Only)
Precision/32-Bit) and DP (IEEE Double • Two Serial Peripheral Interfaces (SPIs) Each with
Precision/64-Bit) Floating Point One Chip Select
• Supports up to Four SP Additions Per Clock, • Multimedia Card (MMC)/Secure Digital (SD) Card
Four DP Additions Every 2 Clocks Interface with Secure Data I/O (SDIO)
• Supports up to Two Floating-Point (SP or • Two Master and Slave Inter-Integrated Circuit (I2C
DP) Reciprocal Approximation (RCPxP) and Bus™)
Square-Root Reciprocal Approximation • One Host-Port Interface (HPI) with 16-Bit-Wide
(RSQRxP) Operations Per Cycle Muxed Address/Data Bus for High Bandwidth
– Two Multiply Functional Units (TMS320C6747 Only)
• Mixed-Precision IEEE Floating Point Multiply • Programmable Real-Time Unit Subsystem
Supported up to: (PRUSS)
– 2 SP x SP -> SP Per Clock – Two Independent Programmable Realtime Unit
– 2 SP x SP -> DP Every Two Clocks (PRU) Cores
– 2 SP x DP -> DP Every Three Clocks • 32-Bit Load and Store RISC Architecture
– 2 DP x DP -> DP Every Four Clocks • 4KB of Instruction RAM per Core
• Fixed-Point Multiply Supports Two 32 x 32- • 512 Bytes of Data RAM per Core
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
www.ti.com
• PRUSS can be Disabled via Software to – RMII Media-Independent Interface
Save Power – Management Data I/O (MDIO) Module
– Standard Power-Management Mechanism • Real-Time Clock with 32-kHz Oscillator and
Separate Power Rail (TMS320C6747 Only)
• Clock Gating • One 64-Bit General-Purpose Timer (Configurable
• Entire Subsystem Under a Single PSC Clock as Two 32-Bit Timers)
Gating Domain • One 64-Bit General-Purpose Watchdog Timer
– Dedicated Interrupt Controller (Configurable as Two 32-Bit General-Purpose
– Dedicated Switched Central Resource Timers)
• USB 1.1 OHCI (Host) with Integrated PHY (USB1) • Three Enhanced Pulse Width Modulators
(TMS320C6747 Only) (eHRPWMs):
• USB 2.0 OTG Port with Integrated PHY (USB0) – Dedicated 16-Bit Time-Base Counter with
– USB 2.0 High- and Full-Speed Client Period and Frequency Control
(TMS320C6747) – 6 Single Edge, 6 Dual Edge Symmetric, or 3
– USB 2.0 Full-Speed Client (TMS320C6745) Dual Edge Asymmetric Outputs
– USB 2.0 High-, Full-, and Low-Speed Host – Dead-Band Generation
(TMS320C6747) – PWM Chopping by High-Frequency Carrier
– USB 2.0 Full- and Low-Speed Host – Trip Zone Input
(TMS320C6745) • Three 32-Bit Enhanced Capture (eCAP) Modules:
– High-Speed Functionality Available on – Configurable as 3 Capture Inputs or 3 Auxiliary
TMS320C6747 Device Only Pulse Width Modulator (APWM) Outputs
– End Point 0 (Control) – Single-Shot Capture of up to Four Event Time-
– End Points 1,2,3,4 (Control, Bulk, Interrupt or Stamps
ISOC) RX and TX • Two 32-Bit Enhanced Quadrature Encoder Pulse
• Three Multichannel Audio Serial Ports (McASPs): (eQEP) Modules
– TMS320C6747 Supports 3 McASPs • TMS320C6747 Device:
– TMS320C6745 Supports 2 McASPs – 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)
– Six Clock Zones and 28 Serial Data Pins [ZKB Suffix], 1.0-mm Ball Pitch
– Supports TDM, I2S, and Similar Formats • TMS320C6745 Device:
– DIT-Capable (McASP2) – 176-pin PowerPAD™ Plastic Quad Flat Pack
– FIFO Buffers for Transmit and Receive [PTP suffix], 0.5-mm Pin Pitch
• 10/100 Mbps Ethernet MAC (EMAC): • Commercial, Industrial, Extended, or Automotive
– IEEE 802.3 Compliant (3.3-V I/O Only) Temperature
1.2 Applications
• A/V Receivers • Home Theatre Systems
• Automotive Amplifiers • Professional Audio
• Soundbars • Network Streaming Audio
1.3 Description
The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP
core. It consumes significantly lower power than other members of the TMS320C6000™ platform of
DSPs.
The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design
manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .
The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program
cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-
associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared
between program and data space. L2 memory can be configured as mapped memory, cache, or
combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional
128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting
DSP performance.
2TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Copyright © 2008–2014, Texas Instruments Incorporated
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output
(MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers
and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a
configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-
purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other
peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width
modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit
enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an
asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a
higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the
TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10
Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for
PHY configuration.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE
TMS320C6745 HLQFP (176) 24.00 mm x 24.00 mm
TMS320C6747 BGA (256) 17.00 mm x 17.00 mm
(1) For more information on these devices, see Section 8, Mechanical Packaging and Orderable
Information.
Copyright © 2008–2014, Texas Instruments Incorporated TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal 3
Processor
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Switched Central Resource (SCR)
BOOT ROM
256KB L2 RAM
32KB
L1 RAM
32KB
L1 Pgm
AET
C674x
DSP CPU
DSP Subsystem
JTAG Interface
Serial Interfaces
I C
(2)
2SPI
(2)
UART
(3)
Audio Ports
McASP
w/FIFO
(2)
DMA
Peripherals
External Memory Interfaces
Connectivity
EDMA3
Control Timers
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
(10/100)
EMAC
(RMII)
MDIO
USB2.0
OTG Ctlr
PHY
MMC/SD
(8b)
EMIFA(8b)
NAND/Flash
EMIFB
SDRAM Only
(16b)
GPIO PRU
Subsystem
System Control
Input
Clock(s)
Power/Sleep
Controller
Memory
Protection
Pin
Multiplexing
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer
General-
Purpose
Timer
(Watchdog)
Switched Central Resource (SCR)
BOOT ROM
256KB L2 RAM
32KB
L1 RAM
32KB
L1 Pgm
AET
C674x
DSP CPU
DSP Subsystem
JTAG Interface
Serial Interfaces
I C
(2)
2SPI
(2)
UART
(3)
Audio Ports
McASP
w/FIFO
(3)
DMA
Peripherals
Display Internal Memory
LCD
Ctlr 128KB
RAM
External Memory Interfaces
Connectivity
EDMA3
Control Timers
eHRPWM
(3)
eCAP
(3)
eQEP
(2)
(10/100)
EMAC
(RMII)
MDIO
USB1.1
OHCI Ctlr
PHY
USB2.0
OTG Ctlr
PHY
HPI MMC/SD
(8b)
EMIFA(8b/16B)
NAND/Flash
16b SDRAM
EMIFB
SDRAM Only
(16b/32b)
GPIO PRU
Subsystem
System Control
Input
Clock(s)
Power/Sleep
Controller
Memory
Protection
Pin
Multiplexing
RTC/
32-kHz
OSC
PLL/Clock
Generator
w/OSC
General-
Purpose
Timer
General-
Purpose
Timer
(Watchdog)
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
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1.4 Functional Block Diagram
Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.
Figure 1-1. TMS320C6747 Functional Block Diagram
Note: Not all peripherals are available at the same time due to multiplexing. See Table 3-1 for details on which device
components are available on each device.
Figure 1-2. TMS320C6745 Functional Block Diagram
4TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Copyright © 2008–2014, Texas Instruments Incorporated
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Table of Contents
1 TMS320C6745, TMS320C6747 Fixed- and 6.11 External Memory Interface B (EMIFB) .............. 98
Floating-Point Digital Signal Processor............. 16.12 Memory Protection Units .......................... 106
1.1 Features .............................................. 16.13 MMC / SD / SDIO (MMCSD)....................... 109
1.2 Applications........................................... 26.14 Ethernet Media Access Controller (EMAC)........ 112
1.3 Description............................................ 26.15 Management Data Input/Output (MDIO)........... 117
1.4 Functional Block Diagram ............................ 46.16 Multichannel Audio Serial Ports (McASP0, McASP1,
and McASP2) ...................................... 119
2 Revision History ......................................... 66.17 Serial Peripheral Interface Ports (SPI0, SPI1)..... 132
3 Device Overview ......................................... 86.18 Enhanced Capture (eCAP) Peripheral............. 151
3.1 Device Characteristics................................ 86.19 Enhanced Quadrature Encoder (eQEP)
3.2 Device Compatibility.................................. 9Peripheral .......................................... 154
3.3 DSP Subsystem..................................... 10 6.20 Enhanced High-Resolution Pulse-Width Modulator
3.4 Memory Map Summary ............................. 21 (eHRPWM)......................................... 156
3.5 Pin Assignments .................................... 26 6.21 LCD Controller ..................................... 160
3.6 Terminal Functions.................................. 28 6.22 Timers.............................................. 175
4 Device Configuration.................................. 56 6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1) .. 177
4.1 Boot Modes ......................................... 56 6.24 Universal Asynchronous Receiver/Transmitter
4.2 SYSCFG Module.................................... 57 (UART)............................................. 182
4.3 Pullup/Pulldown Resistors .......................... 59 6.25 USB1 Host Controller Registers (USB1.1 OHCI).. 184
5 Device Operating Conditions ........................ 60 6.26 USB0 OTG (USB2.0 OTG) ........................ 185
5.1 Absolute Maximum Ratings Over Operating Case 6.27 Host-Port Interface (UHPI)......................... 193
Temperature Range 6.28 Power and Sleep Controller (PSC) ................ 200
(Unless Otherwise Noted) ................................. 60 6.29 Programmable Real-Time Unit Subsystem
5.2 Handling Ratings.................................... 60 (PRUSS) ........................................... 203
5.3 Recommended Operating Conditions............... 61 6.30 Emulation Logic.................................... 206
5.4 Notes on Recommended Power-On Hours (POH) .62 6.31 IEEE 1149.1 JTAG ................................ 209
5.5 Electrical Characteristics Over Recommended 6.32 Real Time Clock (RTC) ............................ 211
Ranges of Supply Voltage and Operating Case 7 Device and Documentation Support.............. 214
Temperature (Unless Otherwise Noted) ............ 63 7.1 Device Support..................................... 214
6 Peripheral Information and Electrical
Specifications........................................... 64 7.2 Documentation Support............................ 215
6.1 Parameter Information .............................. 64 7.3 Community Resources............................. 216
6.2 Recommended Clock and Control Signal Transition 7.4 Related Links ...................................... 216
Behavior............................................. 65 7.5 Trademarks ........................................ 216
6.3 Power Supplies...................................... 65 7.6 Electrostatic Discharge Caution ................... 216
6.4 Reset ................................................ 66 7.7 Glossary............................................ 216
6.5 Crystal Oscillator or External Clock Input........... 69 8 Mechanical Packaging and Orderable
6.6 Clock PLLs .......................................... 71 Information............................................. 217
6.7 Interrupts ............................................ 75 8.1 Thermal Data for ZKB ............................. 217
6.8 General-Purpose Input/Output (GPIO).............. 79 8.2 Thermal Data for PTP ............................. 218
6.9 EDMA ............................................... 82 8.3 Supplementary Information About the 176-pin PTP
PowerPAD™ Package............................. 218
6.10 External Memory Interface A (EMIFA) .............. 87 8.4 Packaging Information ............................. 219
Copyright © 2008–2014, Texas Instruments Incorporated Table of Contents 5
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data manual revision history highlights the changes made to the SPRS377E device-specific data
manual to make it an SPRS377F revision.
Scope: Applicable updates to the TMS320C6747/C6745 Fixed- and Floating-Point Digital Signal
Processor device family, specifically relating to the TMS320C6747 and TMS320C6745 devices, which are
all now in the production data (PD) stage of development, have been incorporated.
Revision History
SEE ADDITIONS/MODIFICATIONS/DELETIONS
• Turned on Navigation Icons on top of first page.
• Updated Features, Applications, and Description for consistency and translation.
Global • Moved Trademarks information from first page to within Section 7, Device and Documentation Support.
• Moved ESDS Warning to within Section 7, Device and Documentation Support.
Section 1.1 Deleted Highlights section. Information was duplicated elsewhere in Features.
Features
Section 1.2 Added NEW section.
Applications
Section 1.3 Added NEW Device Information Table.
Description Table 3-2, C674x Cache Registers:
Section 3.3.2.3 • Updated/Changed REGISTER DESCRIPTION for BYTE ADDRESSES 0000, 0020, and 0040 from
C674x CPU "...See the System reference Guide..." to "See the Technical Reference Manual..."
Table 3-21, Universal Serial Bus (USB) Terminal Functions:
Section 3.6 • Updated/Changed USB0_VDDA12 DESCRIPTION from "...must always be connected via a 1 μF
Terminal Functions capacitor..." to "...is recommended to be connected via a 0.22-μFcapacitor..."
Section 3.6.11
Universal Table 3-16, Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions:
Asynchronous • Updated/Changed footnote from "...DSP Reference Guide - Literature Number SPRUFK4..." to "...DSP
Receiver/Transmitter Technical Reference Manual (SPRUH91)..."
s (UART0, UART1,
UART2) Table 3-26, Reserved and No Connect Terminal Functions:
Section 3.6.21
Reserved and No • Updated/Changed RSV4 DESCRIPTION from "...This pin may be tied high or low." to "...For proper
Connect device operation, this pin must be tied low or to CVDD."
Section 3.6.23 Moved to within Section 3.6, Terminal Functions
Unused USB0 Table 3-28, Unused USB0 and USB1 Pin Configurations:
(USB2.0) and USB1 • Updated/Changed USB0_VDDA12 Configuration by combining both Configuration columns and
(USB1.1) Pin changing text to "Internal USB0 PHY output connected to an external..."
Configurations Section 5.2, Handling Ratings:
Section 5
Device Operating • Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling Ratings
Conditions table.
Section 5.4
Notes on Table 5-1, Recommended Power-On Hours:
Recommended • Added Silicon Revision column.
Power-On Hours
(POH) Table 6-22, EMIFA Asynchronous Memory Switching Characteristics:
Section 6.10.6 • Updated/Changed the MIN, NOM, and MAX equations for NO. 3, 10, 15, and 24 from "...(EWC*16)..." to
EMIFA Electrical "...EWC..."
Data/Timing Section 5.3, Recommended Operating Conditions:
• Added "Unless specifically indicated" to "These I/O specifications apply to ..." footnote
6Revision History Copyright © 2008–2014, Texas Instruments Incorporated
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Revision History (continued)
SEE ADDITIONS/MODIFICATIONS/DELETIONS
Table 6-26, EMIFB SDRAM Interface Timing Requirements:
• Updated/Changed Parameter No. 19 from "tsu(DV-CLKH)" to "t(DV-CLKH)"
• Added new column: "CVDD = 1.3V"
• Added new footnote containing "...range rated devices for 456 MHz max CPU operating..."
• Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU
operating ..."
Table 6-27, EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature
Range:
• Updated/Changed table title from "...Switching Characteristics..." to "...Switching Characteristics for
Commercial (Default) Temperature Range"
Section 6.11.3 • Added new footnote containing "...range rated devices for 456 MHz max CPU operating ..."
EMIFB Electrical • Added new footnote containing "...range rated devices for 400/375/300/266/200 MHz max CPU
Data/Timing operating..."
• Updated/Changed CVDD = 1.3V MIN column values for Parameter No. 4, 6, 8, 10, 12, 14, 16, and 18
from "0.9" to "1.1"
• Updated/Changed CVDD = 1.3V MAX column values for Parameter No. 3, 5, 7, 9, 11, 13, 15, and 17
from "5.1" to "4.25"
• Populated CVDD = 1.2V column with values (was empty)
• Updated/Changed Parameter No. 18 from "tena(CLKH-DLZ)" to "t(CLKH-DLZ)"
Table 6-28, EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive
Temperature Ranges:
• Added NEW table
Table 6-45, McASP Registers Accessed Through DMA Port:
Section 6.16
Multichannel Audio • Updated/Changed Read Accesses Register Description from "XBUSEL = 0 in XFMT" to "RBUSEL = 0 in
Serial Ports RFMT"
(McASP0, McASP1, • Updated/Changed Write Accesses Register Description from "RBUSEL = 0 in RFMT" to "XBUSEL = 0 in
and McASP2) XFMT"
Section 7.4 Added NEW section.
Related Links
Section 7.7 Added NEW section.
Glossary
Copyright © 2008–2014, Texas Instruments Incorporated Revision History 7
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3 Device Overview
3.1 Device Characteristics
Table 3-1 provides an overview of the C6745/6747 low power digital signal processor. The table shows
significant features of the device, including the capacity of on-chip RAM, peripherals, and the package
type with pin count.
Table 3-1. Characteristics of the C6745/C6747 Processor
HARDWARE FEATURES C6745 C6747
EMIFB 16bit, up to 128MB SDRAM 16/32bit, up to 256MB SDRAM
Asynchronous (8/16-bit bus width) RAM,
Asynchronous (8-bit bus width) RAM,
EMIFA Flash, 16bit up to 128MB SDRAM, NOR,
Flash, NOR, NAND NAND
Flash Card Interface MMC and SD cards supported.
EDMA3 32 independent channels, 8 QDMA channels, 2 Transfer controllers
2 64-Bit General Purpose (each configurable as 2 separate 32-bit timers, 1 configurable
Timers as Watch Dog)
UART 3 (one with RTS and CTS flow control)
SPI 2 (each with one hardware chip select)
I2C 2 (both Master/Slave)
Multichannel Audio 2 (each with transmit/receive, FIFO buffer, 3 (each with transmit/receive, FIFO buffer,
Serial Port [McASP] 16/9 serializers) 16/9 serializers)
Peripherals 10/100 Ethernet MAC
with Management Data 1 (RMII Interface)
Not all peripherals pins I/O
are available at the eHRPWM 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
same time (for more
detail, see the Device eCAP 3 32-bit capture inputs or 3 32-bit auxiliary PWM outputs
Configurations section). eQEP 2 32-bit QEP channels with 4 inputs/channel
UHPI - 1 (16-bit multiplexed address/data)
Full Speed Host Or Device with On-Chip High-Speed OTG Controller with on-chip
USB 2.0 (USB0) PHY OTG PHY
Full-Speed OHCI (as host) with on-chip
USB 1.1 (USB1) - PHY
General-Purpose 8 banks of 16-bit
Input/Output Port
LCD Controller - 1
1 (32 KHz oscillator and seperate power
RTC - trail. Provides time and date tracking and
alarm capability.)
PRU Subsystem 2 Programmable PRU Cores
(PRUSS)
Size (Bytes) 320 KB RAM 448 KB RAM
DSP
32KB L1 Program (L1P)/Cache (up to 32KB)
32KB L1 Data (L1D)/Cache (up to 32KB)
On-Chip Memory 256KB Unified Mapped RAM/Cache (L2)
Organization DSP Memories can be made accessible to EDMA3, and other peripherals.
ADDITIONAL MEMORY
-128KB RAM
C674x CPU ID + CPU Control Status Register 0x1400
Rev ID (CSR.[31:16])
C674x Megamodule Revision ID Register 0x0000
Revision (MM_REVID[15:0]) 0x0B7D F02F (Silicon Revision 1.0)
JTAG BSDL_ID DEVIDR0 register 0x8B7D F02F (Silicon Revision 1.1)
0x9B7D F02F (Silicon Revisions 3.0, 2.1, and 2.0)
8Device Overview Copyright © 2008–2014, Texas Instruments Incorporated
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Table 3-1. Characteristics of the C6745/C6747 Processor (continued)
HARDWARE FEATURES C6745 C6747
CPU Frequency MHz 674x DSP at 375 MHz(1.2V) or 456 MHz (1.3V)
Core (V) 1.2V / 1.3V
Voltage I/O (V) 3.3 V
24 mm x 24 mm, 176-Pin, 0.5 mm pitch, 17 mm x 17 mm, 256-Ball 1 mm pitch,
Package TQFP (PTP) PBGA (ZKB)
Product Preview (PP),
Advance Information 375 MHz Versions -PD
Product Status(1) (AI), 456 MHz Version - PD
or Production Data
(PD)
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
3.2 Device Compatibility
The C674x DSP core is code-compatible with the C6000™ DSP platform and supports features of both
the C64x+ and C67x+ DSP families.
Copyright © 2008–2014, Texas Instruments Incorporated Device Overview 9
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Instruction Fetch
C674x
Fixed/Floating Point CPU
Register
File A
Register
File B
Cache Control
Memory Protect
Bandwidth Mgmt
L1P
256
Cache Control
Memory Protect
Bandwidth Mgmt
L1D
64 64
8 x 32
32K Bytes
L1D RAM/
Cache
32K Bytes
L1P RAM/
Cache
256
Cache Control
Memory Protect
Bandwidth Mgmt
L2
256K Bytes
L2 RAM
256
Boot ROM
256
CFG
MDMA SDMA
EMC
Power Down
Interrupt
Controller
IDMA
256
256
256
256
256
64
High
Performance
Switch Fabric
64 64 64
Configuration
Peripherals
Bus
32
TMS320C6745, TMS320C6747
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3.3 DSP Subsystem
The DSP Subsystem includes the following features:
• C674x DSP CPU
• 32KB L1 Program (L1P)/Cache (up to 32KB)
• 32KB L1 Data (L1D)/Cache (up to 32KB)
• 256KB Unified Mapped RAM/Cache (L2)
• Boot ROM (cannot be used for application code)
• Little endian
Figure 3-1. C674x Megamodule Block Diagram
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3.3.1 C674x DSP CPU Description
The C674x Central Processing Unit (CPU) consists of eight functional units, two register files, and two
data paths as shown in Figure 3-2. The two general-purpose register files (A and B) each contain 32 32-
bit registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-
bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored in
register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the
next upper register (which is always an odd-numbered register).
The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.
The C674x CPU combines the performance of the C64x+ core with the floating-point capabilities of the
C67x+ core.
Each C674x .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x
32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for high-precision algorithms on
a variety of signed and unsigned 32-bit data types.
The .L Unit (or Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on
a pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.
The C674x core enhances the .S unit in several ways. On the previous cores, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C674x core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.
Other new features include:
•SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
•Compact Instructions - The native instruction size for the C6000™ devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C674x
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.
•Instruction Set Enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.
•Exceptions Handling - Intended to aid the programmer in isolating bugs. The C674x CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).
•Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.
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•Time-Stamp Counter - Primarily targeted for Real-Time Operating System (RTOS) robustness, a free-
running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.
For more details on the C674x CPU and its enhancements over the C64x architecture, see the following
documents:
•TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (SPRU732)
•TMS320C64x Technical Overview (SPRU395)
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src2
src2
Á
Á
Á
Á
Á
Á
Á
.D1
.M1
Á
Á
Á
Á
Á
Á
Á
.S1
Á
Á
Á
.L1
long src
odd dst
src2
src1
Á
Á
Á
Á
Á
Á
src1
src1
src1
even dst
even dst
odd dst
dst1
dst
src2
src2
src2
long src
DA1
ST1b
LD1b
LD1a
ST1a
Data path A
Odd
register
file A
(A1, A3,
A5...A31)
Á
Á
Á
Odd
register
file B
(B1, B3,
B5...B31)
Á
Á
Á
.D2
Á
Á
Á
Á
src1
dst
src2
DA2
LD2a
LD2b
src2
.M2 src1
Á
Á
Á
dst1
Á
Á
Á
.S2 src1
Á
Á
Á
Á
even dst
long src
odd dst
ST2a
ST2b
long src
.L2
Á
Á
Á
Á
even dst
odd dst
Á
Á
Á
src1
Data path B
Control Register
32 MSB
32 LSB
dst2 (A)
32 MSB
32 LSB
2x
1x
32 LSB
32 MSB
32 LSB
32 MSB
dst2
(B)
(B)
(A)
8
8
8
8
32
32
32
32
(C)
(C)
Even
register
file A
(A0, A2,
A4...A30)
Even
register
file B
(B0, B2,
B4...B30)
(D)
(D)
(D)
(D)
A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.
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Figure 3-2. TMS320C674x CPU (DSP Core) Data Paths
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3.3.2 DSP Memory Mapping
The DSP memory map is shown in Section 3.4.
3.3.2.1 External Memories
The DSP has access to the following External memories:
• Asynchronous EMIF / SDRAM / NAND / NOR Flash (EMIFA)
• SDRAM (EMIFB)
3.3.2.2 DSP Internal Memories
The DSP has access to the following DSP memories:
• L2 RAM
• L1P RAM
• L1D RAM
3.3.2.3 C674x CPU
The C674x core uses a two-level cache-based architecture. The Level 1 Program cache (L1P) is 32 KB
direct mapped cache and the Level 1 Data cache (L1D) is 32 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 256 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.
Table 3-2 shows a memory map of the C674x CPU cache registers for the device.
Table 3-2. C674x Cache Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
L2 Cache configuration register (See the Technical Reference Manual
0x0184 0000 L2CFG SPRUH91 for the reset configuration)
L1P Size Cache configuration register (See the Technical Reference
0x0184 0020 L1PCFG Manual SPRUH91 for the reset configuration)
0x0184 0024 L1PCC L1P Freeze Mode Cache configuration register
L1D Size Cache configuration register (See the Technical Reference
0x0184 0040 L1DCFG Manual SPRUH91 for the reset configuration)
0x0184 0044 L1DCC L1D Freeze Mode Cache configuration register
0x0184 0048 - 0x0184 0FFC - Reserved
0x0184 1000 EDMAWEIGHT L2 EDMA access control register
0x0184 1004 - 0x0184 1FFC - Reserved
0x0184 2000 L2ALLOC0 L2 allocation register 0
0x0184 2004 L2ALLOC1 L2 allocation register 1
0x0184 2008 L2ALLOC2 L2 allocation register 2
0x0184 200C L2ALLOC3 L2 allocation register 3
0x0184 2010 - 0x0184 3FFF - Reserved
0x0184 4000 L2WBAR L2 writeback base address register
0x0184 4004 L2WWC L2 writeback word count register
0x0184 4010 L2WIBAR L2 writeback invalidate base address register
0x0184 4014 L2WIWC L2 writeback invalidate word count register
0x0184 4018 L2IBAR L2 invalidate base address register
0x0184 401C L2IWC L2 invalidate word count register
0x0184 4020 L1PIBAR L1P invalidate base address register
0x0184 4024 L1PIWC L1P invalidate word count register
0x0184 4030 L1DWIBAR L1D writeback invalidate base address register
0x0184 4034 L1DWIWC L1D writeback invalidate word count register
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Table 3-2. C674x Cache Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0184 4038 - Reserved
0x0184 4040 L1DWBAR L1D writeback base address register
0x0184 4044 L1DWWC L1D writeback word count register
0x0184 4048 L1DIBAR L1D invalidate base address register
0x0184 404C L1DIWC L1D invalidate word count register
0x0184 4050 - 0x0184 4FFF - Reserved
0x0184 5000 L2WB L2 writeback all register
0x0184 5004 L2WBINV L2 writeback invalidate all register
0x0184 5008 L2INV L2 Global Invalidate without writeback
0x0184 500C - 0x0184 5027 - Reserved
0x0184 5028 L1PINV L1P Global Invalidate
0x0184 502C - 0x0184 5039 - Reserved
0x0184 5040 L1DWB L1D Global Writeback
0x0184 5044 L1DWBINV L1D Global Writeback with Invalidate
0x0184 5048 L1DINV L1D Global Invalidate without writeback
0x0184 8000 – 0x0184 80FF MAR0 - MAR63 Reserved 0x0000 0000 – 0x3FFF FFFF
Memory Attribute Registers for EMIFA SDRAM Data (CS0)
0x0184 8100 – 0x0184 817F MAR64 – MAR95 0x4000 0000 – 0x5FFF FFFF
Memory Attribute Registers for EMIFA Async Data (CS2)
0x0184 8180 – 0x0184 8187 MAR96 - MAR97 0x6000 0000 – 0x61FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS3)
0x0184 8188 – 0x0184 818F MAR98 – MAR99 0x6200 0000 – 0x63FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS4)
0x0184 8190 – 0x0184 8197 MAR100 – MAR101 0x6400 0000 – 0x65FF FFFF
Memory Attribute Registers for EMIFA Async Data (CS5)
0x0184 8198 – 0x0184 819F MAR102 – MAR103 0x6600 0000 – 0x67FF FFFF
0x0184 81A0 – 0x0184 81FF MAR104 – MAR127 Reserved 0x6800 0000 – 0x7FFF FFFF
Memory Attribute Register for Shared RAM 0x8000 0000 – 0x8001 FFFF
0x0184 8200 MAR128 Reserved 0x8002 0000 – 0x81FF FFFF
0x0184 8204 – 0x0184 82FF MAR129 – MAR191 Reserved 0x8200 0000 – 0xBFFF FFFF
Memory Attribute Registers for EMIFB SDRAM Data (CS0)
0x0184 8300 – 0x0184 837F MAR192 – MAR223 0xC000 0000 – 0xDFFF FFFF
0x0184 8380 – 0x0184 83FF MAR224 – MAR255 Reserved 0xE000 0000 – 0xFFFF FFFF
Table 3-3. C674x L1/L2 Memory Protection Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0184 A000 L2MPFAR L2 memory protection fault address register
0x0184 A004 L2MPFSR L2 memory protection fault status register
0x0184 A008 L2MPFCR L2 memory protection fault command register
0x0184 A00C - 0x0184 A0FF - Reserved
0x0184 A100 L2MPLK0 L2 memory protection lock key bits [31:0]
0x0184 A104 L2MPLK1 L2 memory protection lock key bits [63:32]
0x0184 A108 L2MPLK2 L2 memory protection lock key bits [95:64]
0x0184 A10C L2MPLK3 L2 memory protection lock key bits [127:96]
0x0184 A110 L2MPLKCMD L2 memory protection lock key command register
0x0184 A114 L2MPLKSTAT L2 memory protection lock key status register
0x0184 A118 - 0x0184 A1FF - Reserved
L2 memory protection page attribute register 0
0x0184 A200 L2MPPA0 (controls memory address 0x0080 0000 - 0x0080 1FFF)
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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
L2 memory protection page attribute register 1
0x0184 A204 L2MPPA1 (controls memory address 0x0080 2000 - 0x0080 3FFF)
L2 memory protection page attribute register 2
0x0184 A208 L2MPPA2 (controls memory address 0x0080 4000 - 0x0080 5FFF)
L2 memory protection page attribute register 3
0x0184 A20C L2MPPA3 (controls memory address 0x0080 6000 - 0x0080 7FFF)
L2 memory protection page attribute register 4
0x0184 A210 L2MPPA4 (controls memory address 0x0080 8000 - 0x0080 9FFF)
L2 memory protection page attribute register 5
0x0184 A214 L2MPPA5 (controls memory address 0x0080 A000 - 0x0080 BFFF)
L2 memory protection page attribute register 6
0x0184 A218 L2MPPA6 (controls memory address 0x0080 C000 - 0x0080 DFFF)
L2 memory protection page attribute register 7
0x0184 A21C L2MPPA7 (controls memory address 0x0080 E000 - 0x0080 FFFF)
L2 memory protection page attribute register 8
0x0184 A220 L2MPPA8 (controls memory address 0x0081 0000 - 0x0081 1FFF)
L2 memory protection page attribute register 9
0x0184 A224 L2MPPA9 (controls memory address 0x0081 2000 - 0x0081 3FFF)
L2 memory protection page attribute register 10
0x0184 A228 L2MPPA10 (controls memory address 0x0081 4000 - 0x0081 5FFF)
L2 memory protection page attribute register 11
0x0184 A22C L2MPPA11 (controls memory address 0x0081 6000 - 0x0081 7FFF)
L2 memory protection page attribute register 12
0x0184 A230 L2MPPA12 (controls memory address 0x0081 8000 - 0x0081 9FFF)
L2 memory protection page attribute register 13
0x0184 A234 L2MPPA13 (controls memory address 0x0081 A000 - 0x0081 BFFF)
L2 memory protection page attribute register 14
0x0184 A238 L2MPPA14 (controls memory address 0x0081 C000 - 0x0081 DFFF)
L2 memory protection page attribute register 15
0x0184 A23C L2MPPA15 (controls memory address 0x0081 E000 - 0x0081 FFFF)
L2 memory protection page attribute register 16
0x0184 A240 L2MPPA16 (controls memory address 0x0082 0000 - 0x0082 1FFF)
L2 memory protection page attribute register 17
0x0184 A244 L2MPPA17 (controls memory address 0x0082 2000 - 0x0082 3FFF)
L2 memory protection page attribute register 18
0x0184 A248 L2MPPA18 (controls memory address 0x0082 4000 - 0x0082 5FFF)
L2 memory protection page attribute register 19
0x0184 A24C L2MPPA19 (controls memory address 0x0082 6000 - 0x0082 7FFF)
L2 memory protection page attribute register 20
0x0184 A250 L2MPPA20 (controls memory address 0x0082 8000 - 0x0082 9FFF)
L2 memory protection page attribute register 21
0x0184 A254 L2MPPA21 (controls memory address 0x0082 A000 - 0x0082 BFFF)
L2 memory protection page attribute register 22
0x0184 A258 L2MPPA22 (controls memory address 0x0082 C000 - 0x0082 DFFF)
L2 memory protection page attribute register 23
0x0184 A25C L2MPPA23 (controls memory address 0x0082 E000 - 0x0082 FFFF)
L2 memory protection page attribute register 24
0x0184 A260 L2MPPA24 (controls memory address 0x0083 0000 - 0x0083 1FFF)
L2 memory protection page attribute register 25
0x0184 A264 L2MPPA25 (controls memory address 0x0083 2000 - 0x0083 3FFF)
L2 memory protection page attribute register 26
0x0184 A268 L2MPPA26 (controls memory address 0x0083 4000 - 0x0083 5FFF)
L2 memory protection page attribute register 27
0x0184 A26C L2MPPA27 (controls memory address 0x0083 6000 - 0x0083 7FFF)
L2 memory protection page attribute register 28
0x0184 A270 L2MPPA28 (controls memory address 0x0083 8000 - 0x0083 9FFF)
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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
L2 memory protection page attribute register 29
0x0184 A274 L2MPPA29 (controls memory address 0x0083 A000 - 0x0083 BFFF)
L2 memory protection page attribute register 30
0x0184 A278 L2MPPA30 (controls memory address 0x0083 C000 - 0x0083 DFFF)
L2 memory protection page attribute register 31
0x0184 A27C L2MPPA31 (controls memory address 0x0083 E000 - 0x0083 FFFF)
L2 memory protection page attribute register 32
0x0184 A280 L2MPPA32 (controls memory address 0x0070 0000 - 0x0070 7FFF)
L2 memory protection page attribute register 33
0x0184 A284 L2MPPA33 (controls memory address 0x0070 8000 - 0x0070 FFFF)
L2 memory protection page attribute register 34
0x0184 A288 L2MPPA34 (controls memory address 0x0071 0000 - 0x0071 7FFF)
L2 memory protection page attribute register 35
0x0184 A28C L2MPPA35 (controls memory address 0x0071 8000 - 0x0071 FFFF)
L2 memory protection page attribute register 36
0x0184 A290 L2MPPA36 (controls memory address 0x0072 0000 - 0x0072 7FFF)
L2 memory protection page attribute register 37
0x0184 A294 L2MPPA37 (controls memory address 0x0072 8000 - 0x0072 FFFF)
L2 memory protection page attribute register 38
0x0184 A298 L2MPPA38 (controls memory address 0x0073 0000 - 0x0073 7FFF)
L2 memory protection page attribute register 39
0x0184 A29C L2MPPA39 (controls memory address 0x0073 8000 - 0x0073 FFFF)
L2 memory protection page attribute register 40
0x0184 A2A0 L2MPPA40 (controls memory address 0x0074 0000 - 0x0074 7FFF)
L2 memory protection page attribute register 41
0x0184 A2A4 L2MPPA41 (controls memory address 0x0074 8000 - 0x0074 FFFF)
L2 memory protection page attribute register 42
0x0184 A2A8 L2MPPA42 (controls memory address 0x0075 0000 - 0x0075 7FFF)
L2 memory protection page attribute register 43
0x0184 A2AC L2MPPA43 (controls memory address 0x0075 8000 - 0x0075 FFFF)
L2 memory protection page attribute register 44
0x0184 A2B0 L2MPPA44 (controls memory address 0x0076 0000 - 0x0076 7FFF)
L2 memory protection page attribute register 45
0x0184 A2B4 L2MPPA45 (controls memory address 0x0076 8000 - 0x0076 FFFF)
L2 memory protection page attribute register 46
0x0184 A2B8 L2MPPA46 (controls memory address 0x0077 0000 - 0x0077 7FFF)
L2 memory protection page attribute register 47
0x0184 A2BC L2MPPA47 (controls memory address 0x0077 8000 - 0x0077 FFFF)
L2 memory protection page attribute register 48
0x0184 A2C0 L2MPPA48 (controls memory address 0x0078 0000 - 0x0078 7FFF)
L2 memory protection page attribute register 49
0x0184 A2C4 L2MPPA49 (controls memory address 0x0078 8000 - 0x0078 FFFF)
L2 memory protection page attribute register 50
0x0184 A2C8 L2MPPA50 (controls memory address 0x0079 0000 - 0x0079 7FFF)
L2 memory protection page attribute register 51
0x0184 A2CC L2MPPA51 (controls memory address 0x0079 8000 - 0x0079 FFFF)
L2 memory protection page attribute register 52
0x0184 A2D0 L2MPPA52 (controls memory address 0x007A 0000 - 0x007A 7FFF)
L2 memory protection page attribute register 53
0x0184 A2D4 L2MPPA53 (controls memory address 0x007A 8000 - 0x007A FFFF)
L2 memory protection page attribute register 54
0x0184 A2D8 L2MPPA54 (controls memory address 0x007B 0000 - 0x007B 7FFF)
L2 memory protection page attribute register 55
0x0184 A2DC L2MPPA55 (controls memory address 0x007B 8000 - 0x007B FFFF)
L2 memory protection page attribute register 56
0x0184 A2E0 L2MPPA56 (controls memory address 0x007C 0000 - 0x007C 7FFF)
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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
L2 memory protection page attribute register 57
0x0184 A2E4 L2MPPA57 (controls memory address 0x007C 8000 - 0x007C FFFF)
L2 memory protection page attribute register 58
0x0184 A2E8 L2MPPA58 (controls memory address 0x007D 0000 - 0x007D 7FFF)
L2 memory protection page attribute register 59
0x0184 A2EC L2MPPA59 (controls memory address 0x007D 8000 - 0x007D FFFF)
L2 memory protection page attribute register 60
0x0184 A2F0 L2MPPA60 (controls memory address 0x007E 0000 - 0x007E 7FFF)
L2 memory protection page attribute register 61
0x0184 A2F4 L2MPPA61 (controls memory address 0x007E 8000 - 0x007E FFFF)
L2 memory protection page attribute register 62
0x0184 A2F8 L2MPPA62 (controls memory address 0x007F 0000 - 0x007F 7FFF)
L2 memory protection page attribute register 63
0x0184 A2FC L2MPPA63 (controls memory address 0x007F 8000 - 0x007F FFFF)
0x0184 A300 - 0x0184 A3FF - Reserved
0x0184 A400 L1PMPFAR L1P memory protection fault address register
0x0184 A404 L1PMPFSR L1P memory protection fault status register
0x0184 A408 L1PMPFCR L1P memory protection fault command register
0x0184 A40C - 0x0184 A4FF - Reserved
0x0184 A500 L1PMPLK0 L1P memory protection lock key bits [31:0]
0x0184 A504 L1PMPLK1 L1P memory protection lock key bits [63:32]
0x0184 A508 L1PMPLK2 L1P memory protection lock key bits [95:64]
0x0184 A50C L1PMPLK3 L1P memory protection lock key bits [127:96]
0x0184 A510 L1PMPLKCMD L1P memory protection lock key command register
0x0184 A514 L1PMPLKSTAT L1P memory protection lock key status register
0x0184 A518 - 0x0184 A5FF - Reserved
0x0184 A600 - 0x0184 A63F - Reserved (1)
L1P memory protection page attribute register 16
0x0184 A640 L1PMPPA16 (controls memory address 0x00E0 0000 - 0x00E0 07FF)
L1P memory protection page attribute register 17
0x0184 A644 L1PMPPA17 (controls memory address 0x00E0 0800 - 0x00E0 0FFF)
L1P memory protection page attribute register 18
0x0184 A648 L1PMPPA18 (controls memory address 0x00E0 1000 - 0x00E0 17FF)
L1P memory protection page attribute register 19
0x0184 A64C L1PMPPA19 (controls memory address 0x00E0 1800 - 0x00E0 1FFF)
L1P memory protection page attribute register 20
0x0184 A650 L1PMPPA20 (controls memory address 0x00E0 2000 - 0x00E0 27FF)
L1P memory protection page attribute register 21
0x0184 A654 L1PMPPA21 (controls memory address 0x00E0 2800 - 0x00E0 2FFF)
L1P memory protection page attribute register 22
0x0184 A658 L1PMPPA22 (controls memory address 0x00E0 3000 - 0x00E0 37FF)
L1P memory protection page attribute register 23
0x0184 A65C L1PMPPA23 (controls memory address 0x00E0 3800 - 0x00E0 3FFF)
L1P memory protection page attribute register 24
0x0184 A660 L1PMPPA24 (controls memory address 0x00E0 4000 - 0x00E0 47FF)
L1P memory protection page attribute register 25
0x0184 A664 L1PMPPA25 (controls memory address 0x00E0 4800 - 0x00E0 4FFF)
L1P memory protection page attribute register 26
0x0184 A668 L1PMPPA26 (controls memory address 0x00E0 5000 - 0x00E0 57FF)
L1P memory protection page attribute register 27
0x0184 A66C L1PMPPA27 (controls memory address 0x00E0 5800 - 0x00E0 5FFF)
(1) These addresses correspond to the L1P memory protection page attribute registers 0-15 (L1PMPPA0-L1PMPPA15) of the C674x
megamaodule. These registers are not supported for this device.
18 Device Overview Copyright © 2008–2014, Texas Instruments Incorporated
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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
L1P memory protection page attribute register 28
0x0184 A670 L1PMPPA28 (controls memory address 0x00E0 6000 - 0x00E0 67FF)
L1P memory protection page attribute register 29
0x0184 A674 L1PMPPA29 (controls memory address 0x00E0 6800 - 0x00E0 6FFF)
L1P memory protection page attribute register 30
0x0184 A678 L1PMPPA30 (controls memory address 0x00E0 7000 - 0x00E0 77FF)
L1P memory protection page attribute register 31
0x0184 A67C L1PMPPA31 (controls memory address 0x00E0 7800 - 0x00E0 7FFF)
0x0184 A67F – 0x0184 ABFF - Reserved
0x0184 AC00 L1DMPFAR L1D memory protection fault address register
0x0184 AC04 L1DMPFSR L1D memory protection fault status register
0x0184 AC08 L1DMPFCR L1D memory protection fault command register
0x0184 AC0C - 0x0184 ACFF - Reserved
0x0184 AD00 L1DMPLK0 L1D memory protection lock key bits [31:0]
0x0184 AD04 L1DMPLK1 L1D memory protection lock key bits [63:32]
0x0184 AD08 L1DMPLK2 L1D memory protection lock key bits [95:64]
0x0184 AD0C L1DMPLK3 L1D memory protection lock key bits [127:96]
0x0184 AD10 L1DMPLKCMD L1D memory protection lock key command register
0x0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register
0x0184 AD18 - 0x0184 ADFF - Reserved
0x0184 AE00 - 0x0184 AE3F - Reserved (2)
L1D memory protection page attribute register 16
0x0184 AE40 L1DMPPA16 (controls memory address 0x00F0 0000 - 0x00F0 07FF)
L1D memory protection page attribute register 17
0x0184 AE44 L1DMPPA17 (controls memory address 0x00F0 0800 - 0x00F0 0FFF)
L1D memory protection page attribute register 18
0x0184 AE48 L1DMPPA18 (controls memory address 0x00F0 1000 - 0x00F0 17FF)
L1D memory protection page attribute register 19
0x0184 AE4C L1DMPPA19 (controls memory address 0x00F0 1800 - 0x00F0 1FFF)
L1D memory protection page attribute register 20
0x0184 AE50 L1DMPPA20 (controls memory address 0x00F0 2000 - 0x00F0 27FF)
L1D memory protection page attribute register 21
0x0184 AE54 L1DMPPA21 (controls memory address 0x00F0 2800 - 0x00F0 2FFF)
L1D memory protection page attribute register 22
0x0184 AE58 L1DMPPA22 (controls memory address 0x00F0 3000 - 0x00F0 37FF)
L1D memory protection page attribute register 23
0x0184 AE5C L1DMPPA23 (controls memory address 0x00F0 3800 - 0x00F0 3FFF)
L1D memory protection page attribute register 24
0x0184 AE60 L1DMPPA24 (controls memory address 0x00F0 4000 - 0x00F0 47FF)
L1D memory protection page attribute register 25
0x0184 AE64 L1DMPPA25 (controls memory address 0x00F0 4800 - 0x00F0 4FFF)
L1D memory protection page attribute register 26
0x0184 AE68 L1DMPPA26 (controls memory address 0x00F0 5000 - 0x00F0 57FF)
L1D memory protection page attribute register 27
0x0184 AE6C L1DMPPA27 (controls memory address 0x00F0 5800 - 0x00F0 5FFF)
L1D memory protection page attribute register 28
0x0184 AE70 L1DMPPA28 (controls memory address 0x00F0 6000 - 0x00F0 67FF)
L1D memory protection page attribute register 29
0x0184 AE74 L1DMPPA29 (controls memory address 0x00F0 6800 - 0x00F0 6FFF)
L1D memory protection page attribute register 30
0x0184 AE78 L1DMPPA30 (controls memory address 0x00F0 7000 - 0x00F0 77FF)
(2) These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0-L1DMPPA15) of the C674x
megamaodule. These registers are not supported for this device.
Copyright © 2008–2014, Texas Instruments Incorporated Device Overview 19
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Table 3-3. C674x L1/L2 Memory Protection Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
L1D memory protection page attribute register 31
0x0184 AE7C L1DMPPA31 (controls memory address 0x00F0 7800 - 0x00F0 7FFF)
0x0184 AE80 – 0x0185 FFFF - Reserved
See Table 3-4 for a detailed top level C6745/6747 memory map that includes the DSP memory space.
20 Device Overview Copyright © 2008–2014, Texas Instruments Incorporated
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
3.4 Memory Map Summary
Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined
behavior.
Table 3-4. C6747 Top Level Memory Map
Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC
Map Peripheral Mem
Mem Map Map
0x0000 0000 0x0000 0FFF 4K - PRUSS Local
Address Space
0x0000 1000 0x006F FFFF
0x0070 0000 0x007F FFFF 1024K DSP L2 ROM (1) -
0x0080 0000 0x0083 FFFF 256K DSP L2 RAM -
0x0084 0000 0x00DF FFFF -
0x00E0 0000 0x00E0 7FFF 32K DSP L1P RAM -
0x00E0 8000 0x00EF FFFF
0x00F0 0000 0x00F0 7FFF 32K DSP L1D RAM -
0x00F0 8000 0x017F FFFF
0x0180 0000 0x0180 FFFF 64K DSP Interrupt -
Controller
0x0181 0000 0x0181 0FFF 4K DSP Powerdown -
Controller
0x0181 1000 0x0181 1FFF 4K DSP Security ID -
0x0181 2000 0x0181 2FFF 4K DSP Revision ID -
0x0181 3000 0x0181 FFFF 52K - -
0x0182 0000 0x0182 FFFF 64K DSP EMC -
0x0183 0000 0x0183 FFFF 64K DSP Internal -
Reserved
0x0184 0000 0x0184 FFFF 64K DSP Memory -
System
0x0185 0000 0x01BF FFFF
0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller -
0x01C0 8000 0x01C0 83FF 1024 EDMA3 Transfer Controller 0 -
0x01C0 8400 0x01C0 87FF 1024 EDMA3 Transfer Controller 1 -
0x01C0 8800 0x01C0 FFFF
0x01C1 0000 0x01C1 0FFF 4K PSC 0 -
0x01C1 1000 0x01C1 1FFF 4K PLL Controller -
0x01C1 2000 0x01C1 3FFF
0x01C1 4000 0x01C1 4FFF 4K SYSCFG -
0x01C1 5000 0x01C1 FFFF -
0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 -
0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 -
0x01C2 2000 0x01C2 2FFF 4K I2C 0 -
0x01C2 3000 0x01C2 3FFF 4K RTC -
0x01C2 4000 0x01C3 FFFF -
0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 -
0x01C4 1000 0x01C4 1FFF 4K SPI 0 -
0x01C4 2000 0x01C4 2FFF 4K UART 0 -
0x01C4 3000 0x01CF FFFF -
0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control -
0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Control -
(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code
Copyright © 2008–2014, Texas Instruments Incorporated Device Overview 21
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Table 3-4. C6747 Top Level Memory Map (continued)
Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC
Map Peripheral Mem
Mem Map Map
0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data -
0x01D0 3000 0x01D0 3FFF -
0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control -
0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Control -
0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data -
0x01D0 7000 0x01D0 7FFF -
0x01D0 8000 0x01D0 8FFF 4K McASP 2 Control -
0x01D0 9000 0x01D0 9FFF 4K McASP 2 AFIFO Control -
0x01D0 A000 0x01D0 AFFF 4K McASP 2 Data -
0x01D0 B000 0x01D0 BFFF -
0x01D0 C000 0x01D0 CFFF 4K UART 1 -
0x01D0 D000 0x01D0 DFFF 4K UART 2 -
0x01D0 E000 0x01DF FFFF -
0x01E0 0000 0x01E0 FFFF 64K USB0 -
0x01E1 0000 0x01E1 0FFF 4K UHPI -
0x01E1 1000 0x01E1 1FFF -
0x01E1 2000 0x01E1 2FFF 4K SPI 1 -
0x01E1 3000 0x01E1 3FFF 4K LCD Controller -
0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1) -
0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2) -
0x01E1 6000 0x01E1 FFFF -
0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM -
0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers -
0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers -
0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port -
0x01E2 5000 0x01E2 5FFF 4K USB1 -
0x01E2 6000 0x01E2 6FFF 4K GPIO -
0x01E2 7000 0x01E2 7FFF 4K PSC 1 -
0x01E2 8000 0x01E2 8FFF 4K I2C 1 -
0x01E2 9000 0x01EF FFFF -
0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 -
0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 -
0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 -
0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 -
0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 -
0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 -
0x01F0 6000 0x01F0 6FFF 4K ECAP 0 -
0x01F0 7000 0x01F0 7FFF 4K ECAP 1 -
0x01F0 8000 0x01F0 8FFF 4K ECAP 2 -
0x01F0 9000 0x01F0 9FFF 4K EQEP 0 -
0x01F0 A000 0x01F0 AFFF 4K EQEP 1 -
0x01F0 B000 0x116F FFFF -
0x1170 0000 0x117F FFFF 1024K DSP L2 ROM (2) -
0x1180 0000 0x1183 FFFF 256K DSP L2 RAM -
0x1184 0000 0x11DF FFFF -
(2) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code
22 Device Overview Copyright © 2008–2014, Texas Instruments Incorporated
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Table 3-4. C6747 Top Level Memory Map (continued)
Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC
Map Peripheral Mem
Mem Map Map
0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM -
0x11E0 8000 0x11EF FFFF -
0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM -
0x11F0 8000 0x3FFF FFFF -
0x4000 0000 0x47FF FFFF 128M EMIFA SDRAM data (CS0) -
0x4800 0000 0x5FFF FFFF
0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) -
0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) -
0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) -
0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) -
0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers -
0x6800 8000 0x7FFF FFFF -
0x8000 0000 0x8001 FFFF 128K Shared RAM -
0x8002 0000 0xAFFF FFFF -
0xB000 0000 0xB000 7FFF 32K EMIFB Control Registers
0xB000 8000 0xBFFF FFFF -
0xC000 0000 0xCFFF FFFF 256M EMIFB SDRAM Data
0xD000 0000 0xDFFF FFFF -
Table 3-5. C6745 Top Level Memory Map
Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC
Map Peripheral Mem
Mem Map Map
0x0000 0000 0x0000 0FFF 4K - PRUSS Local
Address Space
0x0000 1000 0x006F FFFF
0x0070 0000 0x007F FFFF 1024K DSP L2 ROM (1) -
0x0080 0000 0x0083 FFFF 256K DSP L2 RAM -
0x0084 0000 0x00DF FFFF -
0x00E0 0000 0x00E0 7FFF 32K DSP L1P RAM -
0x00E0 8000 0x00EF FFFF
0x00F0 0000 0x00F0 7FFF 32K DSP L1D RAM -
0x00F0 8000 0x017F FFFF
0x0180 0000 0x0180 FFFF 64K DSP Interrupt -
Controller
0x0181 0000 0x0181 0FFF 4K DSP Powerdown -
Controller
0x0181 1000 0x0181 1FFF 4K DSP Security ID -
0x0181 2000 0x0181 2FFF 4K DSP Revision ID -
0x0181 3000 0x0181 FFFF 52K - -
0x0182 0000 0x0182 FFFF 64K DSP EMC -
0x0183 0000 0x0183 FFFF 64K DSP Internal -
Reserved
0x0184 0000 0x0184 FFFF 64K DSP Memory -
System
0x0185 0000 0x01BF FFFF
0x01C0 0000 0x01C0 7FFF 32K EDMA3 Channel Controller -
(1) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code
Copyright © 2008–2014, Texas Instruments Incorporated Device Overview 23
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Table 3-5. C6745 Top Level Memory Map (continued)
Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC
Map Peripheral Mem
Mem Map Map
0x01C0 8000 0x01C0 83FF 1024 EDMA3 Transfer Controller 0 -
0x01C0 8400 0x01C0 87FF 1024 EDMA3 Transfer Controller 1 -
0x01C0 8800 0x01C0 FFFF
0x01C1 0000 0x01C1 0FFF 4K PSC 0 -
0x01C1 1000 0x01C1 1FFF 4K PLL Controller -
0x01C1 2000 0x01C1 3FFF
0x01C1 4000 0x01C1 4FFF 4K SYSCFG -
0x01C1 5000 0x01C1 FFFF -
0x01C2 0000 0x01C2 0FFF 4K Timer64P 0 -
0x01C2 1000 0x01C2 1FFF 4K Timer64P 1 -
0x01C2 2000 0x01C2 2FFF 4K I2C 0 -
0x01C2 3000 0x01C3 FFFF -
0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 -
0x01C4 1000 0x01C4 1FFF 4K SPI 0 -
0x01C4 2000 0x01C4 2FFF 4K UART 0 -
0x01C4 3000 0x01CF FFFF -
0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control -
0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Control -
0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data -
0x01D0 3000 0x01D0 3FFF -
0x01D0 4000 0x01D0 4FFF 4K McASP 1 Control -
0x01D0 5000 0x01D0 5FFF 4K McASP 1 AFIFO Control -
0x01D0 6000 0x01D0 6FFF 4K McASP 1 Data -
0x01D0 7000 0x01D0 BFFF -
0x01D0 C000 0x01D0 CFFF 4K UART 1 -
0x01D0 D000 0x01D0 DFFF 4K UART 2 -
0x01D0 E000 0x01DF FFFF -
0x01E0 0000 0x01E0 FFFF 64K USB0 -
0x01E1 0000 0x01E1 1FFF -
0x01E1 2000 0x01E1 2FFF 4K SPI 1 -
0x01E1 3000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1) -
0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2) -
0x01E1 6000 0x01E1 FFFF -
0x01E2 0000 0x01E2 1FFF 8K EMAC Control Module RAM -
0x01E2 2000 0x01E2 2FFF 4K EMAC Control Module Registers -
0x01E2 3000 0x01E2 3FFF 4K EMAC Control Registers -
0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port -
0x01E2 5000 0x01E2 6FFF 4K GPIO -
0x01E2 7000 0x01E2 7FFF 4K PSC 1 -
0x01E2 8000 0x01E2 8FFF 4K I2C 1 -
0x01E2 9000 0x01EF FFFF -
0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 -
0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 -
0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 -
0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 -
0x01F0 4000 0x01F0 4FFF 4K eHRPWM 2 -
24 Device Overview Copyright © 2008–2014, Texas Instruments Incorporated
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Table 3-5. C6745 Top Level Memory Map (continued)
Start Address End Address Size DSP Mem Map EDMA Mem Map PRUSS Mem Master LCDC
Map Peripheral Mem
Mem Map Map
0x01F0 5000 0x01F0 5FFF 4K HRPWM 2 -
0x01F0 6000 0x01F0 6FFF 4K ECAP 0 -
0x01F0 7000 0x01F0 7FFF 4K ECAP 1 -
0x01F0 8000 0x01F0 8FFF 4K ECAP 2 -
0x01F0 9000 0x01F0 9FFF 4K EQEP 0 -
0x01F0 A000 0x01F0 AFFF 4K EQEP 1 -
0x01F0 B000 0x116F FFFF -
0x1170 0000 0x117F FFFF 1024K DSP L2 ROM (2) -
0x1180 0000 0x1183 FFFF 256K DSP L2 RAM -
0x1184 0000 0x11DF FFFF -
0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM -
0x11E0 8000 0x11EF FFFF -
0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM -
0x11F0 8000 0x3FFF FFFF -
0x4000 0000 0x5FFF FFFF
0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2) -
0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3) -
0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4) -
0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5) -
0x6800 0000 0x6800 7FFF 32K EMIFA Control Registers -
0x6800 8000 0xAFFF FFFF -
0xB000 0000 0xB000 7FFF 32K EMIFB Control Registers
0xB000 8000 0xBFFF FFFF -
0xC000 0000 0xC7FF FFFF 128M EMIFB SDRAM Data
0xC800 0000 0xDFFF FFFF -
(2) The DSP L2 ROM is used for boot purposes and cannot be programmed with application code
Copyright © 2008–2014, Texas Instruments Incorporated Device Overview 25
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VSS VSS
TAXR1[0]/
GP4[0]
AXR1[11]/
GP5[11]
SPI0_CLK/
EQEP1I/
GP5[2]/
BOOT[2]
SPI1_CLK/
EQEP1S/
GP5[7]/
BOOT[7]
123456
EMA_CS[3]/
AMUTE2/
GP2[6]
7
EMA_CS[0]
UHPI_HAS
/
/
GP2[4]
8
EMA_A[0]/
LCD_D[7]/
GP1[0]
9
EMA_A[4]/
LCD_D[3]/
GP1[4]
10
EMA_A[8]/
LCD_PCLK/
GP1[8]
11
EMA_SDCKE/
GP2[0]
12
EMA_D[0]/
MMCSD_DAT[0]/
UHPI_HD[0]/
GP0[0]/
BOOT[12]
13
EMA_D[9]/
UHPI_HD[9]/
LCD_D[9]/
GP0[9]
14
VSS VSS
15 16
DVDD
RAXR1[1]/
GP4[1]
UART0_RXD/
I2C0_SDA/
TM64P0_IN12/
GP5[8]/
BOOT[8]
SPI1_ENA/
UART2_RXD/
GP5[12]
SPI0_ENA
UART0_CTS
/
/
EQEP0A/
GP5[3]/
BOOT[3]
SPIO_SOMI[0]/
EQEPOI/
GP5[0]/
BOOT[0]
EMA_OE
UHPI_HDS1
/
/
AXR0[13]/
GP2[7]
EMA_BA[0]/
LCD_D[4]/
GP1[14]
EMA_A[1]/
MMCSD_CLK/
UHPI_HCNTL0/
GP1[1]
EMA_A[5]/
LCD_D[2]/
GP1[5]
EMA_A[9]/
LCD_HSYNC/
GP1[9]
EMA_CLK/
OBSCLK/
AHCLKR2/
GP1[15]
EMA_D[2]/
MMCSD_DAT[2]/
UHPI_HD[2]/
GP0[2]
EMA_D[10]/
UHPI_HD[10]/
LCD_D[10]/
GP0[10]
EMA_D[1]/
MMCSD_DAT[1]/
UHPI_HD[1]/
GP0[1]
DVDD
PAXR1[3]/
EQEP1A/
GP4[3]
AXR1[2]/
GP4[2]
UART0_TXD/
I2C0_SCL/
TM64P0_OUT12/
GP5[9]/
BOOT[9]
SPI1_SCS[0]/
UART2_TXD/
GP5[13]
SPI1_SOMI[0]/
I2C1_SCL/
GP5[5]/
BOOT[5]
SPI0_SIMO[0]/
EQEP0S/
GP5[1]/
BOOT[1]
EMA_CS[2]
UHPI_HCS
/
/
GP2[5]/
BOOT[15]
EMA_BA[1]/
LCD_D[5]/
UHPI_HHWIL/
GP1[13]
EMA_A[2]/
MMCSD_CMD/
UHPI_HCNTL1/
GP1[2]
EMA_A[6]/
LCD_D[1]/
GP1[6]
EMA_A[11]/
/
GP1[11]
LCD_AC_
ENB_CS
EMA_WE_
DQM[1]
UHPI_HDS2
/
/
AXR0[14]/
GP2[8]
EMA_D[4]/
MMCSD_DAT[4]/
UHPI_HD[4]/
GP0[4]
EMA_D[12]/
UHPI_HD[12]/
LCD_D[12]/
GP0[12]
EMA_D[3]/
MMCSD_DAT[3]/
UHPI_HD[3]/
GP0[3]
EMA_D[11]/
UHPI_HD[11]/
LCD_D[11]
GP0[11]
NAXR1[5]/
EPWM2B/
GP4[5]
AXR1[4]/
EQEP1B/
GP4[4]
AXR1[10]/
GP5[10]
SPI0_SCS[0]
UART0_RTS
/
/
EQEP0B/
GP5[4]/
BOOT[4]
SPI1_SIMO[0]/
I2C1_SDA/
GP5[6]/
BOOT[6]
EMA_WAIT[0]/
/
GP2[10]
UHPI_HRDY
EMA_RAS/
EMA_CS[5]/
GP2[2]
EMA_A[10]/
LCD_VSYNC/
GP1[10]
EMA_A[3]/
LCD_D[6]/
GP1[3]
EMA_A[7]/
LCD_D[0]/
GP1[7]
EMA_A[12]/
LCD_MCLK/
GP1[12]
EMA_D[8]/
UHPI_HD[8]/
LCD_D[8]/
GP0[8]
EMA_D[6]/
MMCSD_DAT[6]/
UHPI_HD[6]/
GP0[6]
EMA_D[14]/
UHPI_HD[14]/
LCD_D[14]/
GP0[14]
EMA_D[5]/
MMCSD_DAT[5]/
UHPI_HD[5]/
GP0[5]
EMA_D[13]/
UHPI_HD[13]/
LCD_D[13]/
GP0[13]
MAXR1[9]/
GP4[9]
AXR1[8]/
EPWM1A/
GP4[8]
AXR1[7]/
EPWM1B/
GP4[7]
AXR1[6]/
EPWM2A/
GP4[6]
DVDD VSS VSS DVDD DVDD VSS VSS DVDD
EMA_WE
W
/
UHPI_HR /
AXR0[12]/
GP2[3]/
BOOT[14]
EMA_WE_
DQM[0]
UHPI_HINT
/
/
AXR0[15]/
GP2[9]
EMA_D[7]/
MMCSD_DAT[7]/
UHPI_HD[7]/
GP0[7]/
BOOT[13]
EMA_D[15]/
UHPI_HD[15]/
LCD_D[15]/
GP0[15]
LAHCLKR1/
GP4[11]
ACLKR1/
ECAP2/
APWM2/
GP4[12]
AFSR1/
GP4[13]
AMUTE0/
RESETOUT DVDD CVDD VSS VSS VSS VSS DVDD DVDD EMB_CAS EMB_D[22] EMB_D[23]
EMA_CAS
EMA_CS[4]
/
/
GP2[1]
KGP7[14]
AHCLKX1/
EPWM0B/
GP3[14]
ACLKX1/
EPWM0A/
GP3[15]
AFSX1/
EPWMSYNCI/
EPWMSYNCO/
GP4[10]
DVDD CVDD VSS VSS CVDD CVDD DVDD EMB_D[20]
EMB_WE_
DQM[0]/
GP5[15]
EMB_WE EMB_D[21]CVDD
TMS
JTDI TDO TRST EMU[0]/
GP7[15] CVDD CVDD VSS VSS CVDD CVDD CVDD EMB_D[5]/
GP6[5] EMB_D[19] EMB_D[6]/
GP6[6]
EMB_D[7]/
GP6[7]
RTC_XI
HRTC_XO TCK NC USB0_
VDDA33 CVDD VSS VSS CVDD CVDD EMB_D[3]/
GP6[3] EMB_D[17] EMB_D[18] EMB_D[4]/
GP6[4]
RTC_CVDD
GRTC_VSS RESET USB0_DM DVDD CVDD VSS VSS CVDD CVDD DVDD
CVDD EMB_D[1]/
GP6[1] EMB_D[31] EMB_D[16] EMB_D[2]/
GP6[2]
OSCOUT
FOSCIN NC USB0_DP DVDD CVDD RSV1 VSS VSS VSS DVDD DVDD EMB_D[15]/
GP6[15] EMB_D[29] EMB_D[30] EMB_D[0]/
GP6[0]
PLL0_VSSA
EOSCVSS USB0_
VDDA18
USB0_
DRVVBUS/
GP4[15]
DVDD VSS VSS DVDD VSS VSS
DVDD DVDD EMB_D[13]/
GP6[13] EMB_D[27] EMB_D[28] EMB_D[14]/
GP6[14]
PLL0_VDDA
DUSB0_ID USB0_VBUS
AMUTE1/
EPWMTZ/
GP4[14]
AFSX0/
GP2[13]/
BOOT[10]
UART1_TXD/
AXR0[10]/
GP3[10]
AXR0[6]/
RMII_RXER/
ACLKR2/
GP3[6]
AXR0[2]/
RMII_TXEN/
AXR2[3]/
GP3[2]
EMB_CS[0] EMB_A[0]/
GP7[2]
EMB_A[4]/
GP7[6]
EMB_A[8]/
GP7[10]
EMB_D[9]/
GP6[9]
EMB_D[10]/
GP6[10]
EMB_D[11]/
GP6[11]
EMB_D[12]/
GP6[12]
USB1_
VDDA33
CUSB1_
VDDA18
USB0_
VDDA12
AFSR0/
GP3[12]
ACLKX0/
ECAP0/
APWM0/
GP2[12]
UART1_RXD/
AXR0[9]/
GP3[9]
AXR0[5]/
RMII_RXD[1]/
AFSX2/
GP3[5]
AXR0[1]/
RMII_TXD[1]/
ACLKX2/
GP3[1]
EMB_BA[0]/
GP7[1]
EMB_A[1]/
GP7[3]
EMB_A[5]/
GP7[7]
EMB_A[9]/
GP7[11] EMB_SDCKE EMB_CLK
EMB_WE_
DQM[1]/
GP5[14]
EMB_D[8]/
GP6[8]
BRSV2 VSS USB1_DM
ACLKR0/
ECAP1/
APWM1/
GP2[15]
AHCLKX0/
AHCLKX2/
USB_
REFCLKIN/
GP2[11]
AXR0[8]/
MDIO_D/
GP3[8]
AXR0[4]/
RMII_RXD[0]/
AXR2[1]/
GP3[4]
AXR0[0]/
RMII_TXD[0]/
AFSR2/
GP3[0]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
EMB_BA[1]/
GP7[0]
EMB_A[2]/
GP7[4]
EMB_A[6]/
GP7[8]
EMB_A[11]/
GP7[13]
EMB_WE_
DQM[2] EMB_D[25] EMB_A[12]/
GP3[13] DVDD
AVSS VSS USB1_DP
AHCLKR0/
RMII_MHZ_
50_CLK/
GP2[14]/
BOOT[11]
AXR0[11]/
AXR2[0]/
GP3[11]
AXR0[7]/
MDIO_CLK/
GP3[7]
AXR0[3]/
RMII_CRS_DV/
AXR2[2]/
GP3[3]
EMB_RAS EMB_A[10]/
GP7[12]
EMB_A[3]/
GP7[5]
EMB_A[7]/
GP7[9]
EMB_WE_
DQM[3] EMB_D[24] EMB_D[26] VSS VSS
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
RVDD RVDD
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
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3.5 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
3.5.1 Pin Map (Bottom View)
Figure 3-3 and Figure 3-4 show the pin assignments for ZKB package and PTP package, respectively.
Figure 3-3. Pin Map (ZKB)
26 Device Overview Copyright © 2008–2014, Texas Instruments Incorporated
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133
RSV2
134
USB0_VDDA12
135
USB0_VDDA18
136
NC
137
USB0_DP
138
USB0_DM
139
NC
140
USB0_VDDA33
141
PLL0_VDDA
142
143
OSCIN
144
145
OSCOUT
146
RESET
147
148
RSV4
149
RSV3
150
GP7[14]
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
PLL0_VSSA
OSCVSS
CVDD
TRST
TMS
TDI
TCK
TDO
RVDD
AFSX1/EPWMSYNCI/EPWMSYNC0/GP4[10]
DVDD
AFSR1/GP4[13]
AXR1[8]/EPWM1A/GP4[8]
AXR1[7]/EPWM1B/GP4[7]
AXR1[6]/EPWM2A/GP4[6]
AXR1[5]/EPWM2B/GP4[5]
1
AXR1[0]/GP4[0]
2
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8]
3
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9]
4
AXR1[10]/GP5[10]
5
DVDD
6
AXR1[11]/GP5[11]
7
SPI1_ENA/UART2_RXD/GP5[12]
8
SPI1_SCS[0]/UART2_TXD/GP5[13]
9
SPI0_SCS[0] UART0_RTS/ /EQEP0B/GP5[4]/BOOT[4]
10
11
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2]
12
13
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5]
14
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6]
15
16
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7]
17
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0]
18
19
EMA_WAIT[0]/GP2[10]
20
21
22
23
24
25
EMA_BA[0]/GP1[14]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
CVDD
SPI0_ENA UART0_CTS/ /EQEP0A/GP5[3]/BOOT[3]
DVDD
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1]
CVDD
EMA_CS[3]/GP2[6]
EMA_OE/AXR0[13]/GP2[7]
EMA_CS[2]/GP2[5]/BOOT[15]
DVDD
EMA_BA[1]/GP1[13]
EMA_A[10]/GP1[10]
CVDD
EMA_A[0]/GP1[0]
EMA_A[1]/MMCSD_CLK/GP1[1]
EMA_A[2]/MMCSD_CMD/GP1[2]
EMA_A[3]/GP1[3]
DVDD
EMA_A[4]/GP1[4]
EMA_A[5]/GP1[5]
EMA_A[6]/GP1[6]
EMA_A[7]/GP1[7]
CVDD
EMA_A[8]/GP1[8]
EMA_A[9]/GP1[9]
EMA_A[11]/GP1[11]
EMA_A[12]/GP1[12]
DVDD
EMA_D[0]/MMCSD_DAT[0]/GP0[0]/BOOT[12]
151
DVDD
CVDD
DVDD
AHCLKX1/EPWM0B/GP3[14]
CVDD
ACLKX1/EPWM0A/GP3[15]
ACLKR1/ECAP2/APWM2/GP4[12]
CVDD
DVDD
AXR1[4]/EQEP1B/GP4[4]
AXR1[3]/EQEP1A/GP4[3]
AXR1[2]/GP4[2]
AXR1[1]/GP4[1]
42
43
44
88 EMB_SDCKE
87 DVDD
86 EMB_CLK
85 EMB_WE_DQM[1]/GP5[14]
84 EMB_D[8]/GP6[8]
83 EMB_D[9]/GP6[9]
82 EMB_D[10]/GP6[10]
81 DVDD
80 EMB_D[11]/GP6[11]
79 EMB_D[12]/GP6[12]
78 EMB_D[13]/GP6[13]
77 CVDD
76 EMB_D[14]/GP6[14]
75
74 EMB_D[15]/GP6[15]
73 EMB_D[0]/GP6[0]
72 EMB_D[1]/GP6[1]
71 DVDD
70 EMB_D[2]/GP6[2]
69 CVDD
68 EMB_D[3]/GP6[3]
67 RVDD
66 EMB_D[4]/GP6[4]
65 DVDD
64 EMB_D[5]/GP6[5]
63 EMB_D[6]/GP6[6]
62 EMB_D[7]/GP6[7]
61 CVDD
60 EMB_WE_DQM[0]/GP5[15]
59 EMB_WE
58 DVDD
57 EMB_CAS
56 CVDD
55 EMA_WE/AXR0[12]/GP2[3]/BOOT[14]
54 EMA_D[7]/MMCSD_DAT[7]/GP0[7]/BOOT[13]
53 DVDD
52 EMA_D[6]/MMCSD_DAT[6]/GP0[6]
51 EMA_D[5]/MMCSD_DAT[5]/GP0[5]
50 CVDD
49 EMA_D[4]/MMCSD_DAT[4]/GP0[4]
48 EMA_D[3]/MMCSD_DAT[3]/GP0[3]
47 DVDD
46 EMA_D[2]/MMCSD_DAT[2]/GP0[2]
45 EMA_D[1]/MMCSD_DAT[1]/GP0[1]
DVDD
132 AMUTE1/EPWMTZ/GP4[14]
131 AFSR0/GP3[12]
130 ACLKR0/ECAP1/APWM1/GP2[15]
129 AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11]
128 DVDD
127 AFSX0/GP2[13]/BOOT[10]
126 ACLKX0/ECAP0/APWM0/GP2[12]
125 AHCLKX0/USB_REFCLKIN/GP2[11]
124 AXR0[11]/GP3[11]
123 UART1_TXD/AXR0[10]/GP3[10]
122 UART1_RXD/AXR0[9]/GP3[9]
121 AXR0[8]/MDIO_D/GP3[8]
120 AXR0[7]/MDIO_CLK/GP3[7]
119
118 AXR0[6]/RMII_RXER/GP3[6]
117 AXR0[5]/RMII_RXD[1]/GP3[5]
116 AXR0[4]/RMII_RXD[0]/GP3[4]
115 AXR0[3]/RMII_CRS_DV/GP3[3]
114
113 AXR0[2]/RMII_TXEN/GP3[2]
112 AXR0[1]/RMII_TXD[1]/GP3[1]
111 AXR0[0]/RMII_TXD[0]/GP3[0]
110 EMB_RAS
109 DVDD
108 EMB_CS[0]
107 EMB_BA[0]/GP7[1]
106 EMB_BA[1]/GP7[0]
105 EMB_A[10]/GP7[12]
104
103 EMB_A[0]/GP7[2]
102 EMB_A[1]/GP7[3]
101 EMB_A[2]/GP7[4]
100 EMB_A[3]/GP7[5]
99
98 EMB_A[4]/GP7[6]
97 EMB_A[5]/GP7[7]
96 EMB_A[6]/GP7[8]
95 EMB_A[7]/GP7[9]
94 EMB_A[8]/GP7[10]
93
92 EMB_A[9]/GP7[11]
91 EMB_A[11]/GP7[13]
90
89 EMB_A[12]/GP3[13]
DVDD
DVDD
CVDD
DVDD
CVDD
CVDD
V
(177)
SS
Thermal Pad
TMS320C6745, TMS320C6747
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Figure 3-4. Pin Map (PTP)
Copyright © 2008–2014, Texas Instruments Incorporated Device Overview 27
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3.6 Terminal Functions
to identify the external signal names, the associated pin/ball numbers along with the mechanical package
designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown
resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.
3.6.1 Device Reset and JTAG
Table 3-6. Reset and JTAG Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) DESCRIPTION
PTP ZKB
RESET
RESET 146 G3 I Device reset input
AMUTE0/ RESETOUT - L4 O(3) IPD Reset output
JTAG
TMS 152 J1 I IPU JTAG test mode select
TDI 153 J2 I IPU JTAG test data input
TDO 156 J3 O IPD JTAG test data output
TCK 155 H3 I IPU JTAG test clock
TRST 150 J4 I IPD JTAG test reset
EMU[0]/GP7[15] - J5 I/O IPU Emulation Signal
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Open drain mode for RESETOUT function.
3.6.2 High-Frequency Oscillator and PLL
Table 3-7. High-Frequency Oscillator and PLL Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) DESCRIPTION
PTP ZKB
EMA_CLK/OBSCLK/AHCLKR - R12 O IPU PLL Observation Clock
2/GP1[15]
1.2-V OSCILLATOR
OSCIN 143 F2 I Oscillator input
OSCOUT 145 F1 O Oscillator output
OSCVSS 144 E2 GND Oscillator ground (for filter only)
1.2-V PLL
PLL0_VDDA 141 D1 PWR PLL analog VDD (1.2-V filtered supply)
PLL0_VSSA 142 E1 GND PLL analog VSS (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.3 Real-Time Clock and 32-kHz Oscillator
Table 3-8. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) DESCRIPTION
PTP ZKB
RTC_CVDD - G1 PWR RTC module core power (isolated from rest of chip CVDD)
RTC_XI - H1 I Low-frequency (32-kHz) oscillator receiver for real-time clock
RTC_XO - H2 O Low-frequency (32-kHz) oscillator driver for real-time clock
RTC_Vss - G2 GND Oscillator ground (for filter)
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for
that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
3.6.4 External Memory Interface A (ASYNC, SDRAM)
Table 3-9. External Memory Interface A (EMIFA) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] - M16 I/O IPD
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] - N14 I/O IPD
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] - N16 I/O IPD
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] - P14 I/O IPD UHPI, LCD,
GPIO
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] - P16 I/O IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD MMC/SD,
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] 54 M15 I/O IPU UHPI, GPIO, EMIFA data bus
BOOT
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] 52 N13 I/O IPU
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] 51 N15 I/O IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] 49 P13 I/O IPU MMC/SD,
UHPI, GPIO
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] 48 P15 I/O IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] 46 R13 I/O IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] 45 R15 I/O IPU MMC/SD,
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU UHPI, GPIO,
BOOT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
Copyright © 2008–2014, Texas Instruments Incorporated Device Overview 29
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Table 3-9. External Memory Interface A (EMIFA) Terminal Functions (continued)
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
EMA_A[12]/LCD_MCLK/GP1[12] 42 N11 O IPU
EMA_A[11] /LCD_AC_ENB_CS/GP1[11] 41 P11 O IPU
EMA_A[10]/LCD_VSYNC/GP1[10] 27 N8 O IPU
EMA_A[9]/LCD_HSYNC/GP1[9] 40 R11 O IPU
EMA_A[8]/LCD_PCLK/GP1[8] 39 T11 O IPU LCD, GPIO EMIFA address bus
EMA_A[7]/LCD_D[0]/GP1[7] 37 N10 O IPD
EMA_A[6]/LCD_D[1]/GP1[6] 36 P10 O IPD
EMA_A[5]/LCD_D[2]/GP1[5] 35 R10 O IPD
EMA_A[4]/LCD_D[3]/GP1[4] 34 T10 O IPD
EMA_A[3]/LCD_D[6]/GP1[3] 32 N9 O IPD
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] 31 P9 O IPU MMCSD,
UHPI, GPIO
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] 30 R9 O IPU EMIFA address bus
EMA_A[0]/LCD_D[7]/GP1[0] 29 T9 O IPD LCD, GPIO
LCD, UHPI,
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] 26 P8 O IPU GPIO EMIFA bank address
EMA_BA[0]/LCD_D[4]/GP1[14] 25 R8 O IPU LCD, GPIO
McASP2,
EMA_CLK/OBSCLK/AHCLKR2/GP1[15] - R12 O IPU EMIFA clock
GPIO EMIFA SDRAM clock
EMA_SDCKE/GP2[0] - T12 O IPU GPIO enable
EMIFA SDRAM row
EMA_RAS/EMA_CS[5]/GP2[2] - N7 O IPU address strobe
EMIF A chip EMIFA SDRAM
select, GPIO
EMA_CAS/EMA_CS[4]/GP2[1] - L16 O IPU column address
strobe
EMA_RAS/EMA_CS[5] /GP2[2] - N7 O IPU EMIF A
SDRAM, GPIO
EMA_CAS/EMA_CS[4] /GP2[1] - L16 O IPU EMIFA Async Chip
McASP2,
EMA_CS[3]/AMUTE2/GP2[6] 21 T7 O IPU Select
GPIO
UHPI, GPIO,
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] 23 P7 O IPU BOOT EMIFA SDRAM chip
EMA_CS[0]/UHPI_HAS/GP2[4] - T8 O IPU UHPI, GPIO select
UHPI, EMIFA SDRAM write
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] 55 M13 O IPU MCASP0, enable
GOPIO, BOOT EMIFA write
EMA_WE_DQM[1] /UHPI_HDS2/AXR0[14]/GP2[8] - P12 O IPU enable/data mask for
EMA_D[15:8]
UHPI, McASP,
GPIO EMIFA write
EMA_WE_DQM[0] /UHPI_HINT/AXR0[15]/GP2[9] - M14 O IPU enable/data mask for
EMA_D[7:0]
UHPI,
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] 22 R7 O IPU McASP0, EMIFA output enable
GPIO EMIFA wait
EMA_WAIT[0]/ UHPI_HRDY/GP2[10] 19 N6 I IPU UHPI, GPIO input/interrupt
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3.6.5 External Memory Interface B (only SDRAM)
Table 3-10. External Memory Interface B (EMIFB) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
EMB_D[31] - G14 I/O IPD
EMB_D[30] - F15 I/O IPD
EMB_D[29] - F14 I/O IPD
EMB_D[28] - E15 I/O IPD
EMB_D[27] - E14 I/O IPD
EMB_D[26] - A14 I/O IPD
EMB_D[25] - B14 I/O IPD
EMB_D[24] - A13 I/O IPD
EMB_D[23] - L15 I/O IPD
EMB_D[22] - L14 I/O IPD
EMB_D[21] - K16 I/O IPD
EMB_D[20] - K13 I/O IPD
EMB_D[19] - J14 I/O IPD
EMB_D[18] - H15 I/O IPD
EMB_D[17] - H14 I/O IPD
EMB_D[16] - G15 I/O IPD EMIFB SDRAM data bus
EMB_D[15]/GP6[15] 74 F13 I/O IPD
EMB_D[14]/GP6[14] 76 E16 I/O IPD
EMB_D[13]/GP6[13] 78 E13 I/O IPD
EMB_D[12]/GP6[12] 79 D16 I/O IPD
EMB_D[11]/GP6[11] 80 D15 I/O IPD
EMB_D[10]/GP6[10] 82 D14 I/O IPD
EMB_D[9]/GP6[9] 83 D13 I/O IPD
EMB_D[8]/GP6[8] 84 C16 I/O IPD GPIO
EMB_D[7]/GP6[7] 62 J16 I/O IPD
EMB_D[6]/GP6[6] 63 J15 I/O IPD
EMB_D[5]/GP6[5] 64 J13 I/O IPD
EMB_D[4]/GP6[4] 66 H16 I/O IPD
EMB_D[3]/GP6[3] 68 H13 I/O IPD
EMB_D[2]/GP6[2] 70 G16 I/O IPD
EMB_D[1]/GP6[1] 72 G13 I/O IPD
EMB_D[0]/GP6[0] 73 F16 I/O IPD
EMB_A[12]/GP3[13] 89 B15 O IPD
EMB_A[11]/GP7[13] 91 B12 O IPD
EMB_A[10]/GP7[12] 105 A9 O IPD
EMB_A[9]/GP7[11] 92 C12 O IPD EMIFB SDRAM row/column
GPIO address bus
EMB_A[8]/GP7[10] 94 D12 O IPD
EMB_A[7]/GP7[9] 95 A11 O IPD
EMB_A[6]/GP7[8] 96 B11 O IPD
EMB_A[5]/GP7[7] 97 C11 O IPD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-10. External Memory Interface B (EMIFB) Terminal Functions (continued)
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
EMB_A[4]/GP7[6] 98 D11 O IPD
EMB_A[3]/GP7[5] 100 A10 O IPD EMIFB SDRAM row/column
EMB_A[2]/GP7[4] 101 B10 O IPD address
EMB_A[1]/GP7[3] 102 C10 O IPD GPIO
EMB_A[0]/GP7[2] 103 D10 O IPD
EMB_BA[1]/GP7[0] 106 B9 O IPU EMIFB SDRAM bank address
EMB_BA[0]/GP7[1] 107 C9 O IPU
EMB_CLK 86 C14 O IPU EMIF SDRAM clock
EMB_SDCKE 88 C13 O IPU EMIFB SDRAM clock enable
EMB_WE 59 K15 O IPU EMIFB write enable
EMIFB SDRAM row address
EMB_RAS 110 A8 O IPU strobe
EMIFB column address
EMB_CAS 57 L13 O IPU strobe
EMB_CS[0] 108 D9 O IPU EMIFB SDRAM chip select 0
EMB_WE_DQM[3] - A12 O IPU
EMB_WE_DQM[2] - B13 O IPU EMIFB write enable/data
mask for EMB_D
EMB_WE_DQM[1] /GP5[14] 85 C15 O IPU GPIO
EMB_WE_DQM[0] /GP5[15] 60 K14 O IPU
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3.6.6 Serial Peripheral Interface Modules (SPI0, SPI1)
Table 3-11. Serial Peripheral Interface (SPI) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
SPI0
UART0, EQEP0B,
SPI0_SCS[0] /UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I/O IPU SPI0 chip select
GPIO, BOOT
UART0, EQEP0A,
SPI0_ENA /UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I/O IPU SPI0 enable
GPIO, BOOT
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 T5 I/O IPD eQEP1, GPIO, BOOT SPI0 clock
SPI0 data slave-in-
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I/O IPD master-out
eQEP0, GPIO, BOOT SPI0 data slave-
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I/O IPD out-master-in
SPI1
SPI1_SCS[0] /UART2_TXD/GP5[13] 8 P4 I/O IPU SPI1 chip select
UART2, GPIO
SPI1_ENA /UART2_RXD/GP5[12] 7 R4 I/O IPU SPI1 enable
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 T6 I/O IPD eQEP1, GPIO, BOOT SPI1 clock
SPI1 data slave-in-
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 N5 I/O IPU master-out
I2C1, GPIO, BOOT SPI1 data slave-
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 P5 I/O IPU out-master-in
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.7 Enhanced Capture/Auxiliary PWM Modules (eCAP0, eCAP1, eCAP2)
The eCAP Module pins function as either input captures or auxiliary PWM 32-bit outputs, depending upon
how the eCAP module is programmed.
Table 3-12. Enhanced Capture Module (eCAP) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
eCAP0
enhanced capture 0
ACLKX0/ECAP0/APWM0/GP2[12] 126 C5 I/O IPD McASP0, GPIO input or auxiliary
PWM 0 output
eCAP1
enhanced capture 1
ACLKR0/ECAP1/APWM1/GP2[15] 130 B4 I/O IPD McASP0, GPIO input or auxiliary
PWM 1 output
eCAP2
enhanced capture 2
ACLKR1/ECAP2/APWM2/GP4[12] 165 L2 I/O IPD McASP1, GPIO input or auxiliary
PWM 2 output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.8 Enhanced Pulse Width Modulators (eHRPWM0, eHRPWM1, eHRPWM2)
Table 3-13. Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
eHRPWM0
eHRPWM0 A output
ACLKX1/EPWM0A/GP3[15] 162 K3 I/O IPD (with high-resolution)
McASP1, GPIO
AHCLKX1/EPWM0B/GP3[14] 160 K2 I/O IPD eHRPWM0 B output.
McASP1, eHRPWM1, eHRPWM0 trip zone
AMUTE1/EPWMTZ/GP4[14] 132 D4 I/O IPD GPIO, eHRPWM2 input
Sync input to
McASP1, eHRPWM0, eHRPWM0 module or
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 K4 I/O IPD GPIO sync output to
external PWM
eHRPWM1
eHRPWM1 A (with
AXR1[8]/EPWM1A/GP4[8] 168 M2 I/O IPD high-resolution)
McASP1, GPIO
AXR1[7]/EPWM1B/GP4[7] 169 M3 I/O IPD eHRPWM1 B output
McASP1, eHRPWM0, eHRPWM1 trip zone
AMUTE1/EPWMTZ/GP4[14] 132 D4 I/O IPD GPIO, eHRPWM2 input
eHRPWM2
eHRPWM2 A (with
AXR1[6]/EPWM2A/GP4[6] 170 M4 I/O IPD high-resolution)
McASP1, GPIO
AXR1[5]/EPWM2B/GP4[5] 171 N1 I/O IPD eHRPWM2 B output
McASP1, eHRPWM0, eHRPWM2 trip zone
AMUTE1/EPWMTZ/GP4[14] 132 D4 I/O IPD GPIO, eHRPWM2 input
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.9 Enhanced Quadrature Encoder Pulse Module (eQEP)
Table 3-14. Enhanced Quadrature Encoder Pulse Module (eQEP) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
eQEP0
eQEP0A quadrature
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU input
SPI0, UART0,
GPIO, BOOT eQEP0B quadrature
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I IPU input
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I IPD eQEP0 index
SPI0, GPIO, BOOT
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I IPD eQEP0 strobe
eQEP1
eQEP1A quadrature
AXR1[3]/EQEP1A/GP4[3] 174 P1 I IPD input
McASP1, GPIO eQEP1B quadrature
AXR1[4]/EQEP1B/GP4[4] 173 N2 I IPD input
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 T5 I IPD SPI0, GPIO, BOOT eQEP1 index
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 T6 I IPD SPI1, GPIO, BOOT eQEP1 strobe
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.10 Boot
Table 3-15. Boot Terminal Functions(1)
PIN NO
SIGNAL NAME TYPE(2) PULL(3) MUXED DESCRIPTION
PTP ZKB
EMA_CS[2]/UHPI_HCS/GP2[5]/BOOT[15] 23 P7 I IPU EMIFA, UHPI, GPIO BOOT[15]
EMIFA, UHPI,
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] 55 M13 I IPU BOOT[14]
McASP0, GPIO
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] 54 M15 I IPU BOOT[13]
EMIFA, MMC/SD,
UHPI, GPIO
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I IPU BOOT[12]
McASP0, EMAC,
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 A4 I IPD BOOT[11]
GPIO
AFSX0/GP2[13]/BOOT[10] 127 D5 I IPD McASP0, GPIO BOOT[10]
UART0, I2C0,
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 P3 I IPU BOOT[9]
Timer0, GPIO
UART0, I2C0,
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 R3 I IPU BOOT[8]
Timer0, GPIO
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 T6 I IPD SPI1, eQEP1, GPIO BOOT[7]
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 N5 I IPU BOOT[6]
SPI1, I2C1, GPIO
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 P5 I IPU BOOT[5]
SPI0, UART0,
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I IPU BOOT[4]
eQEP0, GPIO
SPI0, UART0,
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU BOOT[3]
eQEP0, GPIO
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 T5 I IPD SPI0, eQEP1, GPIO BOOT[2]
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I IPD BOOT[1]
SPI0, eQEP0, GPIO
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I IPD BOOT[0]
(1) Boot decoding will be defined in the ROM datasheet.
(2) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(3) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.11 Universal Asynchronous Receiver/Transmitters (UART0, UART1, UART2)
Table 3-16. Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
UART0
I2C0, BOOT, UART0 receive
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 R3 I IPU Timer0, GPIO, data
I2C0, Timer0, UART0 transmit
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 P3 O IPU GPIO, BOOT data
UART0 ready-to-
SPI0_SCS[0]/ UART0_RTS /EQEP0B/GP5[4]/BOOT[4] 9 N4 O IPU send output
SPI0, eQEP0,
GPIO, BOOT UART0 clear-to-
SPI0_ENA/ UART0_CTS /EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU send input
UART1
UART1 receive
UART1_RXD/AXR0[9]/GP3[9](3) 122 C6 I IPD data
McASP0, GPIO UART1 transmit
UART1_TXD/AXR0[10]/GP3[10](3) 123 D6 O IPD data
UART2
UART2 receive
SPI1_ENA/UART2_RXD/GP5[12] 7 R4 I IPU data
SPI1, GPIO UART2 transmit
SPI1_SCS[0]/UART2_TXD/GP5[13] 8 P4 O IPU data
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) As these signals are internally pulled down while the device is in reset, it is necessary to externally pull them high with resistors if
UART1 boot mode is used. Please see the TMS320C6745/C6747 DSP Technical Reference Manual (SPRUH91) for more for details on
entering UART1 boot mode.
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3.6.12 Inter-Integrated Circuit Modules (I2C0, I2C1)
Table 3-17. Inter-Integrated Circuit (I2C) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
I2C0
UART0, Timer0,
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 R3 I/O IPU I2C0 serial data
GPIO, BOOT
UART0, Timer0,
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 P3 I/O IPU I2C0 serial clock
GPIO, BOOT
I2C1
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 N5 I/O IPU I2C1 serial data
SPI1, GPIO,
BOOT
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 P5 I/O IPU I2C1 serial clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.13 Timers
Table 3-18. Timers Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
TIMER0
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 2 R3 I IPU Timer0 lower input
UART0, I2C0, Timer0 lower
GPIO, BOOT
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 3 P3 O IPU output
TIMER1 (Watchdog )
No external pins. The Timer1 peripheral pins are not pinned out as external pins.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.14 Universal Host-Port Interface (UHPI)
Note:
The UHPI module requires 16 data pins for the host port interface to function. Therefore on the PTP, the
UHPI is not available.
Table 3-19. Universal Host-Port Interface (UHPI) Terminal Functions
PIN NO TYPE(
SIGNAL NAME PULL(2) MUXED DESCRIPTION
1)
PTP ZKB
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] - M16 I/O IPD
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] - N14 I/O IPD
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] - N16 I/O IPD
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] - P14 I/O IPD EMIFA, LCD, GPIO
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] - P16 I/O IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/ EMIFA, MMC/SD, UHPI data bus
- M15 I/O IPU
BOOT[13] GPIO, BOOT
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] - N13 I/O IPU
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] - N15 I/O IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] - P13 I/O IPU EMIFA, MMC/SD,
GPIO
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] - P15 I/O IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] - R13 I/O IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] - R15 I/O IPU
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/ EMIFA, MMC/SD,
- T13 I/O IPU
BOOT[12] GPIO, BOOT
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] - P9 I/O IPU EMIFA,
MMCSD_CMD, UHPI access control
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] - R9 I/O IPU GPIO UHPI half-word
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] - P8 I/O IPU EMIFA, LCD, GPIO identification control
EMIFA, McASP,
EMA_WE/UHPI_HRW /AXR0[12]/GP2[3]/BOOT[14] - M13 I/O IPU UHPI read/write
GPIO, BOOT
EMIFA, GPIO,
EMA_CS[2]/ UHPI_HCS /GP2[5]/BOOT[15] - P7 I/O IPU UHPI chip select
BOOT
EMA_WE_DQM[1]/ UHPI_HDS2 /AXR0[14]/GP2[8] - P12 I/O IPU UHPI data strobe
EMIFA, McASP0,
EMA_OE/ UHPI_HDS1 /AXR0[13]/GP2[7] - R7 I/O IPU GPIO
EMA_WE_DQM[0]/ UHPI_HINT /AXR0[15]/GP2[9] - M14 I/O IPU UHPI host interrupt
EMA_WAIT[0]/ UHPI_HRDY /GP2[10] - N6 I/O IPU UHPI ready
EMIFA, GPIO UHPI address
EMA_CS[0]/ UHPI_HAS /GP2[4] - T8 I/O IPU strobe
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.15 Multichannel Audio Serial Ports (McASP0, McASP1, McASP2)
Table 3-20. Multichannel Audio Serial Ports (McASPs) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
McASP0
EMA_WE_DQM[0]/UHPI_HINT/AXR0[15]/GP2[9] - M14 I/O IPU EMIFA, UHPI,
EMA_WE_DQM[1]/UHPI_HDS2/AXR0[14]/GP2[8] - P12 I/O IPU GPIO
EMA_OE/UHPI_HDS1/AXR0[13]/GP2[7] 22 R7 I/O IPU EMIFA, UHPI,
EMA_WE/UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] 55 M13 I/O IPU GPIO, BOOT
McASP2,
AXR0[11]/AXR2[0]/GP3[11] 124 A5 I/O IPD GPIO
UART1_TXD/AXR0[10]/GP3[10] 123 D6 I/O IPD UART1, GPIO
UART1_RXD/AXR0[9]/GP3[9] 122 C6 I/O IPD UART1, GPIO McASP0 serial
AXR0[8]/MDIO_D/GP3[8] 121 B6 I/O IPU data
MDIO, GPIO
AXR0[7]/MDIO_CLK/GP3[7] 120 A6 I/O IPD
AXR0[6]/RMII_RXER/ACLKR2/GP3[6] 118 D7 I/O IPD
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] 117 C7 I/O IPD
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] 116 B7 I/O IPD EMAC,
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] 115 A7 I/O IPD McASP2,
GPIO
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] 113 D8 I/O IPD
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] 112 C8 I/O IPD
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] 111 B8 I/O IPD McASP0
McASP2, USB,
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] 125 B5 I/O IPD transmit master
GPIO clock
McASP0
ACLKX0/ECAP0/APWM0/GP2[12] 126 C5 I/O IPD eCAP0, GPIO transmit bit
clock
McASP0
AFSX0/GP2[13]/BOOT[10] 127 D5 I/O IPD GPIO, BOOT transmit frame
sync
EMAC, GPIO, McASP0 receive
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 A4 I/O IPD BOOT master clock
McASP0 receive
ACLKR0/ECAP1/APWM1/GP2[15] 130 B4 I/O IPD eCAP1, GPIO bit clock
McASP0 receive
AFSR0/GP3[12] 131 C4 I/O IPD GPIO frame sync
McASP0 mute
AMUTE0/RESETOUT - L4 O IPD RESETOUT output
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-20. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
McASP1
AXR1[11]/GP5[11] 6 T4 I/O IPU
AXR1[10]/GP5[10] 4 N3 I/O IPU GPIO
AXR1[9]/GP4[9] - M1 I/O IPD eHRPWM1 A,
AXR1[8]/EPWM1A/GP4[8] 168 M2 I/O IPD GPIO
eHRPWM1 B,
AXR1[7]/EPWM1B/GP4[7] 169 M3 I/O IPD GPIO
eHRPWM2 A, McASP1 serial
AXR1[6]/EPWM2A/GP4[6] 170 M4 I/O IPD GPIO data
eHRPWM2 B,
AXR1[5]/EPWM2B/GP4[5] 171 N1 I/O IPD GPIO
AXR1[4]/EQEP1B/GP4[4] 173 N2 I/O IPD eQEP, GPIO
AXR1[3]/EQEP1A/GP4[3] 174 P1 I/O IPD
AXR1[2]/GP4[2] 175 P2 I/O IPD
AXR1[1]/GP4[1] 176 R2 I/O IPD GPIO
AXR1[0]/GP4[0] 1 T3 I/O IPD McASP1
eHRPWM0,
AHCLKX1/EPWM0B/GP3[14] 160 K2 I/O IPD transmit master
GPIO clock
McASP1
eHRPWM0,
ACLKX1/EPWM0A/GP3[15] 162 K3 I/O IPD transmit bit
GPIO clock
McASP1
eHRPWM0,
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 K4 I/O IPD transmit frame
GPIO sync
McASP1 receive
AHCLKR1/GP4[11] - L1 I/O IPD GPIO master clock
McASP1 receive
ACLKR1/ECAP2/APWM2/GP4[12] 165 L2 I/O IPD eCAP2, GPIO bit clock
McASP1 receive
AFSR1/GP4[13] 166 L3 I/O IPD GPIO frame sync
eHRPWM0,
eHRPWM1, McASP1 mute
AMUTE1/EPWMTZ/GP4[14] 132 D4 O IPD eHRPWM2, output
GPIO
McASP2
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] - B8 I/O IPD
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] - D8 I/O IPD McASP0,
EMAC, GPIO
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] - A7 I/O IPD McASP2 serial
data
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] - B7 I/O IPD McASP0,
AXR0[11]/AXR2[0]/GP3[11] - A5 I/O IPD GPIO McASP2
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] - B5 I/O IPD transmit master
clock
McASP0, USB,
GPIO McASP2
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] - C8 I/O IPD transmit bit
clock
McASP2
McASP0,
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] - C7 I/O IPD transmit frame
EMAC, GPIO sync
McASP2 receive
EMA_CLK/OBSCLK/AHCLKR2/GP1[15] - R12 I/O IPU EMIFA, GPIO master clock
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Table 3-20. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
McASP0, McASP2 receive
AXR0[6]/RMII_RXER/ACLKR2/GP3[6] - D7 I/O IPD EMAC, GPIO bit clock
McASP2 mute
EMA_CS[3]/AMUTE2/GP2[6] - T7 O IPU EMIFA, GPIO output
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3.6.16 Universal Serial Bus Modules (USB0, USB1)
Table 3-21. Universal Serial Bus (USB) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) DESCRIPTION
PTP ZKB
USB0 2.0 OTG (USB0)
USB0_DM 138 G4 A USB0 PHY data minus
USB0_DP 137 F4 A USB0 PHY data plus
USB0_VDDA33 140 H5 PWR USB0 PHY 3.3-V supply
USB0_VDDA18 135 E3 PWR USB0 PHY 1.8-V supply input
USB0 PHY 1.2-V LDO output for bypass cap
For proper device operation, this pin is
USB0_VDDA12(3) 134 C3 PWR recommended to be connected via a 0.22-μF
capacitor to VSS (GND), even if USB0 is not
being used.
USB0_ID - D2 A USB0 PHY identification (mini-A or mini-B plug)
USB0_VBUS - D3 A USB0 bus voltage
USB0_DRVVBUS/GP4[15] - E4 O IPD USB0 controller VBUS control output
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] 125 B5 I IPD USB_REFCLKIN. Optional clock input
USB1 1.1 OHCI (USB1)
USB1_DM - B3 A USB1 PHY data minus
USB1_DP - A3 A USB1 PHY data plus
USB1_VDDA33 - C1 PWR USB1 PHY 3.3-V supply
USB1_VDDA18 - C2 PWR USB1 PHY 1.8-V supply
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] 125 B5 I IPD USB_REFCLKIN. Optional clock input.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Core power supply LDO output for USB PHY.
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3.6.17 Ethernet Media Access Controller (EMAC)
Table 3-22. Ethernet Media Access Controller (EMAC) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
RMII
EMAC 50-MHz
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 A4 I/O IPD McASP0, GPIO, BOOT clock input or
output
EMAC RMII
AXR0[6]/RMII_RXER/ACLKR2/GP3[6] 118 D7 I IPD receiver error
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] 117 C7 I IPD EMAC RMII
receive data
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] 116 B7 I IPD EMAC RMII carrier
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] 115 A7 I IPD McASP0, McASP2, GPIO sense data valid
EMAC RMII
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] 113 D8 O IPD transmit enable
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] 112 C8 O IPD EMAC RMII trasmit
data
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] 111 B8 O IPD
MDIO
AXR0[8]/MDIO_D/GP3[8] 121 B6 I/O IPU McASP0, GPIO MDIO data clock
AXR0[7]/MDIO_CLK/GP3[7] 120 A6 O IPD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.18 Multimedia Card/Secure Digital (MMC/SD)
Table 3-23. Multimedia Card/Secure Digital (MMC/SD) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] 30 R9 O IPU MMCSD Clock
EMIFA, UHPI, GPIO MMCSD
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] 31 P9 I/O IPU Command
EMIFA, UHPI, GPIO,
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] 54 M15 I/O IPU BOOT
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] 52 N13 I/O IPU
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] 51 N15 I/O IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] 49 P13 I/O IPU EMIFA, UHPI, GPIO MMC/SD data
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] 48 P15 I/O IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] 46 R13 I/O IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] 45 R15 I/O IPU EMIFA, UHPI, GPIO,
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU BOOT
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.19 Liquid Crystal Display Controller (LCD)
Table 3-24. Liquid Crystal Display Controller (LCD) Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
EMA_D[15]/UHPI_HD[15]/LCD_D [15]/GP0[15] - M16 I/O IPD
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] - N14 I/O IPD
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] - N16 I/O IPD
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] - P14 I/O IPD EMIFA, UHPI,
GPIO
EMA_D[11]/UHPI_HD[11]/LCD_D[11 ]/GP0[11] - P16 I/O IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD LCD data bus
EMA_A[0]/LCD_D[7]/GP1[0] - T9 I/O IPD EMIFA, GPIO
EMA_A[3]/LCD_D[6]/GP1[3] - N9 I/O IPD EMIFA, UHPI,
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] - P8 I/O IPU GPIO
EMA_BA[0]/LCD_D[4]/GP1[14] - R8 I/O IPU
EMA_A[4]/LCD_D[3]/GP1[4] - T10 I/O IPD
EMA_A[5]/LCD_D[2]/GP1[5] - R10 I/O IPD
EMA_A[6]/LCD_D[1]/GP1[6] - P10 I/O IPD
EMA_A[7]/LCD_D[0]/GP1[7] - N10 I/O IPD EMIFA, GPIO
EMA_A[8]/LCD_PCLK/GP1[8] - T11 O IPU LCD pixel clock
EMA_A[9]/LCD_HSYNC/GP1[9] - R11 O IPU LCD horizontal sync
EMA_A[10]/LCD_VSYNC/GP1[10] - N8 O IPU LCD vertical sync
LCD AC bias enable
EMA_A[11]/ LCD_AC_ENB_CS /GP1[11] - P11 O IPU chip select
EMA_A[12]/LCD_MCLK/GP1[12] - N11 O IPU LCD memory clock
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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3.6.20 General Purpose Input Output (GPIO)
Table 3-25. General Purpose Input Output Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
GP0
EMA_D[15]/UHPI_HD[15]/LCD_D[15]/GP0[15] - M16 I/O IPD
EMA_D[14]/UHPI_HD[14]/LCD_D[14]/GP0[14] - N14 I/O IPD
EMA_D[13]/UHPI_HD[13]/LCD_D[13]/GP0[13] - N16 I/O IPD
EMA_D[12]/UHPI_HD[12]/LCD_D[12]/GP0[12] - P14 I/O IPD EMIFA, UHPI,
LCD
EMA_D[11]/UHPI_HD[11]/LCD_D[11]/GP0[11] - P16 I/O IPD
EMA_D[10]/UHPI_HD[10]/LCD_D[10]/GP0[10] - R14 I/O IPD
EMA_D[9]/UHPI_HD[9]/LCD_D[9]/GP0[9] - T14 I/O IPD
EMA_D[8]/UHPI_HD[8]/LCD_D[8]/GP0[8] - N12 I/O IPD EMIFA, MMC/SD, GPIO Bank 0
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/BOOT[13] 54 M15 I/O IPU UHPI, BOOT
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6] 52 N13 I/O IPU
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5] 51 N15 I/O IPU
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4] 49 P13 I/O IPU EMIFA, MMC/SD,
UHPI
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3] 48 P15 I/O IPU
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2] 46 R13 I/O IPU
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1] 45 R15 I/O IPU EMIFA, MMC/SD,
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/BOOT[12] 44 T13 I/O IPU UHPI, BOOT
GP1
EMA_CLK/OBSCLK/AHCLKR2/GP1[15] - R12 O IPU EMIFA, McASP2
EMA_BA[0]/LCD_D[4]/GP1[14] 25 R8 O IPU EMIFA, LCD
EMIFA, LCD,
EMA_BA[1]/LCD_D[5]/UHPI_HHWIL/GP1[13] 26 P8 O IPU UHPI
EMA_A[12]/LCD_MCLK/GP1[12] 42 N11 O IPU
EMA_A[11]/ LCD_AC_ENB_CS/GP1[11] 41 P11 O IPU
EMA_A[10]/LCD_VSYNC/GP1[10] 27 N8 O IPU
EMA_A[9]/LCD_HSYNC/GP1[9] 40 R11 O IPU
EMA_A[8]/LCD_PCLK/GP1[8] 39 T11 O IPU GPIO Bank 1
EMIFA, LCD
EMA_A[7]/LCD_D[0]/GP1[7] 37 N10 O IPD
EMA_A[6]/LCD_D[1]/GP1[6] 36 P10 O IPD
EMA_A[5]/LCD_D[2]/GP1[5] 35 R10 O IPD
EMA_A[4]/LCD_D[3]/GP1[4] 34 T10 O IPD
EMA_A[3]/LCD_D[6]/GP1[3] 32 N9 O IPD
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2] 31 P9 O IPU EMIFA, MMCSD,
UHPI
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1] 30 R9 O IPU
EMA_A[0]/LCD_D[7]/GP1[0] 29 T9 O IPD EMIFA, LCD
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
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Table 3-25. General Purpose Input Output Terminal Functions (continued)
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
GP2
ACLKR0/ECAP1/APWM1/GP2[15] 130 b4 I/O IPD McASP0, eCAP1
McASP0, EMAC,
AHCLKR0/RMII_MHZ_50_CLK/GP2[14]/BOOT[11] 129 A4 I/O IPD BOOT
AFSX0/GP2[13]/BOOT[10] 127 D5 I/O IPD McASP0, BOOT
ACLKX0/ECAP0/APWM0/GP2[12] 126 CD I/O IPD McASP0, eCAP0
McASP0,
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11] 125 B5 I IPD McASP2, USB
EMA_WAIT[0]/ UHPI_HRDY/GP2[10] 19 N6 I IPU EMIFA, UHPI
EMA_WE_DQM[0] /UHPI_HINT/AXR0[15]/GP2[9] - M14 O IPU EMIFA, UHPI,
EMA_WE_DQM[1] /UHPI_HDS2/AXR0[14]/GP2[8] - P12 O IPU McASP0 GPIO Bank 2
EMA_OE /UHPI_HDS1/AXR0[13]/GP2[7] 22 R7 O IPU
EMA_CS[3] /AMUTE2/GP2[6] 21 T7 O IPU EMIFA, McASP2
EMIFA, UHPI,
EMA_CS[2] /UHPI_HCS/GP2[5]/BOOT[15] 23 P7 O IPU BOOT
EMA_CS[0] /UHPI_HAS/GP2[4] - T8 O IPU EMIFA, UHPI
EMIFA, UHPI,
EMA_WE /UHPI_HRW/AXR0[12]/GP2[3]/BOOT[14] 55 M13 O IPU MCASP0, BOOT
EMA_RAS /EMA_CS[5]/GP2[2] - N7 O IPU EMIFA, EMIFA
EMA_CAS /EMA_CS[4]/GP2[1] - L16 O IPU
EMA_SDCKE/GP2[0] - T12 O IPU EMIFA
GP3
ACLKX1/EPWM0A/GP3[15] 162 K3 I/O IPD McASP1,
eHRPWM0
AHCLKX1/EPWM0B/GP3[14] 160 K2 I/O IPD
EMB_A[12]/GP3[13] 89 B15 O IPD EMIFB
AFSR0/GP3[12] 131 C4 I/O IPD McASP0
AXR0[11]/AXR2[0]/GP3[11] - A5 I/O IPD EMAC,
UART1_TXD/AXR0[10]/GP3[10] 123 D6 I/O IPD UART1, McASP0
UART1_RXD/AXR0[9]/GP3[9] 122 C6 I/O IPD
AXR0[8]/MDIO_D/GP3[8] 121 B6 I/0 IPU McASP0, MDIO GPIO Bank 3
AXR0[7]/MDIO_CLK/GP3[7] 120 A6 O IPD
AXR0[6]/RMII_RXER/ACLKR2/GP3[6] 118 D7 I IPD
AXR0[5]/RMII_RXD[1]/AFSX2/GP3[5] 117 C7 I IPD
AXR0[4]/RMII_RXD[0]/AXR2[1]/GP3[4] 116 B7 I IPD McASP0, EMAC,
AXR0[3]/RMII_CRS_DV/AXR2[2]/GP3[3] 115 A7 I IPD McASP2
AXR0[2]/RMII_TXEN/AXR2[3]/GP3[2] 113 D8 O IPD
AXR0[1]/RMII_TXD[1]/ACLKX2/GP3[1] 112 C8 O IPD
AXR0[0]/RMII_TXD[0]/AFSR2/GP3[0] 111 B8 O IPD
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Table 3-25. General Purpose Input Output Terminal Functions (continued)
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
GP4
USB0_DRVVBUS/GP4[15] - E4 O IPD USB0
McASP1,
eHRPWM0,
AMUTE1/EPWMTZ/GP4[14] 132 D4 O IPD eHRPWM1,
eHRPWM2
AFSR1/GP4[13] 166 L3 I/O IPD McASP1
ACLKR1/ECAP2/APWM2/GP4[12] 165 L2 I/O IPD McASP1, eCAP2
AHCLKR1/GP4[11] - L1 I/O IPD McASP1
McASP1,
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10] 163 K4 I/O IPD eHRPWM0
AXR1[9]/GP4[9] - M1 I/O IPD McASP1
McASP1,
AXR1[8]/EPWM1A/GP4[8] 168 M2 I/O IPD GPIO Bank 4
eHRPWM1 A
McASP1,
AXR1[7]/EPWM1B/GP4[7] 169 M3 I/O IPD eHRPWM1 B
McASP1,
AXR1[6]/EPWM2A/GP4[6] 170 M4 I/O IPD eHRPWM2 A
McASP1,
AXR1[5]/EPWM2B/GP4[5] 171 N1 I/O IPD eHRPWM2 B
AXR1[4]/EQEP1B/GP4[4] 173 N2 I/O IPD McASP1, eQEP
AXR1[3]/EQEP1A/GP4[3] 174 P1 I/O IPD
AXR1[2]/GP4[2] 175 P2 I/O IPD
AXR1[1]/GP4[1] 176 R2 I/O IPD McASP1
AXR1[0]/GP4[0] 1 T3 I/O IPD
GP5
EMB_WE_DQM[0]/GP5[15] 60 K14 O IPU EMIFB
EMB_WE_DQM[1]/GP5[14] 85 C15 O IPU
SPI1_SCS[0]/UART2_TXD/GP5[13] 8 P4 O IPU SPI1, UART2
SPI1_ENA/UART2_RXD/GP5[12] 7 R4 I IPU
AXR1[11]/GP5[11] 6 T4 I/O IPU McASP1
AXR1[10]/GP5[10] 4 N3 I/O IPU
UART0_TXD/I2C0_SCL/TM64P0_OUT12/GP5[9]/BOOT[9] 2 R3 I IPU UART0, I2C0,
BOOT
UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] 3 P3 O IPU SPI1, eQEP1, GPIOBank 5
SPI1_CLK/EQEP1S/GP5[7]/BOOT[7] 16 T6 I IPD BOOT
SPI1_SIMO[0]/I2C1_SDA/GP5[6]/BOOT[6] 14 N5 I/O IPU SPI1, I2C1,
BOOT
SPI1_SOMI[0]/I2C1_SCL/GP5[5]/BOOT[5] 13 P5 I/O IPU
SPI0_SCS[0]/UART0_RTS/EQEP0B/GP5[4]/BOOT[4] 9 N4 I IPU SPI0, UART0,
eQEP0, BOOT
SPI0_ENA/UART0_CTS/EQEP0A/GP5[3]/BOOT[3] 12 R5 I IPU SPI0, eQEP1,
SPI0_CLK/EQEP1I/GP5[2]/BOOT[2] 11 T5 I IPD BOOT
SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] 18 P6 I IPD SPI0, eQEP0,
BOOT
SPI0_SOMI[0]/EQEP0I/GP5[0]/BOOT[0] 17 R6 I IPD
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Table 3-25. General Purpose Input Output Terminal Functions (continued)
PIN NO
SIGNAL NAME TYPE(1) PULL(2) MUXED DESCRIPTION
PTP ZKB
GP6
EMB_D[15]/GP6[15] 74 F13 I/O IPD
EMB_D[14]/GP6[14] 76 E`6 I/O IPD
EMB_D[13]/GP6[13] 78 E13 I/O IPD
EMB_D[12]/GP6[12] 79 D16 I/O IPD
EMB_D[11]/GP6[11] 80 D15 I/O IPD
EMB_D[10]/GP6[10] 82 D14 I/O IPD
EMB_D[9]/GP6[9] 83 D13 I/O IPD
EMB_D[8]/GP6[8] 84 C16 I/O IPD EMIFB GPIO Bank 6
EMB_D[7]/GP6[7] 62 J16 I/O IPD
EMB_D[6]/GP6[6] 63 J15 I/O IPD
EMB_D[5]/GP6[5] 64 J13 I/O IPD
EMB_D[4]/GP6[4] 66 H16 I/O IPD
EMB_D[3]/GP6[3] 68 H13 I/O IPD
EMB_D[2]/GP6[2] 70 G16 I/O IPD
EMB_D[1]/GP6[1] 72 G13 I/O IPD
EMB_D[0]/GP6[0] 73 F16 I/O IPD
GP7
EMU[0]/GP7[15] - J5 I/O IPU JTAG General-Purpose
RTCK/ GP7[14] (1) 157 K1 I/O IPD IO signal
EMB_A[11]/GP7[13] 91 B12 O IPD
EMB_A[10]/GP7[12] 105 A9 O IPD
EMB_A[9]/GP7[11] 92 C12 O IPD
EMB_A[8]/GP7[10] 94 D12 O IPD
EMB_A[7]/GP7[9] 95 A11 O IPD
EMB_A[6]/GP7[8] 96 B11 O IPD
EMB_A[5]/GP7[7] 97 C11 O IPD EMIFB GPIO Bank 7
EMB_A[4]/GP7[6] 98 D11 O IPD
EMB_A[3]/GP7[5] 100 A10 O IPD
EMB_A[2]/GP7[4] 101 B10 O IPD
EMB_A[1]/GP7[3] 102 C10 O IPD
EMB_A[0]/GP7[2] 103 D10 O IPD
EMB_BA[0]/GP7[1] 107 C9 O IPU
EMB_BA[1]/GP7[0] 106 B9 O IPU
(1) GP7[14] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after
the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an
unknown state after reset.
3.6.21 Reserved and No Connect
Table 3-26. Reserved and No Connect Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) DESCRIPTION
PTP ZKB
Reserved. (Leave unconnected, do not connect to power or
RSV1 - F7 - ground.)
(1) PWR = Supply voltage.
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Table 3-26. Reserved and No Connect Terminal Functions (continued)
PIN NO
SIGNAL NAME TYPE(1) DESCRIPTION
PTP ZKB
Reserved. For proper device operation, this pin must be tied either
RSV2 133 B1 PWR directly to CVDD or left unconnected [do not connect to ground
(VSS)].
Reserved. For proper device operation, this pin must be tied
RSV3 149 - PWR directly to CVDD.
Reserved. For proper device operation, this pin must be tied low or
RSV4 148 - I to CVDD.
NC 136 F3 - No Connect (leave unconnected)
NC 139 H4 - No Connect (leave unconnected)
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3.6.22 Supply and Ground
Table 3-27. Supply and Ground Terminal Functions
PIN NO
SIGNAL NAME TYPE(1) DESCRIPTION
PTP ZKB
F6,G6, G7,
10, 20, 28, G10, G11,
38, 50, 56, H7, H10,
61, 69, 77,
CVDD (Core supply) H11, J6, J7, PWR Core supply voltage pins
93, 104, 114, J10, J11,
147, 154, J12, K6, K7,
161, 167 K10, K11,L6
RVDD (Internal RAM supply) 67, 159 H6, H12 PWR Internal ram supply voltage pins
5, 15, 24, 33, B16, E5, E8,
43, 47, 53, E9, E12, F5,
58, 65, 71, F11, F12,
75, 81, 87, G5, G12, K5,
DVDD (I/O supply) PWR I/O supply voltage pins
90, 99, 109, K12, L5, L11,
119, 128, L12, M5, M8,
151, 158, M9, M12, R1,
164, 172 R16
A1, A2, A15,
A16,
B2,
E6, E7, E10,
E11,
F8, F9, F10,
G8, G9,
H8, H9,
VSS (Ground) 177 GND Ground pins
J8, J9,
K8, K9,
L7, L8, L9,
L10,
M6, M7, M10,
M11,
T1, T2, T15,
T16
(1) PWR = Supply voltage, GND - Ground.
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
3.6.23 Unused USB0 (USB2.0) and USB1 (USB1.1) Pin Configurations
If one or both USB modules on the device are not used, then some of the power supplies to those
modules may not be required. This can eliminate the requirement for a 1.8V power supply to the USB
modules. The required pin configurations for unused USB modules are shown below.
Table 3-28. Unused USB0 and USB1 Pin Configurations
SIGNAL NAME Configuration Configuration
(When USB0 and USB1 are not used) (When USB0 is used
and USB1 is not used)
USB0_DM No connect Use as USB0 function
USB0_DP No connect Use as USB0 function
USB0_VDDA33 No connect 3.3V
USB0_VDDA18 No connect 1.8V
USB0_ID No connect Use as USB0 function
USB0_VBUS No connect Use as USB0 function
USB0_DRVVBUS/GP4[15] No connect or use as alternate function Use as USB0 or alternate function
USB0_VDDA12 Internal USB0 PHY output connected to an external 0.22μF filter capacitor
USB1_DM No connect VSS
USB1_DP No connect VSS
USB1_VDDA33 No connect No connect
USB1_VDDA18 No connect No connect
AHCLKX0/AHCLKX2/USB_REFCLKIN/ No connect or use as alternate function Use as USB0 or alternate function
GP2[11]
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4 Device Configuration
4.1 Boot Modes
This device supports a variety of boot modes through an internal ROM bootloader. This device does not
support dedicated hardware boot modes; therefore, all boot modes utilize the internal ROM. The input
states of the BOOT pins are sampled and latched into the BOOTCFG register, which is part of the system
configuration (SYSCFG) module, when device reset is deasserted. Boot mode selection is determined by
the values of the BOOT pins.
The following boot modes are supported:
• NAND Flash boot
– 8-bit NAND
– 16-bit NAND
• NOR Flash boot
– NOR Direct boot (8-bit or 16-bit)
– NOR Legacy boot (8-bit or 16-bit)
– NOR AIS boot (8-bit or 16-bit)
• HPI Boot [C6747 only]
• I2C0 / I2C1 Boot
– EEPROM (Master Mode)
– External Host (Slave Mode)
• SPI0 / SPI1 Boot
– Serial Flash (Master Mode)
– SERIAL EEPROM (Master Mode)
– External Host (Slave Mode)
• UART0 / UART1 / UART2 Boot
– External Host
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4.2 SYSCFG Module
The following system level features of the chip are controlled by the SYSCFG peripheral:
• Readable Device, Die, and Chip Revision ID
• Control of Pin Multiplexing
• Priority of bus accesses different bus masters in the system
• Capture at power on reset the chip BOOT[15:0] pin values and make them available to software
• Special case settings for peripherals:
– Locking of PLL controller settings
– Default burst sizes for EDMA3 TC0 and TC1
– Selection of the source for the eCAP module input capture (including on chip sources)
– McASP AMUTEIN selection and clearing of AMUTE status for the three McASP peripherals
– Control of the reference clock source and other side-band signals for both of the integrated USB
PHYs
– Clock source selection for EMIFA and EMIFB
• Selects the source of emulation suspend signal (from DSP) of peripherals supporting this function.
Many registers are accessible only by a host (DSP) when it is operating in its privileged mode. (ex. from
the kernel, but not from user space code).
Table 4-1. System Configuration (SYSCFG) Module Register Access
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION ACCESS
0x01C1 4000 REVID Revision Identification Register —
0x01C14008 DIEIDR0 Device Identification Register 0 —
0x01C1 400C DIEIDR1 Device Identification Register 1 —
0x01C1 4010 DIEIDR2 Device Identification Register 2 —
0x01C1 4014 DIEIDR3 Device Identification Register 3 —
0x01C1 4018 DEVIDR0 JTAG Identification Register —
0x01C1 4020 BOOTCFG Boot Configuration Register Privileged mode
0x01C1 4024 CHIPREVID Silicon Revision Identification Register Privileged mode
0x01C1 4038 KICK0R Kick 0 Register Privileged mode
0x01C1 403C KICK1R Kick 1 Register Privileged mode
0x01C1 4040 HOST0CFG Host 0 Configuration Register —
0x01C1 4044 HOST1CFG Host 1 Configuration Register —
0x01C1 40E0 IRAWSTAT Interrupt Raw Status/Set Register Privileged mode
0x01C1 40E4 IENSTAT Interrupt Enable Status/Clear Register Privileged mode
0x01C1 40E8 IENSET Interrupt Enable Register Privileged mode
0x01C1 40EC IENCLR Interrupt Enable Clear Register Privileged mode
0x01C1 40F0 EOI End of Interrupt Register Privileged mode
0x01C1 40F4 FLTADDRR Fault Address Register Privileged mode
0x01C1 40F8 FLTSTAT Fault Status Register —
0x01C1 4110 MSTPRI0 Master Priority 0 Register Privileged mode
0x01C1 4114 MSTPRI1 Master Priority 1 Register Privileged mode
0x01C1 4118 MSTPRI2 Master Priority 2 Register Privileged mode
0x01C1 4120 PINMUX0 Pin Multiplexing Control 0 Register Privileged mode
0x01C1 4124 PINMUX1 Pin Multiplexing Control 1 Register Privileged mode
0x01C1 4128 PINMUX2 Pin Multiplexing Control 2 Register Privileged mode
0x01C1 412C PINMUX3 Pin Multiplexing Control 3 Register Privileged mode
0x01C1 4130 PINMUX4 Pin Multiplexing Control 4 Register Privileged mode
0x01C1 4134 PINMUX5 Pin Multiplexing Control 5 Register Privileged mode
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Table 4-1. System Configuration (SYSCFG) Module Register Access (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION ACCESS
0x01C1 4138 PINMUX6 Pin Multiplexing Control 6 Register Privileged mode
0x01C1 413C PINMUX7 Pin Multiplexing Control 7 Register Privileged mode
0x01C1 4140 PINMUX8 Pin Multiplexing Control 8 Register Privileged mode
0x01C1 4144 PINMUX9 Pin Multiplexing Control 9 Register Privileged mode
0x01C1 4148 PINMUX10 Pin Multiplexing Control 10 Register Privileged mode
0x01C1 414C PINMUX11 Pin Multiplexing Control 11 Register Privileged mode
0x01C1 4150 PINMUX12 Pin Multiplexing Control 12 Register Privileged mode
0x01C1 4154 PINMUX13 Pin Multiplexing Control 13 Register Privileged mode
0x01C1 4158 PINMUX14 Pin Multiplexing Control 14 Register Privileged mode
0x01C1 415C PINMUX15 Pin Multiplexing Control 15 Register Privileged mode
0x01C1 4160 PINMUX16 Pin Multiplexing Control 16 Register Privileged mode
0x01C1 4164 PINMUX17 Pin Multiplexing Control 17 Register Privileged mode
0x01C1 4168 PINMUX18 Pin Multiplexing Control 18 Register Privileged mode
0x01C1 416C PINMUX19 Pin Multiplexing Control 19 Register Privileged mode
0x01C1 4170 SUSPSRC Suspend Source Register Privileged mode
0x01C1 4174 CHIPSIG Chip Signal Register —
0x01C1 4178 CHIPSIG_CLR Chip Signal Clear Register —
0x01C1 417C CFGCHIP0 Chip Configuration 0 Register Privileged mode
0x01C1 4180 CFGCHIP1 Chip Configuration 1 Register Privileged mode
0x01C1 4184 CFGCHIP2 Chip Configuration 2 Register Privileged mode
0x01C1 4188 CFGCHIP3 Chip Configuration 3 Register Privileged mode
0x01C1 418C CFGCHIP4 Chip Configuration 4 Register Privileged mode
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4.3 Pullup/Pulldown Resistors
Proper board design should ensure that input pins to the device always be at a valid logic level and not
floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and
internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external
pullup/pulldown resistors.
An external pullup/pulldown resistor needs to be used in the following situations:
• Boot and Configuration Pins: If the pin is both routed out and 3-stated (not driven), an external
pullup/pulldown resistor is strongly recommended, even if the IPU/IPD matches the desired value/state.
• Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external
pullup/pulldown resistor to pull the signal to the opposite rail.
For the boot and configuration pins, if they are both routed out and 3-stated (not driven), it is strongly
recommended that an external pullup/pulldown resistor be implemented. Although, internal
pullup/pulldown resistors exist on these pins and they may match the desired configuration value,
providing external connectivity can help ensure that valid logic levels are latched on these device boot and
configuration pins. In addition, applying external pullup/pulldown resistors on the boot and configuration
pins adds convenience to the user in debugging and flexibility in switching operating modes.
Tips for choosing an external pullup/pulldown resistor:
• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
pulldown resistors.
• Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
the limiting device; which, by definition, have margin to the VIL and VIH levels.
• Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
will reach the target pulled value when maximum current from all devices on the net is flowing through
the resistor. The current to be considered includes leakage current plus, any other internal and
external pullup/pulldown resistors on the net.
• For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
can drive the net to the opposite logic level (including margin).
• Remember to include tolerances when selecting the resistor value.
• For pullup resistors, also remember to include tolerances on the IO supply rail.
• For most systems, a 1-kΩresistor can be used to oppose the IPU/IPD while meeting the above
criteria. Users should confirm this resistor value is correct for their specific application.
• For most systems, a 20-kΩresistor can be used to compliment the IPU/IPD on the boot and
configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
for their specific application.
• For more detailed information on input current (II), and the low-/high-level input voltages (VIL and VIH)
for the device, see Section 5.3, Recommended Operating Conditions.
• For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
functions table.
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5 Device Operating Conditions
5.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) (1)
Core -0.5 V to 1.4 V
(CVDD, RVDD, RTC_CVDD, PLL0_VDDA ) (2)
I/O, 1.8V -0.5 V to 2 V
Supply voltage ranges (USB0_VDDA18, USB1_VDDA18) (2)
I/O, 3.3V -0.5 V to 3.8V
(DVDD, USB0_VDDA33, USB1_VDDA33) (2)
VII/O, 1.2V -0.3 V to CVDD + 0.3V
(OSCIN, RTC_XI)
VII/O, 3.3V -0.3V to DVDD + 0.35V
(Steady State)
VII/O, 3.3V DVDD + 20%
Input voltage ranges (Transient) up to 20% of Signal
Period
VII/O, USB 5V Tolerant Pins: 5.25V(3)
(USB0_DM, USB0_DP, USB0_ID, USB1_DM, USB1_DP)
VII/O, USB0 VBUS 5.50V(3)
VOI/O, 3.3V -0.5 V to DVDD + 0.3V
(Steady State)
Output voltage ranges VOI/O, 3.3V 20% of DVDD for up to
(Transient Overshoot/Undershoot) 20% of the signal period
Input or Output Voltages 0.3V above or below their respective power ±20mA
Clamp Current rails. Limit clamp current that flows through the I/O's internal diode
protection cells.
Commercial 0°C to 90°C
Industrial (D suffix ) -40°C to 90°C
Operating Junction Temperature ranges,
TJExtended (A suffix) -40°C to 105°C
Automotive (T suffix) -40°C to 125°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, PLL0_VSSA, OSCVSS, RTC_VSS
(3) Up to a max of 24 hours.
5.2 Handling Ratings
UNIT
Storage temperature (default) -55 to 150 °C
range, Tstg Human Body Model (HBM)(2) >2000 V
ESD Stress Voltage,
VESD(1) Charged Device Model (CDM)(3) >500 V
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM allows
safe manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary
precautions are taken. Pins listed as 1000V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. Pins listed as 250V may actually have higher performance.
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5.3 Recommended Operating Conditions
MIN NOM MAX UNIT
375 MHz versions 1.14 1.2 1.32
Supply voltage, Core
CVDD V
(CVDD, PLL0_VDDA) 456 MHz version 1.25 1.3 1.35
375 MHz versions 0.9 1.2 1.32
Supply Voltage, RTC Core
RTC_CVDD (1) V
Logic 456 MHz version 0.9 1.3 1.35
375 MHz versions 1.14 1.2 1.32
RVDD Supply Voltage, Internal RAM V
456 MHz version 1.25 1.3 1.35
Supply voltage, I/O, 1.8V 1.71 1.8 1.89 V
(USB0_VDDA18, USB1_VDDA18)
DVDD Supply voltage, I/O, 3.3V 3.0 3.3 3.45 V
(DVDD, USB0_VDDA33, USB1_VDDA33)
Supply ground
VSS 0 0 0 V
(VSS, PLL0_VSSA, OSCVSS(2), RTC_VSS(2))
High-level input voltage, I/O, 3.3V 2 V
VIH (3) High-level input voltage, RTC_XI 0.7*RTC_CVDD V
High-level input voltage, OSCIN 0.7*CVDD
Low-level input voltage, I/O, 3.3V 0.8 V
VIL (3) Low-level input voltage, RTC_XI 0.3*RTC_CVDD V
Low-level input voltage, OSCIN 0.3*CVDD
VHYS Input Hysteresis 160 mV
USB USB0_VBUS 4.75 5 5.25 V
Transition time, 10%-90%, All Inputs (unless otherwise specified
tt0.25P or 10(4) ns
in the electrical data sections)
Commercial 0 70 °C
Industrial (D suffix) -40 70 °C
Operating ambient
TAtemperature range Extended (A suffix) -40 85 °C
Automotive (T suffix) -40 105 °C
Commercial 0 375 / 456 MHz
DSP Industrial (D suffix) 0 456 MHz
FSYSCLK1,6 Operating Frequency Extended (A suffix) 0 375 MHz
(SYSCLK1) Automotive (T suffix) 0 375 MHz
(1) The RTC provides an option for isolating the RTC_CVDD from the CVDD to reduce current leakage when the RTC is powered
independently. If these power supplies are not isolated (CTRL.SPLITPOWER=0), RTC_CVDD must be equal to or greater than CVDD.
If these power supplies are isolated (CTRL.SPLITPOWER=1), RTC_CVDD may be lower than CVDD.
(2) When an external crystal is used, oscillator (OSC_VSS, RTC_VSS) ground must be kept separate from other grounds and connected
directly to the crystal load capacitor ground. These pins are shorted to VSS on the device itself and should not be connected to VSS on
the circuit board. If a crystal is not used and the clock input is driven directly, then the oscillator VSS may be connected to board ground.
(3) Unless specifically indicated, these I/O specifications do not apply to USB I/Os. USB0 I/Os adhere to USB2.0 specification. USB1 I/Os
adhere to USB1.1 specification.
(4) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
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5.4 Notes on Recommended Power-On Hours (POH)
The information in the section below is provided solely for your convenience and does not extend or
modify the warranty provided under TI’s standard terms and conditions for TI semiconductor products.
To avoid significant degradation, the device power-on hours (POH) must be limited to the following:
Table 5-1. Recommended Power-On Hours
Silicon Operating Junction Power-On Hours [POH]
Speed Grade Nominal CVDD Voltage (V)
Revision Temperature (Tj) (hours)
D 300 MHz 0 to 90 °C 1.2V 100,000
D 300 MHz 0 to 90 °C 1.2V 100,000
D 375 MHz 0 to 90 °C 1.2V 100,000
D 375 MHz -40 to 105 °C 1.2V 75,000(1)
D 375 MHz -40 to 125 °C 1.2V 20,000
D 456 MHz 0 to 90 °C 1.3V 100,000
D 456 MHz -40 to 90 °C 1.3V 100,000
(1) 100,000 POH can be achieved at this temperature condition if the device operation is limited to 345 MHz.
Note: Logic functions and parameter values are not assured out of the range specified in the recommended
operating conditions.
The above notations cannot be deemed a warranty or deemed to extend or modify the warranty under
TI’s standard terms and conditions for TI semiconductor products.
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5.5 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Case Temperature (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DVDD= 3.15V, IOH = -4 mA 2.4 V
VOH (1) High-level output voltage (3.3V I/O) DVDD= 3.15V, IOH = 100 μA 2.95 V
DVDD= 3.15V, IOL = 4mA 0.4 V
VOL (1) Low-level output voltage (3.3V I/O) DVDD= 3.15V, IOL = -100 μA 0.2 V
VI= VSS to DVDD without opposing ±35 μA
internal resistor
VI= VSS to DVDD with opposing -30 -200 μA
internal pullup resistor (3)
IIInput current
(2) ,(1) VI= VSS to DVDD with opposing 50 300 μA
internal pulldown resistor (3)
VI= VSS to USB1_VDDA33 - ±40 μA
USB1_DM and USB1_DP
IOH (1) High-level output current -4 mA
IOL (1) Low-level output current 4 mA
IOZ (4) I/O Off-state output current VO = VDD or VSS; Internal pull disabled ±35 μA
LVCMOS signals 3 pF
CIInput capacitance OSCIN and RTC_XI 2 pF
COOutput capacitance LVCMOS signals 3 pF
(1) These I/O specifications apply to regular 3.3V IOs and do not apply to USB0 or USB1 unless specifically indicated. USB0 I/Os adhere to
the USB 2.0 specification. USB1 I/Os adhere to the USB 1.1 specification.
(2) IIapplies to input-only pins and bi-directional pins. For input-only pins, IIindicates the input leakage current. For bi-directional pins, II
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(4) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
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Vref =VIL MAX(orVOL MAX)
Vref =VIH MIN(orVOH MIN)
Vref
TransmissionLine
4.0pF 1.85pF
Z0=50 Ω
(seenote)
Tester PinElectronics Data SheetTimingReferencePoint
Output
Under
Test
42 Ω3.5nH
DevicePin
(seenote)
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6 Peripheral Information and Electrical Specifications
6.1 Parameter Information
6.1.1 Parameter Information Device-Specific Information
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin and the input signals are driven between 0V and the appropriate IO supply rail for the signal.
Figure 6-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
6.1.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V. For 1.2 V I/O, Vref = 0.6 V.
Figure 6-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
Figure 6-3. Rise and Fall Transition Time Voltage Reference Levels
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6.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
6.3 Power Supplies
6.3.1 Power-on Sequence
The device should be powered-on in the following order:
1. RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all other
supplies being applied or powered-up at the same time as CVDD. If the RTC is not used, RTC_CVDD
should be connected to CVDD. RTC_CVDD should not be left unpowered while CVDD is powered.
2. Core logic supplies:
(a) CVDD core logic and RVDD supply
(b) Other 1.2V logic supplies (PLL0_VDDA).
Groups 2a) and 2b) may be powered up together or 2a) first followed by 2b).
3. All 1.8V IO supplies (USB0_VDDA18, USB1_VDDA18).
4. All digital IO and analog 3.3V PHY supplies (DVDD, USB0_VDDA33, USB1_VDDA33).
If both USB0 and USB1 are not used, USB0_VDDA33 and USB1_VDDA33 are not required and may
be left unconnected.
Group 3) and group 4) may be powered on in either order [3 then 4, or 4 then 3] but group 4) must be
powered-on after the core logic supplies.
There is no specific required voltage ramp rate for any of the supplies.
RESET must be maintained active until all power supplies have reached their nominal values.
6.3.2 Power-off Sequence
The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered
with the other supplies unpowered.
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6.4 Reset
6.4.1 Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are tri-stated with the exception of RESETOUT, which remains active
through the reset sequence, and GP7[14]. During reset, GP7[14] is configured as a reserved function, and
its behavior is not deterministic; the user should be aware that this pin will drive a level, and in fact may
toggle, during reset. RESETOUT is an output for use by other controllers in the system that indicates the
device is currently in reset.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
.TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
.RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET. For
maximum reliability, the device includes an internal pulldown on the TRST pin to ensure that TRST will
always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST. When using this type
of JTAG controller, assert TRST to intialize the device after powerup and externally drive TRST high
before attempting any emulation or boundary scan operations.
A summary of the effects of Power-On Reset is given below:
• All internal logic (including emulation logic and the PLL logic) is reset to its default state
• Internal memory is not maintained through a POR
• RESETOUT goes active
• All device pins go to a high-impedance state
• The RTC peripheral is not reset during a POR. A software sequence is required to reset the RTC.
CAUTION: A watchdog reset triggers a POR.
6.4.2 Warm Reset
A warm reset provides a limited reset to the device. Warm Reset is initiated by bringing only RESET low
(TRST is maintained high through a warm reset). Warm reset sets certain portions of the device to their
default state while leaving others unaltered. All pins are tri-stated with the exception of RESETOUT, which
remains active through the reset sequence, and GP7[14]. During reset, GP7[14] is configured as a
reserved function, and its behavior is not deterministic; the user should be aware that this pin will drive a
level, and in fact may toggle, during reset. RESETOUT is an output for use by other controllers in the
system that indicates the device is currently in reset.
During emulation, the emulator will maintain TRST high and hence only warm reset (not POR) is available
during emulation debug and development.
A summary of the effects of Warm Reset is given below:
• All internal logic (except for the emulation logic and the PLL logic) is reset to its default state
• Internal memory is maintained through a warm reset
• RESETOUT goes active
• All device pins go to a high-impedance state
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OSCIN
RESET
RESETOUT
BootPins Config
Power
Supplies
Ramping PowerSuppliesStable
ClockSourceStable
1
23
4
TRST
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• The RTC peripheral is not reset during a warm reset. A software sequence is required to reset the
RTC.
6.4.3 Reset Electrical Data Timings
Table 6-1 assumes testing over the recommended operating conditions.
Table 6-1. Reset Timing Requirements(1)(2)
No. MIN MAX UNIT
1 tw(RSTL) Pulse width, RESET/TRST low 100 ns
2 tsu(BPV-RSTH) Setup time, boot pins valid before RESET/TRST high 20 ns
3 th(RSTH-BPV) Hold time, boot pins valid after RESET/TRST high 20 ns
4 td(RSTH- RESET high to RESETOUT high; Warm reset 4096 cycles(3)
RESETOUTH) RESET high to RESETOUT high; Power-on Reset 6192
(1) RESETOUT is multiplexed with other pin functions. See the Terminal Functions table, Table 3-6 for details.
(2) For power-on reset (POR), the reset timings in this table refer to RESET and TRST together. For warm reset, the reset timings in this
table refer to RESET only (TRST is held high).
(3) OSCIN cycles.
Figure 6-4. Power-On Reset (RESET and TRST active) Timing
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OSCIN
TRST
RESET
RESETOUT
Boot Pins Config
Power Supplies Stable
1
23
4
Driven or Hi-Z
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Figure 6-5. Warm Reset (RESET active, TRST high) Timing
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C2
C1
X1
OSCOUT
OSCIN
OSCVSS
ClockInput
toPLL
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6.5 Crystal Oscillator or External Clock Input
The C6745/6747 device includes two choices to provide an external clock input, which is fed to the on-
chip PLL to generate high-frequency system clocks. These options are illustrated in Figure 6-6 and
Figure 6-7. For input clock frequencies between 12 and 20 MHz, a crystal with 80 ohm max ESR is
recommended. For input clock frequencies between 20 and 30 MHz, a crystal with 60 ohm max ESR is
recommended. Typical load capacitance values are 10-20 pF, where the load capacitance is the series
combination of C1 and C2.
The CLKMODE bit in the PLLCTL register must be 0 to use the on-chip oscillator. If CLKMODE is set to 1,
the internal oscillator is disabled.
•Figure 6-6 illustrates the option that uses on-chip 1.2V oscillator with external crystal circuit.
•Figure 6-7 illustrates the option that uses an external 1.2V clock input.
Figure 6-6. On-Chip 1.2V Oscillator
Table 6-2. Oscillator Timing Requirements
PARAMETER MIN MAX UNIT
fosc Oscillator frequency range (OSCIN/OSCOUT) 12 30 MHz
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OSCOUT
OSCIN
OSCVSS
Clock
Input
toPLL
NC
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Figure 6-7. External 1.2V Clock Source
Table 6-3. OSCIN Timing Requirements
PARAMETER MIN MAX UNIT
fOSCIN OSCIN frequency range (OSCIN) 12 50 MHz
tc(OSCIN) Cycle time, external clock driven on OSCIN 20 ns
tw(OSCINH) Pulse width high, external clock on OSCIN 0.4 tc(OSCIN) ns
tw(OSCINL) Pulse width low, external clock on OSCIN 0.4 tc(OSCIN) ns
tt(OSCIN) Transition time, OSCIN 0.25P or 10 (1) ns
tj(OSCIN) Period jitter, OSCIN 0.02P ns
(1) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
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0.1
µF
0.01
µF
50R
1.14V-1.32V
50RVSS
PLL0_VDDA
PLL0_VSSA
FerriteBead:MurataBLM31PG500SN1L orEquivalent
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6.6 Clock PLLs
The C6745/6747 has one PLL controller that provides clock to different parts of the system. PLL0 provides
clocks (though various dividers) to most of the components of the device.
The PLL controller provides the following:
• Glitch-Free Transitions (on changing clock settings)
• Domain Clocks Alignment
• Clock Gating
• PLL power down
The various clock outputs given by the controller are as follows:
• Domain Clocks: SYSCLK [1:n]
• Auxiliary Clock from reference clock source: AUXCLK
Various dividers that can be used are as follows:
• Post-PLL Divider: POSTDIV
• SYSCLK Divider: D1, ¼, Dn
Various other controls supported are as follows:
• PLL Multiplier Control: PLLM
• Software programmable PLL Bypass: PLLEN
6.6.1 PLL Device-Specific Information
The C6745/6747 DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The PLL requires some external filtering components to reduce power supply noise as shown in Figure 6-
8.
Figure 6-8. PLL External Filtering Components
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
OSCIN pin. The PLL outputs seven clocks that have programmable divider options. Figure 6-9 illustrates
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in Table 6-4 before enabling the DSP to run from the PLL by setting
PLLEN = 1.
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PLLDIV1 (/1) SYSCLK1
PLLDIV2 (/2) SYSCLK2
PLLDIV3 (/3) SYSCLK3
PLLDIV4 (/4) SYSCLK4
PLLDIV5 (/3) SYSCLK5
PLLDIV6 (/1) SYSCLK6
PLLDIV7 (/6) SYSCLK7
DIV4.5 1
0EMIFA
Internal
Clock
Source
CFGCHIP3[EMA_CLKSRC]
DIV4.5 EMIFB
Internal
Clock
Source
CFGCHIP3[EMB_CLKSRC]
1
0
Pre-Div
PLLM
PLLEN
AUXCLK
0
1
PLL Post-Div
CLKMODE
1
0
Square
Wave
Crystal
OSCIN
OBSCLK Pin
14h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
SYSCLK1
SYSCLK2
SYSCLK3
SYSCLK4
SYSCLK5
SYSCLK6
SYSCLK7
OCSEL[OCSRC]
OSCDIV
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Figure 6-9. PLL Topology
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2000 N
Max PLL Lock Time = m
where N = Pre-Divider Ratio
M = PLL Multiplier
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Table 6-4. Allowed PLL Operating Conditions
Default
No. PARAMETER MIN MAX UNIT
Value
PLLRST: Assertion time during
1 N/A 1000 N/A ns
initialization
Lock time: The time that the application
has to wait for the PLL to acquire locks OSCIN
2 N/A N/A
before setting PLLEN, after changing cycles
PREDIV, PLLM, or OSCIN
3 PREDIV /1 /1 /32
PLL input frequency 30 (if internal oscillator is used)
4 12 MHz
( PLLREF) 50 (if external clock source is used)
5 PLL multiplier values (PLLM) (1) x20 x4 x32
6 PLL output frequency. ( PLLOUT ) N/A 300 600 MHz
7 POSTDIV /1 /1 /32
(1) The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given
voltage operating point.
6.6.2 Device Clock Generation
PLL0 is controlled by PLL Controller 0. The PLLC0 manages the clock ratios, alignment, and gating for the
system clocks to the chip. The PLLC is responsible for controlling all modes of the PLL through software,
in terms of pre-division of the clock inputs, multiply factor within the PLL, and post-division for each of the
chip-level clocks from the PLL output. The PLLC also controls reset propagation through the chip, clock
alignment, and test points.
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6.6.3 PLL Controller 0 Registers
Table 6-5. PLL Controller 0 Registers
BYTE ACRONYM REGISTER DESCRIPTION
ADDRESS
0x01C1 1000 REVID Revision Identification Register
0x01C1 10E4 RSTYPE Reset Type Status Register
0x01C1 1100 PLLCTL PLL Control Register
0x01C1 1104 OCSEL OBSCLK Select Register
0x01C1 1110 PLLM PLL Multiplier Control Register
0x01C1 1114 PREDIV PLL Pre-Divider Control Register
0x01C1 1118 PLLDIV1 PLL Controller Divider 1 Register
0x01C1 111C PLLDIV2 PLL Controller Divider 2 Register
0x01C1 1120 PLLDIV3 PLL Controller Divider 3 Register
0x01C1 1124 OSCDIV Oscillator Divider 1 Register (OBSCLK)
0x01C1 1128 POSTDIV PLL Post-Divider Control Register
0x01C1 1138 PLLCMD PLL Controller Command Register
0x01C1 113C PLLSTAT PLL Controller Status Register
0x01C1 1140 ALNCTL PLL Controller Clock Align Control Register
0x01C1 1144 DCHANGE PLLDIV Ratio Change Status Register
0x01C1 1148 CKEN Clock Enable Control Register
0x01C1 114C CKSTAT Clock Status Register
0x01C1 1150 SYSTAT SYSCLK Status Register
0x01C1 1160 PLLDIV4 PLL Controller Divider 4 Register
0x01C1 1164 PLLDIV5 PLL Controller Divider 5 Register
0x01C1 1168 PLLDIV6 PLL Controller Divider 6 Register
0x01C1 116C PLLDIV7 PLL Controller Divider 7 Register
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6.7 Interrupts
The C6745/6747 devices have a large number of interrupts to service the needs of its many peripherals
and subsystems.
6.7.1 DSP Interrupts
The C674x DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 6-6. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts. Table 6-7
summarizes the C674x interrupt controller registers and memory locations.
Table 6-6. C6745/6747 DSP Interrupts
EVT# INTERRUPT NAME SOURCE
0 EVT0 C674x Int Ctl 0
1 EVT1 C674x Int Ctl 1
2 EVT2 C674x Int Ctl 2
3 EVT3 C674x Int Ctl 3
4 T64P0_TINT12 Timer64P0 - TINT12
5 SYSCFG_CHIPINT2 SYSCFG_CHIPSIG Register
6 PRU_EVTOUT0 PRU Interrupt
7 EHRPWM0 HiResTimer/PWM0 Interrupt
8 EDMA3_CC0_INT1 EDMA3 Channel Controller 0 Region 1 interrupt
9 EMU-DTDMA C674x-ECM
10 EHRPWM0TZ HiResTimer/PWM0 Trip Zone Interrupt
11 EMU-RTDXRX C674x-RTDX
12 EMU-RTDXTX C674x-RTDX
13 IDMAINT0 C674x-EMC
14 IDMAINT1 C674x-EMC
15 MMCSD_INT0 MMCSD MMC/SD Interrupt
16 MMCSD_INT1 MMCSD SDIO Interrupt
17 PRU_EVTOUT1 PRU Interrupt
18 EHRPWM1 HiResTimer/PWM1 Interrupt
19 USB0_INT USB0 Interrupt
20 USB1_HCINT USB1 OHCI Host Controller Interrupt
21 USB1_RWAKEUP USB1 Remote Wakeup Interrupt
22 PRU_EVTOUT2 PRU Interrupt
23 EHRPWM1TZ HiResTimer/PWM1 Trip Zone Interrupt
24 EHRPWM2 HiResTimer/PWM2 Interrupt
25 EHRPWM2TZ HiResTimer/PWM2 Trip Zone Interrupt
26 EMAC_C0RXTHRESH EMAC - Core 0 Receive Threshold Interrupt
27 EMAC_C0RX EMAC - Core 0 Receive Interrupt
28 EMAC_C0TX EMAC - Core 0 Transmit Interrupt
29 EMAC_C0MISC EMAC - Core 0 Miscellaneous Interrupt
30 EMAC_C1RXTHRESH EMAC - Core 1 Receive Threshold Interrupt
31 EMAC_C1RX EMAC - Core 1 Receive Interrupt
32 EMAC_C1TX EMAC - Core 1 Transmit Interrupt
33 EMAC_C1MISC EMAC - Core 1 Miscellaneous Interrupt
34 UHPI_DSPINT UHPI DSP Interrupt
35 PRU_EVTOUT3 PRU Interrupt
36 IIC0_INT I2C0
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Table 6-6. C6745/6747 DSP Interrupts (continued)
EVT# INTERRUPT NAME SOURCE
37 SP0_INT SPI0
38 UART0_INT UART0
39 PRU_EVTOUT5 PRU Interrupt
40 T64P1_TINT12 Timer64P1 Interrupt 12
41 GPIO_B1INT GPIO Bank 1 Interrupt
42 IIC1_INT I2C1
43 SPI1_INT SPI1
44 PRU_EVTOUT6 PRU Interrupt
45 ECAP0 ECAP0
46 UART_INT1 UART1
47 ECAP1 ECAP1
48 T64P1_TINT34 Timer64P1 Interrupt 34
49 GPIO_B2INT GPIO Bank 2 Interrupt
50 PRU_EVTOUT7 PRU Interrupt
51 ECAP2 ECAP2
52 GPIO_B3INT GPIO Bank 3 Interrupt
53 EQEP1 EQEP1
54 GPIO_B4INT GPIO Bank 4 Interrupt
55 EMIFA_INT EMIFA
56 EDMA3_CC0_ERRINT EDMA3 Channel Controller 0
57 EDMA3_TC0_ERRINT EDMA3 Transfer Controller 0
58 EDMA3_TC1_ERRINT EDMA3 Transfer Controller 1
59 GPIO_B5INT GPIO Bank 5 Interrupt
60 EMIFB_INT EMIFB Memory Error Interrupt
61 MCASP_INT McASP0,1,2 Combined RX/TX Interrupts
62 GPIO_B6INT GPIO Bank 6 Interrupt
63 RTC_IRQS RTC Combined
64 T64P0_TINT34 Timer64P0 Interrupt 34
65 GPIO_B0INT GPIO Bank 0 Interrupt
66 PRU_EVTOUT4 PRU Interrupt
67 SYSCFG_CHIPINT3 SYSCFG_CHIPSIG Register
68 EQEP0 EQEP0
69 UART2_INT UART2
70 PSC0_ALLINT PSC0
71 PSC1_ALLINT PSC1
72 GPIO_B7INT GPIO Bank 7 Interrupt
73 LCDC_INT LCD Controller
74 MPU_BOOTCFG_ERR Shared MPU and SYSCFG Address/Protection Error Interrupt
75 - 77 - Reserved
78 T64P0_CMPINT0 Timer64P0 - Compare 0
79 T64P0_CMPINT1 Timer64P0 - Compare 1
80 T64P0_CMPINT2 Timer64P0 - Compare 2
81 T64P0_CMPINT3 Timer64P0 - Compare 3
82 T64P0_CMPINT4 Timer64P0 - Compare 4
83 T64P0_CMPINT5 Timer64P0 - Compare 5
84 T64P0_CMPINT6 Timer64P0 - Compare 6
85 T64P0_CMPINT7 Timer64P0 - Compare 7
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Table 6-6. C6745/6747 DSP Interrupts (continued)
EVT# INTERRUPT NAME SOURCE
86 T64P1_CMPINT0 Timer64P1 - Compare 0
87 T64P1_CMPINT1 Timer64P1 - Compare 1
88 T64P1_CMPINT2 Timer64P1 - Compare 2
89 T64P1_CMPINT3 Timer64P1 - Compare 3
90 T64P1_CMPINT4 Timer64P1 - Compare 4
91 T64P1_CMPINT5 Timer64P1 - Compare 5
92 T64P1_CMPINT6 Timer64P1 - Compare 6
93 T64P1_CMPINT7 Timer64P1 - Compare 7
94 - 95 - Reserved
96 INTERR C674x-Int Ctl
97 EMC_IDMAERR C674x-EMC
98 - 112 - Reserved
113 PMC_ED C674x-PMC
114 - 115 - Reserved
116 UMC_ED1 C674x-UMC
117 UMC_ED2 C674x-UMC
118 PDC_INT C674x-PDC
119 SYS_CMPA C674x-SYS
120 PMC_CMPA C674x-PMC
121 PMC_CMPA C674x-PMC
122 DMC_CMPA C674x-DMC
123 DMC_CMPA C674x-DMC
124 UMC_CMPA C674x-UMC
125 UMC_CMPA C674x-UMC
126 EMC_CMPA C674x-EMC
127 EMC_BUSERR C674x-EMC
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Table 6-7. C674x DSP Interrupt Controller Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x0180 0000 EVTFLAG0 Event flag register 0
0x0180 0004 EVTFLAG1 Event flag register 1
0x0180 0008 EVTFLAG2 Event flag register 2
0x0180 000C EVTFLAG3 Event flag register 3
0x0180 0020 EVTSET0 Event set register 0
0x0180 0024 EVTSET1 Event set register 1
0x0180 0028 EVTSET2 Event set register 2
0x0180 002C EVTSET3 Event set register 3
0x0180 0040 EVTCLR0 Event clear register 0
0x0180 0044 EVTCLR1 Event clear register 1
0x0180 0048 EVTCLR2 Event clear register 2
0x0180 004C EVTCLR3 Event clear register 3
0x0180 0080 EVTMASK0 Event mask register 0
0x0180 0084 EVTMASK1 Event mask register 1
0x0180 0088 EVTMASK2 Event mask register 2
0x0180 008C EVTMASK3 Event mask register 3
0x0180 00A0 MEVTFLAG0 Masked event flag register 0
0x0180 00A4 MEVTFLAG1 Masked event flag register 1
0x0180 00A8 MEVTFLAG2 Masked event flag register 2
0x0180 00AC MEVTFLAG3 Masked event flag register 3
0x0180 00C0 EXPMASK0 Exception mask register 0
0x0180 00C4 EXPMASK1 Exception mask register 1
0x0180 00C8 EXPMASK2 Exception mask register 2
0x0180 00CC EXPMASK3 Exception mask register 3
0x0180 00E0 MEXPFLAG0 Masked exception flag register 0
0x0180 00E4 MEXPFLAG1 Masked exception flag register 1
0x0180 00E8 MEXPFLAG2 Masked exception flag register 2
0x0180 00EC MEXPFLAG3 Masked exception flag register 3
0x0180 0104 INTMUX1 Interrupt mux register 1
0x0180 0108 INTMUX2 Interrupt mux register 2
0x0180 010C INTMUX3 Interrupt mux register 3
0x0180 0140 - 0x0180 0144 - Reserved
0x0180 0180 INTXSTAT Interrupt exception status
0x0180 0184 INTXCLR Interrupt exception clear
0x0180 0188 INTDMASK Dropped interrupt mask register
0x0180 01C0 EVTASRT Event assert register
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6.8 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]).
The C6745/6747 GPIO peripheral supports the following:
• Up to 128 Pins on ZKB and up to 109 Pins on PTP package configurable as GPIO
• External Interrupt and DMA request Capability
– Every GPIO pin may be configured to generate an interrupt request on detection of rising and/or
falling edges on the pin.
– The interrupt requests within each bank are combined (logical or) to create eight unique bank level
interrupt requests.
– The bank level interrupt service routine may poll the INTSTATx register for its bank to determine
which pin(s) have triggered the interrupt.
– GPIO Banks 0, 1, 2, 3, 4, 5, 6, and 7 Interrupts assigned to DSP Events 65, 41, 49, 52, 54, 59, 62
and 72 respectively
– Additionally, GPIO Banks 0, 1, 2, 3, 4, and 5 Interrupts assigned to EDMA events 6, 7, 22, 23, 28,
and 29 respectively.
• Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
• Separate Input/Output registers
• Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
The memory map for the GPIO registers is shown in Table 6-8. See the TMS320C6745/C6747 DSP
Peripherals Overview Reference Guide. (SPRUFK9) for more details.
6.8.1 GPIO Register Description(s)
Table 6-8. GPIO Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 6000 REV Peripheral Revision Register
0x01E2 6004 - Reserved
0x01E2 6008 BINTEN GPIO Interrupt Per-Bank Enable Register
GPIO BANKS 0 AND 1
0x01E2 6010 DIR01 GPIO Banks 0 and 1 Direction Register
0x01E2 6014 OUT_DATA01 GPIO Banks 0 and 1 Output Data Register
0x01E2 6018 SET_DATA01 GPIO Banks 0 and 1 Set Data Register
0x01E2 601C CLR_DATA01 GPIO Banks 0 and 1 Clear Data Register
0x01E2 6020 IN_DATA01 GPIO Banks 0 and 1 Input Data Register
0x01E2 6024 SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register
0x01E2 6028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register
0x01E2 602C SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register
0x01E2 6030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register
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Table 6-8. GPIO Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 6034 INTSTAT01 GPIO Banks 0 and 1 Interrupt Status Register
GPIO BANKS 2 AND 3
0x01E2 6038 DIR23 GPIO Banks 2 and 3 Direction Register
0x01E2 603C OUT_DATA23 GPIO Banks 2 and 3 Output Data Register
0x01E2 6040 SET_DATA23 GPIO Banks 2 and 3 Set Data Register
0x01E2 6044 CLR_DATA23 GPIO Banks 2 and 3 Clear Data Register
0x01E2 6048 IN_DATA23 GPIO Banks 2 and 3 Input Data Register
0x01E2 604C SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register
0x01E2 6050 CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register
0x01E2 6054 SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register
0x01E2 6058 CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register
0x01E2 605C INTSTAT23 GPIO Banks 2 and 3 Interrupt Status Register
GPIO BANKS 4 AND 5
0x01E2 6060 DIR45 GPIO Banks 4 and 5 Direction Register
0x01E2 6064 OUT_DATA45 GPIO Banks 4 and 5 Output Data Register
0x01E2 6068 SET_DATA45 GPIO Banks 4 and 5 Set Data Register
0x01E2 606C CLR_DATA45 GPIO Banks 4 and 5 Clear Data Register
0x01E2 6070 IN_DATA45 GPIO Banks 4 and 5 Input Data Register
0x01E2 6074 SET_RIS_TRIG45 GPIO Banks 4 and 5 Set Rising Edge Interrupt Register
0x01E2 6078 CLR_RIS_TRIG45 GPIO Banks 4 and 5 Clear Rising Edge Interrupt Register
0x01E2 607C SET_FAL_TRIG45 GPIO Banks 4 and 5 Set Falling Edge Interrupt Register
0x01E2 6080 CLR_FAL_TRIG45 GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register
0x01E2 6084 INTSTAT45 GPIO Banks 4 and 5 Interrupt Status Register
GPIO BANKS 6 AND 7
0x01E2 6088 DIR67 GPIO Banks 6 and 7 Direction Register
0x01E2 608C OUT_DATA67 GPIO Banks 6 and 7 Output Data Register
0x01E2 6090 SET_DATA67 GPIO Banks 6 and 7 Set Data Register
0x01E2 6094 CLR_DATA67 GPIO Banks 6 and 7 Clear Data Register
0x01E2 6098 IN_DATA67 GPIO Banks 6 and 7 Input Data Register
0x01E2 609C SET_RIS_TRIG67 GPIO Banks 6 and 7 Set Rising Edge Interrupt Register
0x01E2 60A0 CLR_RIS_TRIG67 GPIO Banks 6 and 7 Clear Rising Edge Interrupt Register
0x01E2 60A4 SET_FAL_TRIG67 GPIO Banks 6 and 7 Set Falling Edge Interrupt Register
0x01E2 60A8 CLR_FAL_TRIG67 GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
0x01E2 60AC INTSTAT67 GPIO Banks 6 and 7 Interrupt Status Register
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2
1
GP [ ]asinputn m
GP [ ]asinputn m
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6.8.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-9. Timing Requirements for GPIO Inputs(1) (see Figure 6-10)
No. PARAMETER MIN MAX UNIT
1 tw(GPIH) Pulse duration, GPn[m] as input high 2C(1) (2) ns
2 tw(GPIL) Pulse duration, GPn[m] as input low 2C(1) (2) ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have C6745/6747
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow C6745/6747
enough time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
Table 6-10. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-10)
No. PARAMETER MIN MAX UNIT
3 tw(GPOH) Pulse duration, GPn[m] as output high 2C(1) (2) ns
4 tw(GPOL) Pulse duration, GPn[m] as output low 2C(1) (2) ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C=SYSCLK4 period in ns.
Figure 6-10. GPIO Port Timing
6.8.3 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-11. Timing Requirements for External Interrupts(1) (see Figure 6-11)
No. PARAMETER MIN MAX UNIT
1 tw(ILOW) Width of the external interrupt pulse low 2C(1) (2) ns
2 tw(IHIGH) Width of the external interrupt pulse high 2C (1) (2) ns
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have C6745/6747 recognize
the GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow C6745/6747 enough
time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
Figure 6-11. GPIO External Interrupt Timing
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6.9 EDMA
Table 6-12 is the list of EDMA3 Channel Contoller Registers and Table 6-13 is the list of EDMA3 Transfer
Controller registers.
Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01C0 0000 PID Peripheral Identification Register
0x01C0 0004 CCCFG EDMA3CC Configuration Register
GLOBAL REGISTERS
0x01C0 0200 QCHMAP0 QDMA Channel 0 Mapping Register
0x01C0 0204 QCHMAP1 QDMA Channel 1 Mapping Register
0x01C0 0208 QCHMAP2 QDMA Channel 2 Mapping Register
0x01C0 020C QCHMAP3 QDMA Channel 3 Mapping Register
0x01C0 0210 QCHMAP4 QDMA Channel 4 Mapping Register
0x01C0 0214 QCHMAP5 QDMA Channel 5 Mapping Register
0x01C0 0218 QCHMAP6 QDMA Channel 6 Mapping Register
0x01C0 021C QCHMAP7 QDMA Channel 7 Mapping Register
0x01C0 0240 DMAQNUM0 DMA Channel Queue Number Register 0
0x01C0 0244 DMAQNUM1 DMA Channel Queue Number Register 1
0x01C0 0248 DMAQNUM2 DMA Channel Queue Number Register 2
0x01C0 024C DMAQNUM3 DMA Channel Queue Number Register 3
0x01C0 0260 QDMAQNUM QDMA Channel Queue Number Register
0x01C0 0284 QUEPRI Queue Priority Register(1)
0x01C0 0300 EMR Event Missed Register
0x01C0 0308 EMCR Event Missed Clear Register
0x01C0 0310 QEMR QDMA Event Missed Register
0x01C0 0314 QEMCR QDMA Event Missed Clear Register
0x01C0 0318 CCERR EDMA3CC Error Register
0x01C0 031C CCERRCLR EDMA3CC Error Clear Register
0x01C0 0320 EEVAL Error Evaluate Register
0x01C0 0340 DRAE0 DMA Region Access Enable Register for Region 0
0x01C0 0348 DRAE1 DMA Region Access Enable Register for Region 1
0x01C0 0350 DRAE2 DMA Region Access Enable Register for Region 2
0x01C0 0358 DRAE3 DMA Region Access Enable Register for Region 3
0x01C0 0380 QRAE0 QDMA Region Access Enable Register for Region 0
0x01C0 0384 QRAE1 QDMA Region Access Enable Register for Region 1
0x01C0 0388 QRAE2 QDMA Region Access Enable Register for Region 2
0x01C0 038C QRAE3 QDMA Region Access Enable Register for Region 3
0x01C0 0400 - 0x01C0 043C Q0E0-Q0E15 Event Queue Entry Registers Q0E0-Q0E15
0x01C0 0440 - 0x01C0 047C Q1E0-Q1E15 Event Queue Entry Registers Q1E0-Q1E15
0x01C0 0600 QSTAT0 Queue 0 Status Register
0x01C0 0604 QSTAT1 Queue 1 Status Register
0x01C0 0620 QWMTHRA Queue Watermark Threshold A Register
0x01C0 0640 CCSTAT EDMA3CC Status Register
GLOBAL CHANNEL REGISTERS
0x01C0 1000 ER Event Register
0x01C0 1008 ECR Event Clear Register
(1) On previous architectures, the EDMA3TC priority was controlled by the queue priority register (QUEPRI) in the EDMA3CC memory-
map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System
Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority.
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Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01C0 1010 ESR Event Set Register
0x01C0 1018 CER Chained Event Register
0x01C0 1020 EER Event Enable Register
0x01C0 1028 EECR Event Enable Clear Register
0x01C0 1030 EESR Event Enable Set Register
0x01C0 1038 SER Secondary Event Register
0x01C0 1040 SECR Secondary Event Clear Register
0x01C0 1050 IER Interrupt Enable Register
0x01C0 1058 IECR Interrupt Enable Clear Register
0x01C0 1060 IESR Interrupt Enable Set Register
0x01C0 1068 IPR Interrupt Pending Register
0x01C0 1070 ICR Interrupt Clear Register
0x01C0 1078 IEVAL Interrupt Evaluate Register
0x01C0 1080 QER QDMA Event Register
0x01C0 1084 QEER QDMA Event Enable Register
0x01C0 1088 QEECR QDMA Event Enable Clear Register
0x01C0 108C QEESR QDMA Event Enable Set Register
0x01C0 1090 QSER QDMA Secondary Event Register
0x01C0 1094 QSECR QDMA Secondary Event Clear Register
SHADOW REGION 0 CHANNEL REGISTERS
0x01C0 2000 ER Event Register
0x01C0 2008 ECR Event Clear Register
0x01C0 2010 ESR Event Set Register
0x01C0 2018 CER Chained Event Register
0x01C0 2020 EER Event Enable Register
0x01C0 2028 EECR Event Enable Clear Register
0x01C0 2030 EESR Event Enable Set Register
0x01C0 2038 SER Secondary Event Register
0x01C0 2040 SECR Secondary Event Clear Register
0x01C0 2050 IER Interrupt Enable Register
0x01C0 2058 IECR Interrupt Enable Clear Register
0x01C0 2060 IESR Interrupt Enable Set Register
0x01C0 2068 IPR Interrupt Pending Register
0x01C0 2070 ICR Interrupt Clear Register
0x01C0 2078 IEVAL Interrupt Evaluate Register
0x01C0 2080 QER QDMA Event Register
0x01C0 2084 QEER QDMA Event Enable Register
0x01C0 2088 QEECR QDMA Event Enable Clear Register
0x01C0 208C QEESR QDMA Event Enable Set Register
0x01C0 2090 QSER QDMA Secondary Event Register
0x01C0 2094 QSECR QDMA Secondary Event Clear Register
SHADOW REGION 1 CHANNEL REGISTERS
0x01C0 2200 ER Event Register
0x01C0 2208 ECR Event Clear Register
0x01C0 2210 ESR Event Set Register
0x01C0 2218 CER Chained Event Register
0x01C0 2220 EER Event Enable Register
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Table 6-12. EDMA3 Channel Controller (EDMA3CC) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01C0 2228 EECR Event Enable Clear Register
0x01C0 2230 EESR Event Enable Set Register
0x01C0 2238 SER Secondary Event Register
0x01C0 2240 SECR Secondary Event Clear Register
0x01C0 2250 IER Interrupt Enable Register
0x01C0 2258 IECR Interrupt Enable Clear Register
0x01C0 2260 IESR Interrupt Enable Set Register
0x01C0 2268 IPR Interrupt Pending Register
0x01C0 2270 ICR Interrupt Clear Register
0x01C0 2278 IEVAL Interrupt Evaluate Register
0x01C0 2280 QER QDMA Event Register
0x01C0 2284 QEER QDMA Event Enable Register
0x01C0 2288 QEECR QDMA Event Enable Clear Register
0x01C0 228C QEESR QDMA Event Enable Set Register
0x01C0 2290 QSER QDMA Secondary Event Register
0x01C0 2294 QSECR QDMA Secondary Event Clear Register
0x01C0 4000 - 0x01C0 4FFF — Parameter RAM (PaRAM)
Table 6-13. EDMA3 Transfer Controller (EDMA3TC) Registers
Transfer Controller 0 Transfer Controller 1 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS
0x01C0 8000 0x01C0 8400 PID Peripheral Identification Register
0x01C0 8004 0x01C0 8404 TCCFG EDMA3TC Configuration Register
0x01C0 8100 0x01C0 8500 TCSTAT EDMA3TC Channel Status Register
0x01C0 8120 0x01C0 8520 ERRSTAT Error Status Register
0x01C0 8124 0x01C0 8524 ERREN Error Enable Register
0x01C0 8128 0x01C0 8528 ERRCLR Error Clear Register
0x01C0 812C 0x01C0 852C ERRDET Error Details Register
0x01C0 8130 0x01C0 8530 ERRCMD Error Interrupt Command Register
0x01C0 8140 0x01C0 8540 RDRATE Read Command Rate Register
0x01C0 8240 0x01C0 8640 SAOPT Source Active Options Register
0x01C0 8244 0x01C0 8644 SASRC Source Active Source Address Register
0x01C0 8248 0x01C0 8648 SACNT Source Active Count Register
0x01C0 824C 0x01C0 864C SADST Source Active Destination Address Register
0x01C0 8250 0x01C0 8650 SABIDX Source Active B-Index Register
0x01C0 8254 0x01C0 8654 SAMPPRXY Source Active Memory Protection Proxy Register
0x01C0 8258 0x01C0 8658 SACNTRLD Source Active Count Reload Register
0x01C0 825C 0x01C0 865C SASRCBREF Source Active Source Address B-Reference Register
0x01C0 8260 0x01C0 8660 SADSTBREF Source Active Destination Address B-Reference Register
0x01C0 8280 0x01C0 8680 DFCNTRLD Destination FIFO Set Count Reload Register
0x01C0 8284 0x01C0 8684 DFSRCBREF Destination FIFO Set Source Address B-Reference Register
0x01C0 8288 0x01C0 8688 DFDSTBREF Destination FIFO Set Destination Address B-Reference Register
0x01C0 8300 0x01C0 8700 DFOPT0 Destination FIFO Options Register 0
0x01C0 8304 0x01C0 8704 DFSRC0 Destination FIFO Source Address Register 0
0x01C0 8308 0x01C0 8708 DFCNT0 Destination FIFO Count Register 0
0x01C0 830C 0x01C0 870C DFDST0 Destination FIFO Destination Address Register 0
0x01C0 8310 0x01C0 8710 DFBIDX0 Destination FIFO B-Index Register 0
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Table 6-13. EDMA3 Transfer Controller (EDMA3TC) Registers (continued)
Transfer Controller 0 Transfer Controller 1 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS
0x01C0 8314 0x01C0 8714 DFMPPRXY0 Destination FIFO Memory Protection Proxy Register 0
0x01C0 8340 0x01C0 8740 DFOPT1 Destination FIFO Options Register 1
0x01C0 8344 0x01C0 8744 DFSRC1 Destination FIFO Source Address Register 1
0x01C0 8348 0x01C0 8748 DFCNT1 Destination FIFO Count Register 1
0x01C0 834C 0x01C0 874C DFDST1 Destination FIFO Destination Address Register 1
0x01C0 8350 0x01C0 8750 DFBIDX1 Destination FIFO B-Index Register 1
0x01C0 8354 0x01C0 8754 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1
0x01C0 8380 0x01C0 8780 DFOPT2 Destination FIFO Options Register 2
0x01C0 8384 0x01C0 8784 DFSRC2 Destination FIFO Source Address Register 2
0x01C0 8388 0x01C0 8788 DFCNT2 Destination FIFO Count Register 2
0x01C0 838C 0x01C0 878C DFDST2 Destination FIFO Destination Address Register 2
0x01C0 8390 0x01C0 8790 DFBIDX2 Destination FIFO B-Index Register 2
0x01C0 8394 0x01C0 8794 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2
0x01C0 83C0 0x01C0 87C0 DFOPT3 Destination FIFO Options Register 3
0x01C0 83C4 0x01C0 87C4 DFSRC3 Destination FIFO Source Address Register 3
0x01C0 83C8 0x01C0 87C8 DFCNT3 Destination FIFO Count Register 3
0x01C0 83CC 0x01C0 87CC DFDST3 Destination FIFO Destination Address Register 3
0x01C0 83D0 0x01C0 87D0 DFBIDX3 Destination FIFO B-Index Register 3
0x01C0 83D4 0x01C0 87D4 DFMPPRXY3 Destination FIFO Memory Protection Proxy Register 3
Table 6-14 shows an abbreviation of the set of registers which make up the parameter set for each of 128
EDMA events. Each of the parameter register sets consist of 8 32-bit word entries. Table 6-15 shows the
parameter set entry registers with relative memory address locations within each of the parameter sets.
Table 6-14. EDMA Parameter Set RAM
BYTE ADDRESS RANGE DESCRIPTION
0x01C0 4000 - 0x01C0 401F Parameters Set 0 (8 32-bit words)
0x01C0 4020 - 0x01C0 403F Parameters Set 1 (8 32-bit words)
0x01C0 4040 - 0x01cC0 405F Parameters Set 2 (8 32-bit words)
0x01C0 4060 - 0x01C0 407F Parameters Set 3 (8 32-bit words)
0x01C0 4080 - 0x01C0 409F Parameters Set 4 (8 32-bit words)
0x01C0 40A0 - 0x01C0 40BF Parameters Set 5 (8 32-bit words)
... ...
0x01C0 4FC0 - 0x01C0 4FDF Parameters Set 126 (8 32-bit words)
0x01C0 4FE0 - 0x01C0 4FFF Parameters Set 127 (8 32-bit words)
Table 6-15. Parameter Set Entries
BYTE OFFSET ADDRESS ACRONYM PARAMETER ENTRY
WITHIN THE PARAMETER SET
0x0000 OPT Option
0x0004 SRC Source Address
0x0008 A_B_CNT A Count, B Count
0x000C DST Destination Address
0x0010 SRC_DST_BIDX Source B Index, Destination B Index
0x0014 LINK_BCNTRLD Link Address, B Count Reload
0x0018 SRC_DST_CIDX Source C Index, Destination C Index
0x001C CCNT C Count
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Table 6-16. EDMA Events
Event Event Name / Source Event Event Name / Source
0 McASP0 Receive 16 MMCSD Receive
1 McASP0 Transmit 17 MMCSD Transmit
2 McASP1 Receive 18 SPI1 Receive
3 McASP1 Transmit 19 SPI1 Transmit
4 McASP2 Receive 20 PRU_EVENTOUT6
5 McASP2 Transmit 21 PRU_EVENTOUT7
6 GPIO Bank 0 Interrupt 22 GPIO Bank 2 Interrupt
7 GPIO Bank 1 Interrupt 23 GPIO Bank 3 Interrupt
8 UART0 Receive 24 I2C0 Receive
9 UART0 Transmit 25 I2C0 Transmit
10 Timer64P0 Event Out 12 26 I2C1 Receive
11 Timer64P0 Event Out 34 27 I2C1 Transmit
12 UART1 Receive 28 GPIO Bank 4 Interrupt
13 UART1 Transmit 29 GPIO Bank 5 Interrupt
14 SPI0 Receive 30 UART2 Receive
15 SPI0 Transmit 31 UART2 Transmit
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6.10 External Memory Interface A (EMIFA)
EMIFA is one of two external memory interfaces supported on the C6745/6747. It is primarily intended to
support asynchronous memory types, such as NAND and NOR flash and Asynchronous SRAM. However
on C6745/6747 EMIFA also provides a secondary interface to SDRAM.
6.10.1 EMIFA Asynchronous Memory Support
EMIFA supports asynchronous:
• SRAM memories
• NAND Flash memories
• NOR Flash memories
The EMIFA data bus width is up to 16-bits on the ZKB packageand 8 bits on the PTP package. Both
devices support up to fifteen address lines and an external wait/interrupt input. Up to four asynchronous
chip selects are supported by EMIFA (EMA_CS[5:2]) . All four chip selects are available on the ZKB
package. Two of the four are available on the PTP package (EMA_CS[3:2]).
Each chip select has the following individually programmable attributes:
• Data Bus Width
• Read cycle timings: setup, hold, strobe
• Write cycle timings: setup, hold, strobe
• Bus turn around time
• Extended Wait Option With Programmable Timeout
• Select Strobe Option
• NAND flash controller supports 1-bit and 4-bit ECC calculation on blocks of 512 bytes.
6.10.2 EMIFA Synchronous DRAM Memory Support
The C6745/6747 ZKB package supports 16-bit SDRAM in addition to the asynchronous memories listed in
Section 6.10.1. It has a single SDRAM chip select (EMA_CS[0]). SDRAM configurations that are
supported are:
• One, Two, and Four Bank SDRAM devices
• Devices with Eight, Nine, Ten, and Eleven Column Address
• CAS Latency of two or three clock cycles
• Sixteen Bit Data Bus Width
• 3.3V LVCMOS Interface
Additionally, the SDRAM interface of EMIFA supports placing the SDRAM in Self Refresh and Powerdown
Modes. Self Refresh mode allows the SDRAM to be put into a low power state while still retaining memory
contents; since the SDRAM will continue to refresh itself even without clocks from the DSP. Powerdown
mode achieves even lower power, except the DSP must periodically wake the SDRAM up and issue
refreshes if data retention is required.
Finally, note that the EMIFA does not support Mobile SDRAM devices. Table 6-17 below shows the
supported SDRAM configurations for EMIFA.
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Table 6-17. EMIFA Supported SDRAM Configurations(1)
SDRAM
Memory Memory
Number of EMIFB Data Total Memory Total Memory
Data Bus Rows Columns Banks Density
Memories Bus Size (Mbits) (Mbytes)
Width (Mbits)
(bits)
1 16 13 8 1 32 4 32
1 16 13 8 2 64 8 64
1 16 13 8 4 128 16 128
1 16 13 9 1 64 8 64
1 16 13 9 2 128 16 128
1 16 13 9 4 256 32 256
16 1 16 13 10 1 128 16 128
1 16 13 10 2 256 32 256
1 16 13 10 4 512 64 512
1 16 13 11 1 256 32 256
1 16 13 11 2 512 64 512
1 16 13 11 4 1024 128 1024
2 16 13 8 1 32 4 16
2 16 13 8 2 64 8 32
2 16 13 8 4 128 16 64
2 16 13 9 1 64 8 32
2 16 13 9 2 128 16 64
2 16 13 9 4 256 32 128
82 16 13 10 1 128 16 64
2 16 13 10 2 256 32 128
2 16 13 10 4 512 64 256
2 16 13 11 1 256 32 128
2 16 13 11 2 512 64 256
2 16 13 11 4 1024 128 512
(1) The shaded cells indicate configurations that are possible on the EMIFA interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
6.10.3 EMIFA SDRAM Loading Limitations
EMIFA supports SDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads.
Additional loads will limit the SDRAM operation to lower speeds and the maximum speed should be
confirmed by board simulation using IBIS models.
6.10.4 EMIFA Connection Examples
Figure 6-12 illustrates an example of how SDRAM, NOR, and NAND flash devices might be connected to
EMIFA of a C6745/6747 device simultaneously. The SDRAM chip select must be EMA_CS[0]. Note that
the NOR flash is connected to EMA_CS[2] and the NAND flash is connected to EMA_CS[3] in this
example. Note that any type of asynchronous memory may be connected to EMA_CS[5:2].
The on-chip bootloader makes some assumptions on which chip select the contains the boot image, and
this depends on the boot mode. For NOR boot mode; the on-chip bootloader requires that the image be
stored in NOR flash on EMA_CS[2]. For NAND boot mode, the bootloader requires that the boot image is
stored in NAND flash on EMA_CS[3]. It is always possible to have the image span multiple chip selects,
but this must be supported by second stage boot code stored in the external flash.
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EMA_CLK
EMA_BA[1:0]
EMA_CS[0]
EMA_CAS
EMA_RAS
EMA_WE
CLK
CE
WE
EMIFA
SDRAM
2Mx16x4
Bank
EMA_SDCKE
CAS
RAS
CKE
BA[1:0]
LDQM
UDQM
DQ[15:0]
A[11:0]EMA_A[12:0]
EMA_WE_DQM[0]
EMA_WE_DQM[1]
EMA_D[15:0]
EMA_CS[2]
EMA_CS[3]
EMA_WAIT
EMA_OE
GPIO
(6Pins)
RESET
A[0]
A[12:1]
DQ[15:0]
CE
WE
OE
RESET
A[18:13]
RY/ YB
NOR
FLASH
512Kx16
ALE
CLE
DQ[15:0]
CE
WE
RE
RB
NAND
FLASH
1Gbx16
EMA_BA[1]
EMA_A[1]
EMA_A[2]
...
DVDD
RESET
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A likely use case with more than one EMIFA chip select used for NAND flash is illustrated in Figure 6-13.
This figure shows how two multiplane NAND flash devices with two chip selects each would connect to the
EMIFA. In this case if NAND is the boot memory, then the boot image needs to be stored in the NAND
area selected by EMA_CS[3]. Part of the application image could spill over into the NAND regions
selected by other EMIFA chip selects; but would rely on the code stored in the EMA_CS[3] area to
bootload it. Note that this example could also apply to the C6745 device; except only one multiplane
NAND could be supported with only EMA_CS[3:2] available.
Figure 6-12. C6745/6747 Connection Diagram: SDRAM, NOR, NAND
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EMA_A[1]
EMA_A[2]
EMA_D[7:0]
EMA_CS[2]
EMA_CS[3]
EMA_WE
EMA_OE
ALE
CLE
DQ[7:0]
CE1
CE2
WE
RE
R/ 1B
R/ 2B
EMIFA
NAND
FLASH
x8,
MultiPlane
ALE
CLE
DQ[7:0]
CE1
CE2
WE
RE
R/ 1B
R/ 2B
NAND
FLASH
x8,
MultiPlane
DVDD
EMA_WAIT
EMA_CS[4]
EMA_CS[5]
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Figure 6-13. C6745/6747 EMIFA Connection Diagram: Multiple NAND Flash Planes
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6.10.5 External Memory Interface A (EMIFA) Registers
Table 6-18 is a list of the EMIF registers. For more information about these registers, see the C674x DSP
External Memory Interface (EMIF) User's Guide (SPRUFL6).
Table 6-18. External Memory Interface (EMIFA) Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x6800 0000 MIDR Module ID Register
0x6800 0004 AWCC Asynchronous Wait Cycle Configuration Register
0x6800 0008 SDCR SDRAM Configuration Register
0x6800 000C SDRCR SDRAM Refresh Control Register
0x6800 0010 CE2CFG Asynchronous 1 Configuration Register
0x6800 0014 CE3CFG Asynchronous 2 Configuration Register
0x6800 0018 CE4CFG Asynchronous 3 Configuration Register
0x6800 001C CE5CFG Asynchronous 4 Configuration Register
0x6800 0020 SDTIMR SDRAM Timing Register
0x6800 003C SDSRETR SDRAM Self Refresh Exit Timing Register
0x6800 0040 INTRAW EMIFA Interrupt Raw Register
0x6800 0044 INTMSK EMIFA Interrupt Mask Register
0x6800 0048 INTMSKSET EMIFA Interrupt Mask Set Register
0x6800 004C INTMSKCLR EMIFA Interrupt Mask Clear Register
0x6800 0060 NANDFCR NAND Flash Control Register
0x6800 0064 NANDFSR NAND Flash Status Register
0x6800 0070 NANDF1ECC NAND Flash 1 ECC Register (CS2 Space)
0x6800 0074 NANDF2ECC NAND Flash 2 ECC Register (CS3 Space)
0x6800 0078 NANDF3ECC NAND Flash 3 ECC Register (CS4 Space)
0x6800 007C NANDF4ECC NAND Flash 4 ECC Register (CS5 Space)
0x6800 00BC NAND4BITECCLOAD NAND Flash 4-Bit ECC Load Register
0x6800 00C0 NAND4BITECC1 NAND Flash 4-Bit ECC Register 1
0x6800 00C4 NAND4BITECC2 NAND Flash 4-Bit ECC Register 2
0x6800 00C8 NAND4BITECC3 NAND Flash 4-Bit ECC Register 3
0x6800 00CC NAND4BITECC4 NAND Flash 4-Bit ECC Register 4
0x6800 00D0 NANDERRADD1 NAND Flash 4-Bit ECC Error Address Register 1
0x6800 00D4 NANDERRADD2 NAND Flash 4-Bit ECC Error Address Register 2
0x6800 00D8 NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 1
0x6800 00DC NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2
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6.10.6 EMIFA Electrical Data/Timing
Table 6-19 through Table 6-22 assume testing over recommended operating conditions.
Table 6-19. EMIFA SDRAM Interface Timing Requirements
No. PARAMETER MIN MAX UNIT
19 tsu(DV-CLKH) Input setup time, read data valid on EMA_D[15:0] before EMA_CLK rising 1.3 ns
20 th(CLKH-DIV) Input hold time, read data valid on EMA_D[15:0] after EMA_CLK rising 1.5 ns
Table 6-20. EMIFA SDRAM Interface Switching Characteristics
No. PARAMETER MIN MAX UNIT
1 tc(CLK) Cycle time, EMIF clock EMA_CLK 10 ns
2 tw(CLK) Pulse width, EMIF clock EMA_CLK high or low 3 ns
3 td(CLKH-CSV) Delay time, EMA_CLK rising to EMA_CS[0] valid 7 ns
4 toh(CLKH-CSIV) Output hold time, EMA_CLK rising to EMA_CS[0] invalid 1 ns
5 td(CLKH-DQMV) Delay time, EMA_CLK rising to EMA_WE_DQM[1:0] valid 7 ns
6 toh(CLKH-DQMIV) Output hold time, EMA_CLK rising to EMA_WE_DQM[1:0] invalid 1 ns
7 td(CLKH-AV) Delay time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0] valid 7 ns
Output hold time, EMA_CLK rising to EMA_A[12:0] and EMA_BA[1:0]
8 toh(CLKH-AIV) 1 ns
invalid
9 td(CLKH-DV) Delay time, EMA_CLK rising to EMA_D[15:0] valid 7 ns
10 toh(CLKH-DIV) Output hold time, EMA_CLK rising to EMA_D[15:0] invalid 1 ns
11 td(CLKH-RASV) Delay time, EMA_CLK rising to EMA_RAS valid 7 ns
12 toh(CLKH-RASIV) Output hold time, EMA_CLK rising to EMA_RAS invalid 1 ns
13 td(CLKH-CASV) Delay time, EMA_CLK rising to EMA_CAS valid 7 ns
14 toh(CLKH-CASIV) Output hold time, EMA_CLK rising to EMA_CAS invalid 1 ns
15 td(CLKH-WEV) Delay time, EMA_CLK rising to EMA_WE valid 7 ns
16 toh(CLKH-WEIV) Output hold time, EMA_CLK rising to EMA_WE invalid 1 ns
17 tdis(CLKH-DHZ) Delay time, EMA_CLK rising to EMA_D[15:0] 3-stated 7 ns
18 tena(CLKH-DLZ) Output hold time, EMA_CLK rising to EMA_D[15:0] driving 1 ns
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EMA_CLK
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
1
2 2
4
6
8
8
12
14
19
20
3
5
7
7
11
13
17 18
2 EM_CLK Delay
BASIC SDRAM
READ OPERATION
EMA_CS[0]
EMA_WE_DQM[1:0]
EMA_RAS
EMA_CAS
EMA_WE
EMA_CLK
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
1
2 2
4
6
8
8
12
10
16
3
5
7
7
11
13
15
9
BASIC SDRAM
WRITE OPERATION
EMA_CS[0]
EMA_WE_DQM[1:0]
EMA_RAS
EMA_CAS
EMA_WE
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Figure 6-14. EMIFA Basic SDRAM Write Operation
Figure 6-15. EMIFA Basic SDRAM Read Operation
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Table 6-21. EMIFA Asynchronous Memory Timing Requirements(1)
No. PARAMETER MIN NOM MAX UNIT
READS and WRITES
E tc(CLK) Cycle time, EMIFA module clock 10 ns
2 tw(EM_WAIT) Pulse duration, EM_WAIT assertion and deassertion 2E ns
READS
12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 3 ns
13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 0 ns
14 tsu (EMOEL-EMWAIT) Setup Time, EM_WAIT asserted before end of Strobe Phase(2) 4E+3 ns
WRITES
28 tsu (EMWEL-EMWAIT) Setup Time, EM_WAIT asserted before end of Strobe Phase(2) 4E+3 ns
(1) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 6-18 and Figure 6-19 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 6-22. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3)
No. PARAMETER MIN NOM MAX UNIT
READS and WRITES
1 td(TURNAROUND) Turn around time (TA)*E - 3 (TA)*E (TA)*E + 3 ns
READS
(RS+RST+RH)*E (RS+RST+RH)*E
EMIF read cycle time (EW = 0) (RS+RST+RH)*E ns
- 3 + 3
3 tc(EMRCYCLE) (RS+RST+RH+E (RS+RST+RH+EWC (RS+RST+RH+E
EMIF read cycle time (EW = 1) ns
WC)*E - 3 )*E WC)*E + 3
Output setup time, EMA_CE[5:2] low to (RS)*E-3 (RS)*E (RS)*E+3 ns
EMA_OE low (SS = 0)
4 tsu(EMCEL-EMOEL) Output setup time, EMA_CE[5:2] low to -3 0 +3 ns
EMA_OE low (SS = 1)
Output hold time, EMA_OE high to (RH)*E - 3 (RH)*E (RH)*E + 3 ns
EMA_CE[5:2] high (SS = 0)
5 th(EMOEH-EMCEH) Output hold time, EMA_OE high to -3 0 +3 ns
EMA_CE[5:2] high (SS = 1)
Output setup time, EMA_BA[1:0] valid to
6 tsu(EMBAV-EMOEL) (RS)*E-3 (RS)*E (RS)*E+3 ns
EMA_OE low
Output hold time, EMA_OE high to
7 th(EMOEH-EMBAIV) (RH)*E-3 (RH)*E (RH)*E+3 ns
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
8 tsu(EMBAV-EMOEL) (RS)*E-3 (RS)*E (RS)*E+3 ns
EMA_OE low
Output hold time, EMA_OE high to
9 th(EMOEH-EMAIV) (RH)*E-3 (RH)*E (RH)*E+3 ns
EMA_A[13:0] invalid
EMA_OE active low width (EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns
10 tw(EMOEL) EMA_OE active low width (EW = 1) (RST+EWC)*E-3 (RST+EWC)*E (RST+EWC)*E+3 ns
td(EMWAITH- Delay time from EMA_WAIT deasserted to
11 3E-3 4E 4E+3 ns
EMOEH) EMA_OE high
WRITES
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256].
(2) E = EMA_CLK period or in ns. EMA_CLK is selected either as SYSCLK3 or the PLL output clock divided by 4.5. As an example, when
SYSCLK3 is selected and set to 100MHz, E=10ns.
(3) EWC = external wait cycles determined by EMA_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register.
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Table 6-22. EMIFA Asynchronous Memory Switching Characteristics(1) (2) (3) (continued)
No. PARAMETER MIN NOM MAX UNIT
(WS+WST+WH)* (WS+WST+WH)*
EMIF write cycle time (EW = 0) (WS+WST+WH)*E ns
E-3 E+3
15 tc(EMWCYCLE) (WS+WST+WH+ (WS+WST+WH+EW (WS+WST+WH+
EMIF write cycle time (EW = 1) ns
EWC)*E - 3 C)*E EWC)*E + 3
Output setup time, EMA_CE[5:2] low to (WS)*E - 3 (WS)*E (WS)*E + 3 ns
EMA_WE low (SS = 0)
16 tsu(EMCEL-EMWEL) Output setup time, EMA_CE[5:2] low to -3 0 +3 ns
EMA_WE low (SS = 1)
Output hold time, EMA_WE high to (WH)*E-3 (WH)*E (WH)*E+3 ns
EMA_CE[5:2] high (SS = 0)
17 th(EMWEH-EMCEH) Output hold time, EMA_WE high to -3 0 +3 ns
EMA_CE[5:2] high (SS = 1)
tsu(EMDQMV- Output setup time, EMA_BA[1:0] valid to
18 (WS)*E-3 (WS)*E (WS)*E+3 ns
EMWEL) EMA_WE low
th(EMWEH- Output hold time, EMA_WE high to
19 (WH)*E-3 (WH)*E (WH)*E+3 ns
EMDQMIV) EMA_BA[1:0] invalid
Output setup time, EMA_BA[1:0] valid to
20 tsu(EMBAV-EMWEL) (WS)*E-3 (WS)*E (WS)*E+3 ns
EMA_WE low
Output hold time, EMA_WE high to
21 th(EMWEH-EMBAIV) (WH)*E-3 (WH)*E (WH)*E+3 ns
EMA_BA[1:0] invalid
Output setup time, EMA_A[13:0] valid to
22 tsu(EMAV-EMWEL) (WS)*E-3 (WS)*E (WS)*E+3 ns
EMA_WE low
Output hold time, EMA_WE high to
23 th(EMWEH-EMAIV) (WH)*E-3 (WH)*E (WH)*E+3 ns
EMA_A[13:0] invalid
EMA_WE active low width (EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns
24 tw(EMWEL) EMA_WE active low width (EW = 1) (WST+EWC)*E-3 (WST+EWC)*E (WST+EWC)*E+3 ns
td(EMWAITH- Delay time from EMA_WAIT deasserted to
25 3E-3 4E 4E+3 ns
EMWEH) EMA_WE high
Output setup time, EMA_D[15:0] valid to
26 tsu(EMDV-EMWEL) (WS)*E-3 (WS)*E (WS)*E+3 ns
EMA_WE low
Output hold time, EMA_WE high to
27 th(EMWEH-EMDIV) (WH)*E-3 (WH)*E (WH)*E+3 ns
EMA_D[15:0] invalid
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EMA_CS[5:2]
EMA_BA[1:0]
EMA_A[12:0]
EMA_WE
EMA_D[15:0]
EMA_OE
15
1
16
18
20
22
24
17
19
21
23
26 27
EMA_ _DQM[1:0]WE
EMA_CS[5:2]
EMA_BA[1:0]
13
12
EMA_A[12:0]
EMA_OE
EMA_D[15:0]
EMA_WE
10
5
9
7
4
8
6
31
EMA_ _DQM[1:0]WE
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Figure 6-16. Asynchronous Memory Read Timing for EMIFA
Figure 6-17. Asynchronous Memory Write Timing for EMIFA
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EMA_CS[5:2]
11
Asserted Deasserted
2
2
EMA_BA[1:0]
EMA_A[12:0]
EMA_D[15:0]
EMA_OE
EMA_WAIT
SETUP STROBE Extended Due to EMA_WAIT STROBE HOLD
14
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Figure 6-18. EMA_WAIT Read Timing Requirements
Figure 6-19. EMA_WAIT Write Timing Requirements
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EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[x:0]
EMB_D[x:0]
EMB_WE_DQM[x:0]
SDRAM
Interface
Cmd/Write
FIFO
Registers
Read
FIFO
Crossbar
EMIFB
Master
Peripherals
(USB, UHPI...)
EDMA
CPU
MPU2
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6.11 External Memory Interface B (EMIFB)
Figure 6-20 illustrates a high-level view of the EMIFB and its connections within the device. Multiple
requesters have access to EMIFB through a switched central resource (indicated as crossbar in the
figure). The EMIFB implements a split transaction internal bus, allowing concurrence between reads and
writes from the various requesters.
Figure 6-20. EMIFB Functional Block Diagram
EMIFB supports a 3.3V LVCMOS Interface.
6.11.1 EMIFB SDRAM Loading Limitations
EMIFB supports SDRAM up to 152MHz with up to two SDRAM or asynchronous memory loads. Additional
loads will limit the SDRAM operation to lower speeds and the maximum speed should be confirmed by
board simulation using IBIS models.
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6.11.2 Interfacing to SDRAM
The EMIFB supports a glueless interface to SDRAM devices with the following characteristics:
• Pre-charge bit is A[10]
• Supports 8, 9, 10 or 11 column address bits
• Supports up to 13 row address bits
• Supports 1, 2 or 4 internal banks
Table 6-23 shows the supported SDRAM configurations for EMIFB.
Table 6-23. EMIFB Supported SDRAM Configurations(1)
SDRAM
Memory Memory
Number of EMIFB Data Total Memory Total Memory
Data Bus Rows Columns Banks Density
Memories Bus Size (Mbits) (Mbytes)
Width (Mbits)
(bits)
1 32 13 8 1 64 8 64
1 32 13 8 2 128 16 128
1 32 13 8 4 256 32 256
1 32 13 9 1 128 16 128
1 32 13 9 2 256 32 256
1 32 13 9 4 512 64 512
32 1 32 13 10 1 256 32 256
1 32 13 10 2 512 64 512
1 32 13 10 4 1024 128 1024
1 32 13 11 1 512 64 512
1 32 13 11 2 1024 128 1024
1 32 13 11 4 2048 256 2048
2 32 13 8 1 64 8 32
2 32 13 8 2 128 16 64
2 32 13 8 4 256 32 128
2 32 13 9 1 128 16 64
2 32 13 9 2 256 32 128
2 32 13 9 4 512 64 256
16 2 32 13 10 1 256 32 128
2 32 13 10 2 512 64 256
2 32 13 10 4 1024 128 512
2 32 13 11 1 512 64 256
2 32 13 11 2 1024 128 512
2 32 13 11 4 2048 256 1024
(1) The shaded cells indicate configurations that are possible on the EMIFB interface but as of this writing SDRAM memories capable of
supporting these densities are not available in the market.
Figure 6-21 shows an interface between the EMIFB and a 2M × 16 × 4 bank SDRAM device. In addition,
Figure 6-22 shows an interface between the EMIFB and a 2M × 32 × 4 bank SDRAM device and Figure 6-
23 shows an interface between the EMIFB and two 4M × 16 × 4 bank SDRAM devices. Refer to Table 6-
24, as an example that shows additional list of commonly-supported SDRAM devices and the required
connections for the address pins. Note that in Table 6-24, page size/column size (not indicated in the
table) is varied to get the required addressability range.
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EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[3:0]
EMB_D[31:0]
EMIFB
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
DQM[3:0]
DQ[31:0]
SDRAM
2Mx32x4
Bank
EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[11:0]
EMB_WE_DQM[0]
EMB_WE_DQM[1]
EMB_D[15:0]
EMIFB
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[11:0]
LDQM
UDQM
DQ[15:0]
SDRAM
2Mx16x4
Bank
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Figure 6-21. EMIFB to 2M × 16 × 4 bank SDRAM Interface
Figure 6-22. EMIFB to 2M × 32 × 4 bank SDRAM Interface
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EMB_CS
EMB_CAS
EMB_RAS
EMB_WE
EMB_CLK
EMB_SDCKE
EMB_BA[1:0]
EMB_A[12:0]
EMB_WE_DQM[0]
EMB_D[15:0]
EMIFB
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
DQ[15:0]
SDRAM
4Mx16x4
Bank
EMB_WE_DQM[1] UDQM
EMB_WE_DQM[2]
EMB_D[31:16]
EMB_WE_DQM[3]
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
DQ[15:0]
SDRAM
4Mx16x4
Bank
UDQM
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Figure 6-23. EMIFB to Dual 4M × 16 × 4 bank SDRAM Interface
Table 6-24. Example of 16/32-bit EMIFB Address Pin Connections
SDRAM SIZE WIDTH BANKS MEMORY ADDRESS PINS
64M bits ×16 4 SDRAM A[11:0]
EMIFB EMB_A[11:0]
×32 4 SDRAM A[10:0]
EMIFB EMB_A[10:0]
128M bits ×16 4 SDRAM A[11:0]
EMIFB EMB_A[11:0]
×32 4 SDRAM A[11:0]
EMIFB EMB_A[11:0]
256M bits ×16 4 SDRAM A[12:0]
EMIFB EMB_A[12:0]
×32 4 SDRAM A[11:0]
EMIFB EMB_A[11:0]
512M bits ×16 4 SDRAM A[12:0]
EMIFB EMB_A[12:0]
×32 4 SDRAM A[12:0]
EMIFB EMB_A[12:0]
Table 6-25 is a list of the EMIFB registers.
Table 6-25. EMIFB Base Controller Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0xB000 0000 MIDR Module ID Register
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Table 6-25. EMIFB Base Controller Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0xB000 0008 SDCFG SDRAM Configuration Register
0xB000 000C SDRFC SDRAM Refresh Control Register
0xB000 0010 SDTIM1 SDRAM Timing Register 1
0xB000 0014 SDTIM2 SDRAM Timing Register 2
0xB000 001C SDCFG2 SDRAM Configuration 2 Register
0xB000 0020 BPRIO Peripheral Bus Burst Priority Register
0xB000 0040 PC1 Performance Counter 1 Register
0xB000 0044 PC2 Performance Counter 2 Register
0xB000 0048 PCC Performance Counter Configuration Register
0xB000 004C PCMRS Performance Counter Master Region Select Register
0xB000 0050 PCT Performance Counter Time Register
0xB000 00C0 IRR Interrupt Raw Register
0xB000 00C4 IMR Interrupt Mask Register
0xB000 00C8 IMSR Interrupt Mask Set Register
0xB000 00CC IMCR Interrupt Mask Clear Register
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6.11.3 EMIFB Electrical Data/Timing
Table 6-26. EMIFB SDRAM Interface Timing Requirements
CVDD = 1.3 V(1) CVDD = 1.2V(2) UN
NO. IT
MIN MAX MIN MAX
Input setup time, read data valid on EMB_D[31:0] before
19 t(DV-CLKH) 0.59 0.8 ns
EMB_CLK rising
Input hold time, read data valid on EMB_D[31:0] after
20 th(CLKH-DIV) 1.25 1.5 ns
EMB_CLK rising
(1) Commercial (default), Industrial and Extended temperature range rated devices for 456 MHz max CPU operating frequency as
applicable to the device
(2) Commercial (default), Industrial, Extended and Automotive temperature range rated devices for 400/375/300/266/200 MHz max CPU
operating frequencies as applicable to the device
Table 6-27. EMIFB SDRAM Interface Switching Characteristics for Commercial (Default) Temperature
Range
CVDD = 1.3 V(1) CVDD = 1.2V(2) UN
NO. PARAMETER IT
MIN MAX MIN MAX
1 tc(CLK) Cycle time, EMIF clock EMB_CLK 6.579 7.5 ns
2 tw(CLK) Pulse width, EMIF clock EMB_CLK high or low 2.63 3 ns
3 td(CLKH-CSV) Delay time, EMB_CLK rising to EMB_CS[0] valid 4.25 5.1 ns
4 toh(CLKH-CSIV) Output hold time, EMB_CLK rising to EMB_CS[0] invalid 1.1 1.1 ns
5 td(CLKH-DQMV) Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid 4.25 5.1 ns
Output hold time, EMB_CLK rising to
6 toh(CLKH-DQMIV) 1.1 1.1 ns
EMB_WE_DQM[3:0] invalid
Delay time, EMB_CLK rising to EMB_A[12:0] and
7 td(CLKH-AV) 4.25 5.1 ns
EMB_BA[1:0] valid
Output hold time, EMB_CLK rising to EMB_A[12:0] and
8 toh(CLKH-AIV) 1.1 1.1 ns
EMB_BA[1:0] invalid
9 td(CLKH-DV) Delay time, EMB_CLK rising to EMB_D[31:0] valid 4.25 5.1 ns
Output hold time, EMB_CLK rising to EMB_D[31:0]
10 toh(CLKH-DIV) 1.1 1.1 ns
invalid
11 td(CLKH-RASV) Delay time, EMB_CLK rising to EMB_RAS valid 4.25 5.1 ns
12 toh(CLKH-RASIV) Output hold time, EMB_CLK rising to EMB_RAS invalid 1.1 1.1 ns
13 td(CLKH-CASV) Delay time, EMB_CLK rising to EMB_CAS valid 4.25 5.1 ns
14 toh(CLKH-CASIV) Output hold time, EMB_CLK rising to EMB_CAS invalid 1.1 1.1 ns
15 td(CLKH-WEV) Delay time, EMB_CLK rising to EMB_WE valid 4.25 5.1 ns
16 toh(CLKH-WEIV) Output hold time, EMB_CLK rising to EMB_WE invalid 1.1 1.1 ns
17 tdis(CLKH-DHZ) Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated 4.25 5.1 ns
Output hold time, EMB_CLK rising to EMB_D[31:0]
18 t(CLKH-DLZ) 1.1 1.1 ns
driving
(1) Commercial (default) temperature range rated devices for 456 MHz max CPU operating frequency as applicable to the device
(2) Commercial (default) temperature range rated devices for 400/375/300/266/200 MHz max CPU operating frequencies as applicable to
the device
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Table 6-28. EMIFB SDRAM Interface Switching Characteristics for Industrial, Extended, and Automotive
Temperature Ranges
CVDD = 1.3 V(1) CVDD = 1.2V(2) UN
NO. PARAMETER IT
MIN MAX MIN MAX
1 tc(CLK) Cycle time, EMIF clock EMB_CLK 6.579 7.5 ns
2 tw(CLK) Pulse width, EMIF clock EMB_CLK high or low 2.63 3 ns
3 td(CLKH-CSV) Delay time, EMB_CLK rising to EMB_CS[0] valid 4.25 5.1 ns
4 toh(CLKH-CSIV) Output hold time, EMB_CLK rising to EMB_CS[0] invalid 1.1 0.9 ns
5 td(CLKH-DQMV) Delay time, EMB_CLK rising to EMB_WE_DQM[3:0] valid 4.25 5.1 ns
Output hold time, EMB_CLK rising to
6 toh(CLKH-DQMIV) 1.1 0.9 ns
EMB_WE_DQM[3:0] invalid
Delay time, EMB_CLK rising to EMB_A[12:0] and
7 td(CLKH-AV) 4.25 5.1 ns
EMB_BA[1:0] valid
Output hold time, EMB_CLK rising to EMB_A[12:0] and
8 toh(CLKH-AIV) 1.1 0.9 ns
EMB_BA[1:0] invalid
9 td(CLKH-DV) Delay time, EMB_CLK rising to EMB_D[31:0] valid 4.25 5.1 ns
Output hold time, EMB_CLK rising to EMB_D[31:0]
10 toh(CLKH-DIV) 1.1 0.9 ns
invalid
11 td(CLKH-RASV) Delay time, EMB_CLK rising to EMB_RAS valid 4.25 5.1 ns
12 toh(CLKH-RASIV) Output hold time, EMB_CLK rising to EMB_RAS invalid 1.1 0.9 ns
13 td(CLKH-CASV) Delay time, EMB_CLK rising to EMB_CAS valid 4.25 5.1 ns
14 toh(CLKH-CASIV) Output hold time, EMB_CLK rising to EMB_CAS invalid 1.1 0.9 ns
15 td(CLKH-WEV) Delay time, EMB_CLK rising to EMB_WE valid 4.25 5.1 ns
16 toh(CLKH-WEIV) Output hold time, EMB_CLK rising to EMB_WE invalid 1.1 0.9 ns
17 tdis(CLKH-DHZ) Delay time, EMB_CLK rising to EMB_D[31:0] tri-stated 4.25 5.1 ns
Output hold time, EMB_CLK rising to EMB_D[31:0]
18 t(CLKH-DLZ) 1.1 0.9 ns
driving
(1) Industrial temperature range rated devices for 456 MHz max CPU operating frequency as applicable to the device
(2) Industrial, Extended and Automotive temperature range rated devices for 400/375/300/266/200 MHz max CPU operating frequencies as
applicable to the device
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EMB_CLK
EMB_BA[1:0]
EMB_A[12:0]
EMB_D[31:0]
1
2 2
4
6
8
8
12
14
19
20
3
5
7
7
11
13
17 18
2 EM_CLK Delay
BASIC SDRAM
READ OPERATION
EMB_CS[0]
EMB_WE_DQM[3:0]
EMB_RAS
EMB_CAS
EMB_WE
EMB_CLK
EMB_BA[1:0]
EMB_A[12:0]
EMB_D[31:0]
1
2 2
4
6
8
8
12
10
16
3
5
7
7
11
13
15
9
BASIC SDRAM
WRITE OPERATION
EMB_CS[0]
EMB_WE_DQM[3:0]
EMB_RAS
EMB_CAS
EMB_WE
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Figure 6-24. EMIFB Basic SDRAM Write Operation
Figure 6-25. EMIFB Basic SDRAM Read Operation
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6.12 Memory Protection Units
The MPU performs memory protection checking. It receives requests from a bus master in the system and
checks the address against the fixed and programmable regions to see if the access is allowed. If allowed,
the transfer is passed unmodified to its output bus (to the targeted address). If the transfer is illegal (fails
the protection check) then the MPU does not pass the transfer to the output bus but rather services the
transfer internally back to the input bus (to prevent a hang) returning the fault status to the requestor as
well as generating an interrupt about the fault. The following features are supported by the MPU:
• Provides memory protection for fixed and programmable address ranges
• Supports multiple programmable address region
• Supports secure and debug access privileges
• Supports read, write, and execute access privileges
• Supports privid(8) associations with ranges
• Generates an interrupt when there is a protection violation, and saves violating transfer parameters
• MMR access is also protected
Table 6-29. MPU1 Configuration Registers
MPU1 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS
0x01E1 4000 REVID Revision ID
0x01E1 4004 CONFIG Configuration
0x01E1 4010 IRAWSTAT Interrupt raw status/set
0x01E1 4014 IENSTAT Interrupt enable status/clear
0x01E1 4018 IENSET Interrupt enable
0x01E1 401C IENCLR Interrupt enable clear
0x01E1 4020 - 0x01E1 41FF - Reserved
0x01E1 4200 PROG1_MPSAR Programmable range 1, start address
0x01E1 4204 PROG1_MPEAR Programmable range 1, end address
0x01E1 4208 PROG1_MPPA Programmable range 1, memory page protection attributes
0x01E1 420C - 0x01E1 420F - Reserved
0x01E1 4210 PROG2_MPSAR Programmable range 2, start address
0x01E1 4214 PROG2_MPEAR Programmable range 2, end address
0x01E1 4218 PROG2_MPPA Programmable range 2, memory page protection attributes
0x01E1 421C - 0x01E1 421F - Reserved
0x01E1 4220 PROG3_MPSAR Programmable range 3, start address
0x01E1 4224 PROG3_MPEAR Programmable range 3, end address
0x01E1 4228 PROG3_MPPA Programmable range 3, memory page protection attributes
0x01E1 422C - 0x01E1 422F - Reserved
0x01E1 4230 PROG4_MPSAR Programmable range 4, start address
0x01E1 4234 PROG4_MPEAR Programmable range 4, end address
0x01E1 4238 PROG4_MPPA Programmable range 4, memory page protection attributes
0x01E1 423C - 0x01E1 423F - Reserved
0x01E1 4240 PROG5_MPSAR Programmable range 5, start address
0x01E1 4244 PROG5_MPEAR Programmable range 5, end address
0x01E1 4248 PROG5_MPPA Programmable range 5, memory page protection attributes
0x01E1 424C - 0x01E1 424F - Reserved
0x01E1 4250 PROG6_MPSAR Programmable range 6, start address
0x01E1 4254 PROG6_MPEAR Programmable range 6, end address
0x01E1 4258 PROG6_MPPA Programmable range 6, memory page protection attributes
0x01E1 425C - 0x01E1 42FF - Reserved
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Table 6-29. MPU1 Configuration Registers (continued)
MPU1 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS
0x01E14300 FLTADDRR Fault address
0x01E1 4304 FLTSTAT Fault status
0x01E1 4308 FLTCLR Fault clear
0x01E1 430C - 0x01E1 4FFF - Reserved
Table 6-30. MPU2 Configuration Registers
MPU2 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS
0x01E1 5000 REVID Revision ID
0x01E1 5004 CONFIG Configuration
0x01E1 5010 IRAWSTAT Interrupt raw status/set
0x01E1 5014 IENSTAT Interrupt enable status/clear
0x01E1 5018 IENSET Interrupt enable
0x01E1 501C IENCLR Interrupt enable clear
0x01E1 5020 - 0x01E1 50FF - Reserved
0x01E1 5100 FXD_MPSAR Fixed range start address
0x01E1 5104 FXD_MPEAR Fixed range end start address
0x01E1 5108 FXD_MPPA Fixed range memory page protection attributes
0x01E1 510C - 0x01E1 51FF - Reserved
0x01E1 5200 PROG1_MPSAR Programmable range 1, start address
0x01E1 5204 PROG1_MPEAR Programmable range 1, end address
0x01E1 5208 PROG1_MPPA Programmable range 1, memory page protection attributes
0x01E1 520C - 0x01E1 520F - Reserved
0x01E1 5210 PROG2_MPSAR Programmable range 2, start address
0x01E1 5214 PROG2_MPEAR Programmable range 2, end address
0x01E1 5218 PROG2_MPPA Programmable range 2, memory page protection attributes
0x01E1 521C - 0x01E1 521F - Reserved
0x01E1 5220 PROG3_MPSAR Programmable range 3, start address
0x01E1 5224 PROG3_MPEAR Programmable range 3, end address
0x01E1 5228 PROG3_MPPA Programmable range 3, memory page protection attributes
0x01E1 522C - 0x01E1 522F - Reserved
0x01E1 5230 PROG4_MPSAR Programmable range 4, start address
0x01E1 5234 PROG4_MPEAR Programmable range 4, end address
0x01E1 5238 PROG4_MPPA Programmable range 4, memory page protection attributes
0x01E1 523C - 0x01E1 523F - Reserved
0x01E1 5240 PROG5_MPSAR Programmable range 5, start address
0x01E1 5244 PROG5_MPEAR Programmable range 5, end address
0x01E1 5248 PROG5_MPPA Programmable range 5, memory page protection attributes
0x01E1 524C - 0x01E1 524F - Reserved
0x01E1 5250 PROG6_MPSAR Programmable range 6, start address
0x01E1 5254 PROG6_MPEAR Programmable range 6, end address
0x01E1 5258 PROG6_MPPA Programmable range 6, memory page protection attributes
0x01E1 525C - 0x01E1 525F - Reserved
0x01E1 5260 PROG7_MPSAR Programmable range 7, start address
0x01E1 5264 PROG7_MPEAR Programmable range 7, end address
0x01E1 5268 PROG7_MPPA Programmable range 7, memory page protection attributes
0x01E1 526C - 0x01E1 526F - Reserved
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Table 6-30. MPU2 Configuration Registers (continued)
MPU2 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS
0x01E1 5270 PROG8_MPSAR Programmable range 8, start address
0x01E1 5274 PROG8_MPEAR Programmable range 8, end address
0x01E1 5278 PROG8_MPPA Programmable range 8, memory page protection attributes
0x01E1 527C - 0x01E1 527F - Reserved
0x01E1 5280 PROG9_MPSAR Programmable range 9, start address
0x01E1 5284 PROG9_MPEAR Programmable range 9, end address
0x01E1 5288 PROG9_MPPA Programmable range 9, memory page protection attributes
0x01E1 528C - 0x01E1 528F - Reserved
0x01E1 5290 PROG10_MPSAR Programmable range 10, start address
0x01E1 5294 PROG10_MPEAR Programmable range 10, end address
0x01E1 5298 PROG10_MPPA Programmable range 10, memory page protection attributes
0x01E1 529C - 0x01E1 529F - Reserved
0x01E1 52A0 PROG11_MPSAR Programmable range 11, start address
0x01E1 52A4 PROG11_MPEAR Programmable range 11, end address
0x01E1 52A8 PROG11_MPPA Programmable range 11, memory page protection attributes
0x01E1 52AC - 0x01E1 52AF - Reserved
0x01E1 52B0 PROG12_MPSAR Programmable range 12, start address
0x01E1 52B4 PROG12_MPEAR Programmable range 12, end address
0x01E1 52B8 PROG12_MPPA Programmable range 12, memory page protection attributes
0x01E1 52BC - 0x01E1 52FF - Reserved
0x01E1 5300 FLTADDRR Fault address
0x01E1 5304 FLTSTAT Fault status
0x01E1 5308 FLTCLR Fault clear
0x01E1 530C - 0x01E1 5FFF - Reserved
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6.13 MMC / SD / SDIO (MMCSD)
6.13.1 MMCSD Peripheral Description
The C6745/6747 includes an MMCSD controller which is compliant with MMC V4.0, Secure Digital Part 1
Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V2.0 specifications.
The MMC/SD Controller has following features:
• MultiMediaCard (MMC) support
• Secure Digital (SD) Memory Card support
• MMC/SD protocol support
• SD high capacity support
• SDIO protocol support
• Programmable clock frequency
• 512 bit Read/Write FIFO to lower system overhead
• Slave EDMA transfer capability
The C6745/6747 MMC/SD Controller does not support SPI mode.
6.13.2 MMCSD Peripheral Register Description(s)
Table 6-31. Multimedia Card/Secure Digital (MMC/SD) Card Controller Registers
BYTE ACRONYM REGISTER DESCRIPTION
ADDRESS
0x01C4 0000 MMCCTL MMC Control Register
0x01C4 0004 MMCCLK MMC Memory Clock Control Register
0x01C4 0008 MMCST0 MMC Status Register 0
0x01C4 000C MMCST1 MMC Status Register 1
0x01C4 0010 MMCIM MMC Interrupt Mask Register
0x01C4 0014 MMCTOR MMC Response Time-Out Register
0x01C4 0018 MMCTOD MMC Data Read Time-Out Register
0x01C4 001C MMCBLEN MMC Block Length Register
0x01C4 0020 MMCNBLK MMC Number of Blocks Register
0x01C4 0024 MMCNBLC MMC Number of Blocks Counter Register
0x01C4 0028 MMCDRR MMC Data Receive Register
0x01C4 002C MMCDXR MMC Data Transmit Register
0x01C4 0030 MMCCMD MMC Command Register
0x01C4 0034 MMCARGHL MMC Argument Register
0x01C4 0038 MMCRSP01 MMC Response Register 0 and 1
0x01C4 003C MMCRSP23 MMC Response Register 2 and 3
0x01C4 0040 MMCRSP45 MMC Response Register 4 and 5
0x01C4 0044 MMCRSP67 MMC Response Register 6 and 7
0x01C4 0048 MMCDRSP MMC Data Response Register
0x01C4 0050 MMCCIDX MMC Command Index Register
0x01C4 0064 SDIOCTL SDIO Control Register
0x01C4 0068 SDIOST0 SDIO Status Register 0
0x01C4 006C SDIOIEN SDIO Interrupt Enable Register
0x01C4 0070 SDIOIST SDIO Interrupt Status Register
0x01C4 0074 MMCFIFOCTL MMC FIFO Control Register
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6.13.3 MMC/SD Electrical Data/Timing
Table 6-32. Timing Requirements for MMC/SD Module
(see Figure 6-27 and Figure 6-29)
No. PARAMETER MIN MAX UNIT
1 tsu(CMDV-CLKH) Setup time, MMCSD_CMD valid before MMCSD_CLK high 3.2 ns
2 th(CLKH-CMDV) Hold time, MMCSD_CMD valid after MMCSD_CLK high 1.5 ns
3 tsu(DATV-CLKH) Setup time, MMCSD_DATx valid before MMCSD_CLK high 3.2 ns
4 th(CLKH-DATV) Hold time, MMCSD_DATx valid after MMCSD_CLK high 1.5 ns
Table 6-33. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 6-26 through Figure 6-29)
No. PARAMETER MIN MAX UNIT
7 f(CLK) Operating frequency, MMCSD_CLK 0 52 MHz
8 f(CLK_ID) Identification mode frequency, MMCSD_CLK 0 400 KHz
9 tW(CLKL) Pulse width, MMCSD_CLK low 6.5 ns
10 tW(CLKH) Pulse width, MMCSD_CLK high 6.5 ns
11 tr(CLK) Rise time, MMCSD_CLK 3 ns
12 tf(CLK) Fall time, MMCSD_CLK 3 ns
13 td(CLKL-CMD) Delay time, MMCSD_CLK low to MMCSD_CMD transition -4.5 2.5 ns
14 td(CLKL-DAT) Delay time, MMCSD_CLK low to MMCSD_DATx transition -4.5 2.5 ns
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Start D0 D1 Dx End
7
MMCSD_CLK
MMCSD_DATx
9
10
4
3 3
4
START D0 D1 Dx END
MMCSD_CLK
MMCSD_DATx
7
1414
10
9
14 14
START XMIT Valid Valid Valid END
MMCSD_CLK
MMCSD_CMD
10
9
7
1
2
START XMIT Valid Valid Valid END
MMCSD_CLK
MMCSD_CMD
13
7
10
9
13 13 13
TMS320C6745, TMS320C6747
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Figure 6-26. MMC/SD Host Command Timing
Figure 6-27. MMC/SD Card Response Timing
Figure 6-28. MMC/SD Host Write Timing
Figure 6-29. MMC/SD Host Read and Card CRC Status Timing
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6.14 Ethernet Media Access Controller (EMAC)
The Ethernet Media Access Controller (EMAC) provides an efficient interface between C6745/6747 and
the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100
Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The EMAC controls the flow of packet data from the C6745/6747 device to the PHY. The MDIO module
controls PHY configuration and status monitoring.
Both the EMAC and the MDIO modules interface to the C6745/6747 device through a custom interface
that allows efficient data transmission and reception. This custom interface is referred to as the EMAC
control module, and is considered integral to the EMAC/MDIO peripheral. The control module is also used
to multiplex and control interrupts.
6.14.1 EMAC Peripheral Register Description(s)
Table 6-34. Ethernet Media Access Controller (EMAC) Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 3000 TXREV Transmit Revision Register
0x01E2 3004 TXCONTROL Transmit Control Register
0x01E2 3008 TXTEARDOWN Transmit Teardown Register
0x01E2 3010 RXREV Receive Revision Register
0x01E2 3014 RXCONTROL Receive Control Register
0x01E2 3018 RXTEARDOWN Receive Teardown Register
0x01E2 3080 TXINTSTATRAW Transmit Interrupt Status (Unmasked) Register
0x01E2 3084 TXINTSTATMASKED Transmit Interrupt Status (Masked) Register
0x01E2 3088 TXINTMASKSET Transmit Interrupt Mask Set Register
0x01E2 308C TXINTMASKCLEAR Transmit Interrupt Clear Register
0x01E2 3090 MACINVECTOR MAC Input Vector Register
0x01E2 3094 MACEOIVECTOR MAC End Of Interrupt Vector Register
0x01E2 30A0 RXINTSTATRAW Receive Interrupt Status (Unmasked) Register
0x01E2 30A4 RXINTSTATMASKED Receive Interrupt Status (Masked) Register
0x01E2 30A8 RXINTMASKSET Receive Interrupt Mask Set Register
0x01E2 30AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register
0x01E2 30B0 MACINTSTATRAW MAC Interrupt Status (Unmasked) Register
0x01E2 30B4 MACINTSTATMASKED MAC Interrupt Status (Masked) Register
0x01E2 30B8 MACINTMASKSET MAC Interrupt Mask Set Register
0x01E2 30BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register
0x01E2 3100 RXMBPENABLE Receive Multicast/Broadcast/Promiscuous Channel Enable Register
0x01E2 3104 RXUNICASTSET Receive Unicast Enable Set Register
0x01E2 3108 RXUNICASTCLEAR Receive Unicast Clear Register
0x01E2 310C RXMAXLEN Receive Maximum Length Register
0x01E2 3110 RXBUFFEROFFSET Receive Buffer Offset Register
0x01E2 3114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register
0x01E2 3120 RX0FLOWTHRESH Receive Channel 0 Flow Control Threshold Register
0x01E2 3124 RX1FLOWTHRESH Receive Channel 1 Flow Control Threshold Register
0x01E2 3128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register
0x01E2 312C RX3FLOWTHRESH Receive Channel 3 Flow Control Threshold Register
0x01E2 3130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register
0x01E2 3134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register
0x01E2 3138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register
0x01E2 313C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register
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Table 6-34. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 3140 RX0FREEBUFFER Receive Channel 0 Free Buffer Count Register
0x01E2 3144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register
0x01E2 3148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register
0x01E2 314C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register
0x01E2 3150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register
0x01E2 3154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register
0x01E2 3158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register
0x01E2 315C RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register
0x01E2 3160 MACCONTROL MAC Control Register
0x01E2 3164 MACSTATUS MAC Status Register
0x01E2 3168 EMCONTROL Emulation Control Register
0x01E2 316C FIFOCONTROL FIFO Control Register
0x01E2 3170 MACCONFIG MAC Configuration Register
0x01E2 3174 SOFTRESET Soft Reset Register
0x01E2 31D0 MACSRCADDRLO MAC Source Address Low Bytes Register
0x01E2 31D4 MACSRCADDRHI MAC Source Address High Bytes Register
0x01E2 31D8 MACHASH1 MAC Hash Address Register 1
0x01E2 31DC MACHASH2 MAC Hash Address Register 2
0x01E2 31E0 BOFFTEST Back Off Test Register
0x01E2 31E4 TPACETEST Transmit Pacing Algorithm Test Register
0x01E2 31E8 RXPAUSE Receive Pause Timer Register
0x01E2 31EC TXPAUSE Transmit Pause Timer Register
0x01E2 3200 - 0x01E2 32FC (see Table 6-35) EMAC Statistics Registers
0x01E2 3500 MACADDRLO MAC Address Low Bytes Register, Used in Receive Address Matching
0x01E2 3504 MACADDRHI MAC Address High Bytes Register, Used in Receive Address Matching
0x01E2 3508 MACINDEX MAC Index Register
0x01E2 3600 TX0HDP Transmit Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3608 TX2HDP Transmit Channel 2 DMA Head Descriptor Pointer Register
0x01E2 360C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register
0x01E2 361C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3620 RX0HDP Receive Channel 0 DMA Head Descriptor Pointer Register
0x01E2 3624 RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register
0x01E2 3628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register
0x01E2 362C RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register
0x01E2 3630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register
0x01E2 3634 RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register
0x01E2 3638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register
0x01E2 363C RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register
0x01E2 3640 TX0CP Transmit Channel 0 Completion Pointer Register
0x01E2 3644 TX1CP Transmit Channel 1 Completion Pointer Register
0x01E2 3648 TX2CP Transmit Channel 2 Completion Pointer Register
0x01E2 364C TX3CP Transmit Channel 3 Completion Pointer Register
0x01E2 3650 TX4CP Transmit Channel 4 Completion Pointer Register
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Table 6-34. Ethernet Media Access Controller (EMAC) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 3654 TX5CP Transmit Channel 5 Completion Pointer Register
0x01E2 3658 TX6CP Transmit Channel 6 Completion Pointer Register
0x01E2 365C TX7CP Transmit Channel 7 Completion Pointer Register
0x01E2 3660 RX0CP Receive Channel 0 Completion Pointer Register
0x01E2 3664 RX1CP Receive Channel 1 Completion Pointer Register
0x01E2 3668 RX2CP Receive Channel 2 Completion Pointer Register
0x01E2 366C RX3CP Receive Channel 3 Completion Pointer Register
0x01E2 3670 RX4CP Receive Channel 4 Completion Pointer Register
0x01E2 3674 RX5CP Receive Channel 5 Completion Pointer Register
0x01E2 3678 RX6CP Receive Channel 6 Completion Pointer Register
0x01E2 367C RX7CP Receive Channel 7 Completion Pointer Register
Table 6-35. EMAC Statistics Registers
BYTE ACRONYM REGISTER DESCRIPTION
ADDRESS
0x01E2 3200 RXGOODFRAMES Good Receive Frames Register
Broadcast Receive Frames Register
0x01E2 3204 RXBCASTFRAMES (Total number of good broadcast frames received)
Multicast Receive Frames Register
0x01E2 3208 RXMCASTFRAMES (Total number of good multicast frames received)
0x01E2 320C RXPAUSEFRAMES Pause Receive Frames Register
Receive CRC Errors Register
0x01E2 3210 RXCRCERRORS (Total number of frames received with CRC errors)
Receive Alignment/Code Errors Register
0x01E2 3214 RXALIGNCODEERRORS (Total number of frames received with alignment/code errors)
Receive Oversized Frames Register
0x01E2 3218 RXOVERSIZED (Total number of oversized frames received)
Receive Jabber Frames Register
0x01E2 321C RXJABBER (Total number of jabber frames received)
Receive Undersized Frames Register
0x01E2 3220 RXUNDERSIZED (Total number of undersized frames received)
0x01E2 3224 RXFRAGMENTS Receive Frame Fragments Register
0x01E2 3228 RXFILTERED Filtered Receive Frames Register
0x01E2 322C RXQOSFILTERED Received QOS Filtered Frames Register
Receive Octet Frames Register
0x01E2 3230 RXOCTETS (Total number of received bytes in good frames)
Good Transmit Frames Register
0x01E2 3234 TXGOODFRAMES (Total number of good frames transmitted)
0x01E2 3238 TXBCASTFRAMES Broadcast Transmit Frames Register
0x01E2 323C TXMCASTFRAMES Multicast Transmit Frames Register
0x01E2 3240 TXPAUSEFRAMES Pause Transmit Frames Register
0x01E2 3244 TXDEFERRED Deferred Transmit Frames Register
0x01E2 3248 TXCOLLISION Transmit Collision Frames Register
0x01E2 324C TXSINGLECOLL Transmit Single Collision Frames Register
0x01E2 3250 TXMULTICOLL Transmit Multiple Collision Frames Register
0x01E2 3254 TXEXCESSIVECOLL Transmit Excessive Collision Frames Register
0x01E2 3258 TXLATECOLL Transmit Late Collision Frames Register
0x01E2 325C TXUNDERRUN Transmit Underrun Error Register
0x01E2 3260 TXCARRIERSENSE Transmit Carrier Sense Errors Register
0x01E2 3264 TXOCTETS Transmit Octet Frames Register
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Table 6-35. EMAC Statistics Registers (continued)
BYTE ACRONYM REGISTER DESCRIPTION
ADDRESS
0x01E2 3268 FRAME64 Transmit and Receive 64 Octet Frames Register
0x01E2 326C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register
0x01E2 3270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register
0x01E2 3274 FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register
0x01E2 3278 FRAME512T1023 Transmit and Receive 512 to 1023 Octet Frames Register
0x01E2 327C FRAME1024TUP Transmit and Receive 1024 to 1518 Octet Frames Register
0x01E2 3280 NETOCTETS Network Octet Frames Register
0x01E2 3284 RXSOFOVERRUNS Receive FIFO or DMA Start of Frame Overruns Register
0x01E2 3288 RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register
0x01E2 328C RXDMAOVERRUNS Receive DMA Start of Frame and Middle of Frame Overruns Register
Table 6-36. EMAC Control Module Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 2000 REV EMAC Control Module Revision Register
0x01E2 2004 SOFTRESET EMAC Control Module Software Reset Register
0x01E2 200C INTCONTROL EMAC Control Module Interrupt Control Register
0x01E2 2010 C0RXTHRESHEN EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Enable Register
0x01E2 2014 C0RXEN EMAC Control Module Interrupt Core 0 Receive Interrupt Enable Register
0x01E2 2018 C0TXEN EMAC Control Module Interrupt Core 0 Transmit Interrupt Enable Register
0x01E2 201C C0MISCEN EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Enable Register
0x01E2 2020 C1RXTHRESHEN EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Enable Register
0x01E2 2024 C1RXEN EMAC Control Module Interrupt Core 1 Receive Interrupt Enable Register
0x01E2 2028 C1TXEN EMAC Control Module Interrupt Core 1 Transmit Interrupt Enable Register
0x01E2 202C C1MISCEN EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Enable Register
0x01E2 2030 C2RXTHRESHEN EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Enable Register
0x01E2 2034 C2RXEN EMAC Control Module Interrupt Core 2 Receive Interrupt Enable Register
0x01E2 2038 C2TXEN EMAC Control Module Interrupt Core 2 Transmit Interrupt Enable Register
0x01E2 203C C2MISCEN EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Enable Register
0x01E2 2040 C0RXTHRESHSTAT EMAC Control Module Interrupt Core 0 Receive Threshold Interrupt Status Register
0x01E2 2044 C0RXSTAT EMAC Control Module Interrupt Core 0 Receive Interrupt Status Register
0x01E2 2048 C0TXSTAT EMAC Control Module Interrupt Core 0 Transmit Interrupt Status Register
0x01E2 204C C0MISCSTAT EMAC Control Module Interrupt Core 0 Miscellaneous Interrupt Status Register
0x01E2 2050 C1RXTHRESHSTAT EMAC Control Module Interrupt Core 1 Receive Threshold Interrupt Status Register
0x01E2 2054 C1RXSTAT EMAC Control Module Interrupt Core 1 Receive Interrupt Status Register
0x01E2 2058 C1TXSTAT EMAC Control Module Interrupt Core 1 Transmit Interrupt Status Register
0x01E2 205C C1MISCSTAT EMAC Control Module Interrupt Core 1 Miscellaneous Interrupt Status Register
0x01E2 2060 C2RXTHRESHSTAT EMAC Control Module Interrupt Core 2 Receive Threshold Interrupt Status Register
0x01E2 2064 C2RXSTAT EMAC Control Module Interrupt Core 2 Receive Interrupt Status Register
0x01E2 2068 C2TXSTAT EMAC Control Module Interrupt Core 2 Transmit Interrupt Status Register
0x01E2 206C C2MISCSTAT EMAC Control Module Interrupt Core 2 Miscellaneous Interrupt Status Register
0x01E2 2070 C0RXIMAX EMAC Control Module Interrupt Core 0 Receive Interrupts Per Millisecond Register
0x01E2 2074 C0TXIMAX EMAC Control Module Interrupt Core 0 Transmit Interrupts Per Millisecond Register
0x01E2 2078 C1RXIMAX EMAC Control Module Interrupt Core 1 Receive Interrupts Per Millisecond Register
0x01E2 207C C1TXIMAX EMAC Control Module Interrupt Core 1 Transmit Interrupts Per Millisecond Register
0x01E2 2080 C2RXIMAX EMAC Control Module Interrupt Core 2 Receive Interrupts Per Millisecond Register
0x01E2 2084 C2TXIMAX EMAC Control Module Interrupt Core 2 Transmit Interrupts Per Millisecond Register
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RMII_MHz_50_CLK
RMII_TXEN
RMII_TXD[1:0]
RMII_RXD[1:0]
RMII_CRS_DV
RMII_RXER
1
2 3
5 5
4
6
7
8 9
10
11
TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
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Table 6-37. EMAC Control Module RAM
BYTE ADRESS REGISTER DESCRIPTION
0x01E2 0000 - 0x01E2 1FFF EMAC Local Buffer Descriptor Memory
Table 6-38. RMII Timing Requirements
No. PARAMETER MIN TYP MAX UNIT
1 tc(REFCLK) Cycle Time, RMII_MHZ_50_CLK 20 ns
2 tw(REFCLKH) Pulse Width, RMII_MHZ_50_CLK High 7 13 ns
3 tw(REFCLKL) Pulse Width, RMII_MHZ_50_CLK Low 7 13 ns
6 tsu(RXD-REFCLK) Input Setup Time, RXD Valid before RMII_MHZ_50_CLK High 4 ns
7 th(REFCLK-RXD) Input Hold Time, RXD Valid after RMII_MHZ_50_CLK High 2 ns
8 tsu(CRSDV-REFCLK) Input Setup Time, CRSDV Valid before RMII_MHZ_50_CLK High 4 ns
9 th(REFCLK-CRSDV) Input Hold Time, CRSDV Valid after RMII_MHZ_50_CLK High 2 ns
10 tsu(RXER-REFCLK) Input Setup Time, RXER Valid before RMII_MHZ_50_CLK High 4 ns
11 th(REFCLKR-RXER) Input Hold Time, RXER Valid after RMII_MHZ_50_CLK High 2 ns
Note: Per the RMII industry specification, the RMII reference clock (RMII_MHZ_50_CLK) must have jitter
tolerance of 50 ppm or less.
Table 6-39. RMII Switching Characteristics
No. PARAMETER MIN TYP MAX UNIT
4 td(REFCLK-TXD) Output Delay Time, RMII_MHZ_50_CLK High to TXD Valid 2.5 13 ns
5 td(REFCLK-TXEN) Output Delay Time, RMII_MHZ_50_CLK High to TXEN Valid 2.5 13 ns
Figure 6-30. RMII Timing Diagram
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6.15 Management Data Input/Output (MDIO)
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to
enumerate all PHY devices in the system.
The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to
interrogate and control Ethernet PHY(s) using a shared two-wire bus. Host software uses the MDIO
module to configure the auto-negotiation parameters of each PHY attached to the EMAC, retrieve the
negotiation results, and configure required parameters in the EMAC module for correct operation. The
module is designed to allow almost transparent operation of the MDIO interface, with very little
maintenance from the core processor. Only one PHY may be connected at any given time.
For more detailed information on the MDIO peripheral, see the TMS320C6745/C6747 DSP Peripherals
Overview Reference Guide. (SPRUFK9).
6.15.1 MDIO Registers
For a list of supported MDIO registers see Table 6-40 [MDIO Registers].
Table 6-40. MDIO Register Memory Map
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 4000 REV Revision Identification Register
0x01E2 4004 CONTROL MDIO Control Register
0x01E2 4008 ALIVE MDIO PHY Alive Status Register
0x01E2 400C LINK MDIO PHY Link Status Register
0x01E2 4010 LINKINTRAW MDIO Link Status Change Interrupt (Unmasked) Register
0x01E2 4014 LINKINTMASKED MDIO Link Status Change Interrupt (Masked) Register
0x01E2 4018 – Reserved
0x01E2 4020 USERINTRAW MDIO User Command Complete Interrupt (Unmasked) Register
0x01E2 4024 USERINTMASKED MDIO User Command Complete Interrupt (Masked) Register
0x01E2 4028 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register
0x01E2 402C USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register
0x01E2 4030 - 0x01E2 407C – Reserved
0x01E2 4080 USERACCESS0 MDIO User Access Register 0
0x01E2 4084 USERPHYSEL0 MDIO User PHY Select Register 0
0x01E2 4088 USERACCESS1 MDIO User Access Register 1
0x01E2 408C USERPHYSEL1 MDIO User PHY Select Register 1
0x01E2 4090 - 0x01E2 47FF – Reserved
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MDIO_CLK
MDIO_D
(output)
7
1
MDIO_CLK
MDIO_D
(input)
33
4
5
1
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6.15.2 Management Data Input/Output (MDIO) Electrical Data/Timing
Table 6-41. Timing Requirements for MDIO Input (see Figure 6-31 and Figure 6-32)
No. PARAMETER MIN MAX UNIT
1 tc(MDIO_CLK) Cycle time, MDIO_CLK 400 ns
2 tw(MDIO_CLK) Pulse duration, MDIO_CLK high/low 180 ns
3 tt(MDIO_CLK) Transition time, MDIO_CLK 5 ns
4 tsu(MDIO-MDIO_CLKH) Setup time, MDIO_D data input valid before MDIO_CLK high 10 ns
5 th(MDIO_CLKH-MDIO) Hold time, MDIO_D data input valid after MDIO_CLK high 0 ns
Figure 6-31. MDIO Input Timing
Table 6-42. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
(see Figure 6-32)
No. PARAMETER MIN MAX UNIT
7 td(MDIO_CLKL-MDIO) Delay time, MDIO_CLK low to MDIO_D data output valid 0 100 ns
Figure 6-32. MDIO Output Timing
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Receive Logic
Clock/Frame Generator
State Machine
Clock Check and
Serializer 0
Serializer 1
Serializer y
GIO
Control
DIT RAM
384 C
384 U
Optional
Transmit
Formatter
Receive
Formatter
Transmit Logic
Clock/Frame Generator
State Machine
McASPx (x = 0, 1, 2)
Peripheral
Configuration
Bus
McASP
DMA Bus
(Dedicated)
AHCLKRx
ACLKRx
AFSRx
AMUTEINx
AMUTEx
AFSXx
ACLKXx
AHCLKXx
AXRx[0]
AXRx[1]
AXRx[y]
Pins Function
Receive Master Clock
Receive Bit Clock
Receive Left/Right Clock or Frame Sync
Transmit Master Clock
Transmit Bit Clock
Transmit Left/Right Clock or Frame Sync
Transmit/Receive Serial Data Pin
Transmit/Receive Serial Data Pin
Transmit/Receive Serial Data Pin
Error Detection The McASPs DO NOT have
dedicated AMUTEINx pins.
TMS320C6745, TMS320C6747
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
6.16 Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)
The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
• Flexible clock and frame sync generation logic and on-chip dividers
• Up to sixteen transmit or receive data pins and serializers
• Large number of serial data format options, including:
– TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst)
– Time slots of 8,12,16, 20, 24, 28, and 32 bits
– First bit delay 0, 1, or 2 clocks
– MSB or LSB first bit order
– Left- or right-aligned data words within time slots
• DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers
• Extensive error checking and mute generation logic
• All unused pins GPIO-capable
Additionally, while the C674x McASP modules are backward compatible with the McASP on previous
devices; the C674x McASP includes the following new features:
• Transmit & Receive FIFO Buffers for each McASP. Allows the McASP to operate at a higher sample
rate by making it more tolerant to DMA latency.
• Dynamic Adjustment of Clock Dividers
– Clock Divider Value may be changed without resetting the McASP
The three McASPs on the C6745/6747 are configured with the following options:
Table 6-43. C6745/6747 McASP Configurations(1)
Module Serializers AFIFO DIT C6745/6747 Pins
64 Word RX AXR0[15:0], AHCLKR0, ACLKR0, AFSR0, AHCLKX0, ACLKX0,
McASP0 16 N
64 Word TX AFSX0, AMUTE0
64 Word RX AXR1[11:10], AXR1[8:0], AHCLKR1, ACLKR1, AFSR1, AHCLKX1,
McASP1 12 N
64 Word TX ACLKX1, AFSX1, AMUTE1
16 Word RX AXR2[3:0], AHCLKR2, ACLKR2, AFSR2, AHCLKX2, ACLKX2,
McASP2 4 Y
16 Word TX AFSX2, AMUTE2
(1) Pins available are the maximum number of pins that may be configured for a particular McASP; not including pin multiplexing.
Figure 6-33. McASP Block Diagram
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6.16.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 6-44. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 6-45
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-46. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port.
Table 6-44. McASP Registers Accessed Through Peripheral Configuration Port
McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION
BYTE BYTE BYTE
ADDRESS ADDRESS ADDRESS
0x01D0 0000 0x01D0 4000 0x01D0 8000 REV Revision identification register
0x01D0 0010 0x01D0 4010 0x01D0 8010 PFUNC Pin function register
0x01D0 0014 0x01D0 4014 0x01D0 8014 PDIR Pin direction register
0x01D0 0018 0x01D0 4018 0x01D0 8018 PDOUT Pin data output register
0x01D0 001C 0x01D0 401C 0x01D0 801C PDIN Read returns: Pin data input register
0x01D0 001C 0x01D0 401C 0x01D0 801C PDSET Writes affect: Pin data set register
(alternate write address: PDOUT)
0x01D0 0020 0x01D0 4020 0x01D0 8020 PDCLR Pin data clear register (alternate write address: PDOUT)
0x01D0 0044 0x01D0 4044 0x01D0 8044 GBLCTL Global control register
0x01D0 0048 0x01D0 4048 0x01D0 8048 AMUTE Audio mute control register
0x01D0 004C 0x01D0 404C 0x01D0 804C DLBCTL Digital loopback control register
0x01D0 0050 0x01D0 4050 0x01D0 8050 DITCTL DIT mode control register
0x01D0 0060 0x01D0 4060 0x01D0 8060 RGBLCTL Receiver global control register: Alias of GBLCTL, only receive bits
are affected - allows receiver to be reset independently from
transmitter
0x01D0 0064 0x01D0 4064 0x01D0 8064 RMASK Receive format unit bit mask register
0x01D0 0068 0x01D0 4068 0x01D0 8068 RFMT Receive bit stream format register
0x01D0 006C 0x01D0 406C 0x01D0 806C AFSRCTL Receive frame sync control register
0x01D0 0070 0x01D0 4070 0x01D0 8070 ACLKRCTL Receive clock control register
0x01D0 0074 0x01D0 4074 0x01D0 8074 AHCLKRCTL Receive high-frequency clock control register
0x01D0 0078 0x01D0 4078 0x01D0 8078 RTDM Receive TDM time slot 0-31 register
0x01D0 007C 0x01D0 407C 0x01D0 807C RINTCTL Receiver interrupt control register
0x01D0 0080 0x01D0 4080 0x01D0 8080 RSTAT Receiver status register
0x01D0 0084 0x01D0 4084 0x01D0 8084 RSLOT Current receive TDM time slot register
0x01D0 0088 0x01D0 4088 0x01D0 8088 RCLKCHK Receive clock check control register
0x01D0 008C 0x01D0 408C 0x01D0 808C REVTCTL Receiver DMA event control register
0x01D0 00A0 0x01D0 40A0 0x01D0 80A0 XGBLCTL Transmitter global control register. Alias of GBLCTL, only transmit
bits are affected - allows transmitter to be reset independently from
receiver
0x01D0 00A4 0x01D0 40A4 0x01D0 80A4 XMASK Transmit format unit bit mask register
0x01D0 00A8 0x01D0 40A8 0x01D0 80A8 XFMT Transmit bit stream format register
0x01D0 00AC 0x01D0 40AC 0x01D0 80AC AFSXCTL Transmit frame sync control register
0x01D0 00B0 0x01D0 40B0 0x01D0 80B0 ACLKXCTL Transmit clock control register
0x01D0 00B4 0x01D0 40B4 0x01D0 80B4 AHCLKXCTL Transmit high-frequency clock control register
0x01D0 00B8 0x01D0 40B8 0x01D0 80B8 XTDM Transmit TDM time slot 0-31 register
0x01D0 00BC 0x01D0 40BC 0x01D0 80BC XINTCTL Transmitter interrupt control register
0x01D0 00C0 0x01D0 40C0 0x01D0 80C0 XSTAT Transmitter status register
0x01D0 00C4 0x01D0 40C4 0x01D0 80C4 XSLOT Current transmit TDM time slot register
0x01D0 00C8 0x01D0 40C8 0x01D0 80C8 XCLKCHK Transmit clock check control register
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Table 6-44. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION
BYTE BYTE BYTE
ADDRESS ADDRESS ADDRESS
0x01D0 00CC 0x01D0 40CC 0x01D0 80CC XEVTCTL Transmitter DMA event control register
0x01D0 0100 0x01D0 4100 0x01D0 8100 DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0
0x01D0 0104 0x01D0 4104 0x01D0 8104 DITCSRA1 Left (even TDM time slot) channel status register (DIT mode) 1
0x01D0 0108 0x01D0 4108 0x01D0 8108 DITCSRA2 Left (even TDM time slot) channel status register (DIT mode) 2
0x01D0 010C 0x01D0 410C 0x01D0 810C DITCSRA3 Left (even TDM time slot) channel status register (DIT mode) 3
0x01D0 0110 0x01D0 4110 0x01D0 8110 DITCSRA4 Left (even TDM time slot) channel status register (DIT mode) 4
0x01D0 0114 0x01D0 4114 0x01D0 8114 DITCSRA5 Left (even TDM time slot) channel status register (DIT mode) 5
0x01D0 0118 0x01D0 4118 0x01D0 8118 DITCSRB0 Right (odd TDM time slot) channel status register (DIT mode) 0
0x01D0 011C 0x01D0 411C 0x01D0 811C DITCSRB1 Right (odd TDM time slot) channel status register (DIT mode) 1
0x01D0 0120 0x01D0 4120 0x01D0 8120 DITCSRB2 Right (odd TDM time slot) channel status register (DIT mode) 2
0x01D0 0124 0x01D0 4124 0x01D0 8124 DITCSRB3 Right (odd TDM time slot) channel status register (DIT mode) 3
0x01D0 0128 0x01D0 4128 0x01D0 8128 DITCSRB4 Right (odd TDM time slot) channel status register (DIT mode) 4
0x01D0 012C 0x01D0 412C 0x01D0 812C DITCSRB5 Right (odd TDM time slot) channel status register (DIT mode) 5
0x01D0 0130 0x01D0 4130 0x01D0 8130 DITUDRA0 Left (even TDM time slot) channel user data register (DIT mode) 0
0x01D0 0134 0x01D0 4134 0x01D0 8134 DITUDRA1 Left (even TDM time slot) channel user data register (DIT mode) 1
0x01D0 0138 0x01D0 4138 0x01D0 8138 DITUDRA2 Left (even TDM time slot) channel user data register (DIT mode) 2
0x01D0 013C 0x01D0 413C 0x01D0 813C DITUDRA3 Left (even TDM time slot) channel user data register (DIT mode) 3
0x01D0 0140 0x01D0 4140 0x01D0 8140 DITUDRA4 Left (even TDM time slot) channel user data register (DIT mode) 4
0x01D0 0144 0x01D0 4144 0x01D0 8144 DITUDRA5 Left (even TDM time slot) channel user data register (DIT mode) 5
0x01D0 0148 0x01D0 4148 0x01D0 8148 DITUDRB0 Right (odd TDM time slot) channel user data register (DIT mode) 0
0x01D0 014C 0x01D0 414C 0x01D0 814C DITUDRB1 Right (odd TDM time slot) channel user data register (DIT mode) 1
0x01D0 0150 0x01D0 4150 0x01D0 8150 DITUDRB2 Right (odd TDM time slot) channel user data register (DIT mode) 2
0x01D0 0154 0x01D0 4154 0x01D0 8154 DITUDRB3 Right (odd TDM time slot) channel user data register (DIT mode) 3
0x01D0 0158 0x01D0 4158 0x01D0 8158 DITUDRB4 Right (odd TDM time slot) channel user data register (DIT mode) 4
0x01D0 015C 0x01D0 415C 0x01D0 815C DITUDRB5 Right (odd TDM time slot) channel user data register (DIT mode) 5
0x01D0 0180 0x01D0 4180 0x01D0 8180 SRCTL0 Serializer control register 0
0x01D0 0184 0x01D0 4184 0x01D0 8184 SRCTL1 Serializer control register 1
0x01D0 0188 0x01D0 4188 0x01D0 8188 SRCTL2 Serializer control register 2
0x01D0 018C 0x01D0 418C 0x01D0 818C SRCTL3 Serializer control register 3
0x01D0 0190 0x01D0 4190 0x01D0 8190 SRCTL4 Serializer control register 4
0x01D0 0194 0x01D0 4194 0x01D0 8194 SRCTL5 Serializer control register 5
0x01D0 0198 0x01D0 4198 0x01D0 8198 SRCTL6 Serializer control register 6
0x01D0 019C 0x01D0 419C 0x01D0 819C SRCTL7 Serializer control register 7
0x01D0 01A0 0x01D0 41A0 0x01D0 81A0 SRCTL8 Serializer control register 8
0x01D0 01A4 0x01D0 41A4 0x01D0 81A4 SRCTL9 Serializer control register 9
0x01D0 01A8 0x01D0 41A8 0x01D0 81A8 SRCTL10 Serializer control register 10
0x01D0 01AC 0x01D0 41AC 0x01D0 81AC SRCTL11 Serializer control register 11
0x01D0 01B0 0x01D0 41B0 0x01D0 81B0 SRCTL12 Serializer control register 12
0x01D0 01B4 0x01D0 41B4 0x01D0 81B4 SRCTL13 Serializer control register 13
0x01D0 01B8 0x01D0 41B8 0x01D0 81B8 SRCTL14 Serializer control register 14
0x01D0 01BC 0x01D0 41BC 0x01D0 81BC SRCTL15 Serializer control register 15
0x01D0 0200 0x01D0 4200 0x01D0 8200 XBUF0(1) Transmit buffer register for serializer 0
0x01D0 0204 0x01D0 4204 0x01D0 8204 XBUF1(1) Transmit buffer register for serializer 1
0x01D0 0208 0x01D0 4208 0x01D0 8208 XBUF2(1) Transmit buffer register for serializer 2
0x01D0 020C 0x01D0 420C 0x01D0 820C XBUF3(1) Transmit buffer register for serializer 3
(1) Writes to XRBUF originate from peripheral configuration port only when XBUSEL = 1 in XFMT.
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Table 6-44. McASP Registers Accessed Through Peripheral Configuration Port (continued)
McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION
BYTE BYTE BYTE
ADDRESS ADDRESS ADDRESS
0x01D0 0210 0x01D0 4210 0x01D0 8210 XBUF4(1) Transmit buffer register for serializer 4
0x01D0 0214 0x01D0 4214 0x01D0 8214 XBUF5(1) Transmit buffer register for serializer 5
0x01D0 0218 0x01D0 4218 0x01D0 8218 XBUF6(1) Transmit buffer register for serializer 6
0x01D0 021C 0x01D0 421C 0x01D0 821C XBUF7(1) Transmit buffer register for serializer 7
0x01D0 0220 0x01D0 4220 0x01D0 8220 XBUF8(1) Transmit buffer register for serializer 8
0x01D0 0224 0x01D0 4224 0x01D0 8224 XBUF9(1) Transmit buffer register for serializer 9
0x01D0 0228 0x01D0 4228 0x01D0 8228 XBUF10(1) Transmit buffer register for serializer 10
0x01D0 022C 0x01D0 422C 0x01D0 822C XBUF11(1) Transmit buffer register for serializer 11
0x01D0 0230 0x01D0 4230 0x01D0 8230 XBUF12(1) Transmit buffer register for serializer 12
0x01D0 0234 0x01D0 4234 0x01D0 8234 XBUF13(1) Transmit buffer register for serializer 13
0x01D0 0238 0x01D0 4238 0x01D0 8238 XBUF14(1) Transmit buffer register for serializer 14
0x01D0 023C 0x01D0 423C 0x01D0 823C XBUF15(1) Transmit buffer register for serializer 15
0x01D0 0280 0x01D0 4280 0x01D0 8280 RBUF0(2) Receive buffer register for serializer 0
0x01D0 0284 0x01D0 4284 0x01D0 8284 RBUF1(2) Receive buffer register for serializer 1
0x01D0 0288 0x01D0 4288 0x01D0 8288 RBUF2(3) Receive buffer register for serializer 2
0x01D0 028C 0x01D0 428C 0x01D0 828C RBUF3(3) Receive buffer register for serializer 3
0x01D0 0290 0x01D0 4290 0x01D0 8290 RBUF4(3) Receive buffer register for serializer 4
0x01D0 0294 0x01D0 4294 0x01D0 8294 RBUF5(3) Receive buffer register for serializer 5
0x01D0 0298 0x01D0 4298 0x01D0 8298 RBUF6(3) Receive buffer register for serializer 6
0x01D0 029C 0x01D0 429C 0x01D0 829C RBUF7(3) Receive buffer register for serializer 7
0x01D0 02A0 0x01D0 42A0 0x01D0 82A0 RBUF8(3) Receive buffer register for serializer 8
0x01D0 02A4 0x01D0 42A4 0x01D0 82A4 RBUF9(3) Receive buffer register for serializer 9
0x01D0 02A8 0x01D0 42A8 0x01D0 82A8 RBUF10(3) Receive buffer register for serializer 10
0x01D0 02AC 0x01D0 42AC 0x01D0 82AC RBUF11(3) Receive buffer register for serializer 11
0x01D0 02B0 0x01D0 42B0 0x01D0 82B0 RBUF12(3) Receive buffer register for serializer 12
0x01D0 02B4 0x01D0 42B4 0x01D0 82B4 RBUF13(3) Receive buffer register for serializer 13
0x01D0 02B8 0x01D0 42B8 0x01D0 82BB RBUF14(3) Receive buffer register for serializer 14
0x01D0 02BC 0x01D0 42BC 0x01D0 82BC RBUF15(3) Receive buffer register for serializer 15
(2) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
(3) Reads from XRBUF originate on peripheral configuration port only when RBUSEL = 1 in RFMT.
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Table 6-45. McASP Registers Accessed Through DMA Port
Hex Register McASP0 McASP1 McASP2 REGISTER DESCRIPTION
Address Name BYTE BYTE BYTE
ADDRESS ADDRESS ADDRESS
Read RBUF 01D0 2000 01D0 6000 01D0 A000 Receive buffer DMA port address. Cycles through receive serializers,
Accesses skipping over transmit serializers and inactive serializers. Starts at the
lowest serializer at the beginning of each time slot. Reads from DMA port
only if RBUSEL = 0 in RFMT.
Write XBUF 01D0 2000 01D0 6000 01D0 A000 Transmit buffer DMA port address. Cycles through transmit serializers,
Accesses skipping over receive and inactive serializers. Starts at the lowest
serializer at the beginning of each time slot. Writes to DMA port only if
XBUSEL = 0 in XFMT.
Table 6-46. McASP AFIFO Registers Accessed Through Peripheral Configuration Port
McASP0 McASP1 McASP2 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS
0x01D0 1000 0x01D0 5000 0x01D0 9000 AFIFOREV AFIFO revision identification register
0x01D0 1010 0x01D0 5010 0x01D0 9010 WFIFOCTL Write FIFO control register
0x01D0 1014 0x01D0 5014 0x01D0 9014 WFIFOSTS Write FIFO status register
0x01D0 1018 0x01D0 5018 0x01D0 9018 RFIFOCTL Read FIFO control register
0x01D0 101C 0x01D0 501C 0x01D0 901C RFIFOSTS Read FIFO status register
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6.16.2 McASP Electrical Data/Timing
6.16.2.1 Multichannel Audio Serial Port 0 (McASP0) Timing
Table 6-47 and Table 6-48 assume testing over recommended operating conditions (see Figure 6-34 and
Figure 6-35).
Table 6-47. McASP0 Timing Requirements(1) (2)
No. PARAMATER MIN MAX UNIT
Cycle time, AHCLKR0 external, AHCLKR0 input 25
1 tc(AHCLKRX) ns
Cycle time, AHCLKX0 external, AHCLKX0 input 25
Pulse duration, AHCLKR0 external, AHCLKR0 input 12.5
2 tw(AHCLKRX) ns
Pulse duration, AHCLKX0 external, AHCLKX0 input 12.5
Cycle time, ACLKR0 external, ACLKR0 input greater of 2P or 25
3 tc(ACLKRX) ns
Cycle time, ACLKX0 external, ACLKX0 input greater of 2P or 25
Pulse duration, ACLKR0 external, ACLKR0 input 12.5
4 tw(ACLKRX) ns
Pulse duration, ACLKX0 external, ACLKX0 input 12.5
Setup time, AFSR0 input to ACLKR0 internal(3) 9.4
Setup time, AFSX0 input to ACLKX0 internal 9.4
Setup time, AFSR0 input to ACLKR0 external input(3) 2.9
5 tsu(AFSRX-ACLKRX) ns
Setup time, AFSX0 input to ACLKX0 external input 2.9
Setup time, AFSR0 input to ACLKR0 external output(3) 2.9
Setup time, AFSX0 input to ACLKX0 external output 2.9
Hold time, AFSR0 input after ACLKR0 internal(3) -1.2
Hold time, AFSX0 input after ACLKX0 internal -1.2
Hold time, AFSR0 input after ACLKR0 external input(3) 0.9
6 th(ACLKRX-AFSRX) ns
Hold time, AFSX0 input after ACLKX0 external input 0.9
Hold time, AFSR0 input after ACLKR0 external output(3) 0.9
Hold time, AFSX0 input after ACLKX0 external output 0.9
Setup time, AXR0[n] input to ACLKR0 internal(3) 9.4
Setup time, AXR0[n] input to ACLKX0 internal(4) 9.4
Setup time, AXR0[n] input to ACLKR0 external input(3) 2.9
7 tsu(AXR-ACLKRX) ns
Setup time, AXR0[n] input to ACLKX0 external input(4) 2.9
Setup time, AXR0[n] input to ACLKR0 external output(3) 2.9
Setup time, AXR0[n] input to ACLKX0 external output(4) 2.9
Hold time, AXR0[n] input after ACLKR0 internal(3) -1.3
Hold time, AXR0[n] input after ACLKX0 internal(4) -1.3
Hold time, AXR0[n] input after ACLKR0 external input(3) 0.5
8 th(ACLKRX-AXR) ns
Hold time, AXR0[n] input after ACLKX0 external input(4) 0.5
Hold time, AXR0[n] input after ACLKR0 external output(3) 0.5
Hold time, AXR0[n] input after ACLKX0 external output(4) 0.5
(1) ACLKX0 internal – McASP0 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
(4) McASP0 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX0
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Table 6-48. McASP0 Switching Characteristics(1)
No. PARAMETER MIN MAX UNIT
Cycle time, AHCLKR0 internal, AHCLKR0 output 25
Cycle time, AHCLKR0 external, AHCLKR0 output 25
9 tc(AHCLKRX) ns
Cycle time, AHCLKX0 internal, AHCLKX0 output 25
Cycle time, AHCLKX0 external, AHCLKX0 output 25
Pulse duration, AHCLKR0 internal, AHCLKR0 output (AHR/2) – 2.5(2)
Pulse duration, AHCLKR0 external, AHCLKR0 output (AHR/2) – 2.5(2)
10 tw(AHCLKRX) ns
Pulse duration, AHCLKX0 internal, AHCLKX0 output (AHX/2) – 2.5(3)
Pulse duration, AHCLKX0 external, AHCLKX0 output (AHX/2) – 2.5(3)
Cycle time, ACLKR0 internal, ACLKR0 output greater of 2P or 25(4)
Cycle time, ACLKR0 external, ACLKR0 output greater of 2P or 25(4)
11 tc(ACLKRX) ns
Cycle time, ACLKX0 internal, ACLKX0 output greater of 2P or 25(4)
Cycle time, ACLKX0 external, ACLKX0 output greater of 2P or 25(4)
Pulse duration, ACLKR0 internal, ACLKR0 output (AR/2) – 2.5(5)
Pulse duration, ACLKR0 external, ACLKR0 output (AR/2) – 2.5(5)
12 tw(ACLKRX) ns
Pulse duration, ACLKX0 internal, ACLKX0 output (AX/2) – 2.5(6)
Pulse duration, ACLKX0 external, ACLKX0 output (AX/2) – 2.5(6)
Delay time, ACLKR0 internal, AFSR output(7) 0 5.8
Delay time, ACLKX0 internal, AFSX output 0 5.8
Delay time, ACLKR0 external input, AFSR output(7) 2.5 11.6
13 td(ACLKRX-AFSRX) ns
Delay time, ACLKX0 external input, AFSX output 2.5 11.6
Delay time, ACLKR0 external output, AFSR output(7) 2.5 11.6
Delay time, ACLKX0 external output, AFSX output 2.5 11.6
Delay time, ACLKX0 internal, AXR0[n] output 0 5.8
14 td(ACLKX-AXRV) Delay time, ACLKX0 external input, AXR0[n] output 2.5 11.6 ns
Delay time, ACLKX0 external output, AXR0[n] output 2.5 11.6
Disable time, ACLKX0 internal, AXR0[n] output 0 5.8
15 tdis(ACLKX-AXRHZ) Disable time, ACLKX0 external input, AXR0[n] output 3 11.6 ns
Disable time, ACLKX0 external output, AXR0[n] output 3 11.6
(1) McASP0 ACLKX0 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX0 external input – McASP0 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX0 external output – McASP0ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR0 internal – McASP0 ACLKR0CTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR0 external input – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR0 external output – McASP0 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR0.
(3) AHX - Cycle time, AHCLKX0.
(4) P = SYSCLK2 period
(5) AR - ACLKR0 period.
(6) AX - ACLKX0 period.
(7) McASP0 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR0
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6.16.2.2 Multichannel Audio Serial Port 1 (McASP1) Timing
Table 6-49 and Table 6-50 assume testing over recommended operating conditions (see Figure 6-34 and
Figure 6-35).
Table 6-49. McASP1 Timing Requirements(1) (2)
No. PARAMATER MIN MAX UNIT
Cycle time, AHCLKR1 external, AHCLKR1 input 25
1 tc(AHCLKRX) ns
Cycle time, AHCLKX1 external, AHCLKX1 input 25
Pulse duration, AHCLKR1 external, AHCLKR1 input 12.5
2 tw(AHCLKRX) ns
Pulse duration, AHCLKX1 external, AHCLKX1 input 12.5
Cycle time, ACLKR1 external, ACLKR1 input greater of 2P or 25
3 tc(ACLKRX) ns
Cycle time, ACLKX1 external, ACLKX1 input greater of 2P or 25
Pulse duration, ACLKR1 external, ACLKR1 input 12.5
4 tw(ACLKRX) ns
Pulse duration, ACLKX1 external, ACLKX1 input 12.5
Setup time, AFSR1 input to ACLKR1 internal(3) 10.4
Setup time, AFSX1 input to ACLKX1 internal 10.4
Setup time, AFSR1 input to ACLKR1 external input(3) 2.6
5 tsu(AFSRX-ACLKRX) ns
Setup time, AFSX1 input to ACLKX1 external input 2.6
Setup time, AFSR1 input to ACLKR1 external output(3) 2.6
Setup time, AFSX1 input to ACLKX1 external output 2.6
Hold time, AFSR1 input after ACLKR1 internal(3) -1.9
Hold time, AFSX1 input after ACLKX1 internal -1.9
Hold time, AFSR1 input after ACLKR1 external input(3) 0.7
6 th(ACLKRX-AFSRX) ns
Hold time, AFSX1 input after ACLKX1 external input 0.7
Hold time, AFSR1 input after ACLKR1 external output(3) 0.7
Hold time, AFSX1 input after ACLKX1 external output 0.7
Setup time, AXR1[n] input to ACLKR1 internal(3) 10.4
Setup time, AXR1[n] input to ACLKX1 internal(4) 10.4
Setup time, AXR1[n] input to ACLKR1 external input(3) 2.6
7 tsu(AXR-ACLKRX) ns
Setup time, AXR1[n] input to ACLKX1 external input(4) 2.6
Setup time, AXR1[n] input to ACLKR1 external output(3) 2.6
Setup time, AXR1[n] input to ACLKX1 external output(4) 2.6
Hold time, AXR1[n] input after ACLKR1 internal(3) -1.8
Hold time, AXR1[n] input after ACLKX1 internal(4) -1.8
Hold time, AXR1[n] input after ACLKR1 external input(3) 0.5
8 th(ACLKRX-AXR) ns
Hold time, AXR1[n] input after ACLKX1 external input(4) 0.5
Hold time, AXR1[n] input after ACLKR1 external output(3) 0.5
Hold time, AXR1[n] input after ACLKX1 external output(4) 0.5
(1) ACLKX1 internal – McASP1 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX1 external input – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX1 external output – McASP1 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR1 internal – McASP1 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR1 external input – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR1 external output – McASP1 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(4) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
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Table 6-50. McASP1 Switching Characteristics(1)
NO. PARAMETER MIN MAX UNIT
Cycle time, AHCLKR1 internal, AHCLKR1 output 25
Cycle time, AHCLKR1 external, AHCLKR1 output 25
9 tc(AHCLKRX) ns
Cycle time, AHCLKX1 internal, AHCLKX1 output 25
Cycle time, AHCLKX1 external, AHCLKX1 output 25
Pulse duration, AHCLKR1 internal, AHCLKR1 output (AHR/2) – 2.5(2)
Pulse duration, AHCLKR1 external, AHCLKR1 output (AHR/2) – 2.5(2)
10 tw(AHCLKRX) ns
Pulse duration, AHCLKX1 internal, AHCLKX1 output (AHX/2) – 2.5(3)
Pulse duration, AHCLKX1 external, AHCLKX1 output (AHX/2) – 2.5(3)
Cycle time, ACLKR1 internal, ACLKR1 output greater of 2P or 25(4)
Cycle time, ACLKR1 external, ACLKR1 output greater of 2P or 25(4)
11 tc(ACLKRX) ns
Cycle time, ACLKX1 internal, ACLKX1 output greater of 2P or 25(4)
Cycle time, ACLKX1 external, ACLKX1 output greater of 2P or 25(4)
Pulse duration, ACLKR1 internal, ACLKR1 output (AR/2) – 2.5(5)
Pulse duration, ACLKR1 external, ACLKR1 output (AR/2) – 2.5(5)
12 tw(ACLKRX) ns
Pulse duration, ACLKX1 internal, ACLKX1 output (AX/2) – 2.5(6)
Pulse duration, ACLKX1 external, ACLKX1 output (AX/2) – 2.5(6)
Delay time, ACLKR1 internal, AFSR output(7) 0.5 6.7
Delay time, ACLKX1 internal, AFSX output 0.5 6.7
Delay time, ACLKR1 external input, AFSR output(7) 3.4 13.8
13 td(ACLKRX-AFSRX) ns
Delay time, ACLKX1 external input, AFSX output 3.4 13.8
Delay time, ACLKR1 external output, AFSR output(7) 3.4 13.8
Delay time, ACLKX1 external output, AFSX output 3.4 13.8
Delay time, ACLKX1 internal, AXR1[n] output 0.5 6.7
14 td(ACLKX-AXRV) Delay time, ACLKX1 external input, AXR1[n] output 3.4 13.8 ns
Delay time, ACLKX1 external output, AXR1[n] output 3.4 13.8
Disable time, ACLKX1 internal, AXR1[n] output 0.5 6.7
15 tdis(ACLKX-AXRHZ) Disable time, ACLKX1 external input, AXR1[n] output 3.9 13.8 ns
Disable time, ACLKX1 external output, AXR1[n] output 3.9 13.8
(1) McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR1.
(3) AHX - Cycle time, AHCLKX1.
(4) P = SYSCLK2 period
(5) AR - ACLKR1 period.
(6) AX - ACLKX1 period.
(7) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
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6.16.2.3 Multichannel Audio Serial Port 2 (McASP2) Timing
Table 6-51 and Table 6-52 assume testing over recommended operating conditions (see Figure 6-34 and
Figure 6-35).
Table 6-51. McASP2 Timing Requirements(1) (2)
NO. MIN MAX UNIT
Cycle time, AHCLKR2 external, AHCLKR2 input 15
1 tc(AHCLKRX) ns
Cycle time, AHCLKX2 external, AHCLKX2 input 15
Pulse duration, AHCLKR2 external, AHCLKR2 input 7.5
2 tw(AHCLKRX) ns
Pulse duration, AHCLKX2 external, AHCLKX2 input 7.5
Cycle time, ACLKR2 external, ACLKR2 input greater of 2P or 15
3 tc(ACLKRX) ns
Cycle time, ACLKX2 external, ACLKX2 input greater of 2P or 15
Pulse duration, ACLKR2 external, ACLKR2 input 7.5
4 tw(ACLKRX) ns
Pulse duration, ACLKX2 external, ACLKX2 input 7.5
Setup time, AFSR2 input to ACLKR2 internal(3) 10
Setup time, AFSX2 input to ACLKX2 internal 10
Setup time, AFSR2 input to ACLKR2 external input(3) 1.6
5 tsu(AFSRX-ACLKRX) ns
Setup time, AFSX2 input to ACLKX2 external input 1.6
Setup time, AFSR2 input to ACLKR2 external output(3) 1.6
Setup time, AFSX2 input to ACLKX2 external output 1.6
Hold time, AFSR2 input after ACLKR2 internal(3) -1.7
Hold time, AFSX2 input after ACLKX2 internal -1.7
Hold time, AFSR2 input after ACLKR2 external input(3) 1.3
6 th(ACLKRX-AFSRX) ns
Hold time, AFSX2 input after ACLKX2 external input 1.3
Hold time, AFSR2 input after ACLKR2 external output(3) 1.3
Hold time, AFSX2 input after ACLKX2 external output 1.3
Setup time, AXR2[n] input to ACLKR2 internal(3) 10
Setup time, AXR2[n] input to ACLKX2 internal(4) 10
Setup time, AXR2[n] input to ACLKR2 external input(3) 1.6
7 tsu(AXR-ACLKRX) ns
Setup time, AXR2[n] input to ACLKX2 external input(4) 1.6
Setup time, AXR2[n] input to ACLKR2 external output(3) 1.6
Setup time, AXR2[n] input to ACLKX2 external output(4) 1.6
Hold time, AXR2[n] input after ACLKR2 internal(3) -1.7
Hold time, AXR2[n] input after ACLKX2 internal(4) -1.7
Hold time, AXR2[n] input after ACLKR2 external input(3) 1.3
8 th(ACLKRX-AXR) ns
Hold time, AXR2[n] input after ACLKX2 external input(4) 1.3
Hold time, AXR2[n] input after ACLKR2 external output(3) 1.3
Hold time, AXR2[n] input after ACLKX2 external output(4) 1.3
(1) ACLKX2 internal – McASP2 ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
ACLKX2 external input – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
ACLKX2 external output – McASP2 ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
ACLKR2 internal – McASP2 ACLKRCTL.CLKRM = 1, PDIR.ACLKR =1
ACLKR2 external input – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
ACLKR2 external output – McASP2 ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) P = SYSCLK2 period
(3) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
(4) McASP2 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX2
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Table 6-52. McASP2 Switching Characteristics(1)
NO. PARAMETER MIN MAX UNIT
Cycle time, AHCLKR2 internal, AHCLKR2 output 15
Cycle time, AHCLKR2 external, AHCLKR2 output 15
9 tc(AHCLKRX) ns
Cycle time, AHCLKX2 internal, AHCLKX2 output 15
Cycle time, AHCLKX2 external, AHCLKX2 output 15
Pulse duration, AHCLKR2 internal, AHCLKR2 output (AHR/2) – 2.5(2)
Pulse duration, AHCLKR2 external, AHCLKR2 output (AHR/2) – 2.5(2)
10 tw(AHCLKRX) ns
Pulse duration, AHCLKX2 internal, AHCLKX2 output (AHX/2) – 2.5(3)
Pulse duration, AHCLKX2 external, AHCLKX2 output (AHX/2) – 2.5(3)
Cycle time, ACLKR2 internal, ACLKR2 output greater of 2P or 15(4)
Cycle time, ACLKR2 external, ACLKR2 output greater of 2P or 15(4)
11 tc(ACLKRX) ns
Cycle time, ACLKX2 internal, ACLKX2 output greater of 2P or 15(4)
Cycle time, ACLKX2 external, ACLKX2 output greater of 2P or 15(4)
Pulse duration, ACLKR2 internal, ACLKR2 output (AR/2) – 2.5(5)
Pulse duration, ACLKR2 external, ACLKR2 output (AR/2) – 2.5(5)
12 tw(ACLKRX) ns
Pulse duration, ACLKX2 internal, ACLKX2 output (AX/2) – 2.5(6)
Pulse duration, ACLKX2 external, ACLKX2 output (AX/2) – 2.5(6)
Delay time, ACLKR2 internal, AFSR output(7) -1.4 2.8
Delay time, ACLKX2 internal, AFSX output -1.4 2.8
Delay time, ACLKR2 external input, AFSR output(7) 2.1 10
13 td(ACLKRX-AFSRX) ns
Delay time, ACLKX2 external input, AFSX output 2.1 10
Delay time, ACLKR2 external output, AFSR output(7) 2.1 10
Delay time, ACLKX2 external output, AFSX output 2.1 10
Delay time, ACLKX2 internal, AXR2[n] output -1.4 2.8
14 td(ACLKX-AXRV) Delay time, ACLKX2 external input, AXR2[n] output 2.1 10 ns
Delay time, ACLKX2 external output, AXR2[n] output 2.1 10
Disable time, ACLKX2 internal, AXR2[n] output -1.4 2.8
15 tdis(ACLKX-AXRHZ) Disable time, ACLKX2 external input, AXR2[n] output 2.9 10 ns
Disable time, ACLKX2 external output, AXR2[n] output 2.9 10
(1) McASP2 ACLKX2 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP2 ACLKX2 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP2 ACLKX2 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP2 ACLKR2 internal – ACLKR2CTL.CLKRM = 1, PDIR.ACLKR =1
McASP2 ACLKR2 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP2 ACLKR2 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR2.
(3) AHX - Cycle time, AHCLKX2.
(4) P = SYSCLK2 period
(5) AR - ACLKR2 period.
(6) AX - ACLKX2 period.
(7) McASP2 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR2
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8
7
4
4
3
2
21
A0 A1 B0 B1A30 A31 B30 B31 C0 C1 C2 C3 C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data In/Receive)
6
5
ACLKR/X (CLKRP = CLKXP = 0)(A)
ACLKR/X (CLKRP = CLKXP = 1)(B)
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A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
Figure 6-34. McASP Input Timings
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15
14
13
13
13
13
13
13
13
12
12
11
10
10
9
A0 A1 B0 B1A30 A31 B30 B31 C0 C1 C2 C3 C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
ACLKR/X (CLKRP = CLKXP = 0)(B)
ACLKR/X (CLKRP = CLKXP = 1)(A)
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A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
Figure 6-35. McASP Output Timings
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Peripheral
Configuration Bus
Interrupt and
DMA Requests
16-Bit Shift Register
16-Bit Buffer
GPIO
Control
(all pins)
State
Machine
Clock
Control
SPIx_SIMO
SPIx_SOMI
SPIx_ENA
SPIx_SCS
SPIx_CLK
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6.17 Serial Peripheral Interface Ports (SPI0, SPI1)
Figure 6-36 is a block diagram of the SPI module, which is a simple shift register and buffer plus control
logic. Data is written to the shift register before transmission occurs and is read from the buffer at the end
of transmission. The SPI can operate either as a master, in which case, it initiates a transfer and drives
the SPIx_CLK pin, or as a slave. Four clock phase and polarity options are supported as well as many
data formatting options.
Figure 6-36. Block Diagram of SPI Module
The SPI supports 3-, 4-, and 5-pin operation with three basic pins (SPIx_CLK, SPIx_SIMO, and
SPIx_SOMI) and two optional pins (SPIx_SCS, SPIx_ENA).
The optional SPIx_SCS (Slave Chip Select) pin is most useful to enable in slave mode when there are
other slave devices on the same SPI port. The C6745/6747 will only shift data and drive the SPIx_SOMI
pin when SPIx_SCS is held low.
In slave mode, SPIx_ENA is an optional output. The SPIx_ENA output provides the status of the internal
transmit buffer (SPIDAT0/1 registers). In four-pin mode with the enable option, SPIx_ENA is asserted only
when the transmit buffer is full, indicating that the slave is ready to begin another transfer. In five-pin
mode, the SPIx_ENA is additionally qualified by SPIx_SCS being asserted. This allows a single
handshake line to be shared by multiple slaves on the same SPI bus.
In master mode, the SPIx_ENA pin is an optional input and the master can be configured to delay the start
of the next transfer until the slave asserts SPIx_ENA. The addition of this handshake signal simplifies SPI
communications and, on average, increases SPI bus throughput since the master does not need to delay
each transfer long enough to allow for the worst-case latency of the slave device. Instead, each transfer
can begin as soon as both the master and slave have actually serviced the previous SPI transfer.
Although the SPI module supports two interrupt outputs, SPIx_INT1 is the only interrupt connected on this
device.
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Optional − Slave Chip Select
Optional Enable (Ready)
SLAVE SPIMASTER SPI
SPIx_SIMOSPIx_SIMO
SPIx_SOMI SPIx_SOMI
SPIx_CLK SPIx_CLK
SPIx_ENA SPIx_ENA
SPIx_SCS SPIx_SCS
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Figure 6-37. Illustration of SPI Master-to-SPI Slave Connection
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6.17.1 SPI Peripheral Registers Description(s)
Table 6-53 is a list of the SPI registers.
Table 6-53. SPIx Configuration Registers
SPI0 SPI1 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS
0x01C4 1000 0x01E1 2000 SPIGCR0 Global Control Register 0
0x01C4 1004 0x01E1 2004 SPIGCR1 Global Control Register 1
0x01C4 1008 0x01E1 2008 SPIINT0 Interrupt Register
0x01C4 100C 0x01E1 200C SPILVL Interrupt Level Register
0x01C4 1010 0x01E1 2010 SPIFLG Flag Register
0x01C4 1014 0x01E1 2014 SPIPC0 Pin Control Register 0 (Pin Function)
0x01C4 1018 0x01E1 2018 SPIPC1 Pin Control Register 1 (Pin Direction)
0x01C4 101C 0x01E1 201C SPIPC2 Pin Control Register 2 (Pin Data In)
0x01C4 1020 0x01E1 2020 SPIPC3 Pin Control Register 3 (Pin Data Out)
0x01C4 1024 0x01E1 2024 SPIPC4 Pin Control Register 4 (Pin Data Set)
0x01C4 1028 0x01E1 2028 SPIPC5 Pin Control Register 5 (Pin Data Clear)
0x01C4 102C 0x01E1 202C Reserved Reserved - Do not write to this register
0x01C4 1030 0x01E1 2030 Reserved Reserved - Do not write to this register
0x01C4 1034 0x01E1 2034 Reserved Reserved - Do not write to this register
0x01C4 1038 0x01E1 2038 SPIDAT0 Shift Register 0 (without format select)
0x01C4 103C 0x01E1 203C SPIDAT1 Shift Register 1 (with format select)
0x01C4 1040 0x01E1 2040 SPIBUF Buffer Register
0x01C4 1044 0x01E1 2044 SPIEMU Emulation Register
0x01C4 1048 0x01E1 2048 SPIDELAY Delay Register
0x01C4 104C 0x01E1 204C SPIDEF Default Chip Select Register
0x01C4 1050 0x01E1 2050 SPIFMT0 Format Register 0
0x01C4 1054 0x01E1 2054 SPIFMT1 Format Register 1
0x01C4 1058 0x01E1 2058 SPIFMT2 Format Register 2
0x01C4 105C 0x01E1 205C SPIFMT3 Format Register 3
0x01C4 1060 0x01E1 2060 Reserved Reserved - Do not write to this register
0x01C4 1064 0x01E1 2064 INTVEC1 Interrupt Vector for SPI INT1
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6.17.2 SPI Electrical Data/Timing
6.17.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-54 through Table 6-69 assume testing over recommended operating conditions (see Figure 6-38
through Figure 6-41).
Table 6-54. General Timing Requirements for SPI0 Master Modes(1)
No. PARAMETER MIN MAX UNIT
1 tc(SPC)M Cycle Time, SPI0_CLK, All Master Modes greater of 3P or 20 256P ns
2 tw(SPCH)M Pulse Width High, SPI0_CLK, All Master Modes 0.5tc(SPC)M - 1 ns
3 tw(SPCL)M Pulse Width Low, SPI0_CLK, All Master Modes 0.5tc(SPC)M - 1 ns
Polarity = 0, Phase = 0, 5
to SPI0_CLK rising
Polarity = 0, Phase = 1, - 0.5tc(SPC)M + 5
Delay, initial data bit valid on to SPI0_CLK rising
4 td(SIMO_SPC)M SPI0_SIMO after initial edge ns
Polarity = 1, Phase = 0,
on SPI0_CLK(2) 5
to SPI0_CLK falling
Polarity = 1, Phase = 1, - 0.5tc(SPC)M + 5
to SPI0_CLK falling
Polarity = 0, Phase = 0, 5
from SPI0_CLK rising
Polarity = 0, Phase = 1, 5
Delay, subsequent bits valid from SPI0_CLK falling
5 td(SPC_SIMO)M on SPI0_SIMO after transmit ns
Polarity = 1, Phase = 0,
edge of SPI0_CLK 5
from SPI0_CLK falling
Polarity = 1, Phase = 1, 5
from SPI0_CLK rising
Polarity = 0, Phase = 0, 0.5tc(SPC)M -3
from SPI0_CLK falling
Polarity = 0, Phase = 1, 0.5tc(SPC)M -3
Output hold time, SPI0_SIMO from SPI0_CLK rising
6 toh(SPC_SIMO)M valid after ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK 0.5tc(SPC)M -3
from SPI0_CLK rising
Polarity = 1, Phase = 1, 0.5tc(SPC)M -3
from SPI0_CLK falling
Polarity = 0, Phase = 0, 0
to SPI0_CLK falling
Polarity = 0, Phase = 1, 0
Input Setup Time, SPI0_SOMI to SPI0_CLK rising
7 tsu(SOMI_SPC)M valid before ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK 0
to SPI0_CLK rising
Polarity = 1, Phase = 1, 0
to SPI0_CLK falling
Polarity = 0, Phase = 0, 5
from SPI0_CLK falling
Polarity = 0, Phase = 1, 5
Input Hold Time, SPI0_SOMI from SPI0_CLK rising
8 tih(SPC_SOMI)M valid after ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK 5
from SPI0_CLK rising
Polarity = 1, Phase = 1, 5
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
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Table 6-55. General Timing Requirements for SPI0 Slave Modes(1)
No. PARAMETER MIN MAX UNIT
9 tc(SPC)S Cycle Time, SPI0_CLK, All Slave Modes greater of 3P or 40 ns
10 tw(SPCH)S Pulse Width High, SPI0_CLK, All Slave Modes 18 ns
11 tw(SPCL)S Pulse Width Low, SPI0_CLK, All Slave Modes 18 ns
Polarity = 0, Phase = 0, 2P
to SPI0_CLK rising
Polarity = 0, Phase = 1, 2P
Setup time, transmit data written to to SPI0_CLK rising
12 tsu(SOMI_SPC)S SPI before initial clock edge from ns
Polarity = 1, Phase = 0,
master.(2) (3) 2P
to SPI0_CLK falling
Polarity = 1, Phase = 1, 2P
to SPI0_CLK falling
Polarity = 0, Phase = 0, 18.5
from SPI0_CLK rising
Polarity = 0, Phase = 1, 18.5
Delay, subsequent bits valid on from SPI0_CLK falling
13 td(SPC_SOMI)S SPI0_SOMI after transmit edge of ns
Polarity = 1, Phase = 0,
SPI0_CLK 18.5
from SPI0_CLK falling
Polarity = 1, Phase = 1, 18.5
from SPI0_CLK rising
Polarity = 0, Phase = 0, 0.5tc(SPC)S -3
from SPI0_CLK falling
Polarity = 0, Phase = 1, 0.5tc(SPC)S -3
Output hold time, SPI0_SOMI valid from SPI0_CLK rising
14 toh(SPC_SOMI)S after ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK 0.5tc(SPC)S -3
from SPI0_CLK rising
Polarity = 1, Phase = 1, 0.5tc(SPC)S -3
from SPI0_CLK falling
Polarity = 0, Phase = 0, 0
to SPI0_CLK falling
Polarity = 0, Phase = 1, 0
Input Setup Time, SPI0_SIMO valid to SPI0_CLK rising
15 tsu(SIMO_SPC)S before ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK 0
to SPI0_CLK rising
Polarity = 1, Phase = 1, 0
to SPI0_CLK falling
Polarity = 0, Phase = 0, 5
from SPI0_CLK falling
Polarity = 0, Phase = 1, 5
Input Hold Time, SPI0_SIMO valid from SPI0_CLK rising
16 tih(SPC_SIMO)S after ns
Polarity = 1, Phase = 0,
receive edge of SPI0_CLK 5
from SPI0_CLK rising
Polarity = 1, Phase = 1, 5
from SPI0_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI0_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI0_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Table 6-56. Additional(1) SPI0 Master Timings, 4-Pin Enable Option(2) (3)
No. PARAMATER MIN MAX UNIT
Polarity = 0, Phase = 0, 3P + 3.6
to SPI0_CLK rising
Polarity = 0, Phase = 1, 0.5tc(SPC)M + 3P + 3.6
Delay from slave assertion of to SPI0_CLK rising
17 td(ENA_SPC)M SPI0_ENA active to first SPI0_CLK ns
Polarity = 1, Phase = 0,
from master.(4) 3P + 3.6
to SPI0_CLK falling
Polarity = 1, Phase = 1, 0.5tc(SPC)M + 3P + 3.6
to SPI0_CLK falling
Polarity = 0, Phase = 0, 0.5tc(SPC)M + P + 5
from SPI0_CLK falling
Polarity = 0, Phase = 1,
Max delay for slave to deassert P + 5
from SPI0_CLK falling
SPI0_ENA after final SPI0_CLK edge
18 td(SPC_ENA)M ns
to ensure master does not begin the Polarity = 1, Phase = 0, 0.5tc(SPC)M + P + 5
next transfer.(5) from SPI0_CLK rising
Polarity = 1, Phase = 1, P + 5
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-54).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI0_EN A deassertion.
Table 6-57. Additional(1) SPI0 Master Timings, 4-Pin Chip Select Option(2) (3)
No. PARAMATER MIN MAX UNIT
Polarity = 0, Phase = 0, 2P - 5
to SPI0_CLK rising
Polarity = 0, Phase = 1, 0.5tc(SPC)M + 2P - 5
to SPI0_CLK rising
Delay from SPI0_SCS active to first
19 td(SCS_SPC)M ns
SPI0_CLK(4) (5) Polarity = 1, Phase = 0, 2P - 5
to SPI0_CLK falling
Polarity = 1, Phase = 1, 0.5tc(SPC)M + 2P - 5
to SPI0_CLK falling
Polarity = 0, Phase = 0, 0.5tc(SPC)M + P - 3
from SPI0_CLK falling
Polarity = 0, Phase = 1, P - 3
from SPI0_CLK falling
Delay from final SPI0_CLK edge to
20 td(SPC_SCS)M ns
master deasserting SPI0_SCS (6) (7) Polarity = 1, Phase = 0, 0.5tc(SPC)M + P - 3
from SPI0_CLK rising
Polarity = 1, Phase = 1, P - 3
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-54).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 6-58. Additional(1) SPI0 Master Timings, 5-Pin Option(2) (3)
No. PARAMATER MIN MAX UNIT
Polarity = 0, Phase = 0, 0.5tc(SPC)M + P + 5
from SPI0_CLK falling
Max delay for slave to Polarity = 0, Phase = 1, P + 5
deassert SPI0_ENA after final from SPI0_CLK falling
18 td(SPC_ENA)M SPI0_CLK edge to ensure ns
Polarity = 1, Phase = 0,
master does not begin the 0.5tc(SPC)M + P + 5
from SPI0_CLK rising
next transfer.(4)
Polarity = 1, Phase = 1, P + 5
from SPI0_CLK rising
Polarity = 0, Phase = 0, 0.5tc(SPC)M + P - 3
from SPI0_CLK falling
Polarity = 0, Phase = 1,
Delay from final SPI0_CLK P - 3
from SPI0_CLK falling
edge to
20 td(SPC_SCS)M ns
master deasserting Polarity = 1, Phase = 0, 0.5tc(SPC)M + P -3
SPI0_SCS (5) (6) from SPI0_CLK rising
Polarity = 1, Phase = 1, P - 3
from SPI0_CLK rising
Max delay for slave SPI to drive SPI0_ENA valid after
21 td(SCSL_ENAL)M master asserts SPI0_SCS to delay the C2TDELAY + P ns
master from beginning the next transfer,
Polarity = 0, Phase = 0, 2P -5
to SPI0_CLK rising
Polarity = 0, Phase = 1, 0.5tc(SPC)M + 2P -5
to SPI0_CLK rising
Delay from SPI0_SCS active
22 td(SCS_SPC)M ns
to first SPI0_CLK(7) (8) (9) Polarity = 1, Phase = 0, 2P -5
to SPI0_CLK falling
Polarity = 1, Phase = 1, 0.5tc(SPC)M + 2P -5
to SPI0_CLK falling
Polarity = 0, Phase = 0, 3P + 3.6
to SPI0_CLK rising
Polarity = 0, Phase = 1, 0.5tc(SPC)M + 3P + 3.6
Delay from assertion of to SPI0_CLK rising
23 td(ENA_SPC)M SPI0_ENA low to first ns
Polarity = 1, Phase = 0,
SPI0_CLK edge.(10) 3P + 3.6
to SPI0_CLK falling
Polarity = 1, Phase = 1, 0.5tc(SPC)M + 3P + 3.6
to SPI0_CLK falling
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-55).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI0_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA.
(8) In the case where the master SPI is ready with new data before SPI0_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI0_ENA was initially deasserted high and SPI0_CLK is delayed.
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Table 6-59. Additional(1) SPI0 Slave Timings, 4-Pin Enable Option(2) (3)
No. PARAMATER MIN MAX UNIT
Polarity = 0, Phase = 0, 1.5 P -3 2.5 P + 18.5
from SPI0_CLK falling
Polarity = 0, Phase = 1,
Delay from final – 0.5tc(SPC)M + 1.5 P -3 – 0.5tc(SPC)M + 2.5 P + 18.5
from SPI0_CLK falling
SPI0_CLK edge to
24 td(SPC_ENAH)S ns
slave deasserting Polarity = 1, Phase = 0, 1.5 P -3 2.5 P + 18.5
SPI0_ENA. from SPI0_CLK rising
Polarity = 1, Phase = 1, – 0.5tc(SPC)M + 1.5 P -3 – 0.5tc(SPC)M + 2.5 P + 18.5
from SPI0_CLK rising
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-55).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-60. Additional(1) SPI0 Slave Timings, 4-Pin Chip Select Option(2) (3)
No. PARAMATER MIN MAX UNIT
Required delay from SPI0_SCS asserted at slave to first
25 td(SCSL_SPC)S 2P ns
SPI0_CLK edge at slave. Polarity = 0, Phase = 0, 0.5tc(SPC)M + P+5
from SPI0_CLK falling
Polarity = 0, Phase = 1, P+5
Required delay from final from SPI0_CLK falling
26 td(SPC_SCSH)S SPI0_CLK edge before ns
Polarity = 1, Phase = 0,
SPI0_SCS is deasserted. 0.5tc(SPC)M + P+5
from SPI0_CLK rising
Polarity = 1, Phase = 1, P+5
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
27 tena(SCSL_SOMI)S P + 18.5 ns
SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating
28 tdis(SCSH_SOMI)S P + 18.5 ns
SPI0_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-55).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 6-61. Additional(1) SPI0 Slave Timings, 5-Pin Option(2) (3)
No. PARAMATER MIN MAX UNIT
Required delay from SPI0_SCS asserted at slave to first
25 td(SCSL_SPC)S 2P ns
SPI0_CLK edge at slave. Polarity = 0, Phase = 0, 0.5tc(SPC)M + P +
from SPI0_CLK falling 5
Polarity = 0, Phase = 1, P + 5
Required delay from final SPI0_CLK from SPI0_CLK falling
26 td(SPC_SCSH)S edge before SPI0_SCS is ns
Polarity = 1, Phase = 0, 0.5tc(SPC)M + P +
deasserted. from SPI0_CLK rising 5
Polarity = 1, Phase = 1, P + 5
from SPI0_CLK rising
Delay from master asserting SPI0_SCS to slave driving
27 tena(SCSL_SOMI)S P + 18.5 ns
SPI0_SOMI valid
Delay from master deasserting SPI0_SCS to slave 3-stating
28 tdis(SCSH_SOMI)S P + 18.5 ns
SPI0_SOMI
Delay from master deasserting SPI0_SCS to slave driving
29 tena(SCSL_ENA)S 18.5 ns
SPI0_ENA valid Polarity = 0, Phase = 0, 2.5 P + 18.5
from SPI0_CLK falling
Polarity = 0, Phase = 1, 2.5 P + 18.5
Delay from final clock receive edge from SPI0_CLK rising
30 tdis(SPC_ENA)S on SPI0_CLK to slave 3-stating or ns
Polarity = 1, Phase = 0,
driving high SPI0_ENA.(4) 2.5 P + 18.5
from SPI0_CLK rising
Polarity = 1, Phase = 1, 2.5 P + 18.5
from SPI0_CLK falling
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-55).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is 3-
stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
Table 6-62. General Timing Requirements for SPI1 Master Modes(1)
No. PARAMATER MIN MAX UNIT
1 tc(SPC)M Cycle Time, SPI1_CLK, All Master Modes greater of 3P or 20 ns 256P ns
2 tw(SPCH)M Pulse Width High, SPI1_CLK, All Master Modes 0.5tc(SPC)M - 1 ns
3 tw(SPCL)M Pulse Width Low, SPI1_CLK, All Master Modes 0.5tc(SPC)M - 1 ns
Polarity = 0, Phase =
0, 5
to SPI1_CLK rising
Polarity = 0, Phase =
1, - 0.5tc(SPC)M + 5
Delay, initial data bit valid on to SPI1_CLK rising
4 td(SIMO_SPC)M SPI1_SIMO to initial edge on ns
Polarity = 1, Phase =
SPI1_CLK(2) 0, 5
to SPI1_CLK falling
Polarity = 1, Phase =
1, - 0.5tc(SPC)M + 5
to SPI1_CLK falling
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI1_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI1_SOMI.
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Table 6-62. General Timing Requirements for SPI1 Master Modes(1) (continued)
No. PARAMATER MIN MAX UNIT
Polarity = 0, Phase =
0, 5
from SPI1_CLK rising
Polarity = 0, Phase =
1, 5
Delay, subsequent bits valid on from SPI1_CLK falling
5 td(SPC_SIMO)M SPI1_SIMO after transmit edge of ns
Polarity = 1, Phase =
SPI1_CLK 0, 5
from SPI1_CLK falling
Polarity = 1, Phase =
1, 5
from SPI1_CLK rising
Polarity = 0, Phase =
0, 0.5tc(SPC)M -3
from SPI1_CLK falling
Polarity = 0, Phase =
1, 0.5tc(SPC)M -3
Output hold time, SPI1_SIMO valid from SPI1_CLK rising
6 toh(SPC_SIMO)M after ns
Polarity = 1, Phase =
receive edge of SPI1_CLK 0, 0.5tc(SPC)M -3
from SPI1_CLK rising
Polarity = 1, Phase =
1, 0.5tc(SPC)M -3
from SPI1_CLK falling
Polarity = 0, Phase =
0, 0
to SPI1_CLK falling
Polarity = 0, Phase =
1, 0
Input Setup Time, SPI1_SOMI valid to SPI1_CLK rising
7 tsu(SOMI_SPC)M before ns
Polarity = 1, Phase =
receive edge of SPI1_CLK 0, 0
to SPI1_CLK rising
Polarity = 1, Phase =
1, 0
to SPI1_CLK falling
Polarity = 0, Phase =
0, 5
from SPI1_CLK falling
Polarity = 0, Phase =
1, 5
Input Hold Time, SPI1_SOMI valid from SPI1_CLK rising
8 tih(SPC_SOMI)M after ns
Polarity = 1, Phase =
receive edge of SPI1_CLK 0, 5
from SPI1_CLK rising
Polarity = 1, Phase =
1, 5
from SPI1_CLK falling
Table 6-63. General Timing Requirements for SPI1 Slave Modes(1)
No. PARAMATER MIN MAX UNIT
9 tc(SPC)S Cycle Time, SPI1_CLK, All Slave Modes greater of 3P or 40 ns ns
10 tw(SPCH)S Pulse Width High, SPI1_CLK, All Slave Modes 18 ns
11 tw(SPCL)S Pulse Width Low, SPI1_CLK, All Slave Modes 18 ns
(1) P = SYSCLK2 period
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Table 6-63. General Timing Requirements for SPI1 Slave Modes(1) (continued)
No. PARAMATER MIN MAX UNIT
Polarity = 0, Phase = 0, 2P
to SPI1_CLK rising
Polarity = 0, Phase = 1, 2P
Setup time, transmit data written to to SPI1_CLK rising
12 tsu(SOMI_SPC)S SPI before initial clock edge from ns
Polarity = 1, Phase = 0,
master.(2) (3) 2P
to SPI1_CLK falling
Polarity = 1, Phase = 1, 2P
to SPI1_CLK falling
Polarity = 0, Phase = 0, 19
from SPI1_CLK rising
Polarity = 0, Phase = 1, 19
Delay, subsequent bits valid on from SPI1_CLK falling
13 td(SPC_SOMI)S SPI1_SOMI after transmit edge of ns
Polarity = 1, Phase = 0,
SPI1_CLK 19
from SPI1_CLK falling
Polarity = 1, Phase = 1, 19
from SPI1_CLK rising
Polarity = 0, Phase = 0, 0.5tc(SPC)S -3
from SPI1_CLK falling
Polarity = 0, Phase = 1, 0.5tc(SPC)S -3
Output hold time, SPI1_SOMI valid from SPI1_CLK rising
14 toh(SPC_SOMI)S after ns
Polarity = 1, Phase = 0,
receive edge of SPI1_CLK 0.5tc(SPC)S -3
from SPI1_CLK rising
Polarity = 1, Phase = 1, 0.5tc(SPC)S -3
from SPI1_CLK falling
Polarity = 0, Phase = 0, 0
to SPI1_CLK falling
Polarity = 0, Phase = 1, 0
Input Setup Time, SPI1_SIMO valid to SPI1_CLK rising
15 tsu(SIMO_SPC)S before ns
Polarity = 1, Phase = 0,
receive edge of SPI1_CLK 0
to SPI1_CLK rising
Polarity = 1, Phase = 1, 0
to SPI1_CLK falling
Polarity = 0, Phase = 0, 5
from SPI1_CLK falling
Polarity = 0, Phase = 1, 5
Input Hold Time, SPI1_SIMO valid from SPI1_CLK rising
16 tih(SPC_SIMO)S after ns
Polarity = 1, Phase = 0,
receive edge of SPI1_CLK 5
from SPI1_CLK rising
Polarity = 1, Phase = 1, 5
from SPI1_CLK falling
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPI1_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPI1_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, In analyzing throughput requirements, additional internal bus
cycles must be accounted for to allow data to be written to the SPI module by the DSP CPU.
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Table 6-64. Additional(1) SPI1 Master Timings, 4-Pin Enable Option(2) (3)
No. PARAMETER MIN MAX UNIT
Polarity = 0, Phase = 0, 3P + 3
to SPI1_CLK rising
Polarity = 0, Phase = 1, 0.5tc(SPC)M + 3P + 3
Delay from slave assertion of to SPI1_CLK rising
17 td(EN A_SPC)M SPI1_ENA active to first SPI1_CLK ns
Polarity = 1, Phase = 0,
from master.(4) 3P + 3
to SPI1_CLK falling
Polarity = 1, Phase = 1, 0.5tc(SPC)M + 3P + 3
to SPI1_CLK falling
Polarity = 0, Phase = 0, 0.5tc(SPC)M + P + 5
from SPI1_CLK falling
Polarity = 0, Phase = 1,
Max delay for slave to deassert P + 5
from SPI1_CLK falling
SPI1_ENA after final SPI1_CLK edge
18 td(SPC_ENA)M ns
to ensure master does not begin the Polarity = 1, Phase = 0, 0.5tc(SPC)M + P + 5
next transfer.(5) from SPI1_CLK rising
Polarity = 1, Phase = 1, P + 5
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-62).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA assertion.
(5) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
Table 6-65. Additional(1) SPI1 Master Timings, 4-Pin Chip Select Option(2) (3)
No. PARAMATER MIN MAX UNIT
Polarity = 0, Phase = 0, 2P -5
to SPI1_CLK rising
Polarity = 0, Phase = 1, 0.5tc(SPC)M + 2P -5
to SPI1_CLK rising
Delay from SPI1_SCS active to first
19 td(SCS_SPC)M ns
SPI1_CLK(4) (5) Polarity = 1, Phase = 0, 2P -5
to SPI1_CLK falling
Polarity = 1, Phase = 1, 0.5tc(SPC)M + 2P -5
to SPI1_CLK falling
Polarity = 0, Phase = 0, 0.5tc(SPC)M + P - 3
from SPI1_CLK falling
Polarity = 0, Phase = 1, P - 3
from SPI1_CLK falling
Delay from final SPI1_CLK edge to
20 td(SPC_SCS)M ns
master deasserting SPI1_SCS (6) (7) Polarity = 1, Phase = 0, 0.5tc(SPC)M + P -3
from SPI1_CLK rising
Polarity = 1, Phase = 1, P - 3
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-62).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
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Table 6-66. Additional(1) SPI1 Master Timings, 5-Pin Option(2) (3)
No. PARAMATER MIN MAX UNIT
Polarity = 0, Phase = 0, 0.5tc(SPC)M+P+5
from SPI1_CLK falling
Max delay for slave to Polarity = 0, Phase = 1, P+5
deassert SPI1_ENA after final from SPI1_CLK falling
18 td(SPC_ENA)M SPI1_CLK edge to ensure ns
Polarity = 1, Phase = 0,
master does not begin the 0.5tc(SPC)M+P+5
from SPI1_CLK rising
next transfer.(4)
Polarity = 1, Phase = 1, P+5
from SPI1_CLK rising
Polarity = 0, Phase = 0, 0.5tc(SPC)M + P -3
from SPI1_CLK falling
Polarity = 0, Phase = 1,
Delay from final SPI1_CLK P - 3
from SPI1_CLK falling
edge to
20 td(SPC_SCS)M ns
master deasserting Polarity = 1, Phase = 0, 0.5tc(SPC)M+ P -3
SPI1_SCS (5) (6) from SPI1_CLK rising
Polarity = 1, Phase = 1, P - 3
from SPI1_CLK rising
Max delay for slave SPI to drive SPI1_ENA valid after
21 td(SCSL_ENAL)M master asserts SPI1_SCS to delay the C2TDELAY + P ns
master from beginning the next transfer,
Polarity = 0, Phase = 0, 2P -5
to SPI1_CLK rising
Polarity = 0, Phase = 1, 0.5tc(SPC)M + 2P -5
to SPI1_CLK rising
Delay from SPI1_SCS active
22 td(SCS_SPC)M ns
to first SPI1_CLK(7) (8) (9) Polarity = 1, Phase = 0, 2P -5
to SPI1_CLK falling
Polarity = 1, Phase = 1, 0.5tc(SPC)M + 2P -5
to SPI1_CLK falling
Polarity = 0, Phase = 0, 3P + 3
to SPI1_CLK rising
Polarity = 0, Phase = 1, 0.5tc(SPC)M + 3P + 3
Delay from assertion of to SPI1_CLK rising
23 td(ENA_SPC)M SPI1_ENA low to first ns
Polarity = 1, Phase = 0,
SPI1_CLK edge.(10) 3P + 3
to SPI1_CLK falling
Polarity = 1, Phase = 1, 0.5tc(SPC)M + 3P + 3
to SPI1_CLK falling
(1) These parameters are in addition to the general timings for SPI master modes (Table 6-63).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
(7) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(8) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(9) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(10) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
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Table 6-67. Additional(1) SPI1 Slave Timings, 4-Pin Enable Option(2) (3)
No. PARAMETER MIN MAX UNIT
Polarity = 0, Phase = 0, 1.5 P -3 2.5 P + 19
from SPI1_CLK falling
Polarity = 0, Phase = 1,
Delay from final – 0.5tc(SPC)M + 1.5 P -3 – 0.5tc(SPC)M + 2.5 P + 19
from SPI1_CLK falling
SPI1_CLK edge to
24 td(SPC_ENAH)S ns
slave deasserting Polarity = 1, Phase = 0, 1.5 P -3 2.5 P + 19
SPI1_ENA. from SPI1_CLK rising
Polarity = 1, Phase = 1, – 0.5tc(SPC)M + 1.5 P -3 – 0.5tc(SPC)M + 2.5 P + 19
from SPI1_CLK rising
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-63).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-68. Additional(1) SPI1 Slave Timings, 4-Pin Chip Select Option(2) (3)
No. PARAMETER MIN MAX UNIT
Required delay from SPI1_SCS asserted at slave to first
25 td(SCSL_SPC)S 2P ns
SPI1_CLK edge at slave. Polarity = 0, Phase = 0, 0.5tc(SPC)M + P + 5
from SPI1_CLK falling
Polarity = 0, Phase = 1, P + 5
Required delay from final from SPI1_CLK falling
26 td(SPC_SCSH)S SPI1_CLK edge before ns
Polarity = 1, Phase = 0,
SPI1_SCS is deasserted. 0.5tc(SPC)M + P + 5
from SPI1_CLK rising
Polarity = 1, Phase = 1, P + 5
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
27 tena(SCSL_SOMI)S P + 19 ns
SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating
28 tdis(SCSH_SOMI)S P + 19 ns
SPI1_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-63).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 6-69. Additional(1) SPI1 Slave Timings, 5-Pin Option(2) (3)
No. PARAMETER MIN MAX UNIT
Required delay from SPI1_SCS asserted at slave to first
25 td(SCSL_SPC)S 2P ns
SPI1_CLK edge at slave. Polarity = 0, Phase = 0, 0.5tc(SPC)M + P +
from SPI1_CLK falling 5
Polarity = 0, Phase = 1, P + 5
Required delay from final SPI1_CLK from SPI1_CLK falling
26 td(SPC_SCSH)S edge before SPI1_SCS is ns
Polarity = 1, Phase = 0, 0.5tc(SPC)M + P +
deasserted. from SPI1_CLK rising 5
Polarity = 1, Phase = 1, P + 5
from SPI1_CLK rising
Delay from master asserting SPI1_SCS to slave driving
27 tena(SCSL_SOMI)S P + 19 ns
SPI1_SOMI valid
Delay from master deasserting SPI1_SCS to slave 3-stating
28 tdis(SCSH_SOMI)S P + 19 ns
SPI1_SOMI
Delay from master deasserting SPI1_SCS to slave driving
29 tena(SCSL_ENA)S 19 ns
SPI1_ENA valid
(1) These parameters are in addition to the general timings for SPI slave modes (Table 6-63).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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Table 6-69. Additional(1) SPI1 Slave Timings, 5-Pin Option(2) (3) (continued)
No. PARAMETER MIN MAX UNIT
Polarity = 0, Phase = 0, 2.5 P + 19
from SPI1_CLK falling
Polarity = 0, Phase = 1, 2.5 P + 19
Delay from final clock receive edge from SPI1_CLK rising
30 tdis(SPC_ENA)S on SPI1_CLK to slave 3-stating or ns
Polarity = 1, Phase = 0,
driving high SPI1_ENA.(4) 2.5 P + 19
from SPI1_CLK rising
Polarity = 1, Phase = 1, 2.5 P + 19
from SPI1_CLK falling
(4) SPI1_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is 3-
stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
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SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
6
6
7
7
7
7
8
8
8
8
32
6
1
4
4
4
45
5
56
MASTER MODE
POLARITY = 0 PHASE = 0
MASTER MODE
POLARITY = 0 PHASE = 1
MASTER MODE
POLARITY = 1 PHASE = 0
MASTER MODE
POLARITY = 1 PHASE = 1
5
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Figure 6-38. SPI Timings—Master Mode
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SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SI(0) SI(1) SI(n−1) SI(n)
SO(0) SO(1) SO(n−1) SO(n)
SI(0) SI(1) SI(n−1) SI(n)
SO(0) SO(1) SO(n−1) SO(n)
SI(0) SI(1) SI(n−1) SI(n)
SO(0) SO(1) SO(n−1) SO(n)
SI(0) SI(1) SI(n−1) SI(n)
SO(0) SO(1) SO(n−1) SO(n)
14
14
15
15
15
15
16
16
16
16
1110
14
9
12
12
12
12
13
13
13
13
14
SLAVE MODE
POLARITY = 0 PHASE = 0
SLAVE MODE
POLARITY = 0 PHASE = 1
SLAVE MODE
POLARITY = 1 PHASE = 0
SLAVE MODE
POLARITY = 1 PHASE = 1
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Figure 6-39. SPI Timings—Slave Mode
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MASTER MODE 4 PIN WITH CHIP SELECT
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_ENA
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_SCS
SPIx_CLK
SPIx_SIMO
SPIx_SOMI
SPIx_ENA
SPIx_SCS
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
MO(0) MO(1) MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
MO(0)
MO(1)
MO(n−1) MO(n)
MI(0) MI(1) MI(n−1) MI(n)
17
19
21
22
23
20
18
20
18
MASTER MODE 4 PIN WITH ENABLE
MASTER MODE 5 PIN
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
DESEL(A)DESEL(A)
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Figure 6-40. SPI Timings—Master Mode (4-Pin and 5-Pin)
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27
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_ENA
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_SCS
SPIx_CLK
SPIx_SOMI
SPIx_SIMO
SPIx_ENA
SPIx_SCS
SO(0) SO(1) SO(n−1) SO(n)
SI(0) SI(1) SI(n−1) SI(n)
SO(0) SO(1)
SO(n−1)
SO(n)
SI(0) SI(1) SI(n−1) SI(n)
SO(0)
SO(1)
SO(n−1) SO(n)
SI(0) SI(1) SI(n−1) SI(n)
24
26
28
26
30
28
25
25
27
29
SLAVE MODE 4 PIN WITH ENABLE
SLAVE MODE 4 PIN WITH CHIP SELECT
SLAVE MODE 5 PIN
DESEL(A) DESEL(A)
A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR
3−STATE (REQUIRES EXTERNAL PULLUP)
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Figure 6-41. SPI Timings—Slave Mode (4-Pin and 5-Pin)
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
6.18 Enhanced Capture (eCAP) Peripheral
The C6745/6747 device contains up to three enhanced capture (eCAP) modules. Figure 6-42 shows a
functional block diagram of a module. See the TMS320C6745/C6747 DSP Peripherals Overview
Reference Guide. (SPRUFK9) for more details.
Uses for ECAP include:
• Speed measurements of rotating machinery (e.g. toothed sprockets sensed via Hall sensors)
• Elapsed time measurements between position sensor triggers
• Period and duty cycle measurements of Pulse train signals
• Decoding current or voltage amplitude derived from cuty cycle encoded current/voltage sensors
The ECAP module described in this specification includes the following features:
• 32 bit time base
• 4 event time-stamp registers (each 32 bits)
• Edge polarity selection for up to 4 sequenced time-stamp capture events
• Interrupt on either of the 4 events
• Single shot capture of up to 4 event time-stamps
• Continuous mode capture of time-stamps in a 4 deep circular buffer
• Absolute time-stamp capture
• Difference mode time-stamp capture
• All the above resources are dedicated to a single input pin
The eCAP modules are clocked at the SYSCLK2 rate.
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TSCTR
(counter−32 bit)
RST
CAP1
(APRD active) LD
CAP2
(ACMP active) LD
CAP3
(APRD shadow) LD
CAP4
(ACMP shadow) LD
Continuous /
Oneshot
Capture Control
LD1
LD2
LD3
LD4
32
32
PRD [0−31]
CMP [0−31]
CTR [0−31]
eCAPx
Interrupt
Trigger
and
Flag
control
to Interrupt
Controller
CTR=CMP
32
32
32
32
32
ACMP
shadow
Event
Pre-scale
CTRPHS
(phase register−32 bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR [0−31]
PRD [0−31]
CMP [0−31]
CTR=CMP
CTR=PRD
CTR_OVF
OVF
APWM mode
Delta−mode
SYNC
4
Capture events
CEVT[1:4]
APRD
shadow
32
32
MODE SELECT
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Figure 6-42. eCAP Functional Block Diagram
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Table 6-70 is the list of the ECAP registers.
Table 6-70. ECAPx Configuration Registers
ECAP0 ECAP1 ECAP2 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS
0x01F0 6000 0x01F0 7000 0x01F0 8000 TSCTR Time-Stamp Counter
0x01F0 6004 0x01F0 7004 0x01F0 8004 CTRPHS Counter Phase Offset Value Register
0x01F0 6008 0x01F0 7008 0x01F0 8008 CAP1 Capture 1 Register
0x01F0 600C 0x01F0 700C 0x01F0 800C CAP2 Capture 2 Register
0x01F0 6010 0x01F0 7010 0x01F0 8010 CAP3 Capture 3 Register
0x01F0 6014 0x01F0 7014 0x01F0 8014 CAP4 Capture 4 Register
0x01F0 6028 0x01F0 7028 0x01F0 8028 ECCTL1 Capture Control Register 1
0x01F0 602A 0x01F0 702A 0x01F0 802A ECCTL2 Capture Control Register 2
0x01F0 602C 0x01F0 702C 0x01F0 802C ECEINT Capture Interrupt Enable Register
0x01F0 602E 0x01F0 702E 0x01F0 802E ECFLG Capture Interrupt Flag Register
0x01F0 6030 0x01F0 7030 0x01F0 8030 ECCLR Capture Interrupt Clear Register
0x01F0 6032 0x01F0 7032 0x01F0 8032 ECFRC Capture Interrupt Force Register
0x01F0 605C 0x01F0 705C 0x01F0 805C REVID Revision ID
Table 6-71 shows the eCAP timing requirement and Table 6-72 shows the eCAP switching characteristics.
Table 6-71. Enhanced Capture (eCAP) Timing Requirement
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(CAP) Capture input pulse width Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles
Table 6-72. eCAP Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(APWM) Pulse duration, APWMx output high/low 20 ns
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QWDTMR
QWDPRD
16
QWDOG
UTIME
QUPRD
QUTMR
32
UTOUT
WDTOUT
Quadrature
capture unit
(QCAP)
QCPRDLAT
QCTMRLAT
16
QFLG
QEPSTS
QEPCTL
Registers
used by
multiple units
QCLK
QDIR
QI
QS
PHE
PCSOUT
Quadrature
decoder
(QDU)
QDECCTL
16
Position counter/
control unit
(PCCU)
QPOSLAT
QPOSSLAT
16
QPOSILAT
EQEPxAIN
EQEPxBIN
EQEPxIIN
EQEPxIOUT
EQEPxIOE
EQEPxSIN
EQEPxSOUT
EQEPxSOE
GPIO
MUX
EQEPxA/XCLK
EQEPxB/XDIR
EQEPxS
EQEPxI
QPOSCMP QEINT
QFRC
32
QCLR
QPOSCTL
1632
QPOSCNT
QPOSMAX
QPOSINIT
EQEPxINT
Enhanced QEP (eQEP) Peripheral
System
control registers
QCTMR
QCPRD
1616
QCAPCTL
EQEPxENCLK
SYSCLK2
Data bus
To CPU
Interrupt Controller
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6.19 Enhanced Quadrature Encoder (eQEP) Peripheral
The C6745/6747 device contains up to two enhanced quadrature encoder (eQEP) modules. See the
TMS320C6745/C6747 DSP Peripherals Overview Reference Guide. (SPRUFK9) for more details.
Figure 6-43. eQEP Functional Block Diagram
Table 6-73 is the list of the EQEP registers.
Table 6-74 shows the eQEP timing requirement and Table 6-75 shows the eQEP switching
characteristics.
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Table 6-73. EQEP Registers
EQEP0 EQEP1
BYTE ADDRESS BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01F0 9000 0x01F0 A000 QPOSCNT eQEP Position Counter
0x01F0 9004 0x01F0 A004 QPOSINIT eQEP Initialization Position Count
0x01F0 9008 0x01F0 A008 QPOSMAX eQEP Maximum Position Count
0x01F0 900C 0x01F0 A00C QPOSCMP eQEP Position-compare
0x01F0 9010 0x01F0 A010 QPOSILAT eQEP Index Position Latch
0x01F0 9014 0x01F0 A014 QPOSSLAT eQEP Strobe Position Latch
0x01F0 9018 0x01F0 A018 QPOSLAT eQEP Position Latch
0x01F0 901C 0x01F0 A01C QUTMR eQEP Unit Timer
0x01F0 9020 0x01F0 A020 QUPRD eQEP Unit Period Register
0x01F0 9024 0x01F0 A024 QWDTMR eQEP Watchdog Timer
0x01F0 9026 0x01F0 A026 QWDPRD eQEP Watchdog Period Register
0x01F0 9028 0x01F0 A028 QDECCTL eQEP Decoder Control Register
0x01F0 902A 0x01F0 A02A QEPCTL eQEP Control Register
0x01F0 902C 0x01F0 A02C QCAPCTL eQEP Capture Control Register
0x01F0 902E 0x01F0 A02E QPOSCTL eQEP Position-compare Control Register
0x01F0 9030 0x01F0 A030 QEINT eQEP Interrupt Enable Register
0x01F0 9032 0x01F0 A032 QFLG eQEP Interrupt Flag Register
0x01F0 9034 0x01F0 A034 QCLR eQEP Interrupt Clear Register
0x01F0 9036 0x01F0 A036 QFRC eQEP Interrupt Force Register
0x01F0 9038 0x01F0 A038 QEPSTS eQEP Status Register
0x01F0 903A 0x01F0 A03A QCTMR eQEP Capture Timer
0x01F0 903C 0x01F0 A03C QCPRD eQEP Capture Period Register
0x01F0 903E 0x01F0 A03E QCTMRLAT eQEP Capture Timer Latch
0x01F0 9040 0x01F0 A040 QCPRDLAT eQEP Capture Period Latch
0x01F0 905C 0x01F0 A05C REVID eQEP Revision ID
Table 6-74. Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(QEPP) QEP input period Asynchronous/synchronous 2tc(SCO) cycles
tw(INDEXH) QEP Index Input High time Asynchronous/synchronous 2tc(SCO) cycles
tw(INDEXL) QEP Index Input Low time Asynchronous/synchronous 2tc(SCO) cycles
tw(STROBH) QEP Strobe High time Asynchronous/synchronous 2tc(SCO) cycles
tw(STROBL) QEP Strobe Input Low time Asynchronous/synchronous 2tc(SCO) cycles
Table 6-75. eQEP Switching Characteristics
PARAMETER MIN MAX UNIT
td(CNTR)xin Delay time, external clock to counter increment 4tc(SCO) cycles
td(PCS-OUT)QEP Delay time, QEP input edge to position compare sync output 6tc(SCO) cycles
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EPWMTZ
Peripheral Bus
eHRPWM0 module
eHRPWM1 module
EPWM0SYNCI
EPWM1SYNCI
EPWM1SYNCO
EPWM2SYNCI
EPWM2SYNCO
GPIO
MUX
EPWMSYNCI
EPWM2A
EPWM2B
EPWM1A
EPWM1B
EPWM0A
EPWM0B
EPWM0INT
EPWM1INT
EPWM2INT
EPWMTZ
EPWMTZ
EPWM0SYNCO
Interrupt
Controllers
EPWMSYNCO
To eCAP0
module
(sync in)
eHRPWM2 module
TMS320C6745, TMS320C6747
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6.20 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM)
The C6745/6747 device contains up to three enhanced PWM Modules (eHRPWM). Figure 6-44 shows a
block diagram of multiple eHRPWM modules. Figure 4-4 shows the signal interconnections with the
eHRPWM. See the TMS320C6745/C6747 DSP Peripherals Overview Reference Guide. (SPRUFK9) for
more details.
Figure 6-44. Multiple PWM Modules in a C6745/6747 System
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CTR=PRD
TBPRD shadow (16)
TBPRD active (16)
Counter
up/down
(16 bit)
TBCNT
active (16)
TBCTL[CNTLDE]
TBCTL[SWFSYNC]
(software forced sync)
EPWMSYNCI
CTR=ZERO
CTR_Dir
CTR=CMPB
Disabled
Sync
in/out
control
Mux
TBCTL[SYNCOSEL]
EPWMSYNCO
TBPHS active (24)
16 8
TBPHSHR (8)
Phase
control
Time−base (TB)
CTR=CMPA
CMPA active (24)
16
CMPA shadow (24)
Action
qualifier
(AQ)
8
16
Counter compare (CC)
CMPB active (16)
CTR=CMPB
CMPB shadow (16)
CMPAHR (8)
EPWMA
EPWMB
Dead
band
(DB)
PWM
chopper
(PC)
Trip
zone
(TZ)
CTR = ZERO
EPWMxA
EPWMxB
EPWMxTZINT
TZ
HiRes PWM (HRPWM)
CTR = PRD
CTR = ZERO
CTR = CMPB
CTR = CMPA
CTR_Dir
Event
trigger
and
interrupt
(ET)
EPWMxINT
CTR=ZERO
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Figure 6-45. eHRPWM Sub-Modules Showing Critical Internal Signal Interconnections
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Table 6-76. eHRPWM Module Control and Status Registers Grouped by Submodule
eHRPWM0 eHRPWM1 eHRPWM2
BYTE BYTE BYTE SIZE
ADDRESS ADDRESS ADDRESS ACRONYM (×16) SHADOW REGISTER DESCRIPTION
TIME-BASE SUBMODULE REGISTERS
0x01F0 0000 0x01F0 2000 0x01F0 4000 TBCTL 1 No Time-Base Control Register
0x01F0 0002 0x01F0 2002 0x01F0 4002 TBSTS 1 No Time-Base Status Register
0x01F0 0004 0x01F0 2004 0x01F0 4004 TBPHSHR 1 No Extension for HRPWM Phase Register (1)
0x01F0 0006 0x01F0 2006 0x01F0 4006 TBPHS 1 No Time-Base Phase Register
0x01F0 0008 0x01F0 2008 0x01F0 4008 TBCNT 1 No Time-Base Counter Register
0x01F0 000A 0x01F0 200A 0x01F0 400A TBPRD 1 Yes Time-Base Period Register
COUNTER-COMPARE SUBMODULE REGISTERS
0x01F0 000E 0x01F0 200E 0x01F0 400E CMPCTL 1 No Counter-Compare Control Register
0x01F0 0010 0x01F0 2010 0x01F0 4010 CMPAHR 1 No Extension for HRPWM Counter-Compare A Register (1)
0x01F0 0012 0x01F0 2012 0x01F0 4012 CMPA 1 Yes Counter-Compare A Register
0x01F0 0014 0x01F0 2014 0x01F0 4014 CMPB 1 Yes Counter-Compare B Register
ACTION-QUALIFIER SUBMODULE REGISTERS
0x01F0 0016 0x01F0 2016 0x01F0 4016 AQCTLA 1 No Action-Qualifier Control Register for Output A
(eHRPWMxA)
0x01F0 0018 0x01F0 2018 0x01F0 4018 AQCTLB 1 No Action-Qualifier Control Register for Output B
(eHRPWMxB)
0x01F0 001A 0x01F0 201A 0x01F0 401A AQSFRC 1 No Action-Qualifier Software Force Register
0x01F0 001C 0x01F0 201C 0x01F0 401C AQCSFRC 1 Yes Action-Qualifier Continuous S/W Force Register Set
DEAD-BAND GENERATOR SUBMODULE REGISTER
0x01F0 001E 0x01F0 201E 0x01F0 401E DBCTL 1 No Dead-Band Generator Control Register
0x01F0 0020 0x01F0 2020 0x01F0 4020 DBRED 1 No Dead-Band Generator Rising Edge Delay Count
Register
0x01F0 0022 0x01F0 2022 0x01F0 4022 DBFED 1 No Dead-Band Generator Falling Edge Delay Count
Register
PWM-CHOPPER SUBMODULE REGISTERS
0x01F0 003C 0x01F0 203C 0x01F0 403C PCCTL 1 No PWM-Chopper Control Register
TRIP-ZONE SUBMODULE REGISTERS
0x01F0 0024 0x01F0 2024 0x01F0 4024 TZSEL 1 No Trip-Zone Select Register
0x01F0 0028 0x01F0 2028 0x01F0 4028 TZCTL 1 No Trip-Zone Control Register
0x01F0 002A 0x01F0 202A 0x01F0 402A TZEINT 1 No Trip-Zone Enable Interrupt Register
0x01F0 002C 0x01F0 202C 0x01F0 402C TZFLG 1 No Trip-Zone Flag Register
0x01F0 002E 0x01F0 202E 0x01F0 402E TZCLR 1 No Trip-Zone Clear Register
0x01F0 0030 0x01F0 2030 0x01F0 4030 TZFRC 1 No Trip-Zone Force Register
EVENT-TRIGGER SUBMODULE REGISTERS
0x01F0 0032 0x01F0 2032 0x01F0 4032 ETSEL 1 No Event-Trigger Selection Register
0x01F0 0034 0x01F0 2034 0x01F0 4034 ETPS 1 No Event-Trigger Pre-Scale Register
0x01F0 0036 0x01F0 2036 0x01F0 4036 ETFLG 1 No Event-Trigger Flag Register
0x01F0 0038 0x01F0 2038 0x01F0 4038 ETCLR 1 No Event-Trigger Clear Register
0x01F0 003A 0x01F0 203A 0x01F0 403A ETFRC 1 No Event-Trigger Force Register
HIGH-RESOLUTION PWM (HRPWM) SUBMODULE REGISTERS
0x01F0 1040 0x01F0 3040 0x01F0 5040 HRCNFG 1 No HRPWM Configuration Register (1)
(1) These registers are only available on eHRPWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these
locations are reserved.
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PWM (A)
TZ
tw(TZ)
td(TZ_PWM)HZ
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
6.20.1 Enhanced Pulse Width Modulator (eHRPWM) Timing
PWM refers to PWM outputs on eHRPWM1-6. Table 6-77 shows the PWM timing requirements and
Table 6-78, switching characteristics.
Table 6-77. eHRPWM Timing Requirements
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(SYNCIN) Sync input pulse width Asynchronous 2tc(SCO) cycles
Synchronous 2tc(SCO) cycles
Table 6-78. eHRPWM Switching Characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
tw(PWM) Pulse duration, PWMx output high/low 20 ns
tw(SYNCOUT) Sync output pulse width 8tc(SCO) cycles
td(PWM)TZA Delay time, trip input active to PWM forced high no pin load; 25 ns
Delay time, trip input active to PWM forced low no additional
programmable delay
td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z no additional 20 ns
programmable delay
6.20.2 Trip-Zone Input Timing
A. PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM
recovery software.
Figure 6-46. PWM Hi-Z Characteristics
Table 6-79. Trip-Zone input Timing Requirements
PARAMETER MIN MAX UNIT
tw(TZ) Pulse duration, TZx input low Asynchronous 1tc(SCO) cycles
Synchronous 2tc(SCO) cycles
Table 6-80 shows the high-resolution PWM switching characteristics.
Table 6-80. High Resolution PWM Characteristics at SYSCLKOUT = (60 - 100 MHz)
PARAMETER MIN TYP MAX UNIT
Micro Edge Positioning (MEP) step size(1) 200 ps
(1) MEP step size will increase with low voltage and high temperature and decrease with high voltage and cold temperature.
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6.21 LCD Controller
The LCD controller consists of two independent controllers, the Raster Controller and the LCD Interface
Display Driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
• The Raster Controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the Raster engine which, in turn,
outputs to the external LCD device.
• The LIDD Controller supports the asynchronous LCD interface. It provides full-timing programmability
of control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 1024 x 1024 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate. OMAP-L1x/C674x/AM1x SOC
Architecture and Throughput Overview (SPRAB93).
Table 6-81 lists the LCD Controller registers
Table 6-81. LCD Controller (LCDC) Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E1 3000 REVID LCD Revision Identification Register
0x01E1 3004 LCD_CTRL LCD Control Register
0x01E1 3008 LCD_STAT LCD Status Register
0x01E1 300C LIDD_CTRL LCD LIDD Control Register
0x01E1 3010 LIDD_CS0_CONF LCD LIDD CS0 Configuration Register
0x01E1 3014 LIDD_CS0_ADDR LCD LIDD CS0 Address Read/Write Register
0x01E1 3018 LIDD_CS0_DATA LCD LIDD CS0 Data Read/Write Register
0x01E1 301C LIDD_CS1_CONF LCD LIDD CS1 Configuration Register
0x01E1 3020 LIDD_CS1_ADDR LCD LIDD CS1 Address Read/Write Register
0x01E1 3024 LIDD_CS1_DATA LCD LIDD CS1 Data Read/Write Register
0x01E1 3028 RASTER_CTRL LCD Raster Control Register
0x01E1 302C RASTER_TIMING_0 LCD Raster Timing 0 Register
0x01E1 3030 RASTER_TIMING_1 LCD Raster Timing 1 Register
0x01E1 3034 RASTER_TIMING_2 LCD Raster Timing 2 Register
0x01E1 3038 RASTER_SUBPANEL LCD Raster Subpanel Display Register
0x01E1 3040 LCDDMA_CTRL LCD DMA Control Register
0x01E1 3044 LCDDMA_FB0_BASE LCD DMA Frame Buffer 0 Base Address Register
0x01E1 3048 LCDDMA_FB0_CEILING LCD DMA Frame Buffer 0 Ceiling Address Register
0x01E1 304C LCDDMA_FB1_BASE LCD DMA Frame Buffer 1 Base Address Register
0x01E1 3050 LCDDMA_FB1_CEILING LCD DMA Frame Buffer 1 Ceiling Address Register
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LCD_AC_ENB_CS
LCD_PCLK
2
3
1W_SU
(0 to 31) W_STROBE
(1 to 63) W_HOLD
(1 to 15)
CS_DELAYR_SU
(0 to 31)
R_STROBE
(1 to 63)
R_HOLD
(1 to 15) CS_DELAY
LCD_MCLK
4
Write Data
5 14
16
17
15
Data[7:0]
Not Used
8 9
10 11
12
13
12
13
RS
R/W
E0
E1
LCD_D[15:0]
LCD_VSYNC
LCD_HSYNC
Read Status
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
6.21.1 LCD Interface Display Driver (LIDD Mode)
Table 6-82. LCD LIDD Mode Timing Requirements
No. PARAMETER MIN MAX UNIT
16 tsu(LCD_D) Setup time, LCD_D[15:0] valid before LCD_MCLK high 7 ns
17 th(LCD_D) Hold time, LCD_D[15:0] valid after LCD_MCLK high 0.5 ns
Table 6-83. LCD LIDD Mode Timing Characteristics
No. PARAMETER MIN MAX UNIT
4 td(LCD_D_V) Delay time, LCD_MCLK high to LCD_D[15:0] valid (write) -0.5 10 ns
5 td(LCD_D_I) Delay time, LCD_MCLK high to LCD_D[15:0] invalid (write) -0.5 10 ns
6 td(LCD_E_A) Delay time, LCD_MCLK high to LCD_AC_ENB_CS low -0.5 7 ns
7 td(LCD_E_I) Delay time, LCD_MCLK high to LCD_AC_ENB_CS high -0.5 7 ns
8 td(LCD_A_A) Delay time, LCD_MCLK high to LCD_VSYNC low -0.5 8 ns
9 td(LCD_A_I) Delay time, LCD_MCLK high to LCD_VSYNC high -0.5 8 ns
10 td(LCD_W_A) Delay time, LCD_MCLK high to LCD_HSYNC low -0.5 8 ns
11 td(LCD_W_I) Delay time, LCD_MCLK high to LCD_HSYNC high -0.5 8 ns
12 td(LCD_STRB_A) Delay time, LCD_MCLK high to LCD_PCLK active -0.5 12 ns
13 td(LCD_STRB_I) Delay time, LCD_MCLK high to LCD_PCLK inactive -0.5 12 ns
14 td(LCD_D_Z) Delay time, LCD_MCLK high to LCD_D[15:0] in 3-state -0.5 12 ns
15 td(Z_LCD_D) Delay time, LCD_MCLK high to LCD_D[15:0] (valid from 3-state) -0.5 12 ns
Figure 6-47. Character Display HD44780 Write
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LCD_AC_ENB_CS
LCD_PCLK
LCD_VSYNC
LCD_HSYNC
R_SU
R_STROBE R_HOLD
(0–31)
(1–63) (1–5)
CS_DELAY
Not
Used
RS
R/W
LCD_MCLK
1
2 3
W_SU W_STROBE
W_HOLD
(0–31) (1–63)
(1–15)
CS_DELAY
89
12 13
10 11
Not
Used
LCD_D[7:0]
14 17
16
Read
Data
15 45
E0
E1
12 13
Data[7:0]
Write Instruction
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Figure 6-48. Character Display HD44780 Read
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LCD_D[15:0]
LCD_AC_ENB_CS
(async mode)
LCD_VSYNC
LCD_HSYNC
LCD_MCLK
LCD_PCLK
4
W_SU W_STROBE
W_HOLD
(0−31) (1−63)
(1−15)
CS_DELAY
CS0
CS1
A0
R/W
E
Clock
1
23
W_SU W_STROBE
W_HOLD
(0−31) (1−63)
(1−15)
CS_DELAY
545
6767
89
12 13
Write Address Write Data
12 13
10 11 10 11
Data[15:0]
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Figure 6-49. Micro-Interface Graphic Display 6800 Write
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LCD_D[15:0]
LCD_AC_ENB_CS
(async mode)
LCD_VSYNC
LCD_HSYNC
LCD_MCLK
LCD_PCLK
4
W_SU W_STROBE
W_HOLD
(0−31) (1−63)
(1−15)
CS_DELAY
CS0
CS1
A0
R/W
E
Clock
1
23
R_SU
R_STROBE R_HOLD
(0−31)
(1−63 (1−15)
CS_DELAY
514 15
6767
89
12 13
17
16
Write Address
Read
Data
10 11
1213
Data[15:0]
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Figure 6-50. Micro-Interface Graphic Display 6800 Read
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Read
Data
LCD_D[15:0]
LCD_AC_ENB_CS
(async mode)
LCD_VSYNC
LCD_HSYNC
LCD_MCLK
LCD_PCLK
R_SU
R_STROBE R_HOLD
(0−31)
(1−63) (1−15)
CS_DELAY
CS0
CS1
A0
R/W
E
Clock
1
23
R_STROBE R_HOLD
(1−63) (1−15)
CS_DELAY
14 15
6767
89
12 13
17
16
14 17
16 15
12 13
Data[15:0]
R_SU
(0−31)
Read
Status
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Figure 6-51. Micro-Interface Graphic Display 6800 Status
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LCD_D[15:0]
LCD_AC_ENB_CS
(async mode)
LCD_VSYNC
LCD_HSYNC
LCD_MCLK
LCD_PCLK
4
W_SU W_STROBE
W_HOLD
(0−31) (1−63)
(1−15)
CS_DELAY
DATA[15:0]
CS0
CS1
A0
WR
RD
Clock
1
23
W_SU W_STROBE
W_HOLD
(0−31) (1−63)
(1−15)
CS_DELAY
545
6767
89
10 11
Write Address Write Data
10 11
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Figure 6-52. Micro-Interface Graphic Display 8080 Write
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LCD_D[15:0]
LCD_AC_ENB_CS
(async mode)
LCD_VSYNC
LCD_HSYNC
LCD_MCLK
LCD_PCLK
4
W_SU W_STROBE
W_HOLD
(0−31) (1−63)
(1−15)
CS_DELAY
CS0
CS1
A0
WR
RD
Clock
1
2 3
R_SU
R_STROBE R_HOLD
(0−31)
(1−63) (1−15)
CS_DELAY
514 15
6 7 6 7
89
12 13
1716
Read
Data
10 11
Data[15:0]
Write Address
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Figure 6-53. Micro-Interface Graphic Display 8080 Read
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LCD_D[15:0]
LCD_AC_ENB_CS
LCD_VSYNC
LCD_HSYNC
LCD_MCLK
LCD_PCLK
R_SU
R_STROBE R_HOLD
(0−31)
(1−63) (1−15)
CS_DELAY
CS0
CS1
A0
WR
RD
Clock
1
23
R_STROBE R_HOLD
(1−63) (1−15)
CS_DELAY
14 15
676
8
12 13
1716
Read Status
14 17
16
Read Data
15
12 13
Data[15:0]
7
9
R_SU
(0−31)
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Figure 6-54. Micro-Interface Graphic Display 8080 Status
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6.21.2 LCD Raster Mode
Table 6-84. LCD Raster Mode Timing
See Figure 6-55 through Figure 6-59
No. PARAMETER MIN MAX UNIT
1 tc(PIXEL_CLK) Cycle time, pixel clock 26.6 ns
2 tw(PIXEL_CLK_H) Pulse duration, pixel clock high 10 ns
3 tw(PIXEL_CLK_L) Pulse duration, pixel clock low 10 ns
4 td(LCD_D_V) Delay time, LCD_PCLK high to LCD_D[15:0] valid (write) -0.5 9 ns
5 td(LCD_D_IV) Delay time, LCD_PCLK high to LCD_D[15:0] invalid (write) -0.5 9 ns
6 td(LCD_AC_ENB_CS_A)Delay time, LCD_PCLK low to LCD_AC_ENB_CS high S2 - 0.5(1) S2 + 9(1) ns
7 td(LCD_AC_ENB_CS_I) Delay time, LCD_PCLK low to LCD_AC_ENB_CS low S2 - 0.5(1) S2 + 9(1) ns
8 td(LCD_VSYNC_A) Delay time, LCD_PCLK low to LCD_VSYNC high(2) -0.5 12 ns
9 td(LCD_VSYNC_I) Delay time, LCD_PCLK low to LCD_VSYNC low(2) -0.5 12 ns
10 td(LCD_HSYNC_A) Delay time, LCD_PCLK high to LCD_HSYNC high(2) -0.5 12 ns
11 td(LCD_HSYNC_I) Delay time, LCD_PCLK high to LCD_HSYNC low(2) -0.5 12 ns
(1) S2 = SYSCLK2 cycle time in ns
(2) The activation edge of the control signals LCD_VSYNC and LCD_HSYNC may be programmed to either the rising or falling edge of the
pixel clock through the LCD (RASTER_TIMING_2) register. In Figure 6-56 through Figure 6-59, all signal polarity and activation edges
are based on the default LCD (RASTER_TIMING_2) register settings.
Frame-to-frame timing is derived through the following parameters in the LCD (RASTER_TIMING_1)
register:
• Vertical front porch (VFP)
• Vertical sync pulse width (VSW)
• Vertical back porch (VBP)
• Lines per panel (LPP)
Line-to-line timing is derived through the following parameters in the LCD (RASTER_TIMING_0) register:
• Horizontal front porch (HFP)
• Horizontal sync pulse width (HSW)
• Horizontal back porch (HBP)
• Pixels per panel (PPL)
.LCD_AC_ENB_CS timing is derived through the following parameter in the LCD (RASTER_TIMING_2)
register:
• AC bias frequency (ACB)
The display format produced in raster mode is shown in Figure 6-55. An entire frame is delivered one line
at a time. The first line delivered starts at data pixel (1, 1) and ends at data pixel (P, 1). The last line
delivered starts at data pixel (1, L) and ends at data pixel (P, L). The beginning of each new frame is
denoted by the activation of I/O signal LCD_VSYNC. The beginning of each new line is denoted by the
activation of I/O signal LCD_HSYNC.
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LCD
1, 1 2, 1 3, 1
1, 2 2, 2
1, 3
P, 1
P−1,
1
P−2,
P, 2
P−1,
2
P, 3
1, L
1,
L−1
1,
L−2
3, L2, L
2,
L−1
P, L
P−1,
L−1
P,
L−1
P−1,
L
P,
L−2
P−2,
L
Data Pixels (From 1 to P)
Data Lines (From 1 to L)
1
TMS320C6745, TMS320C6747
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Figure 6-55. LCD Raster-Mode Display Format
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LCD_HSYNC
Hsync
LCD_VSYNC
(1 to 64)
VSW
(1 to 64)
VSW
(0 to 255)
VFP
(1 to 1024)
Frame Time 70 Hz~
LPP
(0 to 255)
LCD_D[15:0]
1, 1
P, 1
1, 2
P, 2
1, L
P, L
1, L-1
P, L-1
Line
Time
Vsync
Data
Active TFT
LCD_AC_ENB_CS
VBP
CLK
LCD_HSYNC Hsync
10 11
LCD_PCLK
LCD_D[15:0] 1, 1 2, 2 P, 2
P, 1
2, 1 1, 2
PLL
16 × (1 to 1024)
HBP
(1 to 256)
Line 1
(1 to 256)
HFP
(1 to 64)
HSW PLL
16 × (1 to 1024)
Line 2
Data
LCD_AC_ENB_CS Enable
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Figure 6-56. LCD Raster-Mode Active
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LCD_HSYNC LP
LCD_VSYNC
VSW = 1
(1 to 1024)
Frame Time ~ 70Hz
LPP
LCD_D[7:0]
1, L−2
P, L−2
1, L−4
P, L−4
Line
Time
LCD_HSYNC LP
10 11
LCD_PCLK
LCD_D[7:0] 1, 5 2, 6 P, 6
P, 52, 5 1, 6
PPL
16 (1 to 1024)
HBP
(1 to 256)
Line 5
HFP
(1 to 64)
HSW PPL
16 (1 to 2024)
Line 6
1, 1:
P, 1
1, 5:
P, 5
1, L−1
P, L−1
1, L
1, L−1
P, L−1
1, L−3
P, L−3
(1 to 64)
VSW = 1
(1 to 64)
VFP = 0
VBP = 0 VFP = 0
VBP = 0
FP
Data
CP
Data
Passive STN
LCD_AC_ENB_CS M
ACB
(0 to 255)
ACB
(0 to 255)
1, 4:
P, 4
1, 3:
P, 3
1, 2:
P, 2
1, L:
P, L
1, 6:
P, 6
1, 2
P, 2
1, 1
P, 1
1, L
P, L
(1 to 256)
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Figure 6-57. LCD Raster-Mode Passive
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LCD_HSYNC
LCD_PCLK
(active mode)
LCD_D[15:0]
(active mode) 1, L P, L
2, L
PPL
16 ×(1 to 1024)
HBP
(1 to 256
Line L
(1 to 256)
HFP
(1 to 64)
HSW PPL
16 ×(1 to 1024)
Line 1 (Passive Only)
LCD_VSYNC
LCD_PCLK
(passive mode)
LCD_AC_ENB_CS
LCD_D[7:0]
(passive mode) 1, L 2, 1 P, 1
P, L
2, L 1, 1
10 11
8
6
4
4
5
5
1
2 3
1
2 3
VSW = 1
VFP = 0
VBP = 0
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Figure 6-58. LCD Raster-Mode Control Signal Activation
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LCD_HSYNC
LCD_PCLK
(active mode)
LCD_D[15:0]
(active mode)
PPL
16 ×(1 to 1024)
HBP
(1 to 256
Line 1 for passive
(1 to 256)
HFP
(1 to 64)
HSW PPL
16 ×(1 to 1024)
Line 1 for active
LCD_VSYNC
LCD_PCLK
(passive mode)
LCD_AC_ENB_CS
LCD_D[7:0]
(passive mode) 1, 1 2, 2 P, 2
P, 1
2, 1 1, 2
10 11
9
7
45
1
2 3
VSW = 1
VFP = 0
VBP = 0
P, 11, 1 2, 1
45
1
3
4
Line 2 for passive
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Figure 6-59. LCD Raster-Mode Control Signal Deactivation
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6.22 Timers
The timers support the following features:
• Configurable as single 64-bit timer or two 32-bit timers
• Period timeouts generate interrupts, DMA events or external pin events
• 8 32-bit compare registers
• Compare matches generate interrupt events
• Capture capability
• 64-bit Watchdog capability (Timer64P1 only)
Table 6-85 lists the timer registers.
Table 6-85. Timer Registers
Timer64P 0 Timer64P 1 ACRONYM REGISTER DESCRIPTION
0x01C2 0000 0x01C2 1000 REV Revision Register
0x01C2 0004 0x01C2 1004 EMUMGT Emulation Management Register
0x01C2 0008 0x01C2 1008 GPINTGPEN GPIO Interrupt and GPIO Enable Register
0x01C2 000C 0x01C2 100C GPDATGPDIR GPIO Data and GPIO Direction Register
0x01C2 0010 0x01C2 1010 TIM12 Timer Counter Register 12
0x01C2 0014 0x01C2 1014 TIM34 Timer Counter Register 34
0x01C2 0018 0x01C2 1018 PRD12 Timer Period Register 12
0x01C2 001C 0x01C2 101C PRD34 Timer Period Register 34
0x01C2 0020 0x01C2 1020 TCR Timer Control Register
0x01C2 0024 0x01C2 1024 TGCR Timer Global Control Register
0x01C2 0028 0x01C2 1028 WDTCR Watchdog Timer Control Register
0x01C2 0034 0x01C2 1034 REL12 Timer Reload Register 12
0x01C2 0038 0x01C2 1038 REL34 Timer Reload Register 34
0x01C2 003C 0x01C2 103C CAP12 Timer Capture Register 12
0x01C2 0040 0x01C2 1040 CAP34 Timer Capture Register 34
0x01C2 0044 0x01C2 1044 INTCTLSTAT Timer Interrupt Control and Status Register
0x01C2 0060 0x01C2 1060 CMP0 Compare Register 0
0x01C2 0064 0x01C2 1064 CMP1 Compare Register 1
0x01C2 0068 0x01C2 1068 CMP2 Compare Register 2
0x01C2 006C 0x01C2 106C CMP3 Compare Register 3
0x01C2 0070 0x01C2 1070 CMP4 Compare Register 4
0x01C2 0074 0x01C2 1074 CMP5 Compare Register 5
0x01C2 0078 0x01C2 1078 CMP6 Compare Register 6
0x01C2 007C 0x01C2 107C CMP7 Compare Register 7
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TM64P0_OUT12
56
1
2
4
4
3
TM64P0_IN12
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6.22.1 Timer Electrical Data/Timing
Table 6-86. Timing Requirements for Timer Input(1) (2) (see Figure 6-60)
No. PARAMETER MIN MAX UNIT
1 tc(TM64Px_IN12) Cycle time, TM64Px_IN12 4P ns
2 tw(TINPH) Pulse duration, TM64Px_IN12 high 0.45C 0.55C ns
3 tw(TINPL) Pulse duration, TM64Px_IN12 low 0.45C 0.55C ns
4 tt(TM64Px_IN12) Transition time, TM64Px_IN12 0.25P or 10(3) ns
(1) P = OSCIN cycle time in ns.
(2) C = TM64P0_IN12 cycle time in ns. For example, when TM64Px_IN12 frequency is 27 MHz, use C = 37.037 ns
(3) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
Figure 6-60. Timer Timing
Table 6-87. Switching Characteristics Over Recommended Operating Conditions for Timer Output (1)
No. PARAMETER MIN MAX UNIT
5 tw(TOUTH) Pulse duration, TM64P0_OUT12 high 4P ns
6 tw(TOUTL) Pulse duration, TM64P0_OUT12 low 4P ns
(1) P = OSCIN cycle time in ns. For example, when OSCIN frequency is 27 MHz, use P = 37.037 ns.
Figure 6-61. Timer Timing
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Peripheral
Configuration
Bus
Noise
Filter
Noise
Filter
Clock Prescaler
I2CPSCx Prescaler
Register
Bit Clock Generator
I2CCLKHx Clock Divide
High Register
I2CCLKLx Clock Divide
Low Register
Control
I2CCOARx Own Address
Register
I2CSARx Slave Address
Register
I2CCMDRx Mode Register
I2CEMDRx Extended Mode
Register
I2CCNTx Data Count
Register
I2CPID1 Peripheral ID
Register 1
I2CPID2 Peripheral ID
Register 2
Transmit
I2CXSRx Transmit Shift
Register
I2CDXRx Transmit Buffer
Receive
I2CDRRx Receive Buffer
I2CRSRx
Receive Shift
Register
I2Cx_SCL
I2Cx_SDA Interrupt/DMA
I2CIERx Interrupt Enable
Register
I2CSTRx Interrupt Status
Register
I2CSRCx Interrupt Source
Register
Control
I2CPFUNC Pin Function
Register
I2CPDIR Pin Direction
Register
I2CPDIN Pin Data In
Register
I2CPDOUT Pin Data Out
Register
I2CPDSET Pin Data Set
Register
I2CPDCLR Pin Data Clear
Register
Interrupt DMA
Requests
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6.23 Inter-Integrated Circuit Serial Ports (I2C0, I2C1)
6.23.1 I2C Device-Specific Information
Having two I2C modules on the C6745/6747 simplifies system architecture, since one module may be
used by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to
communicate with other controllers in a system or to implement a user interface. Figure 6-62 is block
diagram of the C6745/6747 I2C Module.
Each I2C port supports:
• Compatible with Philips® I2C Specification Revision 2.1 (January 2000)
• Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise Filter to Remove Noise 50 ns or less
• Seven- and Ten-Bit Device Addressing Modes
• Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
• Events: DMA, Interrupt, or Polling
• General-Purpose I/O Capability if not used as I2C
Figure 6-62. I2C Module Block Diagram
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6.23.2 I2C Peripheral Registers Description(s)
Table 6-88 is the list of the I2C registers.
Table 6-88. Inter-Integrated Circuit (I2C) Registers
I2C0 I2C1 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS
0x01C2 2000 0x01E2 8000 ICOAR I2C Own Address Register
0x01C2 2004 0x01E2 8004 ICIMR I2C Interrupt Mask Register
0x01C2 2008 0x01E2 8008 ICSTR I2C Interrupt Status Register
0x01C2 200C 0x01E2 800C ICCLKL I2C Clock Low-Time Divider Register
0x01C2 2010 0x01E2 8010 ICCLKH I2C Clock High-Time Divider Register
0x01C2 2014 0x01E2 8014 ICCNT I2C Data Count Register
0x01C2 2018 0x01E2 8018 ICDRR I2C Data Receive Register
0x01C2 201C 0x01E2 801C ICSAR I2C Slave Address Register
0x01C2 2020 0x01E2 8020 ICDXR I2C Data Transmit Register
0x01C2 2024 0x01E2 8024 ICMDR I2C Mode Register
0x01C2 2028 0x01E2 8028 ICIVR I2C Interrupt Vector Register
0x01C2 202C 0x01E2 802C ICEMDR I2C Extended Mode Register
0x01C2 2030 0x01E2 8030 ICPSC I2C Prescaler Register
0x01C2 2034 0x01E2 8034 REVID1 I2C Revision Identification Register 1
0x01C2 2038 0x01E2 8038 REVID2 I2C Revision Identification Register 2
0x01C2 2048 0x01E2 8048 ICPFUNC I2C Pin Function Register
0x01C2 204C 0x01E2 804C ICPDIR I2C Pin Direction Register
0x01C2 2050 0x01E2 8050 ICPDIN I2C Pin Data In Register
0x01C2 2054 0x01E2 8054 ICPDOUT I2C Pin Data Out Register
0x01C2 2058 0x01E2 8058 ICPDSET I2C Pin Data Set Register
0x01C2 205C 0x01E2 805C ICPDCLR I2C Pin Data Clear Register
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6.23.3 I2C Electrical Data/Timing
6.23.3.1 Inter-Integrated Circuit (I2C) Timing
Table 6-89 and Table 6-90 assume testing over recommended operating conditions (see Figure 6-63 and
Figure 6-64).
Table 6-89. I2C Input Timing Requirements
No. PARAMETER MIN MAX UNIT
Standard Mode 10
1 tc(SCL) Cycle time, I2Cx_SCL μs
Fast Mode 2.5
Standard Mode 4.7
2 tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low μs
Fast Mode 0.6
Standard Mode 4
3 th(SCLL-SDAL) Hold time, I2Cx_SCL low after I2Cx_SDA low μs
Fast Mode 0.6
Standard Mode 4.7
4 tw(SCLL) Pulse duration, I2Cx_SCL low μs
Fast Mode 1.3
Standard Mode 4
5 tw(SCLH) Pulse duration, I2Cx_SCL high μs
Fast Mode 0.6
Standard Mode 250
6 tsu(SDA-SCLH) Setup time, I2Cx_SDA before I2Cx_SCL high ns
Fast Mode 100
Standard Mode 0
7 th(SDA-SCLL) Hold time, I2Cx_SDA after I2Cx_SCL low μs
Fast Mode 0 0.9
Standard Mode 4.7
8 tw(SDAH) Pulse duration, I2Cx_SDA high μs
Fast Mode 1.3
Standard Mode 1000
9 tr(SDA) Rise time, I2Cx_SDA ns
Fast Mode 20 + 0.1Cb300
Standard Mode 1000
10 tr(SCL) Rise time, I2Cx_SCL ns
Fast Mode 20 + 0.1Cb300
Standard Mode 300
11 tf(SDA) Fall time, I2Cx_SDA ns
Fast Mode 20 + 0.1Cb300
Standard Mode 300
12 tf(SCL) Fall time, I2Cx_SCL ns
Fast Mode 20 + 0.1Cb300
Standard Mode 4
13 tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high μs
Fast Mode 0.6
Standard Mode N/A
14 tw(SP) Pulse duration, spike (must be suppressed) ns
Fast Mode 0 50
Standard Mode 400
15 CbCapacitive load for each bus line pF
Fast Mode 400
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10
8
4
3
7
12
5
614
2
3
13
Stop Start Repeated
Start
Stop
I2Cx_SDA
I2Cx_SCL
1
11 9
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Table 6-90. I2C Switching Characteristics(1)
No. PARAMETER MIN MAX UNIT
Standard Mode 10
16 tc(SCL) Cycle time, I2Cx_SCL μs
Fast Mode 2.5
Standard Mode 4.7
17 tsu(SCLH-SDAL) Setup time, I2Cx_SCL high before I2Cx_SDA low μs
Fast Mode 0.6
Standard Mode 4
18 th(SDAL-SCLL) Hold time, I2Cx_SCL low after I2Cx_SDA low μs
Fast Mode 0.6
Standard Mode 4.7
19 tw(SCLL) Pulse duration, I2Cx_SCL low μs
Fast Mode 1.3
Standard Mode 4
20 tw(SCLH) Pulse duration, I2Cx_SCL high μs
Fast Mode 0.6
Standard Mode 250
21 tsu(SDAV-SCLH) Setup time, I2Cx_SDA valid before I2Cx_SCL high ns
Fast Mode 100
Standard Mode 0
22 th(SCLL-SDAV) Hold time, I2Cx_SDA valid after I2Cx_SCL low μs
Fast Mode 0 0.9
Standard Mode 4.7
23 tw(SDAH) Pulse duration, I2Cx_SDA high μs
Fast Mode 1.3
Standard Mode 4
28 tsu(SCLH-SDAH) Setup time, I2Cx_SCL high before I2Cx_SDA high μs
Fast Mode 0.6
(1) I2C must be configured correctly to meet the timings in Table 6-90.
Figure 6-63. I2C Receive Timings
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25
23
19
18
22
27
20
21
17
18
28
Stop Start Repeated
Start
Stop
I2Cx_SDA
I2Cx_SCL
16
26 24
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Figure 6-64. I2C Transmit Timings
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6.24 Universal Asynchronous Receiver/Transmitter (UART)
C6745/6747 has three UART peripherals. Each UART has the following features:
• 16-byte storage space for both the transmitter and receiver FIFOs
• Autoflow control signals (CTS, RTS) on UART0 only
• 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• DMA signaling capability for both received and transmitted data
• Programmable auto-rts and auto-cts for autoflow control
• Programmable Baud Rate up to 3MBaud
• Programmable Oversampling Options of x13 and x16
• Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
• Prioritized interrupts
• Programmable serial data formats
– 5, 6, 7, or 8-bit characters
– Even, odd, or no parity bit generation and detection
– 1, 1.5, or 2 stop bit generation
• False start bit detection
• Line break generation and detection
• Internal diagnostic capabilities
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
The UART registers are listed in Section 6.24.1
6.24.1 UART Peripheral Registers Description(s)
Table 6-91 is the list of UART registers.
Table 6-91. UART Registers
UART0 UART1 UART2 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS
0x01C4 2000 0x01D0 C000 0x01D0 D000 RBR Receiver Buffer Register (read only)
0x01C4 2000 0x01D0 C000 0x01D0 D000 THR Transmitter Holding Register (write only)
0x01C4 2004 0x01D0 C004 0x01D0 D004 IER Interrupt Enable Register
0x01C4 2008 0x01D0 C008 0x01D0 D008 IIR Interrupt Identification Register (read only)
0x01C4 2008 0x01D0 C008 0x01D0 D008 FCR FIFO Control Register (write only)
0x01C4 200C 0x01D0 C00C 0x01D0 D00C LCR Line Control Register
0x01C4 2010 0x01D0 C010 0x01D0 D010 MCR Modem Control Register
0x01C4 2014 0x01D0 C014 0x01D0 D014 LSR Line Status Register
0x01C4 2018 0x01D0 C018 0x01D0 D018 MSR Modem Status Register
0x01C4 201C 0x01D0 C01C 0x01D0 D01C SCR Scratchpad Register
0x01C4 2020 0x01D0 C020 0x01D0 D020 DLL Divisor LSB Latch
0x01C4 2024 0x01D0 C024 0x01D0 D024 DLH Divisor MSB Latch
0x01C4 2028 0x01D0 C028 0x01D0 D028 REVID1 Revision Identification Register 1
0x01C4 2030 0x01D0 C030 0x01D0 D030 PWREMU_MGMT Power and Emulation Management Register
0x01C4 2034 0x01D0 C034 0x01D0 D034 MDR Mode Definition Register
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3
2
Start
Bit
Data Bits
UART_TXDn
UART_RXDn
5
Data Bits
Bit
Start
4
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6.24.2 UART Electrical Data/Timing
Table 6-92. Timing Requirements for UARTx Receive(1) (see Figure 6-65)
No. PARAMETER MIN MAX UNIT
4 tw(URXDB) Pulse duration, receive data bit (RXDn) 0.96U 1.05U ns
5 tw(URXSB) Pulse duration, receive start bit 0.96U 1.05U ns
(1) U = UART baud time = 1/programmed baud rate.
Table 6-93. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit(1)
(see Figure 6-65)
No. PARAMETER MIN MAX UNIT
1 f(baud) Maximum programmable baud rate D/E (2) (3) MBaud(4)
2 tw(UTXDB) Pulse duration, transmit data bit (TXDn) U - 2 U + 2 ns
3 tw(UTXSB) Pulse duration, transmit start bit U - 2 U + 2 ns
(1) U = UART baud time = 1/programmed baud rate.
(2) D = UART input clock in MHz. The UART(s) input clock source is PLL0_SYSCLK2.
(3) E = UART divisor x UART sampling rate. The UART divisor is set through the UART divisor latch registers (DLL and DLH). The UART
sampling rate is set through the over-sampling mode select bit (OSM_SEL) of the UART mode definition register (MDR).
(4) Baud rate is not indicative of data rate. Actual data rate will be limited by system factors such as EDMA loading, EMIF loading, system
frequency, etc.
Figure 6-65. UART Transmit/Receive Timing
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6.25 USB1 Host Controller Registers (USB1.1 OHCI)
All the device USB interfaces are compliant with Universal Serial Bus Specification, Revision 1.1.
Table 6-94 is the list of USB Host Controller registers.
Table 6-94. USB1 Host Controller Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E2 5000 HCREVISION OHCI Revision Number Register
0x01E2 5004 HCCONTROL HC Operating Mode Register
0x01E2 5008 HCCOMMANDSTATUS HC Command and Status Register
0x01E2 500C HCINTERRUPTSTATUS HC Interrupt and Status Register
0x01E2 5010 HCINTERRUPTENABLE HC Interrupt Enable Register
0x01E2 5014 HCINTERRUPTDISABLE HC Interrupt Disable Register
0x01E2 5018 HCHCCA HC HCAA Address Register(1)
0x01E2 501C HCPERIODCURRENTED HC Current Periodic Register(1)
0x01E2 5020 HCCONTROLHEADED HC Head Control Register(1)
0x01E2 5024 HCCONTROLCURRENTED HC Current Control Register(1)
0x01E2 5028 HCBULKHEADED HC Head Bulk Register(1)
0x01E2 502C HCBULKCURRENTED HC Current Bulk Register(1)
0x01E2 5030 HCDONEHEAD HC Head Done Register(1)
0x01E2 5034 HCFMINTERVAL HC Frame Interval Register
0x01E2 5038 HCFMREMAINING HC Frame Remaining Register
0x01E2 503C HCFMNUMBER HC Frame Number Register
0x01E2 5040 HCPERIODICSTART HC Periodic Start Register
0x01E2 5044 HCLSTHRESHOLD HC Low-Speed Threshold Register
0x01E2 5048 HCRHDESCRIPTORA HC Root Hub A Register
0x01E2 504C HCRHDESCRIPTORB HC Root Hub B Register
0x01E2 5050 HCRHSTATUS HC Root Hub Status Register
0x01E2 5054 HCRHPORTSTATUS1 HC Port 1 Status and Control Register(2)
0x01E2 5058 HCRHPORTSTATUS2 HC Port 2 Status and Control Register(3)
(1) Restrictions apply to the physical addresses used in these registers.
(2) Connected to the integrated USB1.1 phy pins (USB1_DM, USB1_DP).
(3) Although the controller implements two ports, the second port cannot be used.
Table 6-95. Switching Characteristics Over Recommended Operating Conditions for USB1
LOW SPEED FULL SPEED
No. PARAMETER UNIT
MIN MAX MIN MAX
U1 trRise time, USB1_DP and USB1_DM signals(1) 75(1) 300(1) 4(1) 20(1) ns
U2 tfFall time, USB1_DP and USB1_DM signals(1) 75(1) 300(1) 4(1) 20(1) ns
U3 tRFM Rise/Fall time matching(2) 80(2) 120(2) 90(2) 110(2) %
U4 VCRS Output signal cross-over voltage(1) 1.3(1) 2(1) 1.3(1) 2(1) V
U5 tjDifferential propagation jitter(3) -25(3) 25(3) -2(3) 2(3) ns
U6 fop Operating frequency(4) 1.5 12 MHz
(1) Low Speed: CL= 200 pF. High Speed: CL= 50pF
(2) tRFM =( tr/tf) x 100
(3) t jr = t px(1) - tpx(0)
(4) fop = 1/tper
6.25.1 USB1 Unused Signal Configuration
If USB1 is unused, then the USB1 signals should be configured as shown in Section 3.6.23.
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6.26 USB0 OTG (USB2.0 OTG)
The C6745/6747 USB2.0 peripheral supports the following features:
• USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s - C6747 only) and full speed (FS: 12 Mb/s)
• USB 2.0 host at speeds HS (C6747 only), FS, and low speed (LS: 1.5 Mb/s)
• All transfer modes (control, bulk, interrupt, and isochronous)
• 4 Transmit (TX) and 4 Receive (RX) endpoints in addition to endpoint 0
• FIFO RAM
– 4K endpoint
– Programmable size
• Integrated USB 2.0 High Speed PHY
• Connects to a standard Charge Pump for VBUS 5 V generation
• RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
Important Notice: On the original device pinout (marked "A" in the lower right corner of the package),
pins USB0_VSSA33 (ZKB package pin H4; PTP package pin 139) and USB0_VSSA (ZKB package pin
F3; PTP package pin 136) were connected to ground outside the package. For more robust ESD
performance, the USB0 ground references are now connected inside the package on packages marked
"B" and the package pins are unconnected. This change will require that any external filter circuits
previously referenced to ground at these pins will need to reference the board ground instead.
Important Notice: The USB0 controller module clock (PLL0_SYSCLK2) must be greater than 30 MHz for
proper operation of the USB controller. A clock rate of 60 MHz or greater is recommended to avoid data
throughput reduction.
Table 6-96 is the list of USB OTG registers.
Table 6-96. Universal Serial Bus OTG (USB0) Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E0 0000 REVID Revision Register
0x01E0 0004 CTRLR Control Register
0x01E0 0008 STATR Status Register
0x01E0 000C EMUR Emulation Register
0x01E0 0010 MODE Mode Register
0x01E0 0014 AUTOREQ Autorequest Register
0x01E0 0018 SRPFIXTIME SRP Fix Time Register
0x01E0 001C TEARDOWN Teardown Register
0x01E0 0020 INTSRCR USB Interrupt Source Register
0x01E0 0024 INTSETR USB Interrupt Source Set Register
0x01E0 0028 INTCLRR USB Interrupt Source Clear Register
0x01E0 002C INTMSKR USB Interrupt Mask Register
0x01E0 0030 INTMSKSETR USB Interrupt Mask Set Register
0x01E0 0034 INTMSKCLRR USB Interrupt Mask Clear Register
0x01E0 0038 INTMASKEDR USB Interrupt Source Masked Register
0x01E0 003C EOIR USB End of Interrupt Register
0x01E0 0040 - Reserved
0x01E0 0050 GENRNDISSZ1 Generic RNDIS Size EP1
0x01E0 0054 GENRNDISSZ2 Generic RNDIS Size EP2
0x01E0 0058 GENRNDISSZ3 Generic RNDIS Size EP3
0x01E0 005C GENRNDISSZ4 Generic RNDIS Size EP4
0x01E0 0400 FADDR Function Address Register
0x01E0 0401 POWER Power Management Register
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Table 6-96. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E0 0402 INTRTX Interrupt Register for Endpoint 0 plus Transmit Endpoints 1 to 4
0x01E0 0404 INTRRX Interrupt Register for Receive Endpoints 1 to 4
0x01E0 0406 INTRTXE Interrupt Enable Register for INTRTX
0x01E0 0408 INTRRXE Interrupt Enable Register for INTRRX
0x01E0 040A INTRUSB Interrupt Register for Common USB Interrupts
0x01E0 040B INTRUSBE Interrupt Enable Register for INTRUSB
0x01E0 040C FRAME Frame Number Register
0x01E0 040E INDEX Index Register for Selecting the Endpoint Status and Control Registers
0x01E0 040F TESTMODE Register to Enable the USB 2.0 Test Modes
INDEXED REGISTERS
These registers operate on the endpoint selected by the INDEX register
0x01E0 0410 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
(Index register set to select Endpoints 1-4 only)
0x01E0 0412 PERI_CSR0 Control Status Register for Endpoint 0 in Peripheral Mode.
(Index register set to select Endpoint 0)
HOST_CSR0 Control Status Register for Endpoint 0 in Host Mode.
(Index register set to select Endpoint 0)
PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint.
(Index register set to select Endpoints 1-4)
HOST_TXCSR Control Status Register for Host Transmit Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0414 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
(Index register set to select Endpoints 1-4 only)
0x01E0 0416 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint.
(Index register set to select Endpoints 1-4)
HOST_RXCSR Control Status Register for Host Receive Endpoint.
(Index register set to select Endpoints 1-4)
0x01E0 0418 COUNT0 Number of Received Bytes in Endpoint 0 FIFO.
(Index register set to select Endpoint 0)
RXCOUNT Number of Bytes in Host Receive Endpoint FIFO.
(Index register set to select Endpoints 1- 4)
0x01E0 041A HOST_TYPE0 Defines the speed of Endpoint 0
HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
(Index register set to select Endpoints 1-4 only)
0x01E0 041B HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0.
(Index register set to select Endpoint 0)
HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
(Index register set to select Endpoints 1-4 only)
0x01E0 041C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
(Index register set to select Endpoints 1-4 only)
0x01E0 041D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
(Index register set to select Endpoints 1-4 only)
0x01E0 041F CONFIGDATA Returns details of core configuration.
(Index register set to select Endpoint 0)
FIFO
0x01E0 0420 FIFO0 Transmit and Receive FIFO Register for Endpoint 0
0x01E0 0424 FIFO1 Transmit and Receive FIFO Register for Endpoint 1
0x01E0 0428 FIFO2 Transmit and Receive FIFO Register for Endpoint 2
0x01E0 042C FIFO3 Transmit and Receive FIFO Register for Endpoint 3
0x01E0 0430 FIFO4 Transmit and Receive FIFO Register for Endpoint 4
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Table 6-96. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
OTG DEVICE CONTROL
0x01E0 0460 DEVCTL Device Control Register
DYNAMIC FIFO CONTROL
0x01E0 0462 TXFIFOSZ Transmit Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
0x01E0 0463 RXFIFOSZ Receive Endpoint FIFO Size
(Index register set to select Endpoints 1-4 only)
0x01E0 0464 TXFIFOADDR Transmit Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
0x01E0 0466 RXFIFOADDR Receive Endpoint FIFO Address
(Index register set to select Endpoints 1-4 only)
0x01E0 046C HWVERS Hardware Version Register
TARGET ENDPOINT 0 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0480 TXFUNCADDR Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 0482 TXHUBADDR Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0483 TXHUBPORT Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0484 RXFUNCADDR Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 0486 RXHUBADDR Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0487 RXHUBPORT Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 1 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0488 TXFUNCADDR Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 048A TXHUBADDR Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048B TXHUBPORT Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048C RXFUNCADDR Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 048E RXHUBADDR Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 048F RXHUBPORT Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 2 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0490 TXFUNCADDR Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 0492 TXHUBADDR Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0493 TXHUBPORT Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0494 RXFUNCADDR Address of the target function that has to be accessed through the
associated Receive Endpoint.
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Table 6-96. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E0 0496 RXHUBADDR Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 0497 RXHUBPORT Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 3 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 0498 TXFUNCADDR Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 049A TXHUBADDR Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049B TXHUBPORT Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049C RXFUNCADDR Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 049E RXHUBADDR Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 049F RXHUBPORT Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
TARGET ENDPOINT 4 CONTROL REGISTERS, VALID ONLY IN HOST MODE
0x01E0 04A0 TXFUNCADDR Address of the target function that has to be accessed through the
associated Transmit Endpoint.
0x01E0 04A2 TXHUBADDR Address of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A3 TXHUBPORT Port of the hub that has to be accessed through the associated
Transmit Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A4 RXFUNCADDR Address of the target function that has to be accessed through the
associated Receive Endpoint.
0x01E0 04A6 RXHUBADDR Address of the hub that has to be accessed through the associated
Receive Endpoint. This is used only when full speed or low speed
device is connected via a USB2.0 high-speed hub.
0x01E0 04A7 RXHUBPORT Port of the hub that has to be accessed through the associated Receive
Endpoint. This is used only when full speed or low speed device is
connected via a USB2.0 high-speed hub.
CONTROL AND STATUS REGISTER FOR ENDPOINT 0
0x01E0 0502 PERI_CSR0 Control Status Register for Endpoint 0 in Peripheral Mode
HOST_CSR0 Control Status Register for Endpoint 0 in Host Mode
0x01E0 0508 COUNT0 Number of Received Bytes in Endpoint 0 FIFO
0x01E0 050A HOST_TYPE0 Defines the Speed of Endpoint 0
0x01E0 050B HOST_NAKLIMIT0 Sets the NAK Response Timeout on Endpoint 0
0x01E0 050F CONFIGDATA Returns details of core configuration.
CONTROL AND STATUS REGISTER FOR ENDPOINT 1
0x01E0 0510 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0512 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0514 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
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Table 6-96. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E0 0516 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0518 RXCOUNT Number of Bytes in Host Receive endpoint FIFO
0x01E0 051A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 051B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 051C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
0x01E0 051D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 2
0x01E0 0520 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0522 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0524 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0526 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0528 RXCOUNT Number of Bytes in Host Receive endpoint FIFO
0x01E0 052A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 052B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 052C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
0x01E0 052D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 3
0x01E0 0530 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0532 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0534 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0536 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint
(peripheral mode)
HOST_RXCSR Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0538 RXCOUNT Number of Bytes in Host Receive endpoint FIFO
0x01E0 053A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 053B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 053C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
0x01E0 053D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
CONTROL AND STATUS REGISTER FOR ENDPOINT 4
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Table 6-96. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E0 0540 TXMAXP Maximum Packet Size for Peripheral/Host Transmit Endpoint
0x01E0 0542 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint
(peripheral mode)
HOST_TXCSR Control Status Register for Host Transmit Endpoint
(host mode)
0x01E0 0544 RXMAXP Maximum Packet Size for Peripheral/Host Receive Endpoint
0x01E0 0546 PERI_RXCSR Control Status Register for Peripheral Receive Endpoint (peripheral
mode)
HOST_RXCSR Control Status Register for Host Receive Endpoint
(host mode)
0x01E0 0548 RXCOUNT Number of Bytes in Host Receive endpoint FIFO
0x01E0 054A HOST_TXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Transmit endpoint.
0x01E0 054B HOST_TXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Transmit endpoint.
0x01E0 054C HOST_RXTYPE Sets the operating speed, transaction protocol and peripheral endpoint
number for the host Receive endpoint.
0x01E0 054D HOST_RXINTERVAL Sets the polling interval for Interrupt/ISOC transactions or the NAK
response timeout on Bulk transactions for host Receive endpoint.
DMA REGISTERS
0x01E0 1000 DMAREVID DMA Revision Register
0x01E0 1004 TDFDQ DMA Teardown Free Descriptor Queue Control Register
0x01E0 1008 DMAEMU DMA Emulation Control Register
0x01E0 1800 TXGCR[0] Transmit Channel 0 Global Configuration Register
0x01E0 1808 RXGCR[0] Receive Channel 0 Global Configuration Register
0x01E0 180C RXHPCRA[0] Receive Channel 0 Host Packet Configuration Register A
0x01E0 1810 RXHPCRB[0] Receive Channel 0 Host Packet Configuration Register B
0x01E0 1820 TXGCR[1] Transmit Channel 1 Global Configuration Register
0x01E0 1828 RXGCR[1] Receive Channel 1 Global Configuration Register
0x01E0 182C RXHPCRA[1] Receive Channel 1 Host Packet Configuration Register A
0x01E0 1830 RXHPCRB[1] Receive Channel 1 Host Packet Configuration Register B
0x01E0 1840 TXGCR[2] Transmit Channel 2 Global Configuration Register
0x01E0 1848 RXGCR[2] Receive Channel 2 Global Configuration Register
0x01E0 184C RXHPCRA[2] Receive Channel 2 Host Packet Configuration Register A
0x01E0 1850 RXHPCRB[2] Receive Channel 2 Host Packet Configuration Register B
0x01E0 1860 TXGCR[3] Transmit Channel 3 Global Configuration Register
0x01E0 1868 RXGCR[3] Receive Channel 3 Global Configuration Register
0x01E0 186C RXHPCRA[3] Receive Channel 3 Host Packet Configuration Register A
0x01E0 1870 RXHPCRB[3] Receive Channel 3 Host Packet Configuration Register B
0x01E0 2000 DMA_SCHED_CTRL DMA Scheduler Control Register
0x01E0 2800 WORD[0] DMA Scheduler Table Word 0
0x01E0 2804 WORD[1] DMA Scheduler Table Word 1
... ... ...
0x01E0 28FC WORD[63] DMA Scheduler Table Word 63
QUEUE MANAGER REGISTERS
0x01E0 4000 QMGRREVID Queue Manager Revision Register
0x01E0 4008 DIVERSION Queue Diversion Register
0x01E0 4020 FDBSC0 Free Descriptor/Buffer Starvation Count Register 0
0x01E0 4024 FDBSC1 Free Descriptor/Buffer Starvation Count Register 1
0x01E0 4028 FDBSC2 Free Descriptor/Buffer Starvation Count Register 2
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Table 6-96. Universal Serial Bus OTG (USB0) Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01E0 402C FDBSC3 Free Descriptor/Buffer Starvation Count Register 3
0x01E0 4080 LRAM0BASE Linking RAM Region 0 Base Address Register
0x01E0 4084 LRAM0SIZE Linking RAM Region 0 Size Register
0x01E0 4088 LRAM1BASE Linking RAM Region 1 Base Address Register
0x01E0 4090 PEND0 Queue Pending Register 0
0x01E0 4094 PEND1 Queue Pending Register 1
0x01E0 5000 QMEMRBASE[0] Memory Region 0 Base Address Register
0x01E0 5004 QMEMRCTRL[0] Memory Region 0 Control Register
0x01E0 5010 QMEMRBASE[1] Memory Region 1 Base Address Register
0x01E0 5014 QMEMRCTRL[1] Memory Region 1 Control Register
... ... ...
0x01E0 50F0 QMEMRBASE[15] Memory Region 15 Base Address Register
0x01E0 50F4 QMEMRCTRL[15] Memory Region 15 Control Register
0x01E0 600C CTRLD[0] Queue Manager Queue 0 Control Register D
0x01E0 601C CTRLD[1] Queue Manager Queue 1 Control Register D
... ... ...
0x01E0 63FC CTRLD[63] Queue Manager Queue 63 Status Register D
0x01E0 6800 QSTATA[0] Queue Manager Queue 0 Status Register A
0x01E0 6804 QSTATB[0] Queue Manager Queue 0 Status Register B
0x01E0 6808 QSTATC[0] Queue Manager Queue 0 Status Register C
0x01E0 6810 QSTATA[1] Queue Manager Queue 1 Status Register A
0x01E0 6814 QSTATB[1] Queue Manager Queue 1 Status Register B
0x01E0 6818 QSTATC[1] Queue Manager Queue 1 Status Register C
... ... ...
0x01E0 6BF0 QSTATA[63] Queue Manager Queue 63 Status Register A
0x01E0 6BF4 QSTATB[63] Queue Manager Queue 63 Status Register B
0x01E0 6BF8 QSTATC[63] Queue Manager Queue 63 Status Register C
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6.26.1 USB2.0 Electrical Data/Timing
The USB PHY PLL can support input clock of the following frequencies: 12.0 MHz, 13.0 MHz, 19.2 MHz,
20.0 MHz, 24.0 MHz, 26.0 MHz, 38.4 MHz, 40.0 MHz or 48.0 MHz. USB_REFCLKIN jitter tolerance is 50
ppm maximum.
C6747 supports low-speed, full-speed and high-speed.
C6745 supports only low-speed and full-speed.
Table 6-97. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 6-66)
LOW SPEED FULL SPEED HIGH SPEED
1.5 Mbps 12 Mbps 480 Mbps
No. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
1 tr(D) Rise time, USB0_DP and USB0_DM signals(1) 75 300 4 20 0.5 ns
2 tf(D) Fall time, USB0_DP and USB0_DM signals(1) 75 300 4 20 0.5 ns
3 trfM Rise/Fall time, matching(2) 80 120 90 111 – – %
4 VCRS Output signal cross-over voltage(1) 1.3 2 1.3 2 – – V
5 tjr(source)NT Source (Host) Driver jitter, next transition 2 2 (3)ns
tjr(FUNC)NT Function Driver jitter, next transition 25 2 (3) ns
6 tjr(source)PT Source (Host) Driver jitter, paired transition(4) 1 1 (3) ns
tjr(FUNC)PT Function Driver jitter, paired transition 10 1 (3) ns
7 tw(EOPT) Pulse duration, EOP transmitter (5) 1250 1500 160 175 – – ns
8 tw(EOPR) Pulse duration, EOP receiver (5) 670 82 – ns
9 t(DRATE) Data Rate 1.5 12 480 Mb/s
10 ZDRV Driver Output Resistance – – 40.5 49.5 40.5 49.5 Ω
11 ZINP Receiver Input Impedance 100k 100k - - Ω
(1) Low Speed: CL= 200 pF, Full Speed: CL= 50 pF, High Speed: CL= 50 pF
(2) tRFM = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(3) For more detailed information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(4) tjr = tpx(1) - tpx(0)
(5) Must accept as valid EOP
Figure 6-66. USB0 Integrated Transceiver Interface Timing
6.26.2 USB0 Unused Signal Configuration
If USB0 is unused, then the USB0 signals should be configured as shown in Section 3.6.23.
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6.27 Host-Port Interface (UHPI)
6.27.1 HPI Device-Specific Information
The device includes a user-configurable 16-bit Host-port interface (HPI16). See the TMS320C6745/C6747
DSP Peripherals Overview Reference Guide. (SPRUFK9) for more details.
6.27.2 HPI Peripheral Register Description(s)
Table 6-98. HPI Control Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION COMMENTS
0x01E1 0000 PID Peripheral Identification Register The CPU has read/write
0x01E1 0004 PWREMU_MGMT HPI power and emulation management register access to the
PWREMU_MGMT register.
0x01E1 0008 - Reserved
0x01E1 000C GPIO_EN General Purpose IO Enable Register
0x01E1 0010 GPIO_DIR1 General Purpose IO Direction Register 1
0x01E1 0014 GPIO_DAT1 General Purpose IO Data Register 1
0x01E1 0018 GPIO_DIR2 General Purpose IO Direction Register 2
0x01E1 001C GPIO_DAT2 General Purpose IO Data Register 2
0x01E1 0020 GPIO_DIR3 General Purpose IO Direction Register 3
0x01E1 0024 GPIO_DAT3 General Purpose IO Data Register 3
01E1 0028 - Reserved
01E1 002C - Reserved The Host and the CPU both
01E1 0030 HPIC HPI control register have read/write access to the
HPIC register.
HPIA HPI address register The Host has read/write
01E1 0034 (HPIAW)(1) (Write) access to the HPIA registers.
The CPU has only read
HPIA HPI address register
01E1 0038 access to the HPIA registers.
(HPIAR)(1) (Read)
01E1 000C - 01E1 07FF - Reserved
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently.
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6.27.3 HPI Electrical Data/Timing
Table 6-99. Timing Requirements for Host-Port Interface Cycles(1) (2)
No. PARAMETER MIN MAX UNIT
1 tsu(SELV-HSTBL) Setup time, select signals(3) valid before UHPI_HSTROBE low 5 ns
2 th(HSTBL-SELV) Hold time, select signals(3) valid after UHPI_HSTROBE low 2 ns
3 tw(HSTBL) Pulse duration, UHPI_HSTROBE active low 15 ns
4 tw(HSTBH) Pulse duration, UHPI_HSTROBE inactive high between consecutive accesses 2M ns
9 tsu(SELV-HASL) Setup time, selects signals valid before UHPI_HAS low 5 ns
10 th(HASL-SELV) Hold time, select signals valid after UHPI_HAS low 2 ns
11 tsu(HDV-HSTBH) Setup time, host data valid before UHPI_HSTROBE high 5 ns
12 th(HSTBH-HDV) Hold time, host data valid after UHPI_HSTROBE high 2 ns
Hold time, UHPI_HSTROBE high after UHPI_HRDY low. UHPI_HSTROBE should
13 th(HRDYL-HSTBH) not be inactivated until UHPI_HRDY is active (low); otherwise, HPI writes will not 2 ns
complete properly.
16 tsu(HASL-HSTBL) Setup time, UHPI_HAS low before UHPI_HSTROBE low 2 ns
17 th(HSTBL-HASH) Hold time, UHPI_HAS low after UHPI_HSTROBE low 2 ns
(1) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(2) M=SYSCLK2 period (CPU clock frequency)/2 in ns. For example, when running parts at 300 MHz, use M=6.67 ns.
(3) Select signals include: UHPI_HCNTL[1:0], UHPI_HRW and UHPI_HHWIL.
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Table 6-100. Switching Characteristics for Host-Port Interface Cycles(1) (2) (3)
No. PARAMETER MIN MAX UNIT
For HPI Write, UHPI_HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, UHPI_HRDY stays low (ready):
Case 1: Back-to-back HPIA writes (can be
either first or second half-word)
Case 2: HPIA write following a PREFETCH
command (can be either first or second half-
word)
Case 3: HPID write when FIFO is full or
flushing (can be either first or second half-
word)
Case 4: HPIA write and Write FIFO not empty
For HPI Read, UHPI_HRDY can go high (not
Delay time, ready) for these HPI Read conditions:
5 td(HSTBL-HRDYV) UHPI_HSTROBE low to 12 ns
Case 1: HPID read (with auto-increment) and
UHPI_HRDY valid data not in Read FIFO (can only happen to
first half-word of HPID access)
Case 2: First half-word access of HPID Read
without auto-increment
For HPI Read, UHPI_HRDY stays low (ready)
for these HPI Read conditions:
Case 1: HPID read with auto-increment and
data is already in Read FIFO (applies to either
half-word of HPID access)
Case 2: HPID read without auto-increment
and data is already in Read FIFO (always
applies to second half-word of HPID access)
Case 3: HPIC or HPIA read (applies to either
half-word access)
5a td(HASL-HRDYV) Delay time, UHPI_HAS low to UHPI_HRDY valid 13
6 ten(HSTBL-HDLZ) Enable time, HD driven from UHPI_HSTROBE low 2 ns
7 td(HRDYL-HDV) Delay time, UHPI_HRDY low to HD valid 0 ns
8 toh(HSTBH-HDV) Output hold time, HD valid after UHPI_HSTROBE high 1.5 ns
14 tdis(HSTBH-HDHZ) Disable time, HD high-impedance from UHPI_ HSTROBE high 12 ns
For HPI Read. Applies to conditions where
data is already residing in HPID/FIFO:
Case 1: HPIC or HPIA read
Delay time, Case 2: First half-word of HPID read with
15 td(HSTBL-HDV) 15 ns
UHPI_HSTROBE low to HD valid auto-increment and data is already in Read
FIFO
Case 3: Second half-word of HPID read with
or without auto-increment
For HPI Write, UHPI_HRDY can go high (not
ready) for these HPI Write conditions;
otherwise, UHPI_HRDY stays low (ready):
Delay time, Case 1: HPID write when Write FIFO is full
18 td(HSTBH-HRDYV) UHPI_HSTROBE high to (can happen to either half-word) 12 ns
UHPI_HRDY valid Case 2: HPIA write (can happen to either half-
word)
Case 3: HPID write without auto-increment
(only happens to second half-word)
(1) M=SYSCLK2 period (CPU clock frequency)/2 in ns.
(2) UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR
UHPI_HDS2)] OR UHPI_HCS.
(3) By design, whenever UHPI_HCS is driven inactive (high), HPI will drive UHPI_HRDY active (low).
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UHPI_HCS
UHPI_HAS (D)
UHPI_HCNTL[1:0]
UHPI_HR/W
UHPI_HHWIL
UHPI_HSTROBE
UHPI_HD[15:0]
(output)
UHPI_HRDY
1
2
12
1
2
5
6
3
43
1
2
12
1
2
8
14
15
14
8
7
1st Half-Word 2nd Half-Word
6
13
15
(A)(C)
(B)
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A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or
UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.
D. The diagram above assumes UHPI_HAS has been pulled high.
Figure 6-67. UHPI Read Timing (UHPI_HAS Not Used, Tied High)
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UHPI_HAS(A)
UHPI_HCNTL[1:0]
UHPI_HR/W
UHPI_HHWIL
UHPI_HSTROBE(B)
UHPI_HCS
UHPI_HD[15:0]
(output)
UHPI_HRDY
1st Half-Word 2nd Half-Word
75a
14
815
14
86
4
3
10
9
10
9
10
9
10
9
10
910
917 17
16
16
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A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 6-68. UHPI Read Timing (UHPI_HAS Used)
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UHPI_HAS(D)
UHPI_HCNTL[1:0]
UHPI_HR/W
UHPI_HHWIL
UHPI_HSTROBE(A)(C)
UHPI_HCS
UHPI_HD[15:0]
(input)
UHPI_HRDY (B)
212
1
12
2
1
2
1
12
343
1112
18
13
5
185
1112
13
2nd Half-Word1st Half-Word
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A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-
incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur.
C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or
UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE.
D. he diagram above assumes UHPI_HAS has been pulled high.
Figure 6-69. UHPI Write Timing (UHPI_HAS Not Used, Tied High)
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1st Half-Word 2nd Half-Word
12
11
12
11
4
13
3
10
9
10
9
10
9
10
9
10
9
10
9
UHPI_HAS(A)
UHPI_HCNTL[1:0]
UHPI_HR/W
UHPI_HHWIL
UHPI_HSTROBE(B)
UHPI_HCS
UHPI_HD[15:0]
(input)
UHPI_HRDY
1717
16 16
5a
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A. For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle.
B. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2:
[NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS.
Figure 6-70. UHPI Write Timing (UHPI_HAS Used)
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6.28 Power and Sleep Controller (PSC)
The Power and Sleep Controllers (PSC) are responsible for managing transitions of system power on/off,
clock on/off, resets (device level and module level). It is used primarily to provide granular power control
for on chip modules (peripherals and CPU). A PSC module consists of a Global PSC (GPSC) and a set of
Local PSCs (LPSCs). The GPSC contains memory mapped registers, PSC interrupts, a state machine for
each peripheral/module it controls. An LPSC is associated with every module that is controlled by the PSC
and provides clock and reset control.
The PSC includes the following features:
• Provides a software interface to:
– Control module clock enable/disable
– Control module reset
– Control CPU local reset
• Supports ICEpick TAP Router power, clock and reset features. For details on ICEpick features see
http://tiexpressdsp.com/wiki/index.php?title=ICEPICK.
Table 6-101. Power and Sleep Controller (PSC) Registers
PSC0 PSC1 ACRONYM REGISTER DESCRIPTION
BYTE ADDRESS BYTE ADDRESS
0x01C1 0000 0x01E2 7000 REVID Peripheral Revision and Class Information Register
0x01C1 0018 0x01E2 7018 INTEVAL Interrupt Evaluation Register
0x01C1 0040 0x01E2 7040 MERRPR0 Module Error Pending Register 0 (module 0-15) (PSC0)
Module Error Pending Register 0 (module 0-31) (PSC1)
0x01C1 0050 0x01E2 7050 MERRCR0 Module Error Clear Register 0 (module 0-15) (PSC0)
Module Error Clear Register 0 (module 0-31) (PSC1)
0x01C1 0060 0x01E2 7060 PERRPR Power Error Pending Register
0x01C1 0068 0x01E2 7068 PERRCR Power Error Clear Register
0x01C1 0120 0x01E2 7120 PTCMD Power Domain Transition Command Register
0x01C1 0128 0x01E2 7128 PTSTAT Power Domain Transition Status Register
0x01C1 0200 0x01E2 7200 PDSTAT0 Power Domain 0 Status Register
0x01C1 0204 0x01E2 7204 PDSTAT1 Power Domain 1 Status Register
0x01C1 0300 0x01E2 7300 PDCTL0 Power Domain 0 Control Register
0x01C1 0304 0x01E2 7304 PDCTL1 Power Domain 1 Control Register
0x01C1 0400 0x01E2 7400 PDCFG0 Power Domain 0 Configuration Register
0x01C1 0404 0x01E2 7404 PDCFG1 Power Domain 1 Configuration Register
0x01C1 0800 - 0x01E2 7800 - MDSTAT0-MDSTAT15 Module Status nRegister (modules 0-15) (PSC0)
0x01C1 083C 0x01E2 787C MDSTAT0-MDSTAT31 Module Status nRegister (modules 0-31) (PSC1)
0x01C1 0A00 - 0x01E2 7A00 - MDCTL0-MDCTL15 Module Control nRegister (modules 0-15) (PSC0)
0x01C1 0A3C 0x01E2 7A7C MDCTL0-MDCTL31 Module Control nRegister (modules 0-31) (PSC1)
6.28.1 Power Domain and Module Topology
The device includes two PSC modules.
Each PSC module controls clock states for several of the on chip modules, controllers and interconnect
components. Table 6-102 and Table 6-103 lists the set of peripherals/modules that are controlled by the
PSC, the power domain they are associated with, the LPSC assignment and the default (power-on reset)
module states. The module states and terminology are defined in Section 6.28.1.2.
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Table 6-102. PSC0 Default Module Configuration
LPSC Module Name Power Domain Default Module State Auto Sleep/Wake Only
Number
0 EDMA3 Channel Controller AlwaysON (PD0) SwRstDisable —
1 EDMA3 Transfer Controller 0 AlwaysON (PD0) SwRstDisable —
2 EDMA3 Transfer Controller 1 AlwaysON (PD0) SwRstDisable —
3 EMIFA (BR7) AlwaysON (PD0) SwRstDisable —
4 SPI 0 AlwaysON (PD0) SwRstDisable —
5 MMC/SD 0 AlwaysON (PD0) SwRstDisable —
6-8 Not Used — — —
9 UART 0 AlwaysON (PD0) SwRstDisable —
10 SCR0 (Br 0, Br 1, Br 2, Br 8) AlwaysON (PD0) Enable Yes
11 SCR1 (Br 4) AlwaysON (PD0) Enable Yes
12 SCR2 (Br 3, Br 5, Br 6) AlwaysON (PD0) Enable Yes
13 PRUSS AlwaysON (PD0) SwRstDisable —
14 Not Used — — —
15 DSP PD_DSP (PD1) Enable —
Table 6-103. PSC1 Default Module Configuration
LPSC Module Name Power Domain Default Module State Auto Sleep/Wake Only
Number
0 Not Used — — —
1 USB0 (USB2.0) AlwaysON (PD0) SwRstDisable —
2 USB1 (USB1.1) AlwaysON (PD0) SwRstDisable —
3 GPIO AlwaysON (PD0) SwRstDisable —
4 UHPI AlwaysON (PD0) SwRstDisable —
5 EMAC AlwaysON (PD0) SwRstDisable —
6 EMIFB (Br 20) AlwaysON (PD0) SwRstDisable —
7 McASP0 ( + McASP0 FIFO) AlwaysON (PD0) SwRstDisable —
8 McASP1 ( + McASP1 FIFO) AlwaysON (PD0) SwRstDisable —
9 McASP2( + McASP2 FIFO) AlwaysON (PD0) SwRstDisable —
10 SPI 1 AlwaysON (PD0) SwRstDisable —
11 I2C 1 AlwaysON (PD0) SwRstDisable —
12 UART 1 AlwaysON (PD0) SwRstDisable —
13 UART 2 AlwaysON (PD0) SwRstDisable —
14-15 Not Used — — —
16 LCDC AlwaysON (PD0) SwRstDisable —
17 eHRPWM0/1/2 AlwaysON (PD0) SwRstDisable —
18-19 Not Used — — —
20 ECAP0/1/2 AlwaysON (PD0) SwRstDisable —
21 EQEP0/1 AlwaysON (PD0) SwRstDisable —
22-23 Not Used — — —
24 SCR8 (Br 15) AlwaysON (PD0) Enable Yes
25 SCR7 (Br 12) AlwaysON (PD0) Enable Yes
26 SCR12 (Br 18) AlwaysON (PD0) Enable Yes
27-30 Not Used — — —
31 Shared RAM (Br 13) PD_SHRAM Enable Yes
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6.28.1.1 Power Domain States
A power domain can only be in one of the two states: ON or OFF, defined as follows:
• ON: power to the domain is on
• OFF: power to the domain is off
In the device, for both PSC0 and PSC1, the Always ON domain, or PD0 power domain, is always in the
ON state when the chip is powered-on. This domain is not programmable to OFF state.
• On PSC0 PD1/PD_DSP Domain: Controls the sleep state for DSP L1 and L2 Memories
• On PSC1 PD1/PD_SHRAM Domain: Controls the sleep state for the 128K Shared RAM
6.28.1.2 Module States
The PSC defines several possible states for a module. This states are essentially a combination of the
module reset asserted or de-asserted and module clock on/enabled or off/disabled. The module states are
defined in Table 6-104.
Table 6-104. Module States
Module State Module Reset Module Clock Module State Definition
Enable De-asserted On A module in the enable state has its module reset de-asserted and it has its
clock on. This is the normal operational state for a given module
Disable De-asserted Off A module in the disabled state has its module reset de-asserted and it has its
module clock off. This state is typically used for disabling a module clock to
save power. The device is designed in full static CMOS, so when you stop a
module clock, it retains the module’s state. When the clock is restarted, the
module resumes operating from the stopping point.
SyncReset Asserted On A module state in the SyncReset state has its module reset asserted and it has
its clock on. Generally, software is not expected to initiate this state
SwRstDisable Asserted Off A module in the SwResetDisable state has its module reset asserted and it has
its clock disabled. After initial power-on, several modules come up in the
SwRstDisable state. Generally, software is not expected to initiate this state
Auto Sleep De-asserted Off A module in the Auto Sleep state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it can
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and after servicing the request it will
“automatically” transition into the sleep state (with module reset re de-asserted
and module clock disabled), without any software intervention. The transition
from sleep to enabled and back to sleep state has some cycle latency
associated with it. It is not envisioned to use this mode when peripherals are
fully operational and moving data.
Auto Wake De-asserted Off A module in the Auto Wake state also has its module reset de-asserted and its
module clock disabled, similar to the Disable state. However this is a special
state, once a module is configured in this state by software, it will
“automatically” transition to “Enable” state whenever there is an internal
read/write request made to it, and will remain in the “Enabled” state from then
on (with module reset re de-asserted and module clock on), without any
software intervention. The transition from sleep to enabled state has some
cycle latency associated with it. It is not envisioned to use this mode when
peripherals are fully operational and moving data.
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6.29 Programmable Real-Time Unit Subsystem (PRUSS)
The Programmable Real-Time Unit Subsystem (PRUSS) consists of
• Two Programmable Real-Time Units (PRU0 and PRU1) and their associated memories
• An Interrupt Controller (INTC) for handling system interrupt events. The INTC also supports posting
events back to the device level host CPU.
• A Switched Central Resource (SCR) for connecting the various internal and external masters to the
resources inside the PRUSS.
The two PRUs can operate completely independently or in coordination with each other. The PRUs can
also work in coordination with the device level host CPU. This is determined by the nature of the program
which is loaded into the PRUs instruction memory. Several different signaling mechanisms are available
between the two PRUs and the device level host CPU.
The PRUs are optimized for performing embedded tasks that require manipulation of packed memory
mapped data structures, handling of system events that have tight realtime constraints and interfacing with
systems external to the device.
The PRUSS comprises various distinct addressable regions. Externally the subsystem presents a single
64Kbyte range of addresses. The internal interconnect bus (also called switched central resource, or SCR)
of the PRUSS decodes accesses for each of the individual regions. The PRUSS memory map is
documented in Table 6-105 and in Table 6-106. Note that these two memory maps are implemented
inside the PRUSS and are local to the components of the PRUSS.
Table 6-105. Programmable Real-Time Unit Subsystem (PRUSS) Local Instruction Space Memory Map
BYTE ADDRESS PRU0 PRU1
0x0000 0000 - 0x0000 0FFF PRU0 Instruction RAM PRU1 Instruction RAM
Table 6-106. Programmable Real-Time Unit Subsystem (PRUSS) Local Data Space Memory Map
BYTE ADDRESS PRU0 PRU1
0x0000 0000 - 0x0000 01FF Data RAM 0 (1) Data RAM 1 (1)
0x0000 0200 - 0x0000 1FFF Reserved Reserved
0x0000 2000 - 0x0000 21FF Data RAM 1 (1) Data RAM 0 (1)
0x0000 2200 - 0x0000 3FFF Reserved Reserved
0x0000 4000 - 0x0000 6FFF INTC Registers INTC Registers
0x0000 7000 - 0x0000 73FF PRU0 Control Registers PRU0 Control Registers
0x0000 7400 - 0x0000 77FF Reserved Reserved
0x0000 7800 - 0x0000 7BFF PRU1 Control Registers PRU1 Control Registers
0x0000 7C00 - 0xFFFF FFFF Reserved Reserved
(1) Note that PRU0 accesses Data RAM0at address 0x0000 0000, also PRU1 accesses Data RAM1at address 0x0000 0000. Data RAM0
is intended to be the primary data memory for PRU0 and Data RAM1 is intended to be the primary data memory for PRU1. However for
passing information between PRUs, each PRU can access the data ram of the ‘other’ PRU through address 0x0000 2000.
The global view of the PRUSS internal memories and control ports is documented in Table 6-107. The
offset addresses of each region are implemented inside the PRUSS but the global device memory
mapping places the PRUSS slave port in the address range 0x01C3 0000-0x01C3 FFFF. The PRU0 and
PRU1 can use either the local or global addresses to access their internal memories, but using the local
addresses will provide access time several cycles faster than using the global addresses. This is because
when accessing via the global address the access needs to be routed through the switch fabric outside
PRUSS and back in through the PRUSS slave port.
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Table 6-107. Programmable Real-Time Unit Subsystem (PRUSS) Global Memory Map
BYTE ADDRESS REGION
0x01C3 0000 - 0x01C3 01FF Data RAM 0
0x01C3 0200 - 0x01C3 1FFF Reserved
0x01C3 2000 - 0x01C3 21FF Data RAM 1
0x01C3 2200 - 0x01C3 3FFF Reserved
0x01C3 4000 - 0x01C3 6FFF INTC Registers
0x01C3 7000 - 0x01C3 73FF PRU0 Control Registers
0x01C3 7400 - 0x01C3 77FF PRU0 Debug Registers
0x01C3 7800 - 0x01C3 7BFF PRU1 Control Registers
0x01C3 7C00 - 0x01C3 7FFF PRU1 Debug Registers
0x01C3 8000 - 0x01C3 8FFF PRU0 Instruction RAM
0x01C3 9000 - 0x01C3 BFFF Reserved
0x01C3 C000 - 0x01C3 CFFF PRU1 Instruction RAM
0x01C3 D000 - 0x01C3 FFFF Reserved
Each of the PRUs can access the rest of the device memory (including memory mapped peripheral and
configuration registers) using the global memory space addresses.
6.29.1 PRUSS Register Descriptions
Table 6-108. Programmable Real-Time Unit Subsystem (PRUSS) Control / Status Registers
PRU0 BYTE ADDRESS PRU1 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01C3 7000 0x01C3 7800 CONTROL PRU Control Register
0x01C3 7004 0x01C3 7804 STATUS PRU Status Register
0x01C3 7008 0x01C3 7808 WAKEUP PRU Wakeup Enable Register
0x01C3 700C 0x01C3 780C CYCLCNT PRU Cycle Count
0x01C3 7010 0x01C3 7810 STALLCNT PRU Stall Count
PRU Constant Table Block Index
0x01C3 7020 0x01C3 7820 CONTABBLKIDX0 Register 0
PRU Constant Table Programmable
0x01C3 7028 0x01C3 7828 CONTABPROPTR0 Pointer Register 0
PRU Constant Table Programmable
0x01C3 702C 0x01C3 782C CONTABPROPTR1 Pointer Register 1
PRU Internal General Purpose
0x01C37400 - 0x01C3747C 0x01C3 7C00 - 0x01C3 7C7C INTGPR0 – INTGPR31 Register 0 (for Debug)
PRU Internal General Purpose
0x01C37480 - 0x01C374FC 0x01C3 7C80 - 0x01C3 7CFC INTCTER0 – INTCTER31 Register 0 (for Debug)
Table 6-109. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC) Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01C3 4000 REVID Revision ID Register
0x01C3 4004 CONTROL Control Register
0x01C3 4010 GLBLEN Global Enable Register
0x01C3 401C GLBLNSTLVL Global Nesting Level Register
0x01C3 4020 STATIDXSET System Interrupt Status Indexed Set Register
0x01C3 4024 STATIDXCLR System Interrupt Status Indexed Clear Register
0x01C3 4028 ENIDXSET System Interrupt Enable Indexed Set Register
0x01C3 402C ENIDXCLR System Interrupt Enable Indexed Clear Register
0x01C3 4034 HSTINTENIDXSET Host Interrupt Enable Indexed Set Register
0x01C3 4038 HSTINTENIDXCLR Host Interrupt Enable Indexed Clear Register
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Table 6-109. Programmable Real-Time Unit Subsystem Interrupt Controller (PRUSS INTC)
Registers (continued)
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01C3 4080 GLBLPRIIDX Global Prioritized Index Register
0x01C3 4200 STATSETINT0 System Interrupt Status Raw/Set Register 0
0x01C3 4204 STATSETINT1 System Interrupt Status Raw/Set Register 1
0x01C3 4280 STATCLRINT0 System Interrupt Status Enabled/Clear Register 0
0x01C3 4284 STATCLRINT1 System Interrupt Status Enabled/Clear Register 1
0x01C3 4300 ENABLESET0 System Interrupt Enable Set Register 0
0x01C3 4304 ENABLESET1 System Interrupt Enable Set Register 1
0x01C3 4380 ENABLECLR0 System Interrupt Enable Clear Register 0
0x01C3 4384 ENABLECLR1 System Interrupt Enable Clear Register 1
0x01C3 4400 - 0x01C3 4440 CHANMAP0 - CHANMAP15 Channel Map Registers 0-15
0x01C3 4800 - 0x01C3 4808 HOSTMAP0 - HOSTMAP2 Host Map Register 0-2
HOSTINTPRIIDX0 -
0x01C3 4900 - 0x01C3 4928 Host Interrupt Prioritized Index Registers 0-9
HOSTINTPRIIDX9
0x01C3 4D00 POLARITY0 System Interrupt Polarity Register 0
0x01C3 4D04 POLARITY1 System Interrupt Polarity Register 1
0x01C3 4D80 TYPE0 System Interrupt Type Register 0
0x01C3 4D84 TYPE1 System Interrupt Type Register 1
HOSTINTNSTLVL0-
0x01C3 5100 - 0x01C3 5128 Host Interrupt Nesting Level Registers 0-9
HOSTINTNSTLVL9
0x01C3 5500 HOSTINTEN Host Interrupt Enable Register
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6.30 Emulation Logic
This section describes the steps to use a third party debugger. The debug capabilities and features for
DSP are as shown below.
For TI’s latest debug and emulation information see :
http://tiexpressdsp.com/wiki/index.php?title=Category:Emulation
DSP:
• Basic Debug
– Execution Control
– System Visibility
• Real-Time Debug
– Interrupts serviced while halted
– Low/non-intrusive system visibility while running
• Advanced Debug
– Global Start
– Global Stop
– Specify targeted memory level(s) during memory accesses
– HSRTDX (High Speed Real Time Data eXchange)
• Advanced System Control
– Subsystem reset via debug
– Peripheral notification of debug events
– Cache-coherent debug accesses
• Analysis Actions
– Stop program execution
– Generate debug interrupt
– Benchmarking with counters
– External trigger generation
– Debug state machine state transition
– Combinational and Sequential event generation
• Analysis Events
– Program event detection
– Data event detection
– External trigger Detection
– System event detection (i.e. cache miss)
– Debug state machine state detection
• Analysis Configuration
– Application access
– Debugger access
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Table 6-110. DSP Debug Features
Category Hardware Feature Availability
Software breakpoint Unlimited
Up to 10 HWBPs, including:
4 precise(1) HWBPs inside DSP core and one of them is
Basic Debug associated with a counter.
Hardware breakpoint 2 imprecise(1) HWBPs from AET.
4 imprecise(1) HWBPs from AET which are shared for
watch point.
Up to 4 watch points, which are shared with HWBPs,
Watch point and can also be used as 2 watch points with data (32
bits)
Watch point with Data Up to 2, Which can also be used as 4 watch points.
Analysis Counters/timers 1x64-bits (cycle only) + 2x32-bits (watermark counters)
External Event Trigger In 1
External Event Trigger Out 1
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
6.30.1 JTAG Port Description
The device target debug interface uses the five standard IEEE 1149.1(JTAG) signals (TRST, TCK, TMS,
TDI, and TDO).
TRST holds the debug and boundary scan logic in reset (normal DSP operation) when pulled low (its
default state). Since TRST has an internal pull-down resistor, this ensures that at power up the device
functions in its normal (non-test) operation mode if TRST is not connected. Otherwise, TRST should be
driven inactive by the emulator or boundary scan controller. Boundary scan test cannot be performed
while the TRST pin is pulled low.
Table 6-111. JTAG Port Description
PIN TYPE NAME DESCRIPTION
When asserted (active low) causes all test and debug logic in the device
TRST I Test Logic Reset to be reset along with the IEEE 1149.1 interface
This is the test clock used to drive an IEEE 1149.1 TAP state machine
TCK I Test Clock and logic.
TMS I Test Mode Select Directs the next state of the IEEE 1149.1 test access port state machine
TDI I Test Data Input Scan data input to the device
TDO O Test Data Output Scan data output of the device
EMU[0] I/O Emulation 0 Channel 0 trigger + HSRTDX
6.30.2 Scan Chain Configuration Parameters
Table 6-112 shows the TAP configuration details required to configure the router/emulator for this device.
Table 6-112. JTAG Port Description
Router Port ID Default TAP TAP Name Tap IR Length
17 No C674x 38
The router is ICEpick revision C and has a 6-bit IR length.
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6.30.3 JTAG 1149.1 Boundary Scan Considerations
To use boundary scan, the following sequence should be followed:
• Execute a valid reset sequence and exit reset
• Wait at least 6000 OSCIN clock cycles
• Enter boundary scan mode using the JTAG pins
No specific value is required on the EMU[0] pin for boundary scan testing. If TRST is not driven by the
boundary scan tool or tester, TRST should be externally pulled high during boundary scan testing.
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6.31 IEEE 1149.1 JTAG
The JTAG (1) interface is used for BSDL testing and emulation of the device.
The device requires that both TRST and RESET be asserted upon power up to be properly initialized.
While RESET initializes the device, TRST initializes the device's emulation logic. Both resets are required
for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
.TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
.RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, the device includes an internal pulldown (IPD) on the TRST pin to ensure that
TRST will always be asserted upon power up and the device's internal emulation logic will always be
properly initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
6.31.1 JTAG Peripheral Register Description(s) – JTAG ID Register (DEVIDR0)
Table 6-113. DEVIDR0 Register
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION COMMENTS
Read-only. Provides 32-bit
0x01C1 4018 DEVIDR0 JTAG Identification Register JTAG ID of the device.
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
device, the JTAG ID register resides at address location 0x01C1 4018. The register hex value for each
silicon revision is:
• 0x0B7D F02F for silicon revision 1.0
• 0x8B7D F02F for silicon revision 1.1
• 0x9B7D F02F for silicon revisions 3.0, 2.1, and 2.0
For the actual register bit names and their associated bit field descriptions, see Figure 6-71 and Table 6-
114.
Figure 6-71. JTAG ID (DEVIDR0) Register Description - Register Value
31 28 27 12 11 1 0
VARIANT PART NUMBER (16-bit) MANUFACTURER (11-bit) LSB
(4-bit)
R-xxxx R-1011 1001 0110 1011 R-0000 0010 111 R-1
LEGEND: R = Read, W = Write, n = value at reset
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TCK
TDO
TDI/TMS/TRST
1
66
5
4
3
2
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Table 6-114. JTAG ID Register Selection Bit Descriptions
BIT NAME DESCRIPTION
31:28 VARIANT Variant (4-Bit) value
27:12 PART NUMBER Part Number (16-Bit) value
11-1 MANUFACTURER Manufacturer (11-Bit) value
0 LSB LSB. This bit is read as a "1".
6.31.2 JTAG Test-Port Electrical Data/Timing
Table 6-115. Timing Requirements for JTAG Test Port (see Figure 6-72)
No. PARAMETER MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 40 ns
2 tw(TCKH) Pulse duration, TCK high 16 ns
3 tw(TCKL) Pulse duration, TCK low 16 ns
4 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 4 ns
5 th(TCLKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 4 ns
Table 6-116. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 6-72)
No. PARAMETER MIN MAX UNIT
6 td(TCKL-TDOV) Delay time, TCK low to TDO valid 15 ns
Figure 6-72. JTAG Test-Port Timing
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Seconds Minutes Hours Days Months Years
Alarm
Timer
Alarm
Interrupts
Periodic
Interrupts
Counter
32kHz
Oscillator
Compensation
Week
Days
Oscillator
RTC_XI
XTAL
RTC_XO
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6.32 Real Time Clock (RTC)
The RTC provides a time reference to an application running on the device. The current date and time is
tracked in a set of counter registers that update once per second. The time can be represented in 12-hour
or 24-hour mode. The calendar and time registers are buffered during reads and writes so that updates do
not interfere with the accuracy of the time and date.
Alarms are available to interrupt the CPU at a particular time, or at periodic time intervals, such as once
per minute or once per day. In addition, the RTC can interrupt the CPU every time the calendar and time
registers are updated, or at programmable periodic intervals.
The real-time clock (RTC) provides the following features:
• 100-year calendar (xx00 to xx99)
• Counts seconds, minutes, hours, day of the week, date, month, and year with leap year compensation
• Binary-coded-decimal (BCD) representation of time, calendar, and alarm
• 12-hour clock mode (with AM and PM) or 24-hour clock mode
• Alarm interrupt
• Periodic interrupt
• Single interrupt to the CPU
• Supports external 32.768-kHz crystal or external clock source of the same frequency
• Separate isolated power supply
Figure 6-73 shows a block diagram of the RTC.
Figure 6-73. Real-Time Clock Block Diagram
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XTAL
32.768
kHz
C2
C1
RTC_XI
RTC_XO
RTC_VSS
32K
OSC
Real
Time
Clock
(RTC)
Module
Isolated RTC
Power Domain
Real Time Clock RTC_CVDD
RTC
Power
Source
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6.32.1 Clock Source
The clock reference for the RTC is an external 32.768-kHz crystal or an external clock source of the same
frequency. The RTC also has a separate power supply that is isolated from the rest of the system. When
the CPU and other peripherals are without power, the RTC can remain powered to preserve the current
time and calendar information.
The source for the RTC reference clock may be provided by a crystal or by an external clock source. The
RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected
between pins RTC_XI and RTC_XO. RTC_XI is the input to the on-chip oscillator and RTC_XO is the
output from the oscillator back to the crystal. A crystal with 70k-ohm max ESR is recommended. Typical
load capacitance values are 10-20 pF, where the load capacitance is the series combination of C1 and
C2.
An external 32.768-kHz clock source may be used instead of a crystal. In such a case, the clock source is
connected to RTC_XI, and RTC_XO is left unconnected.
If the RTC is not used, the RTC_XI pin should be static held high or low and RTC_XO should be left
unconnected.
Figure 6-74. Clock Source
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6.32.2 Real-Time Clock Registers
Table 6-117 lists the memory-mapped registers for the RTC.
Table 6-117. Real-Time Clock (RTC) Registers
BYTE ADDRESS ACRONYM REGISTER DESCRIPTION
0x01C2 3000 SECOND Seconds Register
0x01C2 3004 MINUTE Minutes Register
0x01C2 3008 HOUR Hours Register
0x01C2 300C DAY Day of the Month Register
0x01C2 3010 MONTH Month Register
0x01C2 3014 YEAR Year Register
0x01C2 3018 DOTW Day of the Week Register
0x01C2 3020 ALARMSECOND Alarm Seconds Register
0x01C2 3024 ALARMMINUTE Alarm Minutes Register
0x01C2 3028 ALARMHOUR Alarm Hours Register
0x01C2 302C ALARMDAY Alarm Days Register
0x01C2 3030 ALARMMONTH Alarm Months Register
0x01C2 3034 ALARMYEAR Alarm Years Register
0x01C2 3040 CTRL Control Register
0x01C2 3044 STATUS Status Register
0x01C2 3048 INTERRUPT Interrupt Enable Register
0x01C2 304C COMPLSB Compensation (LSB) Register
0x01C2 3050 COMPMSB Compensation (MSB) Register
0x01C2 3054 OSC Oscillator Register
0x01C2 3060 SCRATCH0 Scratch 0 (General-Purpose) Register
0x01C2 3064 SCRATCH1 Scratch 1 (General-Purpose) Register
0x01C2 3068 SCRATCH2 Scratch 2 (General-Purpose) Register
0x01C2 306C KICK0 Kick 0 (Write Protect) Register
0x01C2 3070 KICK1 Kick 1 (Write Protect) Register
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7 Device and Documentation Support
7.1 Device Support
7.1.1 Development Support
TI offers an extensive line of development tools for the TMS320C6745/47 platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules. The tool's support documentation is electronically
available within the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of TMS320C6745/47 applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target
software needed to support any application.
Hardware Development Tools:
Extended Development System (XDS™) Emulator
For a complete listing of development-support tools for TMS320C6745/47, visit the Texas Instruments
web site on the Worldwide Web at www.ti.com uniform resource locator (URL). For information on
pricing and availability, contact the nearest TI field sales office or authorized distributor.
7.1.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., TMS320C6745). Texas Instruments recommends two of three possible prefix
designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of
product development from engineering prototypes (TMX/TMDX) through fully qualified production
devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMS Fully-qualified production device.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
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TMS 320 C6747 ( ) ZKB ( ) ( )
PREFIX
TMX = Experimental Device
TMS = Qualified Device
DEVICE FAMILY
320 = TMS320™ DSP Family
DEVICE
C64x+™ C6747
C6745
DEVICE SPEED RANGE
3 = 300 MHz (for Revision A)
3 = 375 MHz (for Revision B)
4 = 456 MHz (for Revision B)
TEMPERATURE RANGE (JUNCTION)
Blank
D
A
T
= 0°C to 90°C, Commercial Grade
=
= –40°C to 105°C,Extended Grade
–40°C to 90°C, Industrial Grade
= –40°C to 125°C, Automotive Grade
PACKAGE TYPE
256-Pin Plastic BGA, with Pb-free Soldered
Balls [Green]
ZKB =
SILICON REVISION
Blank = Revision 1.0
A
B
C
D
PTP = 176-Pin PowerPAD Plastic Quad Flat Pack
[PTP Suffix], 0.5 mm Pin Pitch
TM
= Revision 1.1
= Revision 2.0
= Revision 2.1
= Revision 3.0
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Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, ZKB), the temperature range (for example, "Blank" is the commercial temperature range),
and the device speed range in megahertz (for example, "Blank" is the default).
Figure 7-1 provides a legend for reading the complete device name for any TMS320C674x member.
Figure 7-1. Device Nomenclature
7.2 Documentation Support
The following documents describe the TMS320C6745/47 Low-power digital signal processor. Copies of
these documents are available on the Internet at www.ti.com.Tip: Enter the literature number in the
search box provided at www.ti.com.
DSP Reference Guides
SPRUFE8 TMS320C674x DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C674x digital signal
processors (DSPs). The C674x DSP is an enhancement of the C64x+ and C67x+ DSPs with
added functionality and an expanded instruction set.
SPRUFK5 TMS320C674x DSP Megamodule Reference Guide. Describes the TMS320C674x digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory
access (IDMA) controller, the interrupt controller, the power-down controller, memory
protection, bandwidth management, and the memory and cache.
SPRUH91 TMS320C6745/C6747 DSP Technical Reference Manual. Describes the System-on-Chip
(SoC) and each peripheral in the device.
User's Guides
SPRU186 TMS320C6000 Assembly Language Tools User's Guide.Describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code),
assembler directives, macros, common object file format, and symbolic debugging directives
for the TMS320C6000 platform of devices (including the C64x+, C67x+, and C674x
generations).
SPRU187 TMS320C6000 Optimizing Compiler User's Guide. Describes the TMS320C6000 C
compiler and the assembly optimizer. This C compiler accepts ANSI standard C source code
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and produces assembly language source code for the TMS320C6000 platform of devices
(including the C64x+, C67x+, and C674x generations). The assembly optimizer helps you
optimize your assembly code.
SPRUG82 TMS320C674x DSP Cache User's Guide. Explains the fundamentals of memory caches
and describes how the two-level cache-based internal memory architecture in the
TMS320C674x digital signal processor (DSP) can be efficiently used in DSP applications.
Shows how to maintain coherence with external memory, how to use DMA to reduce
memory latencies, and how to optimize your code to improve cache efficiency. The internal
memory architecture in the C674x DSP is organized in a two-level hierarchy consisting of a
dedicated program cache (L1P) and a dedicated data cache (L1D) on the first level.
Accesses by the CPU to the these first level caches can complete without CPU pipeline
stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next
lower memory level, L2 or external memory.
7.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help
developers get started with Embedded Processors from Texas Instruments and to foster
innovation and growth of general knowledge about the hardware and software surrounding
these devices.
7.4 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
TMS320C6745 Click here Click here Click here Click here Click here
TMS320C6747 Click here Click here Click here Click here Click here
7.5 Trademarks
DSP/BIOS, PowerPAD, TMS320C6000, C6000, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
7.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
216 Device and Documentation Support Copyright © 2008–2014, Texas Instruments Incorporated
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TMS320C6745, TMS320C6747
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SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
8 Mechanical Packaging and Orderable Information
This section describes the C6745/6747 orderable part numbers, packaging options, materials, thermal and
mechanical parameters.
This section contains mechanical drawings for the ZKB Plastic Ball Grid Array package and the PTP
PowerPAD™ plastic quad flat pack package. Additionally, for the PTP package a detailed drawing of the
actual thermal pad dimensions as well as a recommended PCB footprint are provided.
8.1 Thermal Data for ZKB
The following table(s) show the thermal resistance characteristics for the PBGA–ZKB mechanical
package.
Table 8-1. Thermal Resistance Characteristics (PBGA Package) [ZKB]
No. °C/W(1) °C/W(2) AIR FLOW
(m/s)(3)
1 RΘJC Junction-to-case 12.8 13.5 N/A
2 RΘJB Junction-to-board 15.1 19.7 N/A
3 RΘJA Junction-to-free air 24.5 33.8 0.00
4 21.9 30 0.50
5 21.1 28.7 1.00
RΘJMA Junction-to-moving air
6 20.4 27.4 2.00
7 19.6 26 4.00
8 0.6 0.8 0.00
9 0.8 1 0.50
10 PsiJT Junction-to-package top 0.9 1.2 1.00
11 1.1 1.4 2.00
12 1.3 1.8 4.00
13 14.9 19.1 0.00
14 14.4 18.2 0.50
15 PsiJB Junction-to-board 14.4 18 1.00
16 14.3 17.7 2.00
17 14.1 17.4 4.00
(1) These measurements were conducted in a JEDEC defined 2S2P system and will change based on environment as well as application.
For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment
Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount
Packages. Power dissipation of 1W and ambient temp of 70C assumed. PCB with 2oz (70um) top and bottom copper thickness and
1.5oz (50um) inner copper thickness
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
(3) m/s = meters per second
Copyright © 2008–2014, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 217
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TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
www.ti.com
8.2 Thermal Data for PTP
The following table(s) show the thermal resistance characteristics for the PowerPAD™ PTP mechanical
package.
Table 8-2. Thermal Resistance Characteristics (PowerPAD™ Package) [PTP]"
No. °C/W(1) °C/W(2) °C/W(3) °C/W(4) AIR FLOW
(m/s)(5)
1 RΘJC Junction-to-case 7.8 9.4 8.6 10.1 N/A
2 RΘJB Junction-to-board 6.2 9.9 7.1 10.6 N/A
3 RΘJA Junction-to-free air 21.3 27.9 23.2 30.6 0.00
4 14.3 20.2 22.6 0.50
5 13.1 18.6 21.0 1.00
RΘJMA Junction-to-moving air
6 12.1 17.4 19.6 2.00
7 11.2 16.2 18.2 4.00
8 0.5 0.7 0.8 0.00
9 0.6 0.9 1.0 0.50
10 PsiJT Junction-to-package top 0.7 1.0 1.1 1.00
11 0.8 1.1 1.3 2.00
12 1.0 1.3 1.5 4.00
13 6.3 9.5 10.8 0.00
14 5.9 8.8 9.9 0.50
15 PsiJB Junction-to-board 5.9 8.7 9.8 1.00
16 5.8 8.6 9.7 2.00
17 5.8 8.5 9.6 4.00
(1) Simulation data, using a model of a JEDEC defined 2S2P system with a 12mmx12mm copper pad on the top and bottom copper layers
connected with an 8x8 thermal via array and soldered to the package thermal pad. Power dissipation of 1W assumed, 70C Ambient
temp assumed. Signal layer copper coverage 20%, inner layer copper coverage 90%. Actual performance will change based on
environment as well as application. For more information, see these EIA/JEDEC standards – EIA/JESD51-2, Integrated Circuits Thermal
Test Method Environment Conditions - Natural Convection (Still Air) and JESD51-7, High Effective Thermal Conductivity Test Board for
Leaded Surface Mount Packages.
(2) Simulation data, using the same model but with 1oz (35um) top and bottom copper thickness and 0.5oz (18um) inner copper thickness.
Power dissipation of 1W and ambient temp of 70C assumed.
(3) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 2oz (70um) top and bottom.
(4) Simulation data, 1S1P PCB model with 12x12mm copper pad on the top layer soldered to device thermal pad and connected to the
bottom copper layer (90% copper) with an 8x8 thermal via array. Power dissipation of 1W and ambient temp of 70C assumed. Copper
thickness 1oz (35um) top and bottom.
(5) m/s = meters per second
8.3 Supplementary Information About the 176-pin PTP PowerPAD™ Package
This section highlights a few important details about the 176-pin PTP PowerPAD™ package. Texas
Instruments' PowerPAD Thermally Enhanced Package Technical Brief (SLMA002) should be consulted
when creating a PCB footprint for this device.
8.3.1 Standoff Height
As illustrated in Figure 8-1, the standoff height specification for this device (between 0.050 mm and
0.150 mm) is measured from the seating plane established by the three lowest package pins to the lowest
point on the package body. Due to warpage, the lowest point on the package body is located in the center
of the package at the exposed thermal pad.
Using this definition of standoff height provides the correct result for determining the correct solder paste
thickness. According to TI's PowerPAD Thermally Enhanced Package Technical Brief (SLMA002), the
recommended range of solder paste thickness for this package is between 0.152 mm and 0.178 mm.
218 Mechanical Packaging and Orderable Information Copyright © 2008–2014, Texas Instruments Incorporated
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Thermal Pad on Top Copper
should be as large as Possible. Soldermask opening should be smaller and match
the size of the thermal pad on the DSP.
Standoff Height
TMS320C6745, TMS320C6747
www.ti.com
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
Figure 8-1. Standoff Height Measurement on 176-pin PTP Package
8.3.2 PowerPAD™ PCB Footprint
In general, for proper thermal performance, the thermal pad under the package body should be as large
as possible. However, the soldermask opening for the PowerPAD™ should be sized to match the pad size
on the 176-pin PTP package; as illustrated in Figure 8-2.
Figure 8-2. Soldermask Opening Should Match Size of DSP Thermal Pad
8.4 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
Copyright © 2008–2014, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 219
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PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TMS320C6745DPTP3 ACTIVE HLQFP PTP 176 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR 0 to 90 TMS320
C6745DPTP3
TMS320C6745DPTP4 ACTIVE HLQFP PTP 176 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR TMS320
C6745DPTP4
TMS320C6745DPTPA3 ACTIVE HLQFP PTP 176 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 105 TMS320
C6745DPTPA3
TMS320C6745DPTPD4 ACTIVE HLQFP PTP 176 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 90 TMS320
C6745DPTPD4
TMS320C6745DPTPT3 ACTIVE HLQFP PTP 176 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR -40 to 125 TMS320
C6745DPTPT3
TMS320C6747DZKB3 ACTIVE BGA ZKB 256 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 TMS320
C6747DZKB3
TMS320C6747DZKB4 ACTIVE BGA ZKB 256 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR TMS320
C6747DZKB4
TMS320C6747DZKBA3 ACTIVE BGA ZKB 256 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 TMS320
C6747DZKBA3
TMS320C6747DZKBD4 ACTIVE BGA ZKB 256 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 TMS320
C6747DZKBD4
TMS320C6747DZKBT3 ACTIVE BGA ZKB 256 90 Green (RoHS
& no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 125 TMS320
C6747DZKBT3
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
Addendum-Page 2
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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