1. Product profile
1.1 General description
The BF1205C is a combination of two dual gate MOS-FET amplifiers with shared source
and gate 2 leads and an integr ated switch. The integrated switch is op erated by the gate 1
bias of amplifier b.
The source and substrate are interconnected. Internal bias circuits enable DC stabilization
and a very good cross-modulation performance during AGC. Integrated diodes between
the gates and so urce protect against excessive input voltage surges. Th e transistor h as a
SOT363 micro-miniature plastic package.
1.2 Features and benefits
T wo low noise gain controlled amplifiers in a sing le package; one with a fully integra ted
bias and one with a partly integrated bias
Internal switch to save external components
Superior cross -m o dulation performa nce during AGC
High forward transfer admittance
High forward transfer admittance to input capacitance ratio.
1.3 Applications
Gain controlled low noise amplifiers for VHF and UHF applications with 5 V supply
voltage
digital and analog television tuners
professional communication equipment.
BF1205C
Dual N-channel dual gate MOS-FET
Rev. 3 — 7 September 2011 Product data sheet
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 2 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
1.4 Quick reference data
[1] Tsp is the temperature at the soldering point of the source lead.
2. Pinning information
Table 1. Quick reference data
Per MOS-FET unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage - - 6 V
IDdrain current (DC) - - 30 mA
Ptot total power dissipation Tsp 107 C[1] - - 180 mW
yfsforward transfer admittance f = 1 MHz
amplifier a; ID=19mA 26 31 41 mS
amplifier b; ID=13mA 28 33 43 mS
Cig1-ss input capacitance at gate 1 f = 1 MHz
amplifier a - 2.2 2.7 pF
amplifier b - 2.0 2.5 pF
Crss reverse transfer capacit ance f = 1 MHz - 20 - fF
NF noise figure amplifier a; f = 400 MHz - 1.3 1.9 dB
amplifier b; f = 800 MHz - 1.4 2.1 dB
Xmod cross-modulation input level for k = 1 % at
40 dB AGC
amplifier a 100 105 - dBV
amplifier b 100 103 - dBV
Tjjunction temperature - - 150 C
Table 2. Discrete pinning
Pin Description Simplified outline Symbol
1 gate 1 (a)
2gate2
3 gate 1 (b)
4drain(b)
5source
6drain(a)
001aaa706
1 2 3
6 5 4
sym033
G1
(B)
G1
(A)
G2 S
D
(A)
D
(B)
AMP b
AMP a
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 3 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
3. Ordering information
4. Marking
[1] * = p or -: made in Hong Kong.
* = t: made in Malaysia.
* = W: made in China.
5. Limiting values
[1] Tsp is the temperature at the soldering point of the source lead.
6. Thermal characteristics
Tabl e 3. Ordering i nfo rmation
Type number Package
Name Description Version
BF1205C - plastic surface mounted package; 6 leads SOT363
Table 4. Marking
Type number Marking code[1]
BF1205C M6*
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Per MOS-FET
VDS drain-source voltage - 6 V
IDdrain current (DC) - 30 mA
IG1 gate 1 current - 10 mA
IG2 gate 2 current - 10 mA
Ptot total power dissipation Tsp 107 C[1] -180mW
Tstg storage temperature 65 +150 C
Tjjunction temperature - 150 C
Table 6. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-s) thermal resist ance from junction
to soldering point 240 K/W
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 4 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
7. Static characteristics
[1] RG1 connects gate 1 (b) to VGG = 0 V (see Figure 3).
[2] RG1 connects gate 1 (b) to VGG = 5 V (see Figure 3).
Fig 1. Power derating curve.
Tsp (˚C)
0 20015050 100
001aac193
100
150
50
200
250
Ptot
(mW)
0
Table 7. Static characteristics
Tj=25
C.
Symbol Parameter Conditions Min Typ Max Unit
Per MOS-FET; unless otherwise specified
V(BR)DSS drain-source breakdown voltage VG1-S =V
G2-S =0V; I
D=10A
amplifier a 6 - - V
amplifier b 6 - - V
V(BR)G1-SS gate 1-source breakdown voltage VGS =V
DS =0V; I
G1-S =10mA 6 - 10 V
V(BR)G2-SS gate 2-source breakdown voltage VGS =V
DS =0V; I
G2-S =10mA 6 - 10 V
V(F)S-G1 forward source-gate 1 voltage VG2-S =V
DS =0V; I
S-G1 = 10 mA 0.5 - 1.5 V
V(F)S-G2 forward source-gate 2 voltage VG1-S =V
DS =0V; I
S-G2 = 10 mA 0.5 - 1.5 V
VG1-S(th) gate 1-source threshold voltage VDS =5V; V
G2-S =4V; I
D=100A 0.3 - 1.0 V
VG2-S(th) gate 2-source threshold voltage VDS =5V; V
G1-S =5V; I
D=100A 0.4 - 1.0 V
IDSX drain-source current VG2-S =4V; V
DS(b) =5V; R
G1 =150k
amplifier a; VDS(a) =5V [1] 14 - 24 mA
amplifier b [2] 9-17mA
IG1-S gate 1 cut-off current VG2-S =V
DS(a) =0V
amplifier a; VG1-S(a) =5V; I
D(b) =0A - - 50 nA
amplifier b; VG1-S(b) =5V; V
DS(b) =0V - - 50 nA
IG2-S gate 2 cut-off current VG2-S =4V;
VG1-S(a) =V
DS(a) =V
DS(b) =0V;
VG1-S(b) =0V;
--20nA
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 5 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
8. Dynamic characteristics
8.1 Dynamic characteristics for amplifier a
(1) ID(b); RG1 = 120 k.
(2) ID(b); RG1 = 150 k.
(3) ID(b); RG1 = 180 k.
(4) ID(a); RG1 = 180 k.
(5) ID(a); RG1 = 150 k.
(6) ID(a); RG1 = 120 k.
VGG = 5 V: amplifier a is off; amplifier b is on
VGG = 0 V: amplifier a is on; amplifier b is off.
Fig 2. Drain currents of MOS-FET a and b as function
of VGG.Fig 3. Functional diagram.
001aaa552
8
12
4
16
20
ID
(mA)
0
VGG (V)
054231
(2)
(5)
(4)
(6)
(3)
(1)
001aaa553
RG1
VGG
G1 (B)
G2
G1 (A)
D (B)
S
D (A)
Table 8. Dynamic characteristics for amplifier a[1]
Common source; Tamb =25
C; VG2-S =4V; V
DS =5V; I
D=19mA.
Symbol Parameter Conditions Min Typ Max Unit
yfsforward transfer admittance Tj=25C263141mS
Cig1-ss input capacitance at gate 1 f = 1 MHz - 2.2 2.7 pF
Cig2-ss input capacitance at gate 2 f = 1 MHz - 3.0 - pF
Coss output capacitance f = 1 MHz - 0.9 - pF
Crss reverse transfer capacitance f = 1 MHz - 20 - fF
Gtr power gain BS=B
S(opt); BL=B
L(opt)
f=200MHz; G
S=2mS; G
L= 0.5 mS 31 35 39 dB
f=400MHz; G
S=2mS; G
L= 1 mS 26 30 34 dB
f=800MHz; G
S= 3.3 mS; GL= 1 mS 21 25 29 dB
NF noise figure f = 11 MHz; GS=20mS; B
S= 0 S - 3.0 - dB
f=400MHz; Y
S=Y
S(opt) -1.31.9dB
f=800MHz; Y
S=Y
S(opt) -1.42.1dB
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 6 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
[1] For the MOS-FET not in use: VG1-S(b) =0V; V
DS(b) =0V.
[2] Measured in Figure 33 test circuit.
8.1.1 Graphs for amplifier a
Xmod cross-modulation input level for k = 1 %; fw=50MHz; f
unw =60MHz [2]
at 0 dB AGC 90 - - dBV
at 10 dB AGC - 90 - dBV
at 20 dB AGC - 99 - dBV
at 40 dB AGC 100 105 - dBV
Table 8. Dynamic characteristics for amplifier a[1] …continued
Common source; Tamb =25
C; VG2-S =4V; V
DS =5V; I
D=19mA.
Symbol Parameter Conditions Min Typ Max Unit
(1) VG2-S =4V.
(2) VG2-S =3.5V.
(3) VG2-S =3V.
(4) VG2-S =2.5V.
(5) VG2-S =2V.
(6) VG2-S =1.5V.
(7) VG2-S =1V.
VDS(a) =5V; V
G1-S(b) =V
DS(b) =0V; T
j=25C.
(1) VG1-S(a) =1.8V.
(2) VG1-S(a) =1.7V.
(3) VG1-S(a) =1.6V.
(4) VG1-S(a) =1.5V.
(5) VG1-S(a) =1.4V.
(6) VG1-S(a) =1.3V.
(7) VG1-S(a) =1.2V.
(8) VG1-S(a) =1.1V.
(9) VG1-S(a) =1V.
VG2-S =4V; V
G1-S(b) =V
DS(b) =0V; T
j=25C.
Fig 4. Transfer characteristics; typica l values. Fig 5. Output characteristics; typical values.
VG1-S (V)
021.60.8 1.20.4
001aaa554
10
20
30
ID
(mA)
0
(1)
(2)
(3) (4)
(5)
(7)
(6)
001aaa555
VDS (V)
0642
16
8
24
32
ID
(mA)
0
(2)
(3)
(4)
(6)
(7)
(9)
(8)
(5)
(1)
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 7 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
(1) VG2-S =4V.
(2) VG2-S =3.5V.
(3) VG2-S =3V.
(4) VG2-S =2.5V.
(5) VG2-S =2V.
(6) VG2-S =1.5V.
VDS(a) =5V; V
G1-S(b) =V
DS(b) =0V; T
j=25C.
VDS(a) =5V; V
G2-S =4V; V
DS(b) =5V; V
G1-S(b) =0V;
Tj=25C.
Fig 6. Forward transfer admittance as a function of
drain current; typica l values. Fig 7. Drain current as a function of internal G1
current (current in pin drain (b) if MOS-FET (b)
is switched off); typical values.
ID (mA)
03224816
001aaa556
20
10
30
40
yfs
(mS)
0
(1) (2)
(3)
(4)
(5)
(6)
001aaa557
ID (b) (μA)
0604020
8
12
4
16
20
ID (a)
(mA)
0
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 8 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
VDS(a) =V
DS(b) =V
supply, VG2-S =4V, T
j=25C,
RG1(b) = 150 k(connected to ground); see Figure 3.(1) VDS(b) =5V.
(2) VDS(b) =4.5V.
(3) VDS(b) =4V.
(4) VDS(b) =3.5V.
(5) VDS(b) =3V.
(6) VDS(b) =2.5V.
VDS(a) =5V; V
G1-S(b) = 0 V; gate 1 (a) = open;
Tj=25C.
Fig 8. Drain current of amp lifi e r a as a function of
supply voltage of a and b amplifier; typical
values.
Fig 9. Drain current as a function of gate 2 and drain
supply voltage; typical values.
Vsup (V)
054231
001aaa558
8
12
4
16
20
ID
(mA)
0
001aaa559
VG2-S (V)
0642
16
8
24
32
ID
(mA)
0
(1)
(2)
(3)
(4)
(5)
(6)
VDS(a) =V
DS(b) =5V; V
G1-S(b) =0V; f
w=50MHz;
funw =60MHz; T
amb =25C; see Figure 33.VDS(a) =V
DS(b) =5V; V
G1-S(b) = 0 V; f = 50 MHz; see
Figure 33.
Fig 10. Unwanted vo ltage for 1 % cros s-modulation as
a function of gain reduction; typical values. Fig 11. Gain reduction as a function of AGC voltage;
typical values.
gain reduction (dB)
0504020 3010
001aaa560
100
90
110
120
Vunw
(dBμV)
80
VAGC (V)
04312
001aaa561
30
20
40
10
0
gain
reduction
(dB)
50
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 9 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
VDS(a) =V
DS(b) =5V; V
G1-S(b) =0V; f=50MHz;
Tamb =25C; see Figure 33.VDS(a) =5V; V
G2-S(a) =4V; V
DS(b) =V
G1-S(b) =0V;
ID(a) =19mA.
Fig 12. Drain current as a function of gain reduction;
typical valu e s. Fig 13. Input admittance as a function of frequency;
typical values.
001aaa562
gain reduction (dB)
0604020
16
8
24
32
ID
(mA)
0
001aaa564
f (MHz)
10 103
102
10−1
1
10
102
bis, gis
(mS)
10−2
bis
gis
VDS(a) =5V; V
G2-S(a) =4V; V
DS(b) =V
G1-S(b) =0V;
ID(a) =19mA. VDS(a) =5V; V
G2-S(a) =4V; V
DS(b) =V
G1-S(b) =0V;
ID(a) =19mA.
Fig 14. Forward transfer admittance and phase as a
function of frequency ; typ ic al values. Fig 15. Reverse tran sfer admittance and phase as a
function of frequency: typical values.
f (MHz)
10 103
102
001aaa565
10
102
yfs
(mS)
1
−ϕfs
(deg)
10
102
1
yfs
−ϕfs
001aaa566
102
10
103
yrs
(mS)
1
102
10
103
−ϕrs
(deg)
1
f (MHz)
10 103
102
yrs
−ϕrs
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 10 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
8.1.2 Scattering parameters for amplifier a
8.1.3 Noise data for amplifier a
VDS(a) =5V; V
G2-S(a) =4V; V
DS(b) =V
G1-S(b) =0V; I
D(a) =19mA.
Fig 16. Output admittance as a function of frequency; typical values.
001aaa567
bos, gos
(mS)
1
10
10−2
10−1
f (MHz)
10 103
102
bos
gos
Table 9. Scattering parameters for amplifier a
VDS(a) =5V; V
G2-S =4V; I
D(a) =19mA; V
DS(b) =0V; V
G-1S(b) =0V; T
amb =25
C.
f
(MHz) S11 S21 S12 S22
Magnitude
ratio Angle
(deg) Magnitude
ratio Angle
(deg) Magnitude
ratio Angle
(deg) Magnitude
ratio Angle
(deg)
50 0.992 3.91 3.07 175.56 0.0007 83.61 0.992 1.47
100 0.990 7.76 3.06 171.18 0.0017 83.19 0.992 2.93
200 0.982 15.42 3.04 162.42 0.0026 78.19 0.990 5.84
300 0.971 22.99 3.01 153.79 0.0037 73.75 0.988 8.71
400 0.956 30.52 2.96 145.22 0.0047 69.82 0.985 11.59
500 0.938 37.83 2.90 136.78 0.0055 66.12 0.982 14.48
600 0.917 45.14 2.83 128.46 0.0061 62.11 0.979 17.31
700 0.893 52.31 2.76 120.20 0.0065 58.86 0.975 20.14
800 0.867 59.47 2.69 111.98 0.0068 58.28 0.972 22.98
900 0.838 66.23 2.60 103.90 0.0067 50.64 0.968 25.85
1000 0.807 73.10 2.52 95.875 0.0065 47.28 0.966 28.74
Table 10. Noise data for amplifier a
VDS(a) =5V; V
G2-S =4V; I
D(a) =19mA; V
DS(b) =0V; V
G-1S(b) =0V; T
amb = 25
C.
f
(MHz) Fmin
(dB) opt rn
()
ratio (deg)
400 1.3 0.718 16.06 0.683
800 1.4 0.677 37.59 0.681
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 11 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
8.2 Dynamic characteristics for amplifier b
[1] For the MOS-FET not in use: VG1-S(a) = 0 V; VDS(a) =0 V.
[2] Measured in Figure 34 test circuit.
Table 11. Dynamic characteristics for amplifier b
Common source; Tamb =25
C; VG2-S =4V; V
DS =5V; I
D=13mA.
Symbol Parameter Conditions Min Typ Max Unit
yfsforward transfer admittance Tj=25C283343mS
Cig1-ss input capacitance at gate 1 f = 1 MHz - 2.0 2.5 pF
Cig2-ss input capacitance at gate 2 f = 1 MHz - 3.4 - pF
Coss output capacitance f = 1 MHz - 0.85 - pF
Crss reverse transfer capacitance f = 1 MHz - 20 - fF
Gtr power gain BS=B
S(opt); BL=B
L(opt) [1]
f=200MHz; G
S=2mS; G
L= 0.5 mS 31 35 39 dB
f=400MHz; G
S=2mS; G
L= 1 mS 28 32 36 dB
f=800MHz; G
S= 3.3 mS; GL= 1 mS 24 28 32 dB
NF noise figure f = 11 MHz; GS=20mS; B
S=0S - 5 - dB
f=400MHz; Y
S=Y
S(opt) -1.31.9dB
f=800MHz; Y
S=Y
S(opt) -1.42.1dB
Xmod cross-modulation input level for k = 1 %; fw=50MHz; f
unw =60MHz [2]
at 0 dB AGC 90 - - dBV
at 10 dB AGC - 88 - dBV
at 20 dB AGC - 94 - dBV
at 40 dB AGC 100 103 - dBV
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 12 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
8.2.1 Graphs for amplifier b
(1) VG2-S =4V.
(2) VG2-S =3.5V.
(3) VG2-S =3V.
(4) VG2-S =2.5V.
(5) VG2-S =2V.
(6) VG2-S =1.5V.
(7) VG2-S =1V.
VDS(b) =5V; V
DS(a) =V
G1-S(a) =0V; T
j=25C.
(1) VG1-S(b) =1.6V.
(2) VG1-S(b) =1.5V.
(3) VG1-S(b) =1.4V.
(4) VG1-S(b) =1.3V.
(5) VG1-S(b) =1.2V.
(6) VG1-S(b) =1.1V.
(7) VG1-S(b) =1V.
VG2-S =4V; V
DS(a) =V
G1-S(a) =0V; T
j=25C.
Fig 17. Transfer chara cteristics; typ ica l values. Fig 18. Output charac teristics; typical values.
VG1-S (V)
021.60.8 1.20.4
001aaa568
10
20
30
ID
(mA)
0
(4)
(5)
(6)
(7)
(2)
(3)
(1)
001aaa569
VDS (V)
0642
16
8
24
32
ID
(mA)
0
(1)
(2)
(5)
(6)
(7)
(4)
(3)
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 13 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
(1) VG2-S =4V.
(2) VG2-S =3.5V.
(3) VG2-S =3V.
(4) VG2-S =2.5V.
(5) VG2-S =2V.
(6) VG2-S =1.5V.
(7) VG2-S =1V.
VDS(b) =5V; V
DS(a) =V
G1-S(a) =0V; T
j=25C.
(1) VG2-S =4V.
(2) VG2-S =3.5V.
(3) VG2-S =3V.
(4) VG2-S =2.5V.
(5) VG2-S =2V.
(6) VG2-S =1.5V.
(7) VG2-S =1V.
VDS(b) =5V; V
DS(a) =V
G1-S(a) =0V; T
j=25C.
Fig 19. Gate 1 current as a function of gate 1 voltage;
typical valu e s. Fig 20. Forward tran sfer admittance as a function of
drain current; typical values.
VG1-S (V)
021.60.8 1.20.4
001aaa570
40
60
20
80
100
IG1
(μA)
0
(1) (2)
(4)
(6)
(7)
(3)
(5)
ID (mA)
03224816
001aaa571
20
10
30
40
yfs
(mS)
0
(1)
(2)
(3)
(4)
(5)
(6)
(7)
VDS(b) =5V; V
G2-S =4V; V
DS(a) =V
G1-S(a) =0V;
Tj=25C. VDS(b) =5V; V
G2-S =4V; V
DS(a) =V
G1-S(a) =0V;
Tj=25C; RG1(b) =150k(connected to VGG); see
Figure 3.
Fig 21. Drain current as a function of gate 1 current;
typical valu e s. Fig 22. Drain curren t as a function of gate 1 supply
voltage (VGG); typical values.
IG1 (μA)
0504020 3010
001aaa572
8
16
24
ID
(mA)
0
VGG (V)
054231
001aaa573
8
4
12
16
ID
(mA)
0
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 14 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
(1) RG1(b) =68k.
(2) RG1(b) =82k.
(3) RG1(b) = 100 k.
(4) RG1(b) = 120 k.
(5) RG1(b) = 150 k.
(6) RG1(b) = 180 k.
(7) RG1(b) = 220 k.
(8) RG1(b) = 270 k.
VG2-S =4V; V
DS(a) =V
G1-S(a) =0V; T
j=25C; RG1(b) is
connected to VGG; see Figure 3.
(1) VGG =5.0V.
(2) VGG =4.5V.
(3) VGG =4.0V.
(4) VGG =3.5V.
(5) VGG =3.0V.
VDS(b) =5V; V
DS(a) =V
G1-S(a) =0V; T
j=25C;
RG1(b) = 150 k(connected to VGG); see Figure 3.
Fig 23. Drain current as a function of gate 1 (VGG),
drain suppl y voltage and v al ue of RG 1; ty pical
values.
Fig 24. Drain current as a function of gate 2 voltage;
typical values.
001aaa574
VGG = VDS (V)
0642
8
16
24
ID
(mA)
0
(1)
(2)
(3)
(4)
(5)
(8)
(6)
(7)
001aaa575
VG2-S (V)
0642
8
4
12
16
ID
(mA)
0
(1)
(3)
(4)
(5)
(2)
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 15 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
(1) VGG =5.0V.
(2) VGG =4.5V.
(3) VGG =4.0V.
(4) VGG =3.5V.
(5) VGG =3.0V.
VDS(b) =5V; V
DS(a) =V
G1-S(a) =0V; T
j=25C;
RG1(b) = 150 k(connected to VGG); see Figure 3.
VDS(b) =5V; V
GG =5V; V
DS(a) =V
G1-S(a) =0V;
RG1(b) = 150 k(connected to VGG); fw=50MHz;
funw =60MHz; T
amb =25C; see Figure 34.
Fig 25. Gate 1 current as a function of gate 2 voltage;
typical valu e s. Fig 26. Unwanted voltage for 1 % cross-modulation as
a function of gain reduction; typical values.
VG2-S (V)
0642
001aaa576
10
20
30
IG1
(μA)
0
(1)
(2)
(4)
(5)
(3)
001aaa577
gain reduction (dB)
0604020
100
90
110
120
Vunw
(dBμV)
80
VDS(b) =5V; V
GG =5V; V
DS(a) =V
G1-S(a) =0V;
RG1(b) = 150 k(connected to VGG); f = 5 0 MHz;
Tamb =25C; see Figure 34.
VDS(b) =5V; V
GG =5V; V
DS(a) =V
G1-S(a) =0V;
RG1(b) = 150 k(connected to VGG); f = 50 MHz;
Tamb =25C; see Figure 34.
Fig 27. Typical gain reduction as a function of AGC
voltage. Fig 28. Drain current as a function of gain reduction;
typical values.
VAGC (V)
04312
001aaa578
30
20
40
10
0
gain
reduction
(dB)
50
001aaa579
gain reduction (dB)
0604020
8
4
12
16
ID
(mA)
0
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 16 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
VDS(b) =5V; V
G2-S =4V; V
DS(a) =V
G1-S(a) =0V; I
D(b)
=13mA. VDS(b) =5V; V
G2-S =4V; V
DS(a) =V
G1-S(a) =0V;
ID(b) =13mA.
Fig 29. Input admittance as a function of frequency;
typical valu e s. Fig 30. Forward transfer admitt ance and phase as a
function of frequency; typical values.
001aaa581
f (MHz)
10 103
102
10−1
1
10
102
bis, gis
(mS)
10−2
bis
gis
f (MHz)
10 103
102
001aaa582
10
102
yfs
(mS)
1
−ϕfs
(deg)
10
102
1
yfs
−ϕfs
VDS(b) =5V; V
G2-S =4V; V
DS(a) =V
G1-S(a) =0V;
ID(b) =13mA. VDS(b) =5V; V
G2-S =4V; V
DS(a) =V
G1-S(a) =0V;
ID(b) =13mA.
Fig 31. Reverse transfer admittance and phase as a
function of frequency ; typ ic al values. Fig 32. Output admittance as a function of frequency;
typical values.
001aaa583
102
10
103
yrs
(μS)
1
102
10
103
−ϕrs
(deg)
1
f (MHz)
10 103
102
yrs
−ϕrs
001aaa584
bos, gos
(mS)
1
10
10−2
10−1
f (MHz)
10 103
102
bos
gos
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 17 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
8.2.2 Scattering parameters for amplifier b
8.2.3 Noise data for amplifier b
Table 12. Scattering parameters for amplifier b
VDS(b) =5V; V
G2-S =4V; I
D(b) =13mA; V
DS(a) =0V; V
G1-S(a) =0V; T
amb =25
C.
f
(MHz) S11 S21 S12 S22
Magnitude
ratio Angle
(deg) Magnitude
ratio Angle
(deg) Magnitude
ratio Angle
(deg) Magnitude
ratio Angle
(deg)
50 0.986 3.66 3.26 175.93 0.0008 84.23 0.988 1.65
100 0.982 7.01 3.24 172.04 0.0015 84.91 0.988 3.27
200 0.975 13.71 3.22 164.24 0.0029 83.96 0.986 6.50
300 0.966 20.36 3.19 156.53 0.0042 82.86 0.984 9.69
400 0.955 27.04 3.15 148.86 0.0055 81.88 0.982 12.88
500 0.943 33.62 3.10 141.24 0.0066 80.92 0.978 16.07
600 0.927 40.16 3.05 133.70 0.0076 80.15 0.975 19.21
700 0.909 46.70 2.99 126.13 0.0086 79.68 0.972 22.35
800 0.891 52.07 2.92 118.64 0.0094 78.28 0.968 25.52
900 0.868 59.48 2.84 111.09 0.0100 78.28 0.965 28.65
1000 0.846 65.86 2.77 103.58 0.0107 78.15 0.961 31.85
Table 13. Noise data for amplifier b
VDS(b) =5V; V
G2-S =4V; I
D(b) =13mA; V
DS(a) =0V; V
G1-S(a) =0V; T
amb =25
C.
f
(MHz) Fmin
(dB) opt rn
()
ratio (deg)
400 1.3 0.695 13.11 0.694
800 1.4 0.674 32.77 0.674
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 18 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
9. Test information
Fig 33. Cross-modulation test set-up for amplifie r a.
50 Ω
10 kΩ
RGEN
50 Ω
RL
50 Ω
50 Ω
RG1
4.7 nF
4.7 nF
4.7 nF
g2 S
g1 (b) d (b)
d (a)
4.7 nF
4.7 nF
4.7 nF
g1 (a)
BF1205C
VGG
0V VDS(b)
5V
VDS(a)
5V
VAGC
L2
2.2 μH
L1
2.2 μH
001aaa563
Vi
Fig 34. Cross-modulation test set-up for amplifie r b.
50 Ω
10 kΩ
RGEN
50 Ω50 ΩRG1
4.7 nF
4.7 nF
4.7 nF
g2 S
g1 (b) d (b)
d (a)
4.7 nF
4.7 nF
4.7 nF
g1 (a)
BF1205C
V
GG
5V
V
DS(b)
5V
V
DS(a)
5V
V
AGC
L2
2.2 μH
L1
2.2 μH
RL
50 Ω
001aaa580
Vi
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 19 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
10. Package outline
Fig 35. Package outline.
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT363 SC-88
wBM
bp
D
e1
e
pin 1
index A
A1
Lp
Q
detail X
HE
E
vMA
AB
y
0 1 2 mm
scale
c
X
132
456
Plastic surface-mounted package; 6 leads SOT363
UNIT A1
max bpcDEe1HELpQywv
mm 0.1 0.30
0.20 2.2
1.8
0.25
0.10 1.35
1.15 0.65
e
1.3 2.2
2.0 0.2 0.10.2
DIMENSIONS (mm are the original dimensions)
0.45
0.15 0.25
0.15
A
1.1
0.8
04-11-08
06-03-16
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 20 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
11. Revision history
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BF1205C v.3 20110907 Product data sheet - BF1205C v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
BF1205C v.2 20060815 Product data sheet - BF120 5C v.1
BF1205C v.1
(9397 750 13005) 20040518 Product data sheet - -
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 21 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
12.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect , incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semicondu ctors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liabili ty related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from national authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the obj ective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
BF1205C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 7 September 2011 22 of 23
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
Quick reference data — The Quick reference dat a is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specif ications.
12.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors BF1205C
Dual N-channel dual gate MOS-FET
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 September 2011
Document identifier: BF1205C
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 3
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Thermal characteristics . . . . . . . . . . . . . . . . . . 3
7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
8.1 Dynamic characteristics for amplifier a. . . . . . . 5
8.1.1 Graphs for amplifier a. . . . . . . . . . . . . . . . . . . . 6
8.1.2 Scattering parameters for amplifier a . . . . . . . 10
8.1.3 Noise data for amplifier a . . . . . . . . . . . . . . . . 10
8.2 Dynamic characteristics for amplifier b. . . . . . 11
8.2.1 Graphs for amplifier b. . . . . . . . . . . . . . . . . . . 12
8.2.2 Scattering parameters for amplifier b . . . . . . . 17
8.2.3 Noise data for amplifier b . . . . . . . . . . . . . . . . 17
9 Test information. . . . . . . . . . . . . . . . . . . . . . . . 18
10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13 Contact information. . . . . . . . . . . . . . . . . . . . . 22
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
