Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. C
01/22/08
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specication and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specication before relying on any published information and before placing orders for products.
IS42S16100E
IC42S16100E
JANUARY 2008
FEATURES
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11
(bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• 2048 refresh cycles every 32 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and
precharge command
• Byte controlled by LDQM and UDQM
• Packages 400-mil 50-pin TSOP-II and 60-ball
BGA
• Lead-free package option
• Available in Industrial Temperature
DESCRIPTION
ISSI’s 16Mb Synchronous DRAM IS42S16100E/
IC42S16100E is organized as a 524,288-word x 16-bit
x 2-bank for improved performance. The synchronous
DRAMs achieve high-speed data transfer using pipeline
architecture. All inputs and outputs signals refer to the
rising edge of the clock input.
512K Words x 16 Bits x 2 Banks (16-MBIT)
SYNCHRONOUS DYNAMIC RAM
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
PIN DESCRIPTIONS
A0-A11 Address Input
A0-A10 Row Address Input
A11 Bank Select Address
A0-A7 Column Address Input
DQ0 to DQ15 Data DQ
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
WE Write Enable
LDQM Lower Bye, Input/Output Mask
UDQM Upper Bye, Input/Output Mask
VDD Power
GND Ground
VDDQ Power Supply for DQ Pin
GNDQ Ground for DQ Pin
NC No Connection
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDD
DQ0
DQ1
GNDQ
DQ2
DQ3
VDDQ
DQ4
DQ5
GNDQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
VDD
GND
DQ15
IDQ14
GNDQ
DQ13
DQ12
VDDQ
DQ11
DQ10
GNDQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
GND
IS42S16100E, IC42S16100E
2 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
PIN CONFIGURATION
PACKAGE CODE:
B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
A11
A8
A6
VSS
DQ15
VSSQ
VDDQ
DQ11
VSSQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
DQ0
VDDQ
VSSQ
DQ4
VDDQ
VSSQ
NC
VDD
LDQM
RAS
NC
NC
A0
A2
A3
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE
CAS
CS
NC
A10
A1
VDD
PIN DESCRIPTIONS
A0-A10 Row Address Input
A0-A7 Column Address Input
A11 Bank Select Address
DQ0 to DQ15 Data I/O
CLK System Clock Input
CKE Clock Enable
CS Chip Select
RAS Row Address Strobe Command
CAS Column Address Strobe Command
WE Write Enable
LDQM, UDQM x16 Input/Output Mask
Vd d Power
Vss Ground
Vd d q Power Supply for I/O Pin
Vssq Ground for I/O Pin
NC No Connection
Integrated Silicon Solution, Inc. — www.issi.com 3
Rev. C
01/22/08
IS42S16100E, IC42S16100E
PIN FUNCTIONS
Pin No. Symbol Type Function (In Detail)
20 to 24 A0-A10 Input Pin A0 to A10 are address inputs. A0-A10 are used as row address inputs during active
27 to 32 command input and A0-A7 as column address inputs during read or write command input.
A10 is also used to determine the precharge mode during other commands. If A10 is
LOW during precharge command, the bank selected by A11 is precharged, but if A10 is
HIGH, both banks will be precharged.
When A10 is HIGH in read or write command cycle, the precharge starts automatically
after the burst access.
These signals become part of the OP CODE during mode register set command input.
19 A11 Input Pin A11 is the bank selection signal. When A11 is LOW, bank 0 is selected and when high,
bank 1 is selected. This signal becomes part of the OP CODE during mode register set
command input.
16 CAS Input Pin CAS, in conjunction with the RAS and WE, forms the device command. See the
“Command Truth Table” item for details on device commands.
34 CKE Input Pin The CKE input determines whether the CLK input is enabled within the device. When is
CKE HIGH, the next rising edge of the CLK signal will be valid, and when LOW, invalid.
When CKE is LOW, the device will be in either the power-down mode, the clock suspend
mode, or the self refresh mode. The CKE is an asynchronous input.
35 CLK Input Pin CLK is the master clock input for this device. Except for CKE, all inputs to this device are
acquired in synchronization with the rising edge of this pin.
18 CS Input Pin The CS input determines whether command input is enabled within the device.
Command input is enabled when CS is LOW, and disabled with CS is HIGH. The device
remains in the previous state when CS is HIGH.
2, 3, 5, 6, 8, 9, 11 DQ0 to DQ Pin DQ0 to DQ15 are DQ pins. DQ through these pins can be controlled in byte units
12, 39, 40, 42, 43, DQ15 using the LDQM and UDQM pins.
45, 46, 48, 49
14, 36 LDQM, Input Pin LDQM and UDQM control the lower and upper bytes of the DQ buffers. In read
UDQM mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is LOW, the
corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to
the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds to OE
in conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When
LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be
written to the device. When LDQM or UDQM is HIGH, input data is masked and cannot
be written to the device.
17 RAS Input Pin RAS, in conjunction with CAS and WE, forms the device command. See the “Command
Truth Table” item for details on device commands.
15 WE Input Pin WE, in conjunction with RAS and CAS, forms the device command. See the “Command
Truth Table” item for details on device commands.
7, 13, 38, 44 VddQ Power Supply Pin VddQ is the output buffer power supply.
1, 25 Vdd Power Supply Pin Vdd is the device internal power supply.
4, 10, 41, 47 GNdQ Power Supply Pin GNdQ is the output buffer ground.
26, 50 GNd Power Supply Pin GNd is the device internal ground.
IS42S16100E, IC42S16100E
4 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
A10
COMMAND
DECODER
&
CLOCK
GENERATORMODE
REGISTER
REFRESH
CONTROLLER
REFRESH
COUNTER
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
LATCH
MULTIPLEXER
ROW
ADDRESS
BUFFER
ROW
ADDRESS
BUFFER
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
ROW DECODER ROW DECODER
MEMORY CELL
ARRAY
BANK 0
COLUMN DECODER
MEMORY CELL
ARRAY
BANK 1
DATA IN
BUFFER
DATA OUT
BUFFER
SENSE AMP I/O GATE
SENSE AMP I/O GATE
2048
2048
DQM
DQ 0-1
5
VDD/VDDQ
GND/GNDQ
11
11
11 11
8
11 11
8
16
16 16
16
256
256
S16BLK.eps
Integrated Silicon Solution, Inc. — www.issi.com 5
Rev. C
01/22/08
IS42S16100E, IC42S16100E
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameters Rating Unit
Vd d m a x Maximum Supply Voltage –1.0 to +4.6 V
Vd d q m a x Maximum Supply Voltage for Output Buffer –1.0 to +4.6 V
Vi N Input Voltage –1.0 to +4.6 V
Vo u t Output Voltage –1.0 to +4.6 V
Pd m a x Allowable Power Dissipation 1 W
Ic s output Shorted Current 50 mA
To p r operating Temperature Com 0 to +70 °C
Ind. -40 to +85 °C
Ts t g Storage Temperature –55 to +150 °C
DC RECOMMENDED OPERATING CONDITIONS(2) (At Ta = 0 to +70°C)
Symbol Parameter Min. Typ. Max. Unit
Vd d , Vd d q Supply Voltage 3.0 3.3 3.6 V
Vi h Input High Voltage(3) 2.0 — Vd d + 0.3 V
Vi l Input Low Voltage(4) -0.3 — +0.8 V
CAPACITANCE CHARACTERISTICS(1,2) (At Ta = 0 to +25°C, VDD = VDDQ = 3.3 ± 0.3V, f = 1 MHz)
Symbol Parameter Typ. Max. Unit
Ci N 1 Input Capacitance: A0-A11 — 4 pF
Ci N 2 Input Capacitance: (CLK, CKE, CS, RAS, CAS, WE, LDQM, UDQM) — 4 pF
CI/O Data Input/Output Capacitance: DQ0-DQ15 — 5 pF
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
2. All voltages are referenced to GND.
3. Vi h (max) = Vd d q + 2.0V with a pulse width ≤ 3 ns.
IS42S16100E, IC42S16100E
6 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
DC ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol Parameter Test Condition Speed Min. Max. Unit
ii l Input Leakage Current 0V ≤ Vi N ≤ Vdd, with pins other than –5 5 µA
the tested pin at 0V
io l Output Leakage Current Output is disabled, 0V ≤ Vo u t ≤ Vdd –5 5 µA
Vo h Output High Voltage Level io u t = –2 mA 2.4 — V
Vo l Output Low Voltage Level io u t = +2 mA — 0.4 V
ic c 1 Operating Current(1,2) One Bank Operation, CAS latency = 3 Com. -5 — 170 mA
Burst Length=1 Com. -6 — 160
tr c ≥ tr c (min.) Com. -7 — 140
Io u t = 0mA Ind. -6 — 170
Ind. -7 — 160
ic c 2p Precharge Standby Current CKE ≤ Vi l (m a x ) tc k = tc k (m i N ) Com. — — 3 mA
Ind. — — 4
Ic c 2p s (In Power-Down Mode) tc k = ∞ Com. — — 2
Ind. — — —
ic c 3N Active Standby Current CKE ≥ Vi h (m i N ) tc k = tc k (m i N ) — — 40 mA
Ic c 3N s (In Non Power-Down Mode) tc k = ∞ Com. — — 30
Ind. — — 30
ic c 4 Operating Current tc k = tc k (m i N ) CAS latency = 3 Com. -5 — 170 mA
(In Burst Mode)(1) Io u t = 0mA Com. -6 — 150
Ind. -6 — 170
Com. -7 — 130
Ind. -7 — 150
CAS latency = 2 Com. -5 — 170 mA
Com. -6 — 150
Ind. -6 — 170
Com. -7 — 130
Ind. -7 — 150
ic c 5 Auto-Refresh Current tr c = tr c (m i N ) CAS latency = 3 Com. -5 — 120 mA
Com. -6 — 100
Ind. -6 — 110
Com. -7 — 70
Ind. -7 — 90
CAS latency = 2 Com. -5 — 120 mA
Com. -6 — 100
Ind. -6 — 110
Com. -7 — 70
Ind. -7 — 90
ic c 6 Self-Refresh Current CKE ≤ 0.2V — — 2 mA
Notes:
1. These are the values at the minimum cycle time. Since the currents are transient, these values decrease as the cycle time in-
creases. Also note that a bypass capacitor of at least 0.01 µF should be inserted between Vd d and GND for each memory chip
to suppress power supply voltage noise (voltage drops) due to these transient currents.
2. Icc1 and Icc4 depend on the output load. The maximum values for Icc1 and Icc4 are obtained with the output open state.
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev. C
01/22/08
IS42S16100E, IC42S16100E
AC CHARACTERISTICS(1,2,3)
-5
-6 -7
Symbol Parameter
Min. Max.
Min. Max. Min. Max. Units
tc k 3 Clock Cycle Time CAS Latency = 3 5 — 6 — 7 — ns
tc k 2 CAS Latency = 2 8 — 8 — 8 — ns
ta c 3 Access Time From CLK(4) CAS Latency = 3 — 5 — 5.5 — 5.5 ns
ta c 2 CAS Latency = 2 — 6 — 6 — 6 ns
tc h i CLK HIGH Level Width 2 — 2.5 — 2.5 — ns
tc l CLK LOW Level Width 2 — 2.5 — 2.5 — ns
to h 3 Output Data Hold Time CAS Latency = 3 2 — 2.0 — 2.0 — ns
to h 2 CAS Latency = 2 2.5 — 2.5 — 2.5 — ns
tl z Output LOW Impedance Time 0 — 0 — 0 — ns
th z 3 Output HIGH Impedance Time(5) CAS Latency = 3 — 4 — 5.5 — 5.5 ns
th z 2 CAS Latency = 2 — 6 — 6 — 6 ns
td s Input Data Setup Time 2 — 2 — 2 — ns
td h Input Data Hold Time 1 — 1 — 1 — ns
ta s Address Setup Time 2 — 2 — 2 — ns
ta h Address Hold Time 1 — 1 — 1 — ns
tc k s CKE Setup Time 2 — 2 — 2 — ns
tc k h CKE Hold Time 1 — 1 — 1 — ns
tc k a CKE to CLK Recovery Delay Time 1CLK+3 — 1CLK+3 — 1CLK+3 — ns
tc s Command Setup Time (CS, RAS, CAS, WE, DQM) 2 — 2 — 2 — ns
tc h Command Hold Time (CS, RAS, CAS, WE, DQM) 1 — 1 — 1 — ns
tr c Command Period (REF to REF / ACT to ACT) 48 — 54 — 63 — ns
tr a s Command Period (ACT to PRE) 32 — 36 100,000 42 100,000 ns
tr p Command Period (PRE to ACT) 16 — 18 — 20 — ns
tr c d Active Command To Read / Write Command Delay Time 16 — 16 — 16 — ns
tr r d Command Period (ACT [0] to ACT[1]) 11 — 12 — 14 — ns
td p l 3 Input Data To Precharge CAS Latency = 3 — 2CLK 2CLK — 2CLK — ns
Command Delay time
td p l 2 CAS Latency = 2 — 2CLK 2CLK — 2CLK — ns
td a l 3 Input Data To Active / Refresh CAS Latency = 3 2CLK+tr p — 2CLK+tr p — 2CLK+tr p — ns
Command Delay time (During Auto-Precharge)
td a l 2 CAS Latency = 2 2CLK+tr p — 2CLK+tr p — 2CLK+tr p — ns
tt Transition Time 1 10 1 10 1 10 ns
tr e f Refresh Cycle Time (2048) — 32 — 32 — 32 ms
Notes:
1. When power is rst applied, memory operation should be started 100 µs after Vd d and Vd d q reach their stipulated voltages. Also note that the power-on
sequence must be executed before starting memory operation.
2. measured with tt = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between Vi h (min.) and Vi l (max.).
4. Access time is measured at 1.4V with the load shown in the gure below.
5. The time th z (max.) is dened as the time required for the output voltage to transition by ± 200 mV from Vo h (min.) or Vo l (max.) when the
output is in the high impedance state.
IS42S16100E, IC42S16100E
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER -5 -6 -7 UNITS
— Clock Cycle Time 5 6 7 ns
— Operating Frequency 200 166 143 MHz
tc a c CAS Latency 3 3 3 cycle
tr c d Active Command To Read/Write Command Delay Time 3 3 3 cycle
tr a c RAS Latency (tr c d + tc a c ) 6 6 6 cycle
tr c Command Period (REF to REF / ACT to ACT) 9 9 9 cycle
tr a s Command Period (ACT to PRE) 6 6 6 cycle
tr p Command Period (PRE to ACT) 3 3 3 cycle
tr r d Command Period (ACT[0] to ACT [1]) 2 2 2 cycle
tc c d Column Command Delay Time 1 1 1 cycle
(READ, READA, WRIT, WRITA)
td p l Input Data To Precharge Command Delay Time 2 2 2 cycle
td a l Input Data To Active/Refresh Command Delay Time 5 5 5 cycle
(During Auto-Precharge)
tr b d Burst Stop Command To Output in HIGH-Z Delay Time 3 3 3 cycle
(Read)
tw b d Burst Stop Command To Input in Invalid Delay Time 0 0 0 cycle
(Write)
tr q l Precharge Command To Output in HIGH-Z Delay Time 3 3 3 cycle
(Read)
tw d l Precharge Command To Input in Invalid Delay Time 0 0 0 cycle
(Write)
tp q l Last Output To Auto-Precharge Start Time (Read) -2 –2 –1 cycle
tq m d DQM To Output Delay Time (Read) 2 2 2 cycle
td m d DQM To Input Delay Time (Write) 0 0 0 cycle
tm c d Mode Register Set To Command Delay Time 2 2 2 cycle
AC TEST CONDITIONS (Input/Output Reference Level: 1.4V)
I/O
50 Ω
+1.4V
50 pF
Output Load
Input
t
OH
t
AC
1.4V 1.4V
t
CH
t
CS
t
CK
t
CHI
t
CL
2.8V
1.4V
0.0V
2.8V
1.4V
0.0V
CLK
INPUT
OUTPUT
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. C
01/22/08
IS42S16100E, IC42S16100E
COMMANDS
CLK
CKE
HIGH
ROW
ROW
BANK 1
BANK 0
CS
RAS
CAS
WE
A0-A9
A10
A11
CLK
CKE
HIGH
COLUMN
BANK 1
AUTO PRECHARGE
NO PRECHARGE
BANK 0
CS
RAS
CAS
WE
A0-A9
A10
A11
(1)
CLK
CKE HIGH
COLUMN
AUTO PRECHARGE
BANK 1
BANK 0
CS
RAS
CAS
WE
A0-A9
A10
A11
CLK
CKE HIGH
BANK 1
BANK 0 AND BANK 1
BANK 0 OR BANK 1NO PRECHARGE
BANK 0
CS
RAS
CAS
WE
A0-A9
A10
A11
(1)
Notes:
1. A8-A9 = Don’t Care.
Active Command Read Command
Write Command Precharge Command
IS42S16100E, IC42S16100E
10 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
COMMANDS (cont.)
CLK
CKE HIGH
CS
RAS
CAS
WE
A0-A9
A10
A11
CLK
CKE HIGH
CS
RAS
CAS
WE
A0-A9
A10
A11
CLK
CKE
HIGH
CS
RAS
CAS
WE
A0-A9
A10
A11
CLK
CKE
HIGH
CS
RAS
CAS
WE
A0-A9
A10
A11
OP-CODE
OP-CODE
OP-CODE
Don't Care
No-Operation Command Device Deselect Command
Mode Register Set Command Auto-Refresh Command
Integrated Silicon Solution, Inc. — www.issi.com 11
Rev. C
01/22/08
IS42S16100E, IC42S16100E
COMMANDS (cont.)
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
BANK(S) ACTIVE
HIGH
NOP
NOP
NOP
NOP
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
ALL BANKS IDLE
NOP
NOP
NOP
NOP
Self-Refresh Command Power Down Command
Clock Suspend Command Burst Stop Command
IS42S16100E, IC42S16100E
12 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Mode Register Set Command
(CS, RAS, CAS, WE = LOW)
The IS42S16100E/IC42S16100E product incorporates
a register that denes the device operating mode. This
command functions as a data input pin that loads this
register from the pins A0 to A11. When power is rst
applied, the stipulated power-on sequence should be
executed and then the IS42S16100E/IC42S16100E
should be initialized by executing a mode register set
command.
Note that the mode register set command can be
executed only when both banks are in the idle state (i.e.
deactivated).
Another command cannot be executed after a mode
register set command until after the passage of the period
tm c d , which is the period required for mode register set
command execution.
Active Command
(CS, RAS = LOW, CAS, WE= HIGH)
The IS42S16100E/IC42S16100E includes two banks of
2048 rows each. This command selects one of the two
banks according to the A11 pin and activates the row
selected by the pins A0 to A10.
This command corresponds to the fall of the RAS signal
from HIGH to LOW in conventional DRAMs.
Precharge Command
(CS, RAS, WE = LOW, CAS = HIGH)
This command starts precharging the bank selected by
pins A10 and A11. When A10 is HIGH, both banks are
precharged at the same time. When A10 is LOW, the
bank selected by A11 is precharged. After executing this
command, the next command for the selected bank(s)
is executed after passage of the period tr p , which is the
period required for bank precharging.
This command corresponds to the RAS signal from LOW
to HIGH in conventional DRAMs
Read Command
(CS, CAS = LOW, RAS, WE = HIGH)
This command selects the bank specied by the A11 pin
and starts a burst read operation at the start address
specied by pins A0 to A9. Data is output following CAS
latency.
The selected bank must be activated before executing
this command.
When the A10 pin is HIGH, this command functions as a
read with auto-precharge command. After the burst read
completes, the bank selected by pin A11 is precharged.
When the A10 pin is LOW, the bank selected by the A11
pin remains in the activated state after the burst read
completes.
Write Command
(CS, CAS, WE = LOW, RAS = HIGH)
When burst write mode has been selected with the mode
register set command, this command selects the bank
specied by the A11 pin and starts a burst write operation
at the start address specied by pins A0 to A9. This rst
data must be input to the DQ pins in the cycle in which
this command.
The selected bank must be activated before executing
this command.
When A10 pin is HIGH, this command functions as a
write with auto-precharge command. After the burst write
completes, the bank selected by pin A11 is precharged.
When the A10 pin is low, the bank selected by the A11
pin remains in the activated state after the burst write
completes.
After the input of the last burst write data, the application
must wait for the write recovery period (td p l , td a l ) to elapse
according to CAS latency.
Auto-Refresh Command
(CS, RAS, CAS = LOW, WE, CKE = HIGH)
This command executes the auto-refresh operation. The
row address and bank to be refreshed are automatically
generated during this operation.
Both banks must be placed in the idle state before executing
this command.
The stipulated period (tr c ) is required for a single refresh
operation, and no other commands can be executed
during this period.
The device goes to the idle state after the internal refresh
operation completes.
This command must be executed at least 4096 times
every 64 ms.
This command corresponds to CBR auto-refresh in
conventional DRAMs.
Integrated Silicon Solution, Inc. — www.issi.com 13
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Self-Refresh Command
(CS, RAS, CAS, CKE = LOW, WE = HIGH)
This command executes the self-refresh operation. The
row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation. The self-refresh operation is started by dropping
the CKE pin from HIGH to LOW. The self-refresh operation
continues as long as the CKE pin remains LOW and there
is no need for external control of any other pins. The
self-refresh operation is terminated by raising the CKE
pin from LOW to HIGH. The next command cannot be
executed until the device internal recovery period (tr c )
has elapsed. After the self-refresh, since it is impossible
to determine the address of the last row to be refreshed,
an auto-refresh should immediately be performed for all
addresses (4096 cycles).
Both banks must be placed in the idle state before executing
this command.
Burst Stop Command
(CS, WE, = LOW, RAS, CAS = HIGH)
The command forcibly terminates burst read and write
operations. When this command is executed during a
burst read operation, data output stops after the CAS
latency period has elapsed.
No Operation
(CS, = LOW, RAS, CAS, WE = HIGH)
This command has no effect on the device.
Device Deselect Command
(CS = HIGH)
This command does not select the device for an object of
operation. In other words, it performs no operation with
respect to the device.
Power-Down Command
(CKE = LOW)
When both banks are in the idle (inactive) state, or when
at least one of the banks is not in the idle (inactive) state,
this command can be used to suppress device power
dissipation by reducing device internal operations to
the absolute minimum. Power-down mode is started by
dropping the CKE pin from HIGH to LOW. Power-down
mode continues as long as the CKE pin is held low. All
pins other than the CKE pin are invalid and none of the
other commands can be executed in this mode. The
power-down operation is terminated by raising the CKE
pin from LOW to HIGH. The next command cannot be
executed until the recovery period (tc k a ) has elapsed.
Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tr e f ). Thus
the maximum time that power-down mode can be held
is just under the refresh cycle time.
Clock Suspend
(CKE = LOW)
This command can be used to stop the device internal clock
temporarily during a read or write cycle. Clock suspend
mode is started by dropping the CKE pin from HIGH to
LOW. Clock suspend mode continues as long as the
CKE pin is held LOW. All input pins other than the CKE
pin are invalid and none of the other commands can be
executed in this mode. Also note that the device internal
state is maintained. Clock suspend mode is terminated
by raising the CKE pin from LOW to HIGH, at which point
device operation restarts. The next command cannot be
executed until the recovery period (tc k a ) has elapsed.
Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tr e f ). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
IS42S16100E, IC42S16100E
14 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
COMMAND TRUTH TABLE(1,2)
CKE
Symbol Command n-1 n CS RAS CAS WE DQM A11 A10 A9-A0 I/On
MRS Mode Register Set(3,4) H X L L L L X OP CODE X
REF Auto-Refresh(5) H H L L L H X X X X HIGH-Z
SREF Self-Refresh(5,6) H L L L L H X X X X HIGH-Z
PRE Precharge Selected Bank H X L L H L X BS L X X
PALL Precharge Both Banks H X L L H L X X H X X
ACT Bank Activate(7) H X L L H H X BS Row Row X
WRIT Write H X L H L L X BS L Column(18) X
WRITA Write With Auto-Precharge(8) H X L H L L X BS H Column(18) X
READ Read(8) H X L H L H X BS L Column(18) X
READA Read With Auto-Precharge(8) H X L H L H X BS H Column(18) X
BST Burst Stop(9) H X L H H L X X X X X
NOP No Operation H X L H H H X X X X X
DESL Device Deselect H X H X X X X X X X X
SBY Clock Suspend / Standby Mode L X X X X X X X X X X
ENB Data Write / Output Enable H X X X X X L X X X Active
MASK Data Mask / Output Disable H X X X X X H X X X HIGH-Z
DQM TRUTH TABLE(1,2)
CKE DQM
Symbol Command n-1 n UPPER LOWER
ENB Data Write / Output Enable H X L L
MASK Data Mask / Output Disable H X H H
ENBU Upper Byte Data Write / Output Enable H X L X
ENBL Lower Byte Data Write / Output Enable H X X L
MASKU Upper Byte Data Mask / Output Disable H X H X
MASKL Lower Byte Data Mask / Output Disable H X X H
CKE TRUTH TABLE(1,2)
CKE
Symbol Command Current State n-1 n CS RAS CAS WE A11 A10 A9-A0
SPND Start Clock Suspend Mode Active H L X X X X X X X
— Clock Suspend Other States L L X X X X X X X
— Terminate Clock Suspend Mode Clock Suspend L H X X X X X X X
REF Auto-Refresh Idle H H L L L H X X X
SELF Start Self-Refresh Mode Idle H L L L L H X X X
SELFX Terminate Self-Refresh Mode Self-Refresh L H L H H H X X X
L H H X X X X X X
PDWN Start Power-Down Mode Idle H L L H H H X X X
H L H X X X X X X
— Terminate Power-Down Mode Power-Down L H X X X X X X X
Integrated Silicon Solution, Inc. — www.issi.com 15
Rev. C
01/22/08
IS42S16100E, IC42S16100E
OPERATION COMMAND TABLE(1,2)
Current State Command Operation CS RAS CAS WE A11 A10 A9-A0
Idl
e DESL No Operation or Power-Down(12) H X X X X X X
NOP No Operation or Power-Down(12) L H H H X X X
BST No Operation or Power-Down L H H L X X X
READ / READA Illegal L H L H V V V(18)
WRIT/WRITA Illegal L H L L V V V(18)
ACT Row Active L L H H V V V(18)
PRE/PALL No Operation L L H L V V X
REF/SELF Auto-Refresh or Self-Refresh(13) L L L H X X X
MRS Mode Register Set L L L L OP CODE
Row Active DESL No Operation H X X X X X X
NOP No Operation L H H H X X X
BST No Operation L H H L X X X
READ/READA Read Start(17) L H L H V V V(18)
WRIT/WRITA Write Start(17) L H L L V V V(18)
ACT Illegal(10) L L H H V V V(18)
PRE/PALL Precharge(15) L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Read DESL Burst Read Continues, Row Active When Done H X X X X X X
NOP Burst Read Continues, Row Active When Done L H H H X X X
BST Burst Interrupted, Row Active After Interrupt L H H L X X X
READ/READA Burst Interrupted, Read Restart After Interrupt(16) L H L H V V V(18)
WRIT/WRITA Burst Interrupted Write Start After Interrupt(11,16) L H L L V V V(18)
ACT Illegal(10) L L H H V V V(18)
PRE/PALL Burst Read Interrupted, Precharge After Interrupt L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Write DESL Burst Write Continues, Write Recovery When Done H X X X X X X
NOP Burst Write Continues, Write Recovery When Done L H H H X X X
BST Burst Write Interrupted, Row Active After Interrupt L H H L X X X
READ/READA Burst Write Interrupted, Read Start After Interrupt(11,16) L H L H V V V(18)
WRIT/WRITA Burst Write Interrupted, Write Restart After Interrupt(16) L H L L V V V(18)
ACT Illegal(10) L L H H V V V(18)
PRE/PALL Burst Write Interrupted, Precharge After Interrupt L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Read With DESL Burst Read Continues, Precharge When Done H X X X X X X
Auto- NOP Burst Read Continues, Precharge When Done L H H H X X X
Precharge BST Illegal L H H L X X X
READ/READA Illegal L H L H V V V(18)
WRIT/WRITA Illegal L H L L V V V(18)
ACT Illegal(10) L L H H V V V(18)
PRE/PALL Illegal(10) L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
IS42S16100E, IC42S16100E
16 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
OPERATION COMMAND TABLE(1,2)
Current State Command Operation CS RAS CAS WE A11 A10 A9-A0
Write With DESL Burst Write Continues, Write Recovery And Precharge H X X X X X X
Auto-Precharge When Done
NOP Burst Write Continues, Write Recovery And Precharge L H H H X X X
BST Illegal L H H L X X X
READ/READA Illegal L H L H V V V(18)
WRIT/WRITA Illegal L H L L V V V(18)
ACT Illegal(10) L L H H V V V(18)
PRE/PALL Illegal(10) L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OPCODE
Row Precharge DESL No Operation, Idle State After tr p Has Elapsed H X X X X X X
NOP No Operation, Idle State After tr p Has Elapsed L H H H X X X
BST No Operation, Idle State After tr p Has Elapsed L H H L X X X
READ/READA Illegal(10) L H L H V V V(18)
WRIT/WRITA Illegal(10) L H L L V V V(18)
ACT Illegal(10) L L H H V V V(18)
PRE/PALL No Operation, Idle State After tr p Has Elapsed(10) L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Immediately DESL No Operation, Row Active After tr c d Has Elapsed H X X X X X X
Following NOP No Operation, Row Active After tr c d Has Elapsed L H H H X X X
Row Active BST No Operation, Row Active After tr c d Has Elapsed L H H L X X X
READ/READA Illegal(10) L H L H V V V(18)
WRIT/WRITA Illegal(10) L H L L V V V(18)
ACT Illegal(10,14) L L H H V V V(18)
PRE/PALL Illegal(10) L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Write DESL No Operation, Row Active After td p l Has Elapsed H X X X X X X
Recovery NOP No Operation, Row Active After td p l Has Elapsed L H H H X X X
BST No Operation, Row Active After td p l Has Elapsed L H H L X X X
READ/READA Read Start L H L H V V V(18)
WRIT/WRITA Write Restart L H L L V V V(18)
ACT Illegal(10) L L H H V V V(18)
PRE/PALL Illegal(10) L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Integrated Silicon Solution, Inc. — www.issi.com 17
Rev. C
01/22/08
IS42S16100E, IC42S16100E
OPERATION COMMAND TABLE(1,2)
Current State Command Operation CS RAS CAS WE A11 A10 A9-A0
Write Recovery DESL No Operation, Idle State After td a l Has Elapsed H X X X X X X
With Auto- NOP No Operation, Idle State After td a l Has Elapsed L H H H X X X
Precharge BST No Operation, Idle State After td a l Has Elapsed L H H L X X X
READ/READA Illegal(10) L H L H V V V(18)
WRIT/WRITA Illegal(10) L H L L V V V(18)
ACT Illegal(10) L L H H V V V(18)
PRE/PALL Illegal(10) L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Refresh DESL No Operation, Idle State After tr p Has Elapsed H X X X X X X
NOP No Operation, Idle State After tr p Has Elapsed L H H H X X X
BST No Operation, Idle State After tr p Has Elapsed L H H L X X X
READ/READA Illegal L H L H V V V(18)
WRIT/WRITA Illegal L H L L V V V(18)
ACT Illegal L L H H V V V(18)
PRE/PALL Illegal L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Mode Register DESL No Operation, Idle State After tm c d Has Elapsed H X X X X X X
Set NOP No Operation, Idle State After tm c d Has Elapsed L H H H X X X
BST No Operation, Idle State After tm c d Has Elapsed L H H L X X X
READ/READA Illegal L H L H V V V(18)
WRIT/WRITA Illegal L H L L V V V(18)
ACT Illegal L L H H V V V(18)
PRE/PALL Illegal L L H L V V X
REF/SELF Illegal L L L H X X X
MRS Illegal L L L L OP CODE
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, V: Valid data input
2. All input signals are latched on the rising edge of the CLK signal.
3. Both banks must be placed in the inactive (idle) state in advance.
4. The state of the A0 to A11 pins is loaded into the mode register as an OP code.
5. The row address is generated automatically internally at this time. The DQ pin and the address pin data is ignored.
6. During a self-refresh operation, all pin data (states) other than CKE is ignored.
7. The selected bank must be placed in the inactive (idle) state in advance.
8. The selected bank must be placed in the active state in advance.
9. This command is valid only when the burst length set to full page.
10. This is possible depending on the state of the bank selected by the A11 pin.
11. Time to switch internal busses is required.
12. The IS42S16100E/IC42S16100E can be switched to power-down mode by dropping the CKE pin LOW when both banks in the
idle state. Input pins other than CKE are ignored at this time.
13. The IS42S16100E/IC42S16100E can be switched to self-refresh mode by dropping the CKE pin LOW when both banks in the
idle state. Input pins other than CKE are ignored at this time.
14. Possible if tr r d is satised.
15. Illegal if tr a s is not satised.
16. The conditions for burst interruption must be observed. Also note that the IS42S16100E/IC42S16100E will enter the pre
charged state immediately after the burst operation completes if auto-precharge is selected.
17. Command input becomes possible after the period tr c d has elapsed. Also note that the IS42S16100E/IC42S16100E will enter
the precharged state immediately after the burst operation completes if auto-precharge is selected.
18. A8,A9 = don’t care.
IS42S16100E, IC42S16100E
18 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
CKE RELATED COMMAND TRUTH TABLE(1)
CKE
Current State Operation n-1 n CS RAS CAS WE A11 A10 A9-A0
Self-Refresh Undened H X X X X X X X X
Self-Refresh Recovery(2) L H H X X X X X X
Self-Refresh Recovery(2) L H L H H X X X X
Illegal(2) L H L H L X X X X
Illegal(2) L H L L X X X X X
Self-Refresh L L X X X X X X X
Self-Refresh Recovery Idle State After tr c Has Elapsed H H H X X X X X X
Idle State After tr c Has Elapsed H H L H H X X X X
Illegal H H L H L X X X X
Illegal H H L L X X X X X
Power-Down on the Next Cycle H L H X X X X X X
Power-Down on the Next Cycle H L L H H X X X X
Illegal H L L H L X X X X
Illegal H L L L X X X X X
Clock Suspend Termination on the Next Cycle (2) L H X X X X X X X
Clock Suspend L L X X X X X X X
Power-Down Undened H X X X X X X X X
Power-Down Mode Termination, Idle After L H X X X X X X X
That Termination(2)
Power-Down Mode L L X X X X X X X
Both Banks Idle No Operation H H H X X X X X X
See the Operation Command Table H H L H X X X X X
Bank Active Or Precharge H H L L H X X X X
Auto-Refresh H H L L L H X X X
Mode Register Set H H L L L L OP CODE
See the Operation Command Table H L H X X X X X X
See the Operation Command Table H L L H X X X X X
See the Operation Command Table H L L L H X X X X
Self-Refresh(3) H L L L L H X X X
See the Operation Command Table H L L L L L OP CODE
Power-Down Mode(3) L X X X X X X X X
Other States See the Operation Command Table H H X X X X X X X
Clock Suspend on the Next Cycle(4) H L X X X X X X X
Clock Suspend Termination on the Next Cycle L H X X X X X X X
Clock Suspend Termination on the Next Cycle L L X X X X X X X
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input
2. The CLK pin and the other input are reactivated asynchronously by the transition of the CKE level from LOW to HIGH.
The minimum setup time (tc k a ) required before all commands other than mode termination must be satised.
3. Both banks must be set to the inactive (idle) state in advance to switch to power-down mode or self-refresh mode.
4. The input must be command dened in the operation command table.
Integrated Silicon Solution, Inc. — www.issi.com 19
Rev. C
01/22/08
IS42S16100E, IC42S16100E
TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2)
Previous State Next State
Operation CS RAS CAS WE A11 A10 A9-A0 BANK 0 BANK 1 BANK 0 BANK 1
DESL H X X X X X X Any Any Any Any
NOP L H H H X X X Any Any Any Any
BST L H H L X X X R/W/A I/A A I/A
I I/A I I/A
I/A R/W/A I/A A
I/A I I/A I
READ/READA L H L H H H CA(3) I/A R/W/A I/A RP
H H CA(3) R/W A A RP
H L CA(3) I/A R/W/A I/A R
H L CA(3) R/W A A R
L H CA(3) R/W/A I/A RP I/A
L H CA(3) A R/W RP A
L L CA(3) R/W/A I/A R I/A
L L CA(3) A R/W R A
WRIT/WRITA L H L L H H CA(3) I/A R/W/A I/A WP
H H CA(3) R/W A A WP
H L CA(3) I/A R/W/A I/A W
H L CA(3) R/W A A W
L H CA(3) R/W/A I/A WP I/A
L H CA(3) A R/W WP A
L L CA(3) R/W/A I/A W I/A
L L CA(3) A R/W W A
ACT L L H H H RA RA Any I Any A
L RA RA I Any A Any
PRE/PALL L L H L X H X R/W/A/I I/A I I
X H X I/A R/W/A/I I I
H L X I/A R/W/A/I I/A I
H L X R/W/A/I I/A R/W/A/I I
L L X R/W/A/I I/A I I/A
L L X I/A R/W/A/I I R/W/A/I
REF L L L H X X X I I I I
MRS L L L L OPCODE I I I I
Notes:
1. H: HIGH level input, L: LOW level input, X: HIGH or LOW level input, RA: Row Address, CA: Column Address
2. The device state symbols are interpreted as follows:
I Idle (inactive state)
A Row Active State
R Read
W Write
RP Read With Auto-Precharge
WP Write With Auto-Precharge
Any Any State
3. CA: A8,A9 = don’t care.
IS42S16100E, IC42S16100E
20 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
SIMPLIFIED STATE TRANSITION DIAGRAM (One Bank Operation)
SELF
REFRESH
AUTO
REFRESH
IDLE
POWER
DOWN
ACTIVE
POWER
DOWN
IDLE
MODE
REGISTER
SET
READ
BANK
ACTIVE
WRITE
CLOCK
SUSPEND
READ WITH
AUTO
PRECHARGE
PRE-
CHARGE
POWER ON
WRITE WITH
AUTO
PRECHARGE
CLOCK
SUSPEND
Tr ansition due to command input.
Automatic transition following the
completion of command execution.
MRS
SREF entry
SREF exit
REF
CKE_
CKE
ACT
CKE_
CKE
BST BST
READ
CKE_
CKE
READA
CKE_
CKE
READ
READA
READ
WRITA
WRIT
WRIT
CKE_
CKE
WRITA
CKE_
CKE
WRIT
WRITA
PRE
PRE
READA
PRE
PRE
POWER APPLIED
Integrated Silicon Solution, Inc. — www.issi.com 21
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Device Initialization At Power-On
(Power-On Sequence)
As is the case with conventional DRAMs, the IS42S16100E/
IC42S16100E product must be initialized by executing a
stipulated power-on sequence after power is applied.
After power is applied and Vdd and VddQ reach their
stipulated voltages, set and hold the CKE and DQM pins
HIGH for 100 µs. Then, execute the precharge command
to precharge both bank. Next, execute the auto-refresh
command twice or more and dene the device operation
mode by executing a mode register set command.
The mode register set command can be also set before
auto-refresh command.
Mode Register Settings
The mode register set command sets the mode register.
When this command is executed, pins A0 to A9, A10, and
A11 function as data input pins for setting the register, and
this data becomes the device internal OP code. This OP
code has four elds as listed in the table below.
Note that the mode register set command can be executed
only when both banks are in the idle (inactive) state. Wait
at least two cycles after executing a mode register set
command before executing the next command.
CAS Latency
During a read operation, the between the execution of the
read command and data output is stipulated as the CAS
latency. This period can be set using the mode register
set command. The optimal CAS latency is determined
by the clock frequency and device speed grade. See the
“Operating Frequency / Latency Relationships” item for
details on the relationship between the clock frequency
and the CAS latency. See the table on the next page for
details on setting the mode register.
Input Pin Field
A11, A10, A9, A8, A7 Mode Options
A6, A5, A4 CAS Latency
A3 Burst Type
A2, A1, A0 Burst Length
Burst Length
When writing or reading, data can be input or output data
continuously. In these operations, an address is input only
once and that address is taken as the starting address
internally by the device. The device then automatically
generates the following address. The burst length eld in
the mode register stipulates the number of data items input
or output in sequence. In the IS42S16100E/IC42S16100E
product, a burst length of 1, 2, 4, 8, or full page can be
specied. See the table on the next page for details on
setting the mode register.
Burst Type
The burst data order during a read or write operation is
stipulated by the burst type, which can be set by the mode
register set command. The IS42S16100E/IC42S16100E
product supports sequential mode and interleaved mode
burst type settings. See the table on the next page for
details on setting the mode register. See the “Burst Length
and Column Address Sequence” item for details on DQ
data orders in these modes.
Write Mode
Burst write or single write mode is selected by the OP code
(A11, A10, A9) of the mode register.
A burst write operation is enabled by setting the OP code
(A11, A10, A9) to (0,0,0). A burst write starts on the same
cycle as a write command set. The write start address is
specied by the column address and bank select address
at the write command set cycle.
A single write operation is enabled by setting OP code (A11,
A10, A9) to (0, 0,1). In a single write operation, data is only
written to the column address and bank select address
specied by the write command set cycle without regard
to the bust length setting.
IS42S16100E, IC42S16100E
22 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
MODE REGISTER
M2 M1 M0 Sequential Interleaved
Burst Length 0 0 0 1 1
0 0 1 2 2
0 1 0 4 4
0 1 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
WRITE MODE LT MODE BT BL
M3 Type
Burst Type 0 Sequential
1 Interleaved
M6 M5 M4 CAS Latency
Latency Mode 0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
M11 M10 M9 M8 M7 Write Mode
0 0 1 0 0 Burst Read & Single Write
0 0 0 0 0 Burst Read & Burst Write
Address Bus (Ax)
Mode Register (Mx)
Note: Other values for these bits are reserved.
Integrated Silicon Solution, Inc. — www.issi.com 23
Rev. C
01/22/08
IS42S16100E, IC42S16100E
BURST LENGTH AND COLUMN ADDRESS SEQUENCE
Column Address Address Sequence
Burst Length A2 A1 A0 Sequential Interleaved
2 X X 0 0-1 0-1
X X 1 1-0 1-0
4 X 0 0 0-1-2-3 0-1-2-3
X 0 1 1-2-3-0 1-0-3-2
X 1 0 2-3-0-1 2-3-0-1
X 1 1 3-0-1-2 3-2-1-0
8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Full Page n n n Cn, Cn+1, Cn+2 None
(256) Cn+3, Cn+4.....
...Cn-1(Cn+255),
Cn(Cn+256).....
Notes:
1. The burst length in full page mode is 256.
IS42S16100E, IC42S16100E
24 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
BANK SELECT AND PRECHARGE ADDRESS ALLOCATION
Row X0 — Row Address
X1 — Row Address
X2 — Row Address
X3 — Row Address
X4 — Row Address
X5 — Row Address
X6 — Row Address
X7 — Row Address
X8 — Row Address
X9 — Row Address
X10 0 Precharge of the Selected Bank (Precharge Command) Row Address
1 Precharge of Both Banks (Precharge Command) (Active
Command)
X11 0 Bank 0 Selected (Precharge and Active Command)
1 Bank 1 Selected (Precharge and Active Command)
Column Y0 — Column Address
Y1 — Column Address
Y2 — Column Address
Y3 — Column Address
Y4 — Column Address
Y5 — Column Address
Y6 — Column Address
Y7 — Column Address
Y8 — Don’t Care
Y9 — Don’t Care
Y10 0 Auto-Precharge - Disabled
1 Auto-Precharge - Enables
Y11 0 Bank 0 Selected (Read and Write Commands)
1 Bank 1 Selected (Read and Write Commands)
Integrated Silicon Solution, Inc. — www.issi.com 25
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
used as the starting address. First, the data corresponding to
this address is output in synchronization with the clock signal
after the CAS latency period. Next, data corresponding to
an address generated automatically by the device is output
in synchronization with the clock signal.
The output buffers go to the LOW impedance state CAS
latency minus one cycle after the read command, and go to
the HIGH impedance state automatically after the last data
is output. However, the case where the burst length
is a full page is an exception. In this case the output buffers
must be set to the high impedance state by executing a
burst stop command.
Note that upper byte and lower byte output data can
be masked independently under control of the signals
applied to the U/LDQM pins. The delay period (tq m d ) is
xed at two, regardless of the CAS latency setting, when
this function is used.
The selected bank must be set to the active state before
executing this command.
CAS latency = 3, burst length = 4
Burst Write
The write cycle is started by executing the command.
The address provided during write command execution
is used as the starting address, and at the same time,
data for this address is input in synchronization with the
clock signal.
Next, data is input in other in synchronization with the
clock signal. During this operation, data is written to
address generated automatically by the device. This cycle
terminates automatically after a number of clock cycles
determined by the stipulated burst length. However, the
case where the burst length is a full page is an exception.
In this case the write cycle must be terminated by executing
a burst stop command. The latency for DQ pin data input
is zero, regardless of the CAS latency setting. However, a
wait period (write recovery: td p l ) after the last data input is
required for the device to complete the write operation.
Note that the upper byte and lower byte input data can
be masked independently under control of the signals
applied to the U/LDQM pins. The delay period (td m d ) is
xed at zero, regardless of the CAS latency setting, when
this function is used.
The selected bank must be set to the active state before
executing this command.
CAS latency = 2,3, burst length = 4
READ A0
COMMAND
UDQM
LDQM
DQ8-DQ15
DQ0-DQ 7
CLK
D
OUT
A0
t
QMD=2
HI-Z
HI-Z
HI-Z
READ (CA=A, BANK 0) DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
D
OUT
A2 D
OUT
A3
D
OUT
A1D
OUT
A0
BURST LENGTH
WRITE
COMMAND
DQ
CLK
DIN 0DIN 1DIN 2DIN 3
IS42S16100E, IC42S16100E
26 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read With Auto-Precharge
The read with auto-precharge command rst executes a
burst read operation and then puts the selected bank in
the precharged state automatically. After the precharge
completes, the bank goes to the idle state. Thus this
command performs a read command and a precharge
command in a single operation.
During this operation, the delay period (tp q l ) between the
last burst data output and the start of the precharge opera-
tion differs depending on the CAS latency setting.
When the CAS latency setting is two, the precharge opera-
tion starts on one clock cycle before the last burst data is
output (tp q l = –1). When the CAS latency setting is
three, the precharge operation starts on two clock cycles
before the last burst data is output (tp q l = –2). Therefore,
the selected bank can be made active after a delay of tr p
from the start position of this precharge operation.
The selected bank must be set to the active state before
executing this command.
The auto-precharge function is invalid if the burst length
is set to full page.
CAS Latency 3 2
tp q l –2 –1
COMMAND
DQ
CLK
tRP
tPQL
READA 0
ACT 0
PRECHARGE START
READ WITH AUTO-PRECHARGE
(BANK 0)
D
OUT
0D
OUT
1D
OUT
2D
OUT
3
COMMAND
DQ
CLK
READA 0
ACT 0
t
RP
PRECHARGE START
READ WITH AUTO-PRECHARGE
(BANK 0)
t
PQL
D
OUT
0D
OUT
1D
OUT
2D
OUT
3
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com 27
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write With Auto-Precharge
The write with auto-precharge command rst executes a
burst write operation and then puts the selected bank in
the precharged state automatically. After the precharge
completes the bank goes to the idle state. Thus this
command performs a write command and a precharge
command in a single operation.
During this operation, the delay period (td a l ) between the
last burst data input and the completion of the precharge
operation differs depending on the CAS latency setting.
The delay (td a l ) is tr p plus one CLK period. That is, the
precharge operation starts one clock period after the last
burst data input.
Therefore, the selected bank can be made active after a
delay of td a l .
The selected bank must be set to the active state before
executing this command.
The auto-precharge function is invalid if the burst length
is set to full page.
CAS Latency 3 2
td a l 2CLK 2CLK
+tr p +tr p
tRP
tDAL
PRECHARGE START
DQ
WRITE A0
COMMAND
CLK
ACT 0
WRITE WITH AUTO-PRECHARGE
(BANK 0)
tRP
tDAL
PRECHARGE START
WRITE A0
COMMAND
DQ
CLK
DIN 0DIN 1DIN 2DIN 3
ACT 0
WRITE WITH AUTO-PRECHARGE
(BANK 0)
DIN 0DIN 1DIN 2DIN 3
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
IS42S16100E, IC42S16100E
28 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Interval Between Read Command
A new command can be executed while a read cycle
is in progress, i.e., before that cycle completes. When
the second read command is executed, after the CAS
latency has elapsed, data corresponding to the new read
command is output in place of the data due to the previous
read command.
The interval between two read command (tc c d ) must be
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
Interval Between Write Command
A new command can be executed while a write cycle is in
progress, i.e., before that cycle completes. At the point the
second write command is executed, data corresponding
to the new write command can be input in place of the
data for the previous write command.
The interval between two write commands (tc c d ) must be
at least one clock cycle.
The selected bank must be set to the active state before
executing this command.
READ A0 READ B0
COMMAND
DQ
CLK
D
OUT
A0 D
OUT
B0 D
OUT
B1 D
OUT
B2
READ (CA=A, BANK 0) READ (CA=B, BANK 0)
t
CCD
D
OUT
B3
CAS latency = 2, burstlength = 4
WRITE A0 WRITE B0
COMMAND
DQ
CLK
DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
WRITE (CA=A, BANK 0) WRITE (CA=B, BANK 0)
tCCD
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com 29
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Interval Between Write and Read Commands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the CAS latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
The interval (tc c d ) between command must be at least
one clock cycle.
The selected bank must be set to the active state before
executing this command.
DQ
WRITE A0 READ B0
COMMAND
CLK
DIN A0 DOUT B0 DOUT B2DOUT B1 DOUT B3
t
CCD
HI-Z
WRITE
(
CA=A, BANK 0
)
READ
(
CA=B, BANK 0
)
DQ
WRITE A0 READ B0
COMMAND
CLK
D
IN
A0
DOUT B0 DOUT B2DOUT B1 DOUT B3
t
CCD
HI-Z
WRITE (CA=A, BANK 0) READ (CA=B, BANK 0)
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
IS42S16100E, IC42S16100E
30 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Interval Between Read and Write Commands
A read command can be interrupted and a new write
command executed while the read cycle is in progress,
i.e., before that cycle completes. Data corresponding
to the new write command can be input at the point
new write command is executed. To prevent collision
between input and output data at the DQn pins during
this operation, the
output data must be masked using the U/LDQM pins. The
interval (tc c d ) between these commands must be at least
one clock cycle.
The selected bank must be set to the active state before
executing this command.
WRITE B0
READ A0
COMMAND
U/LDQM
DQ
CLK
D
IN
B0 D
IN
B2D
IN
B1 D
IN
B3
t
CCD
HI-Z
READ (CA=A, BANK 0) WRITE (CA=B, BANK 0)
CAS latency = 2, 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com 31
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Precharge
The precharge command sets the bank selected by
pin A11 to the precharged state. This command can be
executed at a time tr a s following the execution of an active
command to the same bank. The selected bank goes to
the idle state at a time tr p following the execution of the
precharge command, and an active command can be
executed again for that bank.
If pin A10 is low when this command is executed, the bank
selected by pin A11 will be precharged, and if pin A10 is
HIGH, both banks will be precharged at the same time.
This input to pin A11 is ignored in the latter case.
Read Cycle Interruption
Using the Precharge Command
A read cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tr q l ) from the execution of the precharge
command to the completion of the burst output is the
clock cycle of CAS latency.
CAS Latency 3 2
tr q l 3 2
t
RQL
t
RQL
PRE 0
READ A0
COMMAND
DQ
CLK
D
OUT
A0 D
OUT
A1 D
OUT
A2
HI-Z
READ (CA=A, BANK 0) PRECHARGE (BANK 0)
PRE 0
READ A0
COMMAND
DQ
CLK
D
OUT
A0 D
OUT
A1 D
OUT
A2
HI-Z
READ
(
CA=A, BANK 0
)
PRECHARGE
(
BANK 0
)
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
IS42S16100E, IC42S16100E
32 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle Interruption Using the
Precharge Command
A write cycle can be interrupted by the execution of the
precharge command before that cycle completes. The
delay time (tw d l ) from the precharge command to the point
where burst input is invalid, i.e., the point where input data
is no longer written to device internal memory is zero clock
cycles regardless of the CAS.
To inhibit invalid write, the DQM signal must be asserted
HIGH with the precharge command.
This precharge command and burst write command must
be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of dual bank operation.
Inversely, to write all the burst data to the device, the
precharge command must be executed after the write
data recovery period (td p l ) has elapsed. Therefore, the
precharge command must be executed on one clock
cycle that follows the input of the last burst data item.
CAS Latency 3 2
tw d l 0 0
td p l 1 1
PRE 0
WRITE A0
COMMAND
DQM
DQ
CLK
DIN A0 DIN A1 DIN A2 DIN A3
tWDL=0
WRITE (CA=A, BANK 0) PRECHARGE (BANK 0)
MASKED BY DQM
PRE 0
WRITE A0
COMMAND
DQ
CLK
DIN A0 DIN A1 DIN A2 DIN A3
tDPL
WRITE (CA=A, BANK 0) PRECHARGE (BANK 0)
CAS latency = 2, burstlength = 4
CAS latency = 3, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com 33
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16100E/IC42S16100E can output data
continuously from the burst start address (a) to location
a+255 during a read cycle in which the burst length is set
to full page. The IS42S16100E/IC42S16100E repeats the
operation starting at the 256th cycle with the data output
returning to location (a) and continuing with a+1, a+2, a+3,
etc. A burst stop command must be executed to terminate
this cycle. A precharge command must be executed within
the ACT to PRE command period (tr a s max.) following the
burst stop command.
After the period (tr b d ) required for burst data output to
stop following the execution of the burst stop command
has elapsed, the outputs go to the HIGH impedance
state. This period (tr b d ) is two clock cycle when the
CAS latency is two and three clock cycle when the CAS
latency is three.
CAS Latency 3 2
tr b d 3 2
BST
READ A0
COMMAND
DQ
CLK
tRBD
READ (CA=A, BANK 0) BURST STOP
HI-Z
D
OUT
A0 D
OUT
A0 D
OUT
A1 D
OUT
A2
COMMAND
DQ
CLK
tRBD
READ A0
READ (CA=A, BANK 0) BURST STOP
BST
HI-Z
D
OUT
A0 D
OUT
A0 D
OUT
A1 D
OUT
A2 D
OUT
A3
D
OUT
A3
CAS latency = 3, burstlength = 4
CAS latency = 2, burstlength = 4
IS42S16100E, IC42S16100E
34 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The IS42S16100E/IC42S16100E can input data
continuously from the burst start address (a) to location
a+255 during a write cycle in which the burst length
is set to full page. The IS42S16100E/IC42S16100E
repeats the operation starting at the 256th cycle with
data input returning to location (a) and continuing with
a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command
must be executed within the ACT to PRE command
period (tr a s max.) following the burst stop command.
After the period (tw b d ) required for burst data input to
stop following the execution of the burst stop command
has elapsed, the write cycle terminates. This period
(tw b d ) is zero clock cycles, regardless of the CAS
latency.
Burst Data Interruption Using the U/LDQM
Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the CAS latency, two clock cycles (tq m d ) after one of the
U/LDQM pins goes HIGH, the corresponding outputs go
to the HIGH impedance state. Subsequently, the outputs
are maintained in the high impedance state as long as
that U/LDQM pin remains HIGH. When the U/LDQM pin
goes LOW, output is resumed at a time tq m d later. This
output control operates independently on a byte basis
with the UDQM pin controlling upper byte output (pins
DQ8-DQ15) and the LDQM pin controlling lower byte
output (pins DQ0 to DQ7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CAS latency = 2, burstlength = 4
READ A0
COMMAND
UDQM
LDQM
DQ8-DQ15
DQ0-DQ 7
CLK
DOUT A0
t
QMD=2
HI-Z
HI-Z
HI-Z
READ (CA=A, BANK 0) DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
DOUT A2 DOUT A3
DOUT A1DOUT A0
WRITE A0
COMMAND
DQ
CLK
D
IN
A0 D
IN
A1 D
IN
AD
IN
A1 D
IN
A2
t
WBD=0
t
RP
READ (CA=A, BANK 0) BURST STOP
BST PRE 0
INVALID DATA
PRECHARGE (BANK 0)
Don't Care
Integrated Silicon Solution, Inc. — www.issi.com 35
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Burst Data Interruption U/LDQM Pins (Write
Cycle)
Burst data input can be temporarily interrupted (muted )
during a write cycle using the U/LDQM pins. Regardless
of the CAS latency, as soon as one of the U/LDQM pins
goes HIGH, the corresponding externally applied input
data will no longer be written to the device internal circuits.
Subsequently, the corresponding input continues to be
muted as long as that U/LDQM pin remains HIGH.
The IS42S16100E/IC42S16100E will revert to accepting
input as soon as
that pin is dropped to LOW and data will be written to the
device. This input control operates independently on a byte
basis with the UDQM pin controlling upper byte input (pin
DQ8 to DQ15) and the LDQM pin controlling the lower
byte input (pins DQ0 to DQ7).
Since the U/LDQM pins control the device input buffers
only, the cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
Burst Read and Single Write
The burst read and single write mode is set up using the
mode register set command. During this operation, the burst
read cycle operates normally, but the write cycle only writes
a single data item for each write cycle. The CAS latency
and DQM latency are the same as in normal mode.
WRITE A0
COMMAND
UDQM
LDQM
DQ8-DQ15
DQ0-DQ7
CLK
DIN A1
WRITE (CA=A, BANK 0) DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
tDMD=0
DIN A2 DIN A3
DIN A0 DIN A3
Don't Care
CAS latency = 2, 3
CAS latency = 2, burstlength = 4
WRITE A0
COMMAND
DQ
CLK
DIN A0
WRITE (CA=A, BANK 0)
IS42S16100E, IC42S16100E
36 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Bank Active Command Interval
When the selected bank is precharged, the period trp
has elapsed and the bank has entered the idle state,
the bank can be activated by executing the active
command. If the other bank is in the idle state at that
time, the active command can be executed for that bank
after the period tr r d has elapsed. At that point both
banks will be in the active state. When a bank active
command has been executed, a precharge command
must be executed for
that bank within the ACT to PRE command period (tr a s max).
Also note that a precharge command cannot be executed
for an active bank before tr a s (min) has elapsed.
After a bank active command has been executed and
the trcd period has elapsed, read write (including auto-
precharge) commands can be executed for that bank.
ACT 0ACT 1
COMMAND
CLK
BANK ACTIVE (BANK 0) BANK ACTIVE (BANK 1)
t
RRD
ACT 0 READ 0
COMMAND
CLK
BANK ACTIVE (BANK 0) BANK ACTIVE (BANK 0)
t
RCD
CAS latency = 3
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during
a read or write cycle, the IS42S16100E/IC42S16100E
enters clock suspend mode on the next CLK rising edge.
This command reduces the device power dissipation by
stopping the device internal clock. Clock suspend mode
continues as long as the CKE pin remains low. In this
state, all inputs other than CKE pin are invalid and no
other commands can be executed. Also, the device internal
states are maintained. When the CKE pin goes from LOW
to HIGH clock suspend mode is terminated on the next
CLK rising edge and device operation resumes.
The next command cannot be executed until the recovery
period (tc k a ) has elapsed.
Since this command differs from the self-refresh command
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
READ 0
COMMAND
CKE
DQ
CLK
D
OUT 0DOUT 1DOUT 2DOUT 3
READ (BANK 0) CLOCK SUSPEND
CAS latency = 2, burstlength = 4
Integrated Silicon Solution, Inc. — www.issi.com 37
Rev. C
01/22/08
IS42S16100E, IC42S16100E
OPERATION TIMING EXAMPLE
Power-On Sequence, Mode Register Set Cycle
CLK
CKE HIGH
HIGH
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T10 T17 T18 T19 T20
tCK tCHI tCL
tCHtCS
tCH
tCS
tCHtCS
tCHtCS
tAHtAS
BANK 0 & 1
tAHtAS
tAHtAS
tAHtAS
CODE
CODE
CODE
ROW
ROW
BANK 1
BANK 0
WAIT TIME
T=100 µs
tRP tRC tRC tMCD tRAS
tRC
<ACT><MRS><REF>
<PALL><REF>
CAS latency = 2, 3
Don't Care
Undefined
IS42S16100E, IC42S16100E
38 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Power-Down Mode Cycle
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3
tCK
tCKS tCHI tCL
tCH
tCS
tCHtCS
tCHtCS
tCHtCS
tAHtAS
ROW
ROW
BANK 1
BANK 0
tCKS tCKH
tCKA
tCKA
tAHtAS
tRP POWER DOWN MODE
EXIT
POWER DOWN MODE tRAS
tRC
<ACT><SBY>
<PRE>
<PALL>
BANK 0 & 1
BANK 0 OR 1
BANK 1
BANK 0
CAS latency = 2, 3
Don't Care
Undefined
Integrated Silicon Solution, Inc. — www.issi.com 39
Rev. C
01/22/08
IS42S16100E, IC42S16100E
CAS latency = 2, 3
Auto-Refresh Cycle
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 Tl Tm Tn Tn+1
tCK tCHI tCL
tCHtCS
tCHtCS
tCHtCS
tCHtCS
tAHtAS
BANK 0 & 1
ROW
ROW
BANK 1
BANK 0
t
RP
t
RC
t
RC
t
RC
t
RAS
t
RC
<
ACT
><
REF
><
REF
>
<
PALL
><
REF
>
t
CKS
Don't Care
Undefined
IS42S16100E, IC42S16100E
40 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
CAS latency = 2, 3
Self-Refresh Cycle
Don't Care
Undefined
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 Tm Tm+2Tm+1 Tn
tCK tCHI tCL
tCHtCS
tCHtCS
tCHtCS
tCHtCS
tAHtAS
BANK 0 & 1
tCKS
tCKS
tCKA
tCKA
tRP SELF REFRESH MODE
EXIT
SELF
REFRESH
tRC tRC
<REF>
<PALL><SELF>
tCKS
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 41
Rev. C
01/22/08
IS42S16100E, IC42S16100E
CAS latency = 2, burstlength = 4
Don't Care
Undefined
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCHtCS
tCHtCS
tCH
tCS
tCHtCS
tAH
tAS
BANK 1
BANK 0 AND 1
BANK 0 OR 1
NO PRE
tAH
tAS
tCS
tAHtAS
tCKS
tCKA
BANK 0BANK 0
BANK 1 BANK 1
BANK 0
BANK 1
BANK 0
ROWROW
ROW
COLUMN m
ROW
tQMD
tLZ
tRAS
tRC
<ACT><READ><ACT>
<PRE>
<PALL>
tRCD tCAC tRQL
tRP
tRCD
tAC tAC
tOH
tAC tAC
tOH
tCH
tOH
D
OUT
mD
OUT
m+1 D
OUT
m+2
tOH
tHZ
D
OUT
m+3
tRC
tRAS
(1)
Read Cycle
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
42 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
CAS latency = 2, burstlength = 4
Don't Care
Undefined
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
AUTO PRE
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0BANK 0
BANK 1 BANK 1
BANK 0
ROWROW
ROW
COLUMN m
ROW
t
QMD
t
LZ
t
RAS
t
RC
<
ACT
><
READA
><
ACT
>
t
RCD
t
CAC
t
PQL
t
RP
t
RCD
t
AC
t
AC
t
OH
t
AC
t
AC
t
OH
t
CH
t
OH
D
OUT
mD
OUT
m+1 D
OUT
m+2
t
OH
t
HZ
D
OUT
m+3
t
RC
t
RAS
(1)
Read Cycle / Auto-Precharge
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 43
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle / Full Page
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T260 T261 T262 T263
tCK tCHI tCL
tCHtCS
tCHtCS
tCHtCS
tCHtCS
tAH
tAS
NO PRE
tAH
tAS
tCS
tAHtAS
tCKS
tCKA
BANK 0
BANK 0
BANK 0 OR 1
BANK 0
ROW
COLUMN
ROW
tQMD
tLZ
tRAS
tRC
(BANK 0)
<ACT 0><READ0><BST><PRE 0>
tRCD tCAC
(BANK 0)
tRBD
tAC tAC
tOH
tAC tAC tAC
tOH
tCH
tOH
D
OUT
0m D
OUT
0m+1 D
OUT
0m-1
tOH
tHZ
tOH
D
OUT
0m D
OUT
0m+1
tRP
(BANK 0)
(1)
CAS latency = 2, burstlength = full page
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
44 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle / Ping-Pong Operation (Bank Switching)
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 0 BANK 0 BANK 0 BANK 0 BANK 1
BANK 1
BANK 1
BANK 0 OR 1 BANK 0 OR 1NO PRE
NO PRE
t
CH
t
AH
t
AS
t
QMD
t
CS
t
AC
t
AC
t
AC
t
AC
t
RCD
(BANK 0)
t
RAS
(BANK 0)
<
ACT 0
>
<
ACT 0
><
ACT1
>
<
READ 0
>
<
READA 0
><
READA 1
>
<
READ 1
><
PRE 0
><
PRE 1
>
t
AH
t
AS
t
CKS
t
CKA
ROWROW
ROWROW
ROW
COLUMN COLUMN
AUTO PRE AUTO PRE
ROW
t
LZ
t
LZ
t
RCD
(BANK 1)
t
RAS
(BANK 1)
t
RC
(BANK 1)
t
CAC
(BANK 1)
t
CAC
(BANK 1)
t
RC
(BANK 0)
t
RP
(BANK 0)
t
RP
(BANK1)
t
RCD
(BANK 0)
t
RAS
(BANK 0)
t
RC
(BANK 0)
t
RRD
(BANK 0 TO 1)
t
OH
t
OH
t
OH
t
OH
t
HZ
t
HZ
D
OUT
0m D
OUT
0m+1 D
OUT
1m D
OUT
1m+1
(1)(1)
CAS latency = 2, burstlength = 2
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 45
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0
BANK 0 OR 1
BANK 0 AND 1
NO PRE
t
CH
t
AH
t
AS
t
CS
t
DS
t
DS
t
DS
t
DS
t
DH
t
RAS
t
RC
<
PRE
>
<
PALL
>
<
ACT
><
ACT
><
WRIT
>
t
AH
t
AS
t
CKS
t
CKA
ROWROW
ROW
COLUMN m
ROW
t
RCD
t
DH
t
DH
t
DH
t
RP
t
DPL
t
RCD
t
RAS
t
RC
DIN m DIN m+2
DIN m+1 DIN m+3
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
(1)
CAS latency = 2, burstlength = 4
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
46 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle / Auto-Precharge
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0
AUTO PRE
t
CH
t
AH
t
AS
t
CS
t
DS
t
DS
t
DS
t
DS
t
DH
t
RAS
t
RC
<
ACT
><
ACT
><
WRITA
>
t
AH
t
AS
t
CKS
t
CKA
ROWROW
ROW
COLUMN m
ROW
t
RCD
t
DH
t
DH
t
DH
t
RP
t
DAL
t
RCD
t
RAS
t
RC
DIN m DIN m+2
DIN m+1 DIN m+3
BANK 1
BANK 0
BANK 1
BANK 0
(1)
CAS latency = 2, burstlength = 4
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 47
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle / Full Page
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T259T258 T260 T261 T262
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
NO PRE
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0
BANK 0
BANK 0 OR 1
BANK 0
ROW
COLUMN m
ROW
t
RAS
t
RC
<
ACT 0
><
WRIT0
><
BST
><
PRE 0
>
t
RCD
t
CH
t
DPL
t
RP
t
DS
t
DS
t
DS
t
DS
t
DH
t
DH
t
DH
t
DH
DIN 0m DIN 0m+2
DIN 0m+1 DIN 0m-1 DIN 0m
(1)
CAS latency = 2, burst length = full page
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
48 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle / Ping-Pong Operation
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCH
tCS
tCHtCS
tCHtCS
tCHtCS
tAH
tAS
BANK 0 BANK 0 BANK 0 BANK 0
BANK 1
BANK 1
BANK 0 OR 1NO PRE
NO PRE
tCH
tAH
tAS
tCS
tDS tDS
tRCD
(BANK 0)
tRAS
(BANK 0)
<ACT 0><ACT 1>
<WRIT 0>
<WRITA 0><WRITA 1>
<WRIT 1><PRE 0><ACT 0>
tAHtAS
tCKS
tCKA
ROWROW
ROW
ROW
ROW
COLUMN COLUMN
AUTO PRE
AUTO PRE
ROW
tRCD
(BANK 1)
tRAS
(BANK 1)
tRC
(BANK 1)
tRC
(BANK 0)
tRCD
(BANK 0)
tRP
(BANK 0) tRAS
(BANK 0)
tRC
(BANK 0)
tRRD
(BANK 0 TO 1) tDPL tDPL
tDH tDH tDS tDH tDH
DIN 0m
tDS tDS tDH tDS tDH tDH tDH
tDS tDS
DIN 0m+1 DIN 0m+2 DIN 0m+3 DIN 1m DIN 1m+1 DIN 1m+2 DIN 1m+3
(1) (1)
Don't Care
Undefined
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 49
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle / Page Mode
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCH
tCS
tCH
tCS
tCHtCS
tCH
tCS
tAH
tAS
BANK 1
BANK 0 BANK 0 BANK 0
BANK 0
BANK 1
BANK 0 OR 1
BANK 0 AND 1
BANK 1
tCH
tAH
tAS
tLZ
tCS
tRAS
tRC
<ACT><READ>
<READA>
<READ><READ>
<PALL>
<PRE>
tAHtAS
tCKS
tCKA
ROW
COLUMN m COLUMN n COLUMN o
NO PRE NO PRE
NO PRE
AUTO PRE
ROW
tRCD tCAC tCAC tCAC tRQL
tHZ
tRP
tQMD
BANK 1
BANK 0
BANK 1
tAC tAC
tOH
tAC tAC tAC tAC
tOH tOH tOH tOH tOH
D
OUT
mD
OUT
m+1D
OUT
nD
OUT
n+1 D
OUT
oD
OUT
o+1
(1)
(1)
(1)
Don't Care
Undefined
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
50 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle / Page Mode; Data Masking
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK tCHI tCL
tCHtCS
tCH
tCS
tCHtCS
tCHtCS
tAH
tAS
BANK 1
BANK 0 BANK 0 BANK 0 BANK 0
BANK 1
BANK 0 OR 1
BANK 0 AND 1
NO PRE
BANK 1
tQMD
tAH
tAS
tLZ
tCS
tRAS
tRC
<ACT><READ>
<READA, ENB>
<READ, ENB><MASK>
<PALL>
<PRE>
tAHtAS
tCKS
tCKA
ROW
COLUMN m COLUMN n COLUMN o
NO PRE NO PRE
NO PRE
AUTO PRE
ROW
tCH
tRCD tCAC tCAC tCAC tRQL
tHZ
tHZ
tRP
tQMD
BANK 1
BANK 0
BANK 1
tAC
tLZ
tAC
tOH
tAC tAC tAC
tOH tOH tOH tOH
DOUT mDOUT m+1DOUT nDOUT oDOUT o+1
(1) (1) (1)
Don't Care
Undefined
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 51
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle / Page Mode
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0 BANK 0 BANK 0
BANK 0
BANK 1
BANK 0 OR 1
BANK 0 AND 1
BANK 1
t
CH
t
AH
t
AS
t
CS
t
RAS
t
RC
<
ACT
><
WRIT
>
<
WRITA
>
<
WRIT
><
WRIT
>
<
PALL
>
<
PRE
>
t
AH
t
AS
t
CKS
t
CKA
ROW
COLUMN m COLUMN n COLUMN o
NO PRE NO PRE
NO PRE
AUTO PRE
ROW
t
RCD
t
DPL
t
RP
BANK 1
BANK 0
BANK 1
t
DS
t
DS
t
DS
t
DS
t
DH
t
DS
t
DH
t
DH
t
DH
t
DS
t
DH
t
DH
D
IN
m D
IN n
D
IN
m+1 D
IN
n+1 D
IN
oD
IN
o+1
(1) (1) (1)
Don't Care
Undefined
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
52 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle / Page Mode; Data Masking
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0 BANK 0 BANK 0
BANK 0
BANK 1
BANK 1OR 0
BANK 0 AND 1
BANK 1
t
CH
t
AH
t
AS
t
CS
t
RAS
t
RC
<
ACT
><
WRIT
><
WRIT
>
<
WRITA
>
<
WRIT
><
MASK
>
<
PALL
>
<
PRE
>
t
AH
t
AS
t
CKS
t
CKA
ROW
COLUMN m COLUMN n COLUMN o
NO PRE NO PRE
NO PRE
AUTO PRE
ROW
t
RCD
t
DPL
t
RP
BANK 1
BANK 0
BANK 1
t
DS
t
DS
t
DS
t
DH
t
DS
t
DH
t
DH
t
DH
t
DS
t
DH
D
IN
m D
IN n
D
IN
m+1 D
IN
oD
IN
o+1
(1)
(1)
(1)
Don't Care
Undefined
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 53
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle / Clock Suspend
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCHtCS
tCHtCS
tCHtCS
tCHtCS
tAH
tAS
NO PRE
AUTO PRE
tAH
tAS
tCS
tCKH
tAHtAS
tCKS
tCKA
tCKS
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0 BANK 0
BANK 1
BANK 0
BANK 0 AND 1
BANK 0 OR 1
ROWROW
ROW
COLUMN m
ROW
tQMD
tLZ
tRAS
tRC tRC
<ACT 0> <ACT ><READ>
<READ A>
<SPND><SPND><PRE>
<PALL>
tRCD tCAC
tAC tAC
tOH tOH
tCH
DOUT mDOUT m+1
tHZ
tRP tRAS
(1)
Don't Care
Undefined
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
54 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle / Clock Suspend
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
NO PRE
AUTO PRE
t
AH
t
AS
t
CS
t
CKH
t
AH
t
AS
t
CKS
t
CKA
t
CKS
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0 BANK 0
BANK 1
BANK 0
BANK 0 AND 1
BANK 0 OR 1
ROWROW
ROW
COLUMN m
ROW
t
DS
t
RAS
t
RC
t
RC
<
ACT
> <
ACT
><
WRIT, SPND
>
<
WRITA, SPND
>
<
SPND
><
PRE
>
<
PALL
>
t
RCD
t
CH
t
DH
t
DH
t
DS
t
DPL
t
RP
t
RAS
DIN mDIN m+1
(1)
Don't Care
Undefined
CAS latency = 2, burst length = 2
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 55
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle / Precharge Termination
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCHtCS
tCHtCS
tCH
tCS
tCHtCS
tAH
tAS
NO PRE
AUTO PRE
NO PRE
tAH
tAS
tCS
tAHtAS
tCKS
tCKA
BANK 0 BANK 0
BANK 1
BANK 0 BANK 0
BANK 0
BANK 0 OR 1
ROWROW
ROW
COLUMN m COLUMN n
ROW
tQMD
tLZ
tRAS
tRC tRC
<ACT 0> <ACT ><READ 0><PRE 0><READ>
<READA>
tRCD tCAC tRQL
tRP
tRCD
tAC tAC
tOH
tAC tHZ
tOH tOH
tCH
DOUT mD
OUT m+2
tRAS
tCAC
BANK 1
DOUT m+1
(1) (1)
Don't Care
Undefined
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
56 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle / Precharge Termination
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCHtCS
tCHtCS
tCHtCS
tCHtCS
tAH
tAS
NO PRE
AUTO PRE
NO PRE
tAH
tAS
tAHtAS
tCKS
tCKA
BANK 0 BANK 0
BANK 1
BANK 0 BANK 0
BANK 0
BANK 0 OR 1
ROWROW
ROW
COLUMN m COLUMN n
ROW
tRAS
tRC tRC
<ACT 0> <ACT ><WRIT 0><PRE 0><WRIT>
<WRITA>
tRCD
tRP
tRCD
tRAS
BANK 1
D
IN
0m D
IN
0n
D
IN
0m+1 D
IN
0m+2
tDStDStDStDS
tDHtDHtDHtDH
tCS
tCH
tCS tCS
tCH
(1) (1)
Don't Care
Undefined
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 57
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle / Byte Operation
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
LDQM
UDQM
DQ8-15
DQ0-7
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1 BANK 1
BANK 0 AND 1
BANK 0 OR 1
NO PRE
AUTO PRE
t
CH
t
AH
t
AS
t
CS
t
CS
t
CH
t
AH
t
AS
t
CKS
t
CKA
BANK 0
BANK 0
BANK 1
BANK 1
BANK 0 BANK 0
ROW
COLUMN m
ROW
t
QMD
t
QMD
t
RAS
t
RC
<
ACT
> <
ACT
><
READ
>
<
READA
>
<
MASKU
><
MASKL
><
ENBU, MASKL
><
PALL
>
<
PRE
>
t
RCD
t
CAC
t
QMD
t
RQL
t
RCD
t
RAS
t
RC
t
RP
t
AC
t
HZ
t
OH
t
AC
t
AC
t
LZ
t
LZ
t
LZ
D
OUT
m
D
OUT
m
D
OUT
m+2
D
OUT
m+1
D
OUT
m+3
t
OH
t
OH
t
OH
t
AC
t
AC
t
OH
ROW
ROW
(1)
Don't Care
Undefined
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
58 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle / Byte Operation
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
LDQM
UDQM
DQ8-15
DQ0-7
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1 BANK 1
BANK 0 AND 1
BANK 0 OR 1
NO PRE
AUTO PRE
t
CH
t
AH
t
AS
t
CS
t
CS
t
CH
t
AH
t
AS
t
CKS
t
CKA
BANK 0
BANK 0
BANK 1
BANK 1
BANK 0 BANK 0
ROW
COLUMN m
ROW
t
RAS
t
RC
<
ACT
> <
ACT
><
WRIT
>
<
WRITA
>
<
MASK
>
<
MASKL
><
ENB
><
PALL
>
<
PRE
>
t
RCD
t
DPL
t
RCD
t
RAS
t
RC
t
RP
ROW
ROW
t
DH
t
DS
t
DS
t
DH
t
DS
t
DH
t
DS
D
IN
m
D
IN
m D
IN
m+3
t
DH
t
DH
t
DS
D
IN
m+1 D
IN
m+3
(1)
Don't Care
Undefined
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 59
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle, Write Cycle / Burst Read, Single Write
COLUMN n
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0 AND 1
BANK 0 OR 1
NO PRE
NO PRE
AUTO PRE
t
CH
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0BANK 0
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
ROW
COLUMN m
ROW
t
QMD
t
HZ
t
LZ
t
RAS
t
RC
<
ACT
><
READ
><
WRITA
>
<
WRIT
>
<
PALL
>
<
PRE
>
t
RCD
t
CAC
t
DPL
t
RP
t
AC
t
AC
t
OH
t
AC
t
AC
t
OH
t
DH
t
DS
t
OH
D
OUT
mD
OUT
m+1 D
OUT
m+2
t
OH
D
OUT
m+3 D
IN
n
(1) (1)
Don't Care
Undefined
CAS latency = 2, burst length = 4
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
60 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0 AND 1
BANK 0 OR 1
NO PRE
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0BANK 0
BANK 1 BANK 1
BANK 0
BANK 1
BANK 0
ROWROW
ROW
COLUMN m
ROW
t
QMD
t
LZ
t
RAS
t
RC
<
ACT
><
READ
><
ACT
>
<
PRE
>
<
PALL
>
t
RCD
t
CAC
t
RQL
t
RP
t
RCD
t
AC
t
AC
t
OH
t
AC
t
AC
t
OH
t
CH
t
OH
DOUT mDOUT m+1 DOUT m+2
t
OH
t
HZ
DOUT m+3
t
RC
t
RAS
(1)
Don't Care
Undefined
CAS latency = 3, burst length = 4
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 61
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle / Auto-Precharge
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
AUTO PRE
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0BANK 0
BANK 1 BANK 1
BANK 0
ROW
ROW
ROW
COLUMN
ROW
t
QMD
t
LZ
t
RAS
t
RC
<
ACT
><
READA
><
ACT
>
t
RCD
t
CAC
t
PQL
t
RP
t
RCD
t
AC
t
AC
t
OH
t
AC
t
AC
t
OH
t
CH
t
OH
D
OUT
mD
OUT
m+1 D
OUT
m+2
t
OH
t
HZ
D
OUT
m+3
t
RC
t
RAS
(1)
CAS latency = 3, burst length = 4
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
62 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle / Full Page
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T262 T263 T264 T265
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
NO PRE
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0
BANK 0
BANK 0 OR 1
BANK 0
ROW
COLUMN
ROW
t
LZ
t
RAS
(BANK 0)
t
RC
(BANK 0)
<
ACT 0
><
READ0
><
BST
><
PRE 0
>
t
RCD
(BANK 0)
t
CAC
(BANK 0)
t
RBD
t
AC
t
AC
t
OH
t
AC
t
AC
t
AC
t
OH
t
CH
t
OH
D
OUT
0m D
OUT
0m+1 D
OUT
0m-1
t
OH
t
HZ
t
OH
D
OUT
0m D
OUT
0m+1
t
RP
(BANK 0)
(1)
CAS latency = 3, burst length = full page
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 63
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle / Ping Pong Operation (Bank Switching)
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 0 BANK 1 BANK 0 BANK1 BANK 0
BANK 1
BANK 0
BANK 0 OR 1 BANK 0 OR 1NO PRE
NO PRE
t
CH
t
AH
t
AS
t
QMD
t
CS
t
AC
t
AC
t
AC
t
AC
t
RCD
(BANK 0)
t
RAS
(BANK 0)
<
ACT 0
>
<
ACT 0
><
ACT1
><
READ 0
>
<
READA 0
><
READA 1
>
<
READ 1
><
PRE 0
><
PRE 1
>
t
AH
t
AS
t
CKS
t
CKA
ROWROW
ROWROW
ROW
COLUMN COLUMN
AUTO PRE AUTO PRE
ROW
t
LZ
t
RAS
(BANK 1)
t
RC
(BANK 1)
t
RCD
(BANK 1)
t
CAC
(BANK 1)
t
CAC
(BANK 0)
t
RC
(BANK 0)
t
RQL
(BANK 0)
t
RP
(BANK 0)
t
RCD
(BANK 0)
t
RAS
(BANK 0)
t
RP
(BANK1)
t
RC
(BANK 0)
t
RRD
(BANK 0 TO 1)
t
OH
t
OH
t
OH
t
OH
t
HZ
DOUT 0m DOUT 0m+1 DOUT 1m DOUT 1m+1
(1) (1)
CAS latency = 3, burst length = 2
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
64 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10 T11
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0
BANK 0 OR 1
BANK 0 AND 1
NO PRE
t
CH
t
AH
t
AS
t
CS
t
DS
t
DS
t
DS
t
DS
t
DH
t
RAS
t
RC
<
PRE
>
<
PALL
>
<
ACT
><
ACT
><
WRIT
>
t
AH
t
AS
t
CKS
t
CKA
ROWROW
ROW
COLUMN
ROW
t
RCD
t
DH
t
DH
t
DH
t
RP
t
DPL
t
RCD
t
RAS
t
RC
D
IN
m D
IN
m+2
D
IN
m+1 D
IN
m+3
BANK 1
BANK 0
BANK 1
BANK 0
BANK 1
BANK 0
T12
(1)
CAS latency = 3, burst length = 4
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 65
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle / Auto-Precharge
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T7 T6 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0
AUTO PRE
t
CH
t
AH
t
AS
t
CS
t
DS
t
DS
t
DS
t
DS
t
DH
t
RAS
t
RC
<
ACT
><
ACT
><
WRITA
>
t
AH
t
AS
t
CKS
t
CKA
ROWROW
ROW
COLUMN
ROW
t
RCD
t
DH
t
DH
t
DH
t
RP
t
DAL
t
RCD
t
RAS
t
RC
DIN m DIN m+2
DIN m+1 DIN m+3
BANK 1
BANK 0
BANK 1
BANK 0
T11 T12
(1)
CAS latency = 3, burst length = 4
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
66 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle / Full Page
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T259T6 T260 T261 T262 T263 T264
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
NO PRE
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0
BANK 0
BANK 0 OR 1
BANK 0
ROW
COLUMN
ROW
t
RAS
t
RC
<
ACT 0
><
WRIT0
><
BST
><
PRE 0
>
t
RCD
t
CH
t
DPL
t
RP
t
DS
t
DS
t
DS
t
DS
t
DH
t
DH
t
DH
t
DH
D
IN
0m D
IN
0m+2
D
IN
0m+1 D
IN
0m-1 D
IN
0m
(1)
CAS latency = 3, burst length = full page
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 67
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle / Ping-Pong Operation (Bank Switching)
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCHtCS
tCH
tCS
tCHtCS
tCHtCS
tAH
tAS
BANK 0 BANK 0 BANK 0
BANK 1
BANK 1
BANK 0 OR 1
NO PRE
NO PRE
tCH
tAH
tAS
tCS
tDS tDS
tRCD
(BANK 0)
tRAS
(BANK 0)
<ACT 0><ACT 1>
<WRIT 0>
<WRITA 0><WRITA 1>
<WRIT 1><PRE 0><ACT 0>
tAHtAS
tCKS
tCKA
ROWROW
ROW
ROW
ROW
COLUMN COLUMN
AUTO PRE
AUTO PRE
ROW
tRCD
(BANK 1)
tRAS
(BANK 1)
tRC
(BANK 1)
tRC
(BANK 0)
tRCD
tRP
(BANK 0) tRAS
tRC
tRRD
(BANK 0 TO 1) tDPL
(BANK 0) tDPL
tDH tDH tDS tDH tDH
D
IN
0m
tDS tDS tDH tDS tDH tDH tDH
tDS tDS
D
IN
0m+1 D
IN
0m+2 D
IN
0m+3 D
IN
1m D
IN
1m+1 D
IN
1m+2 D
IN
1m+3
T11 T12
BANK 0
BANK 1
(1) (1)
CAS latency = 3, burst length = 4
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
68 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle / Page Mode
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0 BANK 0 BANK 0
BANK 0
BANK 1
BANK 0 OR 1
BANK 0 AND 1
BANK 1
t
CH
t
AH
t
AS
t
LZ
t
CS
t
RAS
t
RC
<
ACT
><
READ
>
<
READA
>
<
READ
><
READ
>
<
PALL
>
<
PRE
>
t
AH
t
AS
t
CKS
t
CKA
ROW
COLUMN m COLUMN n COLUMN o
NO PRE NO PRE
NO PRE
AUTO PRE
ROW
t
RCD
t
CAC
t
CAC
t
CAC
t
RQL
t
HZ
t
RP
t
QMD
BANK 1
BANK 0
BANK 1
t
AC
t
AC
t
OH
t
AC
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
DOUT mDOUT m+1DOUT nDOUT n+1 DOUT oDOUT o+1
T11 T12
(1) (1)(1)
CAS latency = 3, burst length = 2
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 69
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Read Cycle / Page Mode; Data Masking
CAS latency = 3, burst length = 2
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0 BANK 0 BANK 0 BANK 0
BANK 1
BANK 0 OR 1
BANK 0 AND 1
BANK 1
t
QMD
t
AH
t
AS
t
LZ
t
CS
t
RAS
t
RC
<
ACT
><
READ
><
READ
><
ENB
>
<
READA, MASK
>
<
READ, MASK
>
<
PALL
>
<
PRE
>
t
AH
t
AS
t
CKS
t
CKA
ROW
COLUMN m COLUMN n COLUMN o
NO PRE NO PRE
NO PRE
AUTO PRE
ROW
t
CH
t
RCD
t
CAC
t
CAC
t
CAC
t
RQL
t
HZ
t
RP
t
QMD
BANK 1
BANK 0
BANK 1
t
AC
t
AC
t
OH
t
AC
t
AC
t
AC
t
OH
t
OH
t
OH
t
OH
D
OUT
mD
OUT
m+1D
OUT
nD
OUT
oD
OUT
o+1
T11 T12
(1) (1) (1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
70 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Write Cycle / Page Mode
CAS latency = 3, burst length = 2
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCHtCS
tCH
tCS
tCHtCS
tCHtCS
tAH
tAS
BANK 0
BANK 0 BANK 0
BANK 0
BANK 1
BANK 0 OR 1
BANK 0 AND 1
BANK 1
tCH
tAH
tAS
tCS
tRAS
tRC
<ACT><WRIT>
<WRITA>
<WRIT><WRIT><MASK>
<PALL>
<PRE>
tAHtAS
tCKS
tCKA
ROW
COLUMN m COLUMN n COLUMN o
NO PRE NO PRE
NO PRE
AUTO PRE
ROW
tRCD tDPL
tRP
BANK 1
BANK 0
BANK 1
tDS tDS tDS
tDH tDS
tDH tDH tDH tDS tDH
DIN m DIN n
DIN m+1 DIN oDIN o+1
T11 T12
(1) (1) (1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 71
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle / Page Mode; Data Masking
CAS latency = 3, burst length = 2
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
tCK tCHI tCL
tCHtCS
tCHtCS
tCHtCS
tCHtCS
tAH
tAS
BANK 1
BANK 0 BANK 0 BANK 0
BANK 0
BANK 1
BANK 1OR 0
BANK 0 AND 1
BANK 1
tCH
tAH
tAS
tCS
tRAS
tRC
<ACT><WRIT><WRIT>
<WRITA>
<WRIT><MASK>
<PALL>
<PRE>
tAHtAS
tCKS
tCKA
ROW
COLUMN m COLUMN n COLUMN o
NO PRE NO PRE
NO PRE
AUTO PRE
ROW
tRCD tDPL
tRP
BANK 1
BANK 0
BANK 1
tDS tDS tDStDH tDS
tDH tDH tDH tDS tDH
D
IN
m D
IN n
D
IN
m+1 D
IN
oD
IN
o+1
(1) (1) (1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
72 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle / Clock Suspend
CAS latency = 3, burst length = 2
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
tCK tCHI tCL
tCHtCS
tCHtCS
tCHtCS
tCHtCS
tAH
tAS
NO PRE
AUTO PRE
tAH
tAS
tCS
tCKH
tAHtAS
tCKS
tCKA
tCKS
BANK 1
BANK 0 BANK 0
BANK 1
BANK 0
BANK 0 AND 1
BANK 0 OR 1
ROW
COLUMN m
ROW
tQMD
tLZ
tRAS
tRC
<ACT><READ>
<READ A>
<SPND><SPND><PRE>
<PALL>
tRCD tCAC
tAC tAC
tOH tOH
tCH
D
OUT
mD
OUT
m+1
tHZ
tRP
T12
BANK 1
(1)
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 73
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle / Clock Suspend
CAS latency = 3, burst length = 2
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
NO PRE
AUTO PRE
t
AH
t
AS
t
CS
t
CKH
t
AH
t
AS
t
CKS
t
CKA
t
CKS
BANK 1
BANK 0
BANK 1
BANK 1
BANK 0 BANK 0
BANK 1
BANK 0
BANK 0 AND 1
BANK 0 OR 1
ROWROW
ROW
COLUMN m
ROW
t
DS
t
RAS
t
RC
t
RC
<
ACT
> <
ACT
><
WRIT, SPND
>
<
WRITA, SPND
>
<
SPND
><
PRE
>
<
PALL
>
t
RCD
t
CH
t
DH
t
DH
t
DS
t
DPL
t
RP
t
RAS
D
IN
mD
IN
m+1
T11 T12
(1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
74 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle / Precharge Termination
CAS latency = 3, burst length = 2
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
NO PRE
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0
BANK 0
BANK 0
ROWROW
ROW
COLUMN m
ROW
t
QMD
t
LZ
t
RAS
t
RC
t
RP
<
ACT 0
> <
ACT
><
READ 0
><
PRE 0
>
t
RCD
t
CAC
t
RQL
t
RP
t
RCD
t
AC
t
AC
t
OH
t
AC
t
HZ
t
OH
t
OH
t
CH
D
OUT
mD
OUT
m+2
t
RAS
BANK 1
D
OUT
m+1
T11 T12
BANK 0
BANK 0 OR 1
(1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 75
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle / Precharge Termination
CAS latency = 3, burst length = 4
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
NO PRE
t
AH
t
AS
t
AH
t
AS
t
CKS
t
CKA
BANK 0
BANK 0
BANK 0
ROWROW
ROW
COLUMN m
ROW
t
RC
t
RP
<
ACT 0
><
ACT
>
<
WRIT 0
><
PRE 0
>
t
RCD
t
RP
t
RCD
t
RAS
BANK 1
D
IN
0m D
IN
0m+1 D
IN
0m+2
t
DS
t
DS
t
DS
t
DH
t
DH
t
DH
T11 T12
t
CH
t
CH
t
CS
t
CS
BANK 0
BANK 0 OR 1
t
RAS
(1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
76 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle / Byte Operation
CAS latency = 3, burst length = 4
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
LDQM
UDQM
DQ8-15
DQ0-7
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
tCK tCHI tCL
tCHtCS
tCHtCS
tCHtCS
tCHtCS
tAH
tAS
BANK 1 BANK 1
BANK 0 AND 1
BANK 0 OR 1
NO PRE
AUTO PRE
tCH
tAH
tAS
tCS
tCS tCH
tAHtAS
tCKS
tCKA
BANK 0
BANK 0
BANK 1
BANK 1
BANK 0 BANK 0
ROW
COLUMN m
ROW
tQMD
tQMD
tRAS
tRC
<ACT> <ACT><READ>
<READA>
<MASKU><MASKL><ENBU, MASKL><PALL>
<PRE>
tRCD tCAC tQMD tRQL tRCD
tRAS
tRP
tRP
tAC tHZ
tOH
tHZ
tHZ
tAC tAC
tLZ
tLZ
tLZ
DOUT m
DOUT m
DOUT m+2
DOUT m+1
DOUT m+3
tOH
tOH
tACtAC
tOH
ROW
ROW
T12
(1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 77
Rev. C
01/22/08
IS42S16100E, IC42S16100E
Write Cycle / Byte Operation
CAS latency = 3, burst length = 4
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
LDQM
UDQM
DQ8-15
DQ0-7
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
tCK tCHI tCL
tCHtCS
tCH
tCS
tCHtCS
tCHtCS
tAH
tAS
BANK 1 BANK 1
BANK 0 AND 1
BANK 0 OR 1
NO PRE
AUTO PRE
tCH
tAH
tAS
tCS
tCS tCH
tAHtAS
tCKS
tCKA
BANK 0
BANK 0
BANK 1
BANK 1
BANK 0 BANK 0
ROW
COLUMN m
ROW
tRAS
tRC
<ACT> <ACT><WRIT>
<WRITA>
<MASK>
<MASKL><ENB><PALL>
<PRE>
tRCD tDPL tRCD
tRAS
tRP
tRP
ROW
ROW
tDH
tDS tDS
tDH
tDS
tDH
tDS
D
IN
m
D
IN
m D
IN
m+3
tDH
tDH
tDS
D
IN
m+1 D
IN
m+3
T12T11
(1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
IS42S16100E, IC42S16100E
78 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
Read Cycle, Write Cycle / Burst Read, Single Write
CAS latency = 3, burst length = 2
COLUMN n
CLK
CKE
CS
RAS
CAS
WE
A0-A9
A10
A11
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
t
CK
t
CHI
t
CL
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
CH
t
CS
t
AH
t
AS
BANK 1
BANK 0 AND 1
BANK 0 OR 1
NO PRE
NO PRE
AUTO PRE
t
CH
t
AH
t
AS
t
CS
t
AH
t
AS
t
CKS
t
CKA
BANK 0BANK 0
BANK 1
BANK 1
BANK 0
BANK 1
BANK 0
ROW
COLUMN m
ROW
t
QMD
t
HZ
t
LZ
t
RAS
t
RC
<
ACT
><
READ
><
WRITA
>
<
WRIT
>
<
PALL
>
<
PRE
>
t
RC
t
CAC
t
DPL
t
RP
t
AC
t
AC
t
DH
t
DS
t
OH
D
OUT
m
t
OH
D
OUT
m+1 D
IN
n
T11 T12
(1) (1)
Don't Care
Undefined
Note 1: A8,A9 = Don’t Care.
Integrated Silicon Solution, Inc. — www.issi.com 79
Rev. C
01/22/08
IS42S16100E, IC42S16100E
ORDERING INFORMATION
Commercial Range: 0°C to 70°C
Frequency Speed (ns) Order Part No. Package
200 MHz 5 IS42S16100E-5T 400-mil TSOP II
IS42S16100E-5TL 400-mil TSOP II, Lead-free
IS42S16100E-5B 60-ball BGA
IS42S16100E-5BL 60-ball BGA, Lead-free
166 MHz 6 IS42S16100E-6T 400-mil TSOP II
IS42S16100E-6TL 400-mil TSOP II, Lead-free
IC42S16100E-6TL 400-mil TSOP II, Lead-free
IS42S16100E-6B 60-ball BGA
IS42S16100E-6BL 60-ball BGA, Lead-free
143MHz 7 IS42S16100E-7T 400-mil TSOP II
IS42S16100E-7TL 400-mil TSOP II, Lead-free
IC42S16100E-7TL 400-mil TSOP II, Lead-free
IS42S16100E-7B 60-ball BGA
IS42S16100E-7BL 60-ball BGA, Lead-free
Industrial Range: -40°C to +85°C
Frequency Speed (ns) Order Part No. Package
166 MHz 6 IS42S16100E-6TLI 400-mil TSOP II, Lead-free
IS42S16100E-6BI 60-ball BGA
IS42S16100E-6BLI 60-ball BGA, Lead-free
143MHz 7 IS42S16100E-7TLI 400-mil TSOP II, Lead-free
IS42S16100E-7BI 60-ball BGA
IS42S16100E-7BLI 60-ball BGA, Lea-free
Please contact the Product Manager for leaded parts support.
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. F
06/18/03
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
PACKAGING INFORMATION
Plastic TSOP
Package Code: T (Type II)
D
SEATING PLANE
b
eC
1N/2
N/2+1N
E1
A1
A
E
Lα
ZD
.
Notes:
1. Controlling dimension: millimieters,
unless otherwise specified.
2. BSC = Basic lead spacing
between centers.
3. Dimensions D and E1 do not
include mold flash protrusions and
should be measured from the
bottom of the package.
4. Formed leads shall be planar with
respect to one another within
0.004 inches at the seating plane.
Plastic TSOP (T - Type II)
Millimeters Inches Millimeters Inches Millimeters Inches
Symbol Min Max Min Max Min Max Min Max Min Max Min Max
Ref. Std.
No. Leads (N) 32 44 50
A — 1.20 — 0.047 — 1.20 — 0.047 — 1.20 — 0.047
A1 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006 0.05 0.15 0.002 0.006
b 0.30 0.52 0.012 0.020 0.30 0.45 0.012 0.018 0.30 0.45 0.012 0.018
C 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008 0.12 0.21 0.005 0.008
D 20.82 21.08 0.820 0.830 18.31 18.52 0.721 0.729 20.82 21.08 0.820 0.830
E1 10.03 10.29 0.391 0.400 10.03 10.29 0.395 0.405 10.03 10.29 0.395 0.405
E 11.56 11.96 0.451 0.466 11.56 11.96 0.455 0.471 11.56 11.96 0.455 0.471
e 1.27 BSC 0.050 BSC 0.80 BSC 0.032 BSC 0.80 BSC 0.031 BSC
L 0.40 0.60 0.016 0.024 0.41 0.60 0.016 0.024 0.40 0.60 0.016 0.024
ZD 0.95 REF 0.037 REF 0.81 REF 0.032 REF 0.88 REF 0.035 REF
α0° 5° 0° 5° 0° 5° 0° 5° 0° 5° 0° 5°
PACKAGING INFORMATION
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. D
02/16/06
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Mini Ball Grid Array
Package Code: B (60-Ball)
mBGA - 10.1mm x 6.4mm
MILLIMETERS INCHES
Sym. Min. Typ. Max. Min. Typ. Max.
No.
Leads 60
A — — 1.20 — — 0.047
A1 0.23 0.28 0.33 0.009 0.011 0.013
D 10.00 10.10 10.20 0.394 0.398 0.402
D1 — 9.10 — — 0.358 —
E 6.30 6.40 6.50 0.248 0.252 0.256
E1 — 3.90 — — 0.154 —
e — 0.65 — — 0.026 —
7 6 5 4 3 2 1
1 2 3 4 5 6 7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
ø 0.40 + +/-0.05 (60X)
D
e
e
A1
SEATING PLANE
A
D1
E1
E
Notes:
1. Controlling dimensions are in millimeters.
2. 0.65 mm Ball Pitch