TOSHIBA TMP47C440B CMOS 4-BIT MICROCONTROLLER TMP47C440BN TMP47C440BF The 47C440B is high speed and high performance 4-bit single chip micro computers, integrating the 8-bit A/D converter and watchdog timer based on the TLCS-47 series. PART No. ROM RAM PACKAGE OTP version TMP47C440BN SDIP42-P-600-1.78 | TIMP47PA40VN ao nn-= 22 -=---- 4 4096 x 8-bit 256x4-bit -----------------4---------2--- TMP47C440BF QFP44-P-1414-0.80D | TIVIP47P440VE FEATURES @4-bit single chip microcomputer @ Instruction execution time : 1.9 s (at 4.2 MHz) #90 basic instructions @ Table look-up instructions e 5-bit to 8-bit data conversion instruction Subroutine nesting : 15 levels max. 6 interrupt sources (External : 2, Internal : 4) SDIP42-P-600-1.78 All sources have independent latches each, and multiple MPa OAAOEN interrupt control is available 1/0 port (34 pins) QFP44-P-1414-0.80D e Input 2 ports 5 pins Output 2ports 8 pins e I/0 6 ports 21 pins @ Interval timer @Two 12-bit Timer/Counters Timer, event counter, and pulse width measurement mode @Watchdog Timer @Serial Interface with 4-bit buffer External/internal clock, leading/trailing edge shift mode @8-bit successive approximate type A/D converter e With sample and hold @ 8analog inputs Convertingtime : 48 us (4MHz) @High current outputs LED direct drive capability (typ. 20 mA x8 bits) @ Hold function Battery/Capacitor back-up Real Time Emulator : BM47214A TMP47C440BF TMP47P440BF 5-40-1TOSHIBA TMP47C440B PIN ASSIGNMENTS (TOP VIEW) (1) SDIP42-P-600-1.78 (2) QFP44-P-1414-0.80D VAREE [1 42 [}< vop re f vass {] 2 a1 [<> R92 (SCK) FREE, ee A Ju be R40 (AING) ~>[] 3 40 [<> R91 (sO) noo E mI ZAMN ono loOWwWwo-woodo R41(AIN1) ~<[] 4 39 [<> R90(51) meme |r lex XE wu M uv R42 (AIN2) ~<>[] 5 38 [<> R83(T1) { { { | | t | | | | | R43 (AIN3) ~>[] 6 37 [<> R82 (INT?) R50(AIN4) <>] 7 36 [<> R81 (72) R51 (AINS) <>] 8 35 [<> R80 (INT2) 30 29 28 27 26 25 24 23 R52(AING) ~<>[] 9 34 [< HOLD <KE0) R53 (AIN7) ~<>T[] 10 33 [< RESET R83 (T1) * KOO R90 (SI) <> > P23 reo ~<>{] 11 32. [| xout R91 (50) <> pr R61 ~<>[] 12 31 [~ xin R92 (SCK) <> p21 Rez <>] 13 30 [< TEST NC. P20 VDD > NC. R63 <>] 14 29 [I< ko3 VARER > < 55 R70. <> [] 15 28 [l< ko2 VASS > P13 R71(WTO) ~<>T[] 16 27 [I< ko1 R40 (AINO) <> ~ P12 R41 (AIN1) <> Pt pio <[] 17 26 [I< oo RA2 (AIN2) <> > p10 p11 < [18 25 []> p23 Piz ~[] 19 24 []|> p22 P13 ~ [| 20 23 I pai vss >[] 21 22 [] p20 PEAR E ELAS Seg esseesee 224222 - --- - - wrtnrnrnereme BLOCK DIAGRAM aaadad = Morn NS THN Hw a ererer wet wt Power Supply) vss Accumulator HR LR Data Memory PC RAM address buffer (RAM) Program Memory ROM Holdinput = HOLD STACK (ROM) (Sense input) (KEQ) Hold controller EIR EIF TC1 | TC2 | DC Data table . Interrupt controller Resetinput RESET: System controller Test pin TEST Timing Generator Interval Timer . o {xin 2-bit A-bit Serial 8-bit R SC. Cl kG t . =D erla - Connecting | XOUT Ok Generator Timer/Counter Interface A/D converter Decoder pin (2ch) Watchdog Timer R71 (NTO) R63 P23. P13 R83 (T1)_ R92 VAREF R43(AIN3) R53(AIN7) KO3 R70 to to to R82 (INT1) R91 (SO) VASS to to to VO port R60 \P20. PIG, R81(T2)_ R90 (SI) RAQ(AINO) - R50(AIN4) KOO Watchdog timer VO port igh R80 (INT2) , ___<_ output High current VO port vOport _ Analog VO port Input port output port TIC input, (Serial port) reference (Analog input) ( interrupt input voltage 5-40-2TOSHIBA TMP47C440B PIN FUNCTION PIN NAME Input/Output FUNCTIONS KO3 - KOO Input 4-bit input port P13 - P10 4-bit output port with latch. Output P23 - P20 8-bit data are output by the 5-bit to 8-bit data conversion instruction [OUTB @HL]. R43 (AIN : . 3 (AIN3) 4-bit I/O port with latch. R40 (AINO) . . R53 (AIN7) 1/0 (Input) When used as input port or analog input, A/D converter analog input - the latch must be set to "1". R50 (AIN4) R63 - R60 V0 4-bit I/O port with latch R71 (WTO) 1/0 (Output) 2-bit I/O port with latch. Watchdog timer output ee ee eee ee eee When used as input port or watchdog fa ee ee R70 VO timer output, the latch must be set to "1". R83 (T1) 4-bit I/O port with latch. Timer/Counter 1 external input R82 (INT 1) When used as input port, external External interrupt 1 input be ceetneeneteetecteeseeeetaas 1/0 (Input) interrupt input pin, or timer/eounter Lccecereeeeseeeeeeeececaseccuseeereateeteceeeesuseeenneeeeees R81 (T2) , Timer/Counter 2 external input wee eee eee eee ee eee external input pin, the latch must be setto fee eee ee eee eee tenet eee e eee eee eee ee teen ee eee R80 (INT2) aq External interrupt 2 input R92 (SCK) VO(VO) 3-bit /O port with latch. Serial clock /O RONG) dn. vO (Output) When used asinput port orserial port, the | Serialdata output R90 (SI) 1/0 (Input) latch must be set to "1". Serial data input XIN Input Resonator connecting pins. XOUT Output For inputting external clock, XIN is used and XOUT is opened. RESET Input Reset signal input HOLD (KEO) Input (Input) HOLD request/release signal input Sense input TEST Input Test pin for out-going test. Be opened or fixed to low level. VDD +5V VSS OV (GND) Power supply VAREF A/D converter analog reference voltage (High) VASS A/D converter analog reference voltage (Low) 5-40-3TOSHIBA TMP47C440B OPERATIONAL DESCRIPTION Conserning the 47C440B, the hardware configuration and operation of hardwares are described. As the description is porvided with priority on those parts deffering from the 47C400B, the technical data sheets for the 47C400B shall also be referred to. 1. SYSTEM CONFIGURATION @ INTERNAL CPU FUNCTION They are the same as those of the 47C440B. @ PERIPHERAL HARDWARE FUNCTION @ (W/O Port Interval Timer @ Timer/Counters (TC1, TC2) @ A/D Converter Wachdog Timer Serial Interface The description has been provided with priority on functions (, @ and @) added to and changed from the 47C400B. 2. PERIPHERAL HARDWARE FUNCTION 2.1 Ports The 47C440B has 10 I/O ports (34 pins) each as follows : @ KO ; 4-bit input P1, P2 ; 4-bit output @ R4,R5 ; 4-bit input/output (shared with the A/D converter analog inputs) @ R6 ; A-bit input/output R7 ; 2-bit input/output (shared with the watchdog timer output) R8 ; 4-bit input/output(shared with external interrupt request input and timer/counter input) @ RY i 3-bit input/output (shared with serial port) @ KE 1-bit sense input (shared with hold request/release signal input) This section describes ports of @ and which are changed from the 47C400B. Table 2-1 lists the port address assignments and the I/O instructions that can access the ports. (1) Ports R4 (R43-R40), R5 (R53-R50) Ports R4 and R5 are 4-bit I/O ports with latch shared by the analog inputs for A/D converter. When used as an input ports or analog inputs, the latch should be set to "1". If other port is used as an output, be careful not to execute the output instruction for any port during A/D conversion in order to keep accuracy of conversion. The latch is initialized to 1 and analog input is selected R40 (AINO) pin during reset. Port R4 {Port address oP04 / \P04) Analog input selector Analog input R43 R42 R41 R40 (AIN3) (AIN2) (AIN1) (AINO) IN/TEST/TESTP Input data Lt Port R5 (Portaddress OPO5/IPO5) SET/CLR, 3 2 0 < R53 R52 R51 R50 (AIN7) (AIN6) (AIN5) (AIN4) Output data >[LatcH > {_ ein Figure 2-1. Port R4 and R5 5-40-4TOSHIBA TMP47C440B (2) Port R7 (R71, R70) Port R7 is 2-bits I/O port with latch. R71 pin is shared by the watchdog timer output. To use R71 pin for the watchdog timer output, the latch should be set to 1. The latch is initialized to 1 during reset. R70 pin is normal I/O pin. R72 and R73 pins do not exist actually but 1 is read when an input instruction is executed. IN/ TEST / TESTP Port R7 (Portaddress OP0Q7/IPQ7) Input data ne Boone Breese: | Q R71 R70 Output data ee (W10) WTO output Figure 2-2. Port R7 5-40-5@d Pue {dq S}IOd O} ssa92e INeWOING TIH@ giNO] uoysnsysui uoissaauod ej ep 11G-g 0} G-G BYL 7 aION swsesBosd JaSn ay) JOJ a}qesieneup) a)e)S pansasas ay) SueawW , , "| a]0N = = = = = wT = JoljUO> Svepeyul [eles poulepury a - - - - - - - pauyapun ql - - - - - oO - JO4UOD Z J2UNOD/JOWUIL peuyapun dl - - - - - oO - JO4jUO> | Ja2UNOD/JOWUIL peuyapun 3 - - - - - = - peuyepun al - - - - - - - peuyspun| = VIL - - - - - oO - joujUO> JdnwjU! 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Bojeuy) y0d yndui sy SO oO Oo Oo - Oo Oo O yod jndino ry (andul Boyeuy) od indul py v0 - - - - - - - 0 7 O O (z aon O Oo O yod yndino 7q ype] indjno zq z0 - O O oO OQ oO O vod jnd3no Ld yoye| indino | LO - OQ - - - - O yod yndul o> Hoo TO1ISAL | q'dy% gisat| gd% wD ' TH 4% NI ndin ndu 1@ uD des dee IH aino |d% 4# Lno o%1H LO dos (#dO) indino (#xq|)1 | (x) 1 135 gOo% 1541] AO% LAS %V LNO Vi o% NI ssouppy pod Od uolpnaysul yndyngs/ndy| sUOIPNAYsU| O/| B|Ge]!eAy pue s}UaWUBIssy ssaippy HO L-@ 819eLTOSHIBA TMP47C440B 2.2 A/D Converter The 47C440B has a 8-bit successive approximate type A/D converter and is capable of processing 8 analog inputs. 2.2.1 Circuit configuration VAREF LJ Ladder Resistor Tap D VASS [| ap Decoder Reference Voltage aino [[-4 I ______>- Analog Compa: \ Sample rator . . oo, Input &Hold $= Successive Approximate Circuit Multiplexer 1 AIN7 [4 i: Control Circuit IPOD | A/D Converted value Register | 1 1 1 1 1 1 1 7 @ 5 4 3 2 1 #90 OP12 OP13 IPOC gt 1 ADS Eocr | \ L---4I---- 1 EEE OFT Jo---J----4 3 2 1 0 3 2 1 0 3 2 1 0 Figure 2-3. Block Diagram of A/D Converter 2.2.2. Control of A/D converter The operation of A/D converter is controlled by a command register (OP12, OP 13, IPOC, IPOD). (1) Analog input selector (OP12) Analog inputs (AINO through AIN7) are selected by values of this register. Analog input select command register (Port address OP12) (Initial value 0000) 3 2 1 0 | , SAIN SAIN | Analog input selection 0000: R40(AINO) 0001: R41(AIN1) 0010: R42(AIN2) 0011: R43(AIN3) 0100: R50(AINA4) 0101: R51(AIN5) 0110: R52(AIN6) 0111: R53(AIN7) | _1***: Analog input is not selected. Note.*; dontcare Figure 2-4. Analog input selector 5-40-7TOSHIBA TMP47C440B (2) Start of A/D conversion (OP13) A/D conversion is started when ADS is set to 1 . After the conversion is started, ADS is cleared by hardware. If the restart is requested during the conversion, the conversion is started again at the time. Analog input voltage is hold by the sample hold circuit. A/D conversion start command register (Port address OP13) (Initial value 0000) ADS | A/Dconversion enable | 1: A/D conversion is started (clears after starting) Figure 2-5. A/D conversion start register (3) A/D converter and frag (IPOC) End of Conversion Flag (EOCF) is a single bit flag showing the end of conversion and is set to 1 when conversion ended. When both upper 4 bits and lower 4 bits of a converted value are read or A/D conversion is started, EOCF is cleared to "0". A/D converter status register (Port address IPOC) EOCF | End of conversion flag 0: Under A/D conversion or before A/D conversion 1: End of A/D conversion Figure 2-6. A/D converter status register (4) A/D converted value register (IPOD) An A/D converted value is read by accessing port address IPOD. An A/D converted value is read by splitting into upper 4 bits and lower 4 bits by a value of LRo (LSB of the L registers). A/D converted value register (Port address IPOD) 3 2 1 0 [os | mo | o | oo | [0 | > | o | o | D7 to Do| A/D converted value register | When LRg = 0, lower 4 bits of the converted value is read. When LRo = 1, upper 4 bits of the converted value is read. Figure 2-7. A/D converted value register 5-40-8TOSHIBA TMP47C440B 2.2.3 How to use A/D converter Apply positive of analog reference voltage to the VAREF pin and negative to the VASS pin. The A/D conversion is carried out by splitting reference voltage between VAREF and VASS to bit corresponding voltage by a ladder resistor and making a judgement by comparing it with analog input voltage. (1) Startof A/D conversion (2) (3) Prior to conversion, select one of the analog input AINO through AIN7 by the analog input selector. Place output of the analog input, which is to be A/D converted, in the high impedance state by setting 1. If other port is used as an output, be careful not to execute the output instruction for any port during conversion in order to keep accuracy of conversion. A/D conversion is started by setting ADS (bit 1 of the A/D conversion start register). When conversion ends after 24 instruction cycles, EOCF showing the end of conversion is set to "1". Analog input voltage is sampled during the following 2 instruction cycles after setting conversion enable. Note. Thesample and hold circuit has capacitor (C4 = 12 pF typ.) with resister (RA =5 kO, typ.). See I/O circuitry table. This capacitor should be charged or discharged within 2 instruction cycles. Reading of an A/D converted value After the end of conversion, read an A/D converted value is read by splitting into lower 4 bits and upper 4 bits by the A/D converted value register (IPOD). Lower 4 bits of the A/D converted value can be read when LRg = O and upper 4 bits when LRo = 1. Usually an A/D converted value is stored in RAM by an instruction [IN %p, @HL]. Further, if an A/D converted value is read during the conversion, it becomes an indefinite value. A/D conversion with HOLD operation When the HOLD operation is started during the conversion, the conversion is terminated and an A/D converted value becomes indefinite. Therefore, EOCF is kept clear to 0 after release from the HOLD operation. However, if the HOLD operation is started after the end of A/D conversion (after EOCF has been set), A/D converted value and status of EOCF are held. Example: Selecting analog input (AIN3), starting A/D conversion, monitoring EOCF and storing lower 4 bits and upper 4 bits of a converted value to RAM [104] and RAM [114] respectively. LD A, #3H ; Selects analog input (AIN3) OUT A, %OP12 LD A, #1H ; Start of A/D conversion OUT A, %OP13 SLOOP : TEST %IPOC, 3 ; To wait until EOCF goes to "1" B SLOOP LD HL, #10H 3; HL<10y IN %IPOD, @HL ; RAM [10y] < Lower 4 bits INC L ; Increment of L registers IN %IPOD, @HL ; RAM [114] < Upper 4 bits 5-40-9TOSHIBA TMP47C440B 2.3 Watchdog Timer (WDT) The purpose of the watchdog timer is to detect the malfunction (ranaway) of program due to external noise or other causes and return the operation to the normal condition. The watchdog timer output is output to R71 must be set to "1". Further, during reset, the output latch of R71 isset to 1, and the watchdog timer becomes disable state. The initialization at time of runaway will become possible when the WTO pin and RESET pin are connected each other. 2.3.1. Configuration of Watchdog Timer The watchdog timer consists of 3-stage binary counter, flip-flop (F/F), and its control circuit. The F/F is set to 1 during reset, and cleared to 0 at the rising edge of the binary counter output. Binary Counter CPU reset 214/ fc i S l 1) 2) 3 E/F | External Circuit I 216/ fe S Q 38/4 Selector Clear Request R 1 s**t ! R71 (WTO) signal of 3221/4 Control Circuit Atectiog aK etection 1 . . 1 Timing Generater P07 | ! : R7 Output Latch | 3 2 1 0 RESET simplified power-on-reset Figure 2-8. Watchdog Timer 2.3.2. Control of watchdog timer The watchdog timer is controlled by the command register (OP15). This command register is initialized to 0000, during reset. The following are procedure to detect the malfunction (runaway) of CPU by the watchdog timer. @ At first, detection time of the watchdog timer should be set and binary counter should be cleared. @ The watchdog timer should be become enable. @ Binary counter must be cleared before the detection time of the watchdog timer. When the runaway of CPU is taken place for some reason and binary counter is not cleared, the F/F is cleared to OQ at the rising edge of the binary counter and signal of runaway detection is become active (WTO output is L ). 5-40-10TOSHIBA TMP47C440B Watchdog Timer control command register (Portaddress OP15) (Initial value 1000) 3 2 1 0 | RWT | EWT | TWT RWT | Clears binary counter 0: Clears binary counter (After clear, automatically "1" is set) EWT | Enable/Disable 0 : Disable 1: Enable TWT | Setting of watchdog timer detection time Example : At fc = 4.19 MHz 00: 217/fc [s] 31.25 [ms] SOD fe eee "0 ae cess Note. fc; Basic clock frequency [Hz] Wo: 224/fe 4000 Figure 2-9. Command Register Example: To set the watchdog detection time (221 / fc[s] }. And to enable the watchdog timer. LD A, #0010B ; OP15 < 0010, (Sets WDT detection time. Clears binary counter) OUT A, %OP15 LD A, #0110B ; OP15 0110, (Enables WDT) OUT A, %OP15 Within WDT detection time LD A, #0110B ; OP15 01103, (Clears binary counter) OUT A, %OP15 Note. RWT can be operated only by clearing to 0. Note that both EWT (Enable Watchdog Timer) and RWT should not be set to 1 at the same time. 5-40-11TOSHIBA TMP47C440B INPUT/OUTPUT CIRCUITRY (1) Control pins The input/output circuitries of the 47C440B control pins are similar to that of the 47C400B. (2) I/O Ports The input/output circuitries of the 47C440B I/O ports are shown below, any one of the circuitries can be chosen by a code (SA-SC) as a mask option. PORT VO INPUT/OUTPUT CIRCUITRY and CODE REMARKS SA SB SC Pull-up/ pull-down VDD : R resistor KO Input R Rin <Tw-L] Rin Rin = 70kQ (typ.) R R = 1kQ (typ.) Sink open drain VDD output Initial Hi-Z Pq Output P2 : _>o_ High current lo. = 20mA (typ.) Sink open drain RA vpp o*@ R. RY VDD P tout R4, R5 -f : outpu R5 Initial Hi-Z R6 q V0 AIN selector R= 1kQ (typ) R7 R _to_ Ca Ra R Analog input a Ra =5 kO (typ.) Ca = 12 pF (typ.) Sink open drain VDD output Initial Hi-Z ie VO >o_ RO R Hysteresis input 5-40-12TOSHIBA TMP47C440B ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (Vss5 = OV) PARAMETER SYMBOL PINS RATING UNIT Supply Voltage Vpp -0.3 to 6.5 Vv Input Voltage Vin -0.3 to Vpp + 0.3 Vv Output Voltage Vout - 0.3 to Vpp + 0.3 Vv louti Ports R 3.2 Output Current (Per 1 pin) mA lout2 Ports P1, P2 30 Output Current (Total) Slout | PortsP1, P2 120 mA Power Dissipation [Topr =70C] PD 600 mw Soldering Temperature (time) Tsld 260 (10s) C Storage Temperature Tstg -55to 125 C Operating Temperature Topr - 30 to 70 C RECOMMENDED OPERATING CONDITIONS (Vss = OV, Topr = 30 to 70C) PARAMETER SYMBOL PINS CONDITIONS Min. Max. UNIT fc = 6.0 MHz 4.5 Supply Voltage Vop fc=4.2 MHz 2.7 5.5 Vv In the HOLD mode 2.0 Vin1 | Except Hysteresis Input Vop x 0.7 VppZz4.5V Input High Voltage Vin2 | Hysteresis Input Vpp x 0.75 Vop Vv Vin3 Vop<4.5 V Vop x 0.9 Vint Except Hysteresis Input Vpp x 0.3 Vop24.5V Input Low Voltage Vit2 | Hysteresis Input 0 Vpp x 0.25 Vv ViL3 Vop<4.5 V Vpp x 0.1 Clock Frequency fc XIN, XOUT 0.4 6.0 MHz Note. Input voltage Viz3, V3: inthe HOLD mode 5-40-13TOSHIBA TMP47C440B D.C. CHARACTERISTICS (Vss = OV, Topr = 30 to 70 C) PARAMETER SYMBOL PINS CONDITIONS Min. | Typ. | Max. | UNIT Hysteresis Voltage Vus _ | Hysteresis Input - 0.7 - Vv Port KO, TEST, int | RESET, HOLD Vpp=5.5V, Input Current Vin = 5.5V/0V - _ +2 uA line Ports R (open drain) Low Input Current li Ports R (push-pull) Vpp = 5.5V, Vin = 0.4V - - -2 mA Ring Port KO with pull-up/pull-down 30 70 150 Input Resistance kQ Ring RESET 100 220 450 Output Leakage Current lLo Parts R (open drain) Vpp = 5-5V, Vout =5.5V _ _ 2 pA Output Low Valtage Voi2 | Except XOUT, ports P Vpp =4.5V, lol =1.6MA | - 0.4 Vv Low output Current lot: | Ports P1, P2 Vpp = 4.5V, VoL = 1.0V _ 20 _ mA Supply Current lop Vpp=5.5V, f=4MHz | 3 6 | mA (in the Normal mode) Supply Current (in the HOLD mode) | 'D2H Vpp = 5.5V | o5 | 10 | ya Note 1. Typ. values show those at Topr =25 C, Vop = 5V. Note 2. Input Current liy7 ; The current through resistor is not included, when the input resistor (pull- up/pull-down) is contained. Note 3. Supply Current!lpp, Ippy ; = Vin =5-3V/0.2V The KO port is open when the input resistor is contained. The voltage applied to the R port is within the valid range. A/D CONVERSION CHARACTERISTICS (Topr = -30 to 70 C) PARAMETER SYMBOL CONDITIONS Min. Typ. | Max. | UNIT Varer Vpp- 1.5 Vop Analog Reference Voltage Vv Vass Vss - 1.5 Analog Reference Voltage Range AVarer |Varer Vass 2.5 - - V Analog Input Voltage VAIN Vass - Varer} V Analog Supply Current IREF _ 0.5 1.0 mA Nonlinearity Error _ _ +1 Vop = 5.0V, Vss = 0.0V Zero Point Error _ _ +1 Varer = 5.000V LSB Full Scale Error _ _ +1 Vass =0.000V Total Error _ _ +2 5-40-14TOSHIBA TMP47C440B A.C. CHARACTERISTICS (Vss = OV, Vpp = 4.5 to 5.5V, Topr = 30 to 70C) PARAMETER SYMBOL CONDITIONS Min. Typ. | Max. | UNIT Instruction Cycle Time tey 1.9 _ 20 us High level Clock pulse Width tweu External clock mode 80 _ _ ns. Low level Clock pulse Width twei A/D Sampling Time tain fc =4 MHz - 4 - tS Shift Data Hold Time tspy 0.5 try - 300 _ _ ns Note. Shift Data Hold Time . _ . Serial port (completion of transmission) External circuit for SCK pin and SO pin VDD 3CK 1.5V 10kQ tsbH a 90 pF sO x x x H#isv RECOMMENDED OSCILLATING CONDITIONS (Vss = OV, Vpp =4.5 to 5.5V, Topr = 30 to 70C) (1) 4MHz XIN XOUT Ceramic Resonator CSA4. OOMG (MURATA) Cxin = CxouT = 30 pF 4MHz KBR-4. OOMS (KYOCERA) Cxin = Cxout = 30 pF U Crystal Oscillator Cxin Cxourt 204B-6F 4. 0000 (TOYOCOM) Cx|n = Cxout = 20 pF a> > (2) 400kHz XIN XOUT Ceramic Resonator CSB400B (MURATA) Cxin = Cxout = 220 pF, RxoutT = 6.8 ko 400 kHz Ryour KBR-400B (KYOCERA) Cxin = Cxout = 100 pF, Rxout = 10 ka ul ey a Cxout 5-40-15TOSHIBA TYPICAL CHARACTERISTICS R-Ta KO port (KQ) | Vp =5.5V 100 a va < 50 0 Ta -A0 0 40 80 (C) lo. - VoL R port lot (mA) Vpop =4.5V Ta=25C 8 y LIZ 4 71 2 / 0 VoL 0.4 0.8 1.2 (V) Ipp - Vpp Ipp (MA)] Ta = 25C 4 3 fe = 4 MHz 2 1 0 Vpp 3 5 7 (Vv) ' Operating area C MHz) Ta= 30 to 70C ( (Normal mode) Vpp (Vv) (kQ) 400 300 200 100 - 40 (mA) 40 30 20 10 Ipp (mA) TMP47C440B RESET pin Ta 80 (C) P1, P2 port LL Vo 1.2(V) fc i 10 (MHz)