INTEGRATED CIRCUITS DATA SHEET UDA1352TS 48 kHz IEC 60958 audio DAC Preliminary specification Supersedes data of 2002 May 22 2002 Nov 22 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS CONTENTS 11 SPDIF SIGNAL FORMAT 11.1 11.2 11.3 11.4 SPDIF channel encoding SPDIF hierarchical layers for audio data SPDIF hierarchical layers for digital data Timing characteristics 12 REGISTER MAPPING 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 SPDIF mute setting (write) Power-down settings (write) Volume control left and right (write) Sound feature mode, treble and bass boost settings (write) Mute (write) Polarity (write) SPDIF input settings (write) Interpolator status (read-out) SPDIF status (read-out) Channel status (read-out) FPLL status (read-out) 13 LIMITING VALUES 14 THERMAL CHARACTERISTICS 1 FEATURES 1.1 1.2 1.3 1.4 General Control IEC 60958 input Digital sound processing and DAC 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.3 8.4 8.5 Clock regeneration and lock detection Mute Auto mute Data path Control 9 L3-BUS DESCRIPTION 15 CHARACTERISTICS 9.1 9.2 9.3 9.4 9.5 9.6 General Device addressing Register addressing Data write mode Data read mode Initialization string 16 TIMING CHARACTERISTICS 17 APPLICATION INFORMATION 18 PACKAGE OUTLINE 19 SOLDERING 19.1 10 I2C-BUS DESCRIPTION 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 Characteristics of the I2C-bus Bit transfer Byte transfer Data transfer Start and stop conditions Acknowledgment Device address Register address Write and read data Write cycle Read cycle Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 2002 Nov 22 19.2 19.3 19.4 19.5 2 20 DATA SHEET STATUS 21 DISCLAIMERS 22 TRADEMARKS NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 1 UDA1352TS FEATURES 1.1 General * 2.7 to 3.6 V power supply * Integrated digital filter and Digital-to-Analog Converter (DAC) * 256fs system clock output * 20-bit data path in interpolator * Bass boost and treble control in L3-bus or I2C-bus mode * High performance * Interpolating filter (fs to 64fs) by means of a cascade of a recursive filter and a FIR filter * No analog post filtering required for DAC * Supporting sampling frequencies from 28 up to 55 kHz. 1.2 * Fifth-order noise shaper (operating at 64fs) generates the bitstream for the DAC Control * Filter Stream DAC (FSDAC). * Controlled either by means of static pins, I2C-bus or L3-bus microcontroller interface. 1.3 2 * Digital audio systems. IEC 60958 input * On-chip amplifier for converting IEC 60958 input to CMOS levels 3 * Lock indication signal available on pin LOCK A lock indication signal is available on pin LOCK, indicating that the IEC 60958 decoder is locked. A separate pin PCMDET is available to indicate whether or not the PCM data is applied to the input. * For left and right 40 key channel-status bits available via L3-bus or I2C-bus interface. Digital sound processing and DAC By default, the DAC output is muted when the decoder is out-of-lock. However, this setting can be overruled in the L3-bus or I2C-bus mode. * Automatic de-emphasis when using IEC 60958 input with 32.0, 44.1 and 48.0 kHz audio sample frequencies * Soft mute by means of a cosine roll-off circuit selectable via pin MUTE, L3-bus or I2C-bus interface The UDA1352TS has IEC 60958 input to the DAC only and is in SSOP28 package. * Left and right independent dB linear volume control with 0.25 dB steps from 0 to -50 dB, 1 dB steps to -60, -66 and - dB 4 GENERAL DESCRIPTION The UDA1352TS is a single-chip IEC 60958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques. * Information of the Pulse Code Modulation (PCM) status bit and the non-PCM data detection is available on pin PCMDET 1.4 APPLICATIONS Besides the UDA1352TS, the UDA1352HL is also available. The UDA1352HL is the full featured version in LQFP48 package. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1352TS SSOP28 2002 Nov 22 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm 3 VERSION SOT341-1 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 5 QUICK REFERENCE DATA VDDD = VDDA = 3.0 V; IEC 60958 input with fs = 48.0 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 3.6 V Supplies VDDD digital supply voltage VDDA analog supply voltage 2.7 3.0 3.6 V IDDA(DAC) analog supply current of DAC power-on - 3.3 - mA - 35 - A 2.7 power-down; clock off 3.0 IDDA(PLL) analog supply current of PLL - 0.3 - mA IDDD(C) digital supply current of core - 9 - mA IDDD digital supply current - 0.3 - mA P power dissipation DAC in playback mode - 38 - mW DAC in Power-down mode - tbf - mW General trst reset active time - 250 - s Tamb ambient temperature -40 - +85 C Digital-to-analog converter Vo(rms) output voltage (RMS value) fi = 1.0 kHz tone at 0 dBFS; note 1 850 900 950 mV Vo unbalance of output voltages fi = 1.0 kHz tone - 0.1 0.4 dB (THD+N)/S total harmonic distortion-plus-noise to signal ratio fi = 1.0 kHz tone at 0 dBFS - -82 -77 dB at -40 dBFS; A-weighted - -60 -52 dB S/N signal-to-noise ratio fi = 1.0 kHz tone; code = 0; A-weighted 95 100 - dB cs channel separation fi = 1.0 kHz tone 110 - dB Note 1. The output voltage of the DAC is proportional to the DAC power supply voltage. 2002 Nov 22 4 - NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 6 UDA1352TS BLOCK DIAGRAM VDDA(DAC) handbook, full pagewidth TEST1 VDDA(PLL) VSSA(PLL) VDDD(C) VSSD(C) DA0 DA1 L3MODE L3CLOCK L3DATA SELSTATIC SELIIC SPDIF VDDD VSSD 2 24 TEST2 VOUTL 18 15 23 VSSA(DAC) 14 20 DAC CLOCK AND TIMING CIRCUIT 6 Vref VOUTR 19 17 DAC 12 NOISE SHAPER 28 UDA1352TS 25 INTERPOLATOR 10 9 8 L3-BUS OR I2C-BUS INTERFACE AUDIO FEATURE PROCESSOR 11 NON-PCM DATA SYNC DETECTOR 26 4 SLICER 13 5 IEC 60958 DECODER 3 7 21, 22, 27 1 16 MGU655 n.c. PCMDET LOCK Fig.1 Block diagram. 2002 Nov 22 MUTE 5 RESET NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 7 UDA1352TS PINNING SYMBOL PIN TYPE(1) DESCRIPTION PCMDET 1 DO PCM detection indicator output TEST1 2 DO test pin 1; must be left open-circuit in application VDDD 3 DS digital supply voltage SELIIC 4 DID I2C-bus or L3-bus mode selection input RESET 5 DID reset input VDDD(C) 6 DS digital supply voltage for core VSSD 7 DGND L3DATA 8 IIC L3-bus or I2C-bus interface data input and output L3CLOCK 9 DIS L3-bus or I2C-bus interface clock input L3MODE 10 DIS L3 interface mode input MUTE 11 DID mute control input VSSD(C) 12 DGND SPDIF 13 AIO digital ground digital ground for core IEC 60958 channel input VDDA(DAC) 14 AS analog supply voltage for DAC VOUTL 15 AIO DAC left channel analog output LOCK 16 DO SPDIF and PLL lock indicator output VOUTR 17 AIO DAC right channel analog output TEST2 18 DID test pin 2; must be connected to digital ground (VSSD) in application Vref 19 AIO DAC reference voltage VSSA(DAC) 20 AGND analog ground for DAC n.c. 21 - not connected n.c. 22 - not connected VSSA(PLL) 23 AGND VDDA(PLL) 24 AS DA1 25 DISU SELSTATIC 26 DIU n.c. 27 - DA0 28 DID analog ground for PLL analog supply voltage for PLL A1 device address selection input static pin control selection input not connected (reserved) A0 device address selection input Note 1. See Table 1. 2002 Nov 22 6 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC Table 1 UDA1352TS Pin types TYPE DESCRIPTION DS digital supply DGND digital ground AS analog supply AGND analog ground DI digital input DIS digital Schmitt-triggered input DID digital input with internal pull-down resistor DISD digital Schmitt-triggered input with internal pull-down resistor DIU digital input with internal pull-up resistor DISU digital Schmitt-triggered input with internal pull-up resistor DO digital output DIO digital input and output DIOS digital Schmitt-triggered input and output IIC input and open-drain output for I2C-bus AIO analog input and output handbook, halfpage PCMDET 1 28 DA0 TEST1 2 27 n.c. VDDD 3 26 SELSTATIC SELIIC 4 25 DA1 RESET 5 24 VDDA(PLL) VDDD(C) 6 23 VSSA(PLL) VSSD 7 L3DATA 8 21 n.c. L3CLOCK 9 20 VSSA(DAC) 22 n.c. UDA1352TS 19 Vref L3MODE 10 18 TEST2 MUTE 11 17 VOUTR VSSD(C) 12 16 LOCK SPDIF 13 15 VOUTL VDDA(DAC) 14 MGU654 Fig.2 Pin configuration. 2002 Nov 22 7 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8 8.1 UDA1352TS FUNCTIONAL DESCRIPTION Clock regeneration and lock detection The UDA1352TS contains an on-board PLL for regenerating a system clock from the IEC 60958 input bitstream. mute factor 0.8 Remark: If there is no input signal, the PLL generates a minimum frequency and the output spectrum shifts accordingly. Since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band. 0.6 0.4 When the on-board clock locks to the incoming frequency, the lock indicator bit is set and can be read via the L3-bus or I2C-bus interface. Internally, the PLL lock indication can be combined with the PCM status bit of the input data stream and the status whether any burst preamble is detected or not. By default, when both the IEC 60958 decoder and the on-board clock have locked to the incoming signal and the input data stream is PCM data, pin LOCK will be asserted. However, when the IC is locked but the PCM status bit reports non-PCM data, pin LOCK is returned to LOW level. This combination of the lock status and the PCM detection can be overruled by the L3-bus or I2C-bus register setting. 0.2 0 0 10 15 20 25 Fig.3 Mute as a function of raised cosine roll-off. 8.3 Auto mute By default, the DAC outputs will be muted until the UDA1352TS is locked, regardless of the level on pin MUTE or the state of bit MT. In this way, only valid data will be passed to the outputs. This mute is done in the SPDIF interface and is a hard mute, not a cosine roll-off mute. The UDA1352TS has a dedicated pin PCMDET to indicate whether valid PCM data stream is detected or (supposed to be) non-PCM data is detected. If needed, this muting can be bypassed by setting bit MUTEBP = 1 via the L3-bus or I2C-bus interface. As a result, the UDA1352TS will no longer mute during out-of-lock situations. Mute The UDA1352TS is equipped with a cosine roll-off mute in the DSP data path of the DAC part. Muting the DAC (by pin MUTE or via bit MT in the L3-bus or I2C-bus mode) will result in a soft mute as shown in Fig.3. The cosine roll-off soft mute takes 32 x 32 samples = 23 ms at 44.1 kHz sampling frequency. When operating in the L3-bus or I2C-bus mode, the device will mute on start-up. In the L3-bus or I2C-bus mode, it is necessary to explicitly switch off the mute for audio output by means of bit MT in the device register. In the L3-bus or I2C-bus mode, pin MUTE will at all time mute the output signal. This is in contrast to the UDA1350 and the UDA1351 in which pin MUTE in the L3-bus mode does not have any function. 2002 Nov 22 5 t (ms) The lock indication output can be used, for example, for muting purposes. The lock signal can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the PLL runs at its minimum frequency (e.g. when there is no SPDIF input signal). 8.2 MGU119 1 handbook, halfpage 8 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8.4 UDA1352TS Data path 8.4.2 The audio feature processor automatically provides de-emphasis for the IEC 60958 data stream in the static pin control mode and default mute at start-up in the L3-bus or I2C-bus mode. The UDA1352TS data path consists of the IEC 60958 decoder, the audio feature processor, the digital interpolator and noise shaper and the DACs. 8.4.1 AUDIO FEATURE PROCESSOR IEC 60958 INPUT When used in the L3-bus or I2C-bus mode, it provides the following additional features: The IEC 60958 decoder features an on-chip amplifier with hysteresis, which amplifies the SPDIF input signal to CMOS level (see Fig.4). * Left and right independent volume control * Bass boost control All 24 bits of data for left and right are extracted from the input bitstream as well as 40 channel status bits for left and right. These bits can be read via the L3-bus or I2C-bus interface. * Treble control * Mode selection of the sound processing bass boost and treble filters: flat, minimum and maximum * Soft mute control with raised cosine roll-off. 8.4.3 The UDA1352TS includes an on-board interpolating filter which converts the incoming data stream from 1fs to 64fs by cascading a recursive filter and a FIR filter. handbook, halfpage 10 nF 75 INTERPOLATOR Table 2 SPDIF 13 180 pF Interpolator characteristics PARAMETER CONDITIONS VALUE (dB) Pass-band ripple 0 to 0.45fs 0.03 >0.55fs -50 Stop band UDA1352TS Dynamic range MGU656 DC gain 8.4.4 Fig.4 IEC 60958 input circuit and typical application. 114 - -5.67 NOISE SHAPER The fifth-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted to an analog signal using a filter stream DAC. The UDA1352TS supports the following sample frequencies and data bit rates: * fs = 32.0 kHz, resulting in a data rate of 2.048 Mbits/s * fs = 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s * fs = 48.0 kHz, resulting in a data rate of 3.072 Mbits/s. The UDA1352TS supports timing levels I, II and III, as specified by the IEC 60958 standard. This means that the accuracy of the above mentioned sampling frequencies depends on the timing level I, II or III as mentioned in Section 11.4.1. 2002 Nov 22 0 to 0.45fs 9 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 8.4.5 UDA1352TS FILTER STREAM DAC 8.5 The Filter Stream DAC (FSDAC) is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The UDA1352TS can be controlled by means of static pins (when pin SELSTATIC = HIGH), via the I2C-bus (when pin SELSTATIC = LOW and pin SELIIC = HIGH) or via the L3-bus (when pins SELSTATIC and SELIIC are LOW). For optimum use of the features of the UDA1352TS, the L3-bus or I2C-bus mode is recommended since only basic functions are available in the static pin control mode. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. It should be noted that the static pin control mode and the L3-bus or I2C-bus mode are mutually exclusive. 8.5.1 STATIC PIN CONTROL MODE The default values for all non-pin controlled settings are identical to the default values at start-up in the L3-bus or I2C-bus mode (see Table 3). The output voltage of the FSDAC is scaled proportionally with the power supply voltage. Table 3 Control Pin description of static pin control mode PIN NAME VALUE FUNCTION Mode selection pin 26 SELSTATIC 1 select static pin control mode; must be connected to VDDD 5 RESET 0 normal operation 1 reset 9 L3CLOCK 0 must be connected to VSSD 10 L3MODE 0 must be connected to VSSD 8 L3DATA 0 must be connected to VSSD 11 MUTE 0 no mute 1 mute active 0 non-PCM data or burst preamble detected 1 PCM data detected Input pins Status pins 1 16 PCMDET LOCK 0 clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected 1 clock regeneration and IEC 60958 decoder locked and PCM data detected Test pins 2 TEST1 - must be left open-circuit 18 TEST2 0 must be connected to VSSD 2002 Nov 22 10 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS L3-BUS OR I2C-BUS MODE 8.5.2 The L3-bus or I2C-bus mode allows maximum flexibility in controlling the UDA1352TS (see Table 4). It should be noted that in the L3-bus or I2C-bus mode, several base-line functions are still controlled by pins on the device and that, on start-up in the L3-bus or I2C-bus mode, the output is explicitly muted by bit MT via the L3-bus or I2C-bus interface. Table 4 Pin description in the L3-bus or I2C-bus mode PIN NAME VALUE FUNCTION Mode selection pins 26 SELSTATIC 0 select L3-bus mode or I2C-bus mode; must be connected to VSSD 4 SELIIC 0 select L3-bus mode; must be connected to VSSD 1 select I2C-bus mode; must be connected to VDDD 0 normal operation 1 reset - must be connected to the L3-bus - must be connected to the SDA line of the I2C-bus - must be connected to the L3-bus - must be connected to the SCL line of the I2C-bus Input pins 5 8 9 RESET L3DATA L3CLOCK 10 L3MODE - must be connected to the L3-bus 11 MUTE 0 no mute 1 mute active 0 non-PCM data or burst preamble detected 1 PCM data detected Status pins 1 16 PCMDET LOCK 0 clock regeneration and IEC 60958 decoder out-of-lock or non-PCM data detected 1 clock regeneration and IEC 60958 decoder locked and PCM data detected Test pins 2 TEST1 - must be left open-circuit 18 TEST2 0 must be connected to VSSD 2002 Nov 22 11 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 9 9.1 UDA1352TS L3-BUS DESCRIPTION Remark: when the device is powered-up, at least one L3CLOCK pulse must be given to the L3-bus interface to wake-up the interface before starting sending to the device (see Fig.5). This is only needed once after the device is powered-up. General The UDA1352TS has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. 9.2 The controllable settings are: Device addressing * Restoring L3-bus default values The device address consists of 1 byte with: * Power-on * Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see Table 5) * Selection of filter mode and settings of treble and bass boost * Address bits 2 to 7 representing a 6-bit device address. The bits 2 and 3 of the address can be selected via the external pins DA0 and DA1, which allows up to 4 UDA1352TS devices to be independently controlled in a single application. * Volume settings left and right * Selection of soft mute via cosine roll-off and bypass of auto mute. The readable settings are: The primary address of the UDA1352TS is `001000' (LSB to MSB) and the default address is `011000'. * Mute status of interpolator * PLL locked Table 5 * SPDIF input signal locked Selection of data transfer DOM * Audio sample frequency TRANSFER BIT 0 BIT 1 * Pre-emphasis of the IEC 60958 input signal 0 0 not used * Accuracy of the clock. 1 0 not used 0 1 write data or prepare read 1 1 read data * Valid PCM data detected The exchange of data and control information between the microcontroller and the UDA1352TS is LSB first and is accomplished through the serial hardware L3-bus interface comprising the following pins: 9.3 * L3DATA: data line Register addressing The L3-bus format has two modes of operation: After sending the device address (including DOM bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. * Address mode Basically, there are three methods for register addressing: * Data transfer mode. 1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see Fig.5) * L3MODE: mode line * L3CLOCK: clock line. The address mode is used to select a device for a subsequent data transfer. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.5). The data transfer mode is characterized by L3MODE being HIGH and is used to transfer one or more bytes representing a register address, instruction or data. 2. Addressing for prepare read: bit 0 is logic 1, indicating that data will be read from the register (see Fig.6) 3. Addressing for data read action. Here, the device returns a register address prior to sending data from that register. When bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid. Basically, two types of data transfers can be defined: * Write action: data transfer to the device * Read action: data transfer from the device. 2002 Nov 22 12 L3CLOCK L3MODE device address 1 0 L3DATA register address data byte 1 data byte 2 0 MGS753 DOM bits write NXP Semiconductors 48 kHz IEC 60958 audio DAC 2002 Nov 22 L3 wake-up pulse after power-up Fig.5 Data write mode (for L3-bus version 2). 13 L3CLOCK L3MODE register address device address L3DATA DOM bits read 1 1 data byte 2 0/1 valid/invalid prepare read sent by the device Fig.6 Data read mode. MBL565 Preliminary specification 1 data byte 1 UDA1352TS 0 1 requesting register address device address NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 9.4 UDA1352TS Data write mode For reading data from a device, the following 6 bytes are involved (see Table 7): The data write mode is explained in the signal diagram of Fig.5. For writing data to a device, 4 bytes must be sent (see Table 6): 1. One byte with the device address, including `01' for signalling the write action to the device 2. One byte is sent with the register address from which data needs to be read; this byte starts with a `1', which indicates that there will be a read action from the register, followed by seven bits for the source register address in binary format, with A6 being the MSB and A0 being the LSB 1. One byte starting with `01' for signalling the write action to the device, followed by the device address (`011000' for the UDA1352TS default) 2. One byte starting with a `0' for signalling the write action, followed by 7 bits indicating the destination register address in binary format with A6 being the MSB and A0 being the LSB 3. One byte with the device address preceded by `11' is sent to the device; the `11' indicates that the device must write data to the microcontroller 3. One data byte (from the two data bytes) with D15 being the MSB 4. One byte, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) 4. One data byte (from the two data bytes) with D0 being the LSB. It should be noted that each time a new destination register address needs to be written, the device address must be sent again. 9.5 5. One byte (from the two bytes), sent by the device to the bus, with the data information in binary format, with D15 being the MSB Data read mode 6. One byte (from the two bytes), sent by the device to the bus, with the data information in binary format, with D0 being the LSB. To read data from the device, a prepare read must first be done and then data read. The data read mode is explained in the signal diagram of Fig.6. Table 6 L3-bus write data FIRST IN TIME L3-BUS MODE BYTE LAST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 1 address device address 0 1 DA0 DA1 1 0 0 0 2 data transfer register address 0 A6 A5 A4 A3 A2 A1 A0 3 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 4 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 Table 7 L3-bus read data L3-BUS MODE BYTE FIRST IN TIME LAST IN TIME ACTION BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 0 1 DA0 DA1 1 0 0 0 1 address device address 2 data transfer register address 1 A6 A5 A4 A3 A2 A1 A0 3 address device address 1 1 DA0 DA1 1 0 0 0 4 data transfer register address 0 or 1 A6 A5 A4 A3 A2 A1 A0 5 data transfer data byte 1 D15 D14 D13 D12 D11 D10 D9 D8 6 data transfer data byte 2 D7 D6 D5 D4 D3 D2 D1 D0 2002 Nov 22 14 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 9.6 UDA1352TS Initialization string For proper and reliable operation, the UDA1352TS must be initialized in the L3-bus mode. This is required to have the PLL start-up after powering up of the device under all conditions. The initialization string is given in Table 8. Table 8 BYTE L3-bus initialization string and set defaults after power-up FIRST IN TIME L3-BUS MODE LAST IN TIME ACTION init string BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 device address 0 1 DA0 DA1 1 0 0 0 1 address 2 data transfer register address 0 1 0 0 0 0 0 0 3 data transfer data byte 1 0 0 0 0 0 0 0 0 4 data transfer data byte 2 0 0 0 0 0 0 0 1 5 address 6 data transfer 7 8 set defaults device address 0 1 DA0 DA1 1 0 0 0 register address 0 1 1 1 1 1 1 1 data transfer data byte 1 0 0 0 0 0 0 0 0 data transfer data byte 2 0 0 0 0 0 0 0 0 10.2 10 I2C-BUS DESCRIPTION 10.1 Bit transfer One data bit is transferred during each clock pulse (see Fig.7). The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. Characteristics of the I2C-bus The bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the VDD via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz IC the recommendation for this type of bus from NXP Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 to 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy. To be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this high-speed I2C-bus according to specification "The I2C-bus and how to use it", (order code 9398 393 40011). handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed Fig.7 Bit transfer on the I2C-bus. 2002 Nov 22 15 MBC621 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 10.3 UDA1352TS Byte transfer controls the message is the master and the devices which are controlled by the master are the slaves. Each byte (8 bits) is transferred with the MSB first (see Table 9). Table 9 Byte transfer MSB 7 10.4 10.5 BIT NUMBER 6 5 4 3 Both data and clock line will remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as a start condition (S); see Fig.8. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a stop condition (P). LSB 2 1 Start and stop conditions 0 Data transfer A device generating a message is a transmitter, a device receiving a message is the receiver. The device that handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig.8 START and STOP conditions on the I2C-bus. 10.6 Acknowledgment The device that acknowledges has to pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition. The number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Fig.9). At the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. 2002 Nov 22 16 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.9 Acknowledge on the I2C-bus. 10.7 10.8 Device address Register address Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with byte 1 transmitted after the start procedure. The register addresses in the I2C-bus mode are the same as in the L3-bus mode. The device address can be one out of four, being set by pin DA0 and pin DA1. The I2C-bus configuration for a write and read cycle are shown respectively in Tables 11 and 12. The write cycle is used to write groups of two bytes to the internal registers for the digital sound feature control and system setting. It is also possible to read these locations for the device status information. 10.9 The UDA1352TS acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1352TS device address is shown in Table 10. Table 10 I2C-bus device address DEVICE ADDRESS R/W A6 A5 A4 A3 A2 A1 A0 - 1 0 0 1 1 DA1 DA0 0/1 2002 Nov 22 17 Write and read data The format of the write cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `1001 110' and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1352TS. 4. After this the microcontroller writes the 8-bit register address (ADDR) where the writing of the register content of the UDA1352TS must start. 5. The UDA1352TS acknowledges this register address (A). 6. The microcontroller sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the UDA1352TS. 7. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the UDA1352TS. 8. Finally, the UDA1352TS frees the I2C-bus and the microcontroller can generate a stop condition (P). NXP Semiconductors The I2C-bus configuration for a write cycle is shown in Table 11. The write cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a pair of two bytes. 48 kHz IEC 60958 audio DAC 2002 Nov 22 10.10 Write cycle Table 11 Master transmitter writes to the UDA1352TS registers in the I2C-bus mode. 18 S DEVICE ADDRESS R/W 1001 110 0 REGISTER ADDRESS A ADDR DATA 2(1) DATA 1 A MS1 A LS1 A MS2 A LS2 DATA n(1) A MSn A LSn A P acknowledge from UDA1352TS Note 1. Auto increment of register address. Preliminary specification UDA1352TS The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `1001 110' and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1352TS. 4. After this the microcontroller writes the register address (ADDR) where the reading of the register content of the UDA1352TS must start. 5. The UDA1352TS acknowledges this register address. 6. Then the microcontroller generates a repeated start (Sr). 7. Then the microcontroller generates the device address `1001 110' again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1352TS. 8. The UDA1352TS sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the microcontroller. 9. If repeated groups of 2 bytes are transmitted, then the register address is auto incremented. After each byte an acknowledge is followed from the microcontroller. NXP Semiconductors The read cycle is used to read the data values from the internal registers. The I2C-bus configuration for a read cycle is shown in Table 12. 48 kHz IEC 60958 audio DAC 2002 Nov 22 10.11 Read cycle 10. The microcontroller stops this cycle by generating a negative acknowledge (NA). 19 11. Finally, the UDA1352TS frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 12 Master transmitter reads from the UDA1352TS registers in the I2C-bus mode. DEVICE R/W ADDRESS S 1001 110 0 REGISTER ADDRESS A ADDR DEVICE R/W ADDRESS A Sr 1001 110 acknowledge from UDA1352TS 1 DATA 2(1) DATA 1 A MS1 A LS1 A MS2 A LS2 DATA n(1) A MSn A LSn NA P acknowledge from master Note 1. Auto increment of register address. Preliminary specification UDA1352TS NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 11 SPDIF SIGNAL FORMAT 11.1 Table 13 Preambles SPDIF channel encoding CHANNEL CODING PRECEDING STATE The digital signal is coded using Bi-phase Mark Code (BMC), which is a kind of phase-modulation. In this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 to one zero-crossing. An example of the encoding is given in Fig.10. 0 1 B 1110 1000 0001 0111 M 1110 0010 0001 1101 W 1110 0100 0001 1011 11.3 SPDIF hierarchical layers for digital data The difference with the audio format is that the data contained in the SPDIF signal is not audio but is digital data. handbook, halfpage clock When transmitting digital data via SPDIF using the IEC 60958 protocol, the allocation of the bits inside the data word is done as shown in Table 14. data BMC Table 14 Bit allocation for digital data MGU606 FIELD Fig.10 Bi-phase mark encoding. IEC 60958 TIME SLOT BITS DESCRIPTION 0 to 3 preamble according to IEC 60958 4 to 7 auxiliary bits not used; all logic 0 8 to 11 unused data bits not used; all logic 0 From an abstract point of view an SPDIF signal can be represented as in Fig.11. A 2-channel PCM signal can be transmitted as various sequential blocks. Each block in turn consists of 192 frames. Each frame contains two sub-frames, one for each channel. 12 16 bits data sections of the digital bitstream 13 user data according to IEC 60958 14 to 27 16 bits data sections of the digital bitstream Each sub-frame is preceded by a preamble. There are three types of preambles being B, M and W. Preambles can be spotted easily in an SPDIF stream because these sequences can never occur in the channel parts of a valid SPDIF stream. Table 13 indicates the values of the preambles. 28 validity bit according to IEC 60958 29 user data according to IEC 60958 30 channel status bit according to IEC 60958 31 parity bit according to IEC 60958 11.2 SPDIF hierarchical layers for audio data As shown in Table 14 and Fig.13, the non-PCM encoded data bitstreams are transferred within the basic 16 bits data area of the IEC 60958 sub-frames [time-slots 12 (LSB) to 27 (MSB)]. A sub-frame in turn contains a single audio sample which may be up to 24 bits wide, a validity bit which indicates whether the sample is valid, a single bit of user data, and a single bit of channel status. Finally, there is a parity bit for this particular sub-frame (see Fig.12). The data bits from 4 to 31 in each sub-frame will be modulated using a BMC scheme. The sync preamble actually contains a violation of the BMC scheme and consequently can be detected easily. 2002 Nov 22 20 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS handbook, full pagewidth M channel 1 W channel 2 B channel 1 sub-frame frame 191 W channel 2 M channel 1 channel 2 M channel 1 W channel 2 sub-frame frame 0 frame 191 block MGU607 Fig.11 SPDIF block format. 0 handbook, full pagewidth sync preamble 3 4 7 8 L S B L S B auxiliary 27 28 M S B audio sample word V 31 U C P validity flag user data channel status parity bit MGU608 Fig.12 Sub-frame format in audio mode. 0 handbook, full pagewidth sync preamble 3 4 L S B 7 8 auxiliary L unused S data B 11 12 27 28 L S B M S B 16-bit data stream V 31 U C P validity flag user data channel status parity bit MGU609 Fig.13 Sub-frame format in non-PCM mode. 2002 Nov 22 21 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 11.3.1 UDA1352TS FORMAT OF THE BITSTREAM The non-PCM data is transmitted in data bursts, consisting of four 16-bit words (called Pa, Pb, Pc and Pd) followed by the so called burst-payload. The definition of the burst preambles is given in Table 15. Table 15 Burst preamble words PREAMBLE WORD LENGTH OF THE FIELD CONTENTS VALUE Pa 16 bits sync word 1 F872 (hex) Pb 16 bits sync word 2 4E1F (hex) Pc 16 bits burst information see Table 16 Pd 16 bits length code number of bits 11.3.2 BURST INFORMATION The burst information given in preamble Pc, meaning the information contained in the data stream, is defined according to IEC 60958 as given in Table 16. Table 16 Fields of burst information in preamble Pc BITS OF Pc VALUE REPETITION TIME OF DATA BURST IN IEC 60958 FRAMES REFERENCE POINT R CONTENTS 0 NULL data - none 1 AC-3 data R_AC-3 1536 2 reserved - - 3 pause bit 0 of Pa refer to IEC 60958 4 MPEG-1 layer 1 data bit 0 of Pa 384 5 MPEG-1 layer 1, 2 or 3 data or MPEG-2 without extension bit 0 of Pa 1152 6 MPEG-2 with extension bit 0 of Pa 1152 7 reserved - - 8 MPEG-2, layer 1 low sampling rate bit 0 of Pa 768 9 MPEG-2, layer 2 or 3 low sampling rate bit 0 of Pa 2304 10 reserved - - 11 to 13 reserved (DTS) - refer to IEC 61937 14 to 31 reserved - - 5 to 6 0 reserved - - 7 0 error flag indicating a valid burst-payload - - 1 error flag indicating an invalid burst-payload - - 0 to 4 8 to 12 - data type dependant information - - 13 to 15 0 bitstream number - - 2002 Nov 22 22 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 11.3.3 UDA1352TS Rise and fall times should be in the range: MINIMUM BURST SPACING * 0% to 20% when the data bit is a logic 1 In order to be able to detect the start of a data burst, it is prescribed to have a data-burst which does not exceed 4096 frames. After 4096 frames there must be a synchronization sequence containing 2 frames of complete zero data (being 4 times 16 bits) followed by the preamble burst Pa and Pb. In this way a comparison with a sync code of 96 bits can detect the start of a new burst-payload including the Pc and Pd preambles containing additional stream information. 11.4 11.4.1 * 0% to 10% when the data bits are two succeeding logic zeros. 11.4.3 DUTY CYCLE The duty cycle (see Fig.14) is defined as: tH Duty cycle = -------------------- x 100% ( tL + tH ) Timing characteristics The duty cycle should be in the range: * 40% to 60% when the data bit is a logic 1 FREQUENCY REQUIREMENTS * 45% to 55% when the data bits are two succeeding logic zeros. The SPDIF specification IEC 60958 supports three levels of clock accuracy, being: * Level I, high accuracy: tolerance of transmitting sampling frequency shall be within 50 x 10-6 * Level II, normal accuracy: all receivers should receive a signal of 1000 x 10-6 of nominal sampling frequency * Level III, variable pitch shifted clock mode: a deviation of 12.5% of the nominal sampling frequency is possible. 11.4.2 tL tH handbook, halfpage 90% 50% RISE AND FALL TIMES 10% Rise and fall times (see Fig.14) are defined as: tr tr Rise time = -------------------- x 100% ( tL + tH ) tf Fall time = -------------------- x 100% ( tL + tH ) 2002 Nov 22 tf Fig.14 Rise and fall times. 23 MGU612 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 12 REGISTER MAPPING Table 17 Register map of control settings (write) REGISTER ADDRESS FUNCTION System settings 01H SPDIF mute setting 03H power-down settings Interpolator 10H volume control left and right 12H sound feature mode, treble and bass boost 13H mute 14H polarity SPDIF input settings 30H SPDIF input settings Software reset 7FH restore L3-bus default values Table 18 Register map of status bits (read-out) REGISTER ADDRESS FUNCTION Interpolator 18H interpolator status SPDIF input 59H SPDIF status 5AH channel status bits left [15:0] 5BH channel status bits left [31:16] 5CH channel status bits left [39:32] 5DH channel status bits right [15:0] 5EH channel status bits right [31:16] 5FH channel status bits right [39:32] FPLL 68H 2002 Nov 22 FPLL status 24 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.1 UDA1352TS SPDIF mute setting (write) Table 19 Register address 01H BIT 15 14 13 12 11 10 9 8 Symbol - - - - - - - MUTEBP Default - - - - - - - 0 7 6 5 4 3 2 1 0 Symbol - - - - - - - - Default - - - - - 0 0 0 BIT Table 20 Description of register bits BIT SYMBOL DESCRIPTION - reserved MUTEBP Mute bypass setting. A 1-bit value to disable the mute bypass setting. When this mute bypass setting is enabled, then even in out-of-lock situations or non-PCM data detected, the output data will not be suppressed. If this bit is logic 0, then the output will be muted in out-of-lock situations. If this bit is logic 1, then the output will not be muted in out-of-lock situations. Default value 0. 7 to 3 - reserved 2 to 0 - When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. 15 to 9 8 2002 Nov 22 25 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.2 UDA1352TS Power-down settings (write) Table 21 Register address 03H BIT 15 14 13 12 11 10 9 8 Symbol - - - - - - - - Default - - - - - - - - 7 6 5 4 3 2 1 0 Symbol - - - PON_ SPDIFIN - - EN_INT PONDAC Default - - - 1 0 0 1 1 BIT Table 22 Description of register bits BIT SYMBOL DESCRIPTION - reserved PON_SPDIFIN Power control SPDIF input. A 1-bit value to enable or disable the power of the IEC 60958 bit slicer. If this bit is logic 0, then the power is off. If this bit is logic 1, then the power is on. Default value 1. - When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. 1 EN_INT Interpolator clock control. A 1-bit value to control the interpolator clock. If this bit is logic 0, then the interpolator clock is disabled. If this bit is logic 1, then the interpolator clock is enabled. Default value 1. 0 PONDAC Power control DAC. A 1-bit value to switch the DAC into power-on or Power-down mode. If this bit is logic 0, then the DAC is in Power-down mode. If this bit is logic 1, then the DAC is in power-on mode. Default value 1. 15 to 5 4 3 to 2 2002 Nov 22 26 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.3 UDA1352TS Volume control left and right (write) Table 23 Register address 10H BIT 15 14 13 12 11 10 9 8 Symbol VCL_7 VCL_6 VCL_5 VCL_4 VCL_3 VCL_2 VCL_1 VCL_0 Default 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Symbol VCR_7 VCR_6 VCR_5 VCR_4 VCR_3 VCR_2 VCR_1 VCR_0 Default 0 0 0 0 0 0 0 0 BIT Table 24 Description of register bits BIT SYMBOL DESCRIPTION 15 to 8 VCL_[7:0] Volume setting left channel. A 8-bit value to program the left channel volume attenuation. The range is 0 to -50 dB in steps of 0.25 dB, to -60 dB in steps of 1 dB, -66 dB and - dB. Default value 0000 0000; see Table 25. 7 to 0 VCR_[7:0] Volume setting right channel. A 8-bit value to program the right channel volume attenuation. The range is 0 to -50 dB in steps of 0.25 dB, to -60 dB in steps of 1 dB, -66 dB and - dB. Default value 0000 0000; see Table 25. Table 25 Volume settings left and right channel VCL_7 VCL_6 VCL_5 VCL_4 VCL_3 VCL_2 VCL_1 VCL_0 VCR_7 VCR_6 VCR_5 VCR_4 VCR_3 VCR_2 VCR_1 VCR_0 0 0 0 0 0 0 0 0 0 (default) 0 0 0 0 0 0 0 1 -0.25 0 0 0 0 0 0 1 0 -0.5 : : : : : : : : : 1 1 0 0 0 1 1 1 -49.75 1 1 0 0 1 0 0 0 -50 1 1 0 0 1 1 0 0 -51 1 1 0 1 0 0 0 0 -52 : : : : : : : : : 1 1 1 1 0 0 0 0 -60 1 1 1 1 0 1 0 0 -66 1 1 1 1 1 0 0 0 - 1 1 1 1 1 1 0 0 - VOLUME (dB) : : : : : : : : : 1 1 1 1 1 1 1 1 - 2002 Nov 22 27 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.4 UDA1352TS Sound feature mode, treble and bass boost settings (write) Table 26 Register address 12H BIT 15 14 13 12 11 10 9 8 Symbol M1 M0 TR1 TR0 BB3 BB2 BB1 BB0 Default 0 0 0 0 0 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol - - - - - - - - Default - - - - - - - - Table 27 Description of register bits BIT SYMBOL DESCRIPTION 15 to 14 M[1:0] Sound feature mode. A 2-bit value to program the sound processing filter sets (modes) of bass boost and treble. Default value 00; see Table 28. 13 to 12 TR[1:0] Treble settings. A 2-bit value to program the treble setting. The set is selected by the mode bits. Default value 00; see Table 29. 11 to 8 BB[3:0] Bass boost settings. A 4-bit value to program the bass boost settings. The set is selected by the mode bits. Default value 0000; see Table 30. 7 to 0 - reserved Table 28 Sound feature mode M1 M0 MODE SELECTION 0 0 flat set (default) 0 1 minimum set 1 0 1 1 maximum set Table 29 Treble settings TR1 TR0 FLAT SET (dB) MINIMUM SET (dB) MAXIMUM SET (dB) 0 0 0 0 0 0 1 0 2 2 1 0 0 4 4 1 1 0 6 6 2002 Nov 22 28 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS Table 30 Bass boost settings BB3 BB2 BB1 BB0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 0 0 1 0 0 4 4 0 0 1 1 0 6 6 0 1 0 0 0 8 8 0 1 0 1 0 10 10 0 1 1 0 0 12 12 0 1 1 1 0 14 14 1 0 0 0 0 16 16 1 0 0 1 0 18 18 1 0 1 0 0 18 20 1 0 1 1 0 18 22 1 1 0 0 0 18 24 1 1 0 1 0 18 24 1 1 1 0 0 18 24 1 1 1 1 0 18 24 2002 Nov 22 FLAT SET (dB) MINIMUM SET (dB) MAXIMUM SET (dB) 29 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.5 UDA1352TS Mute (write) Table 31 Register address 13H BIT 15 14 13 12 11 10 9 8 Symbol QMUTE MT GS - - - - - Default 0 1 0 - - 0 0 0 BIT 7 6 5 4 3 2 1 0 Symbol - - - - - - - - Default - - - - - - - - Table 32 Description of register bits BIT SYMBOL DESCRIPTION 15 QMUTE Quick mute function. A 1-bit value to set the quick mute mode. If this bit is logic 0, then the soft mute mode is selected. If this bit is logic 1, then the quick mute mode is selected. Default value 0. 14 MT Mute. A 1-bit value to set the mute function. If this bit is logic 0, then the audio output is not muted (unless pin MUTE is logic 1). If this bit is logic 1, then the audio output is muted. Default value 1. 13 GS Gain select. A 1-bit value to set the gain of the interpolator path. If this bit is logic 0, then the gain is 0 dB. If this bit is logic 1, then the gain is 6 dB. Default value 0. 12 to 11 - reserved 10 to 8 - When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. 7 to 0 - reserved 2002 Nov 22 30 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.6 UDA1352TS Polarity (write) Table 33 Register address 14H BIT 15 14 13 12 11 10 9 8 Symbol DA_POL_ INV - - - - - - - Default 0 1 - - - - 1 0 BIT 7 6 5 4 3 2 1 0 Symbol - - - - - - - - Default 0 - - - - - - - Table 34 Description of register bits BIT SYMBOL DESCRIPTION 15 DA_POL_INV DAC polarity control. A 1-bit value to control the signal polarity of the DAC output signal. If this bit is logic 0, then the DAC output is not inverted. If this bit is logic 1, then the DAC output is inverted. Default value 0. 14 - When writing new settings via the L3-bus or I2C-bus interface, this bit should always remain at logic 1 (default value) to guarantee correct operation. 13 to 10 - reserved 9 - When writing new settings via the L3-bus or I2C-bus interface, this bit should always remain at logic 1 (default value) to guarantee correct operation. 8 to 7 - When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. 6 to 0 - reserved 2002 Nov 22 31 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.7 UDA1352TS SPDIF input settings (write) Table 35 Register address 30H BIT 15 14 13 12 11 10 9 8 Symbol - - - - - - - - Default - - - - - - - - BIT 7 6 5 4 3 2 1 0 Symbol - - - - COMBINE_ PCM BURST_ DET_EN - - Default - - - - 1 1 0 0 Table 36 Description of register bits BIT 15 to 4 SYMBOL - DESCRIPTION reserved 3 COMBINE_PCM Combine PCM detection to lock indicator. A 1-bit value to combine the PCM detection status to the lock indicator. If this bit is logic 0, then the lock indicator does not contain PCM detection status. If this bit is logic 1, then the PCM detection status is combined with the lock indicator. Default value 1. 2 BURST_ DET_EN Burst preamble settings. A 1-bit value to enable auto mute when burst preambles are detected. If this bit is logic 0, then there is no muting. If this bit is logic 1, then there is muting when preambles are detected. Default value 1. - When writing new settings via the L3-bus or I2C-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. 1 to 0 2002 Nov 22 32 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.8 UDA1352TS Interpolator status (read-out) Table 37 Register address 18H BIT 15 14 13 12 11 10 9 8 Symbol - - - - - - - - BIT 7 6 5 4 3 2 1 0 Symbol - - - - - MUTE_ STATE - - Table 38 Description of register bits BIT 15 to 3 2 1 to 0 2002 Nov 22 SYMBOL DESCRIPTION - reserved MUTE_STAT E Mute status bit. A 1-bit value to indicate the status of the mute function. If this bit is logic 0, then the audio output is not muted. If this bit is logic 1, then the mute sequence has been completed and the audio output is muted. - reserved 33 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 12.9 UDA1352TS SPDIF status (read-out) Table 39 Register address 59H BIT 15 14 13 12 11 10 9 8 Symbol - - - - - - - - BIT 7 6 5 4 3 2 1 0 Symbol - - - - - BURST_ DET B_ERR SPDIFIN_ LOCK Table 40 Description of register bits BIT SYMBOL DESCRIPTION - reserved 2 BURST_DET Burst preamble detection. A 1-bit value to signal whether burst preamble words are detected in the SPDIF stream or not. If this bit is logic 0, then no preamble words are detected. If this bit is logic 1, then burst-payload is detected. 1 B_ERR Bit error detection. A 1-bit value to signal whether there are bit errors detected in the SPDIF stream or not. If this bit is logic 0, then no errors are detected. If this bit is logic 1, then bi-phase errors are detected. 0 SPDIFIN_LOCK SPDIF lock indicator. A 1-bit value to signal whether the SPDIF decoder block is in lock or not. If this bit is logic 0, then the decoder block is out-of-lock. If this bit is logic 1, then the decoder block is in lock. 15 to 3 2002 Nov 22 34 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 12.10 Channel status (read-out) 12.10.1 CHANNEL STATUS BITS LEFT [15:0] Table 41 Register address 5AH BIT 15 14 13 12 11 10 9 8 Symbol SPDI_ BIT15 SPDI_ BIT14 SPDI_ BIT13 SPDI_ BIT12 SPDI_ BIT11 SPDI_ BIT10 SPDI_ BIT9 SPDI_ BIT8 BIT 7 6 5 4 3 2 1 0 Symbol SPDI_ BIT7 SPDI_ BIT6 SPDI_ BIT5 SPDI_ BIT4 SPDI_ BIT3 SPDI_ BIT2 SPDI_ BIT1 SPDI_ BIT0 12.10.2 CHANNEL STATUS BITS LEFT [31:16] Table 42 Register address 5BH BIT 15 14 13 12 11 10 9 8 Symbol SPDI_ BIT31 SPDI_ BIT30 SPDI_ BIT29 SPDI_ BIT28 SPDI_ BIT27 SPDI_ BIT26 SPDI_ BIT25 SPDI_ BIT24 BIT 7 6 5 4 3 2 1 0 Symbol SPDI_ BIT23 SPDI_ BIT22 SPDI_ BIT21 SPDI_ BIT20 SPDI_ BIT19 SPDI_ BIT18 SPDI_ BIT17 SPDI_ BIT16 12.10.3 CHANNEL STATUS BITS LEFT [39:32] Table 43 Register address 5CH BIT 15 14 13 12 11 10 9 8 Symbol - - - - - - - - BIT 7 6 5 4 3 2 1 0 Symbol SPDI_ BIT39 SPDI_ BIT38 SPDI_ BIT37 SPDI_ BIT36 SPDI_ BIT35 SPDI_ BIT34 SPDI_ BIT33 SPDI_ BIT32 12.10.4 CHANNEL STATUS BITS RIGHT [15:0] Table 44 Register address 5DH BIT 15 14 13 12 11 10 9 8 Symbol SPDI_ BIT15 SPDI_ BIT14 SPDI_ BIT13 SPDI_ BIT12 SPDI_ BIT11 SPDI_ BIT10 SPDI_ BIT9 SPDI_ BIT8 BIT 7 6 5 4 3 2 1 0 Symbol SPDI_ BIT7 SPDI_ BIT6 SPDI_ BIT5 SPDI_ BIT4 SPDI_ BIT3 SPDI_ BIT2 SPDI_ BIT1 SPDI_ BIT0 2002 Nov 22 35 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 12.10.5 CHANNEL STATUS BITS RIGHT [31:16] Table 45 Register address 5EH BIT 15 14 13 12 11 10 9 8 Symbol SPDI_ BIT31 SPDI_ BIT30 SPDI_ BIT29 SPDI_ BIT28 SPDI_ BIT27 SPDI_ BIT26 SPDI_ BIT25 SPDI_ BIT24 BIT 7 6 5 4 3 2 1 0 Symbol SPDI_ BIT23 SPDI_ BIT22 SPDI_ BIT21 SPDI_ BIT20 SPDI_ BIT19 SPDI_ BIT18 SPDI_ BIT17 SPDI_ BIT16 12.10.6 CHANNEL STATUS BITS RIGHT [39:32] Table 46 Register address 5FH BIT 15 14 13 12 11 10 9 8 Symbol - - - - - - - - BIT 7 6 5 4 3 2 1 0 Symbol SPDI_ BIT39 SPDI_ BIT38 SPDI_ BIT37 SPDI_ BIT36 SPDI_ BIT35 SPDI_ BIT34 SPDI_ BIT33 SPDI_ BIT32 Table 47 Description of register bits (two times 40 bits indicating the left and right channel status) BIT SYMBOL DESCRIPTION 39 to 36 - reserved but undefined at present 35 to 33 SPDI_BIT[35:33] Word length. A 3-bit value indicating the word length; see Table 48. 32 SPDI_BIT[32] Audio sample word length. A 1-bit value to signal the maximum audio sample word length. If bit 32 is logic 0, then the maximum length is 20 bits. If bit 32 is logic 1, then the maximum length is 24 bits. 31 to 30 SPDI_BIT[31:30] reserved 29 to 28 SPDI_BIT[29:28] Clock accuracy. A 2-bit value indicating the clock accuracy; see Table 49. 27 to 24 SPDI_BIT[27:24] Sample frequency. A 4-bit value indicating the sampling frequency; see Table 50. 23 to 20 SPDI_BIT[23:20] Channel number. A 4-bit value indicating the channel number; see Table 51. 19 to 16 SPDI_BIT[19:16] Source number. A 4-bit value indicating the source number; see Table 52. 15 to 8 SPDI_BIT[15:8] General information. A 8-bit value indicating general information; see Table 53. 7 to 6 SPDI_BIT[7:6] Mode. A 2-bit value indicating mode 0; see Table 54. 5 to 3 SPDI_BIT[5:3] Audio sampling. A 3-bit value indicating the type of audio sampling; see Table 55. 2 SPDI_BIT2 Software copyright. A 1-bit value indicating software for which copyright is asserted or not. If this bit is logic 0, then copyright is asserted. If this bit is logic 1, then no copyright is asserted. 1 SPDI_BIT1 Audio sample word. A 1-bit value indicating the type of audio sample word. If this bit is logic 0, then the audio sample word represents linear PCM samples. If this bit is logic 1, then the audio sample word is used for other purposes. 0 SPDI_BIT0 Channel status. A 1-bit value indicating the consumer use of the status block. This bit is logic 0. 2002 Nov 22 36 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS Table 48 Word length WORD LENGTH SPDI_BIT35 SPDI_BIT34 SPDI_BIT33 SPDI_BIT32 = 0 SPDI_BIT32 = 1 0 0 0 word length not indicated (default) word length not indicated (default) 0 0 1 16 bits 20 bits 0 1 0 18 bits 22 bits 0 1 1 reserved reserved 1 0 0 19 bits 23 bits 1 0 1 20 bits 24 bits 1 1 0 17 bits 21 bits 1 1 1 reserved reserved Table 49 Clock accuracy SPDI_BIT29 SPDI_BIT28 CLOCK ACCURACY 0 0 level II 0 1 level I 1 0 level III 1 1 reserved Table 50 Sampling frequency SPDI_BIT27 SPDI_BIT26 SPDI_BIT25 SPDI_BIT24 SAMPLING FREQUENCY 0 0 0 0 44.1 kHz 0 0 0 1 48 kHz 0 0 1 0 32 kHz other states reserved : : : : 1 1 1 1 Table 51 Channel number SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20 CHANNEL NUMBER 0 0 0 0 don't care 0 0 0 1 A (left for stereo transmission) 0 0 1 0 B (right for stereo transmission) 0 0 1 1 C 0 1 0 0 D 0 1 0 1 E 0 1 1 0 F 0 1 1 1 G 1 0 0 0 H 1 0 0 1 I 1 0 1 0 J 1 0 1 1 K 2002 Nov 22 37 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS SPDI_BIT23 SPDI_BIT22 SPDI_BIT21 SPDI_BIT20 CHANNEL NUMBER 1 1 0 0 L 1 1 0 1 M 1 1 1 0 N 1 1 1 1 O Table 52 Source number SPDI_BIT19 SPDI_BIT18 SPDI_BIT17 SPDI_BIT16 SOURCE NUMBER 0 0 0 0 don't care 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 2002 Nov 22 38 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS Table 53 General information SPDI_BIT[15:8] FUNCTION 000 00000 general 100 xxxxL laser optical products 010 xxxxL digital-to-digital converters and signal processing products 110 xxxxL magnetic tape or disc based products 001 xxxxL broadcast reception of digitally encoded audio signals with video signals 011 1xxxL broadcast reception of digitally encoded audio signals without video signals 101 xxxxL musical instruments, microphones and other sources without copyright information 011 00xxL analog-to-digital converters for analog signals without copyright information 011 01xxL analog-to-digital converters for analog signals which include copyright information in the form of `Cp- and L-bit status' 000 1xxxL solid state memory based products 000 0001L experimental products not for commercial sale 111 xxxxL reserved 000 0xxxL reserved, except 000 0000 and 000 0001L Table 54 Mode SPDI_BIT7 SPDI_BIT6 MODE 0 0 mode 0 0 1 reserved 1 0 1 1 Table 55 Audio sampling AUDIO SAMPLE SPDI_BIT5 SPDI_BIT4 SPDI_BIT3 SPDI_BIT1 = 0 SPDI_BIT1 = 1 0 0 0 2 audio samples without pre-emphasis default state for applications other than linear PCM 0 0 1 2 audio samples with 50/15 s pre-emphasis other states reserved 0 1 0 reserved (2 audio samples with pre-emphasis) 0 1 1 reserved (2 audio samples with pre-emphasis) : : : other states reserved 1 1 1 2002 Nov 22 39 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 12.11 FPLL status (read-out) Table 56 Register address 68H BIT 15 14 13 12 11 10 9 8 Symbol - - - - - - - FPLL_ LOCK BIT 7 6 5 4 3 2 1 0 Symbol - - - VCO_ TIMEOUT - - - - Table 57 Description of register bits BIT SYMBOL DESCRIPTION 15 to 9 - reserved 8 FPLL_LOCK FPLL lock. A 1-bit value that indicates the FPLL status together with bit 4; see Table 58. 7 to 5 - reserved 4 VCO_TIMEOUT VCO time-out. A 1-bit value that indicates the FPLL status together with bit 8; see Table 58. 3 to 0 - reserved Table 58 Lock status indicators of the FPLL 2002 Nov 22 FPLL_LOCK VCO_TIMEOUT 0 0 FPLL out-of-lock 0 1 FPLL time-out 1 0 FPLL in lock 1 1 FPLL time-out 40 FUNCTION NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 13 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER VDD supply voltage Tstg CONDITIONS MIN. note 1 MAX. UNIT 2.7 5.0 V storage temperature -65 +125 C Tamb ambient temperature -40 +85 C Vesd electrostatic discharge voltage Human Body Model (HBM); note 2 -2000 +2000 V Machine Model (MM); note 3 -200 +200 V - 200 mA output short-circuited to VSSA(DAC) - 20 mA output short-circuited to VDDA(DAC) - 100 mA Ilu(prot) latch-up protection current Tamb = 125 C; VDD = 3.6 V Isc(DAC) short-circuit current of DAC Tamb = 0 C; VDD = 3 V; note 4 Notes 1. All VDD and VSS connections must be made to the same power supply. 2. JEDEC class 2 compliant. 3. JEDEC class B compliant. 4. DAC operation after short-circuiting cannot be warranted. 14 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 110 K/W 15 CHARACTERISTICS VDDD = VDDA = 3.0 V; IEC 60958 input with fs = 48.0 kHz; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies; note 1 VDDA analog supply voltage 2.7 3.0 3.6 V VDDA(DAC) analog supply voltage for DAC 2.7 3.0 3.6 V VDDA(PLL) analog supply voltage for PLL 2.7 3.0 3.6 V VDDD digital supply voltage 2.7 3.0 3.6 V VDDD(C) digital supply voltage for core 2.7 3.0 3.6 V IDDA(DAC) analog supply current of DAC power-on - 3.3 - mA power-down; clock off - 35 - A IDDA(PLL) analog supply current of PLL - 0.3 - mA IDDD(C) digital supply current of core - 9 - mA IDDD digital supply current P power dissipation 2002 Nov 22 - 0.3 - mA - 38 - mW DAC in Power-down mode - tbf - mW DAC in playback mode 41 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC SYMBOL PARAMETER UDA1352TS CONDITIONS MIN. TYP. MAX. UNIT Digital inputs VIH HIGH-level input voltage 0.8VDDD - VDDD + 0.5 V VIL LOW-level input voltage -0.5 - +0.2VDDD V ILI input leakage current - - 10 A Ci input capacitance - - 10 pF Rpu(int) internal pull-up resistance 16 33 78 k Rpd(int) internal pull-down resistance 16 33 78 k Digital outputs VOH HIGH-level output voltage IOH = -2 mA 0.85VDDD - - V VOL LOW-level output voltage IOL = 2 mA - - 0.4 V IO(max) maximum output current - 3 - mA Digital-to-analog converter; note 2 Vo(rms) output voltage (RMS value) fi = 1.0 kHz tone at 0 dBFS; note 3 850 900 950 mV Vo unbalance of output voltages fi = 1.0 kHz tone - 0.1 0.4 dB Vref reference voltage measured with respect to VSSA 0.45VDDA 0.50VDDA 0.55VDDA V (THD+N)/S total harmonic distortion-plus-noise to signal ratio fi = 1.0 kHz tone - -82 -77 dB at -40 dBFS; A-weighted - -60 -52 dB S/N signal-to-noise ratio fi = 1.0 kHz tone; code = 0; 95 A-weighted 100 - dB cs channel separation fi = 1.0 kHz tone - 110 - dB at 0 dBFS SPDIF input Vi(p-p) AC input voltage (peak-to-peak value) 0.2 0.5 3.3 V Ri input resistance - 6 - k Vhys hysteresis voltage - 40 - mV Notes 1. All supply pins VDD and VSS must be connected to the same external power supply unit. 2. When the DAC must drive a higher capacitive load (above 50 pF), a series resistor of 100 must be used to prevent oscillations in the output stage of the operational amplifier. 3. The output voltage of the DAC is proportional to the DAC power supply voltage. 2002 Nov 22 42 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 16 TIMING CHARACTERISTICS VDDD = VDDA = 2.4 to 3.6 V; Tamb = -40 to +85 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Device reset trst - 250 - s fs = 32.0 kHz - 85.0 - ms fs = 44.1 kHz - 63.0 - ms fs = 48.0 kHz - 60.0 - ms reset active time PLL lock time tlock time-to-lock L3-bus microcontroller interface; see Figs 15 and 16 Tcy(CLK)(L3) L3CLOCK cycle time 500 - - ns tCLK(L3)H L3CLOCK HIGH time 250 - - ns tCLK(L3)L L3CLOCK LOW time 250 - - ns tsu(L3)A L3MODE set-up time in address mode 190 - - ns th(L3)A L3MODE hold time in address mode 190 - - ns tsu(L3)D L3MODE set-up time in data transfer mode 190 - - ns th(L3)D L3MODE hold time in data transfer mode 190 - - ns t(stp)(L3) L3MODE stop time in data transfer mode 190 - - ns tsu(L3)DA L3DATA set-up time in address and data transfer mode 190 - - ns th(L3)DA L3DATA hold time in address and data transfer mode 30 - - ns td(L3)R L3DATA delay time in data transfer mode 0 - 50 ns tdis(L3)R L3DATA disable time for read data 0 - 50 ns I2C-bus microcontroller interface; see Fig 17 fSCL SCL clock frequency 0 - 400 kHz tLOW SCL LOW time 1.3 - - s tHIGH SCL HIGH time 0.6 - - s tr rise time SDA and SCL note 1 20 + 0.1Cb - 300 ns tf fall time SDA and SCL note 1 20 + 0.1Cb - 300 ns tHD;STA hold time start condition 0.6 - - s tSU;STA set-up time START condition 0.6 - - s tSU;STO set-up time STOP condition 0.6 - - s tBUF bus free time between a STOP and START condition 1.3 - - s 2002 Nov 22 43 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC SYMBOL UDA1352TS PARAMETER CONDITIONS MIN. TYP. MAX. - - ns 0 - - s 0 - 50 ns - 400 pF tSU;DAT data set-up time 100 tHD;DAT data hold time tSP pulse width of spikes to be suppressed by the input filter Cb capacitive load for each bus line Note 1. Cb is the total capacity of one bus line. handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tCLK(L3)L tsu(L3)A tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA L3DATA th(L3)DA BIT 0 BIT 7 MGL723 Fig.15 Timing for address mode. 2002 Nov 22 44 UNIT NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS tstp(L3) handbook, full pagewidth L3MODE tCLK(L3)L Tcy(CLK)L3 tCLK(L3)H tsu(L3)D th(L3)D L3CLOCK th(L3)DA L3DATA write tsu(L3)DA BIT 0 BIT 7 L3DATA read td(L3)R tdis(L3)R MBL566 Fig.16 Timing for data transfer mode. handbook, full pagewidth SDA tLOW tf tr tSU;DAT tf tHD;STA tSP tr tBUF SCL S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S MSC610 Fig.17 Timing of the I2C-bus transfer. 2002 Nov 22 45 S7 C3 100 nF (50 V) C2 100 F (16 V) VSSA(PLL) L3 BLM31A601S VDDA(DAC) VDDA C12 100 F (16 V) VDDD C13 100 nF (50 V) VSSA(DAC) L3CLOCK L3MODE L3DATA 14 23 VDDA(PLL) 24 RST NORM n.c. n.c. n.c. 21 22 27 RESET TEST2 18 1 2 3 5 19 C7 46 R10 75 15 9 BLM31A601S 10 8 13 6 11 VDDD C10 100 F (16 V) C11 100 nF (50 V) VSSD C20 100 F (16 V) C21 100 F (16 V) VDDD left_out R6 10 k X3 R7 right_out 100 R8 10 k 1 2 3 S2 mute no mute VDDD SELSTATIC 1 2 3 S1 STATIC L3-bus or I2C-bus S4 3 7 4 1 +3 V MUTE X2 R5 100 C18 C5 VSSD(C) 100 nF 12 (50 V) R4 1 VOUTR 47 F (16 V) 26 VDDD C17 UDA1352TS VDDD(C) C4 100 F (16 V) VOUTL 47 F (16 V) 10 nF (50 V) C6 180 pF (50 V) L2 VDDD SPDIF C14 10 F (16 V) C15 100 nF (50 V) 20 17 X1 Vref 16 28 VDDA PCMDET LOCK VDDD R9 1 k R3 1 k D2 D1 HLMP-1385 (2x) VDDD 1 2 3 I2C-bus L3-bus 25 DA1 VDDD VDDD 1 2 3 1 2 3 S5 S6 1 0 handbook, full pagewidth UDA1352TS MGU657 Fig.18 Application diagram. 1 0 Preliminary specification GND DA0 SELIIC NXP Semiconductors BLM31A601S 48 kHz IEC 60958 audio DAC 17 APPLICATION INFORMATION 2002 Nov 22 L1 VDDA NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 18 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 pin 1 index A (A 3) A1 Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT341-1 2002 Nov 22 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 47 o NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 19 SOLDERING 19.1 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. 19.2 The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 19.3 19.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Nov 22 Manual soldering 48 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC 19.5 UDA1352TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your NXP Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Nov 22 49 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS 20 DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 21 DISCLAIMERS property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2002 Nov 22 50 NXP Semiconductors Preliminary specification 48 kHz IEC 60958 audio DAC UDA1352TS Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 2002 Nov 22 22 TRADEMARKS I2C-bus logo is a trademark of NXP B.V. 51 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: salesaddresses@nxp.com (c) NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/02/pp52 Date of release: 2002 Nov 22 Document order number: 9397 750 10469