AD408M96VSA-5 - ASCEND Semiconductor

Rev.1 Page 1

ASCEND

Semiconductor

4Mx4 EDO

Data sheet

Rev.1 Page 2

AD 40 4M 4 2 V S A – 5

Ascend

Semiconductor

EDO/FPM : 40

D-RAMBUS : 41

DDRSDRAM : 42

DDRSGRAM : 43

SGRAM : 46

SDRAM : 48

Density

16M : 16 Mega Bits

8M : 8 Mega Bits

4M : 4 Mega Bits

2M : 2 Mega Bits

1M : 1 Mega Bit

Package

Organization

4: x4

8 : x8

9 : x9

16 : x16

18 : x18

32 : x32

Revision

A : 1st B : 2nd

C : 3rd D :4th

Min Cycle Time ( Max Freq.)

-5 : 5ns ( 200MHz )

-6 : 6ns ( 167MHz )

-7 : 7ns ( 143MHz )

-75 : 7.5ns ( 133MHz )

-8 : 8ns ( 125MHz )

-10 : 10ns ( 100MHz )

EDO : -5 (50 ns)

-6 (60 ns)

Interface

V: 3.3V

R: 2.5V

C: CSP B: uBGA

T: TSOP Q: TQFP

P: PQFP ( QFP )

L: LQFP S: SOJ

Refresh

1 : 1K 8 : 8K

2 : 2K 6 :16K

4 : 4K

Rev.1 Page 3

Description

The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access

mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single

3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable elec-

tronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II).

Features

• Single 3.3V(%) only power supply

• High speed tRAC acess time: 50/60ns

• Low power dissipation

- Active mode : 432/396 mW (Mas)

- Standby mode: 0.54 mW (Mas)

• Extended - data - out(EDO) page mode access

• I/O level: CMOS level (Vcc = 3.3V)

• 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version)

• 4 refresh modesh:

- RAS only refresh

- CAS - before - RAS refresh

- Hidden refresh

- Self-refresh(S-version)

10±

Rev.1 Page 4

Pin Name Function

A0-A10 Address inputs

- Row address

- Column address

- Refresh address

DQ1~DQ4 Data-in / data-out

RAS Row address strobe

CAS Column address strobe

WE Write enable

OE Output enable

Vcc Power (+ 3.3V)

Vss Ground

VCC 1

DQ1 2

DQ2 3DQ3

4

DQ4

5

VCC

6

8

9

10

11

NC

12

WE

13

A0

A1 17

A2

18

A3

19

VSS

RAS CAS

OE

A8

A7

A6

A5

A4

VSS

AD404M42VS

Pin Description

Pin Configuration

21

22

23

24

25

26

15

14

16

A10

26/24-PIN 300mil Plastic SOJ

A9

VCC 1

DQ1 2

DQ2 3DQ3

4

DQ4

5

VCC

6

8

9

10

11

NC

12

WE

13

A0

A1 17

A2

18

A3

19

VSS

RAS CAS

OE

A8

A7

A6

A5

A4

VSS

AD404M42VT

21

22

23

24

25

26

15

14

16

A10

26/24-PIN 300mil Plastic TSOP (ll)

A9

A0-A10

Rev.1 Page 5

WE

CAS

NO. 2 CLOCK

GENERATOR

COLUMN

ADDRESS

BUFFERS (11)

REFRESH

CONTROLLER

REFRESH

COUNTER

BUFFERS (11)

ADDRESS

ROW

NO. 1 CLOCK

GENERATOR

A0

RAS

A1

A2

A3

A4

A5

A6

A7

A8

CONTROL

LOGIC DATA-IN BUFFER

DATA-OUT

BUFFER OE

DQ1

.

DQ4

.

COLUMN

DECODER

2048

SENSE AMPLIFIERS

I/O GATING

2048x4

2048x2048x4

MEMORY

ARRAY

2048

ROW

DECODER

Vcc

Vss

Block Diagram

A9

A10

Rev.1 Page 6

TRUTH TABLE

Notes: 1. EARLY WRITE only.

FUNCTION RAS CAS WE OE

ADDRESSES

DQSNotes

ROW COL

STANDBY HX X X X High-Z

READ L L HLROW COL Data-Out

WRITE: (EARLY WRITE ) L L L XROW COL Data-ln

READ WRITE L L ROW COL Data-Out,Data-ln

EDO-PAGE-

MODE READ 1st Cycle LHLROW COL Data-Out

2nd Cycle LHLn/a COL Data-Out

EDO-PAGE

MODE WRITE 1st Cycle L L XROW COL Data-In

2nd Cycle L L Xn/a COL Data-In

EDO-

PAGE-MODE

READ-WRITE

1st Cycle LROW COL Data-Out, Data-In

2nd Cycle Ln/a COL Data-Out, Data-In

HIDDEN

REFRESH READ LHLROW COL Data-Out

WRITE L L XROW COL Data-In 1

RAS-ONLY REFRESH LHX X ROW n/a High-Z

CBR REFRESH LHXXXHigh-Z

HX→

HL→

LH→

HL→

LH

→

HL→

LH

→

LHL→→

HL→

Rev.1 Page 7

Absolute Maximum Ratings

Recommended DC Operating Conditions

Capacitance

Ta = 25°C, VCC = 3.3V %, f = 1MHz

Note: 1. Capacitance measured with effective capacitance measuring method.

2. RAS, CAS = VIH to disable Dout.

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VT-0.5 to + 4.6 V

Supply voltage relative to Vss VCC -0.5 to + 4.6 V

Short circuit output current IOUT 50 mA

Power dissipation PD1.0 W

Operating temperature TOPT 0 to + 70 °C

Storage temperature TSTG -55 to + 125 °C

Parameter/Condition Symbol 3.3 Volt Version Unit

Min Typ Max

Supply Voltage VCC 3.0 3.3 3.6 V

Input High Voltage, all inputs VIH 2.0 -VCC + 0.3 V

Input Low Voltage, all inputs VIL -0.3 -0.8 V

Parameter Symbol Typ Max Unit Note

Input capacitance (Address) CI1 - 5pF 1

Input capacitance (RAS, CAS, OE, WE)CI2 -7pF 1

Output capacitance

(Data-in, Data-out) CI/O -7pF 1, 2

10±

Rev.1 Page 8

DC Characteristics :

(Ta = 0 to 70°C, VCC = + 3.3V %, VSS = 0V)

Parameter Symbol Test Conditions AD404M42V Unit Notes

-5 -6

Min Max Min Max

Operating current ICC1 RAS cycling

CAS, cycling

tRC = min

-120 -110 mA 1, 2

Standby

Current

Low

power

S-version

ICC2 LVTTL interface

RAS, CAS = VIH

Dout = High-Z

-0.5 -0.5 mA

CMOS interface

RAS, -0.2V

Dout = High-Z

-0.15 -0.15 mA

Standard

power

version

LVTTL interface

RAS, CAS = VIH

Dout = High-Z

-2-2mA

CMOS interface

RAS,-0.2V

Dout = High-Z

-0.5 -0.5 mA

RAS- only refresh current ICC3 RAS cycling, CAS = VIH

tRC = min -120 -110 mA 1, 2

EDO page mode current ICC4 tPC = min -90 -80 mA 1, 3

CAS- before- RAS refresh

current ICC5 tRC = min

RAS, CAS cycling -120 -110 mA 1, 2

Self- refresh current

(S-Version) ICC8

- 550 - 550

10±

CASVCC

≥

CASVCC

≥

t

RASS

100

µ

s

≥

µA

Rev.1 Page 9

DC Characteristics :

(Ta = 0 to 70°C, VCC= +3.3V %, VSS= 0V)

Notes:

1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the

device is selected. ICC max is specified at the output open condition.

2. Address can be changed once or less while RAS = VIL.

3. For ICC4, address can be changed once or less within one EDO page mode cycle time.

Parameter Symbol Test Conditions

AD404M42V Unit Notes

-5 -6

Min Max Min Max

Input leakage current ILI + 0.3V -5 5-5 5

Output leakage current ILO + 0.3V

Dout = Disable

-5 5-5 5

Output high Voltage VOH IOH = -2mA 2.4 -2.4 -V

Output low voltage VOL IOL = +2mA -0.4 -0.4 V

10±

0VVinV

CC

≤≤

µA

0VVoutV

CC

≤≤

µA

Rev.1 Page 10

AC Characteristics

(Ta = 0 to + 70°C, Vcc = 3.3V %, Vss = 0V) *1, *2, *3, *4

Test conditions

• Output load: one TTL Load and 100pF (VCC = 3.3V %)

• Input timing reference levels:

VIH = 2.0V, VIL = 0.8V (VCC = 3.3V %)

• Output timing reference levels:

VOH = 2.0V, VOL = 0.8V

10±

Read, Write, Read- Modify- Write and Refresh Cycles

(Common Parameters)

Parameter Symbol

AD404M42V Unit Notes

-5 -6

Min Max Min Max

Random read or write cycle time tRC 84 -104 -ns

RAS precharge time tRP 30 -40 -ns

CAS precharge time in normal mode tCPN 10 -10 -ns

RAS pulse width tRAS 50 10000 60 10000 ns 5

CAS pulse width tCAS 8 10000 10 10000 ns 6

Row address setup time tASR 0-0-ns

Row address hold time tRAH 8-10 -ns

Column address setup time tASC 0-0-ns 7

Column address hold time tCAH 8-10 -ns

RAS to CAS delay time tRCD 12 37 14 45 ns 8

RAS to column address delay time tRAD 10 25 12 30 ns 9

Column address to RAS lead time tRAL 25 -30 -ns

RAS hold time tRSH 8-10 -ns

CAS hold time tCSH 38 -40 -ns

CAS to RAS precharge time tCRP 5-5-ns 10

OE to Din delay time tOED 12 -15 -ns

Transition time (rise and fall) tT1 50 1 50 ns 11

Refresh period tREF -32 -32 ms

Refresh period (S- Version) tREF -128 -128 ms

CAS to output in Low- Z tCLZ 0-0-ns

CAS delay time from Din tDZC 0-0-ns

OE delay time from Din tDZO 0-0-ns

Rev.1 Page 11

Read Cycle

Write Cycle

Parameter Symbol

AD404M42V Unit Notes

-5 -6

Min Max Min Max

Access time from RAS tRAC -50 -60 ns 12

Access time from CAS tCAC -14 -15 ns 13, 14

Access time from column address tAA -25 -30 ns 14, 15

Access time from OE tOEA -12 -15 ns

Read command setup time tRCS 0-0-ns 7

Read command hold time to CAS tRCH 0-0-ns 10, 16

Read command hold time to RAS tRRH 0-0-ns 16

Output buffer turn-off time tOFF 0 12 0 15 ns 17

Output buffer turn-off time from OE tOEZ 0 12 0 15 ns 17

Parameter Symbol

AD404M42V Unit Notes

-5 -6

Min Max Min Max

Write command setup time tWCS 0-0-ns 7, 18

Write command hold time tWCH 8-10 -ns

Write command pulse width tWP 8-10 -ns

Write command to RAS lead time tRWL 13 -15 -ns

Write command to CAS lead time tCWL 8-10 -ns

Data-in setup time tDS 0-0-ns 19

Data-in hold time tDH 8-10 -ns 19

WE to Data-in delay tWED 10 -10 -ns

Rev.1 Page 12

Read- Modify- Write Cycle

Refresh Cycle

Parameter Symbol

AD404M42V Unit Notes

-5 -6

Min Max Min Max

Read-modify- write cycle time tRWC 108 -133 -ns

RAS to WE delay time tRWD 64 -77 -ns 18

CAS to WE dealy time tCWD 26 -32 -ns 18

Column address to WE delay time tAWD 39 -47 -ns 18

OE hold time from WE tOEH 8-10 -ns

Parameter Symbol

AD404M42V

Unit Notes

-5 -6

Min Max Min Max

CAS setup time (CBR refresh) tCSR 5-5-ns

CAS hold time (CBR refresh) tCHR 8-10 -ns 10

RAS precharge to CAS hold time tRPC 5-5-ns 7

RAS pulse width (self refresh) tRASS 100 -100 -

RAS precharge time (self refresh) tRPS 90 -110 -ns

CAS hold time (CBR self refresh) tCHS -50 --50 -ns

WE setup time tWSR 0-0-ns

WE hold time tWHR 10 -10 -ns

µs

Rev.1 Page 13

EDO Page Mode Cycle

EDO Page Mode Read Modify Write Cycle

Parameter Symbol

AD404M42V

Unit Notes

-5 -6

Min Max Min Max

EDO page mode cycle time tPC 20 -25 -ns

EDO page mode CAS precharge time tCP 10 -10 -ns

EDO page mode RAS pulse width tRASP 50 10560 105ns 20

Access time from CAS precharge tCPA -30 -35 ns 10, 14

RAS hold time from CAS precharge tCPRH 30 -35 -ns

OE high hold time from CAS high tOEHC 5-5-ns

OE high pulse width tOEP 10 -10 -ns

Data output hold time after CAS low tCOH 5-5-ns

Output disable delay from WE tWHZ 3 10 3 10 ns

WE pulse width for output disable when

CAS high tWPZ 7-7-ns

Parameter Symbol

AD404M42V

Unit Notes

-5 -6

Min Max Min Max

EDO page mode read- modify- write cycle

CAS precharge to WE delay time tCPW 45 -55 -ns 10

EDO page mode read- modify- write cycle

time tPRWC 56 -68 -ns

Rev.1 Page 14

Notes :

1. AC measurements assume tT = 2ns.

2. An initial pause of 100 is required after power up, and it followed by a minimum of eight

initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal

refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required.

3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to

the device.

4. All the VCC and VSS pins shall be supplied with the same voltages.

5. tRAS(min) = tRWD(min)+tRWL(min)+tT in read-modify-write cycle.

6. tCAS(min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle.

7. tASC(min), tRCS(min), tWCS(min), and tRPC are determined by the falling edge of CAS .

8. tRCD(max) is specified as a reference point only, and tRAC(max) can be met with the tRCD(max) limit.

Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit.

9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit.

Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit.

10. tCRP, tCHR, tRCH, tCPA and tCPW are determined by the rising edge of CAS .

11. VIH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition

time is measured between VIH and VIL.

12. Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum

recommended value shown in this table, tRAC exceeds the value shown.

13. Assumes that (max) and(max).

14. Access time is determined by the maximum of tAA, tCAC, tCPA.

15. Assumes that (max) and (max).

16. Either tRCH or tRRH must be satisfied for a read cycle.

17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high

impedance). tOFF is determined by the later rising edge of RAS or CAS.

18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data

sheet as electrical characteristics only. If (min), the cycle is an early write cycle and the

data out will remain open circuit (high impedance) throughout the entire cycle. If (min),

(min), (min) and (min), the cycle is a read-modify-write and

the data output will contain data read from the selected cell. If neither of the above sets of conditions

is satisfied, the condition of the data output (at access time) is indeterminate.

19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a

delayed write or a read-modify-write cycle.

20. tRASP defines RAS pulse width in EDO page mode cycles.

µs

≤

t

RCD

t

RCD

≥

tRADtRAD

≤

t

RCD

t

RCD

≤

tRADtRAD

≥

t

WCS

t

WCS

≥

tRWDtRWD

≥

tCWDtCWD

≥

tAWDtAWD

≥

tCPWtCPW

≥

Rev.1 Page 15

Timing Waveforms

• Read Cycle

tRC

tRAS tRP

tCRP

tCPN

tRRH

tRCH

tOEZ

tOFF

tOEA

tCAC

tAA

tRAC

tCLZ

D

OUT

tRCS

tASR tRAH tASC tCAH

tRAD tRAL

tCAS

tRSH

tRCD

tT

tCSH

RAS

CAS

ADDRESS

WE

DQ1~DQ4

Note : = don’t care

OE

tOFF

Row Column

= Invalid Dout

Rev.1 Page 16

•Early Write Cycle

tRC

tRAS tRP

tWCH

tDS tDH

tWCS

tRAL

tCAS

tRSH

tRCD

tT

tCSH

RAS

CAS

WE

DQ1~DQ4

tCRP

tASR tRAH tASC tCAH

ADDRESS Column

Row

tCPN

DIN

tRAD tRAL

Rev.1 Page 17

• Delayed Write Cycle

tRC

tRAS tRP

tRWL

tRCS

tCAS

tRSH

tRCD

tT

tCSH

RAS

CAS

tASR tRAH tCAH

ADDRESS Column

Row

tASC

DIN

DQ1~DQ4

WE

tCRP

tCPN

tDH

tDS

tOEH

tOED

OE

tDS

OPEN

tWP

tCWL

Rev.1 Page 18

• Read - Modify - Write Cycle

tRWC

tRAS tRP

tRWD tWP

tRAD

tRWL

tCAS

tCWL

tRCD

tT

tCPN

RAS

CAS

WE

tCRP

tASR tRAH tASC tCAH

ADDRESS Column

Row

DQ1~DQ4

tDH

tDS

OE

tRCS tAWD

tCWD

DIN

tOED tOEH

tOEZ

tOEA

tCAC

tRAC tAA

DQ1~DQ4 DOUT

OPEN

tDZC

tDZO

Rev.1 Page 19

• EDO Page Mode Read Cycle

tRASP tCPRH

tRCS

tCAS

tRSH

tRCD

tOEA

tCSH

RAS

CAS

tASR tRAH tCAH

ADDRESS

tCAS

WE

tCRP tCP

OE

DQ1~DQ4 OPEN

tOEP

DOUT 1

tPC

tCP tCAS tCPN

tCRP

tRAD

tCAH

tASC tASC tCAH tASC

tRAL

Row Column 1

tOEA

tOEHC

tRRH

tRCH

tRAC

tAA tAA tAA

tCPA tCPA tOEZ

tOFF

tCAC

tOEZ

tCAC

tCOH

DOUT N

WE

OE

Column 2 Column N Row

tRP

DOUT 2

Rev.1 Page 20

• EDO Page Mode Early Write Cycle

tRASP tRP

tWCS

tCAS

tRSH

tRCD

RAS

CAS

tASR tRAH tCAH

ADDRESS

tCAS

WE

tCP

DQ1~DQ4

tPC

tCP tCAS tCPN

tCRP

tCAH

tASC tASC tCAH tASC

Row Column 1

tDS

WE

Column 2 Column N

tWCH tWCS tWCH tWCS tWCH

tDH tDS tDH tDS tDH

DIN 1DIN 2DIN N

tTtCSH

Rev.1 Page 21

• EDO Page Mode Read-Early-Write Cycle

tRASP

tCPRH

tRCS

tCAS

tRSH

tRCD

tOEA

tCSH

RAS

CAS

tASR tRAH tCAH

ADDRESS

tCAS

WE

tCRP tCP

OE

DQ1~DQ4 OPEN

tWED

tPC

tCP tCAS tCPN

tCRP

tRAD

tRAH

tASC tASC tCAH tASC

tRAL

Row Column 1

tWCS

tRCH

tRAC

tAA tAA

tCPA

tDH

tWHZ

tCAC

tCOH

WE

OE

Column 2 Column N Row

tRP

tCAL

tWCH

Data

Doutput 2

Data

Input N

Data

Doutput 1

tDS

tCSH

Rev.1 Page 22

• EDO Page Mode Read-Modify-Write Cycle

tRASP

tCPRH

tRCS

tCAS

tWP

RAS

CAS

tASR

tRAH tCAH

ADDRESS

tCAS

WE

tRCD CP

DQ1~DQ4

tPRWC

tCP tCAS

tCRP

tRAD

tCAH

tASC tASC

tCAH

tASC

Row Column 1

tRWL

tRCS

tOED

tDZO

tCAC

WE

OE

tRP

tRAL

DOUT 2 DOUT N

DOUT 1

tT

t

Column NColumn 2Column 1

tRWD

tAWD

tCWD

tCWL

tRCS tCWD

tAWD

tCPW tCWL tCPW

tAWD

tCWD

tCWL

tOED tOED

tOEH tOEH tOEH

tCAC

tOEA

tAA

tRAC tOEZ

tOEA

tAA

tCPA tOEZ

tOEA

tAA

tCPA tOEZ

tDS

tDH

tWP

tDS

tDH

tWP

tDS

tDH

OPEN OPEN OPEN

DIN 1 DIN N

DIN 2

DQ1~DQ4

tDZC

tDZO

tDZC tDZC

tDZO

Rev.1 Page 23

• Read Cycle with WE Controlled Disable

tWPZ

tRCS

tCAS

tRCD

tT

tCSH

RAS

CAS

tASR tRAH tCAH

ADDRESS Column

Row

tASC

D

DQ1~DQ4

WE

tOEZ

tDS

tWHZ

OE

tRCH

tOEA

tCAC

tAA

tRAC

tCLZ OUT

tRAD

Rev.1 Page 24

RAS-Only Refresh Cycle

RAS

ADDRESS

tRC

tCRP

tASR tRAH

tT

tRPC

ROW

tOFF

CAS

tRAS tRP

OPEN

tCRP

DQ1~DQ4

RAS

tCSR

tWSR

tRP

tTtRPC

tOFF

CAS

tRAS tRP

OPEN

tCRP

DQ1~DQ4

tRPC

tCHR

tRAS tRP

tRC tRC

tCHR

tCSR

tWHR tWSR tWHR

WE

CAS-Before-RAS Refresh Cycle

Rev.1 Page 25

CBR Self-Refesh Cycle

RAS

WE

tRPC

tOFF

tCSR tCHS

tWSR

CAS

tRASS tRPS

OPEN

DQ1~DQ4

tWHR

High lmpedance

Rev.1 Page 26

• Hidden Refresh Cycle

tRP

tRAS

RAS

tRCD

tCRP

ADDRESS

WE

tCHR

tCAS

tRSH

tRAH

tASR tASC tCAH

tRAL

ROW

tRCH

tOEZ

CAS

DQ1~DQ4

tT

t RCS

D

tRAS

tRAS tRP

tRP

tRC tRC tRC

tRAD

tRRH

tOFF

tOEA

tCAC

tAA

tRAC

COlumn

OUT

OE

(READ) (REFRESH) (REFRESH)

Rev.1 Page 27

Ordering information

AD404M42VSA-5

• AD • Ascend Memory Product

• 40 • Device Type

• 4M4 • Density and Organization

• 2 • Refresh Rate, 2: 2K Refresh

• V • T: 5V, V: 3.3V

• S • Package Type (S : SOJ, T : TSOP II)

• A • Version

• 5 • Speed (5: 50 ns, 6: 60 ns)

Part Number Access time Package

AD404M42VSA-5

AD404M42VSA-6

AD404M42VTA-5

AD404M42VTA-6

50 ns

60 ns

50 ns

60 ns

300mil 26/24-Pin

Plastic SOJ

TSOP II

Packaging information

• 300 mil, 26/24-Pin Plastic SOJ

SEATING PLANE

4-e

e

b

b2

0.007"M

C

L

0.025" MIN.

0.004"

SECTION B-B

E2

A

RAD R1

A1 B

B

D

26 21

E

E1

19 14

BASE METAL

WITH PLATING

c1 c

b1

b

0.267 BASIC

0.335 BASIC

0.050 BASIC

R1

e

E1

E2 6.78 BASIC

1.27 BASIC

0.76 ---

7.49 7.62

1.02 0.030

7.75 0.295

17.02

b

D

E

c1

b2

c

b1

A1

A

DIM

0.510.41 0.016

8.51 BASIC

0.18

17.15

---

0.66

0.18

0.41 ---

---

0.46

17.27

0.28

0.670

0.007

0.81

0.30

0.48

0.007

0.026

0.016

MILLIMETERS

MIN. NOM.

2.08

3.25 ---

---

3.51

MAX. MIN.

---

3.76 0.082

0.128

0.305

0.040---

0.300

0.020

0.032

0.019

0.012

0.680

0.011

0.675

---

0.018

---

MAX.

0.148

---

NOM.

---

0.138

---

INCHES

2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.

DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.

MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE.

INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE.

1. CONTROLLING DIMENSION : INCHES

NOTE:

3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR

TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN.

DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH

SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm)

INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE

1 6 8 13

A2

A2 2.54 REF. 0.100 REF.

Rev.1 Page 28

• 300 mil, 26/24-Pin TSOP II

D

(ZD)

bM

REF.

4-1.27

6 81

26 1921

RAD R1

A2

E

E1

SEATING PLANE

0.100(0.004")

e

A

RAD R

A1 L

DETAIL A

13

DETAIL A

0 ~5

Bc

B

14

bSECTION B-B

BASE METAL

WITH PLATING

b1

c

c1

0.0240.0200.60 0.0160.40 0.50L

0.12

R

R1 ------

--- 0.25 0.005

0.005 ---

0.010

---

0.0374 BASIC

0.050 BASIC

0.16 0.005c1 0.12 0.15

17.01

9.02

7.49

e

E1

E

D

ZD

1.27 BASIC

7.62

9.22

7.75

9.42 0.355

0.295

17.2717.14

0.95 REF.

0.670

0.95

0.05

0.12

0.30

c

b1

A2

A1

b

---

0.40

0.21

0.45

0.005

0.012

1.00

---

1.05

0.15

0.037

0.002

0.012

0.52

(0.006)

0.006

0.305

0.371

0.300

0.363

0.680

0.675

0.008

0.018

---

0.016

0.041

0.006

0.020

0.039

---

---A

DIM MIN.

---

NOM.

MILLIMETERS

1.20

MAX.

---

MIN.

0.047

MAX.

---

INCHES

NOM.

0.200(0.008")

ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO

3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION.

INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE.

MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE.

2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION.

1. CONTROLLING DIMENSION : MILLIMETERS

NOTE:

THAN THE MIN b DIMENSION BY MORE THAN 0.07mm.

DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER

BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm.

DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION.