ASCEND Semiconductor 4Mx4 EDO Data sheet Rev.1 Page 1 AD 40 4M 4 2 V S A - 5 Ascend Semiconductor EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : 40 41 42 43 46 48 Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) Organization 4: x4 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K 8 : 8K 2 : 2K 6 :16K 4 : 4K EDO : -5 (50 ns) -6 (60 ns) Revision A : 1st B : 2nd C : 3rd D :4th Interface V: 3.3V R: 2.5V Package C: CSP B: uBGA T: TSOP Q: TQFP P: PQFP ( QFP ) L: LQFP S: SOJ Rev.1 Page 2 Description The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. lt is packaged in JEDEC standard 26/24-pin plastic SOJ or TSOP(II). Features * Single 3.3V( 10 %) only power supply * High speed tRAC acess time: 50/60ns * Low power dissipation - Active mode : 432/396 mW (Mas) - Standby mode: 0.54 mW (Mas) * Extended - data - out(EDO) page mode access * I/O level: CMOS level (Vcc = 3.3V) * 2048 refresh cycle in 32 ms(Std.) or 128 ms(S-version) * 4 refresh modesh: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh(S-version) Rev.1 Page 3 Pin Configuration 26/24-PIN 300mil Plastic SOJ VCC DQ1 1 4 5 NC 6 A10 8 A0 A1 9 A2 11 A3 12 13 VCC 25 24 DQ4 DQ3 21 CAS OE A9 19 23 22 18 17 16 15 10 VSS 14 VCC 1 26 VSS DQ1 2 3 25 DQ4 DQ3 DQ2 WE RAS 4 5 NC 6 A8 A10 8 A7 A6 A5 A0 A1 9 A2 11 A4 A3 12 13 VCC VSS 10 AD404M42VT 2 3 26 AD404M42VS DQ2 WE RAS 26/24-PIN 300mil Plastic TSOP (ll) 24 21 CAS OE A9 19 A8 18 17 16 15 14 A7 A6 23 22 Pin Description Pin Name A0-A10 Function Address inputs - Row address - Column address - Refresh address DQ1~DQ4 Data-in / data-out RAS Row address strobe CAS Column address strobe WE Write enable OE Output enable Vcc Power (+ 3.3V) Vss Ground A0-A10 A0-A10 A0-A10 Rev.1 Page 4 A5 A4 VSS Block Diagram WE CONTROL LOGIC CAS DATA-IN BUFFER DQ1 . . DQ4 NO. 2 CLOCK GENERATOR DATA-OUT BUFFER OE COLUMN ADDRESS BUFFERS (11) COLUMN DECODER A0 A1 A2 A3 2048 REFRESH CONTROLLER A4 SENSE AMPLIFIERS I/O GATING A5 A6 REFRESH COUNTER 2048x4 A7 A8 RAS 2048 ROW ADDRESS BUFFERS (11) ROW DECODER A9 A10 2048x2048x4 MEMORY ARRAY Vcc NO. 1 CLOCK GENERATOR Vss Rev.1 Page 5 TRUTH TABLE ADDRESSES FUNCTION RAS CAS WE OE ROW COL STANDBY H HX X X X X READ L L H L ROW COL Data-Out WRITE: (EARLY WRITE ) L L L X ROW COL Data-ln READ WRITE L L HL LH ROW COL Data-Out,Data-ln 1st Cycle L HL H L ROW COL Data-Out 2nd Cycle L HL H L n/a COL Data-Out EDO-PAGE 1st Cycle MODE WRITE 2nd Cycle L HL L X ROW COL Data-In L HL L X n/a COL Data-In 1st Cycle L HL HL LH ROW COL Data-Out, Data-In 2nd Cycle L HL HL LH n/a COL Data-Out, Data-In READ LHL L H L ROW COL Data-Out WRITE LHL L L X ROW COL Data-In L H X X ROW n/a High-Z HL L H X X X High-Z EDO-PAGEMODE READ EDOPAGE-MODE READ-WRITE HIDDEN REFRESH RAS-ONLY REFRESH CBR REFRESH DQS Notes High-Z 1 Notes: 1. EARLY WRITE only. Rev.1 Page 6 Absolute Maximum Ratings Parameter Symbol Value Unit VT -0.5 to + 4.6 V Supply voltage relative to Vss VCC -0.5 to + 4.6 V Short circuit output current IOUT 50 mA PD 1.0 W Operating temperature TOPT 0 to + 70 C Storage temperature TSTG -55 to + 125 C Voltage on any pin relative to Vss Power dissipation Recommended DC Operating Conditions Parameter/Condition Symbol 3.3 Volt Version Min Typ Supply Voltage VCC 3.0 Input High Voltage, all inputs VIH 2.0 Input Low Voltage, all inputs VIL -0.3 Unit Max 3.3 3.6 V - VCC + 0.3 V - V 0.8 Capacitance Ta = 25C, VCC = 3.3V 10 %, f = 1MHz Parameter Symbol Typ Max Unit Note Input capacitance (Address) CI1 - 5 pF 1 Input capacitance (RAS, CAS, OE, WE) CI2 - 7 pF 1 Output capacitance (Data-in, Data-out) CI/O - 7 pF 1, 2 Note: 1. Capacitance measured with effective capacitance measuring method. 2. RAS, CAS = V IH to disable Dout. Rev.1 Page 7 DC Characteristics : (Ta = 0 to 70C , VCC = + 3.3V 10 %, VSS = 0V) Parameter Symbol Test Conditions AD404M42V -5 Operating current Low power S-version Unit Notes 1, 2 -6 Min Max Min Max ICC1 RAS cycling CAS, cycling tRC = min - 120 - 110 mA ICC2 LVTTL interface RAS, CAS = VIH Dout = High-Z - 0.5 - 0.5 mA CMOS interface - 0.15 - 0.15 mA LVTTL interface RAS, CAS = VIH Dout = High-Z - 2 - 2 mA CMOS interface - 0.5 - 0.5 mA RAS, CAS V C C -0.2V Dout = High-Z Standby Current Standard power version RAS, CAS V C C -0.2V Dout = High-Z RAS- only refresh current ICC3 RAS cycling, CAS = VIH tRC = min - 120 - 110 mA 1, 2 EDO page mode current ICC4 tPC = min - 90 - 80 mA 1, 3 CAS- before- RAS refresh current ICC5 tRC = min RAS, CAS cycling - 120 - 110 mA 1, 2 Self- refresh current (S-Version) ICC8 t RASS 100s - 550 - 550 A Rev.1 Page 8 DC Characteristics : (Ta = 0 to 70C, VCC= +3.3V 10 %, VSS= 0V) AD404M42V -5 Parameter Symbol Test Conditions Min Unit -6 Max Min Max Input leakage current ILI 0V Vin V C C + 0.3V -5 5 -5 5 A Output leakage current ILO 0V Vout V CC + 0.3V -5 5 -5 5 A Output high Voltage VOH IOH = -2mA 2.4 - 2.4 - V Output low voltage VOL IOL = +2mA - 0.4 - 0.4 V Dout = Disable Notes: 1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. For I CC4, address can be changed once or less within one EDO page mode cycle time. Rev.1 Page 9 Notes AC Characteristics (T a = 0 to + 70C, Vcc = 3.3V 10 %, Vss = 0V) *1, *2, *3, *4 Test conditions * Output load: one TTL Load and 100pF (VCC = 3.3V 10 %) * Input timing reference levels: VIH = 2.0V, VIL = 0.8V (VCC = 3.3V 10 %) * Output timing reference levels: VOH = 2.0V, VOL = 0.8V Read, Write, Read- Modify- Write and Refresh Cycles (Common Parameters) AD404M42V -5 Parameter Symbol Min Unit Notes -6 Max Min Max Random read or write cycle time tRC 84 - 104 - ns RAS precharge time tRP 30 - 40 - ns CAS precharge time in normal mode tCPN 10 - 10 - ns RAS pulse width tRAS 50 10000 60 10000 ns 5 CAS pulse width tCAS 8 10000 10 10000 ns 6 Row address setup time tASR 0 - 0 - ns Row address hold time tRAH 8 - 10 - ns Column address setup time tASC 0 - 0 - ns Column address hold time tCAH 8 - 10 - ns RAS to CAS delay time tRCD 12 37 14 45 ns 8 RAS to column address delay time tRAD 10 25 12 30 ns 9 Column address to RAS lead time tRAL 25 - 30 - ns RAS hold time tRSH 8 - 10 - ns CAS hold time tCSH 38 - 40 - ns CAS to RAS precharge time tCRP 5 - 5 - ns OE to Din delay time tOED 12 - 15 - ns tT 1 50 1 50 ns Refresh period tREF - 32 - 32 ms Refresh period (S- Version) tREF - 128 - 128 ms CAS to output in Low- Z tCLZ 0 - 0 - ns CAS delay time from Din tDZC 0 - 0 - ns OE delay time from Din tDZO 0 - 0 - ns Transition time (rise and fall) Rev.1 7 10 11 Page 10 Read Cycle AD404M42V -5 Parameter Symbol Min Unit Notes -6 Max Min Max Access time from RAS tRAC - 50 - 60 ns 12 Access time from CAS tCAC - 14 - 15 ns 13, 14 tAA - 25 - 30 ns 14, 15 Access time from OE tOEA - 12 - 15 ns Read command setup time tRCS 0 - 0 - ns 7 Read command hold time to CAS tRCH 0 - 0 - ns 10, 16 Read command hold time to RAS tRRH 0 - 0 - ns 16 Output buffer turn-off time tOFF 0 12 0 15 ns 17 Output buffer turn-off time from OE tOEZ 0 12 0 15 ns 17 Unit Notes 7, 18 Access time from column address Write Cycle AD404M42V -5 Parameter Symbol Min -6 Max Min Max Write command setup time tWCS 0 - 0 - ns Write command hold time tWCH 8 - 10 - ns Write command pulse width tWP 8 - 10 - ns Write command to RAS lead time tRWL 13 - 15 - ns Write command to CAS lead time tCWL 8 - 10 - ns Data-in setup time tDS 0 - 0 - ns 19 Data-in hold time tDH 8 - 10 - ns 19 tWED 10 - 10 - ns WE to Data-in delay Rev.1 Page 11 Read- Modify- Write Cycle AD404M42V -5 Parameter Min Symbol Unit Notes -6 Max Min Max Read-modify- write cycle time tRWC 108 - 133 - ns RAS to WE delay time tRWD 64 - 77 - ns 18 CAS to WE dealy time tCWD 26 - 32 - ns 18 Column address to WE delay time tAWD 39 - 47 - ns 18 OE hold time from WE tOEH 8 - 10 - ns Refresh Cycle AD404M42V -5 Parameter Symbol Min -6 Max Min Max Unit Notes CAS setup time (CBR refresh) tCSR 5 - 5 - ns CAS hold time (CBR refresh) tCHR 8 - 10 - ns 10 RAS precharge to CAS hold time tRPC 5 - 5 - ns 7 RAS pulse width (self refresh) tRASS 100 - 100 - s RAS precharge time (self refresh) tRPS 90 - 110 - ns CAS hold time (CBR self refresh) tCHS -50 - -50 - ns WE setup time tWSR 0 - 0 - ns WE hold time tWHR 10 - 10 - ns Rev.1 Page 12 EDO Page Mode Cycle AD404M42V -5 Parameter Symbol -6 Min Max Min Max Unit Notes EDO page mode cycle time tPC 20 - 25 - ns EDO page mode CAS precharge time tCP 10 - 10 - ns EDO page mode RAS pulse width tRASP 50 105 60 105 ns 20 Access time from CAS precharge tCPA - 30 - 35 ns 10, 14 RAS hold time from CAS precharge tCPRH 30 - 35 - ns OE high hold time from CAS high tOEHC 5 - 5 - ns OE high pulse width tOEP 10 - 10 - ns Data output hold time after CAS low tCOH 5 - 5 - ns Output disable delay from WE tWHZ 3 10 3 10 ns WE pulse width for output disable when CAS high tWPZ 7 - 7 - ns EDO Page Mode Read Modify Write Cycle AD404M42V -5 Parameter Symbol -6 Min Max Min Max Unit Notes 10 EDO page mode read- modify- write cycle CAS precharge to WE delay time tCPW 45 - 55 - ns EDO page mode read- modify- write cycle time tPRWC 56 - 68 - ns Rev.1 Page 13 Notes : 1. AC measurements assume t T = 2ns. 2. An initial pause of 100 s is required after power up, and it followed by a minimum of eight initialization cycles (RAS - only refresh cycle or CAS - before - RAS refresh cycle). If the internal refresh counter is used, a minimun of eight CAS - before - RAS refresh cycles are required. 3. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 4. All the VCC and VSS pins shall be supplied with the same voltages. 5. tRAS(min) = tRWD(min)+t RWL(min)+tT in read-modify-write cycle. 6. tCAS (min) = tCWD(min)+tCWL(min)+tT in read-modify-write cycle. 7. tASC(min), tRCS (min), tWCS(min), and tRPC are determined by the falling edge of CAS . 8. t RCD(max) is specified as a reference point only, and tRAC (max) can be met with the tRCD(max) limit. Otherwise, tRAC is controlled exclusively by tCAC if tRCD is greater than the specified tRCD(max) limit. 9. tRAD(max) is specified as a reference point only, and tRAC(max) can be met with the tRAD(max) limit. Otherwise, tRAC is controlled exclusively by tAA if tRAD is greater than the specified tRAD(max) limit. 10. tCRP, tCHR , tRCH, tCPA and tCPW are determined by the rising edge of CAS . 11. V IH(min) and VIL(max) are reference levels for measuring timing or input signals. Therefore, transition time is measured between VIH and VIL. 12. Assumes that t RCD tRCD(max) and tRAD tRAD(max). If t RCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 13. Assumes that tRCD t RCD (max) and tRAD t RAD (max). 14. Access time is determined by the maximum of tAA , tCAC, tCPA. 15. Assumes that t RCD tRCD (max) and t RAD tRAD (max). 16. Either tRCH or tRRH must be satisfied for a read cycle. 17. tOFF(max) and tOEZ(max) define the time at which the output achieves the open circuit condition (high impedance). t OFF is determined by the later rising edge of RAS or CAS. 18. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS t WCS (min), the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tRWD tCWD t CWD (min), t AWD t AWD (min) and tCPW tRWD (min), tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data output (at access time) is indeterminate. 19. These parameters are referenced to CAS separately in an early write cycle and to WE edge in a delayed write or a read-modify-write cycle. 20. tRASP defines RAS pulse width in EDO page mode cycles. Rev.1 Page 14 Timing Waveforms * Read Cycle t RC t t RP RAS RAS t CRP t CSH t RCD t RSH t T t CPN t CAS CAS t RAL t RAD t ASR ADDRESS t ASC t RAH t CAH Column Row t RRH t RCH t RCS WE OE t OEA t CAC t OEZ t OFF t AA t OFF t RAC D OUT DQ1~DQ4 t CLZ Note : = don't care = Invalid Dout Rev.1 Page 15 *Early Write Cycle t RC t RAS t RP RAS t CRP t CSH t RCD t RSH t CPN t T t CAS CAS t RAD t ASR ADDRESS t RAH t RAL t ASC Row t CAH Column t RAL t WCS t WCH WE t DS DQ1~DQ4 t DH DIN Rev.1 Page 16 * Delayed Write Cycle t RC t t RP RAS RAS t CSH t CRP t RCD t RSH t T t CPN t CAS CAS t ASR ADDRESS Row t RAH t CAH t ASC Column t CWL t RCS t RWL t WP WE t OED OE t OEH t DS t DS DQ1~DQ4 OPEN t DH DIN Rev.1 Page 17 * Read - Modify - Write Cycle t RWC t t RP RAS RAS t T t RCD t CAS t CRP t CPN CAS t RAD t ASR ADDRESS t ASC t RAH Row t CAH Column t RCS t CWL t RWL t CWD t AWD t RWD t WP WE t DZC t DH t DS OPEN DQ1~DQ4 t DZO DIN t OED t OEH OE t RAC t OEA t CAC t AA t OEZ DQ1~DQ4 DOUT Rev.1 Page 18 * EDO Page Mode Read Cycle t RP t RASP t CPRH RAS t CRP t PC t CSH t CRP t RCD t CAS t RSH t CAS t CP t CAS t CP t CPN CAS t RAD t ASR ADDRESS t RAL t ASC t RAH Row t CAH Column 1 t ASC t ASC t CAH t CAH Column N Column 2 t RRH t RCH t RCS WE Row WE t OEHC t OEA t OEP t OEA OE OE t RAC t CPA t CPA t AA t AA t OEZ t AA t OFF t OEZ t CAC t CAC t CAC t OFF t COH DQ1~DQ4 DOUT 1 DOUT N DOUT 2 Rev.1 Page 19 OPEN * EDO Page Mode Early Write Cycle t t RP RASP RAS tT t CSH t RSH t CAS t PC t CAS t RCD t CAS t CP t CP t CRP t CPN CAS t ASR ADDRESS Row t RAH t ASC t CAH t ASC t CAH Column N t WCS t WCH t WCS t WCH t DS t DH t DS t DH WE t DS DQ1~DQ4 t WCH t CAH Column 2 Column 1 t WCS WE t ASC t DH DIN 2 DIN 1 Rev.1 DIN N Page 20 * EDO Page Mode Read-Early-Write Cycle t t RP RASP t CPRH RAS t CRP t PC t CSH t CRP t RCD t CAS t RSH t CAS t CP t CAS t CP t CPN CAS t CAL t CSH t RAD t ASR ADDRESS t RAL t ASC t RAH Row t RAH t ASC t CAH Column N Column 2 Column 1 t RCH t RCS WE t ASC t CAH Row t WCS t WCH WE t OEA t WED OE OE t RAC t CPA t AA t AA t WHZ t CAC t CAC t DH t DS t COH DQ1~DQ4 OPEN Data Doutput 1 Data Doutput 2 Data Input N Rev.1 Page 21 * EDO Page Mode Read-Modify-Write Cycle t RASP tCPRH t RP RAS t T t RCD t CP t CAS t PRWC t CRP t CP t CAS t CAS CAS t RAD t ASR t ASC t RAH ADDRESS t ASC t CAH Column 2 t CWL t RWD t AWD t CWD WE t CAH t CAH Column 1 Column 1 Row t RAL t ASC t RCS Column N t CWL t CPW t AWD t CWD t RCS t CWL t CPW t AWD t CWD t RWL WE t RCS t WP t WP t DS t DZC DIN 1 t DH OPEN DIN 2 t DZO t DH OPEN DIN N t DZO t DZO t OED t OED t DS t DS t DH OPEN DQ1~DQ4 t WP t DZC t DZC t OEH t OEH t OED t OEH OE t OEA t OEA t CAC t CAC t RAC t AA t CPA t AA t CPA t AA t OEA t CAC t OEZ t OEZ t OEZ DQ1~DQ4 DOUT 1 DOUT Rev.1 2 DOUT N Page 22 * Read Cycle with WE Controlled Disable RAS t CSH t RCD t CAS t T CAS t RAD t ASR ADDRESS t ASC t RAH Row t CAH Column t RCH t RCS t WPZ WE t WHZ t DS OE tOEA tCAC tOEZ t AA t RAC DQ1~DQ4 DOUT tCLZ Rev.1 Page 23 RAS-Only Refresh Cycle t RC t RP t RAS RAS tT tRPC t CRP tCRP CAS tASR ADDRESS tRAH ROW tOFF OPEN DQ1~DQ4 CAS-Before-RAS Refresh Cycle tRC tRP RAS tRC tRAS tT t RAS tRP tRPC tRPC t RP tCRP t CSR t CHR tCSR t CHR tWSR tWHR tWSR tWHR CAS WE tOFF OPEN DQ1~DQ4 Rev.1 Page 24 CBR Self-Refesh Cycle t RPS t RASS RAS t RPC t CSR CAS tCHS tOFF High lmpedance DQ1~DQ4 tWSR WE tWHR OPEN Rev.1 Page 25 * Hidden Refresh Cycle t RC t RC t RC t RP tRAS (READ) tRAS t RP (REFRESH) tRAS t RP (REFRESH) RAS tT t CHR tCRP t RSH t RCD tCAS CAS t RAD t ASR ADDRESS t RAH t RAL tASC tCAH COlumn ROW tRRH t RCS tRCH WE OE t OEZ t OEA t CAC t OFF t AA t OFF t RAC D OUT DQ1~DQ4 Rev.1 Page 26 Ordering information Part Number Access time Package AD404M42VSA-5 50 ns AD404M42VSA-6 60 ns 300mil 26/24-Pin AD404M42VTA-5 50 ns Plastic SOJ TSOP II AD404M42VTA-6 60 ns AD404M42VSA-5 * AD * Ascend Memory Product * 40 * Device Type * 4M4 * Density and Organization *2 * Refresh Rate, 2: 2K Refresh *V * T: 5V, V: 3.3V *S * Package Type (S : SOJ, T : TSOP II) *A * Version *5 * Speed (5: 50 ns, 6: 60 ns) Packaging information * 300 mil, 26/24-Pin Plastic SOJ D A A1 A2 MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. 3.25 3.51 3.76 0.128 0.138 0.148 2.08 ----0.082 ----2.54 REF. 0.100 REF. b 0.41 --- 0.51 0.016 --- 0.020 b1 b2 0.41 0.66 0.46 --- 0.48 0.81 0.016 0.026 0.018 --- 0.019 0.032 c c1 D E E1 E2 e R1 0.18 0.18 17.02 --0.30 --0.28 17.15 17.27 8.51 BASIC 7.49 7.62 7.75 6.78 BASIC 1.27 BASIC 0.76 --1.02 0.007 0.007 0.670 DIM --0.012 0.011 --0.675 0.680 0.335 BASIC 0.295 0.300 0.305 0.267 BASIC 0.050 BASIC 0.030 --0.040 b 26 21 19 14 b1 c1 c E1 E BASE METAL WITH PLATING 1 6 8 13 SECTION B-B CL 0.025" MIN. A2 B B A A1 NOTE: 1. CONTROLLING DIMENSION : INCHES 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006"(0.15mm) PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.01"(0.25mm) PER SIDE. 3. DIMENSION b2 DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE SHOULDER WIDTH TO EXCEED b2 MAX BY MORE THAN 0.005"(0.127mm) DAMBAR INTRUSION SHALL NOT REDUCE THE SHOULDER WIDTH TO LESS THAN 0.001"(0.025mm) BELOW b2 MIN. RAD R1 e b2 b 4-e 0.004" E2 SEATING PLANE 0.007"M Rev.1 Page 27 * 300 mil, 26/24-Pin TSOP II DIM A MILLIMETERS MIN. NOM. INCHES MAX. MIN. NOM. MAX. --- --- 1.20 --- --- 0.047 A1 0.05 --- 0.15 0.002 --- 0.006 A2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.30 --- 0.52 0.012 --- 0.020 b1 0.30 0.40 0.45 0.012 0.016 0.018 c 0.12 --- 0.21 0.005 --- 0.008 c1 0.12 0.15 0.16 0.005 0.006 (0.006) D ZD 17.01 17.14 17.27 0.670 0.675 0.680 e E 9.02 0.95 REF. 0.0374 BASIC 1.27 BASIC 0.050 BASIC RAD R1 26 21 19 14 RAD R A2 c B E1 E B A1 L DETAIL A 0 ~5 b 1 6 8 b1 13 SECTION B-B D 9.22 9.42 0.355 0.363 0.371 E1 7.49 7.62 7.75 0.295 0.300 0.305 L 0.40 0.50 0.60 0.016 0.020 0.024 R 0.12 --- 0.25 0.005 --- 0.010 R1 0.12 --- --- 0.005 --- c1 BASE METAL WITH PLATING --- NOTE: 1. CONTROLLING DIMENSION : MILLIMETERS 2. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15(0.006") PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD PROTRUSION. INTERLEAD PROTRUSION SHALL NOT EXCEED 0.25(0.01") PER SIDE. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSIONS/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD TO BE WIDER THAN THE MAX b DIMENSION BY MORE THAN 0.13mm. DAMBAR INTRUSION SHALL NOT CAUSE THE LEAD TO BE NARROWER THAN THE MIN b DIMENSION BY MORE THAN 0.07mm. c DETAIL A (ZD) A 4-1.27 REF. b e SEATING PLANE 0.200(0.008") M Rev.1 0.100(0.004") Page 28