FW82439TXSL28T - Intel

Intel® 430TX PCIset: 82439TX

System Controller (MTXC)

Specification Update

March 2000

Notice: The 82439TX Sy st em C o ntro lle r (MTXC) m ay co ntai n de si gn de fec ts or erro rs k nown as

errata tha t may c ause th e product to d eviat e from pu blish ed spec ifica tions . Current characte rize d

errata are documented in this specification update. Order Number: 290615-002

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medic al, life saving, or life sustaining applica tions.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82439TX System Controller (MTXC) may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG CODECs, or MPEG enabled

platfo rms may re quire licenses from various entities, including Intel Corporation.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-

548-4725 or by visiting Intel’s website at http://www.intel.com.

*Third-party brands and names are the property of their respective owners.

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update 3

Contents

Revision History......................................................................................... 5

Preface....................................................................................................... 6

Summary Table of Changes....................................................................... 8

Identification Information.......................................................................... 10

Errata........................................................................................................11

Specification Changes............................................................................. 13

Specification Clarifications....................................................................... 14

Documentation Changes ......................................................................... 16

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update 5

Revision History

Date Version Description

March 2000 -002 Added S-Spec SL2LR.

March 1998 -001 Initial release.

6Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update

Preface

This document is an update to the specifications contained in the Affected Documents/Related

Docu ments ta ble belo w. This document is a compilation of device and documentation errata,

specification clarifications and changes. It is intended for hardware system manufacturers and

software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are

no longer published in other documents.

This docum ent may also contain information that was not previously published.

Affected Documents/Related Documents

Title Order Number

Intel 430TX PCIset: 82439TX System Controller (MTXC) 290559

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update 7

Preface

Nomenclature

Errata are design defects or errors. These may cause the 82439TX System Controller (MTXC)’s

behavior to deviat e from published s pecifications. Hardware and so ftware designed to be used with

any given stepping must assume that all errata documented for that stepping are present on all

devices.

Specification Changes are modifications to the current published specifications. These changes

will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a

specification’s impact to a complex design situation. These clarifications will be incorporated in

any new release of the specification.

Documentation Cha nges include typos, errors, or omissions from the current published

specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specificatio n update throughout the product’s lifecycle, or until a particular

stepping is no longer commercially av ailabl e. Under these circumstances, er rata remov ed fr om the

specification update are archived and available upon request. Specification changes, specification

clarifications and documentation changes are removed from the specification update when the

appropriate changes are made to the appropriate product specification or user documentation

(datasheets, manuals, etc.).

8Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update

Summary Table of Changes

The following tables indicate the errata, specification changes, specification clarifications, or

documentation changes which apply to the 82439TX System Controller (MTXC) product. Intel

may fix some of the errata in a future stepping of the component, and account for the other

outstanding issues through documentation or specification changes as noted. This table uses the

following notations:

Codes Used in Summary Table

Stepping

X: Errata exists in the stepping indicated. Specification Change or

Clarification that applies to this stepping.

(No mark)

or (Blank box): This errat um is fi xed in l ist ed s teppi n g or specificati o n chan ge does not

apply to listed stepping.

Page

(Page): Page location of item in this documen t.

Status

Doc: Document change or update will be implemented.

Fix: This erratum is intended to be fixed in a future step of the component.

Fixed: This erratum has been previously fixed.

NoFix: There are no plans to fix this erratum.

Eval: Plans to fix this erratum are under evaluation.

Row

Change bar to left of table row indicates thi s item is either new or

modified from the previous version of the document.

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update 9
Summary Table of Changes
Errata
No. Steppings Page Status ERRATA
A0 A1 A2
1 X X X 11 NoFix SDRAM Speculative Read Enable (SSRE)
2 X 11 Fix Address Setup Time
3 X X 12 NoFix Fast Back-to -Back, PCI Peer-to-P eer Cycles
Specification Changes
No. Steppings Page Status SPECIFICATION CHANGES
A0 A1 A2
None for this revision of this specification update.
Specification Clarifications
No. Steppings Page Status SPECIFICATION CLARIFICATIONS
A0 A1 A2
1 XXX14 DocInsuring Signal Integrity in a Lightly Loaded Systems
2 XX14Doc
Insuring Correct Setting for MTXC Register Offset 53h 
(CEC)
3 X X 14 Doc Bits 4 and 5, Register Offset 52h Clarification
4 X X 14 Doc MTXC Power  Plane Sequencing
5 XXX14Doc
Timing Of The SUSCLK And SUS_STAT# Signals For 
Resume Voltage Well Reset
Documentation Changes
No. Document Revision Page Status DOCUMENTATION CHANGES
1 001 16 Doc NAND Chain Mode
2 001 16 Doc DRAMT - DRAM Timing Register Description
3 001 16 Doc Vcc5REF Sequencing Circuit
4 001 16 Doc SDRAM Performance Summary
5 001 17 Doc SDRAM Control Register Bit 1 Description

10 Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update

Identification Information

Markings

General Information

Component Markings

Component Identification Via Programming Interface

The 82439TX MTXC stepping can be identified by the following register contents:

Table 1. 82439TX MTXC Identification Information

82439TX

Stepping S-Spec Top Marking Freq. Notes

A-0 FW82439TX Q516ES 66/33 Engineering Sample

A-0 FW82439TX Q517ES 66/33 Engineering Sample

A-1 FW82439TX Q536ES 66/33 Engineering Sample

A-1 FW82439TX Q537ES 66/33 Engineering Sample

A-1 FW82439TX S L238 66/33 Production

A-2 Q562 FW82439TX Q562ES 66/33 Engineering Sample

A-2 SL28T FW82439TX S L28T 66/33 Production

A-2 Q557 FW82439TX Q557ES 66/33 Engineering Sample

A-2 SL2LR FW82439TX S L2LR 66/33 Production - Remnant lots

Table 2. 82439TX MTXC Stepping Identification

82439TX MTXC Stepping Vendor ID1Device ID2Revision Number3

A-0 8086h 7100h 00h

A-1 8086h 7100h 01h

A-2 8086h 7100h 01h

NOTES:

1. PCI function 0 configuration space.

2. The Device ID corresponds to bits 15-0 of the Device ID Register located at offset 02-03h in the PCI

function 0 configuration space.

3. The Revision Number correspond to bits 7-0 of the Revision ID Register located at offset 08h in the PCI

function 0 configuration space. The Revision Number remains 01h for the A-2 stepping.

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update 11

Errata

1. SDRAM Speculative Read Enable (SSRE)

Problem: Due to a timing marginality during SDRAM read-page-hit cycles, the SSRE mode does not

function properly and must be disabled. This mode provided a five clock read lead off during CPU

read-page-hit cycles to main memory. This mode impacts SDRAM only.

Implication: If SSRE mode is enabled, the system may not function properly. Intel has tested this mode and

found the performance impact of disabling the SSRE mode is minimal using the 430TX reference

platform with a 200 MHz Pentium® processor with MMX™ technology, 16 Mbytes SDRAM,

512 Kbytes PBSRAM L2, and hard drive in PIO Mode 4.

Workaround: This errata is avoided by disabling the SSRE mode by clearing bit 7 in register offset 56h to “0”.

This bit has been changed to a reserved bit and must always remain in its defau lt state (0).

Status: For the steppings affected see the Summary Table of Changes at the beginning of this section.

2. Address Setup Time

Problem: Intel’s 430TX PCIset external timing specification (ETS) specifies that the PCI address setup to the

MTXC is 7.0 ns. However, it has been determined that the MTXC requires a 7.7 ns address setup

on PCI AD lines 30 and 31.

Implication: If the PCI address setup to the MTXC is not met, then the MTXC will not complete the cycle

correctly. This may result in a system failure or data error which is not immediately visible to the

end user. There is no test currently available to expose this type of error to the end user , theref ore, it

is essential that th e new tim ing requirement is m e t.

In a system with a 33 MHz PCI bus, the setup time is gene rated within a 30 ns window. The delay

components with in this window are: valid delay, fligh t tim e, and PCI cloc k skew (the specific

equation is: 30 ns - valid delay - flight time - PCI clock skew - setup). In general, the OEM has

control o f the fl ight time and clo c k skew. Both of these delay co mponents often h a ve additional

margin which should compensate for the increased timing requirement on the MTXC. OEM’s

should evaluate their board designs to determine if additional clock skew and/or flight time margin

is available.

Workaround: The design should be laid-out in such a manner to compensate for the MTXC’s increased timing

requirement. OEM’s should examine their existing designs to determine if their specific PCI flight

time and PCI clock skews will provide sufficient timing ma rgin.

To check your design for adequate margin:

1. Measure th e PCI C lock Sk ew between t he MTXC P CI Clo ck and t he ot her PC I Clocks in you r

system. If the MTXC PCI clock lags behind the other PCI clocks, this issue should not be a

problem. If the MTXC PCI clock leads the other PCI clocks by less than 1.3 ns, this issue

should not be a problem. This is assuming that all other param eters, external to the MTXC

component , meet P CI bus ti ming require ment s. The max imum skew is meas ured betw een an y

two components, not at the PCI connector. For example, if the measurement is being made

between the MTXC and a PCI device in a slot, make the measurement from the MTXC to the

device on the PCI card, and not to the connector the card is plugged in to. The measurements

are generally m ade at the 1 .5 V t o 1 .5 V l evel. However, refer to the PCI sp ecifi cat io n r ev 2.1 ,

section 4.3.1 for precise measurement points.

12 Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update

Errata

2. T o get an idea of how much PCI flight time mar gin a particular system has, first make sure that

your PCI bus is fully loaded (i.e., populate all of the slots). In general, the flight time is at its

worst between the two devices on the bus that are furthest away from each other. However , for

a complete measurement, check the PCI device nearest to, and furthest from the MTXC,

excluding the PIIX4.

3. The maximum flight time is measured between any two comp onents, not at the PCI connecto r.

For example, when measurin g the flight time, measu re AD31 at the MTXC, on one probe, and

AD31 at the initiating PCI device, on a second probe. The difference between these two

measurement s will giv e you the flig ht tim e on this line. For these measurements, the P CI

master should be driving the address lines. Repeat the measurement for AD30. The

measurements can be made from the 1.5 V to the 1.5 V level.

Status: For the steppings affected see the Summary Table of Changes at the beginning of this section.

3. Fast Back-to-Back, PCI Peer-to-Peer Cycles

Problem: If a fast back-to-back cycle occurs on the PCI bus between the same master peer device and the

same slave peer device (i.e., MTXC and PIIX4 are not the intended targets), and at the same time a

CPU cycle to PCI occurs, the MTXC may miss the second peer-to-peer cycle in the back-to-back

sequence. The specific conditions that need to be met for this to occur, are as follows:

•The PCI peer-to-peer, back-to-back transfer must happen at the same time the CPU is

generating a host cycle to PCI. Specifically, between the rising edge of the first FRAME#

(associated with the first cycle of the back-to-back transfer) to the rising edge of the second

FRAME# (associated with the second cycle in the back-to-back transfer).

•The PCI back-to-back transfer must be peer-to-peer and the transfer must not be targeting the

PIIX4 or the MTXC.

•The PCI master must be capable of running “fast” back-to-back cycles.

•The second cycle of the back-to-back transfer must be targeting the same PCI slave device.

•The PCI slave device must be doing a “fast” decode.

•The first cycle in the back-to-back transfer must be a single transfer.

•The first cycle in the back-to-back transfer must be a PCI write cycle (memory or I/O).

Implication: Intel observed this issue in a system simu lation environment.

Workaround: If deemed necessary by the OEM, this issue can be avoided by clearing bit 3 in register offset 50h

to “0”. When set to “0”, this bit prevents CPU bus access during PCI peer-to-peer transfers.

Status: For the steppings affected see the Summary Table of Changes at the beginning of this section.

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update 13

Specification Changes

None for this revision of the Specification Update.

14 Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update

Specification Clarifications

1. Insuring Signal Integrity in a Lightly Loaded Systems

To insure that DRAM interface signal integrity is maintained for lightly loaded Mobile and desktop

systems, series termination and/or diodes (Gnd and VCC diodes) are recommended on the

following si g nals: C AS# / DQMx, MWEx , S CASx, S RASx, CKEx, and all MA li nes (n ot e: RAS4#

and RAS5# are also used as MA lines, depending on the configuration, and should be terminated

when used as MA lines). This will insure that the overshoot, undershoot, and most importantly,

ring-back do not cause any problems.

If series termination is us ed, use 10 Ω. This value provides the best signal integrity and flight time

results. Place as close to the driver a s possible. If diodes ar e used, the dio des should have a fo rward

current of at least 200 mA at 1 volt. A MMBD1203 diode or equivalent meets this requirement.

The diodes should be placed at the end of the trace.

Diodes im prove signal integrity with out increasing the flight time. A 10 Ω series resistor will

increase the fligh t time by approxi mately 300 ps. Bo th provide sim ilar signal inte grity results.

2. Insuring Correct Setting for MTXC Register Offset 53h (CEC)

During normal operation, the value programmed into register offset 53h should not be changed

from its default value of 14 h. This register controls the ti me the MTXC remains idle duri ng a

DRAM Cache refresh.

3. Bits 4 and 5, Register Offset 52h Clarif ication

In the bit descrip tion for these two bi ts, “Pipelined Burst SRAM ” (bits 5:4 = 00) also applies to a

512 Kbyte L2 size when two 64 Kbit x 32 SRAM devices are used.

The “Note:” in the register description for these to bits should be replaced with the following:

When 512 Kbyte, Two Banks of Pi peline d Burst mode is selected (SCS = 10 and L2SRAMT = 1 1),

NA# will be delayed by one HCLK during burst reads from L2 to ensure that the active bank is not

deselected too early by pipelining a cycle to the opposite bank.

4. MTXC Power Plane Sequencing

The following clarifies the MTXC power plane sequencing requirements described on page 10 of

the MTXC EDS Rev. 1.0. In a system that implements VCC(CORE) and VCC(CPU) as

independent power planes, the VCC(CPU) pins must power up after or simultaneous to

VCC(CORE), and must power down before or simultaneous to VCC(CORE). At any time,

VCC(CORE) should not be more than 1.2 V below the VCC(CPU) plane. VCC(SUS) can power

up and power down independent of all other power pla nes.

5. Timing Of The SUSCLK And SUS_STAT# Signals For Resume Voltage Well

Reset

The following information is added as paragraph 4.6.2.2, MTXC Resume Voltage Well Reset, to

the MTXC datasheet, order nu mber 290559-001: The MTXC will transition from suspend refresh

to normal refresh when it samples SUSC LK activ e (high) with the first sample of SUS_STAT#

inactive (high). Samples are taken on the rising edge of the PCI clock. The MTX will reset its

resume well (DRAM configuration regi sters go to default settings) when it samples SUSC LK

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update 15

Specification Clarifications

inactive (low) with th e first sam ple of SUS_STAT# inactive (high). The mechanism which allows

this functi onality is based on the PIIX4 deassertin g the SUS_STAT# signal in relation to the

SUSCLK, synchronized to the PCI clock . To not reset the suspend well within the MTXC , the

PIIX4 will drive the SUS_STAT# signal just after the SUSCLK signal has gone high. To reset the

resume well within the MTXC , the PIIX4 will driv e the SUS_STAT# signal while the SUSCLK is

disabled (low). Because of this functionality, SUSCLK should not be inverted for any reason in

applications.

16 Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update

Documentation Changes

1. NAND Chain Mode

Issue: The pin name associated with CH3_25 should be MWE#, not MWEB# as shown on page 83 of the

datasheet.

Affected Docs: Intel® 430TX PCIset: 82439TX System Controller (MTXC) datasheet (order number 290559-001)

2. DRAMT - DRAM Timing Register Descri ption

Issue: The description for DRAMT - DRAM Timing Register, off set 58h, bits 6 :5, shoul d read as follows :

Affected Docs: Intel® 430TX PCIset: 82439TX System Controller (MTXC) datasheet (order number 290559-001)

3. Vcc5REF Sequencing Circuit

Issue: Page 16, paragraph 2.4, Figure 2. “Example Vcc5REF Sequencing Circuit”, of the “Intel 430TX

PCIset: 82439TX System Controller (MTXC)” datasheet (order number 290559-001), shows a

Zener diode symbol between the 3.3 V VCC supply and the 5 V supply. This is incorrect. The

following shou ld be implemented to correct this circuit:

•The diode used in t his circui t shou ld be a Schott ky diod e (or an y di o de with a forward vol tage

drop of no more than 0.4 V) and the symbol shown should be a Schottky diode symbol.

The reason for this correction is to provide circuit protection in case of 5 V power loss.

Affected Docs: Intel® 430TX PCIset: 82439TX System Controller (MTXC) datasheet (order number 290559-001)

4. SDRAM Performance Summary

Issue: Page 61, Table 18, “SDRAM Performance Summary”, of the “Intel 430TX PCIset: 82439TX

System Controller (MTXC)” datasheet, order number 290559-001, is changed to correct

typographical errors as shown below:

Bit Description

6:5 DRAM Read Burst Timing (DRBT). The DRAM read burst timings are controlled by

the DRBT field. Slower rates may be required in certain system designs to support

loose layouts or slower memories. Most system designs will be able to use one of

the faster burst mode timings. The timing used depends on the type of DRAM on a

per-bank basis, as indicated by the DRT register.

DRBT EDO Burst Rate FPM Burst Rate

00 x444 x444

01 x333 x444

10 x222 x333

11 Reserved Reserved

Intel® 430TX PCIset: 82439TX System Controller (MTXC) Specification Update 17

Documentation Changes

Affected Docs: Intel® 430TX PCIset: 82439TX System Controller (MTXC) datasheet (order number 290559-001)

5. SDRAM Control Register Bit 1 Descript ion

Issue: Page 30 of the “Intel 430TX PCIset: 82439TX System Controller (MTXC)” data book (order

number 2905 59-001), in the des cri pti on of b it 1 of the SDRAM C ont rol Regis ter, the port ion of the

description relati ve t o when the b it is set t o 1: The sen tence, “In this mode , the RA S#/ CS5# si gnal

becomes RAS#/CS5#/MA13 ...” is corrected to read, “In this mode, the RAS5#/CS5# signal

becomes RAS5#/CS5#/MA13 ...”

Affected Docs: Intel® 430TX PCIset: 82439TX System Controller (MTXC) datasheet (order number 290559-001)

Table 18. SDRAM Performance Summary

Processor Cycle Type 60/66 MHz

CL=3

Five Rows (Max)

60/66 MHz

CL=2

Five Rows (Max)

Burst Read Page Hit 7-1-1-1 6-1-1-1

Read Row Miss19-1-1-1 8-1-1-1

Read Page Miss 12-1-1-1 11-1-1-1

Back-to-Back Burst Reads Page Hit 7-1-1-1-2-1-1-1 6-1-1-1-2-1-1-1

Write Page Hit2,3 33

Write Row Miss2,3 65

Write Page Miss2,3 98

Posted Write2,3 3-1-1-1 3-1-1-1

Write retire rate from Posted Write Buffer -1-1-1 -1-1-1

Reg 54h, Bit 5 (RCO)510

Reg 54h, Bit 4 (CL) 0 1

Reg 54h, Bit 3 (RT) 0 1

Reg 56h, Bit 4 (SLD)400

NOTES:

1. The row miss cycle assumes that the new page is closed from the prior cycle.

2. This cycle timing assumes the write buffer (DWB) is empty.

3. Write data is always posted as 3-1-1-1 (ADS# to BRDY#), if write buffers is available.

4. This bit (SLD) must be set to a 1 (speculative leadoff disable) in systems with cache and to 0 in systems

without cache.

5. For a CL=3 part that can not meet a RAS to CAS timing (Trcd) of two HCLKs, RCO can be set to 0. This

will add an HCLK to the leadoff cycle for Row miss and Page miss cycles.