1
File Number 796.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Americas Inc. |Copyright © Intersil Americas Inc. 2001
CA124, CA224, CA324, LM324, LM2902
Quad, 1MHz, Operational Amplifiers for
Commercial, Industrial, and Military
Applications
The CA124, CA224, CA324, LM324, and LM2902 consist of
four independent, high-gain operational amplifiers on a
single monolithic substrate. An on-chip capacitor in each of
the amplifiers provides frequency compensation for unity
gain. These devices are designed specially to operate from
either single or dual supplies, and the differential voltage
range is equal to the power-supply voltage. Low power drain
and an input common-mode voltage range from 0V to V+
-1.5V (single-supply operation) make these devices suitable
for battery operation.
Features
• Operation from Single or Dual Supplies
• Unity-GainBandwidth ...................1MHz(Typ)
• DCVoltageGain ......................100dB(Typ)
• InputBiasCurrent......................45nA(Typ)
• InputOffsetVoltage..................... 2mV(Typ)
• Input Offset Current
- CA224, CA324, LM324, LM2902 . . ........5nA(Typ)
- CA124...............................3nA(Typ)
• Replacement for Industry Types 124, 224, 324
Applications
• Summing Amplifiers
• Multivibrators
• Oscillators
• Transducer Amplifiers
• DC Gain Blocks
Pinout
CA124, CA224, CA324, LM2902 (PDIP, SOIC)
LM324 (PDIP)
TOP VIEW
Part Number Information
PART
NUMBER
(BRAND) TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CA0124E -55 to 125 14 Ld PDIP E14.3
CA0124M
(124) -55 to 125 14 Ld SOIC M14.15
CA0124M96
(124) -55 to 125 14 Ld SOIC Tape and
Reel M14.15
CA0224E -40 to 85 14 Ld PDIP E14.3
CA0224M
(224) -40to85 14LdSOIC M14.15
CA0324E 0 to 70 14 Ld PDIP E14.3
CA0324M
(324) 0to70 14LdSOIC M14.15
CA0324M96
(324) 0to70 14LdSOICTapeand
Reel M14.15
LM324N 0 to 70 14 Ld PDIP E14.3
LM2902N -40 to 85 14 Ld PDIP E14.3
LM2902M
(2902) -40to85 14LdSOIC M14.15
LM2902M96
(2902) -40to85 14LdSOICTapeand
Reel M14.15
1
2
3
4
5
6
7
14
13
12
11
10
9
8
+
1
+
4
+
2
+
3
OUTPUT 1
OUTPUT 2
OUTPUT 4
V-
OUTPUT 3
V+
POS.
INPUT 2
POS.
INPUT 1
NEG.
INPUT 1
NEG.
INPUT 3
POS.
INPUT 3
POS.
INPUT 4
NEG.
INPUT 4
NEG.
INPUT 2
Data Sheet May 2001
itle
12
224
324
324
290
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ad,
Hz,
ra-
al
pli-
s
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-
,
us-
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i-
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tho
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er-
OBSOLETEPRODUCT
NORECOMMENDEDREPLACEMENT
2
Absolute Maximum Ratings Thermal Information
SupplyVoltage................................32Vor±16V
DifferentialInputVoltage...............................32V
InputVoltage.................................-0.3Vto32V
Input Current (VI<-0.3V,Note1) ......................50mA
Output Short Circuit Duration (V+ ≤15V, Note 2) . . . . . .Continuous
Operating Conditions
Temperature Range
CA124 .................................-55
oCto125
oC
CA224,LM2902...........................-40
oCto85
oC
CA324,LM324..............................0
oCto70
oC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIPPackage............................. 95
SOICPackage............................. 175
MaximumJunctionTemperature(Die)...................175
oC
Maximum Junction Temperature (Plastic Package). . . . . . . . .150oC
MaximumStorageTemperatureRange.......... -65
oCto150
oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. This input current will only exist when the voltage at any of the input leads is driven negative. This current is due to the collector base junction of the
input p-n-p transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral n-p-n
parasitic transistor action on the IC chip. This transistor action can cause the output voltages of the amplifiers to go to the V+ voltage level (or to ground
for a large overdrive) for the time duration that an input is driven negative. This transistor action is not destructive and normal output states will re-
establish when the input voltage, which was negative, again returns to a value greater than -0.3V.
2. The maximum output current is approximately 40mA independent of the magnitude of V+. Continuous short circuits at V+ > 15V can cause
excessive power dissipation and eventual destruction. Short circuits from the output to V+ can cause overheating and eventual destruction of
the device.
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Values Apply for Each Operational Amplifier. Supply Voltage V+ = 5V, V- = 0V,
Unless Otherwise Specified
PARAMETER TEST
CONDITIONS TEMP.
(oC)
CA124 CA224, CA324, LM324 LM2902
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
Input Offset
Voltage (Note 6) 25-25-27---mV
Full--7--9--10mV
Average Input
Offset Voltage
Drift
RS=0ΩFull-7--7--7-µV/oC
Differential Input
Voltage (Note 5) Full--V+--V+--V+V
Input Common
Mode Voltage
Range (Note 5)
V+ = 30V 25 0 - V+ -1.5 0 - V+ -1.5 - - - V
V+ = 30V Full 0 - V+ -2 0 - V+ -2 - - - V
V+=26V Full------0-V+-2V
Common Mode
Rejection Ratio DC 25 70 85 - 65 70 - - - - dB
Power Supply
Rejection Ratio DC 25 65 100 - 65 100 - - - - dB
Input Bias
Current (Note 4) II+orI
I- 25 - 45 150 - 45 250 - - - nA
II+orI
I- Full - - 300 - - 500 - 40 500 nA
Input Offset
Current II+-I
I- 25- 330- 550- - -nA
II+-I
I- Full - - 100 - - 150 - 45 200 nA
Average Input
Offset Current
Drift
Full-10- -10- -10-pA/
oC
Large Signal
Voltage Gain RL≥2kΩ,V+=15V
(For Large VOSwing) 25 94 100 - 88 100 - - - - dB
RL≥2kΩ,V+=15V
(For Large VOSwing) Full 88 - - 83 - - 83 - - dB
CA124, CA224, CA324, LM324, LM2902
3
Schematic Diagram (One of Four Operational Amplifiers)
Output
Voltage
Swing
RL=2kΩ250-V+-1.50-V+-1.5---V
High
Level RL= 2kΩ, V+ = 30V Full 26 - - 26 - - - - - V
RL= 2kΩ,V+=26VFull------22--V
RL=10kΩ, V+ = 30V Full 27 28 - 27 28 - 23 28 - V
Low
Level RL=10kΩFull-520-520-5100mV
Output
Current Source VI+=+1V,V
I-=0V,
V+ = 15V 25 20 40 - 20 40 - - - - mA
VI+=1V,V
I-=0,
V+ = 15V Full 10 20 - 10 20 - 10 20 - mA
Sink VI+=0V,V
I-=1V,
V+ = 15V 25 10 20 - 10 20 - - - - mA
VI+=0V,V
I-=1V,
VO=200mV 25 12 50 - 12 50 - - - - µA
VI-=1V,V
I+=0,
V+ = 15V Full58-58-58-mA
Crosstalk f = 1 to 20kHz
(Input Referred) 25 - -120 - - -120 - - - - dB
Total Supply
Current RL=∞Full-0.82 -0.82 -0.71.2mA
RL=∞,V+=26VFull-------1.53mA
NOTES:
4. Due to the PNP input stage the direction of the input current is out of the IC. No loading change exists on the input lines because the current is
essentially constant, independent of the state of the output.
5. The input signal voltage and the input common mode voltage should not be allowed to go negative by more than 0.3V. The positive limit of the
common mode voltage rangeis V+ - 1.5V, but either or both inputs can go to +32V without damage.
6. VO=1.4V,R
S=0Ωwith V+ from 5V to 30V, and over the full input common mode voltage range (0V to V+ - 1.5V).
Electrical Specifications Values Apply for Each Operational Amplifier. Supply Voltage V+ = 5V, V- = 0V,
Unless Otherwise Specified (Continued)
PARAMETER TEST
CONDITIONS TEMP.
(oC)
CA124 CA224, CA324, LM324 LM2902
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX
11
3
2
4
1
6
5+
-2 7
9
10 +
-3 8
13
12 +
-4 4
TO 2, 3, 4
TO 2, 3, 4
VO
RSC
Q6
Q5
Q7
Q12 50µA
100
µA
Q11
Q10
CCOMP
4µA
6µA
Q9
Q4
Q3
Q2
V+
Q8
Q1
INPUTS
-
+
Q13
V-
CA124, CA224, CA324, LM324, LM2902
4
Typical Performance Curves
FIGURE 1. OPEN LOOP FREQUENCY RESPONSE FIGURE 2. VOLTAGE FOLLOWER PULSE RESPONSE
(SMALL SIGNAL)
FIGURE 3. VOLTAGE FOLLOWER PULSE RESPONSE (LARGE SIGNAL)
FIGURE 4. INPUT CURRENT vs AMBIENT TEMPERATURE FIGURE 5. SUPPLY CURRENT vs SUPPLY VOLTAGE
140
120
100
80
60
40
20
01 10 100 1K 10K 100K 1M 10M
FREQUENCY (Hz)
OPEN-LOOP VOLTAGE GAIN (dB)
TA=-40≤TA≤85oC
V+=10TO15V V+=26V
V+
VO
V+/2
VI
0.1µF
11
4
+
-
3
21
OUTPUT
INPUT
TA=25
oC
V+ = 30V
500
450
400
350
300
2500123456789
TIME (µs)
OUTPUT VOLTAGE (mV)
VO
VI50pF
1
2
3-
+
TA=25
oC
V+ = 15V
RL=2kΩ
4
3
2
1
010203040
4
3
2
1
0
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TIME (µs)
TEMPERATURE (oC)
INPUT CURRENT (nA)
-75 -50 -25 0 25 50 75 100 125
0
10
20
30
40
50
60
VICR =0V
V+=30V
15V
5V
4
3
2
1
0 5 10 15 20 25 30
POSITIVE SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
TA=0
oC TO 125oC
-55oC
0
ID
V+
3
2
mA
1
-
+
11
4
CA124, CA224, CA324, LM324, LM2902
5
FIGURE 6. LARGE SIGNAL FREQUENCY RESPONSE FIGURE 7. OUTPUT CURRENT vs AMBIENT TEMPERATURE
FIGURE 8. INPUT CURRENT vs SUPPLY VOLTAGE FIGURE 9. VOLTAGE GAIN vs SUPPLY VOLTAGE
Typical Performance Curves (Continued)
20
15
10
5
01K 10K 100K 1M
FREQUENCY (Hz)
OUTPUT VOLTAGE SWING (V)
TA=25
oC
1kΩ
100kΩ
+15V
2kΩ
+7V +
-
VI
2
3
4
VO
1
11
TEMPERATURE (oC)
OUTPUT SOURCE CURRENT (mA)
-75 -50 -25 0 25 50 75 100 125
0
10
20
30
40
50
60
70
V+ = 15V
TA=25
oC
75
50
25
0 10203040
POSITIVE SUPPLY VOLTAGE (V)
INPUT CURRENT (nA)
POSITIVE SUPPLY VOLTAGE (V)
OPEN LOOP VOLTAGE GAIN (dB)
0 10203040
0
25
50
75
100
125
150
TA=25
oC
RL=20kΩ
RL=2kΩ
CA124, CA224, CA324, LM324, LM2902
6
CA124, CA224, CA324, LM324, LM2902
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpen-
dicular to datum .
7. eBand eCare measured at the lead tips with the leads uncon-
strained. eCmust be zero or greater.
8. B1maximumdimensionsdonotincludedambarprotrusions.Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
eA-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMINMAXMINMAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N14 149
Rev. 0 12/93
7
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality/iso.asp.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
2401 Palm Bay Rd.
Palm Bay, FL 32905
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100,RuedelaFusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
CA124, CA224, CA324, LM324, LM2902
Small Outline Plastic Packages (SOIC)
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions.Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER.Converted inch dimensions
are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
hx45
o
C
H
µ
0.25(0.010) BM M
α
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMINMAXMINMAX
A 0.0532 0.0688 1.35 1.75 -
A1 0.0040 0.0098 0.10 0.25 -
B 0.013 0.020 0.33 0.51 9
C 0.0075 0.0098 0.19 0.25 -
D 0.3367 0.3444 8.55 8.75 3
E 0.1497 0.1574 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.2284 0.2440 5.80 6.20 -
h 0.0099 0.0196 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N14 147
α0o8o0o8o-
Rev. 0 12/93