LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 LMR12015/LMR12020 SIMPLE SWITCHER(R) 20Vin, 1.5A/2A Step-Down Voltage Regulator in WSON-10 Check for Samples: LMR12015, LMR12020 FEATURES DESCRIPTION * The LMR12015/20 regulator is a monolithic, high frequency, PWM step-down DC-DC converter in a 10pin WSON package. It contains all the active functions to provide local DC-DC conversion with fast transient response and accurate regulation in the smallest possible PCB area. 1 23 * * * * * * * * * * * * Space Saving 3 x 3 x 0.8 mm WSON-10 Package Input Voltage Range of 3V to 20V Output Voltage Range of 1V to 18V LMR12015 and LMR12020 Deliver 1.5A and 2A Maximum Output Current Respectively 2 MHz Switching Frequency Frequency Synchronization from 1.00 MHz to 2.35 MHz 70 nA Shutdown Current 1% Voltage Reference Accuracy Peak Current Mode PWM Operation Thermal Shutdown Internally Compensated Internal Soft-Start WEBENCH(R) Enabled PERFORMANCE BENEFITS * * * Tight Accuracy for Powering Digital ICs Extremely Easy to Use Tiny Overall Solution Reduces System Cost With a minimum of external components the LMR12015/20 is easy to use. The ability to drive 1.5/2A loads respectively, with an internal 150 m NMOS switch results in the best power density available. The control circuitry allows for on-times as low as 65 ns, thus supporting exceptionally high frequency conversion. Switching frequency is internally set to 2 MHz and synchronizable from 1 to 2.35 MHz, which allows the use of extremely small surface mount inductors and chip capacitors. Even though the operating frequency is very high, efficiencies up to 90% are easy to achieve. External shutdown is included featuring an ultra-low shutdown current of 70 nA. The LMR12015/20 utilizes peak current mode control and internal compensation to provide high-performance regulation over a wide range of operating conditions. Additional features include internal soft-start circuitry to reduce inrush current, pulse-by-pulse current limit, thermal shutdown, and output over-voltage protection. APPLICATIONS * * Point-of-Load Conversions from 3.3V, 5V and 12V Rails Space Constrained Applications 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012-2013, Texas Instruments Incorporated LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com System Performance Efficiency vs Load Current LMR12015/20 VOUT = 3.3V, fsw = 2 MHz 100 95 94 90 88 85 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs Load Current LMR12015/20 VOUT = 5V, fsw = 2 MHz 82 76 70 Vin = 7V Vin = 8V Vin = 10V Vin = 12V Vin = 14V Vin = 16V Vin = 18V Vin = 20V 64 58 52 46 80 75 70 Vin = 5V Vin = 7V Vin = 9V Vin = 12V Vin = 14V Vin = 16V Vin = 18V Vin = 20 65 60 55 50 45 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 IOUT(A) 0.0 0.3 0.6 0.9 1.2 IOUT(A) 1.5 1.8 2.1 Typical Application Circuit VIN PVIN BOOST C2 AVIN L1 C1 VOUT SW LMR12015/20 ON C3 D1 EN OFF R1 SYNC CLK FB GND/DAP R2 Connection Diagram SW 1 10 PVIN SW 2 9 PVIN BOOST 3 8 AVIN EN 4 7 GND SYNC 5 6 FB DAP 10 - Lead WSON (Top View) See Package Number DSC 2 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name Function 1,2 SW 3 BOOST Output switch. Connects to the inductor, catch diode, and bootstrap capacitor. 4 EN 5 SYNC 6 FB 7 GND Signal and Power Ground pin. Place the bottom resistor of the feedback network as close as possible to this pin for accurate regulation. Boost voltage that drives the internal NMOS control switch. A bootstrap capacitor is connected between the BOOST and SW pins. Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN + 0.3V. Frequency synchronization input. Drive this pin with an external clock or pulse train. Ground it to use the internal clock. Feedback pin. Connect FB to the external resistor divider to set output voltage. 8 AVIN Supply voltage for the control circuitry. 9,10 PVIN Supply voltage for output power stage. Connect a bypass capacitor to this pin. DAP GND Signal / Power Ground and thermal connection. Tie this directly to GND (pin 7). See APPLICATION INFORMATION regarding optimum thermal layout. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 3 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) AVIN, PVIN -0.5V to 24V SW Voltage -0.5V to 24V Boost Voltage -0.5V to 28V Boost to SW Voltage -0.5V to 6.0V FB Voltage -0.5V to 3.0V SYNC Voltage -0.5V to 6.0V EN Voltage -0.5V to (VIN + 0.3V) Storage Temperature Range -65C to +150C Junction Temperature ESD Susceptibility 150C (3) 2kV Soldering Information Infrared Reflow (5sec) (1) (2) (3) 260C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human body model, 1.5 k in series with 100 pF. Operating Ratings (1) AVIN, PVIN 3V to 20V SW Voltage -0.5V to 20V Boost Voltage -0.5V to 24V Boost to SW Voltage 3.0V to 5.5V Junction Temperature Range -40C to +125C Thermal Resistance (JA) WSON (DSC) (2) (1) (2) 4 33C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and should not be operated beyond such conditions. All numbers apply for packages soldered directly onto a 3" x 3" PC board with 2oz. copper on 4 layers in still air. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 Electrical Characteristics Specifications with standard typeface are for TJ = 25C, and those in boldface type apply over the full Operating Temperature Range (TJ = -40C to 125C). VIN = 12V, and VBOOST - VSW = 4.3V unless otherwise specified. Datasheet min/max specification limits are ensured by design, test, or statistical analysis. Symbol Parameter Conditions Min Typ Max TJ = 0C to 85C 0.990 1.0 1.010 TJ = -40C to 125C 0.984 1.0 1.014 Units SYSTEM PARAMETERS VFB Feedback Voltage VFB/VIN Feedback Voltage Line Regulation IFB OVP UVLO SS IQ VIN = 3V to 20V 0.003 Feedback Input Bias Current 20 Over Voltage Protection, VFB at which PWM Halts. V %/V 100 nA 1.13 Undervoltage Lockout UVLO Hysteresis V VIN Rising until VSW is Switching 2.60 2.75 2.90 VIN Falling from UVLO 0.30 0.47 0.6 0.5 1 1.5 Soft Start Time V ms Quiescent Current, IQ = IQ_AVIN + IQ_PVIN VFB = 1.1 (not switching) 2.4 mA Quiescent Current, IQ = IQ_AVIN + IQ_PVIN VEN = 0V (shutdown) 70 nA fSW= 2 MHz 8.2 10 fSW= 1 MHz 4.4 6 2 2.3 IBOOST Boost Pin Current mA OSCILLATOR fSW Switching Frequency SYNC = GND VFB_FOLD FB Pin Voltage where SYNC input is overridden. fFOLD_MIN Frequency Foldback Minimum 1.75 MHz 0.53 VFB = 0V 220 V 250 kHz 2.35 MHz LOGIC INPUTS (EN, SYNC) fSYNC SYNC Frequency Range 1 VIL EN, SYNC Logic low threshold Logic Falling Edge VIH EN, SYNC Logic high threshold Logic Rising Edge 0.4 1.8 V tSYNC_HIGH SYNC, Time Required above VIH to Ensure a Logical High. 100 ns tSYNC_LOW SYNC, Time Required below VIL to Ensure a Logical Low. 100 ns ISYNC SYNC Pin Current IEN Enable Pin Current VSYNC < 5V 20 nA VEN = 3V 6 15 VIN = VEN = 20V 50 100 150 320 A INTERNAL MOSFET RDS(ON) ICL DMAX Switch ON Resistance Switch Current Limit Maximum Duty Cycle LMR12020 2.5 4.0 LMR12015 2.0 3.7 SYNC = GND 85 m A 93 % tMIN Minimum on time 65 ns ISW Switch Leakage Current 40 nA 3.9 V Junction temperature rising 165 C Junction temperature hysteresis 15 C BOOST LDO VLDO Boost LDO Output Voltage THERMAL TSHDN Thermal Shutdown Temperature (1) Thermal Shutdown Hysteresis (1) Thermal shutdown will occur if the junction temperature exceeds 165C. The maximum power dissipation is a function of TJ(MAX) , JA and TA . The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/JA . Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 5 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS All curves taken at VIN = 12V, VBOOST - VSW = 4.3V and TA = 25C, unless specified otherwise. Efficiency vs Load Current VOUT = 5V, fSW = 2 MHz Refer to Figure 37 Load Transient VOUT = 5V, IOUT = 100 mA - 2A @ slewrate = 2A / s Refer to Figure 37 100 94 EFFICIENCY (%) 88 82 76 70 Vin = 7V Vin = 8V Vin = 10V Vin = 12V Vin = 14V Vin = 16V Vin = 18V Vin = 20V 64 58 52 46 40 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 IOUT(A) Figure 1. Figure 2. Efficiency vs Load Current VOUT = 3.3V, fSW = 2 MHz Refer to Figure 39 Load Transient VOUT = 3.3V, IOUT = 100 mA - 2A @ slewrate = 2A / s Refer to Figure 39 95 90 EFFICIENCY (%) 85 80 75 70 Vin = 5V Vin = 7V Vin = 9V Vin = 12V Vin = 14V Vin = 16V Vin = 18V Vin = 20 65 60 55 50 45 0.0 6 0.3 0.6 0.9 1.2 IOUT(A) 1.5 1.8 2.1 Figure 3. Figure 4. Efficiency vs Load Current VOUT = 1.8V, fSW = 2 MHz Refer to Figure 40 Load Transient VOUT = 1.8V, IOUT = 100 mA - 2A @ slewrate = 2A / s Refer to Figure 40 Figure 5. Figure 6. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) All curves taken at VIN = 12V, VBOOST - VSW = 4.3V and TA = 25C, unless specified otherwise. Line Transient VIN = 10 to 15V, VOUT = 3.3V, no CFF Refer to Figure 39 Line Transient VIN = 10 to 15V, VOUT = 3.3V Refer to Figure 38 Figure 7. Figure 8. Short Circuit Short Circuit Release Figure 9. Figure 10. Soft Start Soft Start with EN Tied to VIN Figure 11. Figure 12. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 7 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) All curves taken at VIN = 12V, VBOOST - VSW = 4.3V and TA = 25C, unless specified otherwise. 8 VIN = 12V, VOUT = 5 V, L = 2.2 H, COUT = 44 F Iout =1A VIN = 12V, VOUT = 3.3V, L = 1.5 H COUT = 44 F Iout =1A Figure 13. Figure 14. VIN = 5V, VOUT = 1.8V, L = 1.0 H COUT = 44 F Iout =1A VIN = 5V, VOUT = 1.2V, L = 0.56 H COUT = 68 F Iout =1A Figure 15. Figure 16. Sync Functionality Loss of Synchronization Figure 17. Figure 18. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) All curves taken at VIN = 12V, VBOOST - VSW = 4.3V and TA = 25C, unless specified otherwise. Oscillator Frequency vs Temperature VSYNC = GND Oscillator Frequency vs VFB VSYNC = GND Figure 19. Figure 20. VFB vs Temperature VFB vs VIN Figure 21. Figure 22. Current Limit vs Temperature VIN = 12V RDSON vs Temperature Figure 23. Figure 24. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 9 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) All curves taken at VIN = 12V, VBOOST - VSW = 4.3V and TA = 25C, unless specified otherwise. 10 IQ (Shutdown) vs Temperature IQ = IAVIN + IPVIN IEN vs VEN Figure 25. Figure 26. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 Block Diagram BOOST D2 LDO PVIN C2 Switch 0.15: RSENSE L SW VOUT iL + AVIN C3 EN Under Voltage Lockout Current Limit D1 Driver Current Sense Amplifier PWM Logic PWM Comparator Reset Pulse Thermal Shutdown + + + OVP Comparator + ISENSE Error Signal 1.13V Corrective Ramp Soft Start SYNC Oscillator + - FB Internal Compensation + Error Amplifier + VREF +- R1 R2 1.0V GND + Freq. Foldback Amplifier 0.53V Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 + - Submit Documentation Feedback 11 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The LMR12015/20 is a constant-frequency, peak current-mode PWM buck regulator IC that delivers a 1.5 or 2A load current. The regulator has a preset switching frequency of 2 MHz. This high frequency allows the LMR12015/20 to operate with small surface mount capacitors and inductors, resulting in a DC-DC converter that requires a minimum amount of board space. The LMR12015/20 is internally compensated, which reduces design time, and requires few external components. The following operating description of the LMR12015/20 will refer to the Block Diagram and to the waveforms in Figure 27. The LMR12015/20 supplies a regulated output voltage by switching the internal NMOS switch at a constant frequency and varying the duty cycle. A switching cycle begins at the falling edge of the reset pulse generated by the internal oscillator. When this pulse goes low, the output control logic turns on the internal NMOS switch. During this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the inductor current (iL) increases with a linear slope. The current-sense amplifier measures iL, which generates an output proportional to the switch current typically called the sense signal. The sense signal is summed with the regulator's corrective ramp and compared to the error amplifier's output, which is proportional to the difference between the feedback voltage (VFB) and VREF. When the output of the PWM comparator goes high, the switch turns off until the next switching cycle begins. During the switch off-time (tOFF), inductor current discharges through the catch diode D1, which forces the SW pin (VSW) to swing below ground by the forward voltage (VD1) of the catch diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage. VSW D = tON/TSW SW Voltage VIN tOFF tON 0 -VD1 t Inductor Current iL TSW ILPK IOUT 'iL t 0 Figure 27. LMR12015/20 Waveforms of SW Pin Voltage and Inductor Current 12 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 BOOST FUNCTION Capacitor C2 in Block Diagram, commonly referred to as CBOOST, is used to store a voltage VBOOST. When the LMR12015/20 starts up, an internal LDO charges CBOOST ,via an internal diode, to a voltage sufficient to turn the internal NMOS switch on. The gate drive voltage supplied to the internal NMOS switch is VBOOST - VSW. During a normal switching cycle, when the internal NMOS control switch is off (tOFF) (refer to Figure 27), VBOOST equals VLDO minus the forward voltage of the internal diode (VD2). At the same time the inductor current (iL) forward biases the catch diode D1 forcing the SW pin to swing below ground by the forward voltage drop of the catch diode (VD1). Therefore, the voltage stored across CBOOST is VBOOST - VSW = VLDO - VD2 + VD1 (1) Thus, VBOOST = VSW + VLDO - VD2 + VD1 (2) When the NMOS switch turns on (tON), the switch pin rises to VSW = VIN - (RDSON x IL), (3) reverse biasing D1, and forcing VBOOST to rise. The voltage at VBOOST is then VBOOST = VIN - (RDSON x IL) + VLDO - VD2 + VD1 (4) which is approximately VIN + VLDO- 0.4V (5) VBOOST has pulled itself up by its "bootstraps", or boosted to a higher voltage. LOW INPUT VOLTAGE CONSIDERATIONS When the input voltage is below 5V and the duty cycle is greater than 75 percent, the gate drive voltage developed across CBOOST might not be sufficient for proper operation of the NMOS switch. In this case, CBOOST should be charged via an external Schottky diode attached to a 5V voltage rail, see Figure 28. This ensures that the gate drive voltage is high enough for proper operation of the NMOS switch in the triode region. Maintain VBOOST - VSW less than the 6V absolute maximum rating. D2 VIN PVIN 5V BOOST C2 AVIN L1 C1 VOUT SW LMR12015/20 C3 D1 ON EN OFF R1 SYNC CLK FB GND/DAP R2 Figure 28. External Diode Charges CBOOST Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 13 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com HIGH OUTPUT VOLTAGE CONSIDERATIONS When the output voltage is greater than 3.3V, a minimum load current is needed to charge CBOOST, see Figure 29. The minimum load current forward biases the catch diode D1 forcing the SW pin to swing below ground. This allows CBOOST to charge, ensuring that the gate drive voltage is high enough for proper operation. The minimum load current depends on many factors including the inductor value. Figure 29. Minimum Load Current for L = 1.5 H ENABLE PIN / SHUTDOWN MODE Connect the EN pin to a voltage source greater than 1.8V to enable operation of the LMR12015/20. Apply a voltage less than 0.4V to put the part into shutdown mode. In shutdown mode the quiescent current drops to typically 70 nA. Switch leakage adds another 40 nA from the input supply. For proper operation, the LMR12015/20 EN pin should never be left floating, and the voltage should never exceed VIN + 0.3V. The simplest way to enable the operation of the LMR12015/20 is to connect the EN pin to AVIN which allows self start-up of the LMR12015/20 when the input voltage is applied. When the rise time of VIN is longer than the soft-start time of the LMR12015/20 this method may result in an overshoot in output voltage. In such applications, the EN pin voltage can be controlled by a separate logic signal, or tied to a resistor divider, which reaches 1.8V after VIN is fully established (see Figure 30). This will minimize the potential for output voltage overshoot during a slow VIN ramp condition. Use the lowest value of VIN , seen in your application when calculating the resistor network, to ensure that the 1.8V minimum EN threshold is reached. VIN PVIN BOOST C2 AVIN L1 C1 R3 VOUT SW C3 D1 LMR12015/20 EN R4 R1 SYNC CLK FB GND/DAP R2 Figure 30. Resistor Divider on EN R3 = 14 VIN - 1 x R4 1.8 Submit Documentation Feedback (6) Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 FREQUENCY SYNCHRONIZATION The LMR12015/20 switching frequency can be synchronized to an external clock, between 1.00 and 2.35 MHz, applied at the SYNC pin. At the first rising edge applied to the SYNC pin, the internal oscillator is overridden and subsequent positive edges will initiate switching cycles. If the external SYNC signal is lost during operation, the LMR12015/20 will revert to its internal 2 MHz oscillator within 1.5 s. To disable Frequency Synchronization and utilize the internal 2 MHz oscillator, connect the SYNC pin to GND. The SYNC pin gives the designer the flexibility to optimize their design. A lower switching frequency can be chosen for higher efficiency. A higher switching frequency can be chosen to keep EMI out of sensitive ranges such as the AM radio band. Synchronization can also be used to eliminate beat frequencies generated by the interaction of multiple switching power converters. Synchronizing multiple switching power converters will result in cleaner power rails. The selected switching frequency (fSYNC) and the minimum on-time (tMIN) limit the minimum duty cycle (DMIN) of the device. DMIN= tMIN x fSYNC (7) Operation below DMIN is not reccomended. The LMR12015/20 will skip pulses to keep the output voltage in regulation, and the current limit is not ensured. The switching is in phase but no longer at the same switching frequency as the SYNC signal. CURRENT LIMIT The LMR12015/20 use cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a current limit comparator detects if the output switch current exceeds 2.0A min (LMR12015) or 2.5A min (LMR12020) , and turns off the switch until the next switching cycle begins. FREQUENCY FOLDBACK The LMR12015/20 employs frequency foldback to protect the device from current run-away during output shortcircuit. Once the FB pin voltage falls below regulation, the switch frequency will smoothly reduce with the falling FB voltage until the switch frequency reaches 220 kHz (typ). If the device is synchronized to an external clock, synchronization is disabled until the FB pin voltage exceeds 0.53V SOFT-START The LMR12015/20 has a fixed internal soft-start of 1 ms (typ). During soft-start, the error amplifier's reference voltage ramps from 0.0 V to its nominal value of 1.0 V in approximately 1 ms. This forces the regulator output to ramp in a controlled fashion, which helps reduce inrush current. Upon soft-start the part will initially be in frequency foldback and the frequency will rise as FB rises. The regulator will gradually rise to 2 MHz. The LMR12015/20 will allow synchronization to an external clock at FB > 0.53V. OUTPUT OVERVOLTAGE PROTECTION The overvoltage comparator turns off the internal power NFET when the FB pin voltage exceeds the internal reference voltage by 13% (VFB > 1.13 * VREF). With the power NFET turned off the output voltage will decrease toward the regulation level. UNDERVOLTAGE LOCKOUT Undervoltage lockout (UVLO) prevents the LMR12015/20 from operating until the input voltage exceeds 2.75V(typ). The UVLO threshold has approximately 470 mV of hysteresis, so the part will operate until VIN drops below 2.28V(typ). Hysteresis prevents the part from turning off during power up if VIN has finite impedance. THERMAL SHUTDOWN Thermal shutdown limits total power dissipation by turning off the internal NMOS switch when the IC junction temperature exceeds 165C (typ). After thermal shutdown occurs, hysteresis prevents the internal NMOS switch from turning on until the junction temperature drops to approximately 150C. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 15 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com Design Guide INDUCTOR SELECTION Inductor selection is critical to the performance of the LMR12015/20. The selection of the inductor affects stability, transient response and efficiency. A key factor in inductor selection is determining the ripple current (iL) (see Figure 27). The ripple current (iL) is important in many ways. First, by allowing more ripple current, lower inductance values can be used with a corresponding decrease in physical dimensions and improved transient response. On the other hand, allowing less ripple current will increase the maximum achievable load current and reduce the output voltage ripple (see Output Capacitor section for more details on calculating output voltage ripple). Increasing the maximum load current is achieved by ensuring that the peak inductor current (ILPK) never exceeds the minimum current limit of 2.0A min (LMR12015) or 2.5A min (LMR12020) . ILPK = IOUT + iL / 2 (8) Secondly, the slope of the ripple current affects the current control loop. The LMR12015/20 has a fixed slope corrective ramp. When the slope of the current ripple becomes significantly less than the converter's corrective ramp (see Block Diagram), the inductor pole will move from high frequencies to lower frequencies. This negates one advantage that peak current-mode control has over voltage-mode control, which is, a single low frequency pole in the power stage of the converter. This can reduce the phase margin, crossover frequency and potentially cause instability in the converter. Contrarily, when the slope of the ripple current becomes significantly greater than the converter's corrective ramp, resonant peaking can occur in the control loop. This can also cause instability (Sub-Harmonic Oscillation) in the converter. For the power supply designer this means that for lower switching frequencies the current ripple must be increased to keep the inductor pole well above crossover. It also means that for higher switching frequencies the current ripple must be decreased to avoid resonant peaking. With all these factors, how is the desired ripple current selected? The ripple ratio (r) is defined as the ratio of inductor ripple current (iL) to output current (IOUT), evaluated at maximum load: r= 'iL lOUT (9) A good compromise between physical size, transient response and efficiency is achieved when we set the ripple ratio between 0.2 and 0.4. The recommended ripple ratio vs. duty cycle shown below (see Figure 31) is based upon this compromise and control loop optimizations. Note that this is just a guideline. Please see Application note AN-1197 SNVA038 for further considerations. Figure 31. Recommended Ripple Ratio Vs. Duty Cycle 16 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 The Duty Cycle (D) can be approximated quickly using the ratio of output voltage (VOUT) to input voltage (VIN): D= VOUT VIN (10) The application's lowest input voltage should be used to calculate the ripple ratio. The catch diode forward voltage drop (VD1) and the voltage drop across the internal NFET (VDS) must be included to calculate a more accurate duty cycle. Calculate D by using the following formula: D= VOUT + VD1 VIN + VD1 - VDS (11) VDS can be approximated by: VDS = IOUT x RDS(ON) (12) The diode forward drop (VD1) can range from 0.3V to 0.5V depending on the quality of the diode. The lower VD1 is, the higher the operating efficiency of the converter. Now that the ripple current or ripple ratio is determined, the required inductance is calculated by: VOUT + VD1 x (1-DMIN) L= IOUT x r x fSW (13) where DMIN is the duty cycle calculated with the maximum input voltage, fsw is the switching frequency, and IOUT is the maximum output current of 2A. Using IOUT = 2A will minimize the inductor's physical size. INDUCTOR CALCULATION EXAMPLE Operating conditions for the LMR12015/20 are: VIN = 7 - 16V fSW = 2 MHz VOUT = 3.3V VD1 = 0.5V IOUT = 2A (14) (15) (16) (17) (18) First the maximum duty cycle is calculated. DMAX= (VOUT + VD1) / (VIN + VD1 - VDS) = (3.3V + 0.5V) / (7V + 0.5V - 0.30V) = 0.528 (19) Using Figure 31 gives us a recommended ripple ratio = 0.4. Now the minimum duty cycle is calculated. DMIN= (VOUT + VD1) / (VIN + VD1 - VDS) = (3.3V + 0.5V) / (16V + 0.5V - 0.30V) = 0.235 (20) The inductance can now be calculated. L= (1 - DMIN) x (VOUT + VD1) / (IOUT x r x fsw) = (1 - 0.235) x (3.3V + .5V) / (2A x 0.4 x 2 MHz) = 1.817 H (21) This is close to the standard inductance value of 1.8 H. This leads to a 1% deviation from the recommended ripple ratio, which is now 0.4038. Finally, we check that the peak current does not reach the minimum current limit of 2.5A. ILPK = IOUT x (1 + r / 2) = 2A x (1 + .4038 / 2 ) = 2.404A (22) The peak current is less than 2.5A, so the DC load specification can be met with this ripple ratio. To design for the LMR12015 simply replace IOUT = 1.5A in the equations for ILPK and see that ILPK does not exceed the LMR12015's current limit of 2.0A (min). Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 17 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com INDUCTOR MATERIAL SELECTION When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating. Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating correctly. To prevent the inductor from saturating over the entire -40 C to 125 C range, pick an inductor with a saturation current higher than the upper limit of ICL listed in the Electrical Characteristics table. Ferrite core inductors are recommended to reduce AC loss and fringing magnetic flux. The drawback of ferrite core inductors is their quick saturation characteristic. The current limit circuit has a propagation delay and so is oftentimes not fast enough to stop a saturated inductor from going above the current limit. This has the potential to damage the internal switch. To prevent a ferrite core inductor from getting into saturation, the inductor saturation current rating should be higher than the switch current limit ICL. The LMR12015/20 is quite robust in handling short pulses of current that are a few amps above the current limit. Saturation protection is provided by a second current limit which is 30% higher than the cycle by cycle current limit. When the saturation protection is triggered the part will turn off the output switch and attempt to soft-start. (When a compromise has to be made, pick an inductor with a saturation current just above the lower limit of the ICL.) Be sure to validate the short-circuit protection over the intended temperature range. An inductor's saturation current is usually lower when hot. So consult the inductor vendor if the saturation current rating is only specified at room temperature. Soft saturation inductors such as the iron powder types can also be used. Such inductors do not saturate suddenly and therefore are safer when there is a severe overload or even shorted output. Their physical sizes are usually smaller than the Ferrite core inductors. The downside is their fringing flux and higher power dissipation due to relatively high AC loss, especially at high frequencies. INPUT CAPACITOR An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The primary specifications of the input capacitor are capacitance, voltage, RMS current rating, and Equivalent Series Inductance (ESL). The recommended input capacitance is 10 F, although 4.7 F works well for input voltages below 6V. The input voltage rating is specifically stated by the capacitor manufacturer. Make sure to check any recommended deratings and also verify if there is any significant change in capacitance at the operating input voltage and the operating temperature. The input capacitor maximum RMS input current rating (IRMS-IN) must be greater than: IRMS-IN = IOUT x r2 Dx 1-D+ 12 where * * * r is the ripple ratio defined earlier IOUT is the output current, and D is the duty cycle (23) It can be shown from the above equation that maximum RMS capacitor current occurs when D = 0.5. Always calculate the RMS at the point where the duty cycle, D, is closest to 0.5. The ESL of an input capacitor is usually determined by the effective cross sectional area of the current path. A large leaded capacitor will have high ESL and a 0805 ceramic chip capacitor will have very low ESL. At the operating frequencies of the LMR12015/20, certain capacitors may have an ESL so large that the resulting impedance (2fL) will be higher than that required to provide stable operation. As a result, surface mount capacitors are strongly recommended. Sanyo POSCAP, Tantalum or Niobium, Panasonic SP or Cornell Dubilier Low ESR are all good choices for input capacitors and have acceptable ESL. Multilayer ceramic capacitors (MLCC) have very low ESL. For MLCCs it is recommended to use X7R or X5R dielectrics. Consult the capacitor manufacturer's datasheet to see how rated capacitance varies over operating conditions. 18 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 OUTPUT CAPACITOR The output capacitor is selected based upon the desired output ripple and transient response. The LMR12015/20's loop compensation is designed for ceramic capacitors. A minimum of 22 F is required at 2 MHz (33 uF at 1 MHz) while 47 - 100 F is recommended for improved transient response and higher phase margin. The output voltage ripple of the converter is: 'VOUT = 'iL x (RESR + 1 ) 8 x fSW x COUT (24) When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the output ripple will be approximately sinusoidal and 90 phase shifted from the switching action. Another benefit of ceramic capacitors is their ability to bypass high frequency noise. A certain amount of switching edge noise will couple through parasitic capacitances in the inductor to the output. A ceramic capacitor will bypass this noise while a tantalum will not. The transient response is determined by the speed of the control loop and the ability of the output capacitor to provide the initial current of a load transient. Capacitance can be increased significantly with little detriment to the regulator stability. However, increasing the capacitance provides dimininshing improvement over 100 uF in most applications, because the bandwidth of the control loop decreases as output capacitance increases. If improved transient performance is required, add a feed forward capacitor. This becomes especially important for higher output voltages where the bandwidth of the LMR12015/20 is lower. See Feed Forward Capacitor and Frequency Synchronization sections. Check the RMS current rating of the capacitor. The RMS current rating of the capacitor chosen must also meet the following condition: IRMS-OUT = IOUT x r 12 where * * IOUT is the output current, and r is the ripple ratio. (25) CATCH DIODE The catch diode (D1) conducts during the switch off-time. A Schottky diode is recommended for its fast switching times and low forward voltage drop. The catch diode should be chosen so that its current rating is greater than: ID1 = IOUT x (1-D) (26) The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin. To improve efficiency choose a Schottky diode with a low forward voltage drop. BOOST DIODE (OPTIONAL) For circuits with input voltages VIN < 5V and duty cycles (D) >0.75V. a small-signal Schottky diode is recommended. A good choice is the BAT54 small signal diode. The cathode of the diode is connected to the BOOST pin and the anode to a 5V voltage rail. BOOST CAPACITOR A ceramic 0.1 F capacitor with a voltage rating of at least 6.3V is sufficient. The X7R and X5R MLCCs provide the best performance. OUTPUT VOLTAGE The output voltage is set using the following equation where R2 is connected between the FB pin and GND, and R1 is connected between VOUT and the FB pin. A good starting value for R2 is 1 k. R1 = VOUT VREF - 1 x R2 (27) Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 19 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com FEED FORWARD CAPACITOR (OPTIONAL) A feed forward capacitor CFF can improve the transient response of the converter. Place CFF in parallel with R1. The value of CFF should place a zero in the loop response at, or above, the pole of the output capacitor and RLOAD. The CFF capacitor will increase the crossover frequency of the design, thus a larger minimum output capacitance is required for designs using CFF. CFF should only be used with an output capacitance greater than or equal to 44 uF. Example waveforms of load transient with and without the CFF caps are as shown below. VOUT x COUT CFF <= IOUT x R1 (28) Figure 32. LMR12015/20 Load Transient with CFF cap VOUT = 3.3V Figure 33. LMR12015/20 Load Transient without CFF cap VOUT = 3.3V 20 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 Calculating Efficiency, and Junction Temperature The complete LMR12015/20 DC-DC converter efficiency can be calculated in the following manner. POUT K= PIN (29) Or K= POUT POUT + PLOSS (30) Calculations for determining the most significant power losses are shown below. Other losses totaling less than 2% are not discussed. Power loss (PLOSS) is the sum of two basic types of losses in the converter, switching and conduction. Conduction losses usually dominate at higher output loads, where as switching losses remain relatively fixed and dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D). D= VOUT + VD1 VIN + VD1 - VDS (31) VDS is the voltage drop across the internal NFET when it is on, and is equal to: VDS = IOUT x RDSON (32) VD is the forward voltage drop across the Schottky diode. It can be obtained from the Electrical Characteristics section of the schottky diode datasheet. If the voltage drop across the inductor (VDCR) is accounted for, the equation becomes: D= VOUT + VD1 + VDCR VIN + VD1 - VDS (33) VDCR usually gives only a minor duty cycle change, and has been omitted in the examples for simplicity. SCHOTTKY DIODE CONDUCTION LOSSES The conduction losses in the free-wheeling Schottky diode are calculated as follows: PDIODE = VD1 x IOUT (1-D) (34) Often this is the single most significant power loss in the circuit. Care should be taken to choose a Schottky diode that has a low forward voltage drop. INDUCTOR CONDUCTION LOSSES Another significant external power loss is the conduction loss in the output inductor. The equation can be simplified to: PIND = IOUT2 x RDCR (35) MOSFET CONDUCTION LOSSES The LMR12015/20 conduction loss is mainly associated with the internal NFET: PCOND = IOUT2 x RDSON x D (36) MOSFET SWITCHING LOSSES Switching losses are also associated with the internal NFET. They occur during the switch on and off transition periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node: PSWF = 1/2(VIN x IOUT x fSW x tFALL) PSWR = 1/2(VIN x IOUT x fSW x tRISE) PSW = PSWF + PSWR (37) (38) (39) Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 21 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com Table 1. Typical Rise and Fall Times vs Input Voltage VIN tRISE tFALL 5V 8ns 8ns 10V 9ns 9ns 15V 10ns 10ns IC QUIESCENT LOSSES Another loss is the power required for operation of the internal circuitry: PQ = IQ x VIN (40) IQ is the quiescent operating current, and is typically around 2.4 mA. MOSFET DRIVER LOSSES The other operating power that needs to be calculated is that required to drive the internal NFET: PBOOST = IBOOST x VBOOST (41) VBOOST is normally between 3VDC and 5VDC. The IBOOST rms current is dependant on switching frequency fSW. IBOOST is approximately 8.2 mA at 2 MHz and 4.4 mA at 1 MHz. TOTAL POWER LOSSES Total power losses are: PLOSS = PCOND + PSWR + PSWF + PQ + PBOOST + PDIODE + PIND (42) Losses internal to the LMR12015/20 are: PINTERNAL = PCOND + PSWR + PSWF + PQ + PBOOST (43) EFFICIENCY CALCULATION EXAMPLE Operating conditions are: VIN = 12V fSW = 2 MHz VOUT = 3.3V VD1 = 0.5V IOUT = 2A RDCR = 20 m (44) (45) (46) (47) (48) (49) Internal Power Losses are: PCOND = IOUT2 x RDSON x D= 22 x 0.15 x 0.314 = 188 mW PSW = (VIN x IOUT x fSW x tFALL) = (12V x 2A x 2 MHz x 10ns) = 480 mW PQ = IQ x VIN = 2.4 mA x 12V = 29 mW PBOOST = IBOOST x VBOOST = 8.2 mA x 4.5V = 37mW PINTERNAL = PCOND + PSW + PQ + PBOOST = 733 mW (50) (51) (52) (53) (54) Total Power Losses are: PDIODE= VD1 x IOUT (1 - D)= 0.5V x 2 x (1 - 0.314) = 686 mW PIND= IOUT2 x RDCR= 22 x 20 m = 80 mW PLOSS = PINTERNAL + PDIODE + P IND = 1.499 W (55) (56) (57) The efficiency can now be estimated as: POUT 6.6 W = = 81 % K= POUT + PLOSS 6.6 W + 1.499 W (58) With this information we can estimate the junction temperature of the LMR12015/20. 22 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 CALCULATING THE LMR12015/20 JUNCTION TEMPERATURE Thermal Definitions: TJ = IC junction temperature TA = Ambient temperature RJC = Thermal resistance from IC junction to device case RJA = Thermal resistance from IC junction to ambient air Figure 34. Cross-Sectional View of Integrated Circuit Mounted on a Printed Circuit Board. Heat in the LMR12015/20 due to internal power dissipation is removed through conduction and/or convection. Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs conductor). Heat Transfer goes as: SiliconLead FramePCB (59) Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural convection occurs when air currents rise from the hot device to cooler air. Thermal impedance is defined as: RT = 'T Power (60) Thermal impedance from the silicon junction to the ambient air is defined as: RTJA = TJ - TA Power (61) This impedance can vary depending on the thermal properties of the PCB. This includes PCB size, weight of copper used to route traces , the ground plane, and the number of layers within the PCB. The type and number of thermal vias can also make a large difference in the thermal impedance. Thermal vias are necessary in most applications. They conduct heat from the surface of the PCB to the ground plane. Six to nine thermal vias should be placed under the exposed pad to the ground plane. Placing more than nine thermal vias results in only a small reduction to RJA for the same copper area. These vias should have 8 mil holes to avoid wicking solder away from the DAP. See AN-1187 SNOA401and AN-1520 SNVA183 for more information on package thermal performance. To predict the silicon junction temperature for a given application, three methods can be used. The first is useful before prototyping and the other two can more accurately predict the junction temperature within the application. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 23 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com Method 1: The first method predicts the junction temperature by extrapolating a best guess RJA from the table or graph. The tables and graph are for natural convection. The internal dissipation can be calculated using the efficiency calculations. This allows the user to make a rough prediction of the junction temperature in their application. Methods two and three can later be used to determine the junction temperature more accurately. The table below has values of RJA for the WSON package. Table 2. RJA values for the LLP @ 1 Watt dissipation: Number of Board Layers Size of Bottom Layer Copper Connected to DAP Size of Top Layer Copper Connected to Dap Number of 8 mil Thermal Vias 2 0.25 in2 0.05 in2 RJA 8 78 C/W 2 0.5625 in 0.05 in2 8 65.6 C/W 2 1 in2 0.05 in2 8 58.6 C/W 2 2 2 1.3225 in 0.05 in2 8 50 C/W 4 (Eval Board) 3.25 in2 2.25 in2 15 30.7 C/W Figure 35. Estimate of Thermal Resistance vs. Ground Copper Area Eight Thermal Vias and Natural Convection Method 2: The second method requires the user to know the thermal impedance of the silicon junction to case. (RJC) is approximately 9.1C/W for the WSON. The case temperature should be measured on the bottom of the PCB at a thermal via directly under the DAP of the LMR12015/20. The solder resist should be removed from this area for temperature testing. The reading will be more accurate if it is taken midway between pins 2 and 9, where the NMOS switch is located. Knowing the internal dissipation from the efficiency calculation given previously, and the case temperature (TC) we have: RTJC = TJ - TC Power (62) Therefore: TJ = (RJC x PLOSS) + TC 24 Submit Documentation Feedback (63) Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 PCB Layout Considerations COMPACT LAYOUT The performance of any switching converter depends as much upon the layout of the PCB as the component selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and minimum generation of unwanted EMI. Parasitic inductance can be reduced by keeping the power path components close together and keeping the area of the loops small, on which high currents travel. Short, thick traces or copper pours (shapes) are best. In particular, the switch node (where L1, D1, and the SW pin connect) should be just large enough to connect all three components without excessive heating from the current it carries. The LMR12015/20 operates in two distinct cycles (see Figure 27) whose high current paths are shown below in Figure 36: + - Figure 36. Buck Converter Current Loops The dark grey, inner loop represents the high current path during the MOSFET on-time. The light grey, outer loop represents the high current path during the off-time. GROUND PLANE AND SHAPE ROUTING The diagram of Figure 36 is also useful for analyzing the flow of continuous current vs. the flow of pulsating currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just like any other circuit path. The path between the input source and the input capacitor and the path between the catch diode and the load are examples of continuous current paths. In contrast, the path between the catch diode and the input capacitor carries a large pulsating current. This path should be routed with a short, thick shape, preferably on the component side of the PCB. Multiple vias in parallel should be used right at the pad of the input capacitor to connect the component side shapes to the ground plane. A second pulsating current loop that is often ignored is the gate drive loop formed by the SW and BOOST pins and boost capacitor CBOOST. To minimize this loop and the EMI it generates, keep CBOOST close to the SW and BOOST pins. FB LOOP The FB pin is a high-impedance input, and the loop created by R2, the FB pin and ground should be made as small as possible to maximize noise rejection. R2 should therefore be placed as close as possible to the FB and GND pins of the IC. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 25 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com PCB SUMMARY 1. Minimize the parasitic inductance by keeping the power path components close together and keeping the area of the high-current loops small. 2. The most important consideration when completing the layout is the close coupling of the GND connections of the CIN capacitor and the catch diode D1. These ground connections should be immediately adjacent, with multiple vias in parallel at the pad of the input capacitor connected to GND. Place CIN and D1 as close to the IC as possible. 3. Next in importance is the location of the GND connection of the COUT capacitor, which should be near the GND connections of CIN and D1. 4. There should be a continuous ground plane on the copper layer directly beneath the converter. This will reduce parasitic inductance and EMI. 5. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R2 placed as close as possible to the GND of the IC. The VOUT trace to R1 should be routed away from the inductor and any other traces that are switching. 6. High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the layout designer must make this trade-off. Radiated noise can be decreased by choosing a shielded inductor. The remaining components should also be placed as close as possible to the IC. Please see Application Note AN-2279 SNVU191 for further considerations and the LMR12015/20 eval board as an example of a four-layer layout. 26 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 LMR12015/20 Circuit Examples VIN PVIN BOOST C2 AVIN L1 C1 VOUT SW LMR12015/20 D1 C3 C4 ON EN OFF R1 SYNC CLK 2 MHz FB GND / DAP R2 C5 Figure 37. VIN = 7 - 20V, VOUT = 5V, fSW = 2 MHz, IOUT = Full Load with CFF Table 3. Bill of Materials for Figure 37 Part Name Part ID Part Value Part Number Manufacturer Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments CPVIN C1 10 F C1210C106K8PACTU Kemet CBOOST C2 0.1 F C0603X104K4RACTU Kemet COUT C3 22 F GRM32ER71C226KE18L MuRata COUT C4 22 F GRM32ER71C226KE18L MuRata CFF C5 0.18 F 0603ZC184KAT2A AVX Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba Inductor L1 3.3 H 7447789003 Wurth Feedback Resistor R1 4.02 k CRCW06034K02FKEA Vishay Feedback Resistor R2 1.02 k CRCW06031K02FKEA Vishay Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 27 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com VIN PVIN BOOST C2 AVIN L1 C1 VOUT SW LMR12015/20 C3 D1 C4 ON EN OFF R1 SYNC CLK 2 MHz FB GND / DAP R2 C5 Figure 38. VIN = 5 - 20V, VOUT = 3.3V, fSW = 2 MHz, IOUT = Full Load with CFF Table 4. Bill of Materials for Figure 38 Part Name Part ID Part Value Part Number Manufacturer Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments CPVIN C1 10 F C1210C106K8PACTU Kemet CBOOST C2 0.1 F C0603X104K4RACTU Kemet COUT C3 22 F GRM32ER71C226KE18L MuRata COUT C4 22 F GRM32ER71C226KE18L MuRata CFF C5 0.18 F 0603ZC184KAT2A AVX Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba Inductor L1 3.3 H 7447789003 Wurth Feedback Resistor R1 2.32 k CRCW06032K32FKEA Vishay Feedback Resistor R2 1.02 k CRCW06031K02FKEA Vishay 28 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 VIN PVIN BOOST C2 AVIN L1 C1 EN VOUT SW LMR12015/20 C3 D1 C4 R1 SYNC FB GND / DAP R2 Figure 39. VIN = 5 - 20V, VOUT = 3.3V, fSW = 2 MHz, IOUT = Full Load without CFF Table 5. Bill of Materials for Figure 39 Part Name Part ID Part Value Part Number Manufacturer Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments CPVIN C1 10 F C1210C106K8PACTU Kemet CBOOST C2 0.1 F C0603X104K4RACTU Kemet COUT C3 22 F GRM32ER71C226KE18L MuRata COUT C4 22 F GRM32ER71C226KE18L MuRata Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba Inductor L1 3.3 H 7447789003 Sumida Feedback Resistor R1 2.32 k CRCW06032K32FKEA Vishay Feedback Resistor R2 1.02 k CRCW06031K02FKEA Vishay Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 29 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com VIN PVIN BOOST C2 AVIN L1 C1 EN VOUT SW LMR12015/20 C3 D1 C4 R1 SYNC FB GND / DAP R2 Figure 40. VIN = 3.3 - 16V, VOUT = 1.8V, fSW = 2 MHz, IOUT = Full Load Table 6. Bill of Materials for Figure 40 Part Name Part ID Part Value Part Number Manufacturer Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments CPVIN C1 10 F GRM32DR71E106KA12L Murata CBOOST C2 0.1 F GRM188R71C104KA01D Murata COUT C3 22 F C3225X7R1C226K TDK COUT C4 22 F C3225X7R1C226K TDK Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba Inductor L1 1.0 H CDRH5D18BHPNP Sumida Feedback Resistor R1 12 k CRCW060312K0FKEA Vishay Feedback Resistor R2 15 k CRCW060315K0FKEA Vishay 30 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 VIN PVIN BOOST C2 AVIN L1 C1 VOUT SW LMR12015/20 D1 C3 C4 ON EN OFF R1 SYNC CLK 1 MHz FB GND / DAP R2 C5 Figure 41. VIN = 3.3 - 16V, VOUT = 1.8V, fSW = 1 MHz, IOUT = Full Load Table 7. Bill of Materials for Figure 41 Part Name Part ID Part Value Part Number Manufacturer Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments CPVIN C1 10 F GRM32DR71E106KA12L Murata CBOOST C2 0.1 F GRM188R71C104KA01D Murata COUT C3 22 uF C3225X7R1C226K TDK COUT C4 22 uF C3225X7R1C226K TDK CFF C5 3.9 nF GRM188R71H392KA01D Murata Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba Inductor L1 1.8 H CDRH5D18BHPNP Sumida Feedback Resistor R1 12 k CRCW060312K0FKEA Vishay Feedback Resistor R2 15 k CRCW060315K0FKEA Vishay Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 31 LMR12015, LMR12020 SNVS817A - JUNE 2012 - REVISED APRIL 2013 www.ti.com VIN PVIN BOOST C2 AVIN L1 C1 VOUT SW LMR12015/20 C3 D1 C4 ON EN OFF R1 SYNC CLK 2 MHz FB GND / DAP R2 C5 Figure 42. VIN = 3.3 - 9V, VOUT = 1.2V, fSW = 2 MHz, IOUT = Full Load Table 8. Bill of Materials for Figure 42 Part Name Part ID Part Value Part Number Manufacturer Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments CPVIN C1 10 F GRM32DR71E106KA12L Murata CBOOST C2 0.1 F GRM188R71C104KA01D Murata COUT C3 47 F GRM32ER61A476KE20L Murata COUT C4 22 F C3225X7R1C226K TDK CFF C5 NOT MOUNTED Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba Inductor L1 0.56 H CDRH2D18/HPNP Sumida Feedback Resistor R1 1.02 k CRCW06031K02FKEA Vishay Feedback Resistor R2 5.10 k CRCW06035K10FKEA Vishay 32 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 LMR12015, LMR12020 www.ti.com SNVS817A - JUNE 2012 - REVISED APRIL 2013 REVISION HISTORY Changes from Original (April 2013) to Revision A * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 32 Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: LMR12015 LMR12020 Submit Documentation Feedback 33 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMR12015XSD/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L285B LMR12015XSDX/NOPB ACTIVE WSON DSC 10 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L285B LMR12020XSD/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L284B LMR12020XSDX/NOPB ACTIVE WSON DSC 10 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L284B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMR12015XSD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMR12015XSDX/NOPB WSON DSC 10 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMR12020XSD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LMR12020XSDX/NOPB WSON DSC 10 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMR12015XSD/NOPB WSON DSC 10 1000 210.0 185.0 35.0 LMR12015XSDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0 LMR12020XSD/NOPB WSON DSC 10 1000 210.0 185.0 35.0 LMR12020XSDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE DSC0010B WSON - 0.8 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 B A PIN 1 INDEX AREA 3.1 2.9 C 0.8 MAX 0.08 SEATING PLANE 0.05 0.00 1.20.1 (0.2) TYP 6 5 8X 0.5 2X 2 20.1 1 10 10X PIN 1 ID (OPTIONAL) 10X 0.5 0.4 0.3 0.2 0.1 0.05 C A C B 4214926/A 07/2014 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DSC0010B WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.2) 10X (0.65) SYMM 10 1 10X (0.25) SYMM (2) (0.75) TYP 8X (0.5) 5 ( 0.2) TYP VIA 6 (0.35) TYP (2.75) LAND PATTERN EXAMPLE SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) METAL UNDER SOLDER MASK SOLDER MASK DEFINED SOLDER MASK DETAILS 4214926/A 07/2014 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com EXAMPLE STENCIL DESIGN DSC0010B WSON - 0.8 mm max height PLASTIC SMALL OUTLINE - NO LEAD 10X (0.65) SYMM METAL TYP 10X (0.25) (0.55) SYMM (0.89) 8X (0.5) (1.13) (2.75) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 84% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4214926/A 07/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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