MCP14A0453/4/5 4.5A Dual MOSFET Driver with Low Threshold Input and Enable Features General Description * High Peak Output Current: 4.5A (typical) * Wide Input Supply Voltage Operating Range: - 4.5V to 18V * Low Shoot-Through/Cross-Conduction Current in Output Stage * High Capacitive Load Drive Capability: - 2200 pF in 12 ns (typical) * Short Delay Times: 16 ns (tD1), 19 ns (tD2) (typical) * Low Supply Current: 620 A (typical) * Low-Voltage Threshold Input and Enable with Hysteresis * Latch-Up Protected: Withstands 500 mA Reverse Current * Space-Saving Packages: - 8-Lead MSOP - 8-Lead SOIC - 8-Lead 2 x 3 TDFN The MCP14A0453/4/5 devices are high-speed dual MOSFET drivers that are capable of providing up to 4.5A of peak current while operating from a single 4.5V to 18V supply. There are three output configurations available: dual inverting (MCP14A0453), dual noninverting (MCP14A0454) and complementary (MCP14A0455). These devices feature low shoot-through current, matched rise and fall times, and short propagation delays, which make them ideal for high switching frequency applications. Applications * * * * * Switch Mode Power Supplies Pulse Transformer Drive Line Drivers Level Translator Motor and Solenoid Drive The MCP14A0453/4/5 family of devices offers enhanced control with Enable functionality. The active-high Enable pins can be driven low to drive the corresponding outputs of the MCP14A0453/4/5 low, regardless of the status of the Input pins. Integrated pull-up resistors allow the user to leave the Enable pins floating for standard operation. These devices are highly latch-up resistant under any condition within their power and voltage ratings. They can accept up to 500 mA of reverse current being forced back into their outputs without damage or logic upset. All terminals are fully protected against electrostatic discharge (ESD) up to 2 kV (HBM) and 200V (MM). Package Types MCP14A0453/4/5 MSOP/SOIC ENA 1 8 ENB INA 2 7 OUTA/OUTA/OUTA 6 VDD GND 3 INB 4 5 OUTB/OUTB/OUTB MCP14A0453/4/5 2 x 3 TDFN* 8 ENB ENA 1 INA 2 GND 3 INB 4 EP* 9 7 OUTA/OUTA/OUTA 6 VDD 5 OUTB/OUTB/OUTB * Includes Exposed Thermal Pad (EP); see Table 3-1. 2018 Microchip Technology Inc. DS20005985A-page 1 MCP14A0453/4/5 Functional Block Diagram VDD Internal Pull-Up Enable VREF GND Inverting Output VDD Input VREF GND DS20005985A-page 2 Non-Inverting MCP14A0453 Dual Inverting MCP14A0454 Dual Non-Inverting MCP14A0455 Complementary: One Inverting, One Non-Inverting 2018 Microchip Technology Inc. MCP14A0453/4/5 1.0 ELECTRICAL CHARACTERISTICS 1.1 Electrical Specifications Absolute Maximum Ratings VDD, Supply Voltage..................................................................................................................................................+20V VIN, Input Voltage............................................................................................................... (VDD + 0.3V) to (GND - 0.3V) VEN, Enable Voltage........................................................................................................... (VDD + 0.3V) to (GND - 0.3V) Package Power Dissipation (TA = +50C) 8L MSOP .................................................................................................................................................0.63W 8L SOIC ...................................................................................................................................................1.00W 8L 2 X 3 TDFN .........................................................................................................................................1.85W ESD protection on all pins ..............................................................................................................................2 kV (HBM) ESD protection on all pins .............................................................................................................................. 200V (MM) Notice: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2018 Microchip Technology Inc. DS20005985A-page 3 MCP14A0453/4/5 TABLE 1-1: DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, TA = +25C, with 4.5V VDD 18V. Parameters Sym. Min. Typ. Max. Units Conditions Input Voltage Range VIN GND - 0.3V -- VDD + 0.3 V Logic `1' High Input Voltage VIH 2.0 1.6 -- V Logic `0' Low Input Voltage VIL -- 1.3 0.8 V VHYST(IN) -- 0.3 -- V IIN -1 -- +1 A Enable Voltage Range VEN GND - 0.3V -- VDD + 0.3 V Logic `1' High Enable Voltage VEH 2.0 1.6 -- V Logic `0' Low Enable Voltage VEL -- 1.3 0.8 V VHYST(EN) -- 0.3 -- V RENBL -- 1.5 -- M Enable Input Current IEN -- 12 -- A VDD = 18V, ENB = AGND Propagation Delay tD3 -- 16 23 ns VDD = 18V, VEN = 5V, see Figure 4-3, (Note 1) Propagation Delay tD4 -- 19 26 ns VDD = 18V, VEN = 5V, see Figure 4-3, (Note 1) VOH VDD - 0.025 -- -- V IOUT = 0A Low Output Voltage VOL -- -- 0.025 V IOUT = 0A Output Resistance, High ROH -- 1.7 2.7 IOUT = 10 mA, VDD = 18V Output Resistance, Low ROL -- 1.3 2.3 IOUT = 10 mA, VDD = 18V Peak Output Current IPK -- 4.5 -- A VDD = 18V (Note 1) Latch-Up Protection Withstand Reverse Current IREV 0.5 -- -- A Duty cycle 2%, t 300 s (Note 1) Rise Time tR -- 12 17 ns VDD = 18V, CL = 1800 pF, see Figure 4-1, Figure 4-2 Fall Time tF -- 12 17 ns VDD = 18V, CL = 1800 pF, see Figure 4-1, Figure 4-2 Delay Time tD1 -- 16 23 ns VDD = 18V, VIN = 5V, see Figure 4-1, Figure 4-2 tD2 -- 19 26 ns VDD = 18V, VIN = 5V, see Figure 4-1, Figure 4-2 VDD 4.5 -- 18 V Input Input Voltage Hysteresis Input Current 0V VIN VDD Enable Enable Voltage Hysteresis Enable Pin Pull-Up Resistance VDD = 18V, ENB = AGND Output High Output Voltage Switching Time (Note 1) Power Supply Supply Voltage Power Supply Current Note 1: IDD -- 620 900 A VINA/B = 3V, VENA/B = 3V IDD -- 620 900 A VINA/B = 0V, VENA/B = 3V IDD -- 620 900 A VINA/B = 3V, VENA/B = 0V IDD -- 620 900 A VINA/B = 0V, VENA/B = 0V Tested during characterization, not production tested. DS20005985A-page 4 2018 Microchip Technology Inc. MCP14A0453/4/5 TABLE 1-2: DC CHARACTERISTICS (OVER OPERATING TEMP. RANGE) Electrical Specifications: Unless otherwise indicated, over the operating range with 4.5V VDD 18V. Sym. Min. Typ. Max. Unit s Input Voltage Range VIN GND - 0.3V -- VDD + 0.3 V Logic `1' High Input Voltage VIH 2.0 1.6 -- V Logic `0' Low Input Voltage VIL -- 1.3 0.8 V VHYST(IN) -- 0.3 -- V IIN -10 -- +10 A Enable Voltage Range VEN GND - 0.3V -- VDD + 0.3 V Logic `1' High Enable Voltage VEH 2.0 1.6 -- V Logic `0' Low Enable Voltage VEL -- 1.3 0.8 V Parameters Conditions Input Input Voltage Hysteresis Input Current 0V VIN VDD Enable Enable Voltage Hysteresis VHYST(EN) -- 0.3 -- V Enable Input Current IEN -- 12 -- A VDD = 18V, ENB = AGND Propagation Delay tD3 -- 20 27 ns VDD = 18V, VEN = 5V, TA = +125C, see Figure 4-3, (Note 1) Propagation Delay tD4 -- 24 31 ns VDD = 18V, VEN = 5V, TA = +125C, see Figure 4-3, (Note 1) High Output Voltage VOH VDD - 0.025 -- -- V DC Test Low Output Voltage VOL -- -- 0.025 V DC Test Output Resistance, High ROH -- -- 3.3 IOUT = 10 mA, VDD = 18V Output Resistance, Low ROL -- -- 2.9 IOUT = 10 mA, VDD = 18V Output Note 1: Tested during characterization, not production tested. 2018 Microchip Technology Inc. DS20005985A-page 5 MCP14A0453/4/5 TABLE 1-2: DC CHARACTERISTICS (OVER OPERATING TEMP. RANGE) (CONTINUED) Electrical Specifications: Unless otherwise indicated, over the operating range with 4.5V VDD 18V. Sym. Min. Typ. Max. Unit s Rise Time tR -- 14 19 ns VDD = 18V, CL = 1800 pF, TA = +125C, see Figure 4-1, Figure 4-2 Fall Time tF -- 14 19 ns VDD = 18V, CL = 1800 pF, TA = +125C, see Figure 4-1, Figure 4-2 Delay Time tD1 -- 20 27 ns VDD = 18V, VIN = 5V, TA = +125C, see Figure 4-1, Figure 4-2 tD2 -- 24 31 VDD 4.5 -- 18 V Parameters Conditions Switching Time (Note 1) VDD = 18V, VIN = 5V, TA = +125C, see Figure 4-1, Figure 4-2 Power Supply Supply Voltage Power Supply Current Note 1: 1.2 IDD -- -- 1100 A VINA/B = 3V, VENA/B = 3V IDD -- -- 1100 A VINA/B = 0V, VENA/B = 3V IDD -- -- 1100 A VINA/B = 3V, VENA/B = 0V IDD -- -- 1100 A VINA/B = 0V, VENA/B = 0V Tested during characterization, not production tested. Temperature Characteristics Electrical Specifications: Unless otherwise noted, all parameters apply with 4.5V VDD 18V Parameter Sym. Min. Typ. Max. Units Comments Specified Temperature Range TA -40 -- +125 C Maximum Junction Temperature TJ -- -- +150 C Storage Temperature Range TA -65 -- +150 C Junction-to-Ambient Thermal Resistance, 8LD MSOP JA -- 158 -- C/W Note 1 Junction-to-Ambient Thermal Resistance, 8LD SOIC JA -- 100 -- C/W Note 1 Junction-to-Ambient Thermal Resistance, 8LD TDFN JA -- 54 -- C/W Note 1 Junction-to-Top Characterization Parameter, 8LD MSOP JT -- 2.4 -- C/W Note 1 Junction-to-Top Characterization Parameter, 8LD SOIC JT -- 5.9 -- C/W Note 1 Junction-to-Top Characterization Parameter, 8LD TDFN JT -- 0.5 -- C/W Note 1 Junction-to-Board Characterization Parameter, 8LD MSOP JB -- 115 -- C/W Note 1 Junction-to-Board Characterization Parameter, 8LD SOIC JB -- 65 -- C/W Note 1 Junction-to-Board Characterization Parameter, 8LD TDFN JB -- 24 -- C/W Note 1 Temperature Ranges Package Thermal Resistances Note 1: Parameter is determined using High K 2S2P 4-Layer board as described in JESD 51-7, as well as JESD 51-5 for packages with exposed pads. DS20005985A-page 6 2018 Microchip Technology Inc. MCP14A0453/4/5 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Note: Unless otherwise indicated, TA = +25C with 4.5V VDD 18V. 120 80 10000 pF 6800 pF 4700 pF 3300 pF 2200 pF 1000 pF 80 70 Fall Time (ns) Rise Time (ns) 100 60 40 60 50 40 5V 12V 30 20 20 18V 10 0 4 6 8 10 12 14 16 0 1000 18 10000 Supply Voltage (V) FIGURE 2-1: Voltage. Capacitive Load (pF) FIGURE 2-4: Load. Rise Time vs. Supply 120 26 24 VDD = 18V tR, 4700 pF 22 80 Time (ns) Rise Time (ns) 100 Fall Time vs. Capacitive 60 5V 40 12V 20 tF, 4700 pF 18 16 14 tR, 2200 pF 12 20 tF, 2200 pF 10 18V 0 1000 8 10000 -40 -25 -10 Capacitive Load (pF) FIGURE 2-2: Load. 50 Crossover Current (A) Fall Time (ns) 60 FIGURE 2-5: Temperature. Rise and Fall Time vs. 10000 10000 pF 6800 pF 4700 pF 3300 pF 2200 pF 1000 pF 70 20 35 50 65 80 95 110 125 Temperature (C) Rise Time vs. Capacitive 80 5 40 30 20 10 0 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz 1000 100 10 4 6 8 10 12 14 16 18 4 6 Supply Voltage (V) FIGURE 2-3: Voltage. Fall Time vs. Supply 2018 Microchip Technology Inc. 8 10 12 14 16 18 Supply Voltage (V) FIGURE 2-6: Supply Voltage. Crossover Current vs. DS20005985A-page 7 MCP14A0453/4/5 50 Enable Propagation Delay (ns) Input Propagation Delay (ns) Note: Unless otherwise indicated, TA = +25C with 4.5V VDD 18V. VIN = 5V 45 40 35 30 tD2 25 20 tD1 15 10 4 6 8 10 12 14 16 50 VEN = 5V 45 40 35 30 tD4 25 20 tD3 15 10 18 4 6 8 Input Propagation Delay vs. 25 VDD = 18V tD2 20 15 tD1 10 2 4 6 8 10 12 14 16 tD4 20 15 tD3 10 4 tD2 20 18 tD1 14 12 5 20 35 50 65 80 95 110 125 24 DS20005985A-page 8 Input Propagation Delay vs. 10 12 14 16 18 VDD = 18V VEN = 5V 22 tD4 20 18 tD3 16 14 12 -40 -25 -10 Temperature (C) FIGURE 2-9: Temperature. 8 FIGURE 2-11: Enable Propagation Delay Time vs. Enable Voltage Amplitude. Enable Propagation Delay (ns) Input Propagation Delay (ns) VIN = 5V 6 Enable Voltage Amplitude (V) 26 VDD = 18V -40 -25 -10 18 25 2 26 16 16 VDD = 18V 18 FIGURE 2-8: Input Propagation Delay Time vs. Input Amplitude. 22 14 30 Input Voltage Amplitude (V) 24 12 FIGURE 2-10: Enable Propagation Delay vs. Supply Voltage. Enable Propagation Delay (ns) Input Propogation Delay (ns) FIGURE 2-7: Supply Voltage. 10 Supply Voltage (V) Supply Voltage (V) 5 20 35 50 65 80 95 110 125 Temperature (C) FIGURE 2-12: vs. Temperature. Enable Propagation Delay 2018 Microchip Technology Inc. MCP14A0453/4/5 Note: Unless otherwise indicated, TA = +25C with 4.5V VDD 18V. 1.8 1.7 Input Threshold (V) Quiescent Current (A) 650 600 VIH 1.6 1.5 1.4 1.3 VIL 1.2 1.1 550 1.0 4 6 8 10 12 14 16 18 4 6 Supply Voltage (V) 650 600 550 16 18 Input Threshold vs. Supply VDD = 18V VEH 1.6 1.5 1.4 1.3 VEL 1.2 1.1 500 1 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (C) FIGURE 2-14: vs. Temperature. 20 35 50 65 80 95 110 125 Temperature (C) Quiescent Supply Current FIGURE 2-17: Temperature. 1.8 Enable Threshold vs. 1.8 VDD = 18V VIH Enable Threshold (V) Input Threshold (V) 14 1.7 700 1.6 1.5 1.4 1.3 1.2 12 1.8 Enable Threshold (V) Quiescent Current (A) FIGURE 2-16: Voltage. VDD = 18V 750 1.7 10 Supply Voltage (V) FIGURE 2-13: Quiescent Supply Current vs. Supply Voltage. 800 8 VIL 1.1 1.7 VEH 1.6 1.5 1.4 1.3 VEL 1.2 1.1 1 1 -40 -25 -10 5 20 35 50 65 80 95 110 125 4 6 Temperature (C) FIGURE 2-15: Temperature. Input Threshold vs. 2018 Microchip Technology Inc. 8 10 12 14 16 18 Supply Voltage (V) FIGURE 2-18: Supply Voltage. Enable Threshold vs. DS20005985A-page 9 MCP14A0453/4/5 Note: Unless otherwise indicated, TA = +25C with 4.5V VDD 18V. VIN = 0V (MCP14A0453) VIN = 5V (MCP14A0454) 4.0 Supply Current (mA) ROH - Output Resistance () 4.5 3.5 TA = +125C 3.0 2.5 TA = +25C 2.0 1.5 4 6 8 10 12 14 16 50 45 40 35 30 25 20 15 10 5 0 18 VDD = 12V 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz 10 kHz 100 1000 Supply Voltage (V) FIGURE 2-19: Output Resistance (Output High) vs. Supply Voltage. 30 VIN = 5V (MCP14A0453) VIN = 0V (MCP14A0454) VDD = 6V 2.5 2 FIGURE 2-22: Supply Current vs. Capacitive Load (VDD = 12V). Supply Current (mA) ROL - Output Resistance () 3 TA = +125C 1.5 TA = +25C 1 25 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz 10 kHz 20 15 10 5 0 4 6 8 10 12 14 16 18 100 1000 Supply Voltage (V) Supply Current (mA) Supply Current (mA) FIGURE 2-23: Supply Current vs. Capacitive Load (VDD = 6V). VDD = 18V 1 MHz 500 kHz 200 kHz 100 kHz 50 kHz 10 kHz 100 1000 Capacitive Load (pF) FIGURE 2-21: Supply Current vs. Capacitive Load (VDD = 18V). DS20005985A-page 10 10000 Capacitive Load (pF) FIGURE 2-20: Output Resistance (Output Low) vs. Supply Voltage. 100 90 80 70 60 50 40 30 20 10 0 10000 Capacitive Load (pF) 10000 100 90 80 70 60 50 40 30 20 10 0 VDD = 18V 10000 pF 6800 pF 3300 pF 1000 pF 470 pF 100 pF 10 100 1000 Switching Frequency (kHz) FIGURE 2-24: Supply Current vs. Frequency (VDD = 18V). 2018 Microchip Technology Inc. MCP14A0453/4/5 Supply Current (mA) Note: Unless otherwise indicated, TA = +25C with 4.5V VDD 18V. 50 45 40 35 30 25 20 15 10 5 0 VDD = 12V 10000 pF 6800 pF 3300 pF 1000 pF 470 pF 100 pF 10 100 1000 Switching Frequency (kHz) FIGURE 2-25: Supply Current vs. Frequency (VDD = 12V). Supply Current (mA) 30 VDD = 6V 25 10000 pF 6800 pF 3300 pF 1000 pF 470 pF 100 pF 20 15 10 5 0 10 100 1000 Switching Frequency (kHz) FIGURE 2-26: Supply Current vs. Frequency (VDD = 6V). 14 Enable Current (A) 13.5 13 12.5 12 11.5 11 10.5 10 4 6 8 10 12 14 16 18 Supply Voltage (V) FIGURE 2-27: Voltage. Enable Current vs. Supply 2018 Microchip Technology Inc. DS20005985A-page 11 MCP14A0453/4/5 NOTES: DS20005985A-page 12 2018 Microchip Technology Inc. MCP14A0453/4/5 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP14A0453/4/5 Symbol 8L 2 x 3 TDFN 3.1 1 1 ENA Enable for Driver A 2 2 INA Input for Driver A 3 3 GND Device Ground 4 4 INB Input for Driver B 5 5 OUTB/OUTB 6 6 VDD 7 7 OUTA/OUTA 8 8 ENB EP -- EP Output Pins (OUTA/OUTA, OUTB/OUTB) The outputs are CMOS push-pull circuits that are capable of sourcing and sinking 4.5A of peak current (VDD = 18V). The low output impedance ensures the gate of the external MOSFET stays in the intended state, even during large transients. This output also has a reverse current latch-up rating of 500 mA. 3.2 Device Ground Pin (GND) GND is the device return pin for the input and output stages. The GND pin should have a low-impedance connection to the bias supply source return. When the capacitive load is being discharged, high peak currents will flow through the ground pin. 3.3 Description 8L MSOP/SOIC Device Enable Pins (ENA, ENB) The MOSFET driver device enable pins are high-impedance inputs featuring low threshold levels. The enable inputs also have hysteresis between the high and low input levels, allowing them to be driven from slow rising and falling signals, and to provide noise immunity. Driving the enable pins below the threshold will disable the corresponding output of the device, pulling OUT/OUT low, regardless of the status of the input pin. Driving the enable pins above the threshold allows normal operation of the OUT/OUT pin based on the status of the input pin. The enable pins utilize internal pull-up resistors, allowing the pins to be left floating for standard driver operation. 2018 Microchip Technology Inc. Push-Pull for Output B Supply Input Voltage Push-Pull for Output A Enable for Driver B Exposed Thermal Pad (GND) 3.4 Control Input Pins (INA, INB) The MOSFET driver control inputs are high-impedance inputs featuring low threshold levels. The inputs also have hysteresis between the high and low input levels, allowing them to be driven from slow rising and falling signals, and to provide noise immunity. 3.5 Supply Input Pin (VDD) VDD is the bias supply input for the MOSFET driver and has a voltage range of 4.5V to 18V. This input must be decoupled to ground with a local capacitor. This bypass capacitor provides a localized low-impedance path for the peak currents that are provided to the load. 3.6 Exposed Metal Pad Pin (EP) The exposed metal pad of the TDFN package is internally connected to GND. Therefore, this pad should be connected to a Ground plane to aid in heat removal from the package. DS20005985A-page 13 MCP14A0453/4/5 NOTES: DS20005985A-page 14 2018 Microchip Technology Inc. MCP14A0453/4/5 4.0 APPLICATION INFORMATION 4.1 General Information VDD = 18V 1 F MOSFET drivers are high-speed, high-current devices that are intended to source/sink high-peak currents to charge/discharge the gate capacitance of external MOSFETs or Insulated-Gate Bipolar Transistors (IGBTs). In high-frequency switching power supplies, the Pulse-Width Modulation (PWM) controller may not have the drive capability to directly drive the power MOSFET. A MOSFET driver such as the MCP14A0453/4/5 family can be used to provide additional source/sink current capability. Input 0.1 F Output CL = 2200 pF MCP14A0454 5V 4.2 MOSFET Driver Timing Input The ability of a MOSFET driver to transition from a fully-off state to a fully-on state is characterized by the driver's rise time (tR), fall time (tF) and propagation delays (tD1 and tD2). Figure 4-1 and Figure 4-2 show the test circuit and timing waveform used to verify the MCP14A0453/4/5 timing. VIH (Typ.) 0V VIL (Typ.) tD1 tR tD2 18V 90% Output 10% 0V VDD = 18V Input Signal: tRISE = tFALL 10 ns, 100 Hz, 0-5V Square Wave 1 F 0.1 F FIGURE 4-2: Waveform. Input 4.3 Output CL = 2200 pF MCP14A0453 5V Input VIH (Typ.) 0V VIL (Typ.) tD1 tF tD2 18V tR 90% Output 10% 0V Input Signal: tRISE = tFALL 10 ns, 100 Hz, 0-5V Square Wave FIGURE 4-1: Waveform. tF Inverting Driver Timing Non-inverting Driver Timing Enable Function The enable pins (EN A, EN B) provide additional control of the output pins (OUT). These pins are active-high and are internally pulled up to VDD so that the pins can be left floating to provide standard MOSFET driver operation. When the enable pin input voltages are above the enable pin high-voltage threshold (VEN_H), the corresponding output is enabled and allowed to react to the status of the input pin. However, when the voltage applied to the enable pins falls below the low threshold voltage (VEN_L), the driver's corresponding output is disabled and doesn't respond to changes in the status of the input pins. When the driver is disabled, the output is pulled down to a low state. Refer to Table 4-1 for the enable pin logic. The threshold voltage levels for the enable pin are similar to the threshold voltage levels of the input pin and are TTL compatible. Hysteresis is provided to help increase the noise immunity of the enable function, avoiding false triggers of the enable signal during driver switching. There are propagation delays associated with the driver receiving an enable signal and the output reacting. These propagation delays, tD3 and tD4, are graphically represented in Figure 4-3. 2018 Microchip Technology Inc. DS20005985A-page 15 MCP14A0453/4/5 TABLE 4-1: 4.6 ENABLE PIN LOGIC EN IN OUT OUT H H L H H L H L L X L L Power Dissipation The total internal power dissipation in a MOSFET driver is the summation of three separate power dissipation elements, as shown in Equation 4-1. EQUATION 4-1: P T = P L + P Q + P CC 5V Where: Enable VEH (Typ.) 0V tD3 VEL (Typ.) PT = Total power dissipation PL = Load power dissipation 90% PQ = Quiescent power dissipation PCC = Operating power dissipation tD4 18V Output 10% 0V Enable Signal: tRISE = tFALL 10 ns, 100 Hz, 0-5V Square Wave FIGURE 4-3: 4.4 Enable Timing Waveform. CAPACITIVE LOAD DISSIPATION The power dissipation caused by a capacitive load is a direct function of the frequency, total capacitive load and supply voltage. The power lost in the MOSFET driver for a complete charging and discharging cycle of a MOSFET is shown in Equation 4-2. Decoupling Capacitors Careful Printed Circuit Board (PCB) layout and decoupling capacitors are required when using power MOSFET drivers. Large current is required to charge and discharge capacitive loads quickly. For example, approximately 720 mA are needed to charge a 1000 pF load with 18V in 25 ns. To operate the MOSFET driver over a wide frequency range with low supply impedance, it is recommended to place 1.0 F and 0.1 F low ESR ceramic capacitors in parallel between the driver VDD and GND. These capacitors should be placed close to the driver to minimize circuit board parasitics and provide a local source for the required current. 4.5 4.6.1 PCB Layout Considerations Proper PCB layout is important in high-current, fastswitching circuits to provide proper device operation and robustness of design. Improper component placement may cause errant switching, excessive voltage ringing or circuit latch-up. The PCB trace loop length and inductance should be minimized by the use of ground planes or traces under the MOSFET gate drive signal. Separate analog and power grounds and local driver decoupling should also be used. Placing a ground plane beneath the MCP14A0453/4/5 devices will help as a radiated noise shield, as well as providing some heat sinking for power dissipated within the device. DS20005985A-page 16 EQUATION 4-2: P L = f C T V DD 2 Where: f = Switching frequency CT = Total load capacitance VDD = MOSFET driver supply voltage 4.6.2 QUIESCENT POWER DISSIPATION The power dissipation associated with the quiescent current draw depends on the state of the Input and Enable pins. See Section 1.0 "Electrical Characteristics" for typical quiescent current draw values in different operating states. The quiescent power dissipation is shown in Equation 4-3. EQUATION 4-3: P Q = I QH D + I QL 1 - D V DD Where: IQH = Quiescent current in the High state D = Duty cycle IQL = Quiescent current in the Low state VDD = MOSFET driver supply voltage 2018 Microchip Technology Inc. MCP14A0453/4/5 4.6.3 OPERATING POWER DISSIPATION The operating power dissipation occurs each time the MOSFET driver output transitions because, for a very short period of time, both MOSFETs in the output stage are on simultaneously. This cross-conduction current leads to a power dissipation described in Equation 4-4. EQUATION 4-4: P CC = V DD I CO Where: ICO = Crossover Current VDD = MOSFET driver supply voltage 2018 Microchip Technology Inc. DS20005985A-page 17 MCP14A0453/4/5 NOTES: DS20005985A-page 18 2018 Microchip Technology Inc. MCP14A0453/4/5 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead MSOP Example: Part Number Code MCP14A0453-E/MS A0453 MCP14A0454-E/MS A0454 MCP14A0455-E/MS A0455 8-Lead SOIC A0453 805256 Example: Part Number Code MCP14A0453-E/SN 14A0453 MCP14A0454-E/SN 14A0454 MCP14A0455-E/SN 14A0455 8-Lead TDFN 14A0453 e3 1805 256 Example: EG3 805 25 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2018 Microchip Technology Inc. DS20005985A-page 19 MCP14A0453/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005985A-page 20 2018 Microchip Technology Inc. MCP14A0453/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2018 Microchip Technology Inc. DS20005985A-page 21 MCP14A0453/4/5 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005985A-page 22 2018 Microchip Technology Inc. MCP14A0453/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A-B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 2 1 e B NOTE 5 NX b 0.25 C A-B D TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A-A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2 2018 Microchip Technology Inc. DS20005985A-page 23 MCP14A0453/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L L1 Footprint Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0 0.17 0.31 5 5 MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8 0.25 0.51 15 15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2 DS20005985A-page 24 2018 Microchip Technology Inc. MCP14A0453/4/5 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev B 2018 Microchip Technology Inc. DS20005985A-page 25 MCP14A0453/4/5 8-Lead Plastic Dual Flat, No Lead Package (MNY) - 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.15 C 1 2X 0.15 C 2 TOP VIEW 0.10 C C SEATING PLANE (A3) A 8X A1 0.08 C SIDE VIEW 0.10 C A B D2 L 1 2 0.10 C A B NOTE 1 E2 K N 8X b e BOTTOM VIEW 0.10 0.05 C A B C Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 1 of 2 DS20005985A-page 26 2018 Microchip Technology Inc. MCP14A0453/4/5 8-Lead Plastic Dual Flat, No Lead Package (MNY) - 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Pins e Pitch A Overall Height A1 Standoff Contact Thickness A3 D Overall Length E Overall Width Exposed Pad Length D2 Exposed Pad Width E2 b Contact Width L Contact Length Contact-to-Exposed Pad K MIN 0.70 0.00 1.35 1.25 0.20 0.25 0.20 MILLIMETERS NOM 8 0.50 BSC 0.75 0.02 0.20 REF 2.00 BSC 3.00 BSC 1.40 1.30 0.25 0.30 - MAX 0.80 0.05 1.45 1.35 0.30 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-129-MNY Rev E Sheet 2 of 2 2018 Microchip Technology Inc. DS20005985A-page 27 MCP14A0453/4/5 8-Lead Plastic Dual Flat, No Lead Package (MNY) - 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X2 EV 8 OV C Y2 EV Y1 1 2 SILK SCREEN X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 1.60 1.50 2.90 0.25 0.85 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-129-MNY Rev. B DS20005985A-page 28 2018 Microchip Technology Inc. MCP14A0453/4/5 APPENDIX A: REVISION HISTORY Revision A (March 2018) * Original Release of this Document. 2018 Microchip Technology Inc. DS20005985A-page 29 MCP14A0453/4/5 NOTES: DS20005985A-page 30 2018 Microchip Technology Inc. MCP14A0453/4/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. [X](1) -X Device Tape and Reel Temperature Range /XX Package Device: MCP14A0453: High-Speed MOSFET Driver MCP14A0453T: High-Speed MOSFET Driver (Tape and Reel) MCP14A0454: High-Speed MOSFET Driver MCP14A0454T: High-Speed MOSFET Driver (Tape and Reel) MCP14A0455: High-Speed MOSFET Driver MCP14A0455T: High-Speed MOSFET Driver (Tape and Reel) Temperature Range: E Package: MS = Plastic Micro Small Outline Package (MSOP),8-lead SN = Plastic Small Outline Package (SOIC), 8-lead MNY = Plastic Dual Flat, No Lead Package (TDFN), 8-lead = -40C to +125C (Extended) 2018 Microchip Technology Inc. Examples: a) MCP14A0453T-E/MS: Tape and Reel, Extended temperature, 8LD MSOP package b) MCP14A0454T-E/SN: Tape and Reel, Extended temperature, 8LD SOIC package c) MCP14A0455T-E/MNY: Tape and Reel Extended temperature, 8LD TDFN package Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. DS20005985A-page 31 MCP14A0453/4/5 NOTES: DS20005985A-page 32 2018 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-2820-6 == ISO/TS 16949 == 2018 Microchip Technology Inc. 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