ALD500ASC - Advanced Linear Devices

Operating Temperature Range *

0°C to +70°C0°C to +70°C0°C to +70°C

16-Pin 16-Pin 16-Pin Wide Body

Plastic Pin Small Outline Small Outline

Package Package (SOIC) Package (SOIC)

ALD500PC (16 bit) ALD500SC (16 bit) ALD500SWC (16 bit)

ALD500APC (17 bit) ALD500ASC (17 bit) ALD500ASWC (17 bit)

ALD500AUPC (18 bit) ALD500AUSC (18 bit) ALD500AUSWC (18 bit)

* Contact factory for industrial temperature range

BENEFITS

• Wide dynamic signal range

• Very high noise immunity

• Low cost, simple functionality

• Automatic compensation and cancellation of

error sources

• Easy to use to acquire true 18 bit,17 bit, or

16 bit conversion and noise performance

• Inherently linear and stable with temperature

and component variations

FEATURES

• Resolution up to 18 bits plus sign bit

and over-range bit

• Accuracy independent of input source

impedances

• High input impedance of 1012 Ω

• Inherently filters and integrates any

external noise spikes

• Differential analog input

• Wide bipolar analog input voltage

range ±3.5V

• Automatic zero offset compensation

• Low linearity error - as low as 0.002%

• Fast zero-crossing comparator - 1µs

• Low power dissipation - 6mW typical

• Automatic internal polarity detection

• Low input current - 2pA typical

• Microprocessor controlled conversion

• Optional digital control from a microcon-

troller, an ASIC, or a dedicated digital circuit

• Flexible conversion speed versus resolution

trade-off

ALD500AU/ALD500A/ALD500

ADVANCED

LINEAR

DEVICES, INC.

ORDERING INFORMATION

PRECISION INTEGRATING ANALOG PROCESSOR

APPLICATIONS

• 4 1/2 digits to 5 1/2 digits plus sign measurements

• Precision analog signal processor

• Precision sensor interface

• High accuracy DC measurement functions

• Portable battery operated instruments

• Computer peripheral

• PCMCIA

GENERAL DESCRIPTION

The ALD500AU/ALD500A/ALD500 are integrating dual slope analog

processors, designed to operate on ±5V power supplies for building

precision analog-to-digital converters. The ALD500AU/ALD500A/

ALD500 feature specifications suitable for 18 bit/17 bit/16 bit resolution

conversion, respectively. Together with three capacitors, one resistor,

a precision voltage reference, and a digital controller, a precision

Analog to Digital converter with auto zero can be implemented. The

digital controller can be implemented by an external microcontroller,

under either hardware (fixed logic) or software control. For ultra high

resolution applications, up to 23 bit conversion can be implemented with

an appropriate digital controller and software.

The ALD500 series of analog processors accept differential inputs and

the external digital controller first counts the number of pulses at a fixed

clock rate that a capacitor requires to integrate against an unknown

analog input voltage, then counts the number of pulses required to

deintegrate the capacitor against a known reference voltage. This

unknown analog voltage can then be converted by the microcontroller

to a digital word, which is translated into a high resolution number,

representing an accurate reading. This reading, when ratioed against

the reference voltage, yields an accurate, absolute voltage measurement

reading.

The ALD500 analog processors consist of on-chip digital control circuitry

to accept control inputs, integrating buffer amplifiers, analog switches,

and voltage comparators. It functions in four operating modes, or

phases, namely auto zero, integrate, deintegrate, and integrator zero

phases. At the end of a conversion, the comparator output goes from

high to low when the integrator crosses zero during deintegration.

ALD500 analog processors also provide direct logic interface to CMOS

logic families.

http://www.aldinc.com

PIN CONFIGURATION

V+

314

413 B

512 A

V+

REF

V-

INT

AGND

V-

REF

C+

REF

V-

V+

OUT

DGND

PC, SC, SWC PACKAGE

C-

REF

ALD500



2 Advanced Linear Devices ALD500AU/ALD500A/ALD500

GENERAL THEORY OF OPERATION

Dual-Slope Conversion Principles of Operation

The basic principle of dual-slope integrating analog to digital

converter is simple and straightforward. A capacitor, CINT, is

charged with the integrator from a starting voltage, V X, for a

fixed period of time at a rate determined by the value of an

unknown input voltage, which is the subject of measurement.

Then the capacitor is discharged at a fixed rate, based on an

external reference voltage, back to VX where the discharge

time, or deintegration time, is measured precisely. Both the

integration time and deintegration time are measured by a

digital counter controlled by a crystal oscillator. It can be

demonstrated that the unknown input voltage is determined

by the ratio of the deintegration time and integration time, and

is directly proportional to the magnitude of the external reference

voltage.

The major advantages of a dual-slope converter are:

a. Accuracy is not dependent on absolute values of

integration time tINT and deintegration time tDINT, but is

dependent on their relative ratios. Long-term clock frequency

variations will not affect the accuracy. A standard crystal

controlled clock running digital counters is adequate to generate

very high accuracies.

b. Accuracy is not dependent on the absolute values of

RINT and CINT. as long as the component values do not vary

through a conversion cycle, which typically lasts less than 1

second.

c. Offset voltage values of the analog components, such

as VX, are cancelled out and do not affect accuracy.

d. Accuracy of the system depends mainly on the accuracy

and the stability of the voltage reference value.

e. Very high resolution, high accuracy measurements

can be achieved simply and at very low cost.

An inherent benefit of the dual slope converter system is noise

immunity. The input noise spikes are integrated (averaged to

near zero) during the integration periods. Integrating ADCs

are immune to the large conversion errors that plague

successive approximation converters and other high resolution

converters and perform very well in high-noise environments.

The slow conversion speed of the integrating converter provides

inherent noise rejection with at least a 20dB/decade attenuation

rate. Interference signals with frequencies at integral multiples

of the integration period are, theoretically, completely removed.

Integrating converters often establish the integration period to

reject 50/60Hz line frequency interference signals.

The relationship of the integrate and deintegrate (charge

and discharge) of the integrating capacitor values are

shown below:

VINT = VX - (VIN . tINT / RINT . CINT)

FIGURE 1. ALD 500 Functional Block Diagram

SW-

(1)

(14)

(15)

OUT

DGND

Level

Shift

Polarity

Detection

Phase

Decoding

Logic

Comp2

Comp1

Integrator

Buffer

Analog

Switch

Control

Signals

Control Logic

AGND

(10)

(5)

(11)

(7) (9) (8) (6) (4)

(2) (16) (13)(12)

INT

C-

REF

C+

REF

V+

REF

V-

REF

SW-

SW+

V-

V+

BUF

(3)

ALD500AU/ALD500A/ALD500 Advanced Linear Devices 3

(integrate cycle) (1)

VX = VINT - (VREF . tDINT / RINT . CINT)

(deintegrate cycle) (2)

Combining equations 1 and 2 results in:

VIN / VREF = -tDINT / tINT (3)

where:

Vx= An offset voltage used as starting voltage

VINT = Voltage change across CINT during tINT and

during tDINT (equal in magnitude)

VIN = Average, or an integrated, value of input voltage

to be measured during tINT (Constant VIN)

tINT = Fixed time period over which unknown voltage is

integrated

tDINT = Unknown time period over which a known

reference voltage is integrated

VREF = Reference Voltage

CINT = Integrating Capacitor value

RINT = Integrating Resistor value

Actual data conversion is accomplished in two phases: Input

Signal Integration Phase and Reference Voltage Deintegration

Phase.

The integrator output is initialized to 0V prior to the start of

Input Signal Integration Phase. During Input Signal Integration

Phase, internal analog switches connect VIN to the buffer

input where it is maintained for a fixed integration time period

(tINT). This fixed integration period is generally determined by

a digital counter controlled by a crystal oscillator. The

application of VIN causes the integrator output to depart 0V at

a rate determined by VIN and a direction determined by the

polarity of VIN.

The Reference Voltage Deintegration Phase is initiated

immediately after tINT, within 1 clock cycle. During Reference

Voltage Deintegration Phase, internal analog switches connect

a reference voltage having a polarity opposite that of VIN to

the integrator input. Simultaneously the same digital counter

controlled by the same crystal oscillator used above is used to

start counting clock pulses. The Reference Voltage

Deintegration Phase is maintained until the comparator output

inside the dual slope analog processor changes state, indicating

the integrator has returned to 0V. At that point the digital

counter is stopped. The Deintegration time period (t DINT), as

measured by the digital counter, is directly proportional to the

magnitude of the applied input voltage.

After the digital counter value has been read, the digital

counter, the integrator, and the auto zero capacitor are all

reset to zero through an Integrator Zero Phase and an Auto

Zero Phase so that the next conversion can begin again. In

practice, this process is usually automated so that analog-to-

digital conversion is continuously updated. The digital control

is handled by a microprocessor or a dedicated logic controller.

The output, in the form of a binary serial word, is read by a

microprocessor or a display adapter when desired.

Figure 2. Basic Dual-Slope Converter

INT

SWITCH DRIVER 

CONTROL

LOGIC

POLARITY CONTROL

REF

SWITCHES

INTEGRATOR

COMPARATOR

PHASE

CONTROL

ANALOG

INPUT

)

OUTPUT

INTEGRATOR

IN ≈

FULL SCALE

IN ≈ 1/2

FULL SCALE

INT

DINT

INT

= 4.1V MAX

Figure 2. Basic Dual-Slope Converter

VOLTAGE

REFERENCE

OUT

POLARITY

DETECTION

DINT

X ≈ 0

MICROCONTROLLER 

(CONTROL LOGIC

+ COUNTER)

4 Advanced Linear Devices ALD500AU/ALD500A/ALD500

OPERATING ELECTRICAL CHARACTERISTICS

TA = 25°C V+ = +5.0V V- = -5.0V (VSUPPLY = ±5.0 V) unless otherwise specified; CAZ = CREF = 0.47µf

500AU 500A 500

Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions

Resolution 15 30 30 60 60 µV Note 1

Zero-Scale ZSE 0.0025 0.003 0.005 %

Error 0.003 0.005 0.008 % 0°C to 70°C

End Point ENL 0.005 0.005 0.010 0.005 0.015 % Notes 1, 2

Linearity 0.007 0.015 0.020 0°C to +70°C

Best Case NL0.0025 0.003 0.005 0.003 0.008 % Notes 1, 2

Straight Line

Linearity 0.004 0.008 0.015 0°C to +70°C

Zero-Scale TCZS 0.3 0.6 0.3 0.7 0.3 0.7 µV/°C0°C to +70°C

Temperature

Coefficient 0.15 0.3 0.15 0.35 0.15 0.35 ppm/°C Note 1

Full-Scale SYE 0.005 0.008 0.01 %

Symmetry Error

(Rollover Error) 0.008 0.010 0.012 % 0°C to 70°C

Full-Scale TCFS 1.3 1.3 1.3 ppm/°C0°C to +70°C

Temperature

Coefficient

Input IIN 222pAV

IN = 0V

Current

Common-Mode CMVR V-+1.5 V+-1.5 V-+1.5 V+-1.5 V-+1.5 V+-1.5 V

Voltage Range

Integrator VINT V-+0.9 V+-0.9 V-+0.9 V+-0.9 V-+0.9 V+-0.9 V

Output Swing

Analog Input VIN V-+1.5 V+-1.5 V-+1.5 V+-1.5 V-+1.5 V+-1.5 V AGND = 0V

Signal Range

Voltage VREF V-+1 V+-1 V-+1 V+-1 V-+1 V+-1 V

Reference

Range

ABSOLUTE MAXIMUM RATINGS

Supply voltage, V+ 13.2V

Differential input voltage range -0.3V to V + +0.3V

Power dissipation 600 mW

Operating temperature range PC, SC, SWC package 0°C to +70°C

Storage temperature range -65°C to +150°C

Lead temperature, 10 seconds +260°C

ALD500AU/ALD500A/ALD500 Advanced Linear Devices 5

DC ELECTRICAL CHARACTERISTICS

TA = 25°C V+ = +5.0V V- = -5.0V (VSUPPLY = ±5.0 V) unless otherwise specified; CAZ = CREF = 0.47µf

500AU 500A 500

Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions

Supply Current IS0.6 1.0 0.6 1.0 0.6 1.0 mA V+ = 5V , A =1,B=1

Power Dissipation PD10 10 10 mW VSUPPLY = ±5V

Positive Supply Range V+S 4.5 5.5 4.5 5.5 4.5 5.5 V Note 4

Negative Supply Range V-S -4.5 -5.5 -4.5 -5.5 -4.5 -5.5 V Note 4

Comparator Logic 1, VOH 44 4VI

SOURCE = 400µA

Output High

Comparator Logic 0, VOL 0.4 0.4 0.4 V ISINK = 1.1mA

Output Low

Logic 1, Input High VIH 3.5 3.5 3.5 V

Voltage

Logic 0, Input Low VIL 111V

Voltage

Logic Input Current IL0.01 0.01 0.01 µA

Comparator Delay tD111µsec Note 5

NOTES:

1. Integrate time ≥ 66 msec., Auto Zero time ≥ 66 msec., VINT = 4V, VIN = 2.0V Full Scale

Resolution = VINT /integrate time/clock period

2. End point linearity at ±1/4, ±1/2, ±3/4 Full Scale after Full Scale adjustment.

3. Rollover Error also depends on CINT, CREF, CAZ characteristics.

4. Contact factory for other power supply operating voltage ranges, including Vsupply = ±3V or Vsupply = ±2.5V.

5. Recommended selection of clock periods of one of the following:

t clk = 0.27µsec, 0.54µsec, or 1.09µsec

which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively.

Figure 3. ALD500 TIMING DIAGRAM

66.667 msec.

123,093

Clock Pulses

Positive Input Signal

Negative Input Signal

66.667 msec.

0.5416 µs

123,093

Clock Pulses

OUT

B INPUT

A INPUT

1.8432 MHz Clock

1 Conversion Cycle

Auto Zero

Phase Input Signal

Integration

Phase

Reference

Voltage

Deintegration

Phase

Integrator Zero

Phase Auto Zero

Phase

Fixed number

of clock pulses

by design.

Variable

number of

clock pulses.

Clock data in

or clock data out

of counters within the

the microcontroller

or fixed logic controller,

as needed.

Fixed period of

approx.1 msec.

At V

MAX,

max. number of

clock pulses

= 246,185

NOT VALID

Stop counter upon

detection of comparator

output going from high

to low state.

START DEINTEGRATION CYCLE

START INTEGRATION CYCLE

START

CONVERSION

CYCLE

START INTEGRATOR ZERO CYCLE

OUT NOT VALID

REPEAT

CONVERSION

CYCLE

6 Advanced Linear Devices ALD500AU/ALD500A/ALD500

INT Integrator capacitor connection.

-Negative power supply.

AZ The Auto-zero capacitor connection.

4 BUF The Integrator resistor buffer connection.

5 AGND This pin is analog ground.

REF Negative reference capacitor connection.

REF Positive reference capacitor connection.

REF External voltage reference (-) connection.

REF External voltage reference (+) connection.

10 V-IN Negative analog input.

11 V+IN Positive analog input.

12 A Converter phase control MSB Input.

13 B Converter phase control LSB Input.

14 COUT Comparator output. COUT is HIGH during the Integration phase when a positive input voltage is being integrated and

is LOW when a negative input voltage is being integrated. A HIGH-to-LOW transition on COUT signals the processor

that the Deintegrate phase is completed. COUT is undefined during the Auto-Zero phase. It should be monitored to

time the Integrator Zero phase.

15 DGND Digital ground.

16 V+Positive power supply.

PIN DESCRIPTION

Pin No. Symbol Description

Switch Functions

Input Reference Input Auto Zero Reference VIN=AGND System

Connect Polarity Sample Offset

Conversion Control

Phase Logic SWIN SW+R or SW-RSWAZ SWRSWGSWS

Auto Zero A = 0, B = 1 Open Open Closed Closed Closed Open

Input Signal A = 1, B = 0 Closed Open Open Open Open Open

Integration

Reference Voltage A = 1, B = 1 Open Closed* Open Open Closed Open

Deintegration

Integrator A = 0, B = 0 Open Open Open Closed Closed Closed

Output Zero

*SW+R would be closed for a positive input signal. SW-R would be closed for a negative input signal.

Table 1. Conversion Phase and Control Logic Internal Analog Switch Functions

ALD500AU/ALD500A/ALD500 Advanced Linear Devices 7

ALD500AU/ALD500A/ALD500 CONVERSION CYCLE

The ALD500AU/ALD500A/ALD500 conversion cycle takes

place in four distinct phases, the Auto Zero Phase, the Input

Signal Integration Phase, the Reference Voltage Deintegration

Phase, and the Integrator Zero Phase. A typical measurement

cycle uses all four phases in an order sequence as mentioned

above. The internal analog switch status for each of these

phases is summarized in Table 1.

The following is a detailed description of each one of the four

phases of the conversion cycle.

Auto Zero Phase (AZ Phase)

The analog-to-digital conversion cycle begins with the Auto

Zero Phase, when the digital controller applies low logic level

to input A and high logic level to input B of the analog

processor. During this phase, the reference voltage is stored

on reference capacitor CREF, comparator offset voltage and

the sum of the buffer and integrator offset voltages are stored

on auto zero capacitor C AZ. During the Auto Zero Phase, the

comparator output is characterized by an indeterminate

waveform.

During the Auto Zero Phase, the external input signal is

disconnected from the internal circuitry of the ALD500AU/

ALD500A/ALD500 by opening the two SWIN analog switches

and connecting the internal input nodes internally to analog

ground. A feedback loop, closed around the integrator and

comparator, charges the CAZ capacitor with a voltage to

compensate for buffer amplifier, integrator and comparator

offset voltages.

This is the system initialization phase, when a conversion is

ready to be initiated at system turn-on. In practice the

converter can be operated in continuous conversion mode,

where AZ phase must be long enough for the circuit conditions

to settle out any system errors. Typically this phase is set to

be equal to tINT.

Input Signal Integration Phase (INT Phase)

During the Input Signal Integration Phase (INT), the ALD500AU/

ALD500A/ALD500 integrates the differential voltage across

the (V +IN) and (V-IN) inputs. The differential voltage must be

within the device's common-mode voltage range CMVR. The

integrator charges C INT for a fixed period of time, or counts a

fixed number of clock pulses, at a rate determined by the

magnitude of the input voltage. During this phase, the analog

inputs see only the high impedance of the noninverting

operational amplifier input of the buffer. The integrator responds

only to the voltage difference between the analog input

terminals, thus providing true differential analog inputs.

The input signal polarity is determined by software control at

the end of this phase: COUT = 1 for positive input polarity;

COUT = 0 for negative input polarity. The value is, in effect, the

sign bit for the overall conversion result.

The duration of this phase is selected by design to be a fixed

time and depends on system parameters and component

value selections. The total number of clock pulses or clock

counts, during integration phase determine the resolution of

the conversion. For high resolution applications, this total

number of clock pulses should be maximized. The basic unit

of resolution is in µV/count. Before the end of this phase,

comparator output is sampled by the microcontroller. This

phase is terminated by changing logic inputs AB from 10 to 11.

Reference Voltage Deintegration Phase ( DINT Phase)

At the end of the Input Signal Integration Phase, Reference

Voltage Deintegration Phase begins. The previously charged

reference capacitor is connected with the proper polarity to

ramp the integrator output back to zero. The ALD500AU/

ALD500A/ALD500 analog processors automatically selects

the proper logic state to cause the integrator to ramp back

toward zero at a rate proportional to the reference voltage

stored on the reference capacitor. The time required to return

to zero is measured by the counter in the digital processor

using the same crystal oscillator. The phase is terminated by

the comparator output after the comparator senses when the

integrator output crosses zero. The counter contents are then

transferred to the register. The resulting time measurement

is proportional to the magnitude of the applied input voltage.

The duration of this phase is precisely measured from the

transition of AB from 10 to 11 to the falling edge of the

comparator output, usually with a crystal controlled digital

counter chain. The comparator delay contributes some error

in this phase. The typical comparator delay is 1µsec. The

comparator delay and overshoot will result in error timing,

which translates into error voltages. This error can be zeroed

and minimized during Integrator Output Zero Phase and

corrected in software, to within ±1 count of the crystal clock

(which is equivalent to within ± 1 LSB, when 1 clock pulse = 1

LSB).

Integrator Zero Phase ( INTZ Phase)

This phase guarantees the integrator output is at 0V when the

Auto Zero phase is entered, and that only system offset

voltages are compensated. This phase is used at the end of

the reference voltage deintegration and is used for applications

with high resolutions. If this phase is not used, the value of the

Auto-Zero capacitor (CAZ) must be much greater than the

value of the integration capacitor (C INT) to reduce the effects

of charge-sharing. The Integrator Zero phase should be

programmed to operate until the Output of the Comparator

returns "HIGH". A typical Integrator Zero Phase lasts 1msec.

The comparator delay and the controller's response latency

may result in Overshoot causing charge buildup on the

integrator at the end of a conversion. This charge must be

removed or performance will degrade. The Integrator Output

Zero phase should be activated (AB = 00) until COUT goes

high. At this point, the integrator output is near zero. Auto Zero

Phase should be entered (AB = 01) and the ALD500AU/

ALD500A/ALD500 is held in this state until the next conversion

cycle.

8 Advanced Linear Devices ALD500AU/ALD500A/ALD500

Differential Inputs (V+IN,V-IN)

The ALD500AU/ALD500A/ALD500 operates with differential

voltages within the input amplifier common-mode voltage

range. The amplifier common-mode range extends from 1.5V

below positive supply to 1.5V above negative supply. Within

this common-mode voltage range, common-mode rejection is

typically 95dB.

The integrator output also follows the common-mode voltage.

When large common-mode voltages with near full-scale

differential input voltages are applied, the input signal drives

the integrator output to near the supply rails where the

integrator output is near saturation. Under such conditions,

linearity of the converter may be adversely affected as the

integrator swing can be reduced. The integrator output must

not be allowed to saturate. Typically, the integrator output can

swing to within 0.9V of either supply rails without loss of

linearity.

Analog Ground

Analog Ground is V-IN during Auto Zero Phase and Reference

Voltage Deintegration Phase. If V-IN is different from analog

ground, a common-mode voltage exists at the inputs. This

common mode signal is rejected by the high common mode

rejection ratio of the converter. In most applications, V-IN is

set at a fixed known voltage (i.e., power supply ground). All

other ground connections should be connected to digital

ground in order to minimize noise at the inputs.

Differential Reference (V+REF, V-REF)

The reference voltage can be anywhere from 1V of the power

supply voltage rails of the converter. Roll-over error is caused

by the reference capacitor losing or gaining charge due to the

stray capacitance on its nodes. The difference in reference for

(+) or (-) input voltages will cause a roll-over error. This error

can be minimized by using a large reference capacitor in

comparison to the stray capacitance.

Phase Control Inputs (A, B)

The A and B logic inputs select the ALD500AU/ALD500A/

ALD500 operating phase. The A and B inputs are normally

driven by a microprocessor I/O port or external logic, using

CMOS logic levels. For logic control functions of A and B logic

inputs, see Table 1.

Comparator Output (COUT)

By monitoring the comparator output during the Input Signal

Integration Phase, which is a fixed signal integrate time

period, the input signal polarity can be determined by the

microcontroller controlling the conversion. The comparator

output is HIGH for positive signals and LOW for negative

signals during the Input Signal Integration Phase. The state of

the comparator should be checked by the microcontroller at

the end of the Input Signal Integration Phase, just before

transition to the Reference Voltage Deintegration Phase. For

very low level input signals noise may cause the comparator

output state to toggle between positive and negative states.

For the ALD500AU/ALD500A/ALD500, this noise has been

minimized to typically within one count.

At the start of the Reference Voltage Deintegration Phase,

comparator output is set to HIGH state. During the Reference

Voltage Deintegration Phase, the microcontroller must monitor

the comparator output to make a HIGH-to-LOW transition as

the integrator output ramp crosses zero relative to analog

ground. This transition indicates that the conversion is

complete. The microcontroller then stops and records the

pulse count. The internal comparator delay is 1µsec, typically.

The comparator output is undefined during the Auto Zero

Phase.

Figure 4. Comparator Output

ANALOG INPUT

INTEGRATE REFERENCE

DEINTEGRATE

ZERO

CROSSING

COMPARATOR

OUTPUT

OUT

)

REFERENCE

DEINTEGRATE

ZERO

CROSSING

INTEGRATOR

OUTPUT

INT

)

ANALOG INPUT

INTEGRATE

INTEGRATOR

OUTPUT

INT

)

Negative Input Signal (V

)

Positive Input Signal (V

)

EXTERNAL INPUT

POLARITY DETECTION

COMPARATOR

OUTPUT

OUT

)

EXTERNAL INPUT

POLARITY DETECTION

ALD500AU/ALD500A/ALD500 Advanced Linear Devices 9

APPLICATIONS AND DESIGN NOTES

Determination and Selection of System Variables

The procedure outlined below allows the user to determine the

values for the following ALD500AU/ALD500A/ALD500 system

design variables:

(1) Determine Input Voltage Range

(2) Clock Frequency and Resolution Selection

(3) Input Integration Phase Timing

(4) Integrator Timing Components (RINT, CINT)

(5) Auto Zero and Reference Capacitors

(6) Voltage Reference

System Timing

Figure 3 and Figure 4 show the overall timing for a typical

system in which ALD500AU/ALD500A/ALD500 is interfaced

to a microcontroller. The microcontroller drives the A, B inputs

with I/O lines and monitors the comparator output, COUT,

using an I/O line or dedicated timer-capture control pin. It may

be necessary to monitor the state of the comparator output in

addition to having it control a timer directly during the Reference

Deintegration Phase.

There are four critical timing events: sampling the input

polarity; capturing the deintegration time; minimizing overshoot

and properly executing the Integrator Output Zero Phase.

Selecting Input Integration Time

For maximum 50/60 cycle noise rejection, Input Integration

Time must be picked as a multiple of the period of line

frequency. For example, t INT times of 33msec, 66msec and

100 msec maximize 60Hz line rejection, and 20msec, 40

msec, 80msec, and 100 msec maximize 50Hz line rejection.

Note that tINT of 100 msec maximizes both 60 Hz and 50Hz

line rejection.

INT and DINT Phase Timing

The duration of the Reference Deintegrate Phase (D INT) is a

function of the amount of voltage charge stored on the

integrator capacitor during INT phase, and the value of VREF.

The DINT phase must be initiated immediately following INT

phase and terminated when an integrator output zero-crossing

is detected. In general, the maximum number of counts

chosen for DINT phase is twice to three times that of INT phase

with VREF chosen as a maximum voltage relative to VIN. For

example, VREF = VIN(max)/2 would be a good reference

voltage.

Integrating Resistor (RINT )

The desired full-scale input voltage and amplifier output

current capability determine the value of RINT. The buffer and

integrator amplifiers each have a full-scale current of 20µA.

The value of RINT is therefore directly calculated as follows:

RINT =V

IN MAX / 20 µA

where: VIN MAX = Maximum input voltage desired

(full count voltage)

RINT = Integrating Resistor value

For minimum noise and maximum linearity, R INT should be in

the range of between 50kΩ to 150kΩ .

Integrating Capacitor (CINT)

The integrating capacitor should be selected to maximize

integrator output voltage swing VINT, for a given integration

time, without output level saturation. For +/-5V supplies,

recommended V INT range is between +/- 3 Volt to +/-4 Volt.

Using the 20µA buffer maximum output current, the value of

the integrating capacitor is calculated as follows:

CINT = (tINT) . (20 x 10-6) / VINT

where: tINT = Input Integration Phase Period

VINT = Maximum integrator output

voltage swing

It is critical that the integrating capacitor must have a very low

dielectric absorption, as charge loss or gain during conversion

directly converts into an error voltage. Polypropylene capacitors

are recommended while Polyester and Polybicarbonate

capacitors may also be used in less critical applications.

Reference (CREF) and Auto Zero (CAZ) Capacitors

CREF and CAZ must be low leakage capacitors (e.g.

polypropylene types). The slower the conversion rate, the

larger the value CREF must be. Recommended capacitor

values for CREF and CAZ are equal to CINT. Larger values for

CAZ and CREF may also be used to limit roll-over errors.

Calculate VREF

The reference deintegration voltage is calculated using:

VREF = (VINT) . (CINT) . (RINT) / 2(tINT)

Converter Noise

The converter noise is the total algebraic sum of the integrator

noise and the comparator noise. This value is typically 14 µV

peak to peak. The higher the value of the reference voltage,

the lower the converter noise. Such sources of noise errors

can be reduced by increased integration times, which effectively

filter out any such noise. If the integration time periods are

selected as multiples of 50/60Hz frequencies, then 50/60Hz

noise is also rejected, or averaged out. The signal-to-noise

ratio is related to the integration time (tINT) and the integration

time constant (RINT) (CINT) as follows:

S/N (dB) = 20 Log ((VINT / 14 x 10-6) . tINT /(RINT . CINT))

This converter noise can also be reduced by using multiple

samples and mathematically averaged. For example, taking

16 samples and averaging the readings result in a mathematical

(by software) filtering of noise to less than 4µV.

10 Advanced Linear Devices ALD500AU/ALD500A/ALD500

EQUATIONS AND DERIVATIONS

Dual Slope Analog Processor equations and derivations

are as follows:

60Hz

2.0

20x10

-6

DESIGN EXAMPLES

We now apply these equations in the following

design examples.

Design Example 1:

1. Pick resolution = 16 bit.

2. Pick t

INT

= 4x = 4 x 16.6667 msec.

3. Pick clock period = 1.08507 µs and number of counts

4. Pick V

MAX value, e.g., V

MAX = 2.0 V

I

MAX = 20µA R

INT

= = 100 kΩ

5. Applying equation (3) to calculate C

INT:

6. Pick C

REF

and C

≥ C

INT

: C

REF

0.33 µF

7. Pick t

DINT

= 2

x t

INT

= 133.3334 msec

8. Calculate V

REF

INT

MAX

INT

DINT

MAX

4 x 0.33 x 10

-6

x 100 x 10

133.3334 x 10

-3

0.99V

1.00V

= 0.0666667 sec.

INT

(t)dt =

∫

INT

DINT

= V

REF

INT

REF

DINT

(2a)

(2)

(1)

INT

= V

INT

(3)

INT

= V

MAX

MAX (4)

For V

(t) = V

IN (constant):

From equation (2a),

Rearranging equations (3) and (4):

At V

INT =

INT

MAX, equation (6) becomes:

Combining (6a) and (7):

In equation (5b), substituting equation (8) for t

INT

For t

DINT

MAX = 2 x t

INT

equation (9) becomes:

MAX

INT

DINT

MAX

INT

DINT

(5a)

(5b)

INT

(6)

MAX = V

MAX

INT

(7)

REF

... t

INT

MAX

INT

MAX (8)

MAX

DINT

MAX

REF

INT

MAX

INT

MAX

= C

INT

MAX

INT

DINT

MAX

(9)

REF

INT

MAX

INT

(10)

INT

REF

DINT

INT

...

INT

MAX

and

At V

MAX, the current I

is also at a maximum level,

for a given R

INT

value:

(6a)

INT

= (0.0666667)(20x10

-6

)/4 where V

INT

= 4.0V

0.33 µF

Design Example 2:

1. Select resolution of 17 bit. Total number of

counts during t

INT

is131,072.

2. We can pick t

INT

of 16.6667 msec. x 5 = 83.3333 msec.

 or alternately, pick t

INT

equal

 16.6667 msec. x 6 = 100.00 msec.

 (for 60 Hz rejection)

 which is t

INT

= 20.00 msec. x 5

 

 Therefore, using t

INT

= 100 msec. would achieve

 both 50 Hz and 60 Hz cycle noise rejection. For this

 example, the following calculations would assume

t

INT

of 100 msec. Now select period equal to

 0.5425 µsec. (clock frequency of 1.8432 MHz)

= 66.6667ms

= 100.00 msec. (for 50 Hz rejection)

0.0666667

1.08507x10

-6

over t

INT

= = 61440

ALD500AU/ALD500A/ALD500 Advanced Linear Devices 11

3. Pick V

MAX = ±2V

 For I

MAX = 20µA, applying equation (4),

4. Calculate, using equation (3) for C

INT



Use C

INT

0.47µF as the closest practical value.

5. Pick C

REF

and C

= 0.47 µF

6. Pick t

DINT

= 2 x t

INT

= 200 msec.

7. Calculate the value for V

REF

, from equation (10):

REF

20x10

-6

= 0.83 µF

20x10

-6

= 0.5 µF

INT

MAX

INT

DINT

MAX

= 1.00V

= 0.1666667 sec.

0.5 x 10

-6

x 4 x 100 x 10

200 x 10

-3

Design Example 3:

1. Pick resolution of 18 bit. Total number of counts during

INT

is 262,144.

2. Pick t

INT

= 16.66667 msec. x 10 cycles

 This t

INT

allows clock period of 0.5425 µsec.

 and still achieve 18 bits resolution.

3. Again, as shown from previous example, pick V

MAX = ±2V

 For I

MAX = 20 µA, R

INT



= 100 KΩ

4. Next, we calculate C

INT:

C

INT

= (0.1666667) x (20 x 10

-6

)/4



 In this case, use CINT = 1.0 µF to keep

V

INT

< 4.0V

5. Pick C

REF

and C

= 1.0 µF

6. Select t

DINT

= 2 x t

INT

= 333.333 msec.

7. Calculate V

REF

as shown in the previous examples

and V

REF

= 1.00V

245776 or 16.276 µV/count

16.276 x V

INT

MAX

MAX = 8.138 µV/count

20 x 10

-6

2 = 100 KΩ

Design Example 4:

Objective: 5 1/2 digit + sign +over-range measurement.

1. Pick t

INT

= 133.333 msec. for 60Hz noise rejection.

(16.6667 msec. x 8 cycles)

Frequency = 1.8432 MHz

clock period = 0.5425 µsec.

During Input Integrate Phase,

For V

INT

= 4.0V, the basic resolution is

For V

MAX = 2.00V, the input resolution is

2. Pick V

range = ± 2V

For I

= 20 µA, R

INT

3. Calculate C

INT

= (0.133333) x (20 x 10

-6

)/4 = 0.67 µF

4. Pick C

REF

= C

= 0.67 µF

5. Select t

DINT

= 2 x t

INT

= 266.667 msec.

6. Calculate V

REF

as shown in Design Example 1,

substituting the appropriate values:

INT

MAX

INT

DINT

MAX

REF

= 1.005V

INT

= = 100 K Ω

INT

= (0.1) x (20 x 10

-6

/4)

 ~

133.333 x 10

-3

0.5425 x 10

-6

(assume V

INT

MAX = 4V)

INT

MAX = 4.0V)

total count =

= 245776