Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 LM5035C PWM Controller With Integrated Half-Bridge and SyncFET Drivers 1 Features 3 Description * * The LM5035C half-bridge controller and gate driver contains all of the features necessary to implement half-bridge topology power converters using voltage mode control with line voltage feedforward. 1 * * * * * * * * * * * * * 105-V and 2-A Half-Bridge Gate Drivers Synchronous Rectifier Control Outputs With Programmable Delays Reduced Dead Time Between High and Low-Side Drive for Higher Maximum Duty Cycle. High Voltage (105 V) Start-Up Regulator Voltage Mode Control With Line Feedforward and Volt Second Limiting Resistor Programmed, 2-MHz Capable Oscillator Programmable Line Undervoltage Lockout and Overvoltage Protection Internal Thermal Shutdown Protection Adjustable Soft Start Versatile Dual Mode Overcurrent Protection With Hiccup Delay Timer Cycle-by-Cycle Overcurrent Protection Direct Opto-coupler Interface Logic Level Synchronous Rectifier Drives 5-V Reference Output Packages: - HTSSOP-20 (Thermally Enhanced) - WQFN-24 (4mm x 5mm) The LM5035, LM5035A, LM5035B, and LM5035C include a floating high-side gate driver, which is capable of operating with supply voltages up to 105 V. Both the high-side and low-side gate drivers are capable of 2-A peak. An internal high-voltage start-up regulator is included, along with programmable line undervoltage lockout (UVLO) and overvoltage protection (OVP). The oscillator is programmed with a single resistor to frequencies up to 2 MHz. The oscillator can also be synchronized to an external clock. A current sense input and a programmable timer provide cycle-by-cycle current limit and adjustable hiccup mode overload protection. The differences between LM5035, LM5035A, LM5035B, and LM5035C are summarized in the Device Comparison Table. Device Information(1) PART NUMBER 2 Applications * * The LM5035C is a functional variant of the LM5035B half-bridge PWM controller. The amplitude of the SR1 and SR2 waveforms are 5 V instead of the VCC level. Also, the soft-stop function is disabled in the LM5035C. Industrial Power Converters Telecom Power Converters LM5035C PACKAGE BODY SIZE (NOM) HTSSOP (20) 6.50 mm x 4.40 mm WQFN (24) 5.00 mm x 4.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application Diagram VPWR LM5035C VIN HO VOUT UVLO OVP LO RAMP RT SS SR2 SR1 COMP AGND PGND GATE DRIVE ISOLATION ERROR AMP AND ISOLATION Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 8 1 1 1 2 3 4 6 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Typical Characteristics ............................................ 10 Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 20 9 Application and Implementation ........................ 21 9.1 Application Information............................................ 21 9.2 Typical Application .................................................. 21 10 Power Supply Recommendations ..................... 33 11 Layout................................................................... 33 11.1 Layout Guidelines ................................................. 33 11.2 Layout Example .................................................... 34 12 Device and Documentation Support ................. 35 12.1 12.2 12.3 12.4 12.5 12.6 Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resource............................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 35 35 35 35 35 35 13 Mechanical, Packaging, and Orderable Information ........................................................... 35 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2013) to Revision D Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 * Changed HBM value from 2000 to 1500 in the ESD Ratings table ................................................................................... 6 * Changed thermal values in the Thermal Information table to align with JEDEC standards................................................... 6 * Deleted THERMAL RESISTANCE section from the Electrical Characteristics table............................................................. 9 Changes from Revision B (March 2013) to Revision C * 2 Page Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 22 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 5 Device Comparison Table PERFORMANCE FEATURE (1) (2) Sync Rectifier Dead-time Ratio (T1:T2) Soft-start: Hiccup Mode Charging Current Bootstrap (HB-HS) Undervoltage Lockout LM5035 LM5035A LM5035B 2:1 3:1 3:1 LM5035C 3:1 50 A:1 A 100 A:1 A 100 A:1 A 100 A:1 A 5V 3.9 V 3.9 V 3.9 V 20 mA (min) 25 mA (min) 40 mA (min) 40 mA (min) SR State in UVLO Shutdown and Hiccup Current Limit High High Low Low HO,LO On-Time at Maximum Duty Cycle Start-up Regulator Current Soft-Stop after UVLO 0.5*T-T1-70 ns 0.5*T-T1-70 ns 0.5*T-T1 0.5*T-T1 HO,LO Yes Yes Yes No SR1,2 Yes Yes No No VCC VCC VCC REF (5 V) SR1, SR2 VOH (high state output) (1) (2) T1 = Delay from SR1, SR2 to leading edge of HO, LO T = Period of HO or LO Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 3 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com 6 Pin Configuration and Functions PWP Package 20-Pin HTSSOP Top View UVLO 2 19 REF OVP 3 18 SR1 COMP 4 17 SR2 RT 5 16 VCC NC VIN VIN 20 NC 1 RAMP RAMP UVLO NHZ Package 24-Pin WQFN Top View 24 23 22 21 20 NC 1 19 REF OVP 2 18 SR1 COMP 3 17 SR2 RT 4 16 VCC AGND 5 15 PGND CS 6 14 LO SS 7 13 HO EP 7 14 LO SS 8 13 13 HO DLY 9 12 HS RES 10 11 HB EP 8 9 10 11 12 HS CS HB PGND NC 15 RES 6 DLY AGND Pin Functions PIN NAME HTSSOP WQFN RAMP 1 23 I/O I DESCRIPTION APPLICATION INFORMATION Modulator ramp signal An external RC circuit from VIN sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET. Discharge is initiated by either the internal clock or the Volt * Second clamp comparator. UVLO 2 24 I Line Undervoltage Lockout An external voltage divider from the power source sets the shutdown and standby comparator levels. When UVLO reaches the 0.4-V threshold the VCC and REF regulators are enabled. When UVLO reaches the 1.25-V threshold, the SS pin is released and the device enters the active mode. Hysteresis is set by an internal current sink that pulls 23 A from the external resistor divider. OVP 3 2 I Line Overvoltage Protection An external voltage divider from the power source sets the shutdown levels. The threshold is 1.25 V. Hysteresis is set by an internal current source that sources 23 A into the external resistor divider. I/O Input to the Pulse Width Modulator An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror. The PWM duty cycle is maximum with zero input current, while 1 mA reduces the duty cycle to zero. The current mirror improves the frequency response by reducing the AC voltage across the opto-coupler detector. Oscillator Frequency Control and Sync Clock Input. Normally biased at 2 V. An external resistor connected between RT and AGND sets the internal oscillator frequency. The internal oscillator can be synchronized to an external clock with a frequency higher than the free running frequency set by the RT resistor. Analog Ground Connect directly to Power Ground. COMP 4 3 RT 5 4 I AGND 6 5 GND 4 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 Pin Functions (continued) PIN NAME I/O DESCRIPTION APPLICATION INFORMATION HTSSOP WQFN CS 7 6 I Current Sense input for current limit If CS exceeds 0.25 V the output pulse will be terminated, entering cycle-by-cycle current limit. An internal switch holds CS low for 50 ns after HO or LO switches high to blank leading edge transients. SS 8 7 I Soft-start Input An internal 110-A current source charges an external capacitor to set the soft-start rate. During a current limit restart sequence, the internal current source is reduced to 1.2 A to increase the delay before retry. DLY 9 8 I Timing programming pin for An external resistor to ground sets the timing for the nonthe LO and HO to SR1 and overlap time of HO to SR1 and LO to SR2. SR2 outputs. Restart Timer If cycle-by-cycle current limit is exceeded during any cycle, a 22-A current is sourced to the RES pin capacitor. If the RES capacitor voltage reaches 2.5 V, the soft-start capacitor will be fully discharged and then released with a pullup current of 1.2 A. After the first output pulse at LO (when SS > COMP offset, typically 1 V), the SS pin charging current will revert to 110 A. RES 10 9 I HB 11 11 I/O Boost voltage for the HO driver An external diode is required from VCC to HB and an external capacitor is required from HS to HB to power the HO gate driver. HS 12 12 I/O Switch node Connection common to the transformer and both power switches. Provides a return path for the HO gate driver. HO 13 13 O High-side gate drive output. Output of the high-side PWM gate driver. Capable of sinking 2-A peak current. LO 14 14 O Low-side gate drive output. Output of the low-side PWM gate driver. Capable of sinking 2-A peak current. PGND 15 15 GND Power Ground Connect directly to Analog Ground. VCC 16 16 I/O Output of the high-voltage If an auxiliary winding raises the voltage on this pin start-up regulator. The VCC above the regulation setpoint, the start-up regulator will voltage is regulated to 7.6 shut down, thus reducing the internal power dissipation. V. SR2 17 17 O Synchronous rectifier driver output. Control output of the synchronous FET gate. Capable of 0.5-A peak current. SR1 18 18 O Synchronous rectifier driver output. Control output of the synchronous FET gate. Capable of 0.5-A peak current. REF 19 19 O Output of 5-V Reference Maximum output current is 20 mA. Locally decoupled with a 0.1-F capacitor. VIN 20 21 I Input voltage source Input to the start-up regulator. Operating input range is 13 V to 100 V with transient capability to 105 V. For power sources outside of this range, the LM5035C can be biased directly at VCC by an external regulator. EP EP EP GND Exposed Pad, underside of package No electrical contact. Connect to system ground plane for reduced thermal resistance. NC -- 1 -- No connection No electrical contact. NC -- 10 -- No connection No electrical contact. NC -- 20 -- No connection No electrical contact. NC -- 22 -- No connection No electrical contact. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 5 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) MIN MAX UNIT -0.3 105 V HS to GND -1 105 V HB to GND -0.3 118 V HB to HS -0.3 18 V VCC to GND -0.3 16 V RT, DLY to GND -0.3 5.5 V 10 mA 1 V VIN to GND COMP input current CS All other inputs to GND -0.3 Junction temperature Storage temperature (1) (2) -65 7 V 150 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and specifications. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 1500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) MIN VIN voltage External voltage applied to VCC Operating junction temperature (1) NOM MAX UNIT 105 V 13 8 15 V -40 125 C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For ensured specifications and test conditions, see Electrical Characteristics. 7.4 Thermal Information LM5035C THERMAL METRIC (1) PWP (HTSSOP) NHZ (WQFN) 20 PINS 24 PINS UNIT RJA Junction-to-ambient thermal resistance 35.9 31.3 C/W RJC(top) Junction-to-case (top) thermal resistance 19.8 25 C/W RJB Junction-to-board thermal resistance 16.7 9.9 C/W JT Junction-to-top characterization parameter 0.4 0.2 C/W JB Junction-to-board characterization parameter 16.6 10.1 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 1.6 1.6 C/W (1) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 7.5 Electrical Characteristics Specifications with standard typeface are for TJ = 25C, unless indicating that type applies over full operating junction temperature range. VVIN = 48 V, VVCC = 10 V externally applied, RRT = 15 k, RDLY = 27.4 k, VUVLO = 3 V, VOVP = 0 V unless otherwise stated. See (1) and (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT START-UP REGULATOR (VCC PIN) TJ = 25C VVCC VCC voltage IVCC = 10 mA IVCC(LIM) VCC current limit VVCC = 7 V, TJ = -40C to 125C VVCCUV IVIN TJ = -40C to 125C 7.6 7.3 58 TJ = 25C VCC undervoltage threshold (VCC increasing) VIN = VCC, VVCC from the regulation setpoint VCC decreasing VCC - PGND Start-up regulator current VIN = 90 V, UVLO = 0 V Supply current into VCC from external source Outputs and COMP open, TJ = 25C VVCC = 10 V, Outputs TJ = -40C to 125C Switching TJ = -40C to 125C V 0.2 6.2 5.5 TJ = 25C V mA 0.1 TJ = 25C TJ = -40C to 125C 7.9 6.9 30 TJ = -40C to 125C 70 V A 4 6 mA VOLTAGE REFERENCE REGULATOR (REF PIN) VREF REF voltage IREF = 0 mA REF voltage regulation IREF = 0 to 10 mA REF current limit REF = 4.5 V TJ = 25C TJ = -40C to 125C 5 4.85 TJ = 25C 5.15 25 TJ = -40C to 125C 50 TJ = 25C TJ = -40C to 125C 20 V mV mA 15 UNDERVOLTAGE LOCKOUT AND SHUTDOWN (UVLO PIN) TJ = 25C 1.25 VUVLO Undervoltage threshold IUVLO Hysteresis current UVLO pin sinking Undervoltage shutdown threshold UVLO voltage falling 0.3 V Undervoltage standby enable threshold UVLO voltage rising 0.4 V TJ = -40C to 125C 1.212 TJ = 25C TJ = -40C to 125C 1.288 23 19 27 V A OVERVOLTAGE PROTECTION (OVP PIN) VOVP Overvoltage threshold IOVP Hysteresis current TJ = 25C 1.25 TJ = -40C to 125C OVP pin sourcing 1.212 TJ = 25C TJ = -40C to 125C 1.288 23 19 27 V A CURRENT SENSE INPUT (CS PIN) VCS Current limit threshold CS delay to output TJ = 25C 0.25 TJ = -40C to 125C 0.288 CS from zero to 1 V. Time for HO and LO to fall to 90% of VCC. Output load = 0 pF. Leading edge blanking time at CS CS sink impedance (clocked) (1) (2) Internal FET sink impedance TJ = 25C TJ = -40C to 125C 0.272 V 80 ns 50 ns 32 60 All limits are ensured. All electrical characteristics having room temperature limits are tested during production with TA = 25C. All hot and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Typical specifications represent the most likely parametric norm at 25C operation Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 7 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25C, unless indicating that type applies over full operating junction temperature range. VVIN = 48 V, VVCC = 10 V externally applied, RRT = 15 k, RDLY = 27.4 k, VUVLO = 3 V, VOVP = 0 V unless otherwise stated. See (1) and (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT RESTART (RES PIN) VRES RES threshold TJ = 25C 2.5 TJ = -40C to 125C Charge source current VRES = 1.5 V Discharge sink current VRES = 1 V 2.4 TJ = 25C 2.6 22 TJ = -40C to 125C 16 TJ = 25C 28 12 TJ = -40C to 125C 8 16 V A A SOFT-START (SS PIN) Charging current in normal operation ISS TJ = 25C VSS = 0 110 TJ = -40C to 125C 80 TJ = 25C Charging current during a hiccup VSS = 0 mode restart 140 1.2 TJ = -40C to 125C 0.6 1.8 A A OSCILLATOR (RT PIN) FSW1 Frequency 1 (at HO, half oscillator frequency) FSW2 Frequency 2 (at HO, half oscillator frequency) RRT = 15 k RRT = 15 k RRT = 5.49 k TJ = 25C 200 TJ = -40C to 125C 185 TJ = -40C to 125C 180 TJ = 25C TJ = -40C to 125C 430 570 2 TJ = 25C 2.5 kHz V 3 TJ = -40C to 125C kHz 220 500 DC level Input sync threshold 215 3.4 V PWM CONTROLLER (COMP PIN) Delay to output VPWM-OS SS to RAMP offset 80 TJ = 25C ns 1 TJ = -40C to 125C 0.7 Minimum duty cycle SS = 0 V Small signal impedance ICOMP = 600 A, COMP current to PWM voltage 1.2 TJ = -40C to 125C V 0% 6200 MAIN OUTPUT DRIVERS (HO AND LO PINS) 8 TJ = 25C 0.25 Output high voltage IOUT = 50 mA, VHB - VHO, VVCC - VLO Output low voltage IOUT = 100 mA Rise time CLOAD = 1 nF 15 ns Fall time CLOAD = 1 nF 13 ns Peak source current VHO,LO = 0 V, VVCC = 10 V 1.25 A Peak sink current VHO,LO = 10 V, VVCC = 10 V 2 A HB threshold VCC rising 3.8 V TJ = -40C to 125C TJ = 25C 0.2 TJ = -40C to 125C Submit Documentation Feedback V 0.5 0.5 V Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25C, unless indicating that type applies over full operating junction temperature range. VVIN = 48 V, VVCC = 10 V externally applied, RRT = 15 k, RDLY = 27.4 k, VUVLO = 3 V, VOVP = 0 V unless otherwise stated. See (1) and (2). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE FEED-FORWARD (RAMP PIN) RAMP comparator threshold COMP current = 0 TJ = 25C TJ = -40C to 125C 2.5 2.4 2.6 V SYNCHRONOUS RECTIFIER DRIVERS (SR1, SR2) TJ = 25C 0.1 Output high voltage IOUT = 5 mA, VREF - VSR1, VREF - VSR2 Output low voltage IOUT = 10 mA (sink) Rise time CLOAD = 1 nF 40 ns Fall time CLOAD = 1 nF 20 ns Peak source current VSR = 0 0.09 A Peak sink current VSR = VREF 0.2 A 33 ns TJ = -40C to 125C TJ = 25C 0.08 TJ = -40C to 125C 0.2 RDLY = 10 k T1 T2 Dead time, SR1 falling to HO rising, SR2 falling to LO rising Dead time, HO falling to SR1 rising, LO falling to SR2 rising RDLY = 27.4 k TJ = 25C TJ = -40C to 125C V 0.25 86 68 120 V ns RDLY = 100 k 300 ns RDLY = 10 k 18 ns RDLY = 27.4 k TJ = 25C TJ = -40C to 125C RDLY = 100 k 26 15 39 ns 80 ns 165 C 20 C THERMAL SHUTDOWN TSD Shutdown temperature Hysteresis Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 9 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com 7.6 Typical Characteristics 8 8 7 7 6 5 5 VVCC (V) VREF 4 3 4 3 2 2 1 1 0 0 5 10 15 0 10 20 20 6 70 900 OSCILLATOR FREQUENCY (kHz) 4 3 2 1 800 700 600 500 400 300 200 100 0 0 0 5 10 15 20 25 0 10 20 IREF (mA) Figure 3. VREF vs IREF SOFT-START and STOP CURRENT (PA) RRT = 15k 400 395 0 40 40 50 Figure 4. Frequency vs RT 405 390 -40 30 RRT (k:) 410 OSCILLATOR FREQUENCY (kHz) 60 1000 5 80 120 120 30 116 29 SOFT-START 112 28 108 27 104 26 100 25 96 24 92 23 88 22 RESTART 84 80 -40 TEMPERATURE (C) 21 20 0 40 80 120 TEMPERATURE (C) Figure 5. Oscillator Frequency vs Temperature 10 50 40 Figure 2. VVCC vs IVCC Figure 1. VVCC and VREF vs VVIN VREF (V) 30 IVCC (mA) VVIN (V) RESTART CURRENT (PA) VVCC and VREF (V) VVCC 6 Figure 6. Soft-Start Current vs Temperature Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 Typical Characteristics (continued) 6500 HO/LO to SR DEADTIME (ns) 350 RESISTANCE (:) 6000 5500 5000 4500 4000 -40 0 40 80 300 250 200 T1 150 100 T2 50 120 0 0 TEMPERATURE (C) 20 40 60 80 100 RDLY (k:) Figure 7. Effective Comp Input Impedance Figure 8. RDLY vs Dead Time 32 105 100 31 95 30 T2 (ns) T1 (ns) 90 85 80 29 28 RDLY = 27.4 k: 75 RDLY = 27.4 k: 27 70 65 -40 0 40 80 26 -40 120 0 40 80 120 TEMPERATURE (C) TEMPERATURE (C) Figure 9. SR T1 Parameter vs Temperature Figure 10. SR T2 Parameter vs Temperature Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 11 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com 8 Detailed Description 8.1 Overview The LM5035C PWM controller contains all of the features necessary to implement half-bridge voltage-mode controlled power converters. The LM5035C provides two gate driver outputs to directly drive the primary side power MOSFETs and two signal level outputs to control secondary synchronous rectifiers through an isolation interface. Secondary side drivers, such as the LM5110, are typically used to provide the necessary gate drive current to control the sync MOSFETs. Synchronous rectification allows higher conversion efficiency and greater power density than conventional PN or Schottky rectifier techniques. The LM5035C can be configured to operate with bias voltages ranging from 8 V to 105 V. Additional features include line undervoltage lockout, cycle-by-cycle current limit, voltage feedforward compensation, hiccup mode fault protection with adjustable delays, soft start, a 2-MHz capable oscillator with synchronization capability, precision reference, thermal shutdown, and programmable volt*second clamping. These features simplify the design of voltage-mode half-bridge DC-DC power converters. See Functional Block Diagram. 12 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 8.2 Functional Block Diagram 7.7V SERIES REGULATOR VCC VIN Vcc UVLO UVLO 0.4V SHUTDOWN 1.25V STANDBY REF REFERENCE DLY 20 PA HB LOGIC THERMAL LIMIT (165C) HO 20 PA +5V OVP HS STANDBY VCC 1.25V T1 and T2 Timer Q RT/SYNC OSCILLATOR T CLK LO Q S ref Q SR1 FEEDFORWARD RAMP: R RAMP ref VREF SR2 5k PWM S COMP Q STANDBY 1V R SS HICCUP SS Buffer (Sink Only) CURRENT LIMIT LOGIC 2.5V MAX V*S CLAMP 2.5V +5V CS D 0.25V Q 22 PA CLK CLK + LEB RES +5V +5V 12 PA 110 PA 1 PA PGND SS AGND Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 13 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com 8.3 Feature Description 8.3.1 High-Voltage Start-Up Regulator The LM5035C contains an internal high-voltage start-up regulator that allows the input pin (VIN) to be connected directly to a nominal 48-VDC input voltage. The regulator input can withstand transients up to 105 V. The regulator output at VCC (7.6 V) is internally current-limited to a minimum of 58 mA. When the UVLO pin potential is greater than 0.4 V, the VCC regulator is enabled to charge an external capacitor connected to the VCC pin. The VCC regulator provides power to the voltage reference (REF) and the output driver (LO). When the voltage on the VCC pin exceeds the UVLO threshold of 7.6 V, the internal voltage reference (REF) reaches its regulation setpoint of 5 V and the UVLO voltage is greater than 1.25 V, the controller outputs are enabled. The value of the VCC capacitor depends on the total system design, and its start-up characteristics. The recommended range of values for the VCC capacitor is 0.1 F to 100 F. The VCC undervoltage comparator threshold is lowered to 6.2 V (typical) after VCC reaches the regulation setpoint. If VCC falls below this value, the outputs are disabled, and the soft-start capacitor is discharged. If VCC increases above 7.6 V, the outputs will be enabled and a soft-start sequence will commence. The internal power dissipation of the LM5035C can be reduced by powering VCC from an external supply. In typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8.3 V to shut off the internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the controller's power dissipation. The undervoltage comparator circuit will still function in this mode, requiring that VCC never falls below 6.2 V during the start-up sequence. During a fault mode, when the converter auxiliary winding is inactive, external current draw on the VCC line should be limited such that the power dissipated in the start-up regulator does not exceed the maximum power dissipation of the IC package. An external DC bias voltage can be used instead of the internal regulator by connecting the external bias voltage to both the VCC and the VIN pins. The external bias must be greater than 8.3 V to exceed the VCC UVLO threshold and less than the VCC maximum operating voltage rating (15 V). 8.3.2 Line Undervoltage Detector The LM5035C contains a dual level undervoltage lockout (UVLO) circuit. When the UVLO pin voltage is below 0.4 V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4 V but less than 1.25 V, the controller is in standby mode. In standby mode the VCC and REF bias regulators are active while the controller outputs are disabled. When the VCC and REF outputs exceed the VCC and REF undervoltage thresholds and the UVLO pin voltage is greater than 1.25 V, the outputs are enabled and normal operation begins. An external setpoint voltage divider from VIN to GND can be used to set the minimum operating voltage of the converter. The divider must be designed such that the voltage at the UVLO pin will be greater than 1.25 V when VIN enters the desired operating range. UVLO hysteresis is accomplished with an internal 23-A current sink that is switched ON or OFF into the impedance of the setpoint divider. When the UVLO threshold is exceeded, the current sink is deactivated to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.25-V threshold, the current sink is enabled causing the voltage at the UVLO pin to quickly fall. The hysteresis of the 0.4-V shutdown comparator is internally fixed at 100 mV. The UVLO pin can also be used to implement various remote enable and disable functions. See Soft Start for more details. 8.3.3 Line Overvoltage, Load Overvoltage, and Remote Thermal Protection The LM5035C provides a multipurpose OVP pin that supports several fault protection functions. When the OVP pin voltage exceeds 1.25 V, the controller is held in standby mode, which immediately halts the PWM pulses at the HO and LO pins. In standby mode, the VCC and REF bias regulators are active while the controller outputs are disabled. When the OVP pin voltage falls below the 1.25-V OVP threshold, the outputs are enabled, and normal soft-start sequence begins. Hysteresis is accomplished with an internal 23-A current source that is switched ON or OFF into the impedance of the OVP pin setpoint divider. When the OVP threshold is exceeded, the current source is enabled to quickly raise the voltage at the OVP pin. When the OVP pin voltage falls below the 1.25-V threshold, the current source is disabled causing the voltage at the OVP pin to quickly fall. Several examples of the use of this pin are provided in Application Information. 14 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 Feature Description (continued) 8.3.4 Reference The REF pin is the output of a 5-V linear regulator that can be used to bias an opto-coupler transistor and external housekeeping circuits. The regulator output is internally current limited to 15 mA (minimum). 8.3.5 Cycle-by-Cycle Current Limit The CS pin is driven by a signal representative of the transformer primary current. If the voltage sensed at CS pin exceeds 0.25 V, the current sense comparator terminates the HO or LO output driver pulse. If the high current condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the current sense comparator instead of the PWM comparator. Cycle-by-cycle current limiting may trigger the hiccup mode restart cycle depending on the configuration of the RES pin (see the following). A small R-C filter connect to the CS pin and located near the controller is recommended to suppress noise. An internal 32- MOSFET connected to the CS input discharges the external current sense filter capacitor at the conclusion of every cycle. The discharge MOSFET remains on for an additional 50 ns after the HO or LO driver switches high to blank leading edge transients in the current sensing circuit. Discharging the CS pin filter each cycle and blanking leading edge spikes reduces the filtering requirements and improves the current sense response time. The current sense comparator is very fast and responds to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the CS and AGND pins. If a current sense transformer is used, both leads of the transformer secondary should be routed to the filter network, which should be located close to the IC. If a sense resistor located in the source of the main MOSFET switch is used for current sensing, a low inductance type of resistor is required. When designing with a current sense resistor, all of the noise sensitive low power ground connections should be connected together near the AGND pin, and a single connection should be made to the power ground (sense resistor ground point). 8.3.6 Overload Protection Timer The LM5035C provides a current limit restart timer to disable the outputs and force a delayed restart (hiccup mode) if a current limit condition is repeatedly sensed. The number of cycle-by-cycle current limit events required to trigger the restart is programmable by the external capacitor at the RES pin. During each PWM cycle, the LM5035C either sources or sinks current from the RES pin capacitor. If no current limit is detected during a cycle, a 12-A discharge current sink is enabled to pull the RES pin to ground. If a current limit is detected, the 12-A sink current is disabled and a 22-A current source causes the voltage at the RES pin to gradually increase. The LM5035C protects the converter with cycle-by-cycle current limiting while the voltage at RES pin increases. If the RES voltage reaches the 2.5-V threshold, the following restart sequence occurs (also see Figure 11): * The RES capacitor and SS capacitors are fully discharged * The soft-start current source is reduced from 110 A to 1 A * The SS capacitor voltage slowly increases. When the SS voltage reaches 1 V, the PWM comparator will produce the first narrow output pulse. After the first pulse occurs, the SS source current reverts to the normal 110-A level. The SS voltage increases at its normal rate, gradually increasing the duty cycle of the output drivers * If the overload condition persists after restart, cycle-by-cycle current limiting will begin to increase the voltage on the RES capacitor again, repeating the hiccup mode sequence * If the overload condition no longer exists after restart, the RES pin will be held at ground by the 12-A current sink and normal operation resumes The overload timer function is very versatile and can be configured for the following modes of protection: 1. Cycle-by-cycle only: The hiccup mode can be completely disabled by connecting a zero to 50-k resistor from the RES pin to AGND. In this configuration, the cycle-by-cycle protection will limit the output current indefinitely and no hiccup sequences will occur. 2. Hiccup only: The timer can be configured for immediate activation of a hiccup sequence upon detection of an overload by leaving the RES pin open circuit. 3. Delayed Hiccup: Connecting a capacitor to the RES pin provides a programmed interval of cycle-by-cycle limiting before initiating a hiccup mode restart, as previously described. The dual advantages of this Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 15 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com Feature Description (continued) configuration are that a short term overload will not cause a hiccup mode restart but during extended overload conditions, the average dissipation of the power converter will be very low. 4. Externally Controlled Hiccup: The RES pin can also be used as an input. By externally driving the pin to a level greater than the 2.5-V hiccup threshold, the controller will be forced into the delayed restart sequence. For example, the external trigger for a delayed restart sequence could come from an overtemperature protection circuit or an output overvoltage sensor. Current Sense Circuit Current Limit CS 5V Restart Current Source Logic 0.25 V CLK 22 PA CRES SS Voltage Feedback COMP 2.5V To Output Drivers PWM S Restart Latch 110 PA SS 110 PA CSS Restart Comparator R Q Drivers Off 1 PA RES 12 PA 100 mV SS Logic Drivers Off LM5035C Copyright (c) 2016, Texas Instruments Incorporated Figure 11. Current Limit Restart Circuit 2.5V Current Limit Detected at CS RES 0V 5V +110 PA #1V +1 PA SS LO HO t1 t2 t3 Figure 12. Current Limit Restart Timing 16 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 Feature Description (continued) REF 5V FEED-FORWARD RAMP + 5k _ 1V COMP 1:1 LM4041 Voltage feedback PWM COMPARATOR Potential across Optocoupler detector is constant (approx. 4.3 V) SOFT-START LM5035C Copyright (c) 2016, Texas Instruments Incorporated Figure 13. Optocoupler to COMP Interface 8.3.7 Soft Start The soft-start circuit allows the regulator to gradually reach a steady state operating point, thereby reducing startup stresses and current surges. When bias is supplied to the LM5035C, the SS pin capacitor is discharged by an internal MOSFET. When the UVLO, VCC and REF pins reach their operating thresholds, the SS capacitor is released and charged with a 110-A current source. The PWM comparator control voltage is clamped to the SS pin voltage by an internal amplifier. When the PWM comparator input reaches 1 V, output pulses commence with slowly increasing duty cycle. The voltage at the SS pin eventually increases to 5 V, while the voltage at the PWM comparator increases to the value required for regulation as determined by the voltage feedback loop. One method to shutdown the regulator is to ground the SS pin. This forces the internal PWM control signal to ground, reducing the output duty cycle quickly to zero. Releasing the SS pin begins a soft-start cycle and normal operation resumes. A second shutdown method is discussed in UVLO. 8.3.8 PWM Comparator The pulse width modulation (PWM) comparator compares the voltage ramp signal at the RAMP pin to the loop error signal. This comparator is optimized for speed to achieve minimum controllable duty cycles. The loop error signal is received from the external feedback and isolation circuit is in the form of a control current into the COMP pin. The COMP pin current is internally mirrored by a matched pair of NPN transistors which sink current through a 5-k resistor connected to the 5-V reference. The resulting control voltage passes through a 1-V level shift before being applied to the PWM comparator. An opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is controlled by a current input, the potential difference across the optocoupler detector is nearly constant. The bandwidth limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is thereby greatly reduced. Higher loop bandwidths can be realized because the bandwidth-limiting pole associated with the opto-coupler is now at a much higher frequency. The PWM comparator polarity is configured such that with no current into the COMP pin, the controller produces the maximum duty cycle at the main gate driver outputs, HO and LO. 8.3.9 Feedforward Ramp and Volt * Second Clamp An external resistor (RFF) and capacitor (CFF) connected to VIN, AGND, and the RAMP pin are required to create the PWM ramp signal. The slope of the signal at RAMP will vary in proportion to the input line voltage. This varying slope provides line feedforward information necessary to improve line transient response with voltage mode control. The RAMP signal is compared to the error signal by the pulse width modulator comparator to control the duty cycle of the HO and LO outputs. With a constant error signal, the on-time (TON) varies inversely with the input voltage (VIN) to stabilize the Volt * Second product of the transformer primary signal. The power path gain of conventional voltage-mode pulse width modulators (oscillator generated ramp) varies directly with input voltage. The use of a line generated ramp (input voltage feedforward) nearly eliminates this gain variation. As a result, the feedback loop is only required to make very small corrections for large changes in input voltage. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 17 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com Feature Description (continued) In addition to the PWM comparator, a Volt * Second Clamp comparator also monitors the RAMP pin. If the ramp amplitude exceeds the 2.5-V threshold of the Volt * Second Clamp comparator, the on-time is terminated. The CFF ramp capacitor is discharged by an internal 32- discharge MOSFET controlled by the V*S Clamp comparator. If the RAMP signal does not exceed 2.5 V before the end of the clock period, then the internal clock will enable the discharge MOSFET to reset capacitor CFF. By proper selection of RFF and CFF values, the maximum on-time of HO and LO can be set to the desired duration. The on-time set by the Volt * Second Clamp varies inversely to the line voltage because the RAMP capacitor is charged by a resistor (RFF) connected to VIN while the threshold of the clamp is a fixed voltage (2.5 V). An example will illustrate the use of the Volt * Second Clamp comparator to achieve a 50% duty cycle limit at 200 kHz with a 48-V line input. A 50% duty cycle at a 200 kHz requires a 2.5-s on-time. To achieve this maximum on-time clamp level, use Equation 1. (c) (c) In 1- 2.5V -1 VIN = 2.5 Ps + 0.25 Ps (c) In 1- (c) TON (1 + 10%) RFF x CFF = 2.5V -1 48V = 51.4 Ps (1) The recommended capacitor value range for CFF is 100 pF to 1000 pF. 470 pF is a standard value that can be paired with an 110 k to approximate the desired 51.4-s time constant. If load transient response is slowed by the 10% margin, the RFF value can be increased. The system signal-to-noise will be slightly decreased by increasing RFF x CFF. 8.3.10 Oscillator, Sync Capability The LM5035C oscillator frequency is set by a single external resistor connected between the RT and AGND pins. To set a desired oscillator frequency, the necessary RT resistor is calculated from Equation 2. 1 (c) FOSC (c) RT = - 110 ns x 6.25 x 109 (2) For example, if the desired oscillator frequency is 400 kHz (HO and LO each switching at 200 kHz) a 15-k resistor would be the nearest standard one percent value. Each output (HO, LO, SR1 and SR2) switches at half the oscillator frequency. The voltage at the RT pin is internally regulated to a nominal 2 V. The RT resistor should be located as close as possible to the IC, and connected directly to the pins (RT and AGND). The tolerance of the external resistor, and the frequency tolerance indicated in Electrical Characteristics, must be considered when determining the worst-case frequency range. The LM5035C can be synchronized to an external clock by applying a narrow pulse to the RT pin. The external clock must be at least 10% higher than the free-running oscillator frequency set by the RT resistor. If the external clock frequency is less than the RT resistor programmed frequency, the LM5035C will ignore the synchronizing pulses. The synchronization pulse width at the RT pin must be a minimum of 15 ns wide. The clock signal should be coupled into the RT pin through a 100-pF capacitor or a value small enough to ensure the pulse width at RT is less than 60% of the clock period under all conditions. When the synchronizing pulse transitions low-to-high (rising edge), the voltage at the RT pin must be driven to exceed 3.2 V from its nominal 2-VDC level. During the clock signal's low time, the voltage at the RT pin will be clamped at 2 VDC by an internal regulator. The output impedance of the RT regulator is approximately 100 . The RT resistor is always required, whether the oscillator is free running or externally synchronized. 8.3.11 Gate Driver Outputs (HO and LO) The LM5035C provides two alternating gate driver outputs: the floating high-side gate driver HO and the ground referenced low-side driver LO. Each driver is capable of sourcing 1.25 A and sinking 2-A peak. The HO and LO outputs operate in an alternating manner, at one-half the internal oscillator frequency. The LO driver is powered directly by the VCC regulator. The HO gate driver is powered from a bootstrap capacitor connected between HB and HS. An external diode connected between VCC (anode pin) and HB (cathode pin) provides the high-side gate driver power by charging the bootstrap capacitor from VCC when the switch node (HS pin) is low. When the high-side MOSFET is turned on, HB rises to a peak voltage equal to VVCC + VHS where VHS is the switch node voltage. 18 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 Feature Description (continued) The HB and VCC capacitors should be placed close to the pins of the LM5035C to minimize voltage transients due to parasitic inductances since the peak current sourced to the MOSFET gates can exceed 1.25 A. The recommended value of the HB capacitor is 0.01 F or greater. A low ESR or ESL capacitor, such as a surface mount ceramic, should be used to prevent voltage droop during the HO transitions. The maximum duty cycle for each output is equal to or slightly less than 50% due to any programmed sync rectifier delay. The programmed sync rectifier delay is determined by the DLY pin resistor. If the COMP pin is open circuit, the outputs will operate at maximum duty cycle. The maximum duty cycle for each output can be calculated with Equation 3. 1 T - T1 2 S Maximum Duty Cycle = TS where * * TS is the period of one complete cycle for either the HO or LO outputs T1 is the programmed sync rectifier delay (3) For example, if the oscillator frequency is 200 kHz, each output will cycle at 100 kHz (TS = 10 s). Using no programmed delay, the maximum duty cycle at this frequency is calculated to be 50%. Using a programmed sync rectifier delay of 100 ns, the maximum duty cycle is reduced to 49%. Because there is no fixed dead time in the LM5035C, TI recommends that the delay pin resistor not be less than 10 K. Internal delays, which are not ensured, are the only protection against cross conduction if the programmed delay is zero, or very small. HO SR1 T1 T2 LO SR2 T1 T2 Figure 14. HO, LO, SR1, and SR2 Timing Diagram 8.3.12 Synchronous Rectifier Control Outputs (SR1 and SR2) Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low-output voltage converters. The reduction of rectifier forward voltage drop (0.5 V - 1.5 V) to 10 mV - 200 mV VDS voltage for a MOSFET significantly reduces rectification losses. In a typical application, the transformer secondary winding is center tapped, with the output power inductor in series with the center tap. The SR MOSFETs provide the ground path for the energized secondary winding and the inductor current. Figure 14 shows that the SR2 MOSFET is conducting while HO enables power transfer from the primary. The SR1 MOSFET must be disabled during this period since the secondary winding connected to the SR1 MOSFET drain is twice the voltage of the center tap. At the conclusion of the HO pulse, the inductor current continues to flow through the SR1 MOSFET body diode. Because the body diode causes more loss than the SR MOSFET, efficiency can be improved by minimizing the T2 period while maintaining sufficient timing margin over all conditions (component tolerances, and so forth) to prevent shoot-through current. When LO enables power transfer from the primary, the SR1 MOSFET is enabled and the SR2 MOSFET is off. During the time that neither HO nor LO is active, the inductor current is shared between both the SR1 and SR2 MOSFETs which effectively shorts the transformer secondary and cancels the inductance in the windings. The SR2 MOSFET is disabled before LO delivers power to the secondary to prevent power being shunted to ground. The SR2 MOSFET body diode continues to carry about half the inductor current until the primary power raises the SR2 MOSFET drain voltage and reverse biases the body diode. Ideally, dead-time T1 would be set to the minimum time that allows the SR MOSFET to turn off before the SR MOSFET body diode starts conducting. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 19 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com Feature Description (continued) The SR1 and SR2 outputs are powered directly by the 5-V reference regulator. Each output is capable of sourcing 0.09 A and sinking 0.2-A peak. The SR1 and SR2 signals can control SR MOSFET gate drivers through a digital isolator. The actual gate sourcing and sinking currents are provided by the secondary-side bias supply and gate drivers. The timing of SR1 and SR2 with respect to HO and LO is shown in Figure 14. SR1 is configured out of phase with HO and SR2 is configured out of phase with LO. The dead time between transitions is programmable by a resistor connected from the DLY pin to the AGND pin. Typically, RDLY is set in the range of 10 k to 100 k. The dead-time periods can be calculated using Equation 4 and Equation 5. T1 = 0.003 x RDLY + 4.6 ns T2 = 0.0007 x RDLY + 10.01 ns (4) (5) When UVLO falls below 1.25 V, or during hiccup current limit, both SR1 and SR2 are held low. During normal operation, if soft start is held low, both SR1 and SR2 will be high. 8.3.13 Thermal Protection Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum rated junction temperature is exceeded. When activated, typically at 165C, the controller is forced into a low-power standby state with the output drivers (HO, LO, SR1, and SR2), the bias regulators (VCC and REF) disabled. This helps to prevent catastrophic failures from accidental device overheating. During thermal shutdown, the soft-start capacitor is fully discharged and the controller follows a normal start-up sequence after the junction temperature falls to the operating level (145C). 8.4 Device Functional Modes The LM5035C can be used as a half-bridge PWM controller or as a push-pull PWM controller. To implement the LM5035C in a push-pull application, the HB pin is connected to VCC and the HS pin is connected to PGND. The LM5035C will deliver 180 out-of-phase ground-referenced PWM signals to the gates of the power MOSFETS. The high-side driver has an HS-to-GND maximum voltage rating of 105 V, but in higher-voltage applications the high-side MOSFET can be driven with a gate-drive transformer. 20 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The LM5035C is a high performance PWM controller integrated half-bridge and synchronous rectifier driver and is ideally suited for half-bridge topology power converters. The LM5035C architecture allows voltage mode control with line voltage feedforward. Cycle-by-cycle current limit protection can be implemented. The hiccup timer helps the system to stay within a safe operation range under overcurrent conditions. The LM5035C allows programming of dead time between the SR1 and SR2 signals and the HO and LO driver outputs, to allow optimal power stage design. The LM5035C also provides complete system level protection functions, including UVLO, OVP, overcurrent protection. 9.2 Typical Application The following schematic shows an example of a 100-W half-bridge power converter controlled by the LM5035C. The operating input voltage range (VPWR) is 36 V to 75 V, and the output voltage is 3.3 V. The output current capability is 30 A. Current sense transformer T2 provides information to the CS pin for current limit protection. The error amplifier and reference, U3 and U5 respectively, provide voltage feedback through opto-coupler U4. Synchronous rectifiers Q4, Q5, Q6, and Q7 minimize rectification losses in the secondary. An auxiliary winding on transformer T1 provides power to the LM5035C VCC pin when the output is in regulation. The input voltage UVLO thresholds are 34 V for increasing VPWR, and 32 V for decreasing VPWR. The circuit can be shut down by driving the ON/OFF input (J2) below 1.25 V with an open-collector or open-drain circuit. An external synchronizing frequency can be applied through a 100-pF capacitor to the RT input (U1 pin 5). The regulator output is current-limited at 34 A. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 21 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com Copyright (c) 2016, Texas Instruments Incorporated Figure 15. Evaluation Board Schematic 22 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 9.2.1 Design Requirements Table 1 lists the parameters for this example. Table 1. Design Parameters PARAMETER Input voltage (VIN) MIN Output voltage (VOUT) Output current (IOUT) NOM 36 MAX 72 3.3 0 400 Efficiency (full load) 89% Efficiency (half load) 92% Load regulation 0.2% Line regulation 0.1% V V 30 Oscillator frequency UNIT A kHz Undervoltage lockout (ON) 33.9 V Undervoltage lockout (OFF) 31.9 V Line overvoltage protection (ON) 79.4 V Line overvoltage protection (OFF) 78.3 V 9.2.2 Detailed Design Procedure The Device Comparison Table lists the differences between the LM5035, LM5035A, LM5035B, and LM5035C. 9.2.2.1 VIN The voltage applied to the VIN pin, which may be the same as the system voltage applied to the power transformer's primary (VPWR), can vary in the range of 13 to 105 V. The current into VIN depends primarily on the gate charge provided to the output drivers, the switching frequency, and any external loads on the VCC and REF pins. TI recommends using the filter shown in Figure 16 to suppress transients which may occur at the input supply. This is particularly important when VIN is operated close to the maximum operating rating of the LM5035C. When power is applied to VIN and the UVLO pin voltage is greater than 0.4 V, the VCC regulator is enabled and supplies current into an external capacitor connected to the VCC pin. When the voltage on the VCC pin reaches the regulation point of 7.6 V, the voltage reference (REF) is enabled. The reference regulation set point is 5 V. The HO, LO, SR1 and SR2 outputs are enabled when the two bias regulators reach their setpoint and the UVLO pin potential is greater than 1.25 V. In typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8.3 V to shut off the internal start-up regulator. After the outputs are enabled and the external VCC supply voltage has begun supplying power to the IC, the current into VIN drops below 1 mA. VIN should remain at a voltage equal to or above the VCC voltage to avoid reverse current through protection diodes. 9.2.2.2 For Applications >100 V For applications where the system input voltage exceeds 100 V or the IC power dissipation is of concern, the LM5035C can be powered from an external start-up regulator as shown in Figure 17. In this configuration, the VIN and the VCC pins should be connected together, which allows the LM5035C to be operated below 13 V. The voltage at the VCC pin must be greater than 8.3 V yet not exceed 15 V. An auxiliary winding can be used to reduce the power dissipation in the external regulator once the power converter is active. The NPN base-emitter reverse breakdown voltage, which can be as low as 5 V for some transistors, should be considered when selecting the transistor. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 23 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com 9.2.2.3 Current Sense The CS pin needs to receive an input signal representative of the transformer's primary current, either from a current sense transformer or from a resistor in series with the source of the LO switch, as shown in Figure 18 and Figure 19. In both cases, the sensed current creates a ramping voltage across R1, and the RF/CF filter suppresses noise and transients. R1, RF and CF should be located as close to the LM5035C as possible, and the ground connection from the current sense transformer, or R1, should be a dedicated track to the AGND pin. The current sense components must provide greater than 0.25 V at the CS pin when an overcurrent condition exists. VPWR 50 VIN LM5035C 0.1 F Copyright (c) 2016, Texas Instruments Incorporated Figure 16. Input Transient Protection VPWR VIN 8.3 V 15 V (from aux winding) VCC LM5035C 9V Copyright (c) 2016, Texas Instruments Incorporated Figure 17. Start-Up Regulator for VPWR >100 V VPWR Power Transformer Current Sense VIN Q1 RF CS CF R1 AGND HO Q2 LO LM5035C Copyright (c) 2016, Texas Instruments Incorporated Figure 18. Current Sense Using Current Sense Transformer 24 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 VPWR Power Transformer Q1 VIN HO Q2 LO RF CS CF R1 Current Sense AGND LM5035C Copyright (c) 2016, Texas Instruments Incorporated Figure 19. Current Sense Using Current Sense Resistor (R1) If the current sense resistor method is used, the overcurrent condition will only be sensed while LO is driving the low-side MOSFET. Overcurrent while HO is driving the high-side MOSFET will not be detected. In this configuration, it will take 4 times as long for continuous cycle-by-cycle current limiting to initiate a restart event since each over-current event during LO enables the 22-A RES pin current source for one oscillator period, and then the lack of an overcurrent event during HO enables the 12-A RES pin current sink for one oscillator period. The time average of this toggling is equivalent to a continuous 5-A current source into the RES capacitor, increasing the delay by a factor of four. The value of the RES capacitor can be reduced to decrease the time before restart cycle is initiated. When using the resistor current sense method, an imbalance in the input capacitor voltages may develop when operating in cycle-by-cycle current limiting mode. If the imbalance persists for an extended period, excessive currents in the non-sensed MOSFET, and possible transformer saturation may result. This condition is inherent to the half-bridge topology operated with cycle-by-cycle current limiting and is compounded by only sensing in one leg of the half-bridge circuit. The imbalance is greatest at large duty cycles (low input voltages). If using this method, TI recommends that the capacitor on the RES pin be no larger than 220 pF. Check the final circuit and reduce the RES capacitor further, or omit the capacitor completely to ensure the voltages across the bridge capacitors remain balanced. The current limit value may decrease slightly as the RES capacitor is reduced. 9.2.2.4 HO, HB, HS, and LO Attention must be given to the PC board layout for the low-side driver and the floating high-side driver pins HO, HB, and HS. A low ESR/ESL capacitor (such as a ceramic surface mount capacitor) should be connected close to the LM5035C, between HB and HS to provide high peak currents during turnon of the high-side MOSFET. The capacitor should be large enough to supply the MOSFET gate charge (Qg) without discharging to the point where the drop in gate voltage affects the MOSFET RDS(ON). TI recommends a value ten to twenty times Qg. CBOOST = 20 x Qg VCC (6) The diode (DBOOST) that charges CBOOST from VCC when the low-side MOSFET is conducting should be capable of withstanding the full converter input voltage range. When the high-side MOSFET is conducting, the reverse voltage at the diode is approximately the same as the MOSFET drain voltage because the high-side driver is boosted up to the converter input voltage by the HS pin, and the high-side MOSFET gate is driven to the HS voltage plus VCC. Because the anode of DBOOST is connected to VCC, the reverse potential across the diode is equal to the input voltage minus the VCC voltage. DBOOST average current is less than 20 mA in most applications, so TI recommends a low-current ultra-fast recovery diode to limit the loss due to diode junction capacitance. Schottky diodes are also a viable option, particularly for lower input voltage applications, but attention must be paid to leakage currents at high temperatures. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 25 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com The internal gate drivers need a very low impedance path to the respective decoupling capacitors; the VCC cap for the LO driver and CBOOST for the HO driver. These connections should be as short as possible to reduce inductance and as wide as possible to reduce resistance. The loop area, defined by the gate connection and its respective return path, should be minimized. The high-side gate driver can also be used with HS connected to PGND for applications other than a half bridge converter (for example, push-pull). The HB pin is then connected to VCC, or any supply greater than the highside driver undervoltage lockout (approximately 6.5 V). In addition, the high-side driver can be configured for high voltage offline applications where the high-side MOSFET gate is driven through a gate drive transformer. 9.2.2.5 Programmable Delay (DLY) The RDLY resistor programs the delays between the SR1 and SR2 signals and the HO and LO driver outputs. Figure 14 shows the relationship between these outputs. The DLY pin is nominally set at 2.5 V and the current is sensed through RDLY to ground. This current is used to adjust the amount of dead time before the HO and LO pulse (T1) and after the HO and LO pulse (T2). Typically RDLY is in the range of 10 k to 100 k. The dead-time periods can be calculated using Equation 7 and Equation 8. T1 = 0.003 x RDLY + 4.6 ns T2 = 0.0007 x RDLY + 10.01 ns (7) (8) This may cause lower than optimal system efficiency if the delays through the SR signal transformer network, the secondary gate drivers and the SR MOSFETs are greater than the delay to turn on the HO or LO MOSFETs. Should an SR MOSFET remain on while the opposing primary MOSFET is supplying power through the power transformer, the secondary winding will experience a momentary short circuit, causing a significant power loss to occur. When choosing the RDLY value, worst case propagation delays and component tolerances should be considered to assure that there is never a time where both SR MOSFETs are enabled AND one of the primary side MOSFETs is enabled. The time period T1 should be set so that the SR MOSFET has turned off before the primary MOSFET is enabled. Conversely, T1 and T2 should be kept as low as tolerances allow to optimize efficiency. The SR body diode conducts during the time between the SR MOSFET turns off and the power transformer begins supplying energy. Power losses increase when this happens since the body diode voltage drop is many times higher than the MOSFET channel voltage drop. The interval of body diode conduction can be observed with an oscilloscope as a negative 0.7-V to 1.5-V pulse at the SR MOSFET drain. 9.2.2.6 UVLO and OVP Voltage Divider Selection For R1, R2, and R3 Two dedicated comparators connected to the UVLO and OVP pins are used to detect undervoltage and overvoltage conditions. The threshold value of these comparators, VUVLO and VOVP, is 1.25 V (typical). The two functions can be programmed independently with two voltage dividers from VIN to AGND as shown in Figure 20 and Figure 21, or with a three-resistor divider as shown in Figure 22. Independent UVLO and OVP pins provide greater flexibility for the user to select the operational voltage range of the system. Hysteresis is accomplished by 23-A current sources (IUVLO and IOVP), which are switched ON or OFF into the sense pin resistor dividers as the comparators change state. When the UVLO pin voltage is below 0.4 V, the controller is in a low current shutdown mode. For a UVLO pin voltage greater than 0.4 V but less than 1.25 V the controller is in standby mode. Once the UVLO pin voltage is greater than 1.25 V, the controller is fully enabled. Two external resistors can be used to program the minimum operational voltage for the power converter as shown in Figure 20. When the UVLO pin voltage falls below the 1.25-V threshold, an internal 23-A current sink is enabled to lower the voltage at the UVLO pin, thus providing threshold hysteresis. Resistance values for R1 and R2 can be determined from Equation 9 and Equation 10. R1 = R2 = VHYS 23 PA (9) 1.25V x R1 VPWR 1.25V (23 PA x R1) where * * 26 VPWR is the desired turn-on voltage VHYS is the desired UVLO hysteresis at VPWR Submit Documentation Feedback (10) Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 For example, if the LM5035C is to be enabled when VPWR reaches 34 V, and disabled when VPWR is decreased to 32 V, R1 should be 87 k, and R2 should be 3.54 k. The voltage at the UVLO pin should not exceed 7 V at any time. Be sure to check both the power and voltage rating (0603 resistors can be rated as low as 50 V) for the selected R1 resistor. VPWR LM5035C R1 UVLO 1.25 V Disable Output Drivers 23 PA 0.4 V R2 Disable VCC and REF Regulators Copyright (c) 2016, Texas Instruments Incorporated Figure 20. Basic UVLO Configuration VPWR LM5035C 5V 23 PA R1 OVP STANDBY 1.25 V R2 Copyright (c) 2016, Texas Instruments Incorporated Figure 21. Basic Overvoltage Protection VPWR LM5035C R1 UVLO 1.25 V 23 A 0.4 V R2 Disable Output Drivers Disable VCC and REF Regulators 5V 23 A OVP 1.25 V STANDBY R3 Copyright (c) 2016, Texas Instruments Incorporated Figure 22. UVLO and OVP Divider Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 27 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com The impedance seen looking into the resistor divider from the UVLO and OVP pins determines the hysteresis level. UVLO and OVP enable and disable thresholds are calculated using the equations in the table below for the three-resistor divider illustrated in Figure 22. Table 2. UVO/OVP Divider Formulas FORMULA R1 + R2 + R 3 Outputs disabled due to VIN falling below UVLO threshold UVLOoff = 1.25V x Outputs enabled due to VIN rising above UVLO threshold UVLOon = UVLOoff + (23 A x R1) R1 OVPoff = 1.25V x Outputs disabled due to VIN rising above OVP threshold (c) Outputs enabled due to VIN falling below OVP threshold R2 + R3 + R2 + R 3 R3 (c) (c) (c) DESCRIPTION (11) (12) OVPon = OVPoff - [23 A x (R1 + R2)] The typical operating ranges of undervoltage and overvoltage thresholds are calculated from the above equations. For example, for resistor values R1 = 86.6 k, R2 = 2.10 k and R3 = 1.40 k the computed thresholds are: * UVLO turnoff = 32.2 V * UVLO turnon = 34.2 V * OVP turnon = 78.4 V * OVP turnoff = 80.5 V VPWR LM5035C R1 UVLO 1.25 V STANDBY 23 PA STANDBY OFF R2 0.4 V OFF Copyright (c) 2016, Texas Instruments Incorporated Figure 23. Remote Standby and Disable Control To maintain the threshold's accuracy, TI recommends a resistor tolerance of 1% or better. The design process starts with the choice of the voltage difference between the UVLO enabling and disabling thresholds. This will also approximately set the difference between OVP enabling and disabling regulation: UVLOon - UVLOoff R1 = 23 PA (13) Next, the combined resistance of R2 and R3 is calculated by choosing the threshold for the UVLO disabling threshold: RCOMBINED = 1.25V x R1 UVLOoff 1.25V (14) Then R3 is determined by selecting the OVP disabling threshold: 1.25V x (R1 + RCOMBINED) R3 = OVPoff (15) Finally, R3 is subtracted from RCOMBINED to give R2: R2 = RCOMBINED - R3 28 (16) Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 Remote configuration of the controller's operational modes can be accomplished with open drain device(s) connected to the UVLO pin as shown in Figure 23. 9.2.2.7 Fault Protection The Overvoltage Protection (OVP) comparator of the LM5035C can be configured for line or load fault protection or thermal protection using an external temperature sensor or thermistor. Figure 21 shows a line over voltage shutdown application using a voltage divider between the input power supply, VPWR, and AGND to monitor the line voltage. Figure 24 demonstrates the use of the OVP pin for latched output overvoltage fault protection, using a Zener and opto-coupler. When VOUT exceeds the conduction threshold of the opto-coupler diode and Zener, the optocoupler momentarily turns on Q1 and the LM5035C enters standby mode, disabling the drivers and enabling the hysteresis current source on the OVP pin. Once the current source is enabled, the OVP voltage will remain at 2.3V (23 A x 100 k) without additional drive from the external circuit. If the opto-coupler transistor emitter were directly connected to the OVP pin, then leakage current in the Zener diode amplified by the opto-coupler's gain could falsely trip the protection latch. R1 and Q1 are added reduce the sensitivity to low-level currents in the opto-coupler. Using the values of Figure 24, the opto-coupler collector current must equal VBE(Q1) / R1 = 350 A before OVP latches. Once the controller has switched to standby mode, the outputs no longer switch but the VCC and REF regulators continue functioning and supply bias to the external circuitry. VCC must fall below 6.2 V or the UVLO pin must fall below 0.4 V to clear the OVP latch. VREF R1 2k VOUT LM5035C 5V 23 A Q1 OVP R2 100k STANDBY 1.25 V Copyright (c) 2016, Texas Instruments Incorporated Figure 24. Latched Load Overvoltage Protection Figure 25 shows an application of the OVP comparator for Remote Thermal Protection using a thermistor (or multiple thermistors), which may be located near the main heat sources of the power supply. The negative temperature coefficient (NTC) thermistor is nearly logarithmic, and in this example a 100-k thermistor with the material constant of 4500 kelvins changes to approximately 2 k at 130C. Setting R1 to one-third of this resistance (665 ) establishes 130C as the desired trip point (for VREF = 5 V). In a temperature band from 20C below to 20C above the OVP threshold, the voltage divider is nearly linear with 25 mV perC sensitivity. R2 provides temperature hysteresis by raising the OVP comparator input by R2 x 23 A. For example, if a 22-k resistor is selected for R2, then the OVP pin voltage will increase by 22 k x 23 A = 506 mV. The NTC temperature must therefore fall by 506 mV / 25 mV perC = 20C before the LM5035C switches from the standby mode to the normal mode. VREF NTC THERMISTOR 23 PA T R2 R1 LM5035C 5V OVP 1.25 V STANDBY Copyright (c) 2016, Texas Instruments Incorporated Figure 25. Remote Thermal Protection Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 29 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com 9.2.2.8 Hiccup Mode Current Limit Restart (RES) The basic operation of the hiccup mode current limit restart is described in the functional description. The delay time to restart is programmed with the selection of the RES pin capacitor CRES as illustrated in Figure 25. In the case of continuous cycle-by-cycle current limit detection at the CS pin, the time required for CRES to reach the 2.5-V hiccup mode threshold is: t1 = CRES x 2.5V 22 PA = 114 k: x CRES (17) For example, if CRES = 0.01 F the time t1 is approximately 1.14 ms. The cool down time, t2 is set by the soft-start capacitor (CSS) and the internal 1-A SS current source, and is equal to Equation 18: t2 = CSS x 1V 1 PA = 1 M: x CSS (18) If CSS = 0.01 F t2 is 10 ms. The soft-start time t3 is set by the internal 110-A current source, and is equal to Equation 19. t3 = CSS x 4V = 40 k: x CSS 110 PA (19) If CSS = 0.01 F t3 is 363 s. The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or short circuit. This off time results in lower average input current and lower power dissipation within the power components. TI recommends that the ratio of t2 / (t1 + t3) be in the range of 5 to 10 to take advantage of this feature. If the application requires no delay from the first detection of a current limit condition to the onset of the hiccup mode (t1 = 0), the RES pin can be left open (no external capacitor). If it is desired to disable the hiccup mode entirely, the RES pin should be connected to ground (AGND). 2.5V Current Limit Detected at CS RES 0V 5V +110 PA #1V +1 PA SS LO HO t1 t2 t3 Figure 26. Hiccup Overload Restart Timing 30 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 9.2.3 Application Curves Conditions: Input Voltage = 48 VDC Output Current = 5 A Trace 1: Output Voltage Volts/div = 500 mV Horizontal Resolution = 0.5 ms/div Figure 27. Output Voltage During a Typical Start-Up Conditions: Input Voltage = 48 VDC Output Current = 30 A Bandwidth Limit = 20 MHz Trace 1: Output Ripple Voltage Volts/div = 20 mV Horizontal Resolution = 1 s/div Figure 29. Typical Output Ripple Seen Across the Output Terminals Conditions: Input Voltage = 48 VDC Output Current = 15 A to 22.5 A Upper Trace: Output Voltage Volts/div = 50 mV Lower Trace: Output Current = 15 A to 22.5 A to 15 A Horizontal Resolution = 0.5 ms/div Figure 28. Transient Response for a Load Change From 15 A to 22.5 A Conditions: Input Voltage = 36 VDC Output Current = 5 A Trace 1: Q1 drain voltage Volts/div = 10 V Horizontal Resolution = 1 s/div Figure 30. Drain Voltage of Q1 With a 5-A Load (Input Voltage of 36 V) Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 31 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com Conditions: Input Voltage = 72 VDC Output Current = 5 A Trace 1: Q2 drain voltage Volts/div = 10 V Horizontal Resolution = 1 s/div Figure 31. Drain Voltage of Q1 With a 5-A Load (Input Voltage of 72 V) 32 Conditions: Input Voltage = 48 VDC Output Current = 5 A Upper Trace: SR1, Q4 gate Volts/div = 5 V Middle Trace: HS, Q2 drain Volts/div = 20 V Lower Trace: SR2, Q6 gate Volts/div = 5 V Horizontal Resolution = 1 s/div Figure 32. Gate Voltages of the Synchronous Rectifiers Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 10 Power Supply Recommendations The LM5035C can be used to control power levels up to 500 W; therefore, the current levels can be considerable. Care must be taken in choosing components with the correct current rating which includes: magnetic components, power MOSFETS and diodes, connectors, and wire sizes. Input and output capacitors must have the correct ripple current rating. TI recommends using a multilayer PCB with a copper area chosen to ensure the LM5035C operates below the maximum junction temperature. Full power loading must never be attempted without providing for adequate cooling. 11 Layout 11.1 Layout Guidelines The LM5035C current sense and PWM comparators are very fast, and respond to short duration noise pulses. The components at the CS, COMP, SS, OVP, UVLO, DLY and the RT pins should be as physically close as possible to the IC, thereby minimizing noise pickup on the PC board tracks. Layout considerations are critical for the current sense filter. If a current sense transformer is used, both leads of the transformer secondary should be routed to the sense filter components and to the IC pins. The ground side of the transformer should be connected through a dedicated PC board track to the AGND pin, rather than through the ground plane. If the current sense circuit employs a sense resistor in the drive transistor source, low inductance resistors should be used. In this case, all the noise sensitive, low-current ground tracks should be connected in common near the IC, and then a single connection made to the power ground (sense resistor ground point). The gate drive outputs of the LM5035C should have short, direct paths to the power MOSFETs to minimize inductance in the PC board traces. The SR control outputs should also have minimum routing distance through the pulse transformers and through the secondary gate drivers to the sync FETs. The two ground pins (AGND, PGND) must be connected together with a short, direct connection, to avoid jitter due to relative ground bounce. If the internal dissipation of the LM5035C produces high junction temperatures during normal operation, the use of multiple vias under the IC to a ground plane can help conduct heat away from the IC. Judicious positioning of the PC board within the end product, along with use of any available air flow (forced or natural convection) will help reduce the junction temperatures. If using forced air cooling, avoid placing the LM5035C in the airflow shadow of tall components, such as input capacitors. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 33 LM5035C SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 www.ti.com 11.2 Layout Example VIN RAMP VIN UVLO REF OVP SR1 COMP SR2 RT AGND To Sense Resistor Positive VCC To sense resistor return PGND CS LO SS HO DLY HS RES HB To Low side MOSFET Gate To High side MOSFET Gate Figure 33. LM5035C Layout Example 34 Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C LM5035C www.ti.com SNVS631D - JANUARY 2010 - REVISED OCTOBER 2016 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: AN-2043 LM5035C Evaluation Board (SNVA433) 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Community Resource The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2010-2016, Texas Instruments Incorporated Product Folder Links: LM5035C 35 PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM5035CMH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5035 CMH LM5035CMHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LM5035 CMH LM5035CSQ/NOPB ACTIVE WQFN NHZ 24 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5035CSQ LM5035CSQX/NOPB ACTIVE WQFN NHZ 24 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 5035CSQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 23-Mar-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) LM5035CMHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 LM5035CSQ/NOPB WQFN NHZ 24 1000 178.0 LM5035CSQX/NOPB WQFN NHZ 24 4500 330.0 6.95 7.1 1.6 8.0 16.0 Q1 12.4 4.3 5.3 1.3 8.0 12.0 Q1 12.4 4.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 23-Mar-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5035CMHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0 LM5035CSQ/NOPB WQFN NHZ 24 1000 210.0 185.0 35.0 LM5035CSQX/NOPB WQFN NHZ 24 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NHZ0024B SQA24B (Rev A) www.ti.com MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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