TPIC0298
DUAL FULL-H DRIVER
SLIS006 – D2942, JUNE 1987 – REVISED JANUARY 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1990, Texas Instruments Incorporated
2–3
•Formerly TLP298
•2-A Output Current Capability Per Full-H
Driver
•Applications Include Half-H and Full-H
Solenoid Drivers and Motor Drivers
•Wide Range of Output Supply Voltage
5 V to 46 V
•Separate Input-Logic Supply Voltage
Thermal Shutdown
•Internal Electrostatic Discharge Protection
•High Noise Immunity
•3-State Outputs
•Minimized Power Dissipation
•Sink/Source Interlock Circuitry Prevents
Simultaneous Conduction
•Improved Functional Replacement for the
SGS L298
description
The TPIC0298 is a dual high-current full-H driver
designed to provide bidirectional drive currents of
up to 2 A at voltages from 5 V to 46 V . It is designed
to drive inductive loads such as relays, solenoids,
dc motors, stepping motors, and other high-
current or high-voltage loads in positive-supply
applications. All inputs are TTL compatible. Each
output (Y) is a complete totem-pole drive with a
Darlington transistor sink and a pseudo-
Darlington source. Each full-H driver is enabled
separately. Outputs 1Y1 and 1Y2 are enabled by
1EN and outputs 2Y1 and 2Y2 are enabled by
2EN. When an EN input is high, the associated
channels are active. When an EN input is low , the
associated channels are off (i.e., in the high-
impedance state).
Each half of the device forms a full-H reversible
driver suitable for solenoid or motor applications.
The current in each full-H driver can be monitored
by connecting a resistor between the sense output
terminal 1E and GND and another resistor
between sense output terminal 2E and GND.
External high-speed output-clamp diodes should be used for inductive transient suppression. To minimize
device power dissipation, a VCC1 supply voltage, separate from VCC2, is provided for the logic inputs.
The TPIC0298 is designed for operation from 0°C to 70°C.
logic symbol†
†This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
1A1
1EN
1A2
2A1
2EN
2A2
5
6
7
10
11
12
2
1
3
13
15
14
1Y1
1E
1Y2
2Y1
2E
2Y2
EN
EN
EN
EN
X
X
KV PACKAGE
(TOP VIEW)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2E
2Y2
2Y1
2A2
2EN
2A1
VCC1
GND
1A2
1EN
1A1
VCC2
1Y2
1Y1
1E
The tab is electrically connected to GND.
INPUTS OUTPUT
Y
FUNCTION TABLE
AEN
H
L
X
H
H
L
H
L
Z
H = high-level , L = low-level
X = irrelevant
Z = high-impedance (off)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TPIC0298
DUAL FULL-H DRIVER
SLIS006 – D2942, JUNE 1987 – REVISED JANUARY 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–4
logic diagram (positive logic)
VCC1
1A1
1A2
1EN
1E
1Y1 1Y2 VCC2 2Y1 2Y2
GND 2E
2A2
2A1
2EN
9
5
7
6
2341314
1815
12
10
11
absolute maximum ratings over operating temperature range (unless otherwise noted)
Logic supply voltage range, VCC1 (see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output supply voltage range, VCC2 –0.3 V to 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range at A or EN, VI (see Note 2) –1.6 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO –2 V to VCC2 + 2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Emitter terminal (1E and 2E) voltage range, VE –0.5 V to 2.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Emitter terminal (1E and 2E) voltage (nonrepetitive, tw ≤ 50 µs) –1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current at A or EN, II –15 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current, IOM: (nonrepetitive, tw ≤ 0.1 ms) ±3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(repetitive, tw ≤ 10 ms, duty cycle ≤ 80%) ±2.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak combined output current for each full-H driver (see Note 3):
(nonrepetitive, tw ≤ 0.1 ms) ±3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(repetitive, tw ≤ 10 ms, duty cycle ≤ 80%) ±2.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous combined output current for each full-H driver (see Note 3) ±2 A. . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous dissipation at (or below) 25°C free-air temperature (see Note 4) 3.575 W. . . . . . . . . . . . . . . . . . .
Continuous dissipation at (or below) 75°C case temperature (see Note 4) 25 W. . . . . . . . . . . . . . . . . . . . . . .
Operating free-air, case, or virtual junction temperature range –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTES: 1. All voltage values are with respect to the network GND, unless otherwise noted.
2. The maximum current limitation at this terminal generally occurs at a voltage of lower magnitude than the voltage limit. Neither the
maximum current nor the maximum voltage for this terminal should be exceeded.
3. Combined output current applies to each of the two full-H drivers individually. This current is the sum of the currents at outputs 1Y1
and 1Y2 for full-H driver 1 and the sum of the currents at outputs 2Y1 and 2Y2 for full-H driver 2. The full-H drivers can carry the rated
combined current simultaneously.
4. For operation above 25°C free-air temperature, derate linearly at the rate of 28.6 mW/°C. For operation above 75°C case temperature,
derate linearly at the rate of 333 mW/°C. Due to variations in individual device electrical characteristics and thermal resistance, the
built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation.
TPIC0298
DUAL FULL-H DRIVER
SLIS006 – D2942, JUNE 1987 – REVISED JANUARY 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5
recommended operating conditions
MIN MAX UNIT
Logic supply voltage, VCC1 4.5 7 V
Output supply voltage, VCC2 546 V
–0.5†2
Emitter terminal (1E or 2E) voltage, VE (see Note 5) VCC1–3.5 V
VCC2–4
A
2.3 VCC1
High level in
p
ut voltage VIH (see Note 5)
A
VCC2–2.5
V
High
-
le
v
el
inp
u
t
v
oltage
,
V
IH
(see
Note
5)
EN
2.3 7
V
EN
VCC1
Low-level input voltage at A or EN, VIL –0.3†1.5 V
Output current, IO±2 A
Communication frequency 40 kHz
Operating free-air temperature, TA0 70 °C
†The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for emitter terminal
voltage and logic voltage levels.
NOTE 5: For optimum device performance, the maximum recommended voltage at any A input is 2.5 V lower than VCC2, the maximum
recommended voltage at any EN input is VCC1, and the maximum recommended voltage at any emitter terminal is 3.5 V lower than
VCC1 and 4 V lower than VCC2.
electrical characteristics over recommended ranges of VCC1, VCC2, and VE, TJ = 25°C (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage II = –12 mA –0.9 –1.5 V
VOH
High level out
p
ut voltage
IOH = –1 A VCC2–1.8 VCC2–1.2
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
IOH = –2 A VCC2–2.8 VCC2–1.8
V
VOL
Low level out
p
ut voltage
IOL = 1 A VE+1.2 VE+1.8
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
IOL = 2 A VE+1.7 VE+2.6
V
Vd
Total source pulse sink output IOH = –1 A, IOL = 1 A
See Note 6
2.4 3.4
V
V
drop voltage drop IOH = –2 A, IOL = 2 A
See
Note
6
3.5 5.2
V
Off-state (high-impedance state)
IOZH
(g )
output current, high-level VO = VCC2 500 µA
OZH
voltage applied
O CC2
µ
Off-state (high-impedance state)
IOZL
(g )
output current, low-level VO = 0 V, VE = 0 V –500 µA
OZL
voltage applied
O
E
µ
VI=V
IH
EN = H 20 100
IIH High-level input current
V
I =
V
IH EN = L 10 µA
EN VI = VIH ≤ VCC1 – 0.6 V 6 100
IIL Low-level input current VI = 0 V to 1.5 V –10 µA
All outputs at high level 7 12
ICC1 Logic supply current IO = 0 All outputs at low level 20 32 mA
All outputs at high impedance 4 6
All outputs at high level 25 50
ICC2 Output supply current IO = 0 All outputs at low level 6 20 mA
All outputs at high impedance 2
†All typical values are at VCC1 = 5 V, VCC2 = 42 V, VE = 0 V, TJ = 25°C (unless otherwise noted).
NOTE 6: The Vdrop specification applies for IOH and IOL applied simultaneously to dif ferent output channels:
Vdrop = VCC2 – VOH + VOL – VE
TPIC0298
DUAL FULL-H DRIVER
SLIS006 – D2942, JUNE 1987 – REVISED JANUARY 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–6
switching characteristics, VCC1 = 5 V, VCC2 = 42 V, VE = 0, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(on) T urn-on delay time, source current from A input 0.6 µs
td(off) Turn-off delay time, source current from A input 0.8 µs
trRise time, source current (turning on)
CL=30
p
F See Figure 1
0.8 µs
tfFall time, source current (turning off)
C
L =
30
pF
,
See
Fig
u
re
1
0.2 µs
td(on) T urn-on delay time, source current from EN input 0.5 µs
td(off) Turn-off delay time, source current from EN input 2.5 µs
td(on) T urn-on delay time, sink current from A input 1.3 µs
td(off) Turn-off delay time sink current from A input 0.5 µs
trRise time, sink current (turning on)
CL=30
p
F See Figure 2
0.2 µs
tfFall time, sink current (turning off)
C
L =
30
pF
,
See
Fig
u
re
2
0.2 µs
td(on) T urn-on delay time, sink current from EN input 0.3 µs
td(off) Turn-off delay time, sink current from EN input 1 µs
TPIC0298
DUAL FULL-H DRIVER
SLIS006 – D2942, JUNE 1987 – REVISED JANUARY 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–7
PARAMETER MEASUREMENT INFORMATION
10%
–IOH
Pulse
Generator
(see Note A)
VCC1 VCC2
GND E
Y
Circuit
Under
Test
4 V
(see Note B)
A/EN
Input
CL = 30 pF
(see Note C) RL = 20 Ω
Output
5 V 42 V
TEST CIRCUIT
90% 90%
10% 10%
2 V 2 V
4 V
0 V
≤ 10 ns ≤ 10 ns
20 µs
10% 10%
90%90%
90% 90%
10%
trtf
td(off)
td(on)
Input Voltage
(see Note B)
Output Current
Output Voltage
VOLTAGE AND CURRENT WAVEFORMS
(see Note B)
IOL ≈ 0 A
IOH ≈ –2 A
VOH ≈ 40 A
VOL ≈ 0 V
EN/A
NOTES: A. The pulse generator has the following characteristics: PRR = 2 kHz, ZO = 50 Ω.
B. EN is at 4 V if A is used as the switching input. A is at 4 V if EN is the switching input.
C. CL includes probe and jig capacitance.
Figure 1. Source Current Test Circuit and Waveforms From Data and Enable Inputs
TPIC0298
DUAL FULL-H DRIVER
SLIS006 – D2942, JUNE 1987 – REVISED JANUARY 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–8
PARAMETER MEASUREMENT INFORMATION
2 V
10%
IOL
Pulse
Generator
(see Note A) VCC1 VCC2
GND E
Y
Circuit
Under
Test
(see Note B)
A/EN
Input
CL = 30 pF
(see Note C)
RL = 20 Ω
Output
5 V 42 V
TEST CIRCUIT
90% 90%
10% 10%
2 V 2 V
4 V
0 V
≤ 10 ns ≤ 10 ns
20 µs
10% 10%
90%90%
90% 90%
10%
trtf
td(off)
td(on)
EN
(see Note B)
Output Current
Output Voltage
VOLTAGE AND CURRENT WAVEFORMS
EN/A
4 V(EN)
0 V(A)
90% 90%
2 V
10% 10%
≤ 10 ns ≤ 10 ns
A
(see Note B)
IOL ≈ 2 A
VOL ≈ 2 V
IOH ≈ 0 A
VOH ≈ 42 V
4 V
0 V
NOTES: A. The pulse generator has the following characteristics: PRR = 2 kHz, ZO = 50 Ω.
B. EN is at 4 V if A is used as the switching input. A is at 0 V if EN is the switching input.
C. CL includes probe and jig capacitance.
Figure 2. Sink Current Test Circuit and Voltage Waveforms From Data and Enable Inputs
TPIC0298
DUAL FULL-H DRIVER
SLIS006 – D2942, JUNE 1987 – REVISED JANUARY 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–9
APPLICATION INFORMATION
This circuit shows one half of a TPIC0298 used to provide full-H bridge drive for a 24-V, 2-A dc motor . Speed control
is achieved with a TLC555 timer. This provides variable duty-cycle pulses to the EN input of the TPIC0298. In this
configuration, the operating frequency is approximately 1.2 kHz. The duty cycle is adjustable from 10% to 90% to
provide a wide range of motor speeds. The motor direction is determined by the logic level at the direction control
input. The circuit can be enabled or disabled by the logic level at the EN input. A 5-V supply for the logic and timer
circuit is provided by a TL431 shunt regulator. For circuit operation, refer to the function table.
FUNCTION TABLE
ENABLE
DIRECTION
1Y1
1Y2
ENABLE
CONTROL
1Y1
1Y2
H H Source Sink
H L Sink Source
L X Disabled Disabled
X = don’t care H = high level L = low level
OUT
Direction
Control
Enable
2.7 kΩ
2.7 kΩ
2.7 kΩ
VCC1 1E GND
1A1
1Y1 1Y2
1/2
TPIC0298
VCC2
1A2
24-V Reversible
DC Motor
GND CONT
TLC555
TRIG
THR
DISC
RESET VDD
1N914
1 kΩ
1N914
0.1 µF
10 kΩ
1 kΩ
Speed
Control +
10 µFTL431
1.2 kΩ
24 V
††
††
SN7401
0.01 µF
1EN
820 Ω
2.7
kΩ
2.7
kΩ
†Diodes are 1N4934 or equivalent.
Figure 3. TPIC0298 as Bidirectional-DC Motor Drive
TPIC0298
DUAL FULL-H DRIVER
SLIS006 – D2942, JUNE 1987 – REVISED JANUARY 1990
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–10
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