To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclose d by Renesa s Electronics such as that disclosed through our website.
2. Renesas Electronics does not assum e any liability for inf ringement of patents, co pyrights, or other int ellectual property rights
of third parties by or arising from the use of Renesas Elec tronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
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3. You should not alter, m odify, copy, or otherw ise misappropriate an y Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsi bility for any losse s incurred by
you or third parties arising from the use of these circuits, software, or information.
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does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
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indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
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written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any applic ation for
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consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
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“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the m aximum rating , opera ting supply voltag e range, movement power voltage ra nge, heat radiation
characteristics, installation and other product characteristic s. Re nesas Electronics shall have no liabil ity for malfunctions or
damages arising out of the use of Re nesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliabili ty of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation res istance design. Pleas e be sure to implement saf ety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
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Directive. Renesas Electronics assum es no liability for damage s or losses occurring as a result of your noncom pliance with
applicable laws and regulatio ns.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions re garding the information conta ined in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Re nesas Electronics produc t(s)” means any product develope d or manufactured by or for Re nesas Electronics.
H8/38524 Group
Hardware Manual
16
User’s Manual
Rev.1.00 2007.12
Renesas 16-Bit Single-Chip
Microcomputer
H8 Family / H8/300H Super Low
Power Series
H8/38524
H8/38523
H8/38522
H8/38521
H8/38520
Rev. 1.00 Dec. 19, 2007 Page ii of xx
Rev. 1.00 Dec. 19, 2007 Page iii of xx
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Notes regarding these materials
Rev. 1.00 Dec. 19, 2007 Page iv of xx
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number, confirm
that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different type numbers, implement a system-evaluation test for
each of the products.
Rev. 1.00 Dec. 19, 2007 Page v of xx
How to Use This Manual
1. Objective and Target Users
This manual was written to explain the hardware functions and electrical characteristics of this
LSI to the target users, i.e. those who will be using this LSI in the design of application
systems. Target users are expected to understand the fundamentals of electrical circuits, logic
circuits, and microcomputers.
This manual is organized in the following items: an overview of the product, descriptions of
the CPU, system control functions, and peripheral functions, electrical characteristics of the
device, and usage notes.
When designing an application system that includes this LSI, take all points to note into
account. Points to note are given in their contexts and at the final part of each section, and
in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions.
It does not cover all revised items. For details on the revised points, see the actual locations
in the manual.
The following documents have been prepared for the H8/38524 Group. Before using any of the
documents, please visit our web site to verify that you have the most up-to-date available
version of the document.
Document Type Contents Document Title Document No.
Data Sheet Overview of hardware and electrical
characteristics
Hardware Manual Hardware specifications (pin
assignments, memory maps,
peripheral specifications, electrical
characteristics, and timing charts)
and descriptions of operation
H8/38524 Group
Hardware Manual
This manual
Software Manual Detailed descriptions of the CPU
and instruction set
H8/300H Series Software
Manual
REJ09B0213
Application Note Examples of applications and
sample programs
Renesas Technical
Update
Preliminary report on the
specifications of a product,
document, etc.
The latest versions are available from our
web site.
Rev. 1.00 Dec. 19, 2007 Page vi of xx
2. Description of Numbers and Symbols
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
(1) Overall notation
(2) Register notation
Rev. 0.50, 10/04, page 416 of 914
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
14.3.1 Interval Count Operation
(4)
(3)
(2)
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary: B'11 or 11
Hexadecimal: H'EFA0 or 0xEFA0
Decimal: 1234
(3) Number notation
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
Note: The bit names and sentences in the above figure are examples and have nothing to do
with the contents of this manual.
(4) Notation for active-low
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Rev. 1.00 Dec. 19, 2007 Page vii of xx
3. Description of Registers
Each register description includes a bit chart, illustrating the arrangement of bits, and a table of
bits, describing the meanings of the bit settings. The standard format and notation for bit charts
and tables are described below.
Indicates the bit number or numbers.
In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case
of a 16-bit register, the bits are arranged in order from 15 to 0.
Indicates the name of the bit or bit field.
When the number of bits has to be clearly indicated in the field, appropriate notation is
included (e.g., ASID[3:0]).
A reserved bit is indicated by "−".
Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such
cases, the entry under Bit Name is blank.
(1) Bit
(2) Bit name
Indicates the value of each bit immediately after a power-on reset, i.e., the initial value.
0: The initial value is 0
1: The initial value is 1
−: The initial value is undefined
(3) Initial value
For each bit and bit field, this entry indicates whether the bit or field is readable or writable,
or both writing to and reading from the bit or field are impossible.
The notation is as follows:
R/W:
R/(W):
R:
W:
The bit or field is readable and writable.
The bit or field is readable and writable.
However, writing is only performed to flag clearing.
The bit or field is readable.
"R" is indicated for all reserved bits. When writing to the register, write
the value under Initial Value in the bit chart to reserved bits or fields.
The bit or field is writable.
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this
manual.
(4) R/W
Describes the function of the bit or field and specifies the values for writing.
(5) Description
Bit
15
13 to 11
10
9
0
All 0
0
0
1
R
R/W
R
R
Address Identifier
These bits enable or disable the pin function.
Reserved
This bit is always read as 0.
Reserved
This bit is always read as 1.
−
ASID2 to
ASID0
−
−
−
Bit Name Initial Value R/W Description
[Table of Bits]
14 −0R
(1) (2) (3) (4) (5)
Reserved
These bits are always read as 0.
Rev. 1.00 Dec. 19, 2007 Page viii of xx
4. Description of Abbreviations
The abbreviations used in this manual are listed below.
• Abbreviations used in this manual
Abbreviation Description
ACIA Asynchronous communication interface adapter
bps Bits per second
CRC Cyclic redundancy check
DMA Direct memory access
DMAC Direct memory access controller
GSM Global System for Mobile Communications
Hi-Z High impedance
IEBus Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.)
I/O Input/output
IrDA Infrared Data Association
LSB Least significant bit
MSB Most significant bit
NC No connection
PLL Phase-locked loop
PWM Pulse width modulation
SFR Special function register
SIM Subscriber Identity Module
UART Universal asynchronous receiver/transmitter
VCO Voltage-controlled oscillator
Rev. 1.00 Dec. 19, 2007 Page ix of xx
5. List of Product Specifications
Below is a table listing the product specifications for each group.
H8/38524 Group
Item Flash Memory Mask ROM
ROM 16 K, 32 Kbytes 8 K, 12 K, 16 K, 24 K, 32 KbytesMemory
RAM 1 Kbyte 512 bytes, 1 Kbyte
4.5 to 5.5 V 20 MHz 20 MHz
2.7 to 5.5 V 20 MHz 20 MHz
1.8 to 5.5 V — —
2.7 to 3.6 V — —
Operating
voltage
and
operating
frequency
1.8 to 3.6 V — —
Input 9 9
Output 6 6
I/O ports
I/O 50 50
Clock (timer A) 1 1
Reload (timer C) 1 1
Compare (timer F) 1 1
Capture (timer G) 1 1
AEC 1 1
WDT — —
Timers
WDT (discrete) 1 1
SCI UART/Synchronous 1 ch 1 ch
A-D
(resolution × input channels) 10 bit × 8 ch 10 bit × 8 ch
seg 32 32 LCD
com 4 4
External interrupt
(internal wakeup)
13(8) 13(8)
POR (power-on reset) 1 1
LVD
(low-voltage detection circuit)
1 1
FP-80A FP-80A Package
TFP-80C TFP-80C
Operating temperature Standard specifications: –20 to 75°C, WTR: –40 to 85°C
All trademarks and registered trademarks are the property of their respective owners.
Rev. 1.00 Dec. 19, 2007 Page x of xx
Contents
Section 1 Overview ...............................................................................................1
1.1 Features................................................................................................................................. 1
1.1.1 Application ........................................................................................................... 1
1.1.2 Overview of Specifications................................................................................... 2
1.2 List of Products..................................................................................................................... 6
1.3 Block Diagram...................................................................................................................... 8
1.4 Pin Assignment..................................................................................................................... 9
1.5 Pin Functions ...................................................................................................................... 10
Section 2 CPU .....................................................................................................15
2.1 Address Space and Memory Map....................................................................................... 17
2.2 Register Configuration........................................................................................................ 22
2.2.1 General Registers................................................................................................ 23
2.2.2 Program Counter (PC) ........................................................................................ 24
2.2.3 Condition-Code Register (CCR)......................................................................... 24
2.3 Data Formats....................................................................................................................... 26
2.3.1 General Register Data Formats........................................................................... 26
2.3.2 Memory Data Formats ........................................................................................ 28
2.4 Instruction Set..................................................................................................................... 29
2.4.1 Table of Instructions Classified by Function ...................................................... 29
2.4.2 Basic Instruction Formats ................................................................................... 39
2.5 Addressing Modes and Effective Address Calculation....................................................... 40
2.5.1 Addressing Modes .............................................................................................. 40
2.5.2 Effective Address Calculation ............................................................................ 44
2.6 Basic Bus Cycle.................................................................................................................. 46
2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................ 46
2.6.2 On-Chip Peripheral Modules .............................................................................. 47
2.7 CPU States.......................................................................................................................... 48
2.8 Usage Notes........................................................................................................................ 49
2.8.1 Notes on Data Access to Empty Areas ............................................................... 49
2.8.2 EEPMOV Instruction.......................................................................................... 49
2.8.3 Bit-Manipulation Instruction .............................................................................. 50
Section 3 Exception Handling .............................................................................55
3.1 Overview ............................................................................................................................ 55
3.2 Reset ................................................................................................................................... 55
Rev. 1.00 Dec. 19, 2007 Page xi of xx
3.2.1 Overview............................................................................................................. 55
3.2.2 Reset Sequence ................................................................................................... 55
3.2.3 Interrupt Immediately after Reset ....................................................................... 57
3.3 Interrupts............................................................................................................................. 57
3.3.1 Overview............................................................................................................. 57
3.3.2 Interrupt Control Registers ................................................................................. 59
3.3.3 External Interrupts .............................................................................................. 71
3.3.4 Internal Interrupts ............................................................................................... 72
3.3.5 Interrupt Operations............................................................................................ 73
3.3.6 Interrupt Response Time..................................................................................... 78
3.4 Application Notes ............................................................................................................... 79
3.4.1 Notes on Stack Area Use .................................................................................... 79
3.4.2 Notes on Rewriting Port Mode Registers ........................................................... 80
3.4.3 Method for Clearing Interrupt Request Flags ..................................................... 83
Section 4 Clock Pulse Generators........................................................................85
4.1 Overview ............................................................................................................................ 85
4.1.1 Block Diagram.................................................................................................... 85
4.1.2 System Clock and Subclock................................................................................ 86
4.1.3 Register Descriptions.......................................................................................... 86
4.2 System Clock Generator ..................................................................................................... 88
4.3 Subclock Generator ............................................................................................................ 92
4.4 Prescalers ............................................................................................................................ 94
4.5 Note on Oscillators ............................................................................................................. 95
4.5.1 Definition of Oscillation Stabilization Wait Time .............................................. 96
4.5.2 Notes on Use of Crystal Oscillator Element
(Excluding Ceramic Oscillator Element) ............................................................ 99
4.6 Usage Note.......................................................................................................................... 99
Section 5 Power-Down Modes ..........................................................................101
5.1 Overview .......................................................................................................................... 101
5.1.1 System Control Registers.................................................................................. 104
5.2 Sleep Mode ....................................................................................................................... 108
5.2.1 Transition to Sleep Mode.................................................................................. 108
5.2.2 Clearing Sleep Mode ........................................................................................ 109
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode........................................... 109
5.3 Standby Mode................................................................................................................... 110
5.3.1 Transition to Standby Mode.............................................................................. 110
5.3.2 Clearing Standby Mode .................................................................................... 110
5.3.3 Oscillator Stabilization Time after Standby Mode is Cleared........................... 111
Rev. 1.00 Dec. 19, 2007 Page xii of xx
5.3.4 Standby Mode Transition and Pin States .......................................................... 112
5.3.5 Notes on External Input Signal Changes before/after Standby Mode............... 113
5.4 Watch Mode...................................................................................................................... 114
5.4.1 Transition to Watch Mode ................................................................................ 114
5.4.2 Clearing Watch Mode....................................................................................... 115
5.4.3 Oscillator Stabilization Time after Watch Mode is Cleared ............................. 115
5.4.4 Notes on External Input Signal Changes before/after Watch Mode ................. 115
5.5 Subsleep Mode.................................................................................................................. 116
5.5.1 Transition to Subsleep Mode ............................................................................ 116
5.5.2 Clearing Subsleep Mode................................................................................... 116
5.6 Subactive Mode ................................................................................................................ 117
5.6.1 Transition to Subactive Mode........................................................................... 117
5.6.2 Clearing Subactive Mode.................................................................................. 117
5.6.3 Operating Frequency in Subactive Mode.......................................................... 117
5.7 Active (Medium-Speed) Mode ......................................................................................... 118
5.7.1 Transition to Active (Medium-Speed) Mode.................................................... 118
5.7.2 Clearing Active (Medium-Speed) Mode........................................................... 118
5.7.3 Operating Frequency in Active (Medium-Speed) Mode................................... 118
5.8 Direct Transfer.................................................................................................................. 119
5.8.1 Overview of Direct Transfer............................................................................. 119
5.8.2 Direct Transition Times .................................................................................... 120
5.8.3 Notes on External Input Signal Changes before/after Direct Transition........... 122
5.9 Module Standby Mode...................................................................................................... 123
5.9.1 Setting Module Standby Mode ......................................................................... 123
5.9.2 Clearing Module Standby Mode....................................................................... 123
Section 6 ROM .................................................................................................. 125
6.1 Overview .......................................................................................................................... 125
6.2 Flash Memory Overview .................................................................................................. 126
6.2.1 Features............................................................................................................. 126
6.2.2 Block Diagram.................................................................................................. 127
6.2.3 Block Configuration ......................................................................................... 128
6.2.4 Register Configuration...................................................................................... 130
6.3 Descriptions of Registers of the Flash Memory................................................................ 130
6.3.1 Flash Memory Control Register 1 (FLMCR1).................................................. 130
6.3.2 Flash Memory Control Register 2 (FLMCR2).................................................. 133
6.3.3 Erase Block Register (EBR) ............................................................................. 134
6.3.4 Flash Memory Power Control Register (FLPWCR)......................................... 134
6.3.5 Flash Memory Enable Register (FENR)........................................................... 135
Rev. 1.00 Dec. 19, 2007 Page xiii of xx
6.4 On-Board Programming Modes........................................................................................ 136
6.4.1 Boot Mode ........................................................................................................ 136
6.4.2 Programming/Erasing in User Program Mode.................................................. 139
6.4.3 Notes on On-Board Programming .................................................................... 140
6.5 Flash Memory Programming/Erasing............................................................................... 140
6.5.1 Program/Program-Verify .................................................................................. 141
6.5.2 Erase/Erase-Verify............................................................................................ 144
6.5.3 Interrupt Handling when Programming/Erasing Flash Memory....................... 144
6.6 Program/Erase Protection ................................................................................................. 146
6.6.1 Hardware Protection ......................................................................................... 146
6.6.2 Software Protection........................................................................................... 146
6.6.3 Error Protection ................................................................................................ 147
6.7 Programmer Mode............................................................................................................ 147
6.7.1 Socket Adapter.................................................................................................. 147
6.7.2 Programmer Mode Commands......................................................................... 148
6.7.3 Memory Read Mode ......................................................................................... 150
6.7.4 Auto-Program Mode ......................................................................................... 153
6.7.5 Auto-Erase Mode.............................................................................................. 155
6.7.6 Status Read Mode ............................................................................................. 156
6.7.7 Status Polling .................................................................................................... 158
6.7.8 Programmer Mode Transition Time ................................................................. 159
6.7.9 Notes on Memory Programming ...................................................................... 159
6.8 Power-Down States for Flash Memory............................................................................. 160
Section 7 RAM ..................................................................................................161
7.1 Overview .......................................................................................................................... 161
7.1.1 Block Diagram.................................................................................................. 161
Section 8 I/O Ports.............................................................................................163
8.1 Overview .......................................................................................................................... 163
8.2 Port 1................................................................................................................................. 165
8.2.1 Overview........................................................................................................... 165
8.2.2 Register Configuration and Description ........................................................... 165
8.2.3 Pin Functions .................................................................................................... 170
8.2.4 Pin States .......................................................................................................... 171
8.2.5 MOS Input Pull-Up........................................................................................... 171
8.3 Port 3................................................................................................................................. 172
8.3.1 Overview........................................................................................................... 172
8.3.2 Register Configuration and Description ........................................................... 172
8.3.3 Pin Functions .................................................................................................... 177
Rev. 1.00 Dec. 19, 2007 Page xiv of xx
8.3.4 Pin States .......................................................................................................... 178
8.3.5 MOS Input Pull-Up........................................................................................... 178
8.4 Port 4................................................................................................................................. 179
8.4.1 Overview........................................................................................................... 179
8.4.2 Register Configuration and Description ........................................................... 179
8.4.3 Pin Functions .................................................................................................... 182
8.4.4 Pin States .......................................................................................................... 183
8.5 Port 5................................................................................................................................. 183
8.5.1 Overview........................................................................................................... 183
8.5.2 Register Configuration and Description ........................................................... 184
8.5.3 Pin Functions .................................................................................................... 186
8.5.4 Pin States .......................................................................................................... 187
8.5.5 MOS Input Pull-Up........................................................................................... 187
8.6 Port 6................................................................................................................................. 188
8.6.1 Overview........................................................................................................... 188
8.6.2 Register Configuration and Description ........................................................... 188
8.6.3 Pin Functions .................................................................................................... 190
8.6.4 Pin States .......................................................................................................... 191
8.6.5 MOS Input Pull-Up........................................................................................... 191
8.7 Port 7................................................................................................................................. 192
8.7.1 Overview........................................................................................................... 192
8.7.2 Register Configuration and Description ........................................................... 192
8.7.3 Pin Functions .................................................................................................... 194
8.7.4 Pin States .......................................................................................................... 194
8.8 Port 8................................................................................................................................. 195
8.8.1 Overview........................................................................................................... 195
8.8.2 Register Configuration and Description ........................................................... 195
8.8.3 Pin Functions .................................................................................................... 197
8.8.4 Pin States .......................................................................................................... 197
8.9 Port 9................................................................................................................................. 198
8.9.1 Overview........................................................................................................... 198
8.9.2 Register Configuration and Description ........................................................... 198
8.9.3 Pin Functions .................................................................................................... 200
8.9.4 Pin States .......................................................................................................... 200
8.10 Port A................................................................................................................................ 201
8.10.1 Overview........................................................................................................... 201
8.10.2 Register Configuration and Description ........................................................... 201
8.10.3 Pin Functions .................................................................................................... 203
8.10.4 Pin States .......................................................................................................... 204
Rev. 1.00 Dec. 19, 2007 Page xv of xx
8.11 Port B................................................................................................................................ 204
8.11.1 Overview........................................................................................................... 204
8.11.2 Register Configuration and Description ........................................................... 205
8.11.3 Pin Functions .................................................................................................... 207
8.12 Input/Output Data Inversion Function .............................................................................. 208
8.12.1 Overview........................................................................................................... 208
8.12.2 Register Configuration and Descriptions.......................................................... 209
8.12.3 Note on Modification of Serial Port Control Register ...................................... 210
8.13 Application Note............................................................................................................... 211
8.13.1 The Management of the Un-Use Terminal ....................................................... 211
Section 9 Timers ................................................................................................213
9.1 Overview .......................................................................................................................... 213
9.2 Timer A............................................................................................................................. 214
9.2.1 Overview........................................................................................................... 214
9.2.2 Register Descriptions........................................................................................ 216
9.2.3 Timer Operation................................................................................................ 219
9.2.4 Timer A Operation States ................................................................................. 220
9.2.5 Application Note............................................................................................... 220
9.3 Timer C............................................................................................................................. 221
9.3.1 Overview........................................................................................................... 221
9.3.2 Register Descriptions........................................................................................ 223
9.3.3 Timer Operation................................................................................................ 226
9.3.4 Timer C Operation States ................................................................................. 228
9.4 Timer F ............................................................................................................................. 229
9.4.1 Overview........................................................................................................... 229
9.4.2 Register Descriptions........................................................................................ 233
9.4.3 CPU Interface ................................................................................................... 241
9.4.4 Operation .......................................................................................................... 244
9.4.5 Application Notes ............................................................................................. 247
9.5 Timer G............................................................................................................................. 251
9.5.1 Overview........................................................................................................... 251
9.5.2 Register Descriptions........................................................................................ 253
9.5.3 Noise Canceler.................................................................................................. 258
9.5.4 Operation .......................................................................................................... 260
9.5.5 Application Notes ............................................................................................. 265
9.5.6 Timer G Application Example.......................................................................... 269
9.6 Watchdog Timer ............................................................................................................... 270
9.6.1 Overview........................................................................................................... 270
9.6.2 Register Descriptions........................................................................................ 272
Rev. 1.00 Dec. 19, 2007 Page xvi of xx
9.6.3 Timer Operation................................................................................................ 278
9.6.4 Watchdog Timer Operation States.................................................................... 279
9.7 Asynchronous Event Counter (AEC)................................................................................ 280
9.7.1 Overview........................................................................................................... 280
9.7.2 Register Configurations .................................................................................... 283
9.7.3 Operation .......................................................................................................... 293
9.7.4 Asynchronous Event Counter Operation Modes............................................... 298
9.7.5 Application Notes ............................................................................................. 299
Section 10 Serial Communication Interface......................................................301
10.1 Overview .......................................................................................................................... 301
10.1.1 Features............................................................................................................. 301
10.1.2 Block Diagram.................................................................................................. 303
10.1.3 Pin Configuration.............................................................................................. 304
10.1.4 Register Configuration...................................................................................... 304
10.2 Register Descriptions........................................................................................................ 305
10.2.1 Receive Shift Register (RSR) ........................................................................... 305
10.2.2 Receive Data Register (RDR)........................................................................... 305
10.2.3 Transmit Shift Register (TSR) .......................................................................... 306
10.2.4 Transmit Data Register (TDR).......................................................................... 306
10.2.5 Serial Mode Register (SMR) ............................................................................ 307
10.2.6 Serial Control Register 3 (SCR3) ..................................................................... 310
10.2.7 Serial Status Register (SSR) ............................................................................. 314
10.2.8 Bit Rate Register (BRR) ................................................................................... 317
10.2.9 Clock stop register 1 (CKSTPR1)..................................................................... 323
10.2.10 Serial Port Control Register (SPCR)................................................................. 324
10.3 Operation .......................................................................................................................... 325
10.3.1 Overview........................................................................................................... 325
10.3.2 Operation in Asynchronous Mode .................................................................... 329
10.3.3 Operation in Synchronous Mode ...................................................................... 338
10.4 Interrupts........................................................................................................................... 345
10.5 Application Notes ............................................................................................................. 346
Section 11 10-Bit PWM ....................................................................................353
11.1 Overview .......................................................................................................................... 353
11.1.1 Features............................................................................................................. 353
11.1.2 Block Diagram.................................................................................................. 354
11.1.3 Pin Configuration.............................................................................................. 354
11.1.4 Register Configuration...................................................................................... 355
Rev. 1.00 Dec. 19, 2007 Page xvii of xx
11.2 Register Descriptions........................................................................................................ 355
11.2.1 PWM Control Register (PWCRm) ................................................................... 355
11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm) .................................. 357
11.2.3 Clock Stop Register 2 (CKSTPR2)................................................................... 358
11.3 Operation .......................................................................................................................... 359
11.3.1 Operation .......................................................................................................... 359
11.3.2 PWM Operation Modes.................................................................................... 360
Section 12 A/D Converter..................................................................................361
12.1 Overview .......................................................................................................................... 361
12.1.1 Features............................................................................................................. 361
12.1.2 Block Diagram.................................................................................................. 362
12.1.3 Pin Configuration.............................................................................................. 363
12.1.4 Register Configuration...................................................................................... 363
12.2 Register Descriptions........................................................................................................ 364
12.2.1 A/D Result Registers (ADRRH, ADRRL) ....................................................... 364
12.2.2 A/D Mode Register (AMR) .............................................................................. 364
12.2.3 A/D Start Register (ADSR) .............................................................................. 366
12.2.4 Clock Stop Register 1 (CKSTPR1)................................................................... 367
12.3 Operation .......................................................................................................................... 368
12.3.1 A/D Conversion Operation ............................................................................... 368
12.3.2 Start of A/D Conversion by External Trigger Input.......................................... 368
12.3.3 A/D Converter Operation Modes...................................................................... 369
12.4 Interrupts........................................................................................................................... 369
12.5 Typical Use....................................................................................................................... 370
12.6 A/D Conversion Accuracy Definitions............................................................................. 374
12.7 Application Notes ............................................................................................................. 376
12.7.1 Permissible Signal Source Impedance .............................................................. 376
12.7.2 Influences on Absolute Precision...................................................................... 376
12.7.3 Additional Usage Notes .................................................................................... 377
Section 13 LCD Controller/Driver ....................................................................379
13.1 Overview .......................................................................................................................... 379
13.1.1 Features............................................................................................................. 379
13.1.2 Block Diagram.................................................................................................. 380
13.1.3 Pin Configuration.............................................................................................. 381
13.1.4 Register Configuration...................................................................................... 381
13.2 Register Descriptions........................................................................................................ 382
13.2.1 LCD Port Control Register (LPCR).................................................................. 382
13.2.2 LCD Control Register (LCR)............................................................................ 384
Rev. 1.00 Dec. 19, 2007 Page xviii of xx
13.2.3 LCD Control Register 2 (LCR2)....................................................................... 386
13.2.4 Clock Stop Register 2 (CKSTPR2)................................................................... 388
13.3 Operation .......................................................................................................................... 389
13.3.1 Settings up to LCD Display .............................................................................. 389
13.3.2 Relationship between LCD RAM and Display................................................. 391
13.3.3 Operation in Power-Down Modes .................................................................... 396
13.3.4 Boosting the LCD Drive Power Supply............................................................ 397
Section 14 Power-On Reset and Low-Voltage Detection Circuits ...................399
14.1 Overview .......................................................................................................................... 399
14.1.1 Features............................................................................................................. 400
14.1.2 Block Diagram.................................................................................................. 401
14.1.3 Pin Description ................................................................................................. 402
14.1.4 Register Descriptions........................................................................................ 402
14.2 Individual Register Descriptions....................................................................................... 402
14.2.1 Low-Voltage Detection Control Register (LVDCR) ........................................ 402
14.2.2 Low-Voltage Detection Status Register (LVDSR) ........................................... 405
14.2.3 Low-Voltage Detection Counter (LVDCNT) ................................................... 407
14.2.4 Clock Stop Register 2 (CKSTPR2)................................................................... 407
14.3 Operation .......................................................................................................................... 408
14.3.1 Power-On Reset Circuit .................................................................................... 408
14.3.2 Low-Voltage Detection Circuit......................................................................... 409
Section 15 Power Supply Circuit ......................................................................417
15.1 When Using Internal Power Supply Step-Down Circuit .................................................. 417
15.2 When Not Using Internal Power Supply Step-Down Circuit ........................................... 418
Section 16 List of Registers...............................................................................419
16.1 Register Addresses (Address Order)................................................................................. 420
16.2 Register Bits...................................................................................................................... 424
16.3 Register States in Each Operating Mode .......................................................................... 428
Section 17 Electrical Characteristics ................................................................. 433
17.1 Absolute Maximum Ratings (Flash Memory Version and Mask ROM Version)............. 433
17.2 Electrical Characteristics (Flash Memory Version and Mask ROM Version).................. 434
17.2.1 Power Supply Voltage and Operating Ranges.................................................. 434
17.2.2 DC Characteristics ............................................................................................ 438
17.2.3 AC Characteristics ............................................................................................ 447
17.2.4 A/D Converter Characteristics.......................................................................... 450
17.2.5 LCD Characteristics.......................................................................................... 451
Rev. 1.00 Dec. 19, 2007 Page xix of xx
17.2.6 Flash Memory Characteristics .......................................................................... 452
17.2.7 Power Supply Voltage Detection Circuit Characteristics ................................. 454
17.2.8 Power-On Reset Circuit Characteristics ........................................................... 457
17.2.9 Watchdog Timer Characteristics....................................................................... 458
17.3 Operation Timing.............................................................................................................. 458
17.4 Output Load Circuit.......................................................................................................... 461
17.5 Resonator Equivalent Circuit............................................................................................ 461
17.6 Usage Note........................................................................................................................ 462
Appendix..............................................................................................................463
A. Instruction Set................................................................................................................... 463
A.1 Instruction List.................................................................................................. 463
A.2 Operation Code Map......................................................................................... 478
A.3 Number of Execution States ............................................................................. 481
A.4 Combinations of Instructions and Addressing Modes ...................................... 492
B. I/O Port Block Diagrams .................................................................................................. 493
B.1 Block Diagrams of Port 1 ................................................................................. 493
B.2 Block Diagrams of Port 3 ................................................................................. 495
B.3 Block Diagrams of Port 4 ................................................................................. 500
B.4 Block Diagram of Port 5................................................................................... 504
B.5 Block Diagram of Port 6................................................................................... 505
B.6 Block Diagram of Port 7................................................................................... 506
B.7 Block Diagram of Port 8................................................................................... 507
B.8 Block Diagrams of Port 9 ................................................................................. 508
B.9 Block Diagram of Port A .................................................................................. 510
B.10 Block Diagrams of Port B................................................................................. 511
C. Port States in the Different Processing States................................................................... 514
D. List of Product Codes ....................................................................................................... 515
E. Package Dimensions......................................................................................................... 516
Index ....................................................................................................................519
Rev. 1.00 Dec. 19, 2007 Page xx of xx
Section 1 Overview
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REJ09B0409-0100
Section 1 Overview
1.1 Features
Microcontrollers of the H8/38524 Group are CISC (complex instruction set computer)
microcontrollers whose core is an H8/300H CPU, which has an internal 32-bit architecture. The
H8/300H CPU provides upward compatibility with the H8/300 CPUs of other Renesas
Technology-original microcontrollers.
As peripheral functions, each LSI of this Group includes various timer functions that realize low-
cost configurations for end systems. The power consumption of these modules can be kept down
dynamically by power-down mode.
1.1.1 Application
Examples of the applications of this LSI include motor control, power meter, and health
equipment.
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REJ09B0409-0100
1.1.2 Overview of Specifications
Table 1.1 lists the functions of H8/38524 Group products in outline.
Table 1.1 Overview of Functions
Classification Module/
Function Description
ROM • ROM lineup: Flash memory version and mask Rom version
• ROM capacity: 8 K, 12 K, 16 K, 24 K, and 32 Kbytes
Memory
RAM • RAM capacity: 512 and 1024 bytes
CPU • H8/300H CPU (CISC type)
Upward compatibility for H8/300 CPU at object level
• Sixteen 16-bit general registers
• Eight addressing modes
• 64-Kbyte address space
Program: 64 Kbytes available
Data: 64 Kbytes available
• 62 basic instructions, classifiable as bit arithmetic and logic
instructions, multiply and divide instructions, bit manipulation
instructions, and others
• Minimum instruction execution time: 400 ns (for an ADD
instruction while system clock φ = 5 MHz and
VCC = 2.7 to 3.6 V)
• On-chip multiplier (16 × 16 → 32 bits)
Operating
mode
• Normal mode
CPU
MCU
operating
mode
Mode: Single-chip mode
• Low power consumption state (transition driven by the SLEEP
instruction)
Interrupt
(source)
Interrupt
controller
(INTC)
• Thirteen external interrupt pins (IRQAEC, IRQ4, IRQ3, IRQ1,
IRQ0, WKP7 to WKP0)
• Nine internal interrupt sources
• Independent vector addresses
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Classification Module/
Function Description
Clock Clock pulse
generator
(CPG)
• Two clock generation circuits available
• Separate clock signals are provided for each of functional
modules
• Includes frequency division circuit, so the operating frequency
is selectable
• Seven low-power-consumption modes: Active (medium speed)
mode, sleep (high speed or medium speed) mode, subactive
mode, subsleep mode, standby mode, and watch mode
• Equipped with an on-chip oscillator
A/D converter A/D
converter
(ADC)
• 10-bit resolution × eight input channels
• Sample and hold function included
• Conversion time:
12.4 µs per channel (with φ at 5-MHz operation) /
6.2 µs per channel (with φ at 10-MHz operation)
• A/D conversion can be started by external trigger input
10-bit PWM • 10 bits × two channels
• Four conversion periods selectable
• Pulse division method for less ripple
Timer A • 8-bit timer
• Interval timer functionality: Eight internal clock sources are
selectable
• Clock time base functionality: Four overflow periods are
selectable
• Generates an interrupt upon overflow
Timer C • 8-bit timer
• Eight clocks are selectable
• Auto-reload function supported
• Generates an interrupt upon overflow
• Up/down-counter switching is possible
Timer
Timer F • 16-bit timer (also can be used as two independent 8-bit timers)
• Five clocks are selectable
• Output compare function supported
• Toggle output function supported
• Two interrupt sources: Compare match and overflow
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REJ09B0409-0100
Classification Module/
Function Description
Timer G • 8-bit timer
• Four counter input clocks are selectable
• Input capture functions supported (a built-in noise canceller)
• Level detection at counter overflow is possible
• Counter clearing option
• Two interrupt sources: Input capture and overflow
Timer
Asynchron-
ous event
counter
(AEC)
• 16-bit pulse timer (also can be used as 8 bits × two channels)
• Can count asynchronously-input external events
Watchdog timer Watchdog
timer (WDT)
8 bits × one channel (selectable from ten counter input clocks)
Serial interface Serial
communi-
cation
interface 3
(SCI3)
• For both asynchronous and clock synchronous serial
communications
• Full-duplex communications capability
• Select the desired bit rate
• Six interrupt sources
I/O ports • Nine CMOS input-only pins
• Six CMOS output-only pins
• 50 CMOS input/output pins
• Six large-current-drive pins (port 9)
• 27 pull-up resistors
• Seven open drains
LCD (Liquid
Crystal Display)
drive
LCD
controller/
driver
• A maximum of 32 segment pins and four common pins
• Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
• LCD RAM capacity: 8 bits × 16 bytes (128 bits)
• Word access to LCD RAM
• All four segment output pins can be used individually as port
pins
• Common output pins not used because of the duty cycle can be
used for common double-buffering (parallel connection)
• Display possible in operating modes other than standby mode
• Choice of 11 frame frequencies
• Built-in power supply split-resistance, supplying LCD drive
power
• A or B waveform selectable by software
• Removal of split-resistance can be controlled in software
Section 1 Overview
Rev. 1.00 Dec. 19, 2007 Page 5 of 520
REJ09B0409-0100
Classification Module/
Function Description
Measures in
power supply
drops
Power-on
reset and
low-voltage
detection
circuits
• Power-on reset circuit:
An internal reset signal can be issued at power-on by
connecting an external capacitor
• Low-voltage detection circuit:
Monitors the power supply voltage and issues an internal reset
signal or interrupt if the voltage goes below or above a specified
range
Internal power
supply step-
down circuit
Power
supply
circuit
• The internal power supply can be fixed at a constant level of
approximately 3.0 V, independently of the voltage of the power
supply connected to the external VCC pin
• It is also possible to use the same level of external power
supply voltage and internal power supply voltage without using
the internal power supply step-down circuit
Package • QFP-80: package code: FP-80A
(package dimensions: 14 × 14 mm, pin pitch: 0.65 mm)
• TQFP-80: package code: TFP-80C
(package dimensions: 12 × 12 mm, pin pitch: 0.50 mm)
Operating frequency/
Power supply voltage
• Operating frequency: 2 to 20 MHz
• Power supply voltage:
Vcc = 2.7 to 5.5 V, AVcc = 2.7 to 5.5 V
• Supply current:
Flash memory version: 4.0 mA (typ.)
(Vcc = 5.0 V, AVcc = 5.0 V, φ = 10 MHz)
Mask ROM version: 3.3 mA (typ.)
(Vcc = 5.0 V, AVcc = 5.0 V, φ = 10 MHz)
Operating peripheral
temperature (°C)
• −20 to +75°C (regular specifications)
• −40 to +85°C (wide-range specifications)
Section 1 Overview
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REJ09B0409-0100
1.2 List of Products
Table 1.2 and figure 1.1 show the list of products and the structure of a product number,
respectively.
Table 1.2 List of Products
Group Product Type
ROM
Size RAM Size Package Remarks
HD64F38524 32 Kbytes 1 Kbyte Flash memory
version
HD64338524 32 Kbytes 1 Kbyte Mask ROM
version
HD64338523 24 Kbytes 1 Kbyte Mask ROM
version
HD64F38522 16 Kbytes 1 Kbyte Flash memory
version
HD64338522 16 Kbytes 1 Kbyte Mask ROM
version
HD64338521 12 Kbytes 512 bytes Mask ROM
version
H8/38524
Group
HD64338520 8 Kbytes 512 bytes
FP-80A,
TFP-80C
Mask ROM
version
Section 1 Overview
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REJ09B0409-0100
Product type no. HD 64 F 38524
Indicates the product-specific number.
Indicates the type of ROM device.
Indicates the product family classification
H8 Family
Indicates the microcontroller.
H8/38524 Group
F: Flash memory
3: Mask ROM
H
Indicates the package.
H: QFP
W: TQFP
Figure 1.1 How to Read the Product Name Code
Section 1 Overview
Rev. 1.00 Dec. 19, 2007 Page 8 of 520
REJ09B0409-0100
1.3 Block Diagram
Sub clock
OSC
H8/300H
CPU
RAM
(512 bytes to 1 Kbyte)
System clock
OSC
ROM
(8 Kbytes to 32 Kbytes)
Power-on reset and
low-voltage detect circuits
Timer A
Timer C Timer F
Timer G
Asynchronous
counter
(16 bits)
A/D
(10 bits)
Serial
communication
interface
(SCI3)
10-bit PWM1
10-bit PWM2
LCD
controller
Large-current (15 mA/pin)
PA
3
/COM
4
PA
2
/COM
3
PA
1
/COM
2
PA
0
/COM
1
P7
7
/SEG
24
P7
6
/SEG
23
P7
5
/SEG
22
P7
4
/SEG
21
P7
3
/SEG
20
P7
2
/SEG
19
P7
1
/SEG
18
P7
0
/SEG
17
P8
7
/SEG
32
P8
6
/SEG
31
P8
5
/SEG
30
P8
4
/SEG
29
P8
3
/SEG
28
P8
2
/SEG
27
P8
1
/SEG
26
P8
0
/SEG
25
P6
0
/SEG
9
P6
1
/SEG
10
P6
2
/SEG
11
P6
3
/SEG
12
P6
4
/SEG
13
P6
5
/SEG
14
P6
6
/SEG
15
P6
7
/SEG
16
P4
0
/SCK
32
P4
1
/RXD
32
P4
2
/TXD
32
P4
3
/IRQ
0
OSC
1
OSC
2
x
1
x
2
P1
3
/TMIG
P1
4
/IRQ
4
/ADTRG
P1
7
/IRQ
3
/TMIF
P3
0
/UD
P3
1
/TMOFL
P3
2
/TMOFH
P3
3
P3
4
P3
5
P3
6
/AEVH
P3
7
/AEVL
P5
0
/WKP
0
/SEG
1
P5
1
/WKP
1
/SEG
2
P5
2
/WKP
2
/SEG
3
P5
3
/WKP
3
/SEG
4
P5
4
/WKP
4
/SEG
5
P5
5
/WKP
5
/SEG
6
P5
6
/WKP
6
/SEG
7
P5
7
/WKP
7
/SEG
8
PB
7
/AN
7
PB
6
/AN
6
PB
5
/AN
5
PB
4
/AN
4
PB
3
/AN
3
/IRQ
1
/TMIC
PB
2
/AN
2
PB
1
/AN
1
/extU
PB
0
/AN
0
/extD
V
1
V
2
V
3
IRQAEC
P9
5
P9
4
P9
3
/V
ref
P9
2
P9
1
/PWM
2
P9
0
/PWM
1
AV
CC
WDT
CV
CC
V
SS
V
SS
= AV
SS
V
CC
RES
TEST
Note: If the on-chip emulator is used, pins 95,
33, 34, and 35 are reserved for the
emulator and not available to the user.
Port 6 Port 5 Port 4 Port 3 Port 1
Port APort 9Port 8Port 7
LCD power
supply
Port B
Figure 1.2 Block Diagram of H8/ 3 85 24 Grou p
Section 1 Overview
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REJ09B0409-0100
1.4 Pin Assignment
FP-80A,TFP-80C
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P3
0
/UD
P3
1
/TMOFL
P3
2
/TMOFH
P3
3
P3
4
P3
5
P3
6
/AEVH
P3
7
/AEVL
P4
0
/SCK
32
P4
1
/RXD
32
P4
2
/TXD
32
P4
3
/IRQ
0
PB
0
/AN
0
/extD
PB
1
/AN
1
/extU
PB
2
/AN
2
PB
3
/AN
3
/IRQ
1
/TMIC
PB
4
/AN
4
PB
5
/AN
5
PB
6
/AN
6
PB
7
/AN
7
AV
CC
P1
3
/TMIG
P1
4
/IRQ
4
/ADTRG
CV
CC
P1
7
/IRQ
3
/TMIF
X
1
X
2
V
SS
=AV
SS
OSC
2
OSC
1
TEST
RES
P5
0
/WKP
0
/SEG
1
P5
1
/WKP
1
/SEG
2
P5
2
/WKP
2
/SEG
3
P5
3
/WKP
3
/SEG
4
P5
4
/WKP
4
/SEG
5
P5
5
/WKP
5
/SEG
6
P5
6
/WKP
6
/SEG
7
P5
7
/WKP
7
/SEG
8
P8
3
/SEG
28
P8
2
/SEG
27
P8
1
/SEG
26
P8
0
/SEG
25
P7
7
/SEG
24
P7
6
/SEG
23
P7
5
/SEG
22
P7
4
/SEG
21
P7
3
/SEG
20
P7
2
/SEG
19
P7
1
/SEG
18
P7
0
/SEG
17
P6
7
/SEG
16
P6
6
/SEG
15
P6
5
/SEG
14
P6
4
/SEG
13
P6
3
/SEG
12
P6
2
/SEG
11
P6
1
/SEG
10
P6
0
/SEG
9
IRQAEC
P9
5
P9
4
P9
3
/V
ref
P9
2
P9
1
/PWM
2
P9
0
/PWM
1
V
SS
V
CC
V
1
V
2
V
3
PA
0
/COM
1
PA
1
/COM
2
PA
2
/COM
3
PA
3
/COM
4
P8
7
/SEG
32
P8
6
/SEG
31
P8
5
/SEG
30
P8
4
/SEG
29
Note: If the on-chip emulator is used, pins 95, 33, 34, and 35 are reserved for the emulator and not available to the user.
Figure 1.3 Pin Assignment of H8/38524 Group
(FP-80A and TFP-80C)
Section 1 Overview
Rev. 1.00 Dec. 19, 2007 Page 10 of 520
REJ09B0409-0100
1.5 Pin Functions
Table 1.3 Pin Functions
Pin No.
Type Symbol FP-80A, TFP-80C I/O Functions
VCC 52 Input Power supply: All VCC pins should be
connected to the system power supply.
VSS 8 (= AVSS), 53 Input Ground: All VSS pins should be
connected to the system power supply
(0 V).
AVCC 1 Input Analog power supply: This is the
power supply pin for the A/D converter.
When the A/D converter is not used,
connect this pin to the system power
supply.
AVSS 8 (= VSS) Input Analog ground: This is the A/D
converter ground pin. It should be
connected to the system power supply
(0V).
V1
V2
V3
51
50
49
Input LCD power supply: These are the
power supply pins for the LCD
controller/driver.
Power
source pins
CVCC 4 Input Power supply: This is the internal
step-down power supply pin. To
ensure stability, a capacitor with a
rating of about 0.1 µF should be
connected between this pin and the VSS
pin.
OSC1 10 Input
OSC2 9 Output
These pins connect to a crystal or
ceramic oscillator, or can be used to
input an external clock. See section 4,
Clock Pulse Generators, for a typical
connection diagram.
X1 6 Input
Clock pins
X2 7 Output
These pins connect to a 32.768-kHz
crystal oscillator. See section 4, Clock
Pulse Generators, for a typical
connection diagram.
Section 1 Overview
Rev. 1.00 Dec. 19, 2007 Page 11 of 520
REJ09B0409-0100
Pin No.
Type Symbol FP-80A, TFP-80C I/O Functions
RES 12 Input Reset: When this pin is driven low, the
chip is reset.
System
control
TEST 11 Input Test pin: This pin is reserved and
cannot be used. It should be
connected to VSS.
IRQ0
IRQ1
IRQ3
IRQ4
72
76
5
3
Input IRQ interrupt request 4, 3, 1, and 0:
These are input pins for edge-sensitive
external interrupts, with a selection of
rising or falling edge.
IRQAEC 60 Input Asynchronous event counter event
signal: This is an interrupt input pin for
enabling asynchronous event input.
This must be fixed at VCC or GND
because the oscillator is selected by
the input level during resets. Refer to
section 4, Clock Pulse Generators, for
information on the selection method.
Interrupt
pins
WKP7 to
WKP0
20 to 13 Input Wakeup interrupt request 7 to 0:
These are input pins for rising or
falling-edge-sensitive external
interrupts.
AEVL
AEVH
68
67
Input Asynchronous event counter event
input: These are event input pins for
input to the asynchronous event
counter.
TMIC 76 Input Timer C event input: This is an event
input pin for input to the timer C
counter.
UD 61 Input Timer C up/down select: This pin
selects up- or down-counting for the
timer C counter. The counter operates
as a down-counter when this pin is
high, and as an up-counter when low.
Timer
TMIF 5 Input Timer F event input: This is an event
input pin for input to the timer F
counter.
Section 1 Overview
Rev. 1.00 Dec. 19, 2007 Page 12 of 520
REJ09B0409-0100
Pin No.
Type Symbol FP-80A, TFP-80C I/O Functions
TMOFL 62 Output Timer FL output: This is an output pin
for waveforms generated by the timer
FL output compare function.
TMOFH 63 Output Timer FH output: This is an output pin
for waveforms generated by the timer
FH output compare function.
Timer
TMIG 2 Input Timer G capture input: This is an
input pin for timer G input capture.
10-bit PWM PWM1
PWM2
54
55
Output 10-bit PWM output: These are output
pins for waveforms generated by the
channel 1 and 2 10-bit PWMs.
P17
P14
P13
5
3
2
I/O Port 1: This is a 3-bit I/O port. Input or
output can be designated for each bit
by means of port control register 1
(PCR1).
P37 to P30 68 to 61 I/O Port 3: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 3
(PCR3).
If the on-chip emulator is used, pins
33, 34, and 35 are reserved for the
emulator and not available to the user.
P43 72 Input Port 4 (bit 3): This is a 1-bit input port.
P42 to P40 71 to 69 I/O Port 4 (bits 2 to 0): This is a 3-bit I/O
port. Input or output can be designated
for each bit by means of port control
register 4 (PCR4).
P57 to P50 20 to 13 I/O Port 5: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 5
(PCR5).
I/O ports
P67 to P60 28 to 21 I/O Port 6: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 6
(PCR6).
Section 1 Overview
Rev. 1.00 Dec. 19, 2007 Page 13 of 520
REJ09B0409-0100
Pin No.
Type Symbol FP-80A, TFP-80C I/O Functions
P77 to P70 36 to 29 I/O Port 7: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 7
(PCR7).
P87 to P80 44 to 37 I/O Port 8: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 8
(PCR8).
P95 to P90 59 to 54 Output Port 9: This is a 6-bit output port. If the
on-chip emulator is used, pin 95 is
reserved for the emulator and not
available to the user. In the case of the
flash memory version, pin 95 should
not be left open in the user mode, and
should instead be pulled up to high
level.
PA3 to PA0 45 to 48 I/O Port A: This is a 4-bit I/O port. Input or
output can be designated for each bit
by means of port control register A
(PCRA).
I/O ports
PB7 to PB0 80 to 73 Input Port B: This is an 8-bit input port.
RXD32 70 Input SCI3 receive data input: This is the
SCI3 data input pin.
TXD32 71 Output SCI3 transmit data output: This is the
SCI3 data output pin.
Serial com-
munication
interface
(SCI)
SCK32 69 I/O SCI3 clock I/O: This is the SCI3 clock
I/O pin.
AN7 to AN0 80 to 73 Input Analog input channels 7 to 0: These
are analog data input channels to the
A/D converter.
A/D
converter
ADTRG 3 Input A/D converter trigger input: This is
the external trigger input pin to the A/D
converter.
COM4 to
COM1
45 to 48 Output LCD common output: These are the
LCD common output pins.
LCD
controller/
driver SEG32 to
SEG1
44 to 13 Output LCD segment output: These are the
LCD segment output pins.
Section 1 Overview
Rev. 1.00 Dec. 19, 2007 Page 14 of 520
REJ09B0409-0100
Pin No.
Type Symbol FP-80A, TFP-80C I/O Functions
Vref 57 Input LVD reference voltage input: This is
the LVD reference voltage input pin.
extD 73 Input LVD power supply drop detect
voltage input: This is the LVD power
supply drop detect voltage input pin.
Low-voltage
detection
circuit (LVD)
extU 74 Input LVD power supply rise detect
voltage input: This is the LVD power
supply rise detect voltage input pin.
NC NC NC pin
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 15 of 520
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Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with
the H8/300 CPU, and supports only normal mode, which has a 64-Kbyte address space.
• Upward-compatible with H8/300 CPUs
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added.
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit registers,
or eight 32-bit registers
• Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 64-Kbyte address space
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract : 2 state
8 × 8-bit register-register multiply : 14 states
16 ÷ 8-bit register-register divide : 14 states
16 × 16-bit register-register multiply : 22 states
32 ÷ 16-bit register-register divide : 22 states
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 16 of 520
REJ09B0409-0100
• Power-down state
Transition to power-down state by SLEEP instruction
Section 2 CPU
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REJ09B0409-0100
2.1 Address Space and Memory Map
The memory map of the H8/38524 is shown in figure 2.1(1), that of the H8/38523 in figure
2.16(2), that of the H8/38522 in figure 2.1(3), that of the H8/38521 in figure 2.1(4), and that of the
H8/38520 in figure 2.1(5).
H'0000
H'0029
H'002A
H'7FFF
H'7000
H'F020
H'F02B
H'F740
H'F74F
H'FB80
H'FB7F
H'FF7F
H'FF80
H'FFFF
Interrupt vector area
User area
(1 Kbyte)
On-chip ROM
32 Kbytes
(32768 bytes)
1024 bytes
Internal I/O register
(128 bytes)
(Workarea for reprogramming
flash memory: 1 Kbyte)*
2
Internal I/O register
Not used
Firmware
for on-chip emulator*
1
H'F780
Not used
Not used
LCD RAM (16 bytes)
H'0000
H'0029
H'002A
H'7FFF
H'F740
H'F74F
H'FB80
H'FF7F
H'FF80
H'FFFF
Interrupt vector area
Flash memory version Mask ROM version
On-chip ROM
32 Kbytes
(32768 bytes)
1024 bytesOn-chip RAM
Internal I/O register
(128 bytes)
Not used
Not used
LCD RAM (16 bytes)
On-chip RAM
(2 Kbytes)
Notes: 1. Not available to the user if the on-chip emulator is used.
2. Used by the programming control program when programming flash memory. Also, not available to the user
if the on-chip emulator is used.
Figure 2.1(1) H8/38524 Memory Map
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 18 of 520
REJ09B0409-0100
H'0000
H'0029
H'002A
H'5FFF
H'F740
H'F74F
H'FB80
H'FF7F
H'FF80
H'FFFF
Interrupt vector area
On-chip ROM
24 Kbytes
(24576 bytes)
1024 bytesOn-chip RAM
Internal I/O registers
(128 bytes)
Not used
Not used
LCD RAM
(16 bytes)
Figure 2.1(2) H8/38523 Memory Map
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 19 of 520
REJ09B0409-0100
H'0000
H'0029
H'002A
H'3FFF H'3FFF
H'7FFF
H'7000
H'F020
H'F02B
H'F740
H'F74F
H'FB80
H'FB7F
H'FF7F
H'FF80
H'FFFF
Interrupt vector area
User area
(1 Kbyte)
On-chip ROM 16 Kbytes
(16384 bytes)
1024 bytes
Internal I/O register
(128 bytes)
(Workarea for reprogramming
flash memory: 1 Kbyte)*
Internal I/O register
Not used
Firmware
for on-chip emulator
H'F780
Not used
Not used
Not used
LCD RAM (16 bytes)
H'0000
H'0029
H'002A
H'F740
H'F74F
H'FB80
H'FF7F
H'FF80
H'FFFF
Interrupt vector area
Flash memory version Mask ROM version
On-chip ROM
16 Kbytes
(16384 bytes)
1024 bytesOn-chip RAM
Internal I/O register
(128 bytes)
Not used
Not used
LCD RAM (16 bytes)
On-chip RAM
(2 Kbytes)
Note: * Used by the programming control program when programming flash memory. Also, not available to the user if
the on-chip emulator is used.
Figure 2.1(3) H8/38522 Memory Map
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 20 of 520
REJ09B0409-0100
H'0000
H'0029
H'002A
H'2FFF
H'F740
H'F74F
H'FD80
H'FF7F
H'FF80
H'FFFF
Interrupt vector area
On-chip ROM
12 Kbytes
(12288 bytes)
512 bytesOn-chip RAM
Internal I/O registers
(128 bytes)
Not used
Not used
LCD RAM
(16 bytes)
Figure 2.1(4) H8/38521 Memory Map
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 21 of 520
REJ09B0409-0100
H'0000
H'0029
H'002A
H'1FFF
H'F740
H'F74F
H'FD80
H'FF7F
H'FF80
H'FFFF
Interrupt vector area
On-chip ROM
8 Kbytes
(8192 bytes)
512 bytesOn-chip RAM
Internal I/O registers
(128 bytes)
Not used
Not used
LCD RAM
(16 bytes)
Figure 2.1(5) H8/38520 Memory Map
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 22 of 520
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2.2 Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition-code register (CCR).
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
SP:
PC:
CCR:
I:
UI:
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
IUIHUNZVC
CCR
76543210
H:
U:
N:
Z:
V:
C:
General Registers (ERn)
Control Registers (CR)
[Legend]
(SP)
Figure 2.2 CPU Registers
Section 2 CPU
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REJ09B0409-0100
2.2.1 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected independently.
• Address registers
• 32-bit registers
• 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.3 Usage of General Regi sters
General register ER7 has the function of the stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
relationship between the stack pointer and the stack area.
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 24 of 520
REJ09B0409-0100
SP (ER7)
Empty area
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area
2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leave flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
Section 2 CPU
Rev. 1.00 Dec. 19, 2007 Page 25 of 520
REJ09B0409-0100
Bit Bit Name
Initial
Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
6 UI Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5 H Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4 U Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3 N Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1 V Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0 C Undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Section 2 CPU
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2.3 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.3.1 General Register Data Formats
Figure 2.5 shows the data formats in general registers.
7 0
70
MSB LSB
MSB LSB
704 3
Don't care
Don't care
Don't care
7 04 3
70
Don't care
6543271
0
70
Don't care 65432710
Don't care
RnH
RnL
RnH
RnL
RnH
RnL
Data Type General Register Data Format
Byte data
Byte data
4-bit BCD data
4-bit BCD data
1-bit data
1-bit data
Upper Lower
Upper Lower
Figure 2.5 General Register Data Formats (1)
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15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Data Type Data FormatGeneral
Register
Word data
Word data
Rn
En
Longword
data
[Legend]
ERn
Figure 2.5 General Register Data Formats (2)
Section 2 CPU
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2.3.2 Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack area, the operand size should be
word or longword.
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Data Type Address
1-bit data
Byte data
Word data
Address L
Address L
Address 2M
Address 2M+1
Longword data Address 2N
Address 2N+1
Address 2N+2
Address 2N+3
Data Format
Figure 2.6 Memory Data Form ats
Section 2 CPU
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2.4 Instruction Set
2.4.1 Table of Instructions Cl assified by Function
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined in table 2.1.
Table 2.1 Operation Nota tion
Symbol Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical XOR
→ Move
¬ NOT (logical complement)
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Symbol Description
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
Table 2.2 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in this LSI.
MOVTPE B Rs → (EAs)
Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3 Arithmetic Operations Instructions (1)
Instruction Size* Function
ADD
SUB
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)
ADDX
SUBX
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3 Arithmetic Operations Instructions (2)
Instruction Size* Function
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4 Logic Operations Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ¬ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.5 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.6 Bit Manipulation Instructions (1)
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
BIAND
B
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
BIOR
B
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note: * Refers to the operand size.
B: Byte
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Table 2.6 Bit Manipulation Instructions (2)
Instruction Size* Function
BXOR
BIXOR
B
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
BILD
B
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
BIST
B
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Refers to the operand size.
B: Byte
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Table 2.7 Branch Instructions
Instruction Size Function
Bcc* Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA(BT) Always (true) Always
BRN(BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC(BHS) Carry clear
(high or same)
C = 0
BCS(BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
JMP Branches unconditionally to a specified address.
BSR Branches to a subroutine at a specified address.
JSR Branches to a subroutine at a specified address.
RTS Returns from a subroutine
Note: * Bcc is the general name for conditional branch instructions.
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Table 2.8 System Control Instructions
Instruction Size* Function
RTE Returns from an exception-handling routine.
SLEEP Causes a transition to a power-down state.
LDC B/W (EAs) → CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition code
register size is one byte, but in transfer to memory, data is written by
word access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the CCR with immediate data.
ORC B CCR ∨ #IMM → CCR
Logically ORs the CCR with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically XORs the CCR with immediate data.
NOP PC + 2 → PC
Only increments the program counter.
Note: * Refers to the operand size.
B: Byte
W: Word
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Table 2.9 Block Data Transfer Instructions
Instruction Size Function
EEPMOV.B if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
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2.4.2 Basic Instruction Formats
H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.7 shows examples of instruction formats.
(1) Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried out
on the operand. The operation field always includes the first four bits of the instruction. Some
instructions have two operation fields.
(2) Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
(3) Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
(4) Condition Field
Specifies the branching condition of Bcc instructions.
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
rn rm
op
EA(disp)
op cc EA(disp) BRA d:8
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
Figure 2.7 Instruction Formats
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2.5 Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective address is 16 bits.
2.5.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit-manipulation instructions use register direct, register indirect, or the absolute addressing mode
(@aa:8) to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions)
or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.10 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
(1) Register DirectRn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
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(2) Register Indirect@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
(3) Register Indirect with Displacement@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacement is sign-extended when added.
(4) Register Indirect with Post-Increment or Pre-Decrement@ERn+ or @-ERn
• Register indirect with post-increment@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For the word
or longword access, the register value should be even.
• Register indirect with pre-decrement@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result is the address of a memory operand.
The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access. For the word or longword access, the register value
should be even.
(5) Absolute Address@aa:8, @aa : 16, @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24)
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
The access ranges of absolute addresses for this LSI are those shown in table 2.11, because the
upper 8 bits are ignored.
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Table 2.11 Absolute Address Access Ranges
Absolute Address Access Range
8 bits (@aa:8) H'FF00 to H'FFFF
16 bits (@aa:16) H'0000 to H'FFFF
24 bits (@aa:24) H'0000 to H'FFFF
(6) Immediate#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number.
(7) Program-Counter Relative@(d:8, PC) or @(d:16, PC )
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
(8) Memory Indirect@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed in words, generating a 16-bit branch address. Figure 2.8 shows
how to specify branch address for in memory indirect mode. The upper bits of the absolute address
are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
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Specified
by @aa:8 Branch address
Figure 2.8 Branch Address Specification in Memory Indirect Mode
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2.5.2 Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
No
1
r
op
31 0
23
2
3Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
4
r
opdisp
r
op
rm
op rn
310
0
r
op
230
31 0
disp
31 0
31 0
23 0
23 0
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register direct(Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect(@ERn)
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
•Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand is general register contents.
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
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Table 2.12 Effective Address Calculation (2)
No
5
op
23 0
abs
@aa:8 7
H'FFFF
op
23 0
@aa:16
@aa:24
abs
15
16
23 0
op
abs
6
op IMM
#xx:8/#xx:16/#xx:32
8
Addressing Mode and Instruction Format
Absolute address
Immediate
Effective Address Calculation Effective Address (EA)
Sign extension
Operand is immediate data.
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
Memory indirect @@aa:8
23 0
disp
0
23 0
disp
op
23
op
8
abs 23 0
abs
H'0000
7
8
0
15 23 0
15
H'00
16
[Legend]
r, rm,rn :
op :
disp :
IMM :
abs :
Register field
Operation field
Displacement
Immediate data
Absolute address
PC contents
Sign
extension
Memory contents
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2.6 Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising
edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
T1 state
Bus cycle
T2 state
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Read data
Address
Write data
Internal data bus
(write access)
SUB
φor φ
Figure 2.9 On-Chip Memory Access Cycle
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2.6.2 On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 16.1, Register Addresses (Address Order).
Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, a bus cycle occurs twice. In two-state access, the operation timing is the
same as that for on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
T
1
state
Bus cycle
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Read data
Address
Internal
data bus
(write access)
T
2
state T
3
state
Write data
SUB
φ or φ
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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2.7 CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or medium-
speed) mode and subactive mode. For the program halt state, there are sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and subsleep mode. These states are shown in
figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and
program halt state, refer to section 5, Power-Down Modes. For details on exception handling, refer
to section 3, Exception Handling.
CPU state Reset state
Program execution state Active (high-speed) mode
Active (medium-speed) mode
Power-down modes
Subactive mode
Sleep (high-speed) mode
Sleep (medium-speed) mode
Standby mode
Watch mode
Subsleep mode
Program halt state
A state in which the CPU
operation is stopped to
reduce power consumption
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Exception-handling state
The CPU is initialized
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
The CPU executes successive
program instructions at reduced
speed, synchronized by the subclock
Figure 2.11 CPU Operating States
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Reset state
Program halt state
Exception-handling state
Program execution state
Reset cleared
SLEEP instruction executed
Reset
occurs
Interrupt
source
Reset
occurs
Interrupt
source
Exception-
handling
complete
Reset occurs
Figure 2.12 State Transitions
2.8 Usage Notes
2.8.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
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2.8.3 Bit-Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address, or when a bit is directly manipulated for a port or a register
containing a write-only bit, because this may rewrite data of a bit other than the bit to be
manipulated.
(1) Bit manipulation for two registers as signe d to the same address
Example 1: Bit manipulation for the timer load register and timer counter
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit-manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit-manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Read
Write
Count clock Timer counter
Timer load register
Reload
Internal data bus
Figure 2.13 Example of Ti mer Confi gur ation with Two Regis ters Allocated to Same
Address
Section 2 CPU
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Example 2: When the BSET instruction is executed for port 5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
• Prior to executing BSET instruction
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
• BSET instruction executed
BSET #0, @PDR5 The BSET instruction is executed for port 5.
• After executing BSET instruction
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 1
PDR5 0 1 0 0 0 0 0 1
• Description on operation
1. When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level
input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
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3. Finally, the CPU writes H'41 to PDR5, completing execution of BSET instruction.
As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level
signal. However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem,
store a copy of the PDR5 data in a work area in memory. Perform the bit manipulation on the
data in the work area, then write this data to PDR5.
• Prior to executing BSET instruction
MOV.B #H'80, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
RAM0 1 0 0 0 0 0 0 0
• BSET instruction executed
BSET #0, @RAM0 The BSET instruction is executed designating the PDR5
work area (RAM0).
• After executing BSET instruction
MOV.B @RAM0, R0L
MOV.B R0L, @PDR5
The work area (RAM0) value is written to PDR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 1
RAM0 1 0 0 0 0 0 0 1
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(2) Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
• Prior to executing BCLR instruction
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
• BCLR instruction executed
BCLR #0, @PCR5 The BCLR instruction is executed for PCR5.
• After executing BCLR instruction
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Output Output Output Output Output Output Output Input
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 1 1 1 1 1 1 1 0
PDR5 1 0 0 0 0 0 0 0
• Description on operation
1. When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
2. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
3. Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However,
bits 7 and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
To prevent this problem, store a copy of the PDR5 data in a work area in memory and
manipulate data of the bit in the work area, then write this data to PDR5.
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• Prior to executing BCLR instruction
MOV.B #H'3F, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PCR5
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
RAM0 0 0 1 1 1 1 1 1
• BCLR instruction executed
BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area
(RAM0).
• After executing BCLR instruction
MOV.B @RAM0, R0L
MOV.B R0L, @PCR5
The work area (RAM0) value is written to PCR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 0
PDR5 1 0 0 0 0 0 0 0
RAM0 0 0 1 1 1 1 1 0
Section 3 Exception Handling
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Section 3 Exception Handling
3.1 Overview
Exception handling is performed when a reset or interrupt occurs. Table 3.1 shows the priorities of
these two types of exception handling.
Table 3.1 Exception Handling Types and Priorities
Priority Exception Source Time of Start of Exception Handling
High Reset Exception handling starts as soon as the reset state is cleared
Low
Interrupt When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling in
progress is completed
3.2 Reset
3.2.1 Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the on-
chip peripheral modules are initialized.
3.2.2 Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
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When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence starting from RES input.
See section 14.3.1, Power-On Reset Circuit.
Vector fetch
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
RES
Internal
processing
Program initial
instruction prefetch
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
(2) (3)
(2)
(1)
Reset cleared
Figure 3.1 Reset Sequence
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3.2.3 Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction
should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
3.3 Interrupts
3.3.1 Overview
The interrupt sources include 13 external interrupts (WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0,
IRQAEC) and 9 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt
sources, their priorities, and their vector addresses. When more than one interrupt is requested, the
interrupt with the highest priority is processed.
The interrupts have the following features:
• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
• IRQ4, IRQ3, IRQ1, IRQ0, and WKP7 to WKP0 can be set to either rising edge sensing or falling
edge sensing, and IRQAEC can be set to either rising edge sensing, falling edge sensing, or
both edge sensing.
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Table 3.2 Interrupt Sources and Their Priorities
Interrupt Source Interrupt Vector Number Vector Address Priority
RES
Watchdog timer
Reset 0 H'0000 to H'0001 High
IRQ0
LVDI
IRQ0
Low-voltage detect interrupt
4 H'0008 to H'0009
IRQ1 IRQ1 5 H'000A to H'000B
IRQAEC IRQAEC 6 H'000C to H'000D
IRQ3 IRQ3 7 H'000E to H'000F
IRQ4 IRQ4 8 H'0010 to H'0011
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
9 H'0012 to H'0013
Timer A Timer A overflow 11 H'0016 to H'0017
Asynchronous
event counter
Asynchronous event
counter overflow
12 H'0018 to H'0019
Timer C Timer C overflow or underflow 13 H'001A to H'001B
Timer FL Timer FL compare match
Timer FL overflow
14 H'001C to H'001D
Timer FH Timer FH compare match
Timer FH overflow
15 H'001E to H'001F
Timer G Timer G input capture
Timer G overflow
16 H'0020 to H'0021
SCI3 SCI3 transmit end
SCI3 transmit data empty
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
18 H'0024 to H'0025
A/D A/D conversion end 19 H'0026 to H'0027
(SLEEP instruction
executed)
Direct transfer 20 H'0028 to H'0029 Low
Notes: Vector addresses H'0002 to H'0007, H'0014 to H'0015, and H'0022 to H'0023 are reserved
and cannot be used.
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3.3.2 Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name Abbreviation R/W Initial Value Address
IRQ edge select register IEGR R/W — H'FFF2
Interrupt enable register 1 IENR1 R/W — H'FFF3
Interrupt enable register 2 IENR2 R/W — H'FFF4
Interrupt request register 1 IRR1 R/W* — H'FFF6
Interrupt request register 2 IRR2 R/W* — H'FFF7
Wakeup interrupt request register IWPR R/W* H'00 H'FFF9
Wakeup edge select register WEGR R/W H'00 H'FF90
Note: * Write is enabled only for writing of 0 to clear a flag.
(1) IRQ Edge Select Register (IEGR)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
IEG4
0
R/W
3
IEG3
0
R/W
0
IEG0
0
R/W
2
W
1
IEG1
0
R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ4, IRQ3, IRQ1, and IRQ0 are
set to rising edge sensing or falling edge sensing. For the IRQAEC pin edge sensing
specifications, see section 9.7, Asynchronous Event Counter (AEC).
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
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Bit 4—IRQ4 Edge Select (IEG4)
Bit 4 selects the input sensing of the IRQ4 pin and ADTRG pin.
Bit 4
IEG4
Description
0 Falling edge of IRQ4 and ADTRG pin input is detected (initial value)
1 Rising edge of IRQ4 and ADTRG pin input is detected
Bit 3—IRQ3 Edge Select (IEG3)
Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin.
Bit 3
IEG3
Description
0 Falling edge of IRQ3 and TMIF pin input is detected (initial value)
1 Rising edge of IRQ3 and TMIF pin input is detected
Bit 2—Reserved
Bit 2 is reserved: it can only be written with 0.
Bit 1—IRQ1 Edge Select (IEG1)
Bit 1 selects the input sensing of the IRQ1 pin and TMIC pin.
Bit 1
IEG1
Description
0 Falling edge of IRQ1 and TMIC pin input is detected (initial value)
1 Rising edge of IRQ1 and TMIC pin input is detected
Bit 0—IRQ0 Edge Select (IEG0)
Bit 0 selects the input sensing of pin IRQ0.
Bit 0
IEG0
Description
0 Falling edge of IRQ0 pin input is detected (initial value)
1 Rising edge of IRQ0 pin input is detected
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(2) Interrupt Enable Register 1 (IENR1)
Bit
Initial value
Read/Write
7
IENTA
0
R/W
6
W
5
IENWP
0
R/W
4
IEN4
0
R/W
3
IEN3
0
R/W
0
IEN0
0
R/W
2
IENEC2
0
R/W
1
IEN1
0
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Timer A Interrupt Enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
Description
0 Disables timer A interrupt requests (initial value)
1 Enables timer A interrupt requests
Bit 6—Reserved
Bit 6 is reserved: it can only be written with 0.
Bit 5—Wakeup Interrupt Enable (IENWP)
Bit 5 enables or disables WKP7 to WKP0 interrupt requests.
Bit 5
IENWP
Description
0 Disables WKP7 to WKP0 interrupt requests (initial value)
1 Enables WKP7 to WKP0 interrupt requests
Bits 4 and 3—IRQ4 and IRQ3 Interrupt Enable (IEN4 and IEN3)
Bits 4 and 3 enable or disable IRQ4 and IRQ3 interrupt requests.
Bit n
IENn
Description
0 Disables interrupt requests from pin IRQn (initial value)
1 Enables interrupt requests from pin IRQn
(n = 4 or 3)
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Bit 2—IRQAEC Interrupt Enable (IENEC2)
Bit 2 enables or disables IRQAEC interrupt requests.
Bit 2
IENEC2
Description
0 Disables IRQAEC interrupt requests (initial value)
1 Enables IRQAEC interrupt requests
Bits 1 and 0—IRQ1 and IRQ0 Interrupt Enable (IEN1 and IEN0)
Bits 1 and 0 enable or disable IRQ1 and IRQ0 interrupt requests.
Bit n
IENn
Description
0 Disables interrupt requests from pin IRQn (initial value)
1 Enables interrupt requests from pin IRQn
(n = 1 or 0)
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(3) Interrupt Enable Register 2 (IENR2)
Bit
Initial value
Read/Write
7
IENDT
0
R/W
6
IENAD
0
R/W
5
—
—
W
4
IENTG
0
R/W
3
IENTFH
0
R/W
0
IENEC
0
R/W
2
IENTFL
0
R/W
1
IENTC
0
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
Description
0 Disables direct transfer interrupt requests (initial value)
1 Enables direct transfer interrupt requests
Bit 6—A/D Converter Interrupt Enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
Description
0 Disables A/D converter interrupt requests (initial value)
1 Enables A/D converter interrupt requests
Bit 5—Reserved
Bit 5 is reserved bit: it can only be written with 0.
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Bit 4—Timer G Interrupt Enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
Description
0 Disables timer G interrupt requests (initial value)
1 Enables timer G interrupt requests
Bit 3—Timer FH Interrupt Enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0 Disables timer FH interrupt requests (initial value)
1 Enables timer FH interrupt requests
Bit 2—Timer FL Interrupt Enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0 Disables timer FL interrupt requests (initial value)
1 Enables timer FL interrupt requests
Bit 1—Timer C Interrupt Enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
Description
0 Disables timer C interrupt requests (initial value)
1 Enables timer C interrupt requests
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Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
Description
0 Disables asynchronous event counter interrupt requests (initial value)
1 Enables asynchronous event counter interrupt requests
For details of SCI3 interrupt control, see section 10.2.6, Serial control register 3 (SCR3).
(4) Interrupt Request Register 1 (IRR1)
Bit
Initial value
Read/Write
7
IRRTA
0
R/(W)*
6
W
5
1
4
IRRI4
0
R/(W)*
3
IRRI3
0
R/(W)*
0
IRRI0
0
R/(W)*
2
IRREC2
0
R/(W)*
1
IRRI1
0
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC, IRQ4, IRQ3, IRQ1, or IRQ0 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7—Timer A Interrupt Request Flag (IRRTA)
Bit 7
IRRTA
Description
0 Clearing conditions: (initial value)
When IRRTA = 1, it is cleared by writing 0
1 Setting conditions:
When the timer A counter value overflows
Bit 6—Reserved
Bit 6 is reserved; it can only be written with 0.
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Bit 5—Reserved
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Bits 4 and 3—IRQ4 and IRQ3 Interrupt Request Flags (IRRI4 and IRRI3)
Bit n
IRRIn
Description
0 Clearing conditions: (initial value)
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
(n = 4 or 3)
Bit 2—IRQAEC Interrupt Request Flag (IRREC2)
Bit 2
IRREC2
Description
0 Clearing conditions: (initial value)
When IRREC2 = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQAEC is designated for interrupt input and the designated signal edge
is input
Bits 1 and 0—IRQ1 and IRQ0 Interrupt Request Flags (IRRI1 and IRRI0)
Bit n
IRRIn
Description
0 Clearing conditions: (initial value)
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQn is designated for interrupt input and the designated signal edge is
input
(n = 1 or 0)
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(5) Interrupt Request Register 2 (IRR2)
Bit
Initial value
Read/Write
7
IRRDT
0
R/(W)*
6
IRRAD
0
R/(W)*
5
W
4
IRRTG
0
R/(W)*
3
IRRTFH
0
R/(W)*
0
IRREC
0
R/(W)*
2
IRRTFL
0
R/(W)*
1
IRRTC
0
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FL, Timer C, or asynchronous event counter
interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7
IRRDT
Description
0 Clearing conditions: (initial value)
When IRRDT = 1, it is cleared by writing 0
1 Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
Bit 6—A/D Convert er Interrupt Request Flag (IRRAD)
Bit 6
IRRAD
Description
0 Clearing conditions: (initial value)
When IRRAD = 1, it is cleared by writing 0
1 Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bit 5—Reserved
Bit 5 is reserved: it can only be written with 0.
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Bit 4—Timer G Interrupt Request Flag (IRRTG)
Bit 4
IRRTG
Description
0 Clearing conditions: (initial value)
When IRRTG = 1, it is cleared by writing 0
1 Setting conditions:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Bit 3—Timer FH Interrupt Request Flag (IRRTFH)
Bit 3
IRRTFH
Description
0 Clearing conditions: (initial value)
When IRRTFH = 1, it is cleared by writing 0
1 Setting conditions:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode
Bit 2—Timer FL Interrupt Request Flag (IRRTFL)
Bit 2
IRRTFL
Description
0 Clearing conditions: (initial value)
When IRRTFL = 1, it is cleared by writing 0
1 Setting conditions:
When TCFL and OCRFL match in 8-bit timer mode
Bit 1—Timer C Interrupt Request Flag (IRRTC)
Bit 1
IRRTC
Description
0 Clearing conditions: (initial value)
When IRRTC = 1, it is cleared by writing 0
1 Setting conditions:
When the timer C counter value overflows or underflows
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Bit 0—Asynchronous Event Counter Interrupt Request Flag (IRREC)
Bit 0
IRREC
Description
0 Clearing conditions: (initial value)
When IRREC = 1, it is cleared by writing 0
1 Setting conditions:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
(6) Wakeup Interrupt Request Regis ter (IWP R)
Bit
Initial value
Read/Write
7
IWPF7
0
R/(W)*
6
IWPF6
0
R/(W)*
5
IWPF5
0
R/(W)*
4
IWPF4
0
R/(W)*
3
IWPF3
0
R/(W)*
0
IWPF0
0
R/(W)*
2
IWPF2
0
R/(W)*
1
IWPF1
0
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the corresponding
interrupt is accepted. Flags must be cleared by writing 0.
Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0)
Bit n
IWPFn
Description
0 Clearing conditions: (initial value)
When IWPFn= 1, it is cleared by writing 0
1 Setting conditions:
When pin WKPn is designated for wakeup input and a rising or falling edge is input
at that pin
(n = 7 to 0)
Section 3 Exception Handling
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(7) Wakeup Edge Select Register (WEGR)
Bit
Initial value
Read/Write
7
WKEGS7
0
R/W
6
WKEGS6
0
R/W
5
WKEGS5
0
R/W
4
WKEGS4
0
R/W
3
WKEGS3
0
R/W
0
WKEGS0
0
R/W
2
WKEGS2
0
R/W
1
WKEGS1
0
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
Bit n—WKPn Edge Select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn
Description
0 WKPn pin falling edge detected (initial value)
1 WKPn pin rising edge detected
(n = 7 to 0)
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3.3.3 External Interrupts
There are 13 external interrupts: WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, and IRQAEC.
(1) Interrupts WKP7 to WKP0
Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to
WKP0. When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a rising
or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the same
vector number, so the interrupt-handling routine must discriminate the interrupt source.
(2) Interrupts IRQ4, IRQ3, IRQ1 and IRQ0
Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins IRQ4, IRQ3, IRQ1,
and IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing,
depending on the settings of bits IEG4, IEG3, IEG1, and IEG0 in IEGR.
When these pins are designated as pins IRQ4, IRQ3, IRQ1, and IRQ0 in port mode register B, 2, and
1 and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an
interrupt. Recognition of these interrupt requests can be disabled individually by clearing bits
IEN4, IEN3, IEN1, and IEN0 to 0 in IENR1. These interrupts can all be masked by setting the I
bit to 1 in CCR.
When IRQ4, IRQ3, IRQ1, and IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in
CCR. Vector numbers 8, 7, 5, and 4 are assigned to interrupts IRQ4, IRQ3, IRQ1, and IRQ0. The
order of priority is from IRQ0 (high) to IRQ4 (low). Table 3.2 gives details.
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(3) IRQAEC Interrupt
The IRQAEC interrupt is requested by an input signal to pin IRQAEC and IECPWM (output of
PWM for AEC). When the IRQAEC input pin is to be used as an external interrupt, set ECPWME
in AEGSR to 0. This interrupt is detected by rising edge, falling edge, or both edge sensing,
depending on the settings of bits AIEGS1 and AIEGS0 in AEGSR.
When bit IENEC2 in IENR1 is 1 and the designated edge is input, the corresponding bit in IRR1 is
set to 1, requesting an interrupt.
When IRQAEC interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 6 is assigned to the IRQAEC interrupt exception handling. Table 3.2 gives details.
3.3.4 Internal Interrupts
There are 9 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 18
and 16 to 11 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts
from on-chip peripheral modules.
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3.3.5 Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Interrupt controller
Priority decision logic
Interrupt
request
CCR (CPU)I
External or
internal
interrupts
External
interrupts or
internal
interrupt
enable
signals
Figure 3.2 Block Diagram of Interrupt Controller
Interrupt operation is described as follows.
• When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2
for a list of interrupt priorities.)
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
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• If the interrupt request is accepted, after processing of the current instruction is completed,
both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in
figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be
executed upon return from interrupt handling.
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
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PC contents saved
CCR contents saved
I← 1
I = 0
Program execution state
No
Yes
Yes
No
[Legend]
PC:
CCR:
I:
Program counter
Condition code register
I bit of CCR
IEN0 = 1 No
Yes
IENDT = 1 No
Yes
IRRDT = 1 No
Yes
Branch to interrupt
handling routine
IRRI0 = 1
No
Yes
IEN1 = 1 No
Yes
IRRI1 = 1
No
Yes
IENEC2 = 1 No
Yes
IRREC2 = 1
Figure 3.3 Flow up to Interrupt Acceptance
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PC and CCR
saved to stack
SP (R7)
SP − 1
SP − 2
SP − 3
SP − 4
Stack area
SP + 4
SP + 3
SP + 2
SP + 1
SP (R7)
Even address
Prior to start of interrupt
exception handling
After completion of interrupt
exception handling
[Legend]
PC
H
:
PC
L
:
CCR:
SP:
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
Notes:
CCR
CCR
PC
H
PC
L
1.
2.
*
PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
Register contents must always be saved and restored by word access,
starting from an even-numbered address.
Ignored on return.
*
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence.
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REJ09B0409-0100
Vector fetch
φ
Internal
address bus
Internal read
signal
Internal write
signal
(2)
Internal data
bus (16 bits)
Interrupt
request
signal
(9)
(1)
Internal
processing
Prefetch instruction of
interrupt-handling routine
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP − 2
(6) SP − 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
(3) (9)(8)(6)(5)
(4) (1) (7) (10)
Stack access
Internal
processing
Instruction
prefetch
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
Figure 3.5 Interrupt Sequence
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3.3.6 Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.
Table 3.4 Interrupt Wait States
Item States Total
Waiting time for completion of executing instruction* 1 to 13 15 to 27
Saving of PC and CCR to stack 4
Vector fetch 2
Instruction fetch 4
Internal processing 4
Note: * Not including EEPMOV instruction.
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3.4 Application Notes
3.4.1 Notes on Stack Area Use
When word data is accessed in the LSI, the least significant bit of the address is regarded as 0.
Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never
indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to
save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
PC
PC
R1L
PC
SP
SP
SP
H'FEFC
H'FEFD
H'FEFF
→
→
→
H
LL
MOV. B R1L, @−R7
SP set to H'FEFF Stack accessed beyond SP
BSR instruction
Contents of PC are lost
H
[Legend]
PCH:
PCL:
R1L:
SP:
Upper byte of program counter
Lower byte of program counter
General register R1L
Stack pointer
Figure 3.6 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
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3.4.2 Notes on Rewri ti ng Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins and when
the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of
IRQAEC, the following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, the interrupt request flag may be set to 1 at
the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear
the interrupt request flag to 0 after switching pin functions. When the value of ECPWME in
AEGSR that sets selection/non-selection of IRQAEC is rewritten, the interrupt request flag may
be set to 1, even if a valid edge has not arrived on the selected IRQAEC or IECPWM (PWM
output for AEC). Therefore, be sure to clear the interrupt request flag to 0 after switching the pin
function. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this
way.
Table 3.5 Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1 Conditions
IRR1 IRRI4 When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit
IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit
IEG4 = 1.
IRRI3 When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit
IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit
IEG3 = 1.
IRREC2
When an edge as designated by AIEGS1 and AIEGS0 in AEGSR is detected
because the values on the IRQAEC pin and of IECPWM at switching are different
(e.g., when the rising edge has been selected and ECPWME in AEGSR is changed
from 1 to 0 while pin IRQAEC is low and IECPWM = 1).
IRRI1 When PMRB bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit
IEG1 = 0.
When PMRB bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit
IEG1 = 1.
IRRI0 When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR bit
IEG0 = 0.
When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR bit
IEG0 = 1.
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Interrupt Request
Flags Set to 1 Conditions
IWPR IWPF7
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low and WEGR bit
WKEGS7 = 0.
When PMR5 bit WKP7 is changed from 1 to 0 while pin WKP7 is low and WEGR bit
WKEGS7 = 1.
IWPF6
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low and WEGR bit
WKEGS6 = 0.
When PMR5 bit WKP6 is changed from 1 to 0 while pin WKP6 is low and WEGR bit
WKEGS6 = 1.
IWPF5
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low and WEGR bit
WKEGS5 = 0.
When PMR5 bit WKP5 is changed from 1 to 0 while pin WKP5 is low and WEGR bit
WKEGS5 = 1.
IWPF4
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low and WEGR bit
WKEGS4 = 0.
When PMR5 bit WKP4 is changed from 1 to 0 while pin WKP4 is low and WEGR bit
WKEGS4 = 1.
IWPF3
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low and WEGR bit
WKEGS3 = 0.
When PMR5 bit WKP3 is changed from 1 to 0 while pin WKP3 is low and WEGR bit
WKEGS3 = 1.
IWPF2
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low and WEGR bit
WKEGS2 = 0.
When PMR5 bit WKP2 is changed from 1 to 0 while pin WKP2 is low and WEGR bit
WKEGS2 = 1.
IWPF1
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low and WEGR bit
WKEGS1 = 0.
When PMR5 bit WKP1 is changed from 1 to 0 while pin WKP1 is low and WEGR bit
WKEGS1 = 1.
IWPF0
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low and WEGR bit
WKEGS0 = 0.
When PMR5 bit WKP0 is changed from 1 to 0 while pin WKP0 is low and WEGR bit
WKEGS0 = 1.
Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
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When switching a pin function, mask the interrupt before setting the bit in the port mode register
(or AEGSR). After accessing the port mode register (or AEGSR), execute at least one instruction
(e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is
executed immediately after the port mode register (or AEGSR) access without executing an
intervening instruction, the flag will not be cleared.
An alternative method is to avoid the setting of interrupt request flag s when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
However, the procedure in Figure 3.7 is recommended because IECPWM is an internal signal and
determining its value is co mplicated.
CCR I bit 1
Set port mode register (or AEGSR) bit
Execute NOP instruction
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
After setting the port mode register
(or AEGSR) bit, first execute at least
one instruction (e.g., NOP), then clear
the interrupt request flag to 0
Interrupt mask cleared
Clear interrupt request flag to 0
←
CCR I bit 0
←
Figure 3.7 Port Mode Register (or AEGSR) Setting and Interrupt Request Flag
Clearing Procedure
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3.4.3 Method for Clearing Interrupt Request Flags
Use the recommended method, given below when clearing the flags of interrupt request registers
(IRR1, IRR2, IWPR).
• Recommended method
Use a single instruction to clear flags. The bit control instruction and byte-size data transfer
instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 of IRR1) are
given below.
BCLR #1, @IRR1:8
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)
• Example of a malfunction
When flags are cleared with multiple instructions, other flags might be cleared during
execution of the instructions, even though they are currently set, and this will cause a
malfunction.
Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1
(bit 1 of IRR1).
MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time
AND.B #B'11111101,R1L ..... Here, IRRI0 = 1
MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0
In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B
instruction is executing.
The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1,
IRRI0 is also cleared.
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Section 4 Clock Pulse Generators
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Section 4 Clock Pulse Generators
4.1 Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
In the H8/38524 Group, the system clock pulse generator includes an on-chip oscillator.
4.1.1 Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators.
System
clock
oscillator
Subclock
oscillator
Subclock
divider
(1/2, 1/4, 1/8)
System
clock
divider
(1/2)
System
clock
divider Prescaler S
(13 bits)
Prescaler W
(5 bits)
OSC
1
Latch
On-chip
oscillator
Internal reset signal (other than watchdog timer or low-voltage detect
circuit reset)
C
DQ
IRQAEC
OSC
2
X
1
X
2
System clock pulse generator
Subclock pulse generator
φ
OSC
(f
OSC
)
R
OSC
φ
W
(f
W
)
φ
W
/2
φ
W
/4 φ
SUB
φ
W
φ/2
to
φ/8192
φ
φ
W
/2
φ
W
/4
φ
W
/8
to
φ
W
/128
φ
W
/8
φ
OSC
/2
φ
OSC
/16
φ
OSC
/32
φ
OSC
/64
φ
OSC
/128
Figure 4.1 Block Diagram of Clock Pulse Generators
Section 4 Clock Pulse Generators
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4.1.2 System Clock and Su bclock
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. Four of
the clock signals have names: φ is the system clock, φSUB is the subclock, φOSC is the oscillator
clock, and φW is the watch clock.
The clock signals available for use by peripheral modules are φ/2, φ/4, φ/8, φ/16, φ/32, φ/64,
φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φW, φW/2, φW/4, φW/8, φW/16, φW/32, φW/64,
and φW/128. The clock requirements differ from one module to another.
4.1.3 Register Descriptions
Table 4.1 lists the registers that control the clock pulse generators.
Table 4.1 Clock Pulse G e nerator Control Registers
Name Abbreviation R/W Initial Value Address
Clock pulse generator control
register
OSCCR R/W — H'FFF5
(1) Clock Pulse Generator Control Register (OSCCR)
Bit 7 6 5 4 3 2 1 0
SUBSTP — — — — IRQAECF OSCF —
Initial value 0 0 0 0 0 — — 0
Read/Write R/W R R/W R/W R/W R R R/W
OSCCR is an 8-bit read/write register that contains the flag indicating the selection of system
clock oscillator or on-chip oscillator, indicates the input level of the IRQAEC pin during resets,
and controls whether the subclock oscillator operates or not.
Bit 7—Subclock Oscillator Stop Control (SUBSTP)
Bit 7 controls whether the subclock oscillator operates or not. It can be set to 1 only in the active
mode (high-speed/medium-speed). Setting bit 7 to 1 in the subactive mode will cause the LSI to
stop operating.
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Rev. 1.00 Dec. 19, 2007 Page 87 of 520
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Bit 7
SUBSTP
Description
0 Subclock oscillator operates (initial value)
1 Subclock oscillator stopped
Bit 6—Reserved
This bit is reserved. It is always read as 0 and cannot be written to.
Bits 5 to 3—Reserved
These bits are read/write enabled reserved bits.
Bit 2—IRQAEC Flag (IRQAECF)
This bit indicates the IRQAEC pin input level set during resets.
Bit 2
IRQAECF
Description
0 IRQAEC pin set to GND during resets
1 IRQAEC pin set to VCC during resets
Bit 1—OSC Flag (OSCF)
This bit indicates the oscillator operating with the system clock pulse generator.
Bit 1
OSCF
Description
0 System clock oscillator operating (on-chip oscillator stopped)
1 On-chip oscillator operating (system clock oscillator stopped)
Bit 0—Reserved
This bit is reserved. Never write 1 to this bit, as it can cause the LSI to malfunction.
Section 4 Clock Pulse Generators
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4.2 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input. As shown in figure 4.1, the selection between a
system clock oscillator and an on-chip oscillator is supported. See section 4.2 (5), On-Chip
Oscillator Selection Method, for information on selecting the on-chip oscillator.
(1) Connecting a Crystal Oscillator
Figure 4.2 shows a typical method of connecting a crystal oscillator.
OSC
1
OSC
2
Frequency Crystal
oscillator
C
1
, C
2
Recommendation
value
Products
name
C
1
C
2
R
f
R = 1 M ±20%
f
Ω
4.0 MHz NDK NR-18 12 pF ±20%
Note: Circuit constants should be determined in consultation
with the resonator manufacturer.
Figure 4.2 Typical Connecti on to Cryst a l Oscill ator
Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
characteristics given in table 4.2 should be used.
CS
C0
RS
OSC1OSC2
LS
Figure 4.3 Equivalent Circ ui t of Crystal Oscillator
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 89 of 520
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Table 4.2 Crystal Oscillator Parameters
Frequency (MHz) 4 4.193
RS max (Ω) 100 100
C0 max (pF) 16 16
(2) Connecting a Ceramic Oscillator
Figure 4.4 shows a typical method of connecting a ceramic oscillator.
Frequency
2.0 MHz
10.0 MHz
16.0 MHz
20.0 MHz
Murata
Ceramic
oscillator Products name
Ceramic oscillator
R
f
= 1 MΩ ±20%
OSC
1
OSC
2
R
f
C
1
C
2
CSTCC2M00G53-B0
CSTCC2M00G56-B0
CSTLS10M0G53-B0
CSTLS10M0G56-B0
CSTLS16M0X53-B0
CSTLS20M0X53-B0
15 pF ±20%
47 pF ±20%
15 pF ±20%
47 pF ±20%
15 pF ±20%
15 pF ±20%
C1, C2
Recommendation
value
Notes: Circuit constants should be determined in consultation
with the resonator manufacturer.
Figure 4.4 Typical Connection to Ceramic Oscillator
Section 4 Clock Pulse Generators
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(3) Notes on Board Design
When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention
to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4.5.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1 and OSC2.
OSC
OSC
C
1
C
2
Signal A Signal B
2
1
To be avoided ××
Figure 4.5 Board Design o f Oscill a tor Circuit
Note: The circuit parameters above are recommended by the crystal or ceramic oscillator
manufacturer.
The circuit parameters are affected by the crystal or ceramic oscillator and floating
capacitance when designing the board. When using the oscillator, consult with the crystal
or ceramic oscillator manufacturer to determine the circuit parameters.
Section 4 Clock Pulse Generators
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(4) External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.6 shows a typical
connection.
OSC
1
OSC
2
External clock input
Open
Figure 4.6 External Clock Input (Example)
Frequency Oscillator Clock (φOSC)
Duty cycle 45% to 55%
(5) On-Chip Oscillator Selection Method
The on-chip oscillator is selected by setting the IRQAEC pin input level during resets.* Table 4.3
lists the methods for selecting the system clock oscillator and the on-chip oscillator. The IRQAEC
pin input level set during resets must be fixed at VCC or GND, based on the oscillator to be
selected. It is not necessary to connect an oscillator to pins OSC1 and OSC2 if the on-chip
oscillator is selected. In this case, pin OSC1 should be fixed at VCC or GND.
Note: The system clock oscillator must be selected in order to program or erase flash memory as
part of operations such as on-board programming. Also, when using the on-chip emulator,
an oscillator should be connected, or an external clock input, even if the on-chip oscillator
is selected.
* Other than watchdog timer or low-voltage detect circuit reset.
Table 4.3 System Clock Oscillator and On-Chip Oscillator Selection Methods
IRQAEC pin input level (during resets) 0 1
System clock oscillator Enabled Disabled
On-chip oscillator Disabled Enabled
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 92 of 520
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4.3 Subclock Generator
(1) Connecting a 32.768 kHz Crystal Oscillator
Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz crystal
oscillator, as shown in figure 4.7. Follow the same precautions as noted under 3. notes on board
design for the system clock in section 4.2.
X
X
C
1
C
2
1
2
C = C = 7 pF (typ.)
1 2
Frequency
32.768 kHz
Manufacturer
Epson Toyocom
Products Name
C-001
Equivalent Series Resistance
35 kΩ max
Note: Consult with the crystal resonator manufacturer
to determine the circuit constants.
Figure 4.7 Typical Connecti on to 32.7 6 8 kHz Cryst al Osci l l ator (Su bcl ock)
Figure 4.8 shows the equivalent circuit of the 32.768 kHz crystal oscillator.
CS
C0
LR
S
X1X2
C = 1.5 pF typ
R = 14 k typ
f = 32.768 kHz
0
S
W
Ω
S
Figure 4.8 Equivalent Circuit of 32.768 kHz Crystal Oscillator
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 93 of 520
REJ09B0409-0100
When using a resonator other than the above, ensure optimal conditions by conducting sufficient
evaluation of consistency in cooperation with the manufacturer of the resonator. Even if the above
resonators or products equivalent to them are implemented, their oscillation characteristics are
affected by the board design. Be sure to use the actual board to evaluate consistency as a system.
The consistency as a system has to be verified not only in a reset state (i.e., the RES pin is driven
low) but also in a state where a reset state has been exited (i.e., the low-level RES signal has been
driven high).
(2) Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure
4.9.
X
X
1
2
GND
Open
Figure 4.9 Pin Connection when not Using Subclock
(3) Method for Disabling Subclock Oscillator
The subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR
register to 1. The register setting to disable the subclock oscillator should be made in the active
mode. When restoring operation of the subclock oscillator after it has been disabled using the
OSCCR register, it is necessary to wait for the oscillation stabilization time (typ: 8s) to elapse
before using the subclock.
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 94 of 520
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4.4 Prescalers
This LSI is equipped with two on-chip prescalers having different input clocks (prescaler S and
prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. Its
prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a
5-bit counter using a 32.768 kHz signal divided by 4 (φW/4) as its input clock. Its prescaled outputs
are used by timer A as a time base for timekeeping.
(1) Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI3, the A/D
converter, the LCD controller, watchdog timer, and the 10-bit PWM. The divider ratio can be set
separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is φosc/16, φosc/32, φosc/64, or
φosc/128.
(2) Prescaler W (PSW)
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (φW/4) as its input clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins X1 and X2.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 95 of 520
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4.5 Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Oscillator circuit constants will differ
depending on the oscillator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the oscillator element
manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding
its maximum rating.
(Vss)
P17
X1
X2
Vss
OSC2
OSC1
TEST
Figure 4.10 Example of Cr yst al and Ceramic Oscillator Element Arrangement
Figure 4.11 (1) shows an example measuring circuit with the negative resistance suggested by the
resonator manufacturer. Note that if the negative resistance of the circuit is less than that
suggested by the resonator manufacturer, it may be difficult to start the main oscillator.
If it is determined that oscillation is not occurring because the negative resistance is lower than the
level suggested by the resonator manufacturer, the circuit may be modified as shown in figure 4.11
(2) through (4). Which of the modification suggestions to use and the capacitor capacitance should
be decided based upon an evaluation of factors such as the negative resistance and the frequency
deviation.
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 96 of 520
REJ09B0409-0100
(1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1
(3) Oscillator Circuit Modification Suggestion 2 (4) Oscillator Circuit Modification Suggestion 3
C3
OSC1
OSC2
Rf
C1
C2
Negative resistance,
addition of −R
OSC1
OSC2
Rf
C1
C2
Modification
point
Modification
point
Modification
point
OSC1
OSC2
Rf
C1
C2
OSC1
OSC2
Rf
C1
C2
Figure 4.11 Negative Resistance Measurement and Circuit Modification Suggesti ons
4.5.1 Definition of Oscillation Stabilization Wait Time
Figure 4.12 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator.
As shown in figure 4.12, as the system clock oscillator is halted in standby mode, watch mode,
and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the
sum of the following two times (oscillation stabilization time and wait time) is required.
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 97 of 520
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1. Oscillation stabilization time (trc)
The time from the point at which the system clock oscillator oscillation waveform starts to change
when an interrupt is generated, until the amplitude of the oscillation waveform increases and the
oscillation frequency stabilizes.
2. Wait time
The time required for the CPU and peripheral functions to begin operating after the oscillation
waveform frequency and system clock have stabilized.
The wait time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in
system control register 1 (SYSCR1)).
Oscillation
waveform
(OSC2)
System clock
(φ)
Oscillation
stabilization
time
Operating
mode
Standby mode,
watch mode,
or subactive
mode
Wait time
Oscillation stabilization wait time Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
Figure 4.12 Oscillation Stabilization Wait Time
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 98 of 520
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When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a
transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to
change at the point at which the interrupt is accepted. Therefore, when an oscillator element is
connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is
halted, the time from the point at which this oscillation waveform starts to change until the
amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is,
the oscillation stabilization time—is required.
The oscillation stabilization time in the case of these state transitions is the same as the oscillation
stabilization time at power-on (the time from the point at which the power supply voltage reaches
the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time trc"
in the AC characteristics.
Meanwhile, once the system clock has halted, a wait time of at least 8 states is necessary in order
for the CPU and peripheral functions to operate normally.
Thus, the time required from interrupt generation until operation of the CPU and peripheral
functions is the sum of the above described oscillation stabilization time and wait time. This total
time is called the oscillation stabilization wait time, and is expressed by equation (1) below.
Oscillation stabilization wait time = oscillation stabilization time + wait time
= trc + (8 to 131,072 states) ................. (1)
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator, careful evaluation must be carried out on the installation circuit before deciding on the
oscillation stabilization wait time. In particular, since the oscillation stabilization time is affected
by installation circuit constants, stray capacitance, and so forth, suitable constants should be
determined in consultation with the oscillator element manufacturer.
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 99 of 520
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4.5.2 Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual crystal oscillator element
characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after
the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by
fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted,
leading to an unstable system clock and erroneous operation of the microcomputer.
If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer wait time.
For example, if erroneous operation occurs with a wait time setting of 16 states, check the
operation with a wait time setting of 8,192 states or more.
If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
4.6 Usage Note
When using the on-chip emulator, system clock precision is necessary for programming or erasing
the flash memory. However, the on-chip oscillator frequency can vary due to changes in
conditions such as voltage or temperature. Consequently, even if the on-chip oscillator is selected
when using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator, or an
external clock should be supplied. In this case, the LSI uses the on-chip oscillator when user
programs are being executed and the system clock oscillator when programming or erasing flash
memory. The process is controlled by the on-chip emulator.
Section 4 Clock Pulse Generators
Rev. 1.00 Dec. 19, 2007 Page 100 of 520
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Section 5 Power-Down Modes
Rev. 1.00 Dec. 19, 2007 Page 101 of 520
REJ09B0409-0100
Section 5 Power-Down Modes
5.1 Overview
The LSI has nine modes of operation after a reset. These include eight power-down modes, in
which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating
modes.
Table 5.1 Operating Modes
Operating Mode Description
Active (high-speed) mode The CPU and all on-chip peripheral functions are operable on
the system clock in high-speed operation
Active (medium-speed) mode The CPU and all on-chip peripheral functions are operable on
the system clock in low-speed operation
Subactive mode The CPU and all on-chip peripheral functions are operable on
the subclock in low-speed operation
Sleep (high-speed) mode The CPU halts. On-chip peripheral functions are operable on
the system clock
Sleep (medium-speed) mode The CPU halts. On-chip peripheral functions operate at a
frequency of 1/128, 1/64, 1/32, or 1/16 of the system clock
frequency
Subsleep mode The CPU halts. The time-base function of timer A, timer C,
timer F, timer G, SCI3, AEC, and LCD controller/driver are
operable on the subclock
Watch mode The CPU halts. The time-base function of timer A, timer F,
timer G, AEC and LCD controller/driver are operable on the
subclock
Standby mode The CPU and all on-chip peripheral functions halt
Module standby mode Individual on-chip peripheral functions specified by software
enter standby mode and halt
Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode.
Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal
states in each mode.
Section 5 Power-Down Modes
Rev. 1.00 Dec. 19, 2007 Page 102 of 520
REJ09B0409-0100
Program
halt state
SLEEP
instruction
*e
SLEEP
instruction
*c
SLEEP
instruction
*h
SLEEP
instruction
*i
SLEEP
instruction
*g
SLEEP
instruction
*f
Program
execution state
SLEEP
instruction
*a
Program
halt state
SLEEP
instruction
*i
Power-down modes
A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupts are enabled.
Details on the mode transition conditions are given in the explanations of each mode,
in sections 5.2 to 5.8.
Notes: 1.
2.
Mode Transition Conditions (1)
*a
*b
*c
*d
*e
*f
*g
*h
*i
*j
LSON MSON SSBY DTON
0
0
1
0
*
0
0
0
1
0
0
1
*
*
*
0
1
1
*
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
1
1
1
1
1
*: Don't care
Mode Transition Conditions (2)
*1
Interrupt Sources
Timer A, Timer F, Timer G interrupt, IRQ0 interrupt,
WKP7 to WKP0 interrupts
Timer A, Timer C, Timer F, Timer G, SCI3 interrupt,
IRQ4, IRQ3, IRQ1 and IRQ0 interrupts, IRQAEC,
WKP7 to WKP0 interrupts, AEC
All interrupts
IRQ1 or IRQ0 interrupt, WKP7 to WKP0 interrupts
*2
*3
*4
*3
*3
*2*1
*4
*4
*1
Standby
mode
Watch
mode
Subactive
mode
Active
(medium-speed)
mode
Active
(high-speed)
mode
Sleep
(high-speed)
mode
Sleep
(medium-speed)
mode
Subsleep
mode
SLEEP
instruction*
a
SLEEP
instruction
*e
SLEEP
instruction
*d
SLEEP
instruction
*b
SLEEP
instruction
*j
*1
SLEEP
instruction
*e
SLEEP
instruction*b
TMA3
*
*
1
0
1
*
*
1
1
1
SLEEP
instruction
*d
Reset state
Figure 5.1 Mode Transiti o n Diagram
Section 5 Power-Down Modes
Rev. 1.00 Dec. 19, 2007 Page 103 of 520
REJ09B0409-0100
Table 5.2 Internal State in Each Operating Mode
Active Mode Sleep Mode
Function High-
Speed Medium-
Speed High-
Speed Medium-
Speed Watch
Mode Subactive
Mode Subsleep
Mode Standby
Mode
System clock oscillator Functions Functions Functions Functions Halted Halted Halted Halted
Subclock oscillator Functions Functions Functions Functions Functions Functions Functions Functions
Instructions Functions Functions Halted Halted Halted Functions Halted Halted
CPU
operations RAM Retained Retained Retained Retained Retained
Registers
I/O ports Retained*1
IRQ0 Functions Functions Functions Functions Functions Functions Functions Functions
External
interrupts IRQ1 Retained
*6
IRQAEC Retained
*6
IRQ3
IRQ4
WKP0 Functions Functions Functions Functions Functions Functions Functions Functions
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Timer A Functions Functions Functions Functions Functions*5Functions*5Functions*5 Retained
Peripheral
functions Asynchronous
event counter
Functions*8Functions Functions Functions*8
Timer C Retained
Functions/
Retained*2
Functions/
Retained*2
Retained
WDT Functions/
Retained*10
Functions/
Retained*7
Functions/
Retained*10
Functions/
Retained*11
Timer F
Timer G
Functions/
Retained*9
Functions/
Retained*9
Functions/
Retained*9
Retained
SCI3 Reset
Functions/
Retained*3
Functions/
Retained*3
Reset
PWM Retained Retained Retained Retained
A/D converter Retained Retained Retained Retained
LCD Functions/
Retained*4
Functions/
Retained*4
Functions/
Retained*4
Retained
LVD Functions Functions Functions Functions Functions Functions Functions Functions
Notes: 1. Register contents are retained, but output is high-impedance state.
2. Functions if an external clock or the φW/4 internal clock is selected; otherwise halted and retained.
3. Functions if φW/2 is selected as the internal clock; otherwise halted and retained.
4. Functions if φW, φW/2 or φW/4 is selected as the operating clock; otherwise halted and retained.
5. Functions if the timekeeping time-base function is selected.
6. External interrupt requests are ignored. Interrupt request register contents are not altered.
7. Operates when φW/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and
stands by.
8. Incrementing is possible, but interrupt generation is not.
9. Functions if φW/4 is selected as the internal clock; otherwise halted and retained.
10. Operates when φW/32 is selected as the internal clock or the on-chip oscillator is selected; otherwise stops and
stands by.
11. Operates only when the on-chip oscillator is selected; otherwise stops and stands by.
Section 5 Power-Down Modes
Rev. 1.00 Dec. 19, 2007 Page 104 of 520
REJ09B0409-0100
5.1.1 System Control Registers
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3 System Control Registers
Name Abbreviation R/W Initial Value Address
System control register 1 SYSCR1 R/W H'07 H'FFF0
System control register 2 SYSCR2 R/W H'F0 H'FFF1
(1) System Control Register 1 (SYSCR1)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
LSON
0
R/W
0
MA0
1
R/W
2
1
1
MA1
1
R/W
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'07.
Bit 7—Software Standby (SSBY)
This bit designates transition to standby mode or watch mode.
Bit 7
SSBY
Description
0 • When a SLEEP instruction is executed in active mode, (initial value)
a transition is made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode
1 • When a SLEEP instruction is executed in active mode, a transition is made to
standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode
Section 5 Power-Down Modes
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Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the operating frequency so that the waiting time is at least equal to
the oscillation stabilization time.
Bit 6
STS2 Bit 5
STS1 Bit 4
STS0
Description
0 0 0 Wait time = 8,192 states (initial value)
0 0 1 Wait time = 16,384 states
0 1 0 Wait time = 32,768 states
0 1 1 Wait time = 65,536 states
1 0 0 Wait time = 131,072 states
1 0 1 Wait time = 2 states (External clock input mode)
1 1 0 Wait time = 8 states
1 1 1 Wait time = 16 states
Note: If an external clock is being input, set standby timer select to external clock mode before
mode transition. Also, do not set standby timer select to external clock mode if no external
clock is used. 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip
oscillator is used.
Bit 3—Low Speed on Flag (LSON)
This bit chooses the system clock (φ) or subclock (φSUB) as the CPU operating clock when watch
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
Description
0 The CPU operates on the system clock (φ) (initial value)
1 The CPU operates on the subclock (φSUB)
Bit 2—Reserved
Bit 2 is reserved: it is always read as 1 and cannot be modified.
Section 5 Power-Down Modes
Rev. 1.00 Dec. 19, 2007 Page 106 of 520
REJ09B0409-0100
Bits 1 and 0—Active (Medium-Speed) Mode Clock Select (MA1, MA0)
Bits 1 and 0 choose φosc/128, φosc/64, φosc/32, or φosc/16 as the operating clock in active (medium-
speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in active (high-
speed) mode or subactive mode.
Bit 1
MA1 Bit 0
MA0
Description
0 0 φosc/16
0 1 φosc/32
1 0 φosc/64
1 1 φosc/128 (initial value)
(2) System Control Register 2 (SYSCR2)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
NESEL
1
R/W
3
DTON
0
R/W
0
SA0
0
R/W
2
MSON
0
R/W
1
SA1
0
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5—Reserved
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4—Noise Elimination Sampling Frequency Select (NESEL)
This bit selects the frequency at which the watch clock signal (φW) generated by the subclock pulse
generator is sampled, in relation to the oscillator clock (φOSC) generated by the system clock pulse
generator. When φOSC = 2 to 20 MHz, clear NESEL to 0.
Bit 4
NESEL
Description
0 Sampling rate is φOSC/16
1 Sampling rate is φOSC/4 (initial value)
Section 5 Power-Down Modes
Rev. 1.00 Dec. 19, 2007 Page 107 of 520
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Bit 3—Direct Transfer on Flag (DTON)
This bit designates whether or not to make direct transitions among active (high-speed), active
(medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which
the transition is made after the SLEEP instruction is executed depends on a combination of other
control bits.
Bit 3
DTON
Description
0 • When a SLEEP instruction is executed in active mode, (initial value)
a transition is made to standby mode, watch mode, or sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode or subsleep mode
1 • When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON =
0, and MSON = 1
Bit 2—Medium Speed on Flag (MSON)
After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active
(medium-speed) mode.
Bit 2
MSON
Description
0 Operation in active (high-speed) mode (initial value)
1 Operation in active (medium-speed) mode
Section 5 Power-Down Modes
Rev. 1.00 Dec. 19, 2007 Page 108 of 520
REJ09B0409-0100
Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0)
These bits select the CPU clock rate (φW/2, φW/4, or φW/8) in subactive mode. SA1 and SA0 cannot
be modified in subactive mode.
Bit 1
SA1 Bit 0
SA0
Description
0 0 φW/8 (initial value)
0 1 φW/4
1 * φW/2
*: Don’t care
5.2 Sleep Mode
5.2.1 Transition to Sl eep Mode
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON
bits in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction
is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in
SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed)
mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral
functions are operational. The clock frequency in sleep (medium-speed) mode is determined
by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.
Section 5 Power-Down Modes
Rev. 1.00 Dec. 19, 2007 Page 109 of 520
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5.2.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, SCI3, A/D converter), or by input at
the RES pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φ(s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
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5.3 Standby Mode
5.3.1 Transiti on to St andby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip
peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O
ports go to the high-impedance state.
5.3.2 Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ1 or IRQ0), WKP7 to WKP0 or by input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in
bits STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the
entire chip, standby mode is cleared, and interrupt exception handling starts. Operation
resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed)
mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
• Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse
generator output stabilizes.
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5.3.3 Oscillato r Stabilization Time after Standby Mode is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
• When an oscillator is used
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
wait time at least as long as the oscillation stabilization time.
Table 5.4 Clock Frequency and Stabilizat ion Time
(Unit: ms)
STS2 STS1 STS0 Wait Time 5 MHz 2 MHz
0 0 0 8,192 states 1.638 4.1
1 16,384 states 3.277 8.2
1 0 32,768 states 6.554 16.4
1 65,536 states 13.108 32.8
1 0 0 131,072 states 26.216 65.5
1 2 states
(Use prohibited with other than
external clock)
0.0004 0.001
1 0 8 states 0.002 0.004
1 16 states 0.003 0.008
• When an external clock is used
STS2 = 1, STS1 = 0, and STS0 = 1 should be set. Other values possible use, but CPU
sometimes will start operation before wait time completion.
• When the on-chip oscillator is used
8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used.
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5.3.4 Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the high-
impedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows
the timing in this case.
SLEEP instruction fetch Internal data bus Fetch of next instruction
Port outputPins High-impedance
Active (high-speed) mode or active (medium-speed) mode Standby mode
SLEEP instruction execution Internal processing
φ
Figure 5.2 Standby Mode T r ansi tion and Pin States
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5.3.5 Notes on External Input Signal Changes before/after Standby Mode
1. When external input signal changes before/after standby mode or watch mode
When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB
(referred to together in this section as the internal clock). As the internal clock stops in standby
mode and watch mode, the width of external input signals requires careful attention when a
transition is made via these operating modes. Ensure that external input signals conform to the
conditions stated in 3, Recommended timing of external input signals, below
2. When external input signals cannot be captured because internal clock stops
The case of falling edge capture is illustrated in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active (high-speed or medium-speed) mode or subactive
mode, after oscillation is started by an interrupt via a different signal, the external input signal
cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc.
3. Recommended timing of external input signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch
mode, as shown in “Capture possible: case 1” in figure 5.3.
External input signal capture is also possible with the timing shown in “Capture possible: case
2” and “Capture possible: case 3” in figure 5.3, in which a 2 tcyc or 2 tsubcyc level width is
secured.
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t
cyc
t
subcyc
Operating
mode
φ or φ
SUB
Capture possible:
case 1
Capture possible:
case 2
Capture possible:
case 3
Capture not
possible
Interrupt by different
signal
External input signal
Active (high-speed,
medium-speed) mode
or subactive mode
Active (high-speed,
medium-speed) mode
or subactive mode
Standby mode
or watch mode
Wait for
oscillation
to settle
t
cyc
t
subcyc
t
cyc
t
subcyc
t
cyc
t
subcyc
Figure 5.3 External Input Signal Capture when Signal Changes before/after
Standby Mode or Watch Mo de
4. Input pins to which these notes apply:
IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, IRQAEC, TMIC, TMIF, TMIG, ADTRG.
5.4 Watch Mode
5.4.1 Transition to Wa tch M ode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F,
timer G, AEC and the LCD controller/driver (for which operation or halting can be set) is halted.
As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip
RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same
states as before the transition.
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5.4.2 Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0) or
by input at the RES pin.
• Clearing by interrupt
When watch mode is cleared by interrupt, the mode to which a transition is made depends on
the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are
cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition
is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the
transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a
stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception
handling starts. Watch mod e is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see Clearing by RES input in section
5.3.2, Clearing Standby Mode.
5.4.3 Oscillato r Stabilization Time after Watch Mode is Cleared
The wait time is the same as for standby mode; see secti o n 5. 3. 3, Osci ll a to r Sta bi l izat i on Ti me
after Standby Mode is Cleared.
5.4.4 Notes on External Input Signal Changes before/after Watch Mode
See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.
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5.5 Subsleep Mode
5.5.1 Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter and PWM is in active state. As long as a minimum required voltage is applied, the
contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules
are retained. I/O ports keep the same states as before the transition.
5.5.2 Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, SCI3, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0) or by a low input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and in terrupt exception handling
starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φSUB(s) delay may
occur after the interrupt request signal occurrence, before the interrupt exception handling
start.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see Clearing by RES input in section
5.3.2, Clearing Standby Mode.
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5.6 Subactive Mode
5.6.1 Transition to Sub active Mode
Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to
WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From sub s leep mode,
subactive mode is entered if a timer A, timer C, timer F, timer G, a synchronous event counter,
SCI3, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, or WKP7 to WKP0 interrupt is requested. A transition to
subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
5.6.2 Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed while th e SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct
Transfer, below.
• Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see Clearing by RES input in section
5.3.2, Clearing Standby Mode.
5.6.3 Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are φW/2, φW/4, and φW/8.
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5.7 Active (Medium-Speed) Mode
5.7.1 Transition to Active (Medium-Speed) Mo de
If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ0, IRQ1 or WKP7 to WKP0 interrupts in standby
mode, timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupts in watch mode, or any
interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I bit
of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register.
Furthermore, it sometimes acts with half state early timing at the time of transition to active
(medium-speed) mode.
5.7.2 Clearing Active (Medium-Speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction.
• Clearing by SLEEP instruction
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY
bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA
is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit
TMA3 in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also
possible. See section 5.8, Direct Transfer, below for details.
• Clearing by RES pin
When the RES pin is driven low, a transition is made to the reset state and active (medium-
speed) mode is cleared.
5.7.3 Operating Frequency in Active (Medium-Speed) Mode
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
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5.8 Direct Transfer
5.8.1 Overview of Direct Transfer
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is
made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I
bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear
the resulting mode by means of an interrupt.
• Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the
DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep
mode.
• Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0,
the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits
STS2 to STS0 has elapsed.
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• Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the
DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1
bits STS2 to STS0 has elapsed.
5.8.2 Direct Transition Times
1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode
A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both
cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from
execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition
time) is given by equation (1) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (1)
Example: Direct transition time = (2 + 1) × 2tosc + 14 × 16tosc = 230tosc (when φ/8 is selected
as the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
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2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode
A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by
executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are
both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
The time from execution of the SLEEP instruction to the end of interrupt exception handling (the
direct transition time) is given by equation (2) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (2)
Example: Direct transition time = (2 + 1) × 16tosc + 14 × 2tosc = 76tosc (when φ/8 is selected as
the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition) ........................ (3)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when
φw/8 is selected as the CPU operating clock, and wait time = 8192 states)
[Legend]
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
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4. Time for direct transition from subactive mode to active (medium-speed) mode
A direct transition from subactive mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is
cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set
to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (4) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition) ........................ (4)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc
(when φw/8 or φ/8 is selected as the CPU operating clock, and wait time = 8192 states)
[Legend]
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
5.8.3 Notes on External Input Signal Changes before/after Direct Transition
1. Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
2. Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
3. Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
4. Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
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5.9 Module Standby Mode
5.9.1 Setting Module Standby Mode
Module standby mode is set for individual peripheral functions. All the on-chip peripheral
modules can be placed in module standby mode. When a module enters module standby mode, the
system clock supply to the module is stopped and operation of the module halts. This state is
identical to standby mode.
Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock
stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
5.9.2 Clearing Mod ul e Stan db y Mode
Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in
clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
Following a reset, clock stop register 1 (CKSTPR1) and clock stop register 2 (CKSTPR2) are both
initialized to H'FF.
Table 5.5 Setting and Clearing Module Standby Mode by Clock Stop Regi s ter
Register Name Bit Name Operation
CKSTPR1 TACKSTP 1 Timer A module standby mode is cleared
0 Timer A is set to module standby mode
TCCKSTP 1 Timer C module standby mode is cleared
0 Timer C is set to module standby mode
TFCKSTP 1 Timer F module standby mode is cleared
0 Timer F is set to module standby mode
TGCKSTP 1 Timer G module standby mode is cleared
0 Timer G is set to module standby mode
ADCKSTP 1 A/D converter module standby mode is cleared
0 A/D converter is set to module standby mode
S32CKSTP 1 SCI3 module standby mode is cleared
0 SCI3 is set to module standby mode
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Register Name Bit Name Operation
CKSTPR2 LDCKSTP 1 LCD module standby mode is cleared
0 LCD is set to module standby mode
PW1CKSTP 1 PWM1 module standby mode is cleared
0 PWM1 is set to module standby mode
WDCKSTP 1 Watchdog timer module standby mode is cleared
0 Watchdog timer is set to module standby mode
AECKSTP 1 Asynchronous event counter module standby mode
is cleared
0 Asynchronous event counter is set to module
standby mode
PW2CKSTP 1 PWM2 module standby mode is cleared
0 PWM2 is set to module standby mode
LVDCKSTP 1 LVD module standby mode is cleared
0 LVD is set to module standby mode
Note: For details of module operation, see the sections on the individual modules.
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Section 6 ROM
6.1 Overview
The H8/38524 has 32 Kbytes of on-chip mask ROM, the H8/38523 has 24 Kbytes, the H8/38522
has 16 Kbytes, the H8/38521 has 12 Kbytes, and the H8/38520 has 8 Kbytes. The ROM is
connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data
and word data. Flash memory versions of the H8/38524 and H8/38522 are available. The former
has 32 Kbytes, and the latter 16 Kbytes, of flash memory.
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6.2 Flash Memory Overview
6.2.1 Features
The features of the 32-Kbyte or 16-Kbyte flash memory built into the flash memory versions are
summarized below.
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. On the HD64F38524, the flash memory is configured as follows: 1 Kbyte × 4 blocks,
28 Kbytes × 1 block. On the HD64F38522, the flash memory is configured as follows: 1
Kbyte × 4 blocks, 12 Kbytes × 1 block. To erase the entire flash memory, each block must
be erased in turn.
Note: The system clock oscillator must be used when programming or erasing the flash
memory.
• Reprogramming capability
The HD64F38524 and HD64F38522 can be reprogrammed up to 1,000 times.
• On-board programming
On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
Flash memory can be programmed/erased in programmer mode using a PROM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
Sets software protection against flash memory programming/erasing.
• Power-down mode
The power supply circuit is partly halted in the subactive mode and can be read in the
power-down mode.
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6.2.2 Block Diagram
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1
Bus interface/controller Operating
mode
TES pin
P95 pin
P34 pin
[Legend]
FLMCR1: Flash memory control register 1
FLMCR2: Flash memory control register 2
EBR: Erase block register
FLPWCR: Flash memory power control register
FENR: Flash memory enable register
FLMCR2
EBR
FLPWCR
FENR
Flash memory
Figure 6.1 Block Diagram of Flas h Memory
Section 6 ROM
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6.2.3 Block Configuration
Figure 6.2 shows the block configuration of the flash memory. The thick lines indicate erasing
units, the narrow lines indicate programming units, and the values are addresses. In versions with
32 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4 blocks and 28 Kbytes ×
1 block. In versions with 16 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4
blocks and 12 Kbytes × 1 block. Erasing is performed in these units. Programming is performed in
128-byte units starting from an address with lower eight bits H'00 or H'80.
H'007F
H'0000 H'0001 H'0002
H'00FF
H'0080 H'0081 H'0082
H'03FF
H'0380 H'0381 H'0382
H'047F
H'0400 H'0401 H'0402
H'04FF
H'0480 H'0481 H'0482
H'07FF
H'0780 H'0781 H'0782
H'087F
H'0800 H'0801 H'0802
H'08FF
H'0880 H'0881 H'0882
H'0BFF
H'0B80 H'0B81 H'0B82
H'0C7F
H'0C00 H'0C01 H'0C02
H'0CFF
H'0C80 H'0C81 H'0C82
H'0FFF
H'0F80 H'0F81 H'0F82
H'107F
H'1000 H'1001 H'1002
H'10FF
H'1080 H'1081 H'1082
H'7FFF
H'7F80 H'7F81 H'7F82
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
1 Kbyte
Erase unit
1 Kbyte
Erase unit
1 Kbyte
Erase unit
1 Kbyte
Erase unit
28 Kbytes
Erase unit
Figure 6.2(1) Block Confi g ura tion of 32- K by te Flash Memory
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H'007F
H'0000 H'0001 H'0002
H'00FF
H'0080 H'0081 H'0082
H'03FF
H'0380 H'0381 H'0382
H'047F
H'0400 H'0401 H'0402
H'04FF
H'0480 H'0481 H'0482
H'07FF
H'0780 H'0781 H'0782
H'087F
H'0800 H'0801 H'0802
H'08FF
H'0880 H'0881 H'0882
H'0BFF
H'0B80 H'0B81 H'0B82
H'0C7F
H'0C00 H'0C01 H'0C02
H'0CFF
H'0C80 H'0C81 H'0C82
H'0FFF
H'0F80 H'0F81 H'0F82
H'107F
H'1000 H'1001 H'1002
H'10FF
H'1080 H'1081 H'1082
H'3FFF
H'3F80 H'3F81 H'3F82
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
1 Kbyte
Erase unit
1 Kbyte
Erase unit
1 Kbyte
Erase unit
1 Kbyte
Erase unit
12 Kbytes
Erase unit
Figure 6.2(2) Block Confi g ura tion of 16- K by te Flash Memory
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6.2.4 Register Configuration
Table 6.1 lists the register configuration to control the flash memory when the built in flash
memory is effective.
Table 6.1 Register Configuration
Register Name Abbreviation R/W Initial Value Address
Flash memory control register 1 FLMCR1 R/W H'00 H'F020
Flash memory control register 2 FLMCR2 R H'00 H'F021
Flash memory power control register FLPWCR R/W H'00 H'F022
Erase block register EBR R/W H'00 H'F023
Flash memory enable register FENR R/W H'00 H'F02B
Note: FLMCR1, FLMCR2, FLPWCR, EBR, and FENR are 8 bit registers. Only byte access is
enabled which are two-state access. These registers are dedicated to the product in which
flash memory is included. The product in which mask ROM is included does not have these
registers. When the corresponding address is read in these products, the value is
undefined. A write is disabled.
6.3 Descriptions of Registers of the Flash Memory
6.3.1 Flash Memory Control Register 1 (FLMCR1)
Bit 7 6 5 4 3 2 1 0
— SWE ESU PSU EV PV E P
Initial value 0 0 0 0 0 0 0 0
Read/Write — R/W R/W R/W R/W R/W R/W R/W
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.5, Flash
Memory Programming/Erasing. By setting this register, the flash memory enters program mode,
erase mode, program-verify mode, or erase-verify mode. Read the data in the state that bits 6 to 0
of this register are cleared when using flash memory as normal built-in ROM.
Bit 7—Reserved
This bit is always read as 0 and cannot be modified.
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Bit 6—Software Write Enable (SWE)
This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to
0 and the EBR register are to be set).
Bit 6
SWE
Description
0 Programming/erasing is disabled. Other FLMCR1 register bits and all EBR bits
cannot be set. (initial value)
1 Flash memory programming/erasing is enabled.
Bit 5—Erase Setup (ESU)
This bit is to prepare for changing to erase mode. Set this bit to 1 before setting the E bit to 1 in
FLMCR1 (do not set SWE, PSU, EV, PV, E, and P bits at the same time).
Bit 5
ESU
Description
0 The erase setup state is cancelled (initial value)
1 The flash memory changes to the erase setup state. Set this bit to 1 before setting
the E bit to 1 in FLMCR1.
Bit 4—Program Setup (PSU)
This bit is to prepare for changing to program mode. Set this bit to 1 before setting the P bit to 1 in
FLMCR1 (do not set SWE, ESU, EV, PV, E, and P bits at the same time).
Bit 4
PSU
Description
0 The program setup state is cancelled (initial value)
1 The flash memory changes to the program setup state. Set this bit to 1 before
setting the P bit to 1 in FLMCR1.
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Bit 3—Erase-Verify (EV)
This bit is to set changing to or canceling erase-verify mode (do not set SWE, ESU, PSU, PV, E,
and P bits at the same time).
Bit 3
EV
Description
0 Erase-verify mode is cancelled (initial value)
1 The flash memory changes to erase-verify mode
Bit 2—Program-Verify (PV)
This bit is to set changing to or canceling program-verify mode (do not set SWE, ESU, PSU, EV,
E, and P bits at the same time).
Bit 2
PV
Description
0 Program-verify mode is cancelled (initial value)
1 The flash memory changes to program-verify mode
Bit 1—Erase (E)
This bit is to set changing to or canceling erase mode (do not set SWE, ESU, PSU, EV, PV, and P
bits at the same time).
Bit 1
E
Description
0 Erase mode is cancelled (initial value)
1 When this bit is set to 1, while the SWE = 1 and ESU = 1, the flash memory
changes to erase mode.
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Bit 0—Program (P)
This bit is to set changing to or canceling program mode (do not set SWE, ESU, PSU, EV, PV,
and E bits at the same time).
Bit 0
P
Description
0 Program mode is cancelled (initial value)
1 When this bit is set to 1, while the SWE = 1 and PSU = 1, the flash memory
changes to program mode.
6.3.2 Flash Memory Control Register 2 (FLMCR2)
Bit 7 6 5 4 3 2 1 0
FLER — — — — — — —
Initial value 0 0 0 0 0 0 0 0
Read/Write R — — — — — — —
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit 7—Flash Memory Error (FLER)
This bit is set when the flash memory detects an error and goes to the error-protection state during
programming or erasing to the flash memory. See section 6.6.3, Error Protection, for details.
Bit 7
FLER
Description
0 The flash memory operates normally. (initial value)
1 Indicates that an error has occurred during an operation on flash memory
(programming or erasing).
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
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6.3.3 Erase Block Regi ster (E B R )
Bit 7 6 5 4 3 2 1 0
— — — EB4 EB3 EB2 EB1 EB0
Initial value 0 0 0 0 0 0 0 0
Read/Write — — — R/W R/W R/W R/W R/W
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be
erased. Other blocks change to the erase-protection state. See table 6.2 for the method of dividing
blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a
block.
Table 6.2 Division of Blocks to Be Erased
EBR Bit Name Block (Size) Address
0 EB0 EB0 (1 Kbyte) H'0000 to H'03FF
1 EB1 EB1 (1 Kbyte) H'0400 to H'07FF
2 EB2 EB2 (1 Kbyte) H'0800 to H'0BFF
3 EB3 EB3 (1 Kbyte) H'0C00 to H'0FFF
4 EB4 EB4 (12 Kbytes) H'1000 to H'3FFF (HD64F38522)
EB4 (28 Kbytes) H'1000 to H'7FFF (HD64F38524)
6.3.4 Flash Memory Power Control Register (FLPWCR)
Bit 7 6 5 4 3 2 1 0
PDWND — — — — — — —
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W — — — — — — —
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
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Bit 7—Power-down Dis able (PD WN D )
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
Bit 7
PDWND
Description
0 When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode. (initial value)
1 When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
6.3.5 Flash Memory Enabl e Register (FENR)
Bit 7 6 5 4 3 2 1 0
FLSHE — — — — — — —
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W — — — — — — —
FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and
FLPWCR.
Bit 7—Flash Memory Control Register Enable (FLSHE)
This bit controls access to the flash memory control registers.
Bit 7
FLSHE
Description
0 Flash memory control registers cannot be accessed (initial value)
1 Flash memory control registers can be accessed
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
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6.4 On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables on-
board programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, the series of HD64F38524 and HD64F38522 changes
to a mode depending on the TEST pin settings, P95 pin settings, and input level of each port, as
shown in table 6.3. The input level of each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 6.3 Setting Programming Modes
TEST P95 P34 PB0 PB1 PB2 LSI State after Reset End
0 1 X X X X User Mode
0 0 1 X X X Boot Mode
1 X X 0 0 0 Programmer Mode
X: Don’t care
6.4.1 Boot Mode
Table 6.4 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 6.5, Flash Memory Programming/Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity. The inversion function of TXD and RXD pins by the SPCR register is set to
“Not to be inverted,” so do not put the circuit for inverting a value between the host and this
LSI.
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3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 6.5.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the TEST pin and P95 pin. Boot mode is also cleared when a
WDT overflow occurs.
8. Do not change the TEST pin and P95 pin input levels in boot mode.
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Table 6.4 Boot Mode Operation
Item
Host Operation LSI Operation
Branches to boot program at reset-start.
Processing Contents Processing Contents
Bit rate
adjustment
Flash memory erase
Continuously transmits data H'00 at
specified bit rate.
· Measures low-level period of receive data H'00.
· Calculates bit rate and sets it in BRR of SCI3.
· Transmits data H'00 to the host to indicate that the
adjustment has ended.
Checks flash memory data, erases all flash memory
blocks in case of written data existing, and transmits
data H'AA to host. (If erase could not be done,
transmits data H'FF to host and aborts operation.)
Transmits data H'55 when data H'00
is received and no error occurs.
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte)
Transmits 1-byte of programming
control program
Transfer of
programming control
program
Execution of
Programming
control program
Transfer of
programming control
program (repeated for
N times)
Echobacks the 2-byte received data to host.
Transmits 1-byte data H'AA to host.
Branches to programming control program
transferred to on-chip RAM and starts execution.
Echobacks received data to host and also
transfers it to RAM.
Table 6.5 Oscillating Frequencies (fOSC) for which Automatic Adjustment of LSI Bit Rate
is Possible
Host Bit Rate Oscillating Frequencies (fOSC) Range of LSI
19,200 bps 16 to 20 MHz
9,600 bps 8 to 20 MHz
4,800 bps 6 to 20 MHz
2,400 bps 2 to 20 MHz
1,200 bps 2 to 20 MHz
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6.4.2 Programming/Erasing in User Program Mode
The term user mode refers to the status when a user program is being executed. On-board
programming/erasing of an individual flash memory block can also be performed in user program
mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 6.3 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 6.5,
Flash Memory Programming/Erasing.
Yes
No
Program/erase?
Transfer user program/erase control
program to RAM
Reset-start
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Branch to flash memory application
program
Figure 6.3 Programming/Erasing Flowchart Example in User Program Mode
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6.4.3 Notes on On-Board Programming
1. You must use the system clock oscillator when programming or erasing flash memory. The on-
chip oscillator should not be used for programming or erasing flash memory. See section 4.2
(5), On-Chip Oscillator Selection Method, for information on switching between the system
clock oscillator and the on-chip oscillator.
2. The watchdog timer operates after a reset is canceled. When executing a program prepared by
the user that performs programming and erasing in the user mode, the watchdog timer’s
overflow cycle should be set to an appropriate value. Refer to section 6.5.1, Program/Program-
Verify, for information on the appropriate watchdog timer overflow cycle for programming,
and refer to section 6.5.2, Erase/Erase-Verify, for information on the appropriate watchdog
timer overflow cycle for erasing.
6.5 Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the on-
board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 6.5.1, Program/Program-Verify and section 6.5.2,
Erase/Erase-Verify, respectively.
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6.5.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 6.4 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to the flash memory without subjecting the chip to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 6.6, and additional programming data
computation according to table 6.7.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Table 6.8 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent over-programming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
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START
End of programming
Set SWE bit in FLMCR1
Write pulse application subroutine
Wait 1 µs
Apply Write Pulse
End Sub
Set PSU bit in FLMCR1
WDT enable
Disable WDT
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time = programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
n = 1
m = 0
No
No
No Yes
Yes
Yes
Yes
Wait 4 µs
Wait 2 µs
Wait 2 µs
Apply Write pulse
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Reprogram data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
Increment address
Programming failure
Clear SWE bit in FLMCR1
Wait 100 µs
No
Yes
No
Yes
No
Wait 100 µs
n ≤ 1000 ?
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Store 128-byte program data in program
data area and reprogram data area
Apply Write Pulse
Sub-Routine-Call
Successively write 128-byte data from
additional-programming data area
in RAM to flash memory
Set block start address as
verify address
n ← n + 1
m = 1
m = 0 ?
n ≤ 6?
128-byte
data verification
completed?
n ≤ 6 ?
Additional-programming data
computation
Verify data =
write data?
Figure 6.4 Program/Program-Verify Flowchart
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Table 6.6 Reprogram Data Comput at i on Tabl e
Program Data Verify Data Reprogram Data Comments
0 0 1 Programming completed
0 1 0 Reprogram bit
1 0 1 —
1 1 1 Remains in erased state
Table 6.7 Additional-Program Data Computation Table
Reprogram Data
Verify Data Additional-Program
Data
Comments
0 0 0 Additional-program bit
0 1 1 No additional programming
1 0 1 No additional programming
1 1 1 No additional programming
Table 6.8 Programming Time
n
(Number of Writes) Programming
Time In Additional
Programming
Comments
1 to 6 30 10
7 to 1,000 200 —
Note: Time shown in µs.
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6.5.2 Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.5 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent over-erasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
verify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
6.5.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, are disabled while flash memory is being programmed or erased, or while the boot
program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
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Erase start
Set EBR
Enable WDT
Wait 1 µs
Wait 100 µs
SWE bit ← 1
n ← 1
ESU bit ← 1
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 0
Wait 10 µs
Disable WDT
Read verify data
Increment address Verify data = all 1s ?
Last address of block ?
All erase block erased ?
Set block start address as verify address
H'FF dummy write to verify address
Wait 20 µs
Wait 2 µs
EV bit ← 1
Wait 100 µs
End of erasing
SWE bit ← 0
Wait 4 µs
EV bit ← 0
n ≤100 ?
Wait 100 µs
Erase failure
SWE bit ← 0
Wait 4µs
EV bit ← 0
n ← n + 1
Yes
No
Yes
Yes
Yes
No
No
No
Figure 6.5 Erase/Erase-Verify Flowchart
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6.6 Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
6.6.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode,
or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), and erase block register (EBR) are initialized. In a reset via the RES pin, the reset
state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the
AC Characteristics section.
6.6.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00, erase
protection is set for all blocks.
Section 6 ROM
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REJ09B0409-0100
6.6.3 Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to over-programming or over-erasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, and EBR settings are retained, however program mode or erase mode is
aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered
by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be
made to verify mode. Error protection can be cleared only by a power-on reset.
6.7 Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-Kbyte flash memory
(F-ZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to
programmer mode, see table 6.3.
6.7.1 Socket Adapter
The socket adapter converts the pin allocation of the HD64F38524 and HD64F38522 to that of the
discrete flash memory HN28F101. The address of the on-chip flash memory is H'0000 to H'7FFF.
Figure 6.6 shows a socket-adapter-pin correspondence diagram of the HD64F38524 and
HD64F38522.
Section 6 ROM
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6.7.2 Programmer Mode Commands
The following commands are supported in programmer mode.
• Memory Read Mode
• Auto-Program Mode
• Auto-Erase Mode
• Status Read Mode
Status polling is used for auto-programming, auto-erasing, and status read modes. In status read
mode, detailed internal information is output after the execution of auto-programming or auto-
erasing. Table 6.9 shows the sequence of each command. In auto-programming mode, 129 cycles
are required since 128 bytes are written at the same time. In memory read mode, the number of
cycles depends on the number of address write cycles (n).
Table 6.9 Command Sequence in Programmer Mode
1st Cycle 2nd Cycle
Command Name Number
of Cycles Mode Address Data Mode Address Data
Memory read 1 + n Write X H'00 Read RA Dout
Auto-program 129 Write X H'40 Write WA Din
Auto-erase 2 Write X H'20 Write X H'20
Status read 2 Write X H'71 Write X H'71
n: the number of address write cycles
Section 6 ROM
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REJ09B0409-0100
HD64F38524, HD64F38522
FP-80A
TFP-80C
Pin No.
Pin No.
Pin Name Pin Name
P71
P77
P92
P60
P61
P62
P63
P64
P65
P66
P67
P40
P41
P32
P33
P34
P35
P36
P37
P70
P42
P72
P73
P74
P75
P76
P43
Vcc
AVcc
X1
TEST
V1
Vcc
P94
CVcc, P95
Vss
Vss
PB0
PB1
PB2
OSC1,OSC2
RES
(OPEN)
HN28F101
(32 Pins)
1
26
2
3
31
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
32
16
FWE
A9
A16
A15
WE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
A10
A11
A12
A13
A14
CE
Vcc
Vss
30
36
56
21
22
23
24
25
26
27
28
69
70
63
64
65
66
67
68
29
71
31
32
33
34
35
72
52
1
6
11
51
52
58
4, 59
8
53
73
74
75
10,9
12
Power-on
reset circuit
Oscillator circuit
Socket Adapter
(Conversion to
32-Pin
Arrangement)
Other than the above
[Legend]
FWE: Flash-write enable
I/O7 to I/O0: Data input/output
A16 to A0: Address input
CE: Chip enable
OE: Output enable
WE: Write enable
Note: The oscillation frequency
of the oscillator circuit
should be 10 MHz.
Figure 6.6 Socket Adapter Pin Correspondence Diagram
(HD64F38524, HD64F38522)
Section 6 ROM
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6.7.3 Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the
command wait state. When reading memory contents, a transition to memory read mode must
first be made with a command write, after which the memory contents are read. Once memory
read mode has been entered, consecutive reads can be performed.
2. In memory read mode, command writes can be performed in the same way as in the command
wait state.
3. After powering on, memory read mode is entered.
4. Tables 6.10 to 6.12 show the AC characteristics.
Table 6.10 AC Characteristics in Transition to Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 — µs Figure 6.7
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 — ns
Data setup time tds 50 — ns
Write pulse width twep 70 — ns
WE rise time tr — 30 ns
WE fall time tf — 30 ns
CE
OE
CE
A15−A0
OE
WE
I/O7−I/O0
Note: Data is latched on the rising edge of WE.
t
ceh
t
wep
t
f
t
r
t
ces
t
nxtc
Address stable
t
ds
t
dh
Command write Memory read mode
Figure 6.7 Timing Waveforms for Memo ry Read after Mem ory Write
Section 6 ROM
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Table 6.11 AC Characteri sti cs in Tra nsition from Memory Read Mode to Anothe r Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 — µs Figure 6.8
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 — ns
Data setup time tds 50 — ns
Write pulse width twep 70 — ns
WE rise time tr — 30 ns
WE fall time tf — 30 ns
CE
A15−A0
OE
WE
I/O7−I/O0
Note: Do not enable WE and OE at the same time.
t
ceh
t
wep
t
f
t
r
t
ces
t
nxtc
Address stable
t
ds
t
dh
Other mode command writeMemory read mode
Figure 6.8 Timing Waveforms in Transition from Memory Read Mode to Another Mode
Section 6 ROM
Rev. 1.00 Dec. 19, 2007 Page 152 of 520
REJ09B0409-0100
Table 6.12 AC Characteristics in Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Access time tacc — 20 µs Figure 6.9
CE output delay time tce — 150 ns Figure 6.10
OE output delay time toe — 150 ns
Output disable delay time tdf — 100 ns
Data output hold time toh 5 — ns
CE
A15−A0
OE
WE
I/O7−I/O0
t
acc
t
acc
t
oh
t
oh
Address stableAddress stable
Figure 6.9 CE and OE Enable State Read Timing Waveforms
CE
A15−A0
OE
WE
I/O7−I/O0
t
acc
t
ce
t
oe
t
oe
t
ce
t
acc
t
oh
t
df
t
df
t
oh
Address stableAddress stable
Figure 6.10 CE and OE Clock System Read Timing Waveforms
Section 6 ROM
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REJ09B0409-0100
6.7.4 Auto-Program Mode
1. When reprogramming previously programmed addresses, perform auto-erasing before auto-
programming.
2. Perform auto-programming once only on the same address block. It is not possible to program
an address block that has already been programmed.
3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when
programming fewer than 128 bytes. In this case, H'FF data must be written to the extra
addresses.
4. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
5. Memory address transfer is performed in the second cycle (figure 6.11). Do not perform
transfer after the third cycle.
6. Do not perform a command write during a programming operation.
7. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
8. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose (I/O7 status polling uses the auto-program operation end
decision pin).
9. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
10. Table 6.13 shows the AC characteristics.
Section 6 ROM
Rev. 1.00 Dec. 19, 2007 Page 154 of 520
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Table 6.13 AC Characteristics in Auto-Program Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 — µs Figure 6.11
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 — ns
Data setup time tds 50 — ns
Write pulse width twep 70 — ns
Status polling start time twsts 1 — ms
Status polling access time tspa — 150 ns
Address setup time tas 0 — ns
Address hold time tah 60 — ns
Memory write time twrite 1 3000 ms
WE rise time tr — 30 ns
WE fall time tf — 30 ns
CE
A15−A0
OE
WE
I/O7
I/O6
I/O5−I/O0
t
wep
t
ds
t
dh
t
f
t
r
t
as
t
ah
t
wsts
t
write
t
spa
t
ces
t
ceh
t
nxtc
t
nxtc
Address
stable
H'40 H'00
Data transfer
1 to 128 bytes
Write operation end decision signal
Write normal end decision signal
Figure 6.11 Auto-Program Mode Timing Waveforms
Section 6 ROM
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REJ09B0409-0100
6.7.5 Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.
2. Do not perform a command write during auto-erasing.
3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also
be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).
4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
5. Table 6.14 shows the AC characteristics.
Table 6.14 AC Characteri sti cs in Aut o - E rase Mo de
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 — µs Figure 6.12
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 — ns
Data setup time tds 50 — ns
Write pulse width twep 70 — ns
Status polling start time tests 1 — ms
Status polling access time tspa — 150 ns
Memory erase time terase 100 40000 ms
WE rise time tr — 30 ns
WE fall time tf — 30 ns
Section 6 ROM
Rev. 1.00 Dec. 19, 2007 Page 156 of 520
REJ09B0409-0100
CE
A15−A0
OE
WE
I/O7
I/O6
I/O5−I/O0
t
wep
t
ds
t
dh
t
f
t
r
t
ests
t
erase
t
spa
t
ces
t
ceh
t
nxtc
t
nxtc
H'20 H'20 H'00
Erase end
decision signal
Erase normal
end
decision signal
Figure 6.12 Auto-Erase Mode Timing Waveforms
6.7.6 Status Read Mo de
1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than a status read mode command
write is executed.
3. Table 6.15 shows the AC characteristics and 6.16 shows the return codes.
Section 6 ROM
Rev. 1.00 Dec. 19, 2007 Page 157 of 520
REJ09B0409-0100
Table 6.15 AC Characteristics in Status Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Max Unit Notes
Read time after command write tnxtc 20 — µs Figure 6.13
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 — ns
Data setup time tds 50 — ns
Write pulse width twep 70 — ns
OE output delay time toe — 150 ns
Disable delay time tdf — 100 ns
CE output delay time tce — 150 ns
WE rise time tr — 30 ns
WE fall time tf — 30 ns
CE
A15−A0
OE
WE
I/O7−/O0
t
wep
t
f
t
r
t
oe
t
df
t
ds
t
ds
t
dh
t
dh
t
ces
t
ceh
t
ce
t
ceh
t
nxtc
t
nxtc
t
nxtc
t
ces
H'71
t
wep
t
f
t
r
H'71
Note: I/O2 and I/O3 are undefined.
Figure 6.13 Status Read Mode Timing Waveforms
Section 6 ROM
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Table 6.16 Status Read Mode Return Codes
Pin Name Initial Value Indications
I/O7 0 1: Abnormal end
0: Normal end
I/O6 0 1: Command error
0: Otherwise
I/O5 0 1: Programming error
0: Otherwise
I/O4 0 1: Erasing error
0: Otherwise
I/O3 0
I/O2 0
I/O1 0 1: Over counting of writing or erasing
0: Otherwise
I/O0 0 1: Effective address error
0: Otherwise
6.7.7 Status Polling
1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.
2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 6.17 Status Polling Output Truth Table
I/O7 I/O6 I/O0 to 5 Status
0 0 0 During internal operation
1 0 0 Abnormal end
1 1 0 Normal end
0 1 0 —
Section 6 ROM
Rev. 1.00 Dec. 19, 2007 Page 159 of 520
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6.7.8 Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 6.18 Stipulated Transition Times to Command Wait State
Item Symbol Min Max Unit Notes
Oscillation stabilization time(crystal oscillator) Tosc1 10 — ms Figure 6.14
Oscillation stabilization time(ceramic oscillator) Tosc1 5 — ms
Programmer mode setup time Tbmv 10 — ms
Vcc hold time Tdwn 0 — ms
t
osc1
t
bmv
t
dwn
Vcc
R
ES
Auto-program mode
Auto-erase mode
Figure 6.14 Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence
6.7.9 Notes on Memory Programming
1. When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
2. The flash memory is initially in the erased state when the device is shipped by Renesas
Technology. For other chips for which the erasure history is unknown, it is recommended that
auto-erasing be executed to check and supplement the initialization (erase) level.
Section 6 ROM
Rev. 1.00 Dec. 19, 2007 Page 160 of 520
REJ09B0409-0100
6.8 Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of the flash memory is partly halted and can be read under low power
consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.19 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize the power supply circuits that were
stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to
STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the external
clock is being used.
Table 6.19 Flash Memory Operating States
Flash Memory Operating State
LSI Operating State PDWND = 0 (Initial value) PDWND = 1
Active mode Normal operating mode Normal operating mode
Subactive mode Power-down mode Normal operating mode
Sleep mode Normal operating mode Normal operating mode
Subsleep mode Standby mode Standby mode
Standby mode Standby mode Standby mode
Watch mode Standby mode Standby mode
Section 7 RAM
Rev. 1.00 Dec. 19, 2007 Page 161 of 520
REJ09B0409-0100
Section 7 RAM
7.1 Overview
The H8/38524, H8/38523, and H8/38522 have 1 Kbyte of high-speed static RAM on-chip, and the
H8/38521 and H8/38520 have 512 bytes. The RAM is connected to the CPU by a 16-bit data bus,
allowing high-speed 2-state access for both byte data and word data.
7.1.1 Block Diagram
Figure 7.1 shows a block diagram of the on-chip RAM.
H'FF7E H'FF7F
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Even-numbered
address
Odd-numbered
address
H'FF7E
H'FB82
H'FB80 H'FB80
H'FB82
H'FB81
H'FB83
On-chip RAM
Figure 7.1 RAM Block Diagra m
Section 7 RAM
Rev. 1.00 Dec. 19, 2007 Page 162 of 520
REJ09B0409-0100
Section 8 I/O Ports
Rev. 1.00 Dec. 19, 2007 Page 163 of 520
REJ09B0409-0100
Section 8 I/O Ports
8.1 Overview
The LSI is provided with five 8-bit I/O ports, one 4-bit I/O port, two 3-bit I/O ports, one 8-bit
input-only port, one 1-bit input-only port, and one 6-bit output-only port. Table 8.1 indicates the
functions of each port.
Each port has of a port control register (PCR) that controls input and output, and a port data
register (PDR) for storing output data. Input or output can be assigned to individual bits.
See section 2.8.3, Bit-Manipulation Instruction, for information on executing bit-manipulation
instructions to write data in PCR or PDR.
Ports 5, 6, 7, 8, and A are also used as liquid crystal display segment and common pins, selectable
in 4-bit units.
Block diagrams of each port are given in appendix B, I/O Port Block Diagrams.
Table 8.1 Port Functions
Port
Description
Pins
Other Functions
Function
Switching
Registers
Port 1
P17/IRQ3/TMIF External interrupt 3, timer
event input pin TMIF
PMR1
TCRF
P14/IRQ4/ADTRG External interrupt 4, A/D
converter external trigger
PMR1
AMR
• 3-bit I/O port
• MOS input pull-up
option
P13/TMIG Timer G input capture PMR1
PMR2
Port 3 P37/AEVL
P36/AEVH
Asynchronous counter event
input pins AEVL, AEVH
PMR3
ECCR
P35 to P33 None PMR2
P32, TMOFH
P31, TMOFL
Timer F output compare
output
PMR3
• 8-bit I/O port
• MOS input pull-up
option
• Large-current port
• MOS open drain
output selectable
(only P35)
P30/UD Timer C count up/down
selection input
PMR3
Section 8 I/O Ports
Rev. 1.00 Dec. 19, 2007 Page 164 of 520
REJ09B0409-0100
Port
Description
Pins
Other Functions
Function
Switching
Registers
Port 4 P43/IRQ0 External interrupt 0 PMR2
• 1-bit input port
• 3-bit I/O port P42/TXD32
P41/RXD32
P40/SCK32
SCI3 data output (TXD32),
data input (RXD32), clock
input/output (SCK32)
SCR3
SMR3
SPCR
Port 5 • 8-bit I/O port
• MOS input pull-up
option
P57 to P50/
WKP7 to WKP0/
SEG8 to SEG1
Wakeup input (WKP7 to
WKP0), segment output
(SEG8 to SEG1)
PMR5
LPCR
Port 6 • 8-bit I/O port
• MOS input pull-up
option
P67 to P60/
SEG16 to SEG9
Segment output (SEG16 to
SEG9)
LPCR
Port 7 • 8-bit I/O port P77 to P70/
SEG24 to SEG17
Segment output (SEG24 to
SEG17)
LPCR
Port 8 • 8-bit I/O port P87 to P80/
SEG32 to SEG25
Segment output (SEG32 to
SEG25)
LPCR
Port 9 P95, P94, P92,
P93/Vref
LVD reference voltage
external input pin
LVDSR
• Dedicated 6-bit
output port
P91, P90/
PWM2, PWM1
10-bit PWM output PMR9
• Input port IRQAEC None
Port A • 4-bit I/O port PA3 to PA0/
COM4 to COM1
Common output
(COM4 to COM1)
LPCR
Port B • Dedicated 8-bit
input port
PB7 to PB4/
AN7 to AN4
A/D converter analog input
(AN7 to AN4)
AMR
PB3/AN3/IRQ1 A/D converter analog input
(AN3), external interrupt 1,
timer event input (TMIC)
AMR
PMRB
TMC
PB2/AN2 A/D converter analog input AMR
PB1/AN1/(extU)
PB0/AN0/(extD)
A/D converter analog input
(LVD detect voltage external
input pin)
AMR
(LVDCR)
Section 8 I/O Ports
Rev. 1.00 Dec. 19, 2007 Page 165 of 520
REJ09B0409-0100
8.2 Port 1
8.2.1 Overview
Port 1 is a 3-bit I/O port. Figure 8.1 shows its pin configuration.
P1
7
/IRQ
3
/TMIF
P1
4
/IRQ
4
/ADTRG
P1
3
/TMIG
Port 1
Figure 8.1 Port 1 Pin Configuration
8.2.2 Register Configuration and Description
Table 8.2 shows the port 1 register configuration.
Table 8.2 Port 1 Registers
Name Abbr. R/W Initial Value Address
Port data register 1 PDR1 R/W — H'FFD4
Port control register 1 PCR1 W — H'FFE4
Port pull-up control register 1 PUCR1 R/W — H'FFE0
Port mode register 1 PMR1 R/W — H'FFC8
Port mode register 2 PMR2 R/W H'D8 H'FFC9
Section 8 I/O Ports
Rev. 1.00 Dec. 19, 2007 Page 166 of 520
REJ09B0409-0100
(1) Port Data Register 1 (PDR1)
Bit 7 6 5 4 3 2 1 0
P17 — — P14 P13 — — —
Initial value 0 — — 0 0 — — —
Read/Write R/W — — R/W R/W — — —
PDR1 is an 8-bit register that stores data for port 1 pins P17, P14, and P13. If port 1 is read while
PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If
port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
(2) Port Control Register 1 (PCR1)
Bit 7 6 5 4 3 2 1 0
PCR17 — — PCR14 PCR13 — — —
Initial value 0 — — 0 0 — — —
Read/Write W — W W W W W W
PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17, P14, and P13 functions
as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin,
while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid
only when the corresponding pin is designated in PMR1 as a general I/O pin.
PCR1 is a write-only register, which is always read as all 1s.
(3) Port Pull-Up Control Register 1 (PUCR1)
Bit 7 6 5 4 3 2 1 0
PUCR17 — — PUCR14PUCR13— — —
Initial value 0 — — 0 0 — — —
Read/Write R/W — W R/W R/W W W W
PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17, P14, and P13 is on or off.
When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-
up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Section 8 I/O Ports
Rev. 1.00 Dec. 19, 2007 Page 167 of 520
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(4) Port Mode Register 1 (PMR1)
Bit 7 6 5 4 3 2 1 0
IRQ3 — — IRQ4 TMIG — — —
Initial value 0 1 — 0 0 — 1 —
Read/Write R/W — W R/W R/W W — W
PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins.
Bit 7—P17/IRQ3/TMIF Pin Function Swit ch (I RQ 3)
This bit selects whether pin P17/IRQ3/TMIF is used as P17 or as IRQ3/TMIF.
Bit 7
IRQ3
Description
0 Functions as P17 I/O pin (initial value)
1 Functions as IRQ3/TMIF input pin
Note: Rising or falling edge sensing can be designated for IRQ3, TMIF. For details on TMIF
settings, see (3) Timer Control Register F (TCRF) in section 9.4.2, Register Descriptions.
Bit 6—Reserved
This bit is reserved; it is always read as 1 and cannot be modified.
Bit 5—Reserved
This bit is reserved; it can only be written with 0.
Bit 4—P14/IRQ4/ADTRG Pin Function Switch (IRQ4)
This bit selects whether pin P14/IRQ4/ADTRG is used as P14 or as IRQ4/ADTRG.
Bit 4
IRQ4
Description
0 Functions as P14 I/O pin (initial value)
1 Functions as IRQ4/ADTRG input pin
Note: For details of ADTRG pin setting, see section 12.3.2, Start of A/D Conversion by External
Trigger Input.
Section 8 I/O Ports
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Bit 3—P13/TMIG Pin Function Switch (TMIG)
This bit selects whether pin P13/TMIG is used as P13 or as TMIG.
Bit 3
TMIG
Description
0 Functions as P13 I/O pin (initial value)
1 Functions as TMIG input pin
Bits 2 and 0—Reserved
These bits are reserved; they can only be written with 0.
Bit 1—Reserved
This bit is reserved; it is always read as 1 and cannot be modified.
(5) Port Mode Register 2 (PMR2)
Bit 7 6 5 4 3 2 1 0
— — POF1 — — WDCKS NCS IRQ0
Initial value 1 1 0 1 1 0 0 0
Read/Write — — R/W — — R/W R/W R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
This section only deals with the bits related to timer G and the watchdog timer. For the functions
of the bits, see the descriptions of port 3 (POF1) and port 4 (IRQ0).
Section 8 I/O Ports
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Bit 2—Watchdog Timer Source Clock (WDCKS)
This bit selects the watchdog timer source clock.
Bit 2
WDCKS
Description
0 Selects clock based on timer mode register W (TMW) setting* (Initial value)
1 Selects φW/32
Note: * See section 9.6, Watchdog Timer, for details.
Bit 1—TMIG Noise Canceller Select (NCS)
This bit selects controls the noise cancellation circuit of the input capture input signal (TMIG).
Bit 1
NCS
Description
0 No noise cancellation circuit (Initial value)
1 Noise cancellation circuit
Section 8 I/O Ports
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8.2.3 Pin Functions
Table 8.3 shows the port 1 pin functions.
Table 8.3 Port 1 Pin Functions
Pin Pin Functions and Selection Method
P17/IRQ3/TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF,
and bit PCR17 in PCR1.
IRQ3 0 1
PCR17 0 1 *
CKSL2 to CKSL0 * Not 0** 0**
Pin function P17 input pin P17 output pin IRQ3 input pin IRQ3/TMIF
input pin
Note: When this pin is used as the TMIF input pin, clear bit IEN3 to 0 in IENR1
to disable the IRQ3 interrupt.
P14/IRQ4
ADTRG
The pin function depends on bit IRQ4 in PMR1, bit TRGE in AMR, and bit PCR14
in PCR1.
IRQ4 0 1
PCR14 0 1 *
TRGE * 0 1
Pin function P14 input pin P14 output pin IRQ4 input pin IRQ4/ADTRG
input pin
Note: When this pin is used as the ADTRG input pin, clear bit IEN4 to 0 in
IENR1 to disable the IRQ4 interrupt.
P13/TMIG The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1.
TMIG 0 1
PCR13 0 1 *
Pin function P13 input pin P13 output pin TMIG input pin
*: Don’t care
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8.2.4 Pin States
Table 8.4 shows the port 1 pin states in each operating mode.
Table 8.4 Port 1 Pin States
Pins Reset Sleep Subsleep Standby Watch Subactive Active
P17/IRQ3/TMIF
P14/IRQ4/ADTRG
P13/TMIG
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance*
Retains
previous
state
Functional Functional
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.2.5 MOS Input Pull-Up
Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1
bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up for
that pin. The MOS input pull-up function is in the off state after a reset.
PCR1n 0 0 1
PUCR1n 0 1 *
MOS input pull-up Off On Off
(n = 7, 4, 3)
*: Don’t care
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8.3 Port 3
8.3.1 Overview
Port 3 is an 8-bit I/O port, configured as shown in figure 8.2.
P3 /AEVL
P3 /AEVH
P3
7
6
5
Port 3
P3
P3
P3 /TMOFH
4
3
2
P3 /TMOFL
1
P3 /UD
0
Figure 8.2 Port 3 Pin Configuration
8.3.2 Register Configuration and Description
Table 8.5 shows the port 3 register configuration.
Table 8.5 Port 3 Registers
Name Abbr. R/W Initial Value Address
Port data register 3 PDR3 R/W H'00 H'FFD6
Port control register 3 PCR3 W H'00 H'FFE6
Port pull-up control register 3 PUCR3 R/W H'00 H'FFE1
Port mode register 2 PMR2 R/W H'D8 H'FFC9
Port mode register 3 PMR3 R/W — H'FFCA
Section 8 I/O Ports
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(1) Port Data Register 3 (PDR3)
Bit
Initial value
Read/Write
7
P3
0
R/W
6
P3
0
R/W
5
P3
0
R/W
4
P3
0
R/W
3
P3
0
R/W
0
P3
0
0
R/W
2
P3
0
R/W
1
P3
0
R/W
215476 3
PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3
bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is
read while PCR3 bits are cleared to 0, the pin states are read.
Upon reset, PDR3 is initialized to H'00.
(2) Port Control Register 3 (PCR3)
Bit
Initial value
Read/Write
7
PCR3
0
W
6
PCR3
0
W
5
PCR3
0
W
4
PCR3
0
W
3
PCR3
0
W
0
PCR3
0
0
W
2
PCR3
0
W
1
PCR3
0
W
2154 376
PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P30 functions as an
input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only
when the corresponding pin is designated in PMR3 as a general I/O pin.
Upon reset, PCR3 is initialized to H'00.
PCR3 is a write-only register, which is always read as all 1s.
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(3) Port Pull-Up Control Register 3 (PUCR3)
Bit
Initial value
Read/Write
7
PUCR3
0
R/W
6
PUCR3
0
R/W
5
PUCR3
0
R/W
4
PUCR3
0
R/W
3
PUCR3
0
R/W
0
PUCR3
0
0
R/W
2
PUCR3
0
R/W
1
PUCR3
0
R/W
21
54376
PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P30 is on or off. When
a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR3 is initialized to H'00.
(4) Port Mode Register 2 (PMR2)
Bit 7 6 5 4 3 2 1 0
— — POF1 — — WDCKS NCS IRQ0
Initial value 1 1 0 1 1 0 0 0
Read/Write — — R/W — — R/W R/W R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
This section only deals with the bit that controls whether the PMOS transistor internal to pin P35 is
on or off. For the functions of the other bits, see the descriptions of port 1 (WDCKS and NCS) and
port 4 (IRQ0).
Bit 5—Pin P35 PMOS Transistor Control (POF1)
This bit selects whether the PMOS transistor of the output buffer for pin P35 is on or off.
Bit 5
POF1
Description
0 CMOS output (initial value)
1 NMOS open-drain output
Note: The pin is an NMOS open-drain output when this bit is set to 1 and P35 is an output.
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(5) Port Mode Register 3 (PMR3)
Bit
Initial value
Read/Write
7
AEVL
0
R/W
6
AEVH
0
R/W
5
W
4
W
3
W
0
UD
0
R/W
2
TMOFH
0
R/W
1
TMOFL
0
R/W
PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins.
Bit 7—P37/AEVL Pin Function Switch (AEVL)
This bit selects whether pin P37/AEVL is used as P37 or as AEVL.
Bit 7
AEVL
Description
0 Functions as P37 I/O pin (initial value)
1 Functions as AEVL input pin
Bit 6—P36/AEVH Pin Function Switch (AEVH)
This bit selects whether pin P36/AEVH is used as P36 or as AEVH.
Bit 6
AEVH
Description
0 Functions as P36 I/O pin (initial value)
1 Functions as AEVH input pin
Bits 5 to 3—Reserved
These bits are reserved; they can only be written with 0.
Bit 2—P32/TMOFH Pin Functi on Switch (TMOFH)
This bit selects whether pin P32/TMOFH is used as P32 or as TMOFH.
Bit 2
TMOFH
Description
0 Functions as P32 I/O pin (initial value)
1 Functions as TMOFH output pin
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Bit 1—P31/TMOFL Pin Function Switch (TMOFL)
This bit selects whether pin P31/TMOFL is used as P31 or as TMOFL.
Bit 1
TMOFL
Description
0 Functions as P31 I/O pin (initial value)
1 Functions as TMOFL output pin
Bit 0—P30/UD Pin Function Switch (UD)
This bit selects whether pin P30/UD is used as P30 or as UD.
Bit 0
UD
Description
0 Functions as P30 I/O pin (initial value)
1 Functions as UD input pin
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8.3.3 Pin Functions
Table 8.6 shows the port 3 pin functions.
Table 8.6 Port 3 Pin Functions
Pin Pin Functions and Selection Method
P37/AEVL The pin function depends on bit AEVL in PMR3 and bit PCR37 in PCR3.
AEVL 0 1
PCR37 0 1 *
Pin function P37 input pin P37 output pin AEVL input pin
P36/AEVH The pin function depends on bit AEVH in PMR3 and bit PCR36 in PCR3.
AEVH 0 1
PCR36 0 1 *
Pin function P36 input pin P36 output pin AEVH input pin
P35 to P33 The pin function depends on the corresponding bit in PCR3.
PCR3n 0 1
Pin function P3n input pin P3n output pin
(n = 5 to 3)
P32/TMOFH The pin function depends on bit TMOFH in PMR3 and bit PCR32 in PCR3.
TMOFH 0 1
PCR32 0 1 *
Pin function P32 input pin P32 output pin TMOFH output pin
P31/TMOFL The pin function depends on bit TMOFL in PMR3 and bit PCR31 in PCR3.
TMOFL 0 1
PCR31 0 1 *
Pin function P31 input pin P31 output pin THOFL output pin
P30/UD The pin function depends on bit UD in PMR3 and bit PCR30 in PCR3.
UD 0 1
PCR30 0 1 *
Pin function P30 input pin P30 output pin UD input pin
*: Don’t care
Section 8 I/O Ports
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8.3.4 Pin States
Table 8.7 shows the port 3 pin states in each operating mode.
Table 8.7 Port 3 Pin States
Pins Reset Sleep Subsleep Standby Watch Subactive Active
P37/AEVL
P36/AEVH
P35
P34
P33
P32/TMOFH
P31/TMOFL
P30/UD
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance*
Retains
previous
state
Functional Functional
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.3.5 MOS Input Pull-Up
Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a PCR3
bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for that pin.
The MOS pull-up function is in the off state after a reset.
PCR3n 0 0 1
PUCR3n 0 1 *
MOS input pull-up Off On Off
(n = 7 to 0)
*: Don’t care
Section 8 I/O Ports
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8.4 Port 4
8.4.1 Overview
Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.3.
P4
P4
P4
P4
/IRQ
0
/TXD
32
/RXD
32
/SCK
32
3
2
1
0
Port 4
Figure 8.3 Port 4 Pin Configuration
8.4.2 Register Configuration and Description
Table 8.8 shows the port 4 register configuration.
Table 8.8 Port 4 Registers
Name Abbr. R/W Initial Value Address
Port data register 4 PDR4 R/W H'F8 H'FFD7
Port control register 4 PCR4 W H'F8 H'FFE7
Port mode register 2 PMR2 R/W H'D8 H'FFC9
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(1) Port Data Register 4 (PDR4)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
P4
1
R
0
P4
0
R/W
2
P4
0
R/W
1
P4
0
R/W
3210
PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4
bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is
read while PCR4 bits are cleared to 0, the pin states are read.
Upon reset, PDR4 is initialized to H'F8.
(2) Port Control Register 4 (PCR4)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
1
3
1
0
PCR4
0
W
2
PCR4
0
W
1
PCR4
0
W
210
PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an
input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR4 and PDR4 settings are valid when the
corresponding pins are designated for general-purpose input/output by SCR3.
Upon reset, PCR4 is initialized to H'F8.
PCR4 is a write-only register, which is always read as all 1s.
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(3) Port Mode Register 2 (PMR2)
Bit
Initial value
Read/Write
7
1
6
1
5
POF1
0
R/W
4
1
3
1
0
IRQ
0
0
R/W
2
WDCKS
0
R/W
1
NCS
0
R/W
PMR2 is an 8-bit read/write register. It controls whether the PMOS transistor internal to P35 is on
or off, the selection of the watchdog timer clock, the selection of TMIG noise cancellation, and
switching of the P43/IRQ0 pin functions.
Upon reset, PMR2 is initialized to H'D8.
This section only deals with the bit that controls switching of the P43/IRQ0 pin functions. For the
functions of the other bits, see the descriptions of port 1 (WDCKS and NCS) and port 3 (POF1).
Bit 0—P43/IRQ0 Pin Function Switch (IRQ0)
This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0.
Bit 0
IRQ0
Description
0 Functions as P43 input pin (initial value)
1 Functions as IRQ0 input pin
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8.4.3 Pin Functions
Table 8.9 shows the port 4 pin functions.
Table 8.9 Port 4 Pin Functions
Pin Pin Functions and Selection Method
P43/IRQ0 The pin function depends on bit IRQ0 in PMR2.
IRQ0 0 1
Pin function P43 input pin IRQ0 input pin
P42/TXD32 The pin function depends on bit TE in SCR3, bit SPC32 in SPCR, and bit
PCR42 in PCR4.
SPC32 0 1
TE 0 1
PCR42 0 1 *
Pin function P42 input pin P42 output pin TXD32 output pin
P41/RXD32 The pin function depends on bit RE in SCR3 and bit PCR41 in PCR4.
RE 0 1
PCR41 0 1 *
Pin function P41 input pin P41 output pin RXD32 input pin
P40/SCK32 The pin function depends on bit CKE1 and CKE0 in SCR3, bit COM in SMR3,
and bit PCR40 in PCR4.
CKE1 0 1
CKE0 0 1 *
COM 0 1 * *
PCR40 0 1 * *
Pin function P40 input pin P40 output pin SCK32 output
pin
SCK32 input
pin
*: Don’t care
Section 8 I/O Ports
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8.4.4 Pin States
Table 8.10 shows the port 4 pin states in each operating mode.
Table 8.10 Port 4 Pin States
Pins Reset Sleep Subsleep Standby Watch Subactive Active
P43/IRQ0
P42/TXD32
P41/RXD32
P40/SCK32
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance
Retains
previous
state
Functional Functional
8.5 Port 5
8.5.1 Overview
Port 5 is an 8-bit I/O port, configured as shown in figure 8.4.
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
P54/WKP4/SEG5
P53/WKP3/SEG4
P52/WKP2/SEG3
P51/WKP1/SEG2
P50/WKP0/SEG1
Port 5
Figure 8.4 Port 5 Pin Configuration
Section 8 I/O Ports
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8.5.2 Register Configuration and Description
Table 8.11 shows the port 5 register configuration.
Table 8.11 Port 5 Registers
Name Abbr. R/W Initial Value Address
Port data register 5 PDR5 R/W H'00 H'FFD8
Port control register 5 PCR5 W H'00 H'FFE8
Port pull-up control register 5 PUCR5 R/W H'00 H'FFE2
Port mode register 5 PMR5 R/W H'00 H'FFCC
(1) Port Data Register 5 (PDR5)
Bit 7 6 5 4 3 2 1 0
P57 P56 P55 P54 P53 P52 P51 P50
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5
bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is
read while PCR5 bits are cleared to 0, the pin states are read.
Upon reset, PDR5 is initialized to H'00.
(2) Port Control Register 5 (PCR5)
Bit
Initial value
Read/Write
7
PCR5
0
W
6
PCR5
0
W
5
PCR5
0
W
4
PCR5
0
W
3
PCR5
0
W
0
PCR5
0
W
2
PCR5
0
W
1
PCR5
0
W
76543210
PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an
input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR5 and PDR5 settings are valid when the
corresponding pins are designated for general-purpose input/output by PMR5 and bits SGS3 to
SGS0 in LPCR.
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Upon reset, PCR5 is initialized to H'00.
PCR5 is a write-only register, which is always read as all 1s.
(3) Port Pull-Up Control Register 5 (PUCR5)
Bit
Initial value
Read/Write
7
PUCR5
0
R/W
6
PUCR5
0
R/W
5
PUCR5
0
R/W
4
PUCR5
0
R/W
3
PUCR5
0
R/W
0
PUCR5
0
R/W
2
PUCR5
0
R/W
1
PUCR5
0
R/W
76543210
PUCR5 controls whether the MOS pull-up of each of port 5 pins P57 to P50 is on or off. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR5 is initialized to H'00.
(4) Port Mode Register 5 (PMR5)
Bit 7 6 5 4 3 2 1 0
WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins.
Upon reset, PMR5 is initialized to H'00.
Bit n—P5n/WKPn/SEGn+1 Pin Function Switch (WKPn)
When pin P5n/WKPn/SEGn+1 is not used as SEGn+1, these bits select whether the pin is used as
P5n or WKPn.
Bit n
WKPn
Description
0 Functions as P5n I/O pin (initial value)
1 Functions as WKPn input pin
(n = 7 to 0)
Note: For use as SEGn+1, see section 13.2.1, LCD Port Control Register (LPCR).
Section 8 I/O Ports
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8.5.3 Pin Functions
Table 8.12 shows the port 5 pin functions.
Table 8.12 Port 5 Pin Functions
Pin Pin Functions and Selection Method
P57/WKP7/
SEG8 to
The pin function depends on bits WKP7 to WKP0 in PMR5, bits PCR57 to PCR50
in PCR5, and bits SGS3 to SGS0 in LPCR.
P50/WKP0/
SEG1
P57 to P54
(n = 7 to 4)
SGS3 to SGS0 Other than 0010, 0011, 0100, 0101, 0110,
0111, 1000, 1001
0010, 0011,
0100, 0101,
0110, 0111,
1000, 1001
WKPn 0 1 *
PCR5n 0 1 * *
Pin function P5n input pin P5n output pin WKPn input
pin
SEGn+1
output pin
P53 to P50 (m= 3 to 0)
SGS3 to SGS0 Other than 0001, 0010, 0011, 0100, 0101,
0110, 0111, 1000
0001, 0010,
0011, 0100,
0101, 0110,
0111, 1000
WKPm 0 1 *
PCR5m 0 1 * *
Pin function P5m input pin P5m output pin WKPm output
pin
SEGm+1
output pin
*: Don’t care
Section 8 I/O Ports
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8.5.4 Pin States
Table 8.13 shows the port 5 pin states in each operating mode.
Table 8.13 Port 5 Pin States
Pins Reset Sleep Subsleep Standby Watch Subactive Active
P57/WKP7/
SEG8 to P50/
WKP0/SEG1
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance*
Retains
previous
state
Functional Functional
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.5.5 MOS Input Pull-Up
Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5
bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin.
The MOS pull-up function is in the off state after a reset.
PCR5n 0 0 1
PUCR5n 0 1 *
MOS input pull-up Off On Off
(n = 7 to 0)
*: Don’t care
Section 8 I/O Ports
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8.6 Port 6
8.6.1 Overview
Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.5.
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Port 6
Figure 8.5 Port 6 Pin Configuration
8.6.2 Register Configuration and Description
Table 8.14 shows the port 6 register configuration.
Table 8.14 Port 6 Registers
Name Abbr. R/W Initial Value Address
Port data register 6 PDR6 R/W H'00 H'FFD9
Port control register 6 PCR6 W H'00 H'FFE9
Port pull-up control register 6 PUCR6 R/W H'00 H'FFE3
Section 8 I/O Ports
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(1) Port Data Register 6 (PDR6)
Bit
Initial value
Read/Write
7
P6
0
R/W
6
P6
0
R/W
5
P6
0
R/W
4
P6
0
R/W
3
P6
0
R/W
0
P6
0
R/W
2
P6
0
R/W
1
P6
0
R/W
2105476 3
PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60.
If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the
actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Upon reset, PDR6 is initialized to H'00.
(2) Port Control Register 6 (PCR6)
Bit
Initial value
Read/Write
7
PCR6
7
0
W
6
PCR6
6
0
W
5
PCR6
5
0
W
4
PCR6
4
0
W
3
PCR6
3
0
W
0
PCR6
0
0
W
2
PCR6
2
0
W
1
PCR6
1
0
W
PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an
input pin or output pin.
Setting a PCR6 bit to 1 makes the corresponding pin (P67 to P60) an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR6 and PDR6 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR6 is initialized to H'00.
PCR6 is a write-only register, which is always read as all 1s.
Section 8 I/O Ports
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(3) Port Pull-Up Control Register 6 (PUCR6)
Bit
Initial value
Read/Write
7
PUCR6
0
R/W
6
PUCR6
0
R/W
5
PUCR6
0
R/W
4
PUCR6
0
R/W
3
PUCR6
0
R/W
0
PUCR6
0
R/W
2
PUCR6
0
R/W
1
PUCR6
0
R/W
210
54376
PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When
a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR6 is initialized to H'00.
8.6.3 Pin Functions
Table 8.15 shows the port 6 pin functions.
Table 8.15 Port 6 Pin Functions
Pin Pin Functions and Selection Method
P67/SEG16 to
P60/SEG9
The pin function depends on bits PCR67 to PCR60 in PCR6 and bits SGS3 to
SGS0 in LPCR.
P67 to P64 (n = 7 to 4)
SGS3 to SGS0 Other than 0100, 0101, 0110, 0111,
1000, 1001, 1010, 1011
0100, 0101, 0110,
0111, 1000, 1001,
1010, 1011
PCR6n 0 1 *
Pin function P6n input pin P6n output pin SEGn+9 output pin
P63 to P60 (m = 3 to 0)
SGS3 to SGS0 Other than 0011, 0100, 0101, 0110,
0111, 1000, 1001, 1010
0011, 0100, 0101,
0110, 0111, 1000,
1001, 1010
PCR6m 0 1 *
Pin function P6m input pin P6m output pin SEGm+9 output pin
*: Don’t care
Section 8 I/O Ports
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8.6.4 Pin States
Table 8.16 shows the port 6 pin states in each operating mode.
Table 8.16 Port 6 Pin States
Pin Reset Sleep Subsleep Standby Watch Subactive Active
P67/SEG16 to
P60/SEG9
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance*
Retains
previous
state
Functional Functional
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.6.5 MOS Input Pull-Up
Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is
cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The
MOS pull-up function is in the off state after a reset.
PCR6n 0 0 1
PUCR6n 0 1 *
MOS input pull-up Off On Off
(n = 7 to 0)
*: Don’t care
Section 8 I/O Ports
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8.7 Port 7
8.7.1 Overview
Port 7 is an 8-bit I/O port, configured as shown in figure 8.6.
P7
7
/SEG
24
P7
6
/SEG
23
P7
5
/SEG
22
P7
4
/SEG
21
P7
3
/SEG
20
Port 7
P7
2
/SEG
19
P7
1
/SEG
18
P7
0
/SEG
17
Figure 8.6 Port 7 Pin Configuration
8.7.2 Register Configuration and Description
Table 8.17 shows the port 7 register configuration.
Table 8.17 Port 7 Registers
Name Abbr. R/W Initial Value Address
Port data register 7 PDR7 R/W H'00 H'FFDA
Port control register 7 PCR7 W H'00 H'FFEA
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(1) Port Data Register 7 (PDR7)
Bit
Initial value
Read/Write
7
P7
0
R/W
6
P7
0
R/W
5
P7
0
R/W
4
P7
0
R/W
3
P7
0
R/W
0
P7
0
R/W
2
P7
0
R/W
1
P7
0
R/W
76543210
PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7
bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is
read while PCR7 bits are cleared to 0, the pin states are read.
Upon reset, PDR7 is initialized to H'00.
(2) Port Control Register 7 (PCR7)
Bit
Initial value
Read/Write
7
PCR7
0
W
6
PCR7
0
W
5
PCR7
0
W
4
PCR7
0
W
3
PCR7
0
W
0
PCR7
0
W
2
PCR7
0
W
1
PCR7
0
W
76543210
PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an
input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR7 and PDR7 settings are valid when the
corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in
LPCR.
Upon reset, PCR7 is initialized to H'00.
PCR7 is a write-only register, which is always read as all 1s.
Section 8 I/O Ports
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8.7.3 Pin Functions
Table 8.18 shows the port 7 pin functions.
Table 8.18 Port 7 Pin Functions
Pin Pin Functions and Selection Method
P77/SEG24 to
P70/SEG17
The pin function depends on bits PCR77 to PCR70 in PCR7 and bits SGS3 to
SGS0 in LPCR.
P77 to P74 (n = 7 to 4)
SGS3 to SGS0 Other than 0110, 0111, 1000, 1001,
1010, 1011, 1100, 1101
0110, 0111, 1000,
1001, 1010, 1011,
1100, 1101
PCR7n 0 1 *
Pin function P7n input pin P7n output pin SEGn+17 output pin
P73 to P70 (m = 3 to 0)
SGS3 to SGS0 Other than 0101, 0110, 0111, 1000,
1001, 1010, 1011, 1100
0101, 0110, 0111,
1000, 1001, 1010,
1011, 1100
PCR7m 0 1 *
Pin function P7m input pin P7m output pin SEGm+17 output pin
*: Don’t care
8.7.4 Pin States
Table 8.19 shows the port 7 pin states in each operating mode.
Table 8.19 Port 7 Pin States
Pins Reset Sleep Subsleep Standby Watch Subactive Active
P77/SEG24 to
P70/SEG17
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance
Retains
previous
state
Functional Functional
Section 8 I/O Ports
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8.8 Port 8
8.8.1 Overview
Port 8 is an 8-bit I/O port configured as shown in figure 8.7.
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Port 8
Figure 8.7 Port 8 Pin Configuration
8.8.2 Register Configuration and Description
Table 8.20 shows the port 8 register configuration.
Table 8.20 Port 8 Registers
Name Abbr. R/W Initial Value Address
Port data register 8 PDR8 R/W H'00 H'FFDB
Port control register 8 PCR8 W H'00 H'FFEB
Section 8 I/O Ports
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(1) Port Data Register 8 (PDR8)
Bit
Initial value
Read/Write
7
P8
7
0
R/W
6
P8
6
0
R/W
5
P8
5
0
R/W
4
P8
4
0
R/W
3
P8
3
0
R/W
0
P8
0
R/W
2
P8
2
0
R/W
1
P8
1
0
R/W
0
PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8
bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is
read while PCR8 bits are cleared to 0, the pin states are read.
Upon reset, PDR8 is initialized to H'00.
(2) Port Control Register 8 (PCR8)
Bit
Initial value
Read/Write
7
PCR8
7
0
W
6
PCR8
6
0
W
5
PCR8
5
0
W
4
PCR8
4
0
W
3
PCR8
3
0
W
0
PCR8
0
0
W
2
PCR8
2
0
W
1
PCR8
1
0
W
PCR8 is an 8-bit register for controlling whether the port 8 pins P87 to P80 functions as an input or
output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR8 and PDR8 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR8 is initialized to H'00.
PCR8 is a write-only register, which is always read as all 1s.
Section 8 I/O Ports
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8.8.3 Pin Functions
Table 8.21 shows the port 8 pin functions.
Table 8.21 Port 8 Pin Functions
Pin Pin Functions and Selection Method
The pin function depends on bits PCR87 to PCR80 in PCR8 and bits SGS3 to SGS0
in LPCR.
P87 to P84 (n = 7 to 4)
P87/SEG32
to
P80/SEG25
SGS3 to SGS0 Other than 1000, 1001, 1010, 1011, 1100,
1101, 1110, 1111
1000, 1001, 1010,
1011, 1100, 1101,
1110, 1111
PCR8n 0 1 *
Pin function P8n input pin P8n output pin SEGn+25 output pin
P83 to P80 (m = 3 to 0)
SGS3 to SGS0 Other than 0111, 1000, 1001, 1010, 1011,
1100, 1101, 1110
0111, 1000, 1001,
1010, 1011, 1100,
1101, 1110
PCR8m 0 1 *
Pin function P8m input pin P8m output pin SEGm+25 output pin
*: Don’t care
8.8.4 Pin States
Table 8.22 shows the port 8 pin states in each operating mode.
Table 8.22 Port 8 Pin States
Pins Reset Sleep Subsleep Standby Watch Subactive Active
P87/SEG32 to
P80/SEG25
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance
Retains
previous
state
Functional Functional
Section 8 I/O Ports
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8.9 Port 9
8.9.1 Overview
Port 9 is a 6-bit output port, configured as shown in figure 8.8.
P9
5
P9
4
P9
3
/V
ref
P9
2
P9
1
/PWM
2
P9
0
/PWM
1
Port 9
Figure 8.8 Port 9 Pin Configuration
8.9.2 Register Configuration and Description
Table 8.23 shows the port 9 register configuration.
Table 8.23 Port 9 Registers
Name Abbr. R/W Initial Value Address
Port data register 9 PDR9 R/W H'FF H'FFDC
Port mode register 9 PMR9 R/W — H'FFEC
Section 8 I/O Ports
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(1) Port Data Register 9 (PDR9)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
P9
1
R/W
4
P9
1
R/W
3
P9
1
R/W
0
P9
1
R/W
2
P9
1
R/W
1
P9
1
R/W
543210
PDR9 is an 8-bit register that stores data for port 9 pins P95 to P90.
Upon reset, PDR9 is initialized to H'FF.
(2) Port Mode Register 9 (PMR9)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
1
3
0
R/W
0
PWM
1
0
R/W
2
W
1
PWM
2
0
R/W
PMR9 is an 8-bit read/write register controlling the selection of the P90 and P91 pin functions.
Bit 3—Reserved
This bit is reserved; it is readable/writable.
Bit 2—Reserved
This bit is reserved; it can only be written with 0.
Bits 1 and 0—P9n/PWM Pin Function Switches
These pins select whether pin P9n/PWMn+1 is used as P9n or as PWMn+1.
Bit n
PWMn+1
Description
0 Functions as P9n output pin (initial value)
1 Functions as PWMn+1 output pin
(n = 0 or 1)
Section 8 I/O Ports
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8.9.3 Pin Functions
Table 8.24 shows the port 9 pin functions.
Table 8.24 Port 9 Pin Functions
Pin Pin Functions and Selection Method
P93/Vref*
VREFSEL 0 1
Pin function P93 output pin Vref input pin
(n = 1 or 0) P91/PWMn+1 to
P9
0
/PWM
n+1 PMR9n 0 1
Pin function P9n output pin PWMn+1 output pin
Note: * The Vref pin is the input pin for the LVD’s external reference voltage.
8.9.4 Pin States
Table 8.25 shows the port 9 pin states in each operating mode.
Table 8.25 Port 9 Pin States
Pins Reset Sleep Subsleep Standby Watch Subactive Active
P95 to P92
P9n/PWMn+1 to
P9n/PWMn+1
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance
Retains
previous
state
Functional Functional
(n = 1 or 0)
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8.10 Port A
8.10.1 Overview
Port A is a 4-bit I/O port, configured as shown in figure 8.9.
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port A
Figure 8.9 Port A Pin Configuration
8.10.2 Register Configuration and Description
Table 8.26 shows the port A register configuration.
Table 8.26 Port A Registers
Name Abbr. R/W Initial Value Address
Port data register A PDRA R/W H'F0 H'FFDD
Port control register A PCRA W H'F0 H'FFED
(1) Port Data Register A (PDRA)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
1
3
PA
0
R/W
0
PA
0
R/W
2
PA
0
R/W
1
PA
0
R/W
3210
PDRA is an 8-bit register that stores data for port A pins PA3 to PA0. If port A is read while PCRA
bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If port A is
read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
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(2) Port Control Register A (PCRA)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
1
3
PCRA
0
W
0
PCRA
0
W
2
PCRA
0
W
1
PCRA
0
W
3210
PCRA controls whether each of port A pins PA3 to PA0 functions as an input pin or output pin.
Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin. PCRA and PDRA settings are valid when the corresponding pins are
designated for general-purpose input/output by LPCR.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register, which is always read as all 1s.
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8.10.3 Pin Functions
Table 8.27 shows the port A pin functions.
Table 8.27 Port A Pin Functions
Pin Pin Functions and Selection Method
PA3/COM4 The pin function depends on bit PCRA3 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0 0000 0000 Not 0000
PCRA3 0 1 *
Pin function PA3 input pin PA3 output pin COM4 output pin
PA2/COM3 The pin function depends on bit PCRA2 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0 0000 0000 Not 0000
PCRA2 0 1 *
Pin function PA2 input pin PA2 output pin COM3 output pin
PA1/COM2 The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0 0000 0000 Not 0000
PCRA1 0 1 *
Pin function PA1 input pin PA1 output pin COM2 output pin
PA0/COM1 The pin function depends on bit PCRA0 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0 0000 Not 0000
PCRA0 0 1 *
Pin function PA0 input pin PA0 output pin COM1 output pin
*: Don’t care
Section 8 I/O Ports
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8.10.4 Pin States
Table 8.28 shows the port A pin states in each operating mode.
Table 8.28 Port A Pin States
Pins Reset Sleep Subsleep Standby Watch Subactive Active
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
High-
impedance
Retains
previous
state
Retains
previous
state
High-
impedance
Retains
previous
state
Functional Functional
8.11 Port B
8.11.1 Overview
Port B is an 8-bit input-only port, configured as shown in figure 8.10.
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3/IRQ1/TMIC
PB2/AN2
PB1/AN1/extU
PB0/AN0/extD
Port B
Figure 8.10 Port B Pin Configuration
Section 8 I/O Ports
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8.11.2 Register Configuration and Description
Table 8.29 shows the port B register configuration.
Table 8.29 Port B Register
Name Abbr. R/W Initial Value Address
Port data register B PDRB R — H'FFDE
Port mode register B PMRB R/W H'F7 H'FFEE
(1) Port Data Register B (PDRB)
Bit
Read/Write
7
PB
7
R
6
PB
6
R
5
PB
5
R
4
PB
4
R
3
PB
R
0
PB
R
2
PB
R
1
PB
R
32 1 0
Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.
(2) Port Mode Register B (PMRB)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
1
3
IRQ1
0
R/W
0
1
2
1
1
1
PMRB is an 8-bit read/write register controlling the selection of the PB3 pin function. Upon reset,
PMRB is initialized to H'F7.
Bits 7 to 4 and 2 to 0—Reser ved
Bits 7 to 4 and 2 to 0 are reserved; they are always read as 1 and cannot be modified.
Section 8 I/O Ports
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Bit 3—PB3/AN3/IRQ1 Pin Function Switc h (IRQ1)
These bits select whether pin PB3/AN3/IRQ1 is used as PB3/AN3 or as IRQ1/TMIC.
Bit 3
IRQ1
Description
0 Functions as PB3/AN3 input pin (initial value)
1 Functions as IRQ1/TMIC input pin
Note: Rising or falling edge sensing can be selected for the IRQ1/TMIC pin.
For TMIC pin setting information, see the Timer Mode Register C (TMC) description in section
9.3.2, Register Descriptions.
Section 8 I/O Ports
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8.11.3 Pin Functions
Table 8.30 shows the port B pin functions.
Table 8.30 Port B Pin Functions
Pin Pin Functions and Selection Method
PB7/AN7 The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0 Not 1011 1011
Pin function PB7 input pin AN7 input pin
PB6/AN6 The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0 Not 1010 1010
Pin function PB6 input pin AN6 input pin
PB5/AN5 The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0 Not 1001 1001
Pin function PB5 input pin AN5 input pin
PB4/AN4 The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0 Not 1000 1000
Pin function PB4 input pin AN4 input pin
PB3/AN3/IRQ1/
TMIC
The pin function depends on bits CH3 to CH0 in AMR and bit IRQ1 in PMRB and
bits TMC2 to TMC0 in TMC.
IRQ1 0 1
CH3 to CH0 Not 0111 0111 *
TMC2 to TMC0 * Not 111 111
Pin function PB3 input pin AN3 input pin IRQ1 input pin TMIC input
pin
Note: When this pin is used as the TMIC input pin, clear IEN1 to 0 in IENR1 to
disable the IRQ1 interrupt.
PB2/AN2 The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0 Not 0110 0110
Pin function PB2 input pin AN2 input pin
Section 8 I/O Ports
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Pin Pin Functions and Selection Method
PB1/AN1/extU Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in
LVDCR as shown below.
VINTUSEL 0 1
CH3 to CH0 Not B'0101 B'0101 *
Pin function PB1 input pin AN1 input pin extU input pin
PB0/AN0/extD Switching is accomplished by combining CH3 to CH0 in AMR and VINTDSEL in
LVDCR as shown below.
VINTDSEL 0 1
CH3 to CH0 Not B'0100 B'0100 *
Pin function PB0 input pin AN0 input pin extD input pin
*: Don’t care
8.12 Input/Output Data Inversion Function
8.12.1 Overview
With input pin RXD32 and output pin TXD32, the data can be handled in inverted form.
SCINV2
RXD
32
P4
1
/RXD
32
SCINV3
TXD
32
P4
2
/TXD
32
Figure 8.11 Input/Output Data Inversion Function
Section 8 I/O Ports
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8.12.2 Register Configuration and Descriptions
Table 8.31 shows the registers used by the input/output data inversion function.
Table 8.31 Register Configuration
Name Abbr. R/W Address
Serial port control register SPCR R/W H'FF91
(1) Serial Port Control Register (SPCR)
Bit
Initial value
Read/Write
7
1
6
1
5
SPC32
0
R/W
4
W
3
SCINV3
0
R/W
0
W
2
SCINV2
0
R/W
1
W
SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data
inversion switching.
Bits 7 and 6—Reserved
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Bit 5—P42/TXD32 Pin Function Switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0 Functions as P42 I/O pin (initial value)
1 Functions as TXD32 output pin*
Note: * Set the TE bit in SCR3 after setting this bit to 1.
Bit 4—Reserved
Bit 4 is reserved; it can only be written with 0.
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Bit 3—TXD32 Pin Output Data Inversion Switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0 TXD32 output data is not inverted (initial value)
1 TXD32 output data is inverted
Bit 2—RXD32 Pin Input Data Inversion Switch
Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0 RXD32 input data is not inverted (initial value)
1 RXD32 input data is inverted
Bits 1 and 0—Reserved
Bits 1 and 0 are reserved; they can only be written with 0.
8.12.3 Note on Modification of Serial Port Control Register
When a serial port control register is modified, the data being input or output up to that point is
inverted immediately after the modification, and an invalid data change is input or output. When
modifying a serial port control register, do so in a state in which data changes are invalidated.
Section 8 I/O Ports
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8.13 Application Note
8.13.1 The Management of the Un-Use Terminal
If an I/O pin not used by the user system is floating, pull it up or down.
• If an unused pin is an input pin, handle it in one of the following ways:
Pull it up to VCC with an on-chip pull-up MOS.
Pull it up to VCC with an external resistor of approximately 100 kΩ.
Pull it down to VSS with an external resistor of approximately 100 kΩ.
For a pin also used by the A/D converter, pull it up to AVCC.
• If an unused pin is an output pin, handle it in one of the following ways:
Set the output of the unused pin to high and pull it up to VCC with an on-chip pull-up MOS.
Set the output of the unused pin to high and pull it up to VCC with an external resistor of
approximately 100 kΩ.
Set the output of the unused pin to low and pull it down to GND with an external resistor of
approximately 100 kΩ.
Section 8 I/O Ports
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Section 9 Timers
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Section 9 Timers
9.1 Overview
This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event
counter. The functions of these timers are outlined in table 9.1.
Table 9.1 Timer Functions
Name
Functions
Internal Clock Event
Input Pin Waveform
Output Pin
Remarks
Timer A • 8-bit timer — —
• Interval function
φ/8 to φ/8192
(8 choices)
• Time base φw/128 (choice of 4
overflow periods)
Timer C • 8-bit timer
• Interval function
• Event counting function
• Up-count/down-count
selectable
φ/4 to φ/8192, φW/4
(7 choices)
TMIC — Up-count/
down-count
controllable by
software or
hardware
Timer F • 16-bit timer
• Event counting function
• Also usable as two
independent 8-bit timers
• Output compare output
function
φ/4 to φ/32, φw/4
(4 choices)
TMIF TMOFL
TMOFH
Timer G • 8-bit timer
• Input capture function
• Interval function
φ/2 to φ/64, φW/4
(4 choices)
TMIG — Counter
clearing option
Built-in capture
input signal
noise canceler
Watchdog
timer
• Reset signal generated
when 8-bit counter
overflows
φ/64 to φ/8192
φW/32
On-chip oscillator
— —
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Name
Functions
Internal Clock Event
Input Pin Waveform
Output Pin
Remarks
Asynchro-
nous event
counter
• 16-bit counter
• Also usable as two
independent 8-bit
counters
• Counts events
asynchronous to φ and φw
• Can count asynchronous
events (rising/falling/both
edges) independ-ently of
the MCU's internal clock
φ/2 to φ/8
(3 choices)
AEVL
AEVH
IRQAEC
—
9.2 Timer A
9.2.1 Overview
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768 kHz crystal resonator is connected as the subclock.
(1) Features
Features of timer A are given below.
• Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32,
φ/8).
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal resonator is connected as the subclock).
• An interrupt is requested when the counter overflows.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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(2) Block Diagram
Figure 9.1 shows a block diagram of timer A.
φ
W
PSW
Internal data bus
PSS
[Legend]
1/4 TMA
TCA
φ/8192, φ/4096, φ/2048,
φ/512, φ/256, φ/128,
φ/32, φ/8
IRRT
A
+8*
+64*
+128*
+256*
φ
W
/4
φ
W
/128
TMA:
TCA:
IRRTA:
PSW:
PSS:
Note: * Can be selected only when the prescaler W output (φ
W
/128) is used as the TCA input clock.
Timer mode register A
Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S
φ
Figure 9.1 Block Diagram of Timer A
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(3) Register Configuration
Table 9.2 shows the register configuration of timer A.
Table 9.2 Timer A Registers
Name Abbr. R/W Initial Value Address
Timer mode register A TMA R/W — H'FFB0
Timer counter A TCA R H'00 H'FFB1
Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA
9.2.2 Register Descriptions
(1) Timer Mode Register A (TMA)
Bit
Initial value
Read/Write
7
W
6
W
5
W
4
1
3
TMA3
0
R/W
0
TMA0
0
R/W
2
TMA2
0
R/W
1
TMA1
0
R/W
TMA is an 8-bit read/write register for selecting the prescaler, and input clock.
Bits 7 to 5—Reserved
Bits 7 to 5 are reserved; only 0 can be written to these bits.
Bit 4—Reserved
Bit 4 is reserved; it is always read as 1, and cannot be modified.
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Bits 3 to 0—Internal Clock Select (TMA3 to TMA0)
Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Description
Bit 3
TMA3 Bit 2
TMA2 Bit 1
TMA1 Bit 0
TMA0 Prescaler and Divider Ratio
or Overflow Period
Function
0 0 0 0 PSS, φ/8192 (initial value) Interval timer
1 PSS, φ/4096
1 0 PSS, φ/2048
1 PSS, φ/512
1 0 0 PSS, φ/256
1 PSS, φ/128
1 0 PSS, φ/32
1 PSS, φ/8
1 0 0 0 PSW, 1 s Clock time
1 PSW, 0.5 s base
1 0 PSW, 0.25 s (when using
1 PSW, 0.03125 s 32.768 kHz)
1 0 0 PSW and TCA are reset
1
1 0
1
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(2) Timer Counter A (TCA)
Bit
Initial value
Read/Write
7
TCA7
0
R
6
TCA6
0
R
5
TCA5
0
R
4
TCA4
0
R
3
TCA3
0
R
0
TCA0
0
R
2
TCA2
0
R
1
TCA1
0
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
(3) Clock Stop Register 1 ( CKSTPR1)
TFCKSTP TCCKSTP TACKSTPS32CKSTP ADCKSTP TGCKSTP
76543210
11111111
R/W R/W R/W
R/W R/W R/W
Bit:
Initial value:
Read/Write:
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer A is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 0—Timer A Module Standby Mode Control (TACKSTP)
Bit 0 controls setting and clearing of module standby mode for timer A.
TACKSTP Description
0 Timer A is set to module standby mode
1 Timer A module standby mode is cleared (initial value)
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9.2.3 Timer Operation
(1) Interval Timer Operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
Note: * For details on interrupts, see section 3.3, Interrupts.
(2) Real-Time Clock Time Base Operation
When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting
clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and
TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting
bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00.
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9.2.4 Timer A Operation States
Table 9.3 summarizes the timer A operation states.
Table 9.3 Timer A Operation States
Operation Mode
Reset
Active
Sleep
Watch Sub-
active Sub-
sleep
Standby Module
Standby
TCA Interval Reset Functions Functions Halted Halted Halted Halted Halted
Clock time base Reset Functions Functions Functions Functions Functions Halted Halted
TMA Reset Functions Retained Retained Functions Retained Retained Retained
Note: When the real-time clock time base function is selected as the internal clock of TCA in
active mode or sleep mode, the internal clock is not synchronous with the system clock, so
it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s) in
the count cycle.
9.2.5 Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
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9.3 Timer C
9.3.1 Overview
Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This
timer has two operation modes, interval and auto reload.
(1) Features
Features of timer C are given below.
• Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φW/4) or an
external clock (can be used to count external events).
• An interrupt is requested when the counter overflows.
• Up/down-counter switching is possible by hardware or software.
• Subactive mode or subsleep mode operation is possible when φW/4 is selected as the internal
clock, or when an external clock is selected.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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(2) Block Diagram
Figure 9.2 shows a block diagram of timer C.
UD
φ
TMIC
φ
W
/4
PSS
TMC
Internal data bus
TCC
TLC
IRRTC
[Legend]
TMC:
TCC:
TLC:
IRRTC:
PSS:
Timer mode register C
Timer counter C
Timer load register C
Timer C overflow interrupt request flag
Prescaler S
Figure 9.2 Block Diagram of Timer C
(3) Pin Configuration
Table 9.4 shows the timer C pin configuration.
Table 9.4 Pin Configuration
Name Abbr. I/O Function
Timer C event input TMIC Input Input pin for event input to TCC
Timer C up/down select UD Input Timer C up/down-count selection
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(4) Register Configuration
Table 9.5 shows the register configuration of timer C.
Table 9.5 Timer C Registers
Name Abbr. R/W Initial Value Address
Timer mode register C TMC R/W H'18 H'FFB4
Timer counter C TCC R H'00 H'FFB5
Timer load register C TLC W H'00 H'FFB5
Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA
9.3.2 Register Descriptions
(1) Timer Mode Register C (TMC)
Bit
Initial value
Read/Write
7
TMC7
0
R/W
6
TMC6
0
R/W
5
TMC5
0
R/W
4
1
3
1
0
TMC0
0
R/W
2
TMC2
0
R/W
1
TMC1
0
R/W
TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and
performing up/down-counter control.
Upon reset, TMC is initialized to H'18.
Bit 7—Auto-Reload Function Select (TMC7)
Bit 7 selects whether timer C is used as an interval timer or auto-reload timer.
Bit 7
TMC7
Description
0 Interval timer function selected (initial value)
1 Auto-reload function selected
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Bits 6 and 5—Counter Up/Down Control (TMC6, TMC5)
Selects whether TCC up/down control is performed by hardware using UD pin input, or whether
TCC functions as an up-counter or a down-counter.
Bit 6
TMC6 Bit 5
TMC5
Description
0 0 TCC is an up-counter (initial value)
0 1 TCC is a down-counter
1 * Hardware control by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
*: Don't care
Bits 4 and 3—Reserved
Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified.
Bits 2 to 0—Clock Select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2
TMC2 Bit 1
TMC1 Bit 0
TMC0
Description
0 0 0 Internal clock: φ/8192 (initial value)
0 0 1 Internal clock: φ/2048
0 1 0 Internal clock: φ/512
0 1 1 Internal clock: φ/64
1 0 0 Internal clock: φ/16
1 0 1 Internal clock: φ/4
1 1 0 Internal clock: φW/4
1 1 1 External event (TMIC): rising or falling edge*
Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt
Control Registers, for details. IRQ1 in port mode register B (PMRB) must be set to 1
before setting 111 in bits TMC2 to TMC0.
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(2) Timer Counter C (TCC)
Bit
Initial value
Read/Write
7
TCC7
0
R
6
TCC6
0
R
5
TCC5
0
R
4
TCC4
0
R
3
TCC3
0
R
0
TCC0
0
R
2
TCC2
0
R
1
TCC1
0
R
TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal
clock or external event input. The clock source for input to this counter is selected by bits TMC2
to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to
H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.
TCC is allocated to the same address as TLC.
Upon reset, TCC is initialized to H'00.
(3) Timer Load Register C (TLC)
Bit
Initial value
Read/Write
7
TLC7
0
W
6
TLC6
0
W
5
TLC5
0
W
4
TLC4
0
W
3
TLC3
0
W
0
TLC0
0
W
2
TLC2
0
W
1
TLC1
0
W
TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC).
When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC
starts counting up/down from that value. When TCC overflows or underflows during operation in
auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow period can
be set within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
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(4) Clock Stop Register 1 ( CKSTPR1)
TFCKSTP TCCKSTP TACKSTPS32CKSTP ADCKSTP TGCKSTP
76543210
11111111
R/W R/W R/W
R/W R/W R/W
Bit:
Initial value:
Read/Write:
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer C is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 1—Timer C Module Standby Mode Control (TCCKSTP)
Bit 1 controls setting and clearing of module standby mode for timer C.
TCCKSTP Description
0 Timer C is set to module standby mode
1 Timer C module standby mode is cleared (initial value)
9.3.3 Timer Operation
(1) Interval Timer Operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit
interval timer.
Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an
interval up-counter without halting immediately after a reset. The timer C operating clock is
selected from seven internal clock signals output by prescalers S and W, or an external clock input
at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC.
TCC up/down-count control can be performed either by software or hardware. The selection is
made by bits TMC6 and TMC5 in TMC.
After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow
(underflow), setting bit IRRTC in IRR2 to 1. If IENTC = 1 in interrupt enable register 2 (IENR2),
a CPU interrupt is requested.
At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again.
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During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC),
the same value is set in TCC.
Note: For details on interrupts, see section 3.3, Interrupts.
(2) Auto-Reload Timer Operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a
reload value is set in TLC, the same value is loaded into TCC, becoming the value from which
TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that
value. The overflow/underflow period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in
TCC.
(3) Event Counter Operation
Timer C can operate as an event counter, counting rising or falling edges of an external event
signal input at pin TMIC. External event counting is selected by setting bits TMC2 to TMC0 in
timer mode register C (TMC) to all 1s (111). TCC counts up/down at the rising/falling edge of an
external event signal input at pin TMIC.
When timer C is used to count external event input, bit IRQ1 in PMRB should be set to 1 and bit
IEN1 in IENR1 cleared to 0 to disable interrupt IRQ1 requests.
(4) TCC Up/Down Control by Hardware
With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 in TMC
is set to 1, TCC functions as an up-counter when UD pin input is low, and as a down-counter
when high.
When using UD pin input, set bit UD in PMR3 to 1.
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9.3.4 Timer C Operation States
Table 9.6 summarizes the timer C operation states.
Table 9.6 Timer C Operation States
Operation Mode
Reset
Active
Sleep
Watch Sub-
active Sub-
sleep
Standby Module
Standby
TCC Interval Reset Functions Functions Halted Functions/
Halted*
Functions/
Halted*
Halted Halted
Auto reload Reset Functions Functions Halted Functions/
Halted*
Functions/
Halted*
Halted Halted
TMC Reset Functions Retained Retained Functions Retained Retained Retained
Note: * When φw/4 is selected as the TCC internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode or subsleep mode, either
select φw/4 as the internal clock or select an external clock. The counter will not operate
on any other internal clock. If φw/4 is selected as the internal clock for the counter when
φw/8 has been selected as subclock φSUB, the lower 2 bits of the counter operate on the
same cycle, and the operation of the least significant bit is unrelated to the operation of
the counter.
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9.4 Timer F
9.4.1 Overview
Timer F is a 16-bit timer with a built-in output compare function. As well as counting external
events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc.,
using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH
and timer FL).
(1) Features
Features of timer F are given below.
• Choice of four internal clock sources (φ/32, φ/16, φ/4, φw/4) or an external clock (can be used
as an external event counter)
• TMOFH/TMOFL pin toggle output provided using a single compare match signal (toggle
output initial value can be set)
• Counter resetting by a compare match signal
• Two interrupt sources: one compare match, one overflow
• Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode).
Timer FH 8-Bit Timer* Timer FL
8-Bit Timer/Event Counter
Internal clock Choice of 4 (φ/32, φ/16, φ/4, φw/4)
Event input — TMIF pin
Toggle output One compare match signal, output to
TMOFH pin(initial value settable)
One compare match signal, output to
TMOFL pin (initial value settable)
Counter reset Counter can be reset by compare match signal
Interrupt sources One compare match
One overflow
Note: * When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal.
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• Operation in watch mode, subactive mode, and subsleep mode
When φw/4 is selected as the internal clock, timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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(2) Block Diagram
Figure 9.3 shows a block diagram of timer F.
PSS
Toggle
circuit
Toggle
circuit
φ
TMIF
φ
W
/4
TMOFL
TMOFH
TCRF
TCFL
OCRFL
TCFH
OCRFH
TCSRF
Comparator
Comparator Match
IRRTFH
IRRTFL
[Legend]
TCRF:
TCSRF:
TCFH:
TCFL:
OCRFH:
OCRFL:
IRRTFH:
IRRTFL:
PSS:
Timer control register F
Timer control/status register F
8-bit timer counter FH
8-bit timer counter FL
Output compare register FH
Output compare register FL
Timer FH interrupt request flag
Timer FL interrupt request flag
Prescaler S
Internal data bus
Figure 9.3 Block Diagram of Timer F
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(3) Pin Configuration
Table 9.7 shows the timer F pin configuration.
Table 9.7 Pin Configuration
Name Abbr. I/O Function
Timer F event input TMIF Input Event input pin for input to TCFL
Timer FH output TMOFH Output Timer FH toggle output pin
Timer FL output TMOFL Output Timer FL toggle output pin
(4) Register Configuration
Table 9.8 shows the register configuration of timer F.
Table 9.8 Timer F Registers
Name Abbr. R/W Initial Value Address
Timer control register F TCRF W H'00 H'FFB6
Timer control/status register F TCSRF R/W H'00 H'FFB7
8-bit timer counter FH TCFH R/W H'00 H'FFB8
8-bit timer counter FL TCFL R/W H'00 H'FFB9
Output compare register FH OCRFH R/W H'FF H'FFBA
Output compare register FL OCRFL R/W H'FF H'FFBB
Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA
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9.4.2 Register Descriptions
(1) 16-bit Timer Counter (TCF)
8-bit Timer Counter (TCFH)
8-bit Timer Counter (TCFL)
15 14 13 12 11 10 9 8
TCF
TCFH TCFL
76543210
0000000000000000
R/W
Bit:
Initial value:
Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters
TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits
and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data
transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP,
see section 9.4.3, CPU Interface.
TCFH and TCFL are each initialized to H'00 upon reset.
a. 16-bit mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock
is selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an
interrupt request is sent to the CPU.
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b. 8-bit mode (TCFL/TCFH)
When CKSH2 is set to 1 in TCRF, TCFH, and TCFL operate as two independent 8-bit
counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to
CKSL0) in TCRF.
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL)
in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If
OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if
IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
(2) 16-bit Output Compare Register (OCRF)
8-bit Output Compare Register (OCRFH)
8-bit Output Compare Register (OCRFL)
15 14 13 12 11 10 9 8
OCRF
OCRFH OCRFL
76543210
1111111111111111
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
Read/Write:
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In
addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as
the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,
data transfer to and from the CPU is performed via a temporary register (TEMP). For details of
TEMP, see section 9.4.3, CPU Interface.
OCRFH and OCRFL are each initialized to H'FF upon reset.
a. 16-bit mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are
constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At
the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt
request is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and the
output level can be set (high or low) by means of TOLH in TCRF.
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b. 8-bit mode (OCRFH/OCRFL)
When CKSH2 is set to 1 in TCRF, OCRFH, and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL.
When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in
TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF.
(3) Timer Control Register F (TCRF)
TOLH CKSL2 CKSL1 CKSL0CKSH2 CKSH1 CKSH0 TOLL
76543210
00000000
WWWW
WWWW
Bit:
Initial value:
Read/Write:
TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the
input clock from among four internal clock sources or external event input, and sets the output
level of the TMOFH and TMOFL pins.
TCRF is initialized to H'00 upon reset.
Bit 7—Toggle Output Level H (TOLH)
Bit 7 sets the TMOFH pin output level. The output level is effective immediately after this bit is
written.
Bit 7
TOLH
Description
0 Low level (initial value)
1 High level
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Bits 6 to 4—Clock Select H (CKSH2 to CKSH0)
Bits 6 to 4 select the clock input to TCFH from amo ng four internal clock sources or TCFL
overflow.
Bit 6
CKSH2 Bit 5
CKSH1 Bit 4
CKSH0
Description
0 0 0 16-bit mode, counting on TCFL overflow si gnal (initial value)
0 0 1
0 1 0
0 1 1 Use prohibited
1 0 0 Internal clock: counting on φ/32
1 0 1 Internal clock: counting on φ/16
1 1 0 Internal clock: counting on φ/4
1 1 1 Internal clock: counting on φw/4
Bit 3—Toggle Output Level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immed iately after this bit is
written.
Bit 3
TOLL
Description
0 Low level (initial value)
1 High level
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Bits 2 to 0—Clock Select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external
event input.
Bit 2
CKSL2 Bit 1
CKSL1 Bit 0
CKSL0
Description
0 0 0
0 0 1
Counting on external event (TMIF) rising/falling edge*
(initial value)
0 1 0
0 1 1 Use prohibited
1 0 0 Internal clock: counting on φ/32
1 0 1 Internal clock: counting on φ/16
1 1 0 Internal clock: counting on φ/4
1 1 1 Internal clock: counting on φw/4
Note: * External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For
details, see IRQ Edge Select Register (IEGR) in section 3.3.2, Interrupt Control
Registers.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register
1 (PMR1) is changed from 0 to 1 or from 1 to 0 while the TMIF pin is low in order to
change the TMIF pin function.
(4) Timer Control/Status Register F (TCSRF)
OVFH CMFL OVIEL CCLRLCMFH OVIEH CCLRH OVFL
76543210
00000000
R/(W)*R/(W)*R/W R/W
R/(W)*R/W R/W R/(W)*
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
Bit:
Initial value:
Read/Write:
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
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Bit 7—Timer Overflow Flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
Description
0 Clearing condition: (initial value)
After reading OVFH = 1, cleared by writing 0 to OVFH
1 Setting condition:
Set when TCFH overflows from H’FF to H’00
Bit 6—Compare Match Flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
Description
0 Clearing condition: (initial value)
After reading CMFH = 1, cleared by writing 0 to CMFH
1 Setting condition:
Set when the TCFH value matches the OCRFH value
Bit 5—Timer Overflow Interrupt Enable H (OVIEH)
Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows.
Bit 5
OVIEH
Description
0 TCFH overflow interrupt request is disabled (initial value)
1 TCFH overflow interrupt request is enabled
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Bit 4—Counter Clear H (CCLRH)
In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Bit 4
CCLRH
Description
0 16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled (initial value)
1 16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Bit 3—Timer Overflow Flag L (OVFL)
Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 3
OVFL
Description
0 Clearing condition: (initial value)
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting condition:
Set when TCFL overflows from H’FF to H’00
Bit 2—Compare Match Flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL
Description
0 Clearing condition: (initial value)
After reading CMFL = 1, cleared by writing 0 to CMFL
1 Setting condition:
Set when the TCFL value matches the OCRFL value
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Bit 1—Timer Overflow Interrupt Enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
Description
0 TCFL overflow interrupt request is disabled (initial value)
1 TCFL overflow interrupt request is enabled
Bit 0—Counter Clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
Description
0 TCFL clearing by compare match is disabled (initial value)
1 TCFL clearing by compare match is enabled
(5) Clock Stop Register 1 ( CKSTPR1)
TFCKSTP TCCKSTP TACKSTPS32CKSTP ADCKSTP TGCKSTP
76543210
11111111
R/W R/W R/W
R/W R/W R/W
Bit:
Initial value:
Read/Write:
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 2—Timer F Module Standby Mode C on trol (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP Description
0 Timer F is set to module standby mode
1 Timer F module standby mode is cleared (initial value)
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9.4.3 CPU Interface
TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral
modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit
temporary register (TEMP).
When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be
transferred correctly if only the upper byte or only the lower byte is accessed. Access must be
performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte
must be accessed before the lower byte.
In 8-bit mode, there are no restrictions on the order of access.
(1) Write Access
Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next, write
access to the lower byte results in transfer of the data in TEMP to the upper register byte, and
direct transfer of the lower-byte write data to the lower register byte.
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Figure 9.4 shows an example in which H'AA55 is written to TCF.
Write to upper byte
CPU
(H'AA)
TEMP
(H'AA)
TCFH
( )
TCFL
( )
Bus
interface
Module data bus
Write to lower byte
CPU
(H'55)
TEMP
(H'AA)
TCFH
(H'AA)
TCFL
(H'55)
Bus
interface
Module data bus
Figure 9.4 Write Access to TCF (CPU → TCF)
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(2) Read Access
In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the
CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the
lower-byte data in TEMP is transferred to the CPU.
In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the
CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU.
Figure 9.5 shows an example in which TCF is read when it contains H'AAFF.
Read upper byte
CPU
(H'AA)
TEMP
(H'FF)
TCFH
(H'AA)
TCFL
(H'FF)
Bus
interface
Module data bus
Read lower byte
CPU
(H'FF)
TEMP
(H'FF)
TCFH
(AB)*
TCFL
(00)*
Bus
interface
Module data bus
Note: * H'AB00 if counter has been updated once.
Figure 9.5 Read Access to TCF (TCF → CPU)
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9.4.4 Operation
Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can
also function as two independent 8-bit timers.
(1) Timer F Operation
Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each
of these modes is described below.
a. Operation in 16-bit timer mode
When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit
timer.
Following a reset, timer counter F (TCF) is initialized to H'0000, output compare register F
(OCRF) to H'FFFF, and timer control register F (TCRF) and timer control/status register F
(TCSRF) to H'00. The counter starts incrementing on external event (TMIF) input. The
external event edge selection is set by IEG3 in the IRQ edge select register (IEGR).
The timer F operating clock can be selected from three internal clocks output by prescaler S or
an external clock by means of bits CKSL2 to CKSL0 in TCRF.
OCRF contents are constantly compared with TCF, and when both values match, CMFH is set
to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU,
and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared.
TMOFH pin output can also be set by TOLH in TCRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU.
b. Operation in 8-bit timer mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and
TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in
TCRF.
When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in
TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the
same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1,
TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in
TCRF.
When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If
OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is
sent to the CPU.
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(2) TCF Increment Timing
TCF is incremented by clock input (internal clock or external event input).
a. Internal clock operation
Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock
sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw).
b. External event operation
External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on either
the rising or falling edge of external event input. External event edge selection is set by IEG3
in the interrupt controller’s IEGR register. An external event pulse width of at least 2 system
clocks (φ) is necessary. Shorter pulses will not be counted correctly.
(3) TMOFH/TMOFL Output Timing
In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is
toggled by the occurrence of a compare match. Figure 9.6 shows the output timing.
φ
TMIF
(when IEG3 = 1)
Count input
clock
TCF
OCRF
TMOFH TMOFL
Compare match
signal
NN
NN
N+1 N+1
Figure 9.6 TMOFH/TMOFL Output Timing
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(4) TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
(5) Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
(6) Compare Match Flag Set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
(7) Timer F Operation Modes
Timer F operation modes are shown in table 9.9.
Table 9.9 Timer F Operation Modes
Operation Mode
Reset
Active
Sleep
Watch Sub-
active Sub-
sleep
Standby Module
Standby
TCF Reset Functions Functions Functions/
Halted*
Functions/
Halted*
Functions/
Halted*
Halted Halted
OCRF Reset Functions Held Held Functions Held Held Held
TCRF Reset Functions Held Held Functions Held Held Held
TCSRF Reset Functions Held Held Functions Held Held Held
Note: * When φw/4 is selected as the TCF internal clock in active mode or sleep mode, since the
system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, φw/4 must be selected as the internal clock. The counter will not operate if any
other internal clock is selected.
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9.4.5 Application Notes
The following types of contention and operation can occur when timer F is used.
(1) 16-bit Timer Mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match
signal is generated. If a TCRF write by a MOV instruction and generation of the compare match
signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF
write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin
should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
(2) 8-bit Timer Mode
a. TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not
output.
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b. TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write
by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLL data is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match
signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not
output.
(3) Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer
Overflow Flags H, L (OVFH, OVFL) and Compare Match Flags H, L (CMFH, CMFL)
When φw/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated
with φw and the signal will be outputted with φw width. And, “Overflow signal” and “Compare
match signal” are controlled with 2 cycles of φw signals. Those signals are outputted with 2 cycles
width of φw (figure 9.7)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt factor generation signal”, same interrupt request flag is set. (figure
9.7 (1)) And, you cannot be cleared timer overflow flag and compare match flag during the term
of validity of “Overflow signal” and “Compare match signal”.
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (figure 9.7 (2)) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the
longest number of execution states in used instruction. (10 states of RTE instruction when
MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In
subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.
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The term of validity of “Interrupt factor generation signal”
= 1 cycle of φw + waiting time for completion of executing instruction
+ interrupt time synchronized with φ = 1/φw + ST × (1/φ) + (2/φ) (second).....(1)
ST: Executing number of execution states
Method 1 is recommended to operate for time efficiency.
Method 1
1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0).
2. After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than that calculated with (1) formula.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
4. Operate interrupt permission (set IENFH, IENFL to 1).
Method 2
1. Set interrupt handling routine time to more than time that calculated with (1) formula.
2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16-bit mode and 8-bit mode.
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Program process
φW
Interrupt request flag
(IRRTFH, IRRTFL)
Interrupt factor
generation signal
(Internal signal,
nega-active)
Overflow signal,
Compare match signal
(Internal signal,
nega-active)
Interrupt Interrupt Normal
Interrupt request
flag clear Interrupt request
flag clear
(1)
(2)
Figure 9.7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid
(4) Timer Counter (TCF) Read/Write
When φw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on
TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually
asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF
read value error of ±1.
When read/write TCF in active (high-speed, medium-speed) mode is needed, please select internal
clock except for φw/4 before read/write.
In subactive mode, even φw/4 is selected as the internal clock, normal read/write TCF is possible.
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9.5 Timer G
9.5.1 Overview
Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of
pulses input from the input capture input pin (input capture input signal). High-frequency
component noise in the input capture input signal can be eliminated by a noise canceler, enabling
accurate measurement of the input capture input signal duty cycle. If input capture input is not set,
timer G functions as an 8-bit interval timer.
(1) Features
Features of timer G are given below.
• Choice of four internal clock sources (φ/64, φ/32, φ/2, φw/4)
• Dedicated input capture functions for rising and falling edges
• Level detection at counter overflow
It is possible to detect whether overflow occurred when the input capture input signal was high
or when it was low.
• Selection of whether or not the counter value is to be cleared at the input capture input signal
rising edge, falling edge, or both edges
• Two interrupt sources: one input capture, one overflow. The input capture input signal rising
or falling edge can be selected as the interrupt source.
• A built-in noise canceler eliminates high-frequency component noise in the input capture input
signal.
• Watch mode, subactive mode, or subsleep mode operation is possible when φw/4 is selected as
the internal clock.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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(2) Block Diagram
Figure 9.8 shows a block diagram of timer G.
PSS
TMG
ICRGF
TCG
ICRGR
Noise
canceler
Edge
detector
Level
detector
IRRTG
φ
φW/4
TMIG
NCS
[Legend]
TMG:
TCG:
ICRGF:
ICRGR:
IRRTG:
NCS:
PSS:
Timer mode register G
Timer counter G
Input capture register GF
Input capture register GR
Timer G interrupt request flag
Noise canceler select
Prescaler S
Internal data bus
Figure 9.8 Block Diagram of Timer G
(3) Pin Configuration
Table 9.10 shows the timer G pin configuration.
Table 9.10 Pin Configuration
Name Abbr. I/O Function
Input capture input TMIG Input Input capture input pin
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(4) Register Configuration
Table 9.11 shows the register configuration of timer G.
Table 9.11 Timer G Registers
Name Abbr. R/W Initial Value Address
Timer mode register G TMG R/W H'00 H'FFBC
Timer counter G TCG — H'00 —
Input capture register GF ICRGF R H'00 H'FFBD
Input capture register GR ICRGR R H'00 H'FFBE
Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA
9.5.2 Register Descriptions
(1) Timer Counter G (TCG)
TCG7 TCG2 TCG1 TCG0TCG6 TCG5 TCG4 TCG3
76543210
00000000
Bit:
Initial value:
Read/Write:
TCG is an 8-bit up-counter, which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
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(2) Input Capture Register GF (ICRGF)
ICRGF7 ICRGF2 ICRGF1 ICRGF0ICRGF6 ICRGF5 ICRGF4 ICRGF3
76543210
00000000
RRRR
RRRR
Bit:
Initial value:
Read/Write:
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φSUB (when the noise canceler is not used).
ICRGF is initialized to H'00 upon reset.
(3) Input Capture Register GR (ICRGR)
ICRGR7 ICRGR2 ICRGR1 ICRGR0ICRGR6 ICRGR5 ICRGR4 ICRGR3
76543210
00000000
RRRR
RRRR
Bit:
Initial value:
Read/Write:
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time,
IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φSUB (when the noise canceler is not used).
ICRGR is initialized to H'00 upon reset.
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(4) Timer Mode Register G (TMG)
OVFH CCLR0 CKS1 CKS0OVFL OVIE IIEGS CCLR1
76543210
00000000
R/(W)*R/W R/W R/W
R/(W)*R/W R/W R/W
Bit:
Initial value:
Read/Write:
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
Bit 7—Timer Overflow Flag H (OVFH)
Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH
Description
0 Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH (initial value)
1 Setting condition:
Set when input capture input signal is high level and TCG overflows from H'FF to H'00
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Bit 6—Timer Overflow Flag L (OVFL)
Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is low, or in interval operation. This flag is set by hardware and cleared by software. It
cannot be set by software.
Bit 6
OVFL
Description
0 Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL (initial value)
1 Setting condition:
Set when TCG overflows from H'FF to H'00 while input capture input signal is high
level or during interval operation
Bit 5—Timer Overflow Interrupt Enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE
Description
0 TCG overflow interrupt request is disabled (initial value)
1 TCG overflow interrupt request is enabled
Bit 4—Input Capture Interrupt Edge Select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS
Description
0 Interrupt generated on rising edge of input capture input signal (initial value)
1 Interrupt generated on falling edge of input capture input signal
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Bits 3 and 2—Counter Clea r 1 and 0 (C C L R1 , CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1 Bit 2
CCLR0
Description
0 0 TCG clearing is disabled (initial value)
0 1 TCG cleared by falling edge of input capture input signal
1 0 TCG cleared by rising edge of input capture input signal
1 1 TCG cleared by both edges of input capture input signal
Bits 1 and 0—Clock Select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
CKS1 Bit 0
CKS0
Description
0 0 Internal clock: counting on φ/64 (initial value)
0 1 Internal clock: counting on φ/32
1 0 Internal clock: counting on φ/2
1 1 Internal clock: counting on φw/4
(5) Clock Stop Register 1 ( CKSTPR1)
TFCKSTP TCCKSTP TACKSTPS32CKSTP ADCKSTP TGCKSTP
76543210
11111111
R/W R/W R/W
R/W R/W R/W
Bit:
Initial value:
Read/Write:
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.
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Bit 3—Timer G Module Standby Mode Control (TGCKSTP)
Bit 3 controls setting and clearing of module standby mode for timer G.
TGCKSTP Description
0 Timer G is set to module standby mode
1 Timer G module standby mode is cleared (initial value)
9.5.3 Noise Canceler
The noise canceler consists of a digital low-pass filter that eliminates high-frequency component
noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in
PMR2.
Figure 9.9 shows a block diagram of the noise canceler.
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
C
DQ
Latch
Match
detector
Noise
canceler
output
Sampling
clock
Input capture
input signal
Sampling clock
∆t
∆t: Set by CKS1 and CKS0
Figure 9.9 Noise Canceler Block Diagram
The noise canceler consists of five latch circuits connected in series and a match detector circuit.
When the noise cancellation function is not used (NCS = 0), the system clock is selected as the
sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the
internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the
rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If
all the outputs do not match, the previous value is retained. After a reset, the noise canceler output
is initialized when the falling edge of the input capture input signal has been sampled five times.
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Therefore, after making a setting for use of the noise cancellation function, a pulse with at least
five times the width of the sampling clock is a dependable input capture signal. Even if noise
cancellation is not used, an input capture input signal pulse width of at least 2φ or 2φSUB is
necessary to ensure that input capture operations are performed properly
Note: * An input capture signal may be generated when the NCS bit is modified.
Figure 9.10 shows an example of noise canceler timing.
In this example, high-level input of less than five times the width of the sampling clock at the
input capture input pin is eliminated as noise.
Input capture
input signal
Sampling clock
Noise canceler
output
Eliminated as noise
Figure 9.10 Noise Canceler Timing (Example)
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9.5.4 Operation
Timer G is an 8-bit timer with built-in input capture and interval functions.
(1) Timer G Functions
Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval
timer function.
The operation of these two functions is described below.
a. Input capture timer operation
When the TMIG bit in port mode register 1 (PMR1) is set to 1, timer G functions as an input
capture timer*.
In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF
(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.
Following a reset, TCG starts counting on the φ/64 internal clock.
The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in
TMG.
When a rising edge/falling edge is detected in the input capture signal input from the TMIG
pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected by
IIEGS in TMG is input, IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1 at this
time, an interrupt request is sent to the CPU. For details of the interrupt, see section 3.3,
Interrupts.
TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal,
according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the input
capture signal is high, the OVFH bit in TMG is set; if TCG overflows when the input capture
signal is low, the OVFL bit in TMG is set. If the OVIE bit in TMG is 1 when these bits are set,
IRRTG in IRR2 is set to 1, and if the IENTG bit in IENR2 is 1, timer G sends an interrupt
request to the CPU. For details of the interrupt, see section 3.3, Interrupts.
Timer G has a built-in noise canceler that enables high-frequency component noise to be
eliminated from pulses input from the TMIG pin. For details, see section 9.5.3, Noise
Canceler.
Note: * An input capture signal may be generated when TMIG is modified.
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b. Interval timer operation
When the TMIG bit in PMR1 is cleared to 0, timer G functions as an interval timer.
Following a reset, TCG starts counting on the φ/64 internal clock. The input clock can be
selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments
on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit in TMG is set to
1. If the OVIE bit in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if the IENTG bit in
IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see
section 3.3, Interrupts.
(2) Count Timing
TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four
internal clock sources (φ/64, φ/32, φ/2, or φw/4) created by dividing the system clock (φ) or watch
clock (φw).
(3) Input Capture Input Timing
a. Without noise cancellation function
For input capture input, dedicated input capture functions are provided for rising and falling
edges.
Figure 9.11 shows the timing for rising/falling edge input capture input.
Input capture
input signal
Input capture
signal F
Input capture
signal R
Figure 9.11 Input Capture Input Timing (without Noise Cancellation Function)
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b. With noise cancellation function
When noise cancellation is performed on the input capture input, the passage of the input
capture signal through the noise canceler results in a delay of five sampling clock cycles from
the input capture input signal edge.
Figure 9.12 shows the timing in this case.
Input capture
input signal
Sampling clock
Noise canceler
output
Input capture
signal R
Figure 9.12 Input Capture Input Timing (wit h Noise Cancellation Function)
(4) Timing of In put Capture by Inpu t Capture Input
Figure 9.13 shows the timing of input capture by input capture input
Input capture
signal
TCG N-1 N
NH'XX
N+1
Input capture
register
Figure 9.13 Timing of Inpu t Capture by Input Capture Input
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(5) TCG Clear Timing
TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input
signal.
Figure 9.14 shows the timing for clearing by both edges.
Input capture
input signal
Input capture
signal F
Input capture
signal R
TCG N NH'00 H'00
Figure 9.14 TCG Clear Timing
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(6) Timer G Operation Modes
Timer G operation modes are shown in table 9.12.
Table 9.12 Timer G Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby Module
Standby
TCG Input
capture
Reset Functions* Functions*Functions/
halted*
Functions/
halted*
Functions/
halted*
Halted Halted
Interval Reset Functions* Functions*Functions/
halted*
Functions/
halted*
Functions/
halted*
Halted Halted
ICRGF Reset Functions* Functions*Functions/
halted*
Functions/
halted*
Functions/
halted*
Retained Retained
ICRGR Reset Functions* Functions*Functions/
halted*
Functions/
halted*
Functions/
halted*
Retained Retained
TMG Reset Functions Retained Retained Functions Retained Retained Retained
Note: * When φw/4 is selected as the TCG internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ(s). When φw/4 is selected as the TCG internal clock in watch mode, TCG and the
noise canceler operate on the φw/4 internal clock without regard to the φSUB subclock
(φw/8, φw/4, φw/2). Note that when another internal clock is selected, TCG and the
noise canceler do not operate, and input of the input capture input signal does not result
in input capture.
To operate the timer G in subactive mode or subsleep mode, select φw/4 as the TCG
internal clock and φw/2 as the subclock φSUB. Note that when other internal clock is
selected, or when φw/8 or φw/4 is selected as the subclock φSUB, TCG and the noise
canceler do not operate.
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9.5.5 Application Notes
(1) Internal Clock Switchin g a nd T CG Operation
Depending on the timing, TCG may be incremented by a switch between different internal clock
sources. Table 9.13 shows the relation between internal clock switchover timing (by write to bits
CKS1 and CKS0) and TCG operation.
When TCG is internally clocked, an increment pulse is generated on detection of the falling edge
of an internal clock signal, which is divided from the system clock (φ) or subclock (φw). For this
reason, in a case like No. 3 in table 9.13 where the switch is from a high clock signal to a low
clock signal, the switchover is seen as a falling edge, causing TCG to increment.
Table 9.13 Internal Clock Switchin g a nd T CG Oper ation
No. Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
1 Goes from low level to low level
Clock before
switching
Clock after
switching
Count
clock
TCG N N+1
Write to CKS1 and CKS0
2 Goes from low level to high level
Clock before
switching
Clock after
switching
Count
clock
TCG N N+1 N+2
Write to CKS1 and CKS0
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No. Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
3 Goes from high level to low level
*
TCG N N+1 N+2
Clock before
switching
Clock after
switching
Count
clock
Write to CKS1 and CKS0
4 Goes from high level to high level
TCG N N+1 N+2
Clock before
switching
Clock after
switching
Count
clock
Write to CKS1 and CKS0
Note: * The switchover is seen as a falling edge, and TCG is incremented.
(2) Notes on Port Mode Register Modific atio n
The following points should be noted when a port mode register is modified to switch the input
capture function or the input capture input noise canceler function.
• Switching input capture input pin function
Note that when the pin function is switched by modifying TMIG in port mode register 1
(PMR1), which performs input capture input pin control, an edge will be regarded as having
been input at the pin even though no valid edge has actually been input. Input capture input
signal input edges, and the conditions for their occurrence, are summarized in table 9.14.
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Table 9.14 Input Capture Input Signal Input Edges Due to Input Capture Input Pin
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge When TMIG is modified from 0 to 1 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
Generation of falling edge When TMIG is modified from 1 to 0 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is low, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 1 to 0 after the signal is sampled five times by
the noise canceler
Note: When the P13 pin is not set as an input capture input pin, the timer G input capture input
signal is low.
• Switching input capture input noise canceler function
When performing noise canceler function switching by modifying NCS in port mode register 2
(PMR2), which controls the input capture input noise canceler, TMIG should first be cleared to
0. Note that if NCS is modified without first clearing TMIG, an edge will be regarded as
having been input at the pin even though no valid edge has actually been input. Input capture
input signal input edges, and the conditions for their occurrence, are summarized in table 9.15.
Table 9.15 Input Capture Input Signal Input Edges Due to Noise Canceler Function
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge When the TMIG pin is modified from 0 to 1 while TMIG is 1, then NCS
is modified from 0 to 1 before the signal is sampled five times by the
noise canceler
Generation of falling edge When the TMIG pin is modified from 1 to 0 while TMIG is 1, then NCS
is modified from 1 to 0 before the signal is sampled five times by the
noise canceler
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When the pin function is switched and an edge is generated in the input capture input signal, if this
edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt
request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use.
Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag
clearing. When switching the pin function, set the interrupt-disabled state before manipulating the
port mode register, then, after the port mode register operation has been performed, wait for the
time required to confirm the input capture input signal as an input capture signal (at least two
system clocks when the noise canceler is not used; at least five sampling clocks when the noise
canceler is used), before clearing the interrupt enable flag to 0. There are two ways of preventing
interrupt request flag setting when the pin function is switched: by controlling the pin level so that
the conditions shown in tables 9.14 and 9.15 are not satisfied, or by setting the opposite of the
generated edge in the IIEGS bit in TMG.
Set I bit in CCR to 1
Manipulate port mode register
*TMIG confirmation time
Clear interrupt request flag to 0
Clear I bit in CCR to 0
Disable interrupts. (Interrupts can also be disabled by
manipulating the interrupt enable bit in interrupt enable
register 2.)
After manipulating the port mode register, wait for the
TMIG confirmation time* (at least two system clocks when
the noise canceler is not used; at least five sampling
clocks when the noise canceler is used), then clear the
interrupt enable flag to 0.
Enable interrupts
Figure 9.15 Port Mode Register Manipulation and Interrupt Enable Flag Clearing
Procedure
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9.5.6 Timer G Application Example
Using timer G, it is possible to measure the high and low widths of the input capture input signal
as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1.
Figure 9.16 shows an example of the operation in this case.
Counter clearedTCG
H'FF
H'00
Input capture
input signal
Input capture
register GF
Input capture
register GR
Figure 9.16 Timer G Application Example
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9.6 Watchdog Timer
9.6.1 Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
(1) Features
Features of the watchdog timer are given below.
• Ten internal clocks (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φw/32, or
watchdog on-chip oscillator) are available for selection for use by the counter.
• A reset signal is generated when the counter overflows. The overflow period can be set from 1
to 256 times the selected clock (from approximately 4 ms to 1,000 ms when φ = 2.00 MHz).
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. See section 5.9, Module Standby Mode, for details.
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(2) Block Diagram
Figure 9.17 shows a block diagram of the watchdog timer.
TCSRW
TMW
TCW
Internal data bus
PSS
Watchdog
on-chip
oscillator
φ
φ
W
/32
Internal reset signal or
interrupt request signal
Interrupt/reset
controller
[Legend]
TCSRW:
TCW:
TMW:
PSS:
Timer control/status register W
Timer counter W
Timer mode register W
Prescaler S
Figure 9.17 Block Diagram of Watchdog Timer
(3) Register Configuration
Table 9.16 shows the register configuration of the watchdog timer.
Table 9.16 Watchdog Timer Registers
Name Abbr. R/W Initial Value Address
Timer control/status register W TCSRW R/W H'AA H'FFB2
Timer counter W TCW R/W H'00 H'FFB3
Timer mode register W TMW R/W H'FF H'FFF8
Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB
Port mode register 2 PMR2 R/W H'D8 H'FFC9
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9.6.2 Register Descriptions
(1) Timer Control/Status Register W (TCSRW)
Bit
Initial value
Read/Write
7
B6WI
1
R
6
TCWE
0
(R/W)
*
5
B4WI
1
R
4
TCSRWE
0
(R/W)
*
3
B2WI
1
R
0
WRST
0
(R/W)
*
2
WDON
1
(R/W)
*
1
B0WI
1
R
Note: * Write is enabled only under certain conditions, which are given in the descriptions
of the individual bits.
TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,
controls watchdog timer operations, and indicates operating status.
Bit 7—Bit 6 Write Disable (B6WI)
Bit 7 controls the writing of data to bit 6 in TCSRW.
Bit 7
B6WI
Description
0 Bit 6 is write-enabled
1 Bit 6 is write-protected (initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 6—Timer Counter W Write Enable (TCWE)
Bit 6 controls the writing of data to TCW.
Bit 6
TCWE
Description
0 Data cannot be written to TCW (initial value)
1 Data can be written to TCW
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Bit 5—Bit 4 Write Disable (B4WI)
Bit 5 controls the writing of data to bit 4 in TCSRW.
Bit 5
B4WI
Description
0 Bit 4 is write-enabled
1 Bit 4 is write-protected (initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 4—Timer Control/Status Register W Write Enable (TCSRWE)
Bit 4 controls the writing of data to bits 2 and 0 in TCSRW.
Bit 4
TCSRWE
Description
0 Data cannot be written to bits 2 and 0 (initial value)
1 Data can be written to bits 2 and 0
Bit 3—Bit 2 Write Inhibit (B2WI)
Bit 3 controls the writing of data to bit 2 in TCSRW.
Bit 3
B2WI
Description
0 Bit 2 is write-enabled
1 Bit 2 is write-protected (initial value)
This bit is always read as 1. Data written to this bit is not stored.
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Bit 2—Watchdog Timer On (WDON)
Bit 2 enables watchdog timer operation.
Bit 2
WDON
Description
0 Watchdog timer operation is disabled
Clearing condition:
When TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note
that a reset sets WDON to 1.
1 Watchdog timer operation is enabled
Setting condition:
Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and 1 is
written to WDON
(initial value)
Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 1—Bit 0 Write Inhibit (B0WI)
Bit 1 controls the writing of data to bit 0 in TCSRW.
Bit 1
B0WI
Description
0 Bit 0 is write-enabled
1 Bit 0 is write-protected (initial value)
This bit is always read as 1. Data written to this bit is not stored.
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Bit 0—Watchdog Timer Reset (WRST)
Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset
signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the
RES pin, or when software writes 0.
Bit 0
WRST
Description
0 Clearing conditions:
Reset by RES pin
When TCSRWE = 1, and 0 is written in both B0WI and WRST
1 Setting condition:
When TCW overflows and an internal reset signal is generated
(2) Timer Counter W (TCW)
Bit
Initial value
Read/Write
7
TCW7
0
R/W
6
TCW6
0
R/W
5
TCW5
0
R/W
4
TCW4
0
R/W
3
TCW3
0
R/W
0
TCW0
0
R/W
2
TCW2
0
R/W
1
TCW1
0
R/W
TCW is an 8-bit read/write up-counter that counts up by the internal clock. The clock source is
selected based on the timer mode register (TMW) setting if WDCKS is 0 and is φw/32 if WDCKS
is 1. TCW is always read or written to by the CPU.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
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(3) Timer Mode Register (TMW)
Bit 7 6 5 4 3 2 1 0
— — — — CKS3 CKS2 CKS1 CKS0
Initial value 1 1 1 1 1 1 1 1
Read/Write — — — — R/W R/W R/W R/W
The input clock is selected using combinations of CKS3 to CKS0.
Bits 7 to 4—Reserved
These bits are always read as 1.
Bits 3 to 0—Clock Select (CKS3 to CKS0)
These bits are used to select the clock input to TCW from among 10 internal options. Clock source
selection using this register is enabled when WDCKS in port mode register 2 (PMR2) is cleared to
0. If WDCKS is set to 1 the φw/32 clock source is selected, regardless of the settings of the bits in
this register.
Bit 3
CKS3 Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0
Description
1 0 0 0 Internal clock: φ/64 count
1 Internal clock: φ/128 count
1 0 Internal clock: φ/256 count
1 Internal clock: φ/512 count
1 0 0 Internal clock: φ/1024 count
1 Internal clock: φ/2048 count
1 0 Internal clock: φ/4096 count
1 Internal clock: φ/8192 count (initial value)
0 X X X Watchdog on-chip oscillator
Note: X: Don't care
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(4) Clock Stop Register 2 ( CKSTPR2)
LVDCKSTP
WDCKSTP
PW1CKSTP
LDCKSTP
PW2CKSTP
AECKSTP
76543210
11111111
R/W R/W R/W R/W
R/W R/W
Bit
Initial value
Read/Write
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the watchdog timer is described here. For details of the other bits,
see the sections on the relevant modules.
Bit 2—Watchdog Timer Module Standby Mode Control (WDCKSTP)
Bit 2 controls setting and clearing of module standby mode for the watchdog timer.
WDCKSTP Description
0 Watchdog timer is set to module standby mode
1 Watchdog timer module standby mode is cleared (initial value)
Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W
(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer
operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog
function and will not enter module standby mode. When the watchdog function ends and
WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the
watchdog timer will enter module standby mode.
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(5) Port Mode Register 2 (PMR2)
Bit 7 6 5 4 3 2 1 0
— — POF1 — — WDCKS NCS IRQ0
Initial value 1 1 0 1 1 0 0 0
Read/Write — — R/W — — R/W R/W R/W
PMR2 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 2.
Only the bit relating to the watchdog timer is described here. For details of the other bits, see
section 8, I/O Ports.
Bit 2—Watchdog Timer Source Clock Select (WDCKS)
This bit selects the watchdog timer source clock.
WDCKS Description
0 Selects clock based on timer mode register W (TMW) setting (initial value)
1 φw/32 selected
9.6.3 Timer Operation
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input
clock is selected by the WDCKS in port mode register 2 (PMR2). If WDCKS is cleared to 0 the
clock selection is specified by the setting of timer mode register W (TMW), and if WDCKS is set
to 1 the φw/32 clock source is selected. When TCSRWE = 1 in TCSRW, if 0 is written in B2WI
and 1 is simultaneously written in WDON, TCW starts counting up. (Write access to TCSRW is
required twice to turn on the watchdog timer. However, WDON is set to 1 after a reset is
cancelled, TCW starts to be incremented even without gaining write access to TCSRW.) When the
TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow, and
an internal reset signal is generated one base clock (φ or φSUB) cycle later. The internal reset signal
is output for 512 clock cycles of the φOSC clock. It is possible to write to TCW, causing TCW to
count up from the written value. The overflow period can be set in the range from 1 to 256 input
clocks, depending on the value written in TCW.
Figure 9.18 shows an example of watchdog timer operations.
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H'F8
TCW overflow
Start
H'F8 is written
in TCW
H'F8 is written in TCW Reset
Internal reset
signal
512 φ
OSC
clock cycles
H'FF
H'00
TCW count
value
Example: φ = 2 MHz and the desired overflow period is 30 ms.
The value set in TCW should therefore be 256 − 8 = 248 (H'F8).
2 • 10
6
• 30 • 10
−3
= 7.3
8192
Figure 9.18 Typical Watchdog Timer Operations (Example)
9.6.4 Watchdog Timer Operation States
Table 9.17 summarizes the watchdog timer operation states for the H8/38524 Group.
Table 9.17 Watchdog Timer Operation States
Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby Module
Standby
TCW Reset Functions Functions Functions/
Halted*1
Functions/
Halted*1
Functions/
Halted*1
Functions/
Halted*2
Halted
TCSRW Reset Functions Functions Functions/
Retained*1
Functions/
Halted*1
Functions/
Retained*1
Functions/
Retained*2
Retained
TMW Reset Functions Functions Functions/
Retained*1
Functions/
Halted*1
Functions/
Retained*1
Functions/
Retained*2
Retained
Notes: 1. Operates when φw/32 or the on-chip oscillator is selected as the internal clock.
2. Operates only when the on-chip oscillator is selected.
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9.7 Asynchronous Event Counter (AEC)
9.7.1 Overview
The asynchronous event counter is incremented by external event clock or internal clock input.
(1) Features
Features of the asynchronous event counter are given below.
• Can count asynchronous events
Can count external events input asynchronously without regard to the operation of base clocks
φ and φSUB.
The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
• Can also be used as two independent 8-bit event counter channels.
• Can be used as single-channel independent 16-bit event counter.
• Event/clock input is enabled only when IRQAEC is high or event counter PWM output
(IECPWM) is high.
• Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM)
interrupts. When the asynchronous counter is not used, independent interrupt function use is
possible.
• When an event counter PWM is used, event clock input enabling/disabling can be performed
automatically in a fixed cycle.
• External event input or a prescaler output clock can be selected by software for the ECH and
ECL clock sources. φ/2, φ/4, or φ/8 can be selected as the prescaler output clock.
• Both edge counting is possible for AEVL and AEVH.
• Counter resetting and halting of the count-up function controllable by software
• Automatic interrupt generation on detection of event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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(2) Block Diagram
Figure 9.19 shows a block diagram of the asynchronous event counter.
AEVH
AEVL
IRQAEC
IECPWM
ECCR
PSS
ECCSR
OVH
OVL
ECPWCRH
ECPWDRH
AEGSR
ECPWCRL
Internal data bus
ECPWDRL
ECH
(8 bits) CK
ECL
(8 bits) CK
IRREC
To CPU interrupt
(IRREC2)
Edge sensing
circuit
Edge sensing
circuit
Edge sensing
circuit
PWM waveform generator
φ
φ/2
φ/4, φ/8
φ
/2,
φ
/4,
φ
/8,
φ
/16,
φ
/32,
φ
/64
[Legend]
ECPWCRH: Event counter PWM compare register H
ECPWDRH: Event counter PWM data register H
AEGSR: Input pin edge select register
ECCSR: Event counter control/status register
ECH: Event counter H
ECL: Event counter L
ECPWCRL: Event counter PWM compare register L
ECPWDRL: Event counter PWM data register L
ECCR: Event counter control register
Figure 9.19 Block Diagram of Asynchr onous Event Counter
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(3) Pin Configuration
Table 9.18 shows the asynchronous event counter pin configuration.
Table 9.18 Pin Configuration
Name Abbr. I/O Function
Asynchronous event input H AEVH Input Event input pin for input to event counter H
Asynchronous event input L AEVL Input Event input pin for input to event counter L
Event input enable interrupt input IRQAEC Input Input pin for interrupt enabling event input
(4) Register Configuration
Table 9.19 shows the register configuration of the asynchronous event counter.
Table 9.19 Asynchronous Event Counter Registers
Name Abbr. R/W Initial Value Address
Event counter PWM compare register H ECPWCRH R/W H'FF H'FF8C
Event counter PWM compare register L ECPWCRL R/W H'FF H'FF8D
Event counter PWM data register H ECPWDRH W H'00 H'FF8E
Event counter PWM data register L ECPWDRL W H'00 H'FF8F
Input pin edge select register AEGSR R/W H'00 H'FF92
Event counter control register ECCR R/W H'00 H'FF94
Event counter control/status register ECCSR R/W H'00 H'FF95
Event counter H ECH R H'00 H'FF96
Event counter L ECL R H'00 H'FF97
Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB
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9.7.2 Register Configurations
(1) Event Counter PWM Compare Register H (ECPWCRH)
Bit
Initial value
Read/Write
7
ECPWCRH7
1
R/W
6
ECPWCRH6
1
R/W
5
ECPWCRH5
1
R/W
4
ECPWCRH4
1
R/W
3
ECPWCRH3
1
R/W
0
ECPWCRH0
1
R/W
2
ECPWCRH2
1
R/W
1
ECPWCRH1
1
R/W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH
should not be modified.
When changing the conversion period, event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRH.
ECPWCRH is an 8-bit read/write register that sets the event counter PWM waveform conversion
period.
(2) Event Counter PWM Compare Register L (ECPWCRL)
Bit
Initial value
Read/Write
7
ECPWCRL7
1
R/W
6
ECPWCRL6
1
R/W
5
ECPWCRL5
1
R/W
4
ECPWCRL4
1
R/W
3
ECPWCRL3
1
R/W
0
ECPWCRL0
1
R/W
2
ECPWCRL2
1
R/W
1
ECPWCRL1
1
R/W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRL
should not be modified.
When changing the conversion period, event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRL.
ECPWCRL is an 8-bit read/write register that sets the event counter PWM waveform conversion
period.
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(3) Event Counter PWM Data Register H (ECPWDRH)
Bit
Initial value
Read/Write
7
ECPWDRH7
0
W
6
ECPWDRH6
0
W
5
ECPWDRH5
0
W
4
ECPWDRH4
0
W
3
ECPWDRH3
0
W
0
ECPWDRH0
0
W
2
ECPWDRH2
0
W
1
ECPWDRH1
0
W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRH
should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying ECPWDRH.
ECPWDRH is an 8-bit write-only register that controls event counter PWM waveform generator
data.
(4) Event Counter PWM Data Register L (ECPWDRL)
Bit
Initial value
Read/Write
7
ECPWDRL7
0
W
6
ECPWDRL6
0
W
5
ECPWDRL5
0
W
4
ECPWDRL4
0
W
3
ECPWDRL3
0
W
0
ECPWDRL0
0
W
2
ECPWDRL2
0
W
1
ECPWDRL1
0
W
Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRL
should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying ECPWDRL.
ECPWDRL is an 8-bit write-only register that controls event counter PWM waveform generator
data.
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(5) Input Pin Edge Selection Register (AEGSR)
Bit
Initial value
Read/Write
7
AHEGS1
0
R/W
6
AHEGS0
0
R/W
5
ALEGS1
0
R/W
4
ALEGS0
0
R/W
3
AIEGS1
0
R/W
0
—
0
R/W
2
AIEGS0
0
R/W
1
ECPWME
0
R/W
AEGSR is an 8-bit read/write register that selects rising, falling, or both edge sensing for the
AEVH, AEVL, and IRQAEC pins.
Bits 7 and 6—AEC Edge Select H
Bits 7 and 6 select rising, falling, or both edge sensing for the AEVH pin.
Bit 7
AHEGS1 Bit 6
AHEGS0
Description
0 0 Falling edge on AEVH pin is sensed (initial value)
1 Rising edge on AEVH pin is sensed
1 0 Both edges on AEVH pin are sensed
1 Use prohibited
Bits 5 and 4—AEC Edge Select L
Bits 5 and 4 select rising, falling, or both edge sensing for the AEVL pin.
Bit 5
ALEGS1 Bit 4
ALEGS0
Description
0 0 Falling edge on AEVL pin is sensed (initial value)
1 Rising edge on AEVL pin is sensed
1 0 Both edges on AEVL pin are sensed
1 Use prohibited
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Bits 3 and 2—IRQAEC Edge Select
Bits 3 and 2 select rising, falling, or both edge sensing for the IRQAEC pin.
Bit 3
AIEGS1 Bit 2
AIEGS0
Description
0 0 Falling edge on IRQAEC pin is sensed (initial value)
1 Rising edge on IRQAEC pin is sensed
1 0 Both edges on IRQAEC pin are sensed
1 Use prohibited
Bit 1—Event Counter PWM Enable
Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC.
Bit 1
ECPWME
Description
0 AEC PWM halted, IRQAEC selected (initial value)
1 AEC PWM operation enabled, IRQAEC deselected
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
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(6) Event Counter Control Register (ECCR)
Bit
Initial value
Read/Write
7
ACKH1
0
R/W
6
ACKH0
0
R/W
5
ACKL1
0
R/W
4
ACKL0
0
R/W
3
PWCK2
0
R/W
0
0
R/W
2
PWCK1
0
R/W
1
PWCK0
0
R/W
ECCR performs counter input clock and IRQAEC/IECPWM control.
Bits 7 and 6—AEC Clock Select H (ACKH1, ACKH0)
Bits 7 and 6 select the clock used by ECH.
Bit 7
ACKH1 Bit 6
ACKH0
Description
0 0 AEVH pin input (initial value)
1 φ/2
1 0 φ/4
1 φ/8
Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0)
Bits 5 and 4 select the clock used by ECL.
Bit 5
ACKL1 Bit 4
ACKL0
Description
0 0 AEVL pin input (initial value)
1 φ/2
1 0 φ/4
1 φ/8
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Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0)
Bits 3 to 1 select the event counter PWM clock.
Bit 3
PWCK2 Bit 2
PWCK1 Bit 1
PWCK0
Description
0 0 0 φ/2 (initial value)
1 φ/4
1 0 φ/8
1 φ/16
1 * 0 φ/32
1 φ/64
*: Don’t care
Bit 0—Reserved
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
(7) Event Counter Control/Status Regis ter (ECC SR )
OVH CUEL CRCH CRCLOVL CH2 CUEH
76543210
00000000
R/W*R/W R/W R/W
R/W*R/W R/W R/W
Bit
Note:
*
Bits 7 and 6 can only be written with 0, for flag clearing.
Initial Value
Read/Write
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
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Bit 7—Counter Overflow H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by reading
it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as
a status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
Description
0 ECH has not overflowed (initial value)
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
1 ECH has overflowed
Setting condition:
Set when ECH overflows from H’FF to H’00
Bit 6—Counter Overflow L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by reading
it when set to 1, then writing 0.
Bit 6
OVL
Description
0 ECL has not overflowed (initial value)
Clearing condition:
After reading OVL = 1, cleared by writing 0 to OVL
1 ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00
Bit 5—Reserved
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
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Bit 4—Channel Select (CH2)
Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two
independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a
16-bit event counter which is incremented each time an event clock is input to the AEVL pin. In
this case, the overflow signal from ECL is selected as the ECH input clock. When CH2 is set to 1,
ECH and ECL function as independent 8-bit event counters which are incremented each time an
event clock is input to the AEVH or AEVL pin, respectively.
Bit 4
CH2
Description
0 ECH and ECL are used together as a single-channel 16-bit event counter
(initial value)
1 ECH and ECL are used as two independent 8-bit event counter channels
Bit 3—Count-up Enable H (CUEH)
Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock
source by bit CH2.
Bit 3
CUEH
Description
0 ECH event clock input is disabled (initial value)
ECH value is held
1 ECH event clock input is enabled
Bit 2—Count-up Enable L (CUEL)
Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL
Description
0 ECL event clock input is disabled (initial value)
ECL value is held
1 ECL event clock input is enabled
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Bit 1—Counter Reset Control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
Description
0 ECH is reset (initial value)
1 ECH reset is cleared and count-up function is enabled
Bit 0—Counter Reset Control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enab led.
Bit 0
CRCL
Description
0 ECL is reset (initial value)
1 ECL reset is cleared and count-up function is enabled
(8) Event Counter H (ECH)
ECH7 ECH2 ECH1 ECH0ECH6 ECH5 ECH4 ECH3
76543210
00000000
RRRR
RRRR
Bit
Initial Value
Read/Write
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. The
external asynchronous even t AEVH pin, φ/2, φ/4, φ/8, or the overflow signal from lower 8-bit
counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software,
and is also initialized to H'00 upon reset.
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(9) Event Counter L (ECL)
ECL7 ECL2 ECL1 ECL0ECL6 ECL5 ECL4 ECL3
76543210
00000000
RRRR
RRRR
Bit
Initial Value
Read/Write
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin, φ/2, φ/4, or φ/8 is used as the input
clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
(10) Clock Sto p Register 2 (CKSTPR2)
LVDCKSTP
WDCKSTP
PW1CKSTP
LDCKSTP
PW2CKSTP
AECKSTP
76543210
11111111
R/W
R/W R/W R/W
R/W R/W
Bit
Initial value
Read/Write
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3—Asynchronous Event Counter Module Standby Mode Control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP Description
0 Asynchronous event counter is set to module standby mode
1 Asynchronous event counter module standby mode is cleared (initial value)
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9.7.3 Operation
(1) 16-bit Event Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter.
Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR.
When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.20 shows an example of the software processing when ECH and ECL are used as
a 16-bit event counter.
Start
End
Clear CH2 to 0
Set ACKL1, ACKL0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
Figure 9.20 Example of S oftw are Proce ssi ng when Using ECH and ECL as 16-Bit Event
Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset,
and as ACKL1 and ACKL0 are cleared to 00, the operating clock is asynchronous event input
from the AEVL pin (using falling edge sensing). When the next clock is input after the count
value reaches H'FF in both ECH and ECL, ECH and ECL overflow from H'FFFF to H'0000, the
OVH flag is set to 1 in ECCSR, the ECH and ECL count values each return to H'00, and counting
up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
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(2) 8-bit Event Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of
bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the
input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and
with bits ALEGS1 and ALEGS0 when AEVL pin input is selected.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.21 shows an example of the software processing when ECH and ECL are used as
8-bit event counters.
Start
End
Set CH2 to 1
Set ACKH1, ACKH0, ACKL1, ACKL0, AHEGS1,
AHEGS0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
Figure 9.21 Example of Sof tw are Proce ssi ng when Using ECH and E CL as 8-B it E vent
Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9.21. When the next clock is input after the ECH count value reaches
H'FF, ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00,
and counting up is restarted. Similarly, when the next clock is input after the ECL count value
reaches H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to
H'00, and counting up is restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the
IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
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(3) IRQAEC Operation
When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC
is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and
ECL do not count. ECH and ECL count operations can therefore be controlled from outside by
controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually.
IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector
addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin, with bits AIAGS1
and AIAGS0 in AEGSR.
Note: The control of switching between the system clock oscillator and the on-chip oscillator
during resets should be performed by setting the IRQAEC input level. Refer to section 4,
Clock Pulse Generators, for details.
(4) Event Counter PWM Operation
When ECPWME in AEGSR is 1, the ECH and ECL input clocks are enabled only when event
counter PWM output (IECPWM) is high. When IECPWM is low, the input clocks are not input to
the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled cyclically from outside by controlling event counter PWM. In this case, ECH and ECL
cannot be controlled individually.
IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the
vector addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIAGS1 and AIAGS0 in AEGSR.
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Figure 9.22 and table 9.20 show examples of event counter PWM operation.
t
off
= T × (N
dr
+1)
t
on
t
cm
= T × (N
cm
+1)
T
on
: Clock input enabled time
T
off
: Clock input disabled time
T
cm
: One conversion period
T : ECPWM input clock cycle
N
dr
: Value of ECPWDRH and ECPWDRL
Fixed low when Ndr = H'FFFF
N
cm
: Value of ECPWCRH and ECPWCRL
Figure 9.22 Event Counter Operation Waveform
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this condition,
do not set ECPWME in AEGSR to 1.
Table 9.20 Examples of Event Counte r PWM O per ation
Conditions: fosc = 4 MHz, fφ = 2 MHz, high-speed active mode, ECPWCR value (Ncm) = H'7A11,
ECPWDR value (Ndr) = H'16E3
Clock Source
Selection Clock Source
Cycle (T)* ECPWCR
Value (Ncm) ECPWDR
Value (Ndr) toff = T ×
(Ndr + 1) tcm = T ×
(Ncm + 1)
ton = tcm – toff
φ/2 1 µs 5.86 ms 31.25 ms 25.39 ms
φ/4 2 µs
H'7A11
D'31249
H'16E3
D'5859 11.72 ms 62.5 ms 50.78 ms
φ/8 4 µs 23.44 ms 125.0 ms 101.56 ms
φ/16 8 µs 46.88 ms 250.0 ms 203.12 ms
φ/32 16 µs 93.76 ms 500.0 ms 406.24 ms
φ/64 32 µs 187.52 ms 1000.0 ms 812.48 ms
Note: * t
off minimum width
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(5) Clock Input Enable/Disable Function Operation
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by event counter PWM output IECPWM when ECPWME in AEGSR is 1. As
this function forcibly terminates the clock input by each signal, a maximum error of one count will
occur depending the IRQAEC or IECPWM timing.
Figure 9.23 shows an example of the operation of this function.
Clock stopped
N+2 N+3 N+4 N+5 N+6N N+1
Edge generated by clock return
Input event
IRQAEC or
IECPWM
A
ctually counted
clock source
Counter value
Figure 9.23 Example of Cl ock C on trol O pera ti on
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9.7.4 Asynchronous Event Counter Operation Modes
Asynchronous event counter operation modes are shown in table 9.21.
Table 9.21 Asynchronous Event Counter Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby Module
Standby
AEGSR Reset Functions Functions Retained*1 Functions Functions Retained*1 Retained
ECCR Reset Functions Functions Retained*1 Functions Functions Retained*1 Retained
ECCSR Reset Functions Functions Retained*1 Functions Functions Retained*1 Retained
ECH Reset Functions Functions Functions*1*2Functions*2Functions*2Functions*1*2 Halted
ECL Reset Functions Functions Functions*1*2Functions*2Functions*2Functions*1*2 Halted
IRQAEC Reset Functions Functions Retained*3 Functions Functions Retained*3 Retained*4
Event
counter
PWM
Reset Functions Functions Retained Retained Retained Retained Retained
Notes: 1. When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
2. Operates when asynchronous external events are selected; halted and retained
otherwise.
3. Clock control by IRQAEC operates, but interrupts do not.
4. As the clock is stopped in module standby mode, IRQAEC has no effect.
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9.7.5 Application Notes
1. When reading the values in ECH and ECL, the correct value will not be returned if the event
counter increments during the read operation. Therefore, if the counter is being used in the 8-
bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the
counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL.
2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and
ensure that the high and low widths of the clock are at least half the OSC clock cycle duration.
The duty cycle is immaterial.
Mode Maximum AEVH/AEVL Pin Input
Clock Frequency
Active (high-speed), sleep (high-speed) 16 MHz
Active (medium-speed), sleep (medium-speed) (φ/16)
(φ/32)
(φ/64)
fOSC = 1 MHz to 4 MHz (φ/128)
2 • fOSC
fOSC
1/2 • fOSC
1/4 • fOSC
Watch, subactive, subsleep, standby (φw/2)
(φw/4)
φw = 32.768 kHz (φw/8)
1000 kHz
500 kHz
250 kHz
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL
and CRCH to 0 sequentially, in that order.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
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Section 10 Serial Communication Interface
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Section 10 Serial Communication Interface
10.1 Overview
This LSI is provided with one serial communication interface, SCI3.
Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode.
10.1.1 Features
Features of SCI3 are listed below.
• Choice of asynchronous or synchronous mode for serial data communication
Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA).
There is a choice of 16 data transfer formats.
Data length 7, 8, 5 bits
Stop bit length 1 or 2 bits
Parity Even, odd, or none
Receive error detection Parity, overrun, and framing errors
Break detection Break detected by reading the RXD32 pin level directly when a
framing error occurs
Synchronous mode
Serial data communication is synchronized with a clock. In this mode, serial data can be
exchanged with another LSI that has a synchronous communication function.
Data length 8 bits
Receive error detection Overrun errors
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• Full-duplex communication
Separate transmission and reception units are provided, enabling transmission and reception to
be carried out simultaneously. The transmission and reception units are both double-buffered,
allowing continuous transmission and reception.
• On-chip baud rate generator, allowing any desired bit rate to be selected
• Choice of an internal or external clock as the transmit/receive clock source
• Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error,
framing error, and parity error
Note: The system clock generator must be used when carrying out this function.
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10.1.2 Block Diagram
Figure 10.1 shows a block diagram of SCI3.
Clock
TXD
32
RXD
32
SCK
BRR
SMR
SCR3
SSR
TDR
RDR
TSR
RSR
SPCR
Transmit/receive
control circuit
Internal data bus
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
SPCR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Serial port control register
Interrupt request
(TEI, TXI, RXI, ERI)
32
Internal clock (φ/64, φ/16, φW/2, φ)
External
clock
BRC
Baud rate generator
Figure 10.1 SCI3 Block Diagram
Section 10 Serial Communication Interface
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10.1.3 Pin Configuration
Table 10.1 shows the SCI3 pin configuration.
Table 10.1 Pin Configuration
Name Abbr. I/O Function
SCI3 clock SCK32 I/O SCI3 clock input/output
SCI3 receive data input RXD32 Input SCI3 receive data input
SCI3 transmit data output TXD32 Output SCI3 transmit data output
10.1.4 Register Configuration
Table 10.2 shows the SCI3 register configuration.
Table 10.2 Registers
Name Abbr. R/W Initial Value Address
Serial mode register SMR R/W H'00 H'FFA8
Bit rate register BRR R/W H'FF H'FFA9
Serial control register 3 SCR3 R/W H'00 H'FFAA
Transmit data register TDR R/W H'FF H'FFAB
Serial status register SSR R/W H'84 H'FFAC
Receive data register RDR R H'00 H'FFAD
Transmit shift register TSR Protected — —
Receive shift register RSR Protected — —
Bit rate counter BRC Protected — —
Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA
Serial port control register SPCR R/W — H'FF91
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10.2 Register Descriptions
10.2.1 Receive Shift Register (RSR)
Bit
Read/Write
7
6
5
4
3
0
2
1
RSR is a register used to receive serial data. Serial data input to RSR from the RXD32 pin is set in
the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
When one byte of data is received, it is transferred to RDR automatically.
RSR cannot be read or written directly by the CPU.
10.2.2 Receive Data Register (RDR)
Bit
Initial value
Read/Write
7
RDR7
0
R
6
RDR6
0
R
5
RDR5
0
R
4
RDR4
0
R
3
RDR3
0
R
0
RDR0
0
R
2
RDR2
0
R
1
RDR1
0
R
RDR is an 8-bit register that stores received serial data.
When reception of one byte of data is finished, the received data is transferred from RSR to RDR,
and the receive operation is completed. RSR is then able to receive data. RSR and RDR are
double-buffered, allowing consecutive receive operations.
RDR is a read-only register, and cannot be written by the CPU.
RDR is initialized to H'00 upon reset, and in standby, module standby or watch mode.
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10.2.3 Transmit Shift Register (TSR)
Bit
Read/Write
7
6
5
4
3
0
2
1
TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR,
and serial data transmission is carried out by sending the data to the TXD32 pin in order, starting
from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is
transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is not
performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status register
(SSR)).
TSR cannot be read or written directly by the CPU.
10.2.4 Transmit Da t a Regi s ter (T DR )
Bit
Initial value
Read/Write
7
TDR7
1
R/W
6
TDR6
1
R/W
5
TDR5
1
R/W
4
TDR4
1
R/W
3
TDR3
1
R/W
0
TDR0
1
R/W
2
TDR2
1
R/W
1
TDR1
1
R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
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10.2.5 Serial Mode Regis ter (S M R)
Bit
Initial value
Read/Write
7
COM
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
PM
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, module standby, or watch mode.
Bit 7—Communication Mode (COM)
Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode.
Bit 7
COM
Description
0 Asynchronous mode (initial value)
1 Synchronous mode
Bit 6—Character Length (CHR)
Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous
mode the data length is always 8 bits, irrespective of the bit 6 setting.
Bit 6
CHR
Description
0 8-bit data/5-bit data*2 (initial value)
1 7-bit data*1/5-bit data*2
Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
2. When 5-bit data is selected, set both PE and MP to 1. The three most significant bits
(bits 7, 6, and 5) of TDR are not transmitted.
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Bit 5—Parity Enable (PE)
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,
irrespective of the bit 5 setting.
Bit 5
PE
Description
0 Parity bit addition and checking disabled*2 (initial value)
1 Parity bit addition and checking enabled*1/*2
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
2. For the case where 5-bit data is selected, see table 10.11.
Bit 4—Parity Mode (PM)
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity
bit addition and checking is disabled.
Bit 4
PM
Description
0 Even parity*1 (initial value)
1 Odd parity*2
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
2. When odd parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
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Bit 3—Stop Bit Length (STOP)
Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is
only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is
invalid since stop bits are not added.
Bit 3
STOP
Description
0 1 stop bit*1 (initial value)
1 2 stop bits*2
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2— 5-Bit Communication (MP)
When this bit is set to 1, the 5-bit communication format is enabled. When writing 1 to this bit,
always write 1 to bit 5 (RE) at the same time.
Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see section
10.2.8, Bit rate register (BRR).
Bit 1
CKS1 Bit 0
CKS0
Description
0 0 φ clock (initial value)
0 1 φ w/2 clock*1/φ w clock*2
1 0 φ/16 clock
1 1 φ/64 clock
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode. In subactive or subsleep mode, SCI3
can be operated when CPU clock is φw/2 only.
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10.2.6 Serial Control Register 3 (SCR3)
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode.
Bit 7—Transmit Interrupt Enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7
TIE
Description
0 Transmit data empty interrupt request (TXI) disabled (initial value)
1 Transmit data empty interrupt request (TXI) enabled
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Bit 6—Receive Interrupt Enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive errors: overrun, framing, and parity.
RXI and ERI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
Bit 6
RIE
Description
0 Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
(initial
value)
1 Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
Bit 5—Transmit Enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
Description
0 Transmit operation disabled*1 (TXD32 pin is I/O port) (initial value)
1 Transmit operation enabled*2 (TXD32 pin is transmit data pin)
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDRE in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC32 in SPCR, to decide the transmission format before
setting bit TE to 1.
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Bit 4—Receive Enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
Description
0 Receive operation disabled*1 (RXD32 pin is I/O port) (initial value)
1 Receive operation enabled*2 (RXD32 pin is receive data pin)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3— Reserved (MPIE)
Bit 3 is reserved.
Bit 2—Transmit End Interrupt Enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
Description
0 Transmit end interrupt request (TEI) disabled (initial value)
1 Transmit end interrupt request (TEI) enabled*
Note: * TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
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Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0 )
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK32 pin.
The combination of CKE1 and CKE0 determines whether the SCK32 pin functions as an I/O port, a
clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10.9 in section 10.3.1, Overview.
Description
Bit 1
CKE1 Bit 0
CKE0 Communication Mode Clock Source SCK32 Pin Function
0 0 Asynchronous Internal clock I/O port*1
Synchronous Internal clock Serial clock output*1
0 1 Asynchronous Internal clock Clock output*2
Synchronous Reserved
1 0 Asynchronous External clock Clock input*3
Synchronous External clock Serial clock input
1 1 Asynchronous Reserved
Synchronous Reserved
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
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10.2.7 Serial Status Regi s ter (SS R )
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
OER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPBR
0
R
Note: * Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written to by the CPU at any time, but 1 cannot be written to bits TDRE,
RDRF, OER, PER, and FER.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.
Bit 7—Transmit Data Register Empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE
Description
0 Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1 Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR (initial value)
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Bit 6—Receive Data Register Full (RDRF)
Bit 6 indicates that received data is stored in RDR.
Bit 6
RDRF
Description
0 There is no receive data in RDR (initial value)
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction
1 There is receive data in RDR
Setting condition:
When reception ends normally and receive data is transferred from RSR to RDR
Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,
RDR and bit RDRF are not affected and retain their previous state.
Note that if data reception is completed while bit RDRF is still set to 1, an overrun error
(OER) will result and the receive data will be lost.
Bit 5—Overrun Error (OER)
Bit 5 indicates that an overrun error has occurred during reception.
Bit 5
OER
Description
0 Reception in progress or completed*1 (initial value)
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
1 An overrun error has occurred during reception*2
Setting condition:
When reception is completed with RDRF set to 1
Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous
state.
2. RDR retains the receive data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be continued with bit OER set to 1,
and in synchronous mode, transmission cannot be continued either.
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Bit 4—Framing Error (FER)
Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Bit 4
FER
Description
0 Reception in progress or completed*1 (initial value)
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
1 A framing error has occurred during reception
Setting condition:
When the stop bit at the end of the receive data is checked for a value
of 1 at the end of reception, and the stop bit is 0*2
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit FER
set to 1. In synchronous mode, neither transmission nor reception is possible when bit
FER is set to 1.
Bit 3—Parity Error (PER)
Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous
mode.
Bit 3
PER
Description
0 Reception in progress or completed*1 (initial value)
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
1 A parity error has occurred during reception*2
Setting condition:
When the number of 1 bits in the receive data plus parity bit does not
match the parity designated by bit PM in the serial mode register (SMR)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit FER is set to 1.
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Bit 2—Transmit End (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
Description
0 Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1 Transmission ended (initial value)
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is sent
Bit 1—Reserved (MPBR)
Bit 1 is read-only and reserved. It cannot be written to.
Bit 0— Reserved (MPBT)
Bit 0 is reserved. The write value should always be 0.
10.2.8 Bit Rate Register (BRR)
Bit
Initial value
Read/Write
7
BRR7
1
R/W
6
BRR6
1
R/W
5
BRR5
1
R/W
4
BRR4
1
R/W
3
BRR3
1
R/W
0
BRR0
1
R/W
2
BRR2
1
R/W
1
BRR1
1
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
Table 10.3 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
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Table 10.3 Examples of BRR Settings for Various Bit Rates (Asyn c hron ou s Mo de) (1 )
φ
16.4 kHz 19.2 kHz 1 MHz 1.2288 MHz 2 MHz
Bit Rate
(bit/s)
n
N Error
(%)
n
N Error
(%)
n
N Error
(%)
n
N Error
(%)
n
N Error
(%)
110 — — — — — — 2 17 –1.36 2 21 –0.83 3 8 –1.36
150 — — — 0 3 0 2 12 0.16 3 3 0 2 25 0.16
200 — — — 0 2 0 2 9 –2.34 3 2 0 3 4 –2.34
250 0 1 2.5 — — — 3 1 –2.34 0 153 –0.26 2 15 –2.34
300 — — — 0 1 0 0 103 0.16 3 1 0 2 12 0.16
600 — — — 0 0 0 0 51 0.16 3 0 0 0 103 0.16
1200 — — — 0 25 0.16 2 1 0 0 51 0.16
2400 — — — 0 12 0.16 2 0 0 0 25 0.16
4800 — — — — — — 0 7 0 0 12 0.16
9600 — — — — — — 0 3 0 — — —
19200 — — — — — — 0 1 0 — — —
31250 — — — 0 0 0 — — — 0 1 0
38400 — — — — — — 0 0 0 — — —
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Table 10.3 Examples of BRR Settings for Various Bit Rates (Asyn c hron ou s Mo de) (2 )
φ
5 MHz 8 MHz 10 MHz
Bit Rate
(bit/s)
n
N Error
(%)
n
N Error
(%)
n
N Error
(%)
110 3 21 0.88 3 35 –1.36 3 43 0.88
150 3 15 1.73 3 25 0.16 3 32 –1.36
200 3 11 1.73 3 19 –2.34 3 23 1.73
250 3 9 –2.34 3 15 –2.34 3 19 –2.34
300 3 7 1.73 3 12 0.16 3 15 1.73
600 3 3 1.73 2 25 0.16 3 7 1.73
1200 3 1 1.73 2 12 0.16 3 3 1.73
2400 3 0 1.73 0 103 0.16 3 1 1.73
4800 2 1 1.73 0 51 0.16 3 0 1.73
9600 2 0 173 0 25 0.16 2 1 1.73
19200 0 7 1.73 0 12 0.16 2 0 1.73
31250 0 4 0 0 7 0 0 9 0
38400 0 3 1.73 — — — 0 7 1.73
Notes: No indication: Setting not possible.
—: Setting possible, but errors may result.
1. The value set in BRR is given by the following equation:
φ
N = (32 × 22n × B) – 1
where B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: System clock frequency
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.4.)
2. The error in table 10.3 is the value obtained from the following equation, rounded to two
decimal places.
B (rate obtained from n, N, OSC) – R(bit rate in left-hand column in table 10.3.)
Error (%) = R (bit rate in left-hand column in table 10.3.) × 100
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Table 10.4 Relation between n and Clock
SMR Setting
n Clock CKS1 CKS0
0 φ 0 0
0 φw/2*1/φw*2 0 1
2 φ/16 1 0
3 φ/64 1 1
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active (high-
speed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz) φ (MHz) Maximum Bit Rate
(bit/s) n N
0.0384* 0.0192 600 0 0
2 1 31250 0 0
2.4576 1.2288 38400 0 0
4 2 62500 0 0
10 5 156250 0 0
16 8 250000 0 0
20 10 312500 0 0
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.
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Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.
Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode ) (1)
φ
19.2 kHz 1 MHz 2 MHz
Bit Rate
(bit/s) n N Error n N Error n N Error
200 0 23 0 — — — — — —
250 — — — — — — 2 124 0
300 2 0 0 — — — — — —
500 — — — — — —
1K 0 249 0 — — —
2.5K 0 99 0 0 199 0
5K 0 49 0 0 99 0
10K 0 24 0 0 49 0
25K 0 9 0 0 19 0
50K 0 4 0 0 9 0
100K — — — 0 4 0
250K 0 0 0 0 1 0
500K 0 0 0
1M
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Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode ) (2)
φ
5 MHz 8 MHz 10 MHz
Bit Rate
(bit/s) n N Error n N Error n N Error
200 — — — — — — 0 12499 0
250 — — — 3 124 0 2 624 0
300 — — — — — — 0 8332 0
500 — — — 2 249 0 0 4999 0
1K — — — 2 124 0 0 2499 0
2.5K — — — 2 49 0 0 999 0
5K 0 249 0 2 24 0 0 499 0
10K 0 124 0 0 199 0 0 249 0
25K 0 49 0 0 79 0 0 99 0
50K 0 24 0 0 39 0 0 49 0
100K — — — 0 19 0 0 24 0
250K 0 4 0 0 7 0 0 9 0
500K — — — 0 3 0 0 4 0
1M — — — 0 1 0 — — —
Blank: Cannot be set.
— : A setting can be made, but an error will result.
Notes: The value set in BRR is given by the following equation:
φ
N = (4 × 22n × B) – 1
where B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
φ: System clock frequency
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)
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Table 10.7 Relation between n and Clock
SMR Setting
n Clock CKS1 CKS0
0 φ 0 0
0 φw/2*1/φw*2 0 1
2 φ/16 1 0
3 φ/64 1 1
Notes: 1. φw/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φw clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
10.2.9 Clock stop register 1 (CKSTPR1)
TFCKSTP TCCKSTP TACKSTPS32CKSTP ADCKSTP TGCKSTP
76543210
11111111
R/W R/W R/W
R/W R/W R/W
Bit
Initial value
Read/Write
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the
sections on the relevant modules.
Bit 5—SCI3 Module Standby Mode Control (S32CKSTP)
Bit 5 controls setting and clearing of module standby mode for SCI3.
S32CKSTP Description
0 SCI3 is set to module standby mode*
1 SCI3 module standby mode is cleared (initial value)
Note: * All SCI3 register is initialized in module standby mode.
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10.2.10 Serial Port Control Register (SPCR)
Bit
Initial value
Read/Write
7
1
6
1
5
SPC32
0
R/W
4
W
3
SCINV3
0
R/W
0
W
2
SCINV2
0
R/W
1
W
SPCR is an 8-bit readable/writable register that performs RXD32 and TXD32 pin input/output data
inversion switching.
Bits 7 and 6—Reserved
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Bit 5—P42/TXD32 Pin Function Switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0 Functions as P42 I/O pin (initial value)
1 Functions as TXD32 output pin*
Note: * Set the TE bit in SCR3 after setting this bit to 1.
Bit 4—Reserved
Bit 4 is reserved; only 0 can be written to this bit.
Bit 3—TXD32 Pin Output Data Inversion Switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0 TXD32 output data is not inverted (initial value)
1 TXD32 output data is inverted
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Bit 2—RXD32 Pin Input Data Inversion Switch
Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0 RXD32 input data is not inverted (initial value)
1 RXD32 input data is inverted
Bits 1 and 0—Reserved
Bits 1 and 0 are reserved; only 0 can written to these bits.
10.3 Operation
10.3.1 Overview
SCI3 can perform serial communication in two modes: asynchronous mode in which
synchronization is provided character by character, and synchronous mode in which
synchronization is provided by clock pulses. The serial mode register (SMR) is used to select
asynchronous or synchronous mode and the data transfer format, as shown in table 10.8.
The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3,
as shown in table 10.9.
(1) Asynchronous Mode
• Choice of 5-, 7-, or 8-bit data length
• Choice of parity addition and addition of 1 or 2 stop bits. (The combination of these
parameters determines the data transfer format and the character length.)
• Framing error (FER), parity error (PER), overrun error (OER), and break detection during
reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock
with the same frequency as the bit rate can be output.
When external clock is selected: A clock with a frequency 16 times the bit rate must be input.
(The on-chip baud rate generator is not used.)
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(2) Synchronous Mode
• Data transfer format: Fixed 8-bit data length
• Overrun error (OER) detection during reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial
clock is output.
When external clock is selected: The on-chip baud rate generator is not used, and SCI3
operates on the input serial clock.
Table 10.8 SMR Settings and Corresponding Data Transfer Formats
SMR Data Transfer Format
Bit 7
COM Bit 6
CHR Bit 2
MP Bit 5
PE Bit 3
STOP
Mode Data Length Parity Bit Stop Bit
Length
0 1 bit 0
1
No
2 bits
0 1 bit
0
1
1
8-bit data
Yes
2 bits
0 1 bit 0
1
No
2 bits
0 1 bit
1
0
1
1
Asynchronous
mode
7-bit data
Yes
2 bits
0 0
1
Setting
prohibited
0 1 bit
0
1
1
Asynchronous
mode
5-bit data No
2 bits
0 0
1
Setting
prohibited
0 1 bit
0
1
1
1
1
Asynchronous
mode
5-bit data Yes
2 bits
1 * 0 * * Synchronous
mode
8-bit data No No
*: Don’t care
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Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR SCR3
Bit 7 Bit 1 Bit 0 Transmit/Receive Clock
COM CKE1 CKE0 Mode Clock Source SCK32 Pin Function
0 0 0 Internal I/O port (SCK32 pin not used)
1
Asynchronous
mode Outputs clock with same frequency as bit rate
1 0 External Inputs clock with frequency 16 times bit rate
1 0 0 Internal Outputs serial clock
1 0
Synchronous
mode External Inputs serial clock
0 1 1 Reserved (Do not specify these combinations)
1 0 1
1 1 1
(3) Interrupts and Continuous Transmission/Reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These
interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt Flags Interrupt Request Conditions Notes
RXI RDRF
RIE
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI
is enabled and an interrupt is requested.
(See figure 10.2(a).)
The RXI interrupt routine reads the
receive data transferred to RDR and
clears bit RDRF to 0. Continuous
reception can be performed by
repeating the above operations until
reception of the next RSR data is
completed.
TXI TDRE
TIE
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.2(b).)
The TXI interrupt routine writes the
next transmit data to TDR and clears
bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations until
the data transferred to TSR has
been transmitted.
TEI TEND
TEIE
When the last bit of the character in
TSR is transmitted, if bit TDRE is set to
1, bit TEND is set to 1. If bit TEIE is set
to 1 at this time, TEI is enabled and an
interrupt is requested. (See figure
10.2(c).)
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
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RDR
RSR (reception in progress)
RDRF = 0
RXD
32
pin
RDR
RSR↑ (reception completed, transfer)
RDRF ← 1
(RXI request when RIE = 1)
RXD
32
pin
Figure 10.2(a) RDRF Setti ng and RXI Interrupt
TDR (next transmit data)
TSR (transmission in progress)
TDRE = 0
TXD
32
pin
TDR
TSR (transmission completed, transfer)
TDRE ← 1
(TXI request when TIE = 1)
TXD
32
pin
↓
Figure 10.2(b) TDRE Setting and TXI Interrupt
TDR
TSR (transmission in progress)
TEND = 0
TXD
32
pin
TDR
TSR (reception completed)
TEND ← 1
(TEI request when TEIE = 1)
TXD
32
pin
Figure 10.2(c) TEND Setting and TEI Interrupt
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10.3.2 Operation in Asynchronous Mode
In asynchronous mode, serial communication is performed with synchronization provided
character by character. A start bit indicating the start of communication and one or two stop bits
indicating the end of communication are added to each character before it is sent.
SCI3 has separate transmission and reception units, allowing full-duplex communication. As the
transmission and reception units are both double-buffered, data can be written during transmission
and read during reception, making possible continuous transmission and reception.
(1) Data Transfer Format
The general data transfer format in asynchronous communication is shown in figure 10.3.
Serial
data
Start
bit
1 bit
Transmit/receive data Parity
bit
Stop
bit(s)
5, 7, or 8 bits
One transfer data unit (character or frame)
1 bit
or none
1 or 2 bits
Mark
state
1(MSB)(LSB)
Figure 10.3 Data Format in Asynchronous Communication
In asynchronous communication, the communication line is normally in the mark state (high
level). SCI3 monitors the communication line and when it detects a space (low level), identifies
this as a start bit and begins serial data communication.
One transfer data character consists of a start bit (low level), followed by transmit/receive data
(LSB-first format, starting from the least significant bit), a parity bit (high or low level), and
finally one or two stop bits (high level).
In asynchronous mode, synchronization is performed by the falling edge of the start bit during
reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit period,
so that the transfer data is latched at the center of each bit.
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Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format
is selected by the settings in the serial mode register (SMR).
Table 10.11 Data Transfer Formats (Asynchronous Mode)
1CHR
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
PE MP STOP 2 3 4 5
8-bit data
Serial Data Transfer Format and Frame LengthSMR
STOP
S
67891011
12
8-bit data
S
7-bit data
STOP STOP
S
STOP
7-bit data
S
STOP STOP
5-bit data
S
STOP
5-bit data
S
STOP STOP
8-bit data
P
S
STOP
8-bit data
P
S
STOP STOP
Setting prohibited
Setting prohibited
7-bit data
P STOP
S
STOP
7-bit data
STOP
S
5-bit data
STOPP
P
P
S
5-bit data
STOP STOP
S
[Legend]
S:
STOP:
P:
Start bit
Stop bit
Parity bit
Setting prohibited
Setting prohibited
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 331 of 520
REJ09B0409-0100
(2) Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK32 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of
bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source
selection.
When an external clock is input at the SCK32 pin, the clock frequency should be 16 times the bit
rate.
When SCI3 operates on an internal clock, the clock can be output at the SCK32 pin. In this case the
frequency of the output clock is the same as the bit rate, and the phase is such that the clock rises
at the center of each bit of transmit/receive data, as shown in figure 10.4.
1 character (1 frame)
0 D0D1D2D3D4D5D6D70/1 1 1
Clock
Serial
data
Figure 10.4 Phase Relatio nship bet ween Output Clock and Transfer Da t a
(Asynchronous Mode) (8-Bit Data, Parity, 2 Stop Bits)
(3) Data Transfer Operations
(a) SCI3 Initialization
Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then
SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 332 of 520
REJ09B0409-0100
Figure 10.5 shows an example of a flowchart for initializing SCI3.
Start
End
Clear bits TE and
RE to 0 in SCR3
Set bits CKE1
and CKE0
Set data transfer
format in SMR
Set bit SPC32 to
1 in SPCR
Set value in BRR
No
Wait
Yes
[1]
[2]
[3]
[4]
Set bits TIE, RIE,
MPIE, and TEIE in
SCR3, and set bits
RE or TE to 1
in SCR3
Has 1-bit period
elapsed?
Set clock selection in SCR3. Be sure to
clear the other bits to 0. If clock output
is selected in asynchronous mode, the
clock is output immediately after setting
bits CKE1 and CKE0. If clock output is
selected for reception in synchronous
mode, the clock is output immediately
after bits CKE1, CKE0, and RE are
set to 1.
Set the data transfer format in the serial
mode register (SMR).
Write the value corresponding to the
transfer rate in BRR. This operation is
not necessary when an external clock
is selected.
Wait for at least one bit period, then set
bits TIE, RIE, MPIE, and TEIE in SCR3,
and set bits RE or TE to 1 in SCR3.
Setting bits TE and RE enables the TXD
32
and RXD
32
pins to be used. In asynchronous
mode the mark state is established when
transmitting, and the idle state waiting for
a start bit when receiving.
[1]
[2]
[3]
[4]
Figure 10.5 Example of SCI 3 Ini tial i zat i on Fl owc hart
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 333 of 520
REJ09B0409-0100
(b) Transmitting
Figure 10.6 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
End
Read bit TDRE
in SSR
Sets bit SPC32 to
1 in SPCR
[1]
[2]
[3]
Write transmit
data to TDR
Read bit TEND
in SSR
Set PDR = 0,
PCR = 1
Clear bit TE to 0
in SCR3
No
TDRE = 1?
Yes
Continue data
transmission?
No
TEND = 1?
No
Yes
Yes
Yes
No
Break output?
Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then write transmit data to the transmit
data register (TDR). When data is
written to TDR, bit TDRE is cleared to 0
automatically.
(After the TE bit is set to 1, one frame of
1s is output, then transmission is possible.)
When continuing data transmission,
be sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0
automatically.
If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
[1]
[2]
[3]
Figure 10.6 Example of Data Transmission Flowchart (Asynchronous Mode)
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 334 of 520
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SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD32 pin using the relevant data transfer format in table 10.11.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If bit
TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.7 shows an example of the operation when transmitting in asynchronous mode.
1 frame
Start
bit
Start
bit
Transmit
data
Transmit
data
Parity
bit
Stop
bit
Parity
bit
Stop
bit
Mark
state
1 frame
01 D0 D1 D7 0/1 1 1 10 D0 D1 D7 0/1
Serial
data
TDRE
TEND
LSI
operation
TXI request TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request TEI request
Figure 10.7 Example of Operation when Transmitting in Asynchronous Mode
(8-Bit Data, Parity, 1 Stop Bit)
Section 10 Serial Communication Interface
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(c) Receiving
Figure 10.8 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
End
Read bits OER,
PER, FER in SSR [1]
[2]
[3]
[4]
Read bit RDRF
in SSR
Read receive
data in RDR
Clear bit RE to
0 in SCR3
Yes
OER + PER
+ FER = 1?
No
RDRF = 1?
Yes
Continue data
reception?
No
No
Yes
Receive error
processing
(A)
Read bits OER, PER, and FER in the
serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.
Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.
When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
[1]
[2]
[3]
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode)
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 336 of 520
REJ09B0409-0100
Start receive
error processing
End of receive
error processing
[4]
Clear bits OER, PER,
FER to 0 in SSR
Yes
OER = 1?
Yes
Yes
FER = 1?
Break?
Yes
PER = 1?
No
No
No
No
Overrun error
processing
Framing error
processing
(A)
Parity error
processing
If a receive error has
occurred, read bits OER,
PER, and FER in SSR to
identify the error, and after
carrying out the necessary
error processing, ensure
that bits OER, PER, and
FER are all cleared to 0.
Reception cannot be
resumed if any of these
bits is set to 1. In the case
of a framing error, a break
can be detected by reading
the value of the RXD32 pin.
[4]
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode) (cont)
Section 10 Serial Communication Interface
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SCI3 operates as follows when receiving data.
SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal
synchronization and begins reception. Reception is carried out in accordance with the relevant
data transfer format in table 10.11. The received data is first placed in RSR in LSB-to-MSB order,
and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
• Parity check
SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)
set in bit PM in the serial mode register (SMR).
• Stop bit check
SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from
RSR to RDR.
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a
receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.12 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER,
PER, and RDRF must therefore be cleared to 0 before resuming reception.
Table 10.12 Receive Error Detection Conditions and Receive Data Processing
Receive Error Abbr. Detection Conditions Receive Data Processing
Overrun error OER When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
Receive data is not transferred
from RSR to RDR
Framing error FER When the stop bit is 0 Receive data is transferred
from RSR to RDR
Parity error PER When the parity (odd or even) set
in SMR is different from that of
the received data
Receive data is transferred
from RSR to RDR
Section 10 Serial Communication Interface
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Figure 10.9 shows an example of the operation when receiving in asynchronous mode.
1 frame
Start
bit
Start
bit
Receive
data
Receive
data
Parity
bit
Stop
bit
Parity
bit
Stop
bit
Mark state
(idle state)
1 frame
01 D0 D1 D7 0/1 1 0 10 D0 D1 D7 0/1
Serial
data
RDRF
FER
LSI
operation
User
processing
RDRF
cleared to 0
RDR data read Framing error
processing
RXI request 0 start bit
detected
ERI request in
response to
framing error
Figure 10.9 Example of Operation when Receiving in Asynchronous Mode
(8-Bit Data, Parity, 1 Stop Bit)
10.3.3 Operation in Synchronous Mode
In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This
mode is suitable for high-speed serial communication.
SCI3 has separate transmission and reception units, allowing full-duplex communication with a
shared clock.
As the transmission and reception units are both double-buffered, data can be written during
transmission and read during reception, making possible continuous transmission and reception.
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 339 of 520
REJ09B0409-0100
(1) Data Transfer Format
The general data transfer format in asynchronous communication is shown in figure 10.10.
Serial
clock
Serial
data
Note: * High level except in continuous transmission/reception
LSB MSB
* *
Bit 1Bit 0 Bit 2 Bit 3 Bit 4
8 bits
One transfer data unit (character or frame)
Bit 5 Bit 6 Bit 7
Don't
care
Don't
care
Figure 10.10 Data Format in Synchronous Communication
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of
the serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the MSB,
the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity bits cannot be added.
(2) Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK32 pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in
SMR and bits CKE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK32 pin. Eight pulses
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 340 of 520
REJ09B0409-0100
(3) Data Transfer Operations
(a) SCI3 Initialization
Data tran sfer on SCI3 first of all requires that SCI3 be initialized as described in section 10.3.2
(3), (a) SCI3 Initialization, and sh own in figure 10.5.
(b) Transmitting
Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
End
Read bit TDRE
in SSR
Sets bit SPC32 to
1 in SPCR
[1]
[2]
Write transmit
data to TDR
Read bit TEND
in SSR
Clear bit TE to 0
in SCR3
No
TDRE = 1?
Yes
Continue data
transmission?
No
TEND = 1?
Yes
Yes
No
Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started. When clock output is selected,
the clock is output and data transmission
started when data is written to TDR.
When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.
[1]
[2]
Figure 10.11 Example of Data Transmission Flowchart (Synchronous Mode)
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 341 of 520
REJ09B0409-0100
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock is
selected, data is output in synchronization with the input clock.
Serial data is transmitted from the TXD32 pin in order from the LSB (bit 0) to the MSB (bit 7).
When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit
TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3
is set to 1 at this time, a TEI request is made.
After transmission ends, the SCK pin is fixed at the high level.
Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data
reception status is set to 1. Check that these error flags are all cleared to 0 before a
transmit operation.
Figure 10.12 shows an example of the operation when transmitting in synchronous mode.
Serial
clock
Serial
data Bit 1Bit 0 Bit 7 Bit 0
1 frame 1 frame
Bit 1 Bit 6 Bit 7
TDRE
TEND
LSI
operation
User
processing
TXI request
Data written
to TDR
TDRE cleared
to 0
TXI request TEI request
Figure 10.12 Example of Operation when Transmitting in Synchronous Mode
Section 10 Serial Communication Interface
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REJ09B0409-0100
(c) Receiving
Figure 10.13 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
End
Read bit OER
in SSR [1]
[2]
[3]
[4]
Read bit RDRF
in SSR
Overrun error
processing
4
Clear bit OER to
0 in SSR
Read receive
data in RDR
Clear bit RE to
0 in SCR3
Yes
OER = 1?
No
RDRF = 1?
Yes
Continue data
reception?
No
No
Yes
Overrun error
processing
End of overrun
error processing
Start overrun
error processing
Read bit OER in the serial status register
(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.
When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
If an overrun error has occurred, read bit
OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.
[1]
[2]
[3]
[4]
Figure 10.13 Example of Data Reception Flowchart (Synchronous Mode)
Section 10 Serial Communication Interface
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SCI3 operates as follows when receiving data.
SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check identifies
an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10.12 for the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER, FER,
PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.14 shows an example of the operation when receiving in synchronous mode.
Serial
clock
Serial
data Bit 0Bit 7 Bit 7 Bit 0
1 frame 1 frame
Bit 1 Bit 6 Bit 7
RDRF
OER
LSI
operation
User
processing
RXI request
RDR data read
RDRE cleared
to 0
RXI request ERI request in
response to
overrun error
Overrun error
processing
RDR data has
not been read
(RDRF = 1)
Figure 10.14 Example of Operation when Receiving in Synchronous Mode
Section 10 Serial Communication Interface
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(d) Simultaneous transmit/receive
Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
End
Read bit TDRE
in SSR
Sets bit SPC32 to
1 in SPCR
[1]
[2]
[3]
[4]
Write transmit
data to TDR
Read bit OER
in SSR
Read bit RDRF
in SSR
Clear bits TE and
RE to 0 in SCR3
Yes
TDRE = 1? No
OER = 1?
No
RDRF = 1?
Yes
Continue data
transmission/reception?
No
Yes
No
Read receive data
in RDR
Yes
Overrun error
processing
Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmis-
sion and reception cannot be resumed if bit
OER is set to 1.
See figure 10.13 for details on overrun error
processing.
[1]
[2]
[3]
[4]
Figure 10.15 Example of Simultaneous Data Transmission/Reception Flowc har t
(Synchronous Mode)
Section 10 Serial Communication Interface
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REJ09B0409-0100
Notes: 1. When switching from transmission to simultaneous transmission/reception, check that
SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE
to 0, and then set bits TE and RE to 1 simultaneously.
2. When switching from reception to simultaneous transmission/reception, check that
SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error
flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1
simultaneously.
10.4 Interrupts
SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and
three receive error interrupts (overrun error, framing error, and parity error). These interrupts have
the same vector address.
The various interrupt requests are shown in table 10.13.
Table 10.13 SCI3 Interrupt Requests
Interrupt Abbr.
Interrupt Request Vector
Address
RXI Interrupt request initiated by receive data full flag (RDRF) H'0024
TXI Interrupt request initiated by transmit data empty flag (TDRE)
TEI Interrupt request initiated by transmit end flag (TEND)
ERI Interrupt request initiated by receive error flag (OER, FER, PER)
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3.
When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in
SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.
The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request
(TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI
interrupt will be requested even if the transmit data is not ready.
Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request
(TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a
TEI interrupt will be requested even if the transmit data has not been sent.
Effective use of these interrupt requests can be made by having processing that transfers transmit
data to TDR carried out in the interrupt service routine.
Section 10 Serial Communication Interface
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To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable
bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been
transferred to TDR.
When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and
FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during
reception.
For further details, see section 3.3, Interrupts.
10.5 Application Notes
The following points should be noted when using SCI3.
1. Relation between writes to T DR and bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not
yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR
once only (not two or more times).
2. Operation when a number of receive errors occur simultaneously
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the
states shown in table 10.14. If an overrun error is detected, data transfer from RSR to RDR will
not be performed, and the receive data will be lost.
Section 10 Serial Communication Interface
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Table 10.14 SSR Status Flag States and Receive Data Transfer
SSR Status Flags
RDRF* OER FER PER Receive Data Transfer
RSR → RDR Receive Error Status
1 1 0 0 X Overrun error
0 0 1 0 O Framing error
0 0 0 1 O Parity error
1 1 1 0 X Overrun error + framing error
1 1 0 1 X Overrun error + parity error
0 0 1 1 O Framing error + parity error
1 1 1 1 X Overrun error + framing error + parity error
O : Receive data is transferred from RSR to RDR.
X : Receive data is not transferred from RSR to RDR.
Note: * Bit RDRF retains its state prior to data reception. However, note that if RDR is read
after an overrun error has occurred in a frame because reading of the receive data in
the previous frame was delayed, RDRF will be cleared to 0.
3. Break detection and processing
When a framing error is detected, a break can be detected by reading the value of the RXD32 pin
directly. In a break, the input from the RXD32 pin becomes all 0s, with the result that bit FER is set
and bit PER may also be set.
SCI3 continues the receive operation even after receiving a break. Note, therefore, that even
though bit FER is cleared to 0 it will be set to 1 again.
4. Mark state and break detection
When bit TE is cleared to 0, the TXD32 pin functions as an I/O port whose input/output direction
and level are determined by PDR and PCR. This fact can be used to set the TXD32 pin to the mark
state, or to detect a break during transmission.
To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and
PDR = 1. Since bit TE is cleared to 0 at this time, the TXD32 pin functions as an I/O port and 1 is
output.
To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0.
When bit TE is cleared to 0, the transmission unit is initialized regardless of the current
transmission state, the TXD32 pin functions as an I/O port, and 0 is output from the TXD32 pin.
Section 10 Serial Communication Interface
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5. Receive error flags and transmit operation (synchronous mode only)
When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if
bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission.
Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0.
6. Receive data sampling timing and receive margin in asynchr onous mode
In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate.
When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start
bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock.
This is illustrated in figure 10.16.
0 7 15 0 7 15 0
Internal
basic clock
Receive data
(RXD32) Start bit D0
16 clock pulses
8 clock pulses
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10.16 Receive Data Sampling Timing in Asynchronous Mode
Consequently, the receive margin in asynchronous mode can be expressed as shown in equation
(1).
1 D – 0.5
M ={(0.5 – 2N ) – N – (L – 0.5) F} × 100 [%] ..... Equation (1)
where M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Section 10 Serial Communication Interface
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Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
M = {0.5 – 1/(2 × 16)} × 100 [%]
= 46.875% .... Equation (2)
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
7. Relation betwee n RDR reads and bit RDRF
In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when
reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit RDR
is read more than once, the second and subsequent read operations will be performed while bit
RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0,
if the read operation coincides with completion of reception of a frame, the next frame of data may
be read. This is illustrated in figure 10.17.
Communication
line
RDRF
RDR
Frame 1 Frame 2 Frame 3
Data 1
Data 1
RDR read RDR read
Data 1 is read at point
(A)
Data 2 Data 3
Data 2
(A)
Data 2 is read at point
(B)
(B)
Figure 10.17 Relation between RDR Read Timing and Data
Section 10 Serial Communication Interface
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In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To be
precise in terms of timing, the RDR read should be completed before bit 7 is transferred in
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
8. Transmit and receive operations when making a state transition
Make sure that transmit and receive operations have completely finished before carrying out state
transition processing.
9. Switching SCK32 function
If pin SCK32 is used as a clock output pin by SCI3 in synchronous mode and is then switched to a
general input/output pin (a pin with a different function), the pin outputs a low level signal for half
a system clock (φ) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
a. When an SCK32 function is switched from clock output to non clock-output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be
left 1. The above prevents SCK32 from being used as a general input/output pin. To avoid an
intermediate level of voltage from being applied to SCK32, the line connected to SCK32 should
be pulled up to the VCC level via a resistor, or supplied with output from an external device.
b. When an SCK32 function is switched from clock output to general input/output
When stopping data transfer,
(i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3
to 1 and 0, respectively.
(ii) Clear bit COM in SMR to 0
(iii) Clear bits CKE1 and CKE0 in SCR3 to 0
Note that special care is also needed here to avoid an intermediate level of voltage from being
applied to SCK32.
10. Set up at subactive or subsleep mode
At subactive or subsleep mode, SCI3 becomes possible use only at CPU clock is φw/2.
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 351 of 520
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11. Oscillator use with serial communications interface
When implementing the serial communications interface, the system clock oscillator must be used.
The on-chip oscillator should not be used in this case. See section 4.2 (5), On-Chip Oscillator
Selection Method, for information on switching between the system clock oscillator and the on-
chip oscillator.
Section 10 Serial Communication Interface
Rev. 1.00 Dec. 19, 2007 Page 352 of 520
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Section 11 10-Bit PWM
Rev. 1.00 Dec. 19, 2007 Page 353 of 520
REJ09B0409-0100
Section 11 10-Bit PWM
11.1 Overview
This LSI is provided with two on-chip 10-bit PWMs (pulse width modulators), designated PWM1
and PWM2, with identical functions. The PWMs can be used as D/A converters by connecting a
low-pass filter. In this section the suffix m (m = 1 or 2) is used with register names, etc., as in
PWDRLm, which denotes the PWDRL registers for each PWM.
11.1.1 Features
Features of the 10-bit PWMs are as follows.
• Choice of four conversion periods
Any of the following conversion periods can be chosen:
4,096/φ, with a minimum modulation width of 4/φ
2,048/φ, with a minimum modulation width of 2/φ
1,024/φ, with a minimum modulation width of 1/φ
512/φ, with a minimum modulation width of 1/2 φ
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
It is possible to select between two types of PWM output: pulse-division PWM and event counter
PWM (PWM incorporating AEC). Refer to section 9.7, Asynchronous Event Counter (AEC), for
information on event counter PWM.
Section 11 10-Bit PWM
Rev. 1.00 Dec. 19, 2007 Page 354 of 520
REJ09B0409-0100
11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the 10-bit PWM.
PWDRLm
PWDRUm
PWCRm
PWM waveform
generator
φ/2
φ/4
φ/8
φ
PWMm
(IECPWM)
IECPWM
Internal data bus
[Legend]
PWCRm:
PWDRLm:
PWDRUm:
PWMm:
IECPWM:
PWM control register
PWM data register L
PWM data register U
PWM output pin
Event counter PWM (PWM incorporating AEC)
m = 1 or 2
Figure 11.1 Block Diagram of the 10-bit PWM (1-Channel Configuration)
11.1.3 Pin Configuration
Table 11.1 shows the output pin assigned to the 10-bit PWM.
Table 11.1 Pin Configuration
Name Abbr. I/O Function
PWM1 output pin PWM1 Output Pulse-division PWM waveform output (PWM1)/
event counter PWM output (IECPWM)
PWM2 output pin PWM2 Output Pulse-division PWM waveform output (PWM2)/
event counter PWM output (IECPWM)
Section 11 10-Bit PWM
Rev. 1.00 Dec. 19, 2007 Page 355 of 520
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11.1.4 Register Configuration
Table 11.2 shows the register configuration of the 10-bit PWM.
Table 11.2 Register Configuration
Name Abbr. R/W Initial Value Address
PWM1 control register PWCR1 W H'F8 H'FFD0
PWM1 data register U PWDRU1 W H'FC H'FFD1
PWM1 data register L PWDRL1 W H'00 H'FFD2
PWM2 control register PWCR2 W H'F8 H'FFCD
PWM2 data register U PWDRU2 W H'FC H'FFCE
PWM2 data register L PWDRL2 W H'00 H'FFCF
Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB
11.2 Register Descriptions
11.2.1 PWM Control Register (PWCRm)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
1
3
1
0
PWCRm0
0
W
2
0
W
1
PWCRm1
0
W
PWCRm2
On the H8/38524 Group, PWCRm is an 8-bit write-only register used to select the input clock and
PWM output type. At reset PWCRm is initialized to H'F8.
Bits 7 to 3—Reserved
Bits 7 to 3 are reserved; they are always read as 1, and cannot be modified.
Section 11 10-Bit PWM
Rev. 1.00 Dec. 19, 2007 Page 356 of 520
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Bit 2—Output Format Select (PWCRm2)
This bit selects the format of the output from the PWMm output pin.
This bit is write-only. Reading it always returns 1.
Bit 2
PWCRm2
Description
0 Pulse-division PWM (initial value)
1 Event counter PWM
Bits 1 and 0—Clock Select 1 and 0 (PWCRm1, PWCRm0)
Bits 1 and 0 select the clock supplied to the 10-bit PWM. These bits are write-only bits; they are
always read as 1.
Bit 1
PWCRm1 Bit 0
PWCRm0
Description
0 0 The input clock is φ (tφ* = 1/φ) (initial value)
The conversion period is 512/φ, with a minimum modulation
width of 1/2φ
0 1 The input clock is φ/2 (tφ* = 2/φ)
The conversion period is 1,024/φ, with a minimum
modulation width of 1/φ
1 0 The input clock is φ/4 (tφ* = 4/φ)
The conversion period is 2,048/φ, with a minimum
modulation width of 2/φ
1 1 The input clock is φ/8 (tφ* = 8/φ)
The conversion period is 4,096/φ, with a minimum
modulation width of 4/φ
Note: * Period of PWM input clock.
Section 11 10-Bit PWM
Rev. 1.00 Dec. 19, 2007 Page 357 of 520
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11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm)
Bit
Initial value
Read/Write
7
1
6
1
5
1
4
1
3
1
0
PWDRUm0
0
W
2
1
1
PWDRUm
1
0
W
PWDRUm
Bit
Initial value
Read/Write
7
PWDRLm7
0
W
6
PWDRLm6
0
W
5
PWDRLm5
0
W
4
PWDRLm4
0
W
3
PWDRLm3
0
W
0
PWDRLm0
0
W
2
PWDRLm2
0
W
1
PWDRLm1
0
W
PWDRLm
PWDRUm and PWDRLm form a 10-bit write-only register, with the upper 2 bits assigned to
PWDRUm and the lower 8 bits to PWDRLm. The value written to PWDRUm and PWDRLm
gives the total high-level width of one PWM waveform cycle.
When 10-bit data is written to PWDRUm and PWDRLm, the register contents are latched in the
PWM waveform generator, updating the PWM waveform generation data. The 10-bit data should
always be written in the following sequence:
1. Write the lower 8 bits to PWDRLm.
2. Write the upper 2 bits to PWDRUm for the same channel.
PWDRUm and PWDRLm are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRUm is initialized to H'FC, and PWDRLm to H'00.
Section 11 10-Bit PWM
Rev. 1.00 Dec. 19, 2007 Page 358 of 520
REJ09B0409-0100
11.2.3 Clock Stop Regi ster 2 ( CKS T P R2 )
LVDCKSTP
WDCKSTP
PW1CKSTP
LDCKSTP——
PW2CKSTP
AECKSTP
76543210
11111111
R/W R/W R/W R/W
——R/W R/W
Bit
Initial value
Read/Write
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the PWM is described here. For details of the other bits, see the
sections on the relevant modules.
Bits 4 and 1—PWM Module Standby Mode Control (PWmCKSTP)
Bits 4 and 1 control setting and clearing of module standby mode for the PWMm.
PWmCKSTP Description
0 PWMm is set to module standby mode
1 PWMm module standby mode is cleared (initial value)
Section 11 10-Bit PWM
Rev. 1.00 Dec. 19, 2007 Page 359 of 520
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11.3 Operation
11.3.1 Operation
When using the 10-bit PWM, set the registers in the following sequence.
1. Set PWM1 or PWM2 in PMR9 to 1 for the PWM channel to be used, so that pin P90/PWM1 or
P91/PWM2 is designated as the PWM output pin, or both are designated as PWM output pins.
2. Set bits PWCRm1 and PWCRm0 in the PWM control register (PWCRm) to select a
conversion period of 4,096/φ (PWCRm1 = 1, PWCRm0 = 1), 2,048/φ (PWCRm1 = 1,
PWCRm0 = 0), 1,024/φ (PWCRm1 = 0, PWCRm0 = 1), or 512/φ (PWCRm1 = 0, PWCRm0 =
0). In addition, select between pulse-division PWM (PWCRm2 = 0) and event counter PWM
(PWCRm2 = 1) output. Refer to section 9.7, Asynchronous Event Counter (AEC), for
information on the event counter PWM (PWM incorporating AEC) output format.
3. Set the output waveform data in PWDRUm and PWDRLm. Be sure to write in the correct
sequence, first PWDRLm then PWDRUm for the same channel. When data is written to
PWDRUm, the data will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 4 pulses, as shown in figure 11.2. The total of the high-level
pulse widths during this period (TH) corresponds to the data in PWDRUm and PWDRLm. This
relation can be represented as follows.
TH = (data value in PWDRUm and PWDRLm + 4) • tφ/2
where tφ is the PWM input clock period: 1/φ (PWCRm = H'0), 2/φ (PWCRm = H'1), 4/φ
(PWCRm = H'2), or 8/φ (PWCRm = H'3).
Section 11 10-Bit PWM
Rev. 1.00 Dec. 19, 2007 Page 360 of 520
REJ09B0409-0100
Example: Settings in order to obtain a conversion period of 1,024 µs:
When PWCRm1 = 0 and PWCRm0 = 0, the conversion period is 512/φ, so φ must be
0.5 MHz. In this case, tfn = 256 µs, with 1/2φ (resolution) = 1.0 µs.
When PWCRm1 = 0 and PWCRm0 = 1, the conversion period is 1,024/φ, so φ must be
1 MHz. In this case, tfn = 256 µs, with 1/φ (resolution) = 1.0 µs.
When PWCRm1 = 1 and PWCRm0 = 0, the conversion period is 2,048/φ , so φ must
be 2 MHz. In this case, tfn = 256 µs, with 2/φ (resolution) = 1.0 µs.
When PWCRm1 = 1 and PWCRm0 = 1, the conversion period is 4,096/φ, so φ must be
4 MHz. In this case, tfn = 256 µs, with 4/φ (resolution) = 1.0 µs
Accordingly, for a conversion period of 1,024 µs, the system clock frequency (φ) must
be 0.5 MHz, 1 MHz, 2 MHz, or 4 MHz.
1 conversion period
tf1
tH1 tH2 tH3 tH4
tf2 tf3 tf4
TH = tH1 + tH2 + tH3 + tH4
tf1 = tf2 = tf3 = tf4
Figure 11.2 PWM Output Waveform
11.3.2 PWM Operation Modes
PWM operation modes are shown in table 11.3.
Table 11.3 PWM Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch Sub-
active Sub-
sleep
Standby Module
Standby
PWCRm Reset Functions Functions Retained Retained Retained Retained Retained
PWDRUm Reset Functions Functions Retained Retained Retained Retained Retained
PWDRLm Reset Functions Functions Retained Retained Retained Retained Retained
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 361 of 520
REJ09B0409-0100
Section 12 A/D Converter
12.1 Overview
This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital
converter, and can convert up to 8 channels of analog input.
12.1.1 Features
The A/D converter has the following features.
• 10-bit resolution
• Eight input channels
• Conversion time: approx. 12.4 µs per channel (at 5 MHz operation)/6.2 µs (at 10 MHz
operation)
• Built-in sample-and-hold function
• Interrupt requested on completion of A/D conversion
• A/D conversion can be started by external trigger input
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 362 of 520
REJ09B0409-0100
12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the A/D converter.
Internal data bus
AMR
ADSR
ADRRH
ADRRL
Control logic
+
Com-
parator
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
ADTRG
AV
AV
CC
SS
Multiplexer
Reference
voltage
IRRAD
AV
CC
AV
SS
[Legend]
AMR:
ADSR:
ADRR:
IRRAD:
A/D mode register
A/D start register
A/D result register
A/D conversion end interrupt request flag
−
Figure 12.1 Block Diagram of the A/D Converter
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 363 of 520
REJ09B0409-0100
12.1.3 Pin Configuration
Table 12.1 shows the A/D converter pin configuration.
Table 12.1 Pin Configuration
Name Abbr. I/O Function
Analog power supply AVCC Input Power supply and reference voltage of analog part
Analog ground AVSS Input Ground and reference voltage of analog part
Analog input 0 AN0 Input Analog input channel 0
Analog input 1 AN1 Input Analog input channel 1
Analog input 2 AN2 Input Analog input channel 2
Analog input 3 AN3 Input Analog input channel 3
Analog input 4 AN4 Input Analog input channel 4
Analog input 5 AN5 Input Analog input channel 5
Analog input 6 AN6 Input Analog input channel 6
Analog input 7 AN7 Input Analog input channel 7
External trigger input ADTRG Input External trigger input for starting A/D conversion
12.1.4 Register Configuration
Table 12.2 shows the A/D converter register configuration.
Table 12.2 Register Configuration
Name Abbr. R/W Initial Value Address
A/D mode register AMR R/W H'30 H'FFC6
A/D start register ADSR R/W H'7F H'FFC7
A/D result register H ADRRH R Not fixed H'FFC4
A/D result register L ADRRL R Not fixed H'FFC5
Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 364 of 520
REJ09B0409-0100
12.2 Register Descriptions
12.2.1 A/D Result Registers (ADRRH, ADRRL)
Bit 7 6 5 4 3
ADRRH ADRRL
021 76543 021
Initial value
Read/Write
Unde-
fined
R
Unde-
fined
R
Unde-
fined
R
Unde-
fined
R
Unde-
fined
R
Unde-
fined
R
Unde-
fined
R
Unde-
fined
R
Unde-
fined
R
Unde-
fined
R
ADR9 ADR8 ADR7 ADR6 ADR5 ADR2ADR4 ADR3 ADR1 ADR0
ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of
analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2 bits
in ADRRL.
ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values
during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is
stored as 10-bit data, and this data is held until the next conversion operation starts.
ADRRH and ADRRL are not cleared on reset.
12.2.2 A/D Mode Re gister (AMR)
Bit
Initial value
Read/Write
7
CKS
0
R/W
6
TRGE
0
R/W
5
1
4
1
3
CH3
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 365 of 520
REJ09B0409-0100
Bit 7—Clock Select (CKS)
Bit 7 sets the A/D conversion speed.
Conversion Time
Bit 7
CKS Conversion Period φ = 1 MHz φ = 5 MHz φ = 10 MHz
0 62/φ (initial value) 62 µs 12.4 µs 6.2 µs
1 31/φ 31 µs —* —
*
Note: * The operation cannot be guaranteed if the conversion time is less than 6.2 µs. Make
sure to select a setting that gives a conversion time of 6.2 µs or more.
Bit 6—External Trigger Select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
Description
0 Disables start of A/D conversion by external trigger (initial value)
1 Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of IEGR. See (1) IRQ Edge
Select Register (IEGR) in section 3.3.2, Interrupt Control Registers, for details.
Bits 5 and 4—Reserved
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 366 of 520
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Bits 3 to 0—Channel Select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3
CH3 Bit 2
CH2 Bit 1
CH1 Bit 0
CH0
Analog Input Channel
0 0 * * No channel selected (initial value)
0 1 0 0 AN0
0 1 0 1 AN1
0 1 1 0 AN2
0 1 1 1 AN3
1 0 0 0 AN4
1 0 0 1 AN5
1 0 1 0 AN6
1 0 1 1 AN7
1 1 * * Setting prohibited
*: Don’t care
12.2.3 A/D Start Register (ADSR)
Bit
Initial value
Read/Write
7
ADSF
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in ADRRH and ADRRL, and at the same time ADSF is cleared to 0.
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 367 of 520
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Bit 7—A/D Start Flag (ADSF)
Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7
ADSF
Description
0 Read: Indicates the completion of A/D conversion (initial value)
Write: Stops A/D conversion
1 Read: Indicates A/D conversion in progress
Write: Starts A/D conversion
Bits 6 to 0—Reserved
Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
12.2.4 Clock Stop Register 1 (CKSTPR1)
TFCKSTP TCCKSTP TACKSTPS32CKSTP ADCKSTP TGCKSTP
76543210
11111111
R/W R/W R/W
R/W R/W R/W
Bit
Initial value
Read/Write
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the A/D converter is described here. For details of the other bits,
see the sections on the relevant modules.
Bit 4—A/D Converter Module Standby Mode Control (ADCKSTP)
Bit 4 controls setting and clearing of module standby mode for the A/D converter.
ADCKSTP Description
0 A/D converter is set to module standby mode
1 A/D converter module standby mode is cleared (initial value)
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 368 of 520
REJ09B0409-0100
12.3 Operation
12.3.1 A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 10-
bit data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2 Start of A/D Conversion by External Trigger Input
The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit IRQ4 in PMR1 is set to 1 and bit TRGE
in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of interrupt edge
select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D
conversion.
Figure 12.2 shows the timing.
φ
Pin ADTRG
(when bit
IEG4 = 0)
A
DSF A/D conversion
Figure 12.2 External Trigger Input Timing
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 369 of 520
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12.3.3 A/D Converter Operation Modes
A/D converter operation modes are shown in table 12.3.
Table 12.3 A/D Converter Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby Module
Standby
AMR Reset Functions Functions Retained Retained Retained Retained Retained
ADSR Reset Functions Functions Retained Retained Retained Retained Retained
ADRRH Retained* Functions Functions Retained Retained Retained Retained Retained
ADRRL Retained* Functions Functions Retained Retained Retained Retained Retained
Note: * Undefined in a power-on reset.
12.4 Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2
(IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see section 3.3, Interrupts.
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 370 of 520
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12.5 Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.3 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D converter
goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 371 of 520
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Idle A/D conversion (1) Idle A/D conversion (2) Idle
Interrupt
(IRRAD)
IENAD
A
DSF
Channel 1 (AN
1
)
operation state
A
DRRH
A
DRRL
Set*
Set*Set*
Read conversion result Read conversion result
A/D conversion result (1) A/D conversion result (2)
A/D conversion starts
Note: * ( ) indicates instruction execution by software.
Figure 12.3 Typical A/D Converter Operation Timing
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 372 of 520
REJ09B0409-0100
Start
Set A/D conversion speed
and input channel
Perform A/D
conversion?
End
Yes
No
Disable A/D conversion
end interrupt
Start A/D conversion
ADSF = 0?
No
Yes
Read ADSR
Read ADRRH/ADRRL data
Figure 12.4 Flow Chart of Procedure fo r Using A/D Converter (Polling by Software)
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 373 of 520
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Start
Set A/D conversion speed
and input channel
Enable A/D conversion
end interrupt
Start A/D conversion
A/D conversion
end interrupt?
Yes
No
End
Yes
No
Clear bit IRRAD to
0 in IRR2
Read ADRRH/ADRRL data
Perform A/D
conversion?
Figure 12.5 Flow Chart of Proce dure for Using A/D Converter (Interrupts Used)
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 374 of 520
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12.6 A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.6).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 12.7).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 12.7).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristics between zero voltage and
full-scale voltage. Does not include offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, full-
scale error, quantization error, and nonlinearity error.
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 375 of 520
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111
110
101
100
011
010
001
000
1
8
2
8
6
8
7
8
FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
3
8
4
8
5
8
Figure 12.6 A/D Conversion Accuracy Definitions (1)
FS
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Analog
input voltage
Offset error
Actual A/D conversion
characteristic
Full-scale error
Figure 12.7 A/D Conversion Accuracy Definitions (2)
Section 12 A/D Converter
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12.7 Application Notes
12.7.1 Permissible Signal Source Impedance
This LSI’s analog input is designed such that conversion precision is guaranteed for an input
signal for which the signal source impedance is 10 kΩ or less. This specification is provided to
enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it
may not be possible to guarantee A/D conversion precision. However, a large capacitance
provided externally, the input load will essentially comprise only the internal input resistance of
10 kΩ, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained
in this case, it may not be possible to follow an analog signal with a large differential coefficient
(e.g., 5 mV/µs or greater) (see figure 12.8). When converting a high-speed analog signal, a low-
impedance buffer should be inserted.
12.7.2 Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
A/D converter
equivalent circuit
This LSI
20 pF
Cin =
15 pF
10 kΩ
Up to 10 kΩ
Low-pass
filter
C to 0.1 µF
Sensor output
impedance
Sensor input
Figure 12.8 Analog Input Circuit Example
Section 12 A/D Converter
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12.7.3 Additional Usage Notes
• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D
start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
• When A/D conversion is started after clearing module standby mode, wait for 10 φ clock
cycles before starting.
• In active mode or sleep mode, analog power supply current (AISTOP1) flows into the ladder
resistance even when the A/D converter is not operating. Therefore, if the A/D converter is not
used, it is recommended that AVCC be connected to the system power supply and the
ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop
register 1 (CKSTPR1).
Section 12 A/D Converter
Rev. 1.00 Dec. 19, 2007 Page 378 of 520
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Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 379 of 520
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Section 13 LCD Controller/Driver
13.1 Overview
This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit,
enabling it to directly drive an LCD panel.
13.1.1 Features
Features of the LCD controller/driver are given below.
• Display capacity
Duty Cycle Internal Driver
Static 32 seg
1/2 32 seg
1/3 32 seg
1/4 32 seg
• LCD RAM capacity
8 bits × 16 bytes (128 bits)
• Word access to LCD RAM
• All four segment output pins can be used individually as port pins.
• Common output pins not used because of the duty cycle can be used for common double-
buffering (parallel connection).
• Display possible in operating modes other than standby mode
• Choice of 11 frame frequencies
• Built-in power supply split-resistance, supplying LCD drive power
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
• A or B waveform selectable by software
• Removal of split-resistance can be controlled in software.
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 380 of 520
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13.1.2 Block Diagram
Figures 13.1 shows a block diagram of the LCD controller/driver.
φ/256 to φ/2
φw
SEGn
LPCR
LCR
LCR2
V
1
V
2
V
3
V
SS
COM
1
COM
4
SEG
32
SEG
1
V
CC
Internal data bus
Display timing generator
LCD RAM
(16 bytes)
32-bit
shift
register
LCD drive
power supply
Segment
driver
Common
data latch
Common
driver
[Legend]
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
Figure 13.1 Block Diagram of LCD Controller/Driver
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 381 of 520
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13.1.3 Pin Configuration
Table 13.1 shows the LCD controller/driver pin configuration.
Table 13.1 Pin Configuration
Name Abbr. I/O Function
Segment output pins SEG32 to SEG1 Output LCD segment drive pins
All pins are multiplexed as port pins
(setting programmable)
Common output pins COM4 to COM1 Output LCD common drive pins
Pins can be used in parallel with static or
1/2 duty
LCD power supply pins V1, V2, V3 — Used when a bypass capacitor is
connected externally, and when an
external power supply circuit is used
13.1.4 Register Configuration
Table 13.2 shows the register configuration of the LCD controller/driver.
Table 13.2 LCD Controller/Driver Registers
Name Abbr. R/W Initial Value Address
LCD port control register LPCR R/W — H'FFC0
LCD control register LCR R/W H'80 H'FFC1
LCD control register 2 LCR2 R/W — H'FFC2
LCD RAM — R/W Undefined H'F740 to H'F74F
Clock stop register 2 CKSTPR2 R/W H'FF H'FFFB
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 382 of 520
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13.2 Register Descriptions
13.2.1 LCD Port Control Register (LPCR)
Bit
Initial value
Read/Write
7
DTS1
0
R/W
6
DTS0
0
R/W
5
CMX
0
R/W
4
W
3
SGS3
0
R/W
0
SGS0
0
R/W
2
SGS2
0
R/W
1
SGS1
0
R/W
LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions.
Bits 7 to 5—Duty Cycle Sel ect 1 and 0 (DT S1, DTS0), Common Function Select (CMX)
The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether
or not the same waveform is to be output from multiple pins to increase the common drive power
when not all common pins are used because of the duty setting.
Bit 7
DTS1 Bit 6
DTS0 Bit 5
CMX
Duty Cycle
Common Drivers
Notes
0 0 0 Static COM1 (initial value) Do not use COM4, COM3, and
COM2.
1 COM
4 to COM1 COM4, COM3, and COM2 output the
same waveform as COM1.
0 1 0 1/2 duty COM2 and COM1 Do not use COM4 and COM3.
1 COM
4 to COM1 COM4 outputs the same waveform
as COM3, and COM2 outputs the
same waveform as COM1.
1 0 0 1/3 duty COM3 to COM1 Do not use COM4.
1 COM
4 to COM1 Do not use COM4.
1 1 0 1/4 duty COM4 to COM1 —
1
Bit 4—Reserved
Bit 4 is reserved. It can only be written with 0.
Section 13 LCD Controller/Driver
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Bits 3 to 0—Segment Driver Select 3 to 0 (SGS3 to SGS0)
Bits 3 to 0 select the segment drivers to be used.
Function of Pins SEG32 to SEG1
Bit 3
SGS3 Bit 2
SGS2 Bi t 1
SGS1 Bit 0
SGS0 SEG32 to
SEG29 SEG28 to
SEG25 SEG24 to
SEG21 SEG20 to
SEG17 SEG16 to
SEG13 SEG12 to
SEG9 SEG8 to
SEG5 SEG4 to
SEG1
Notes
0 0 0 0 Port Port Port Port Port Port Port Port (Initial value)
1 Port Port Port Port Port Port Port SEG
1 0 Port Port Port Port Port Port SEG SEG
1 Port Port Port Port Port SEG SEG SEG
1 0 0 Port Port Port Port SEG SEG SEG SEG
1 Port Port Port SEG SEG SEG SEG SEG
1 0 Port Port SEG SEG SEG SEG SEG SEG
1 Port SEG SEG SEG SEG SEG SEG SEG
1 0 0 0 SEG SEG SEG SEG SEG SEG SEG SEG
1 SEG SEG SEG SEG SEG SEG SEG Port
1 0 SEG SEG SEG SEG SEG SEG Port Port
1 SEG SEG SEG SEG SEG Port Port Port
1 0 0 SEG SEG SEG SEG Port Port Port Port
1 SEG SEG SEG Port Port Port Port Port
1 0 SEG SEG Port Port Port Port Port Port
1 SEG Port Port Port Port Port Port Port
Section 13 LCD Controller/Driver
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13.2.2 LCD Control Register (LCR)
Bit
Initial value
Read/Write
7
1
6
PSW
0
R/W
5
ACT
0
R/W
4
DISP
0
R/W
3
CKS3
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and
display data control, and selects the frame frequency.
LCR is initialized to H'80 upon reset.
Bit 7—Reserved
Bit 7 is reserved; it is always read as 1 and cannot be modified.
Bit 6—LCD Drive Power Supply On/Off Control (PSW)
Bit 6 can be used to turn the LCD drive power supply off when LCD display is not required in a
power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0,
or in standby mode, the LCD drive power supply is turned off regardless of the setting of this bit.
Bit 6
PSW
Description
0 LCD drive power supply off (initial value)
1 LCD drive power supply on
Bit 5—Display Function Activate (ACT)
Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts
operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless
of the setting of the PSW bit. However, register contents are retained.
Bit 5
ACT
Description
0 LCD controller/driver operation halted (initial value)
1 LCD controller/driver operates
Section 13 LCD Controller/Driver
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Bit 4—Displa y Da t a Co ntrol (DISP)
Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents.
Bit 4
DISP
Description
0 Blank data is displayed (initial value)
1 LCD RAM data is display
Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0)
Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,
and subsleep mode, the system clock (φ) is halted, and therefore display operations are not
performed if one of the clocks from φ/2 to φ/256 is selected. If LCD display is required in these
modes, φw, φw/2, or φw/4 must be selected as the operating clock.
Frame Frequency*2
Bit 3
CKS3 Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0 Operating Clock φ = 2 MHz φ = 250 kHz*1
0 * 0 0 φw 128 Hz*3 (initial value)
0 * 0 1 φw/2 64 Hz*3
0 * 1 * φw/4 32 Hz*3
1 0 0 0 φ/2 — 244 Hz
1 0 0 1 φ/4 977 Hz 122 Hz
1 0 1 0 φ/8 488 Hz 61 Hz
1 0 1 1 φ/16 244 Hz 30.5 Hz
1 1 0 0 φ/32 122 Hz —
1 1 0 1 φ/64 61 Hz —
1 1 1 0 φ/128 30.5 Hz —
1 1 1 1 φ/256 — —
*: Don’t care
Notes: 1. This is the frame frequency in active (medium-speed, φosc/16) mode when φ = 2 MHz.
2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
3. This is the frame frequency when φw = 32.768 kHz.
Section 13 LCD Controller/Driver
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13.2.3 LCD Control Regis ter 2 (LCR 2 )
Bit 7 6 5 4 3 2 1 0
LCDAB — — — CDS3 CDS2 CDS1 CDS0
Initial value 0 1 1 — 0 0 0 0
Read/Write R/W — — R/W R/W R/W R/W R/W
LCR2 is an 8-bit read/write register which controls switching between the A waveform and B
waveform and removal of split-resistance. LCR2 is initialized to H'7F upon a reset.
Bit 7—A Waveform/B Waveform Switching Control (LCDAB)
Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform.
Bit 7
LCDAB
Description
0 Drive using A waveform (initial value)
1 Drive using B waveform
Bits 6 and 5—Reserved
Bits 6 and 5 are reserved; they are always read as 1 and cannot be modified.
Bit 4—Reserved
Bit 4 is reserved; this can only be written with 0.
Section 13 LCD Controller/Driver
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Bits 3 to 0—Removal of Split-Resistance Control
These bits control whether the split-resistance is removed or connected.
Bit 3
CDS3 Bit 2
CDS2 Bit 1
CDS1
Bit 0
CDS0 Description
0 0 0 0 (initial value)
1 Split-resistance connected
1 0
1
1 0 0
1
1 0
1 Split-resistance removed
1 0 0 0 Split-resistance connected
1
1 0
1
1 0 0
1
1 0
1
Section 13 LCD Controller/Driver
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13.2.4 Clock Stop Regi ster 2 ( CKS T P R2 )
Bit
Initial value
Read/Write
7
LVDCKSTP
1
R/W
6
1
5
1
4
PW2CKSTP
1
R/W
3
AECKSTP
1
R/W
0
LDCKSTP
1
R/W
2
WDCKSTP
1
R/W
1
PW1CKSTP
1
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the LCD controller/driver is described here. For details of the
other bits, see the sections on the relevant modules.
Bit 0—LCD Controller/Driver Module Standby Mode Control (LDCKSTP)
Bit 0 controls setting and clearing of module standby mode for the LCD controller/driver.
Bit 0
LDCKSTP
Description
0 LCD controller/driver is set to module standby mode
1 LCD controller/driver module standby mode is cleared (initial value)
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 389 of 520
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13.3 Operation
13.3.1 Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
(1) Hardware Settings
a. Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.2.
VCC
V1
V2
V3
VSS
Figure 13.2 Handling of LCD Drive Power Supply when Usin g 1/2 Du ty
b. Large-panel display
As the impedance of the built-in power supply split-resistance is large, it may not be suitable
for driving a large panel. If the display lacks sharpness when using a large panel, refer to
section 13.3.4, Boosting the LCD Drive Power Supply. When static or 1/2 duty is selected, the
common output drive capability can be increased. Set CMX to 1 when selecting the duty cycle.
In this mode, with a static duty cycle pins COM4 to COM1 output the same waveform, and with
1/2 duty the COM1 waveform is output from pins COM2 and COM1, and the COM2 waveform
is output from pins COM4 and COM3.
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 390 of 520
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(2) Software Settings
a. Duty selection
Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits
DTS1 and DTS0.
b. Segment selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
c. Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see section 13.3.3, Operation in
Power-Down Modes.
d. A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 391 of 520
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13.3.2 Relationship bet ween L CD RA M and Display
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1H'F740
H'F74F SEG31SEG32SEG32SEG32SEG32 SEG31 SEG31 SEG31
COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1
Figure 13.3 LCD RAM Map (1/4 Duty)
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 392 of 520
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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SEG2 SEG2 SEG2 SEG1 SEG1 SEG1H'F740
H'F74F SEG31SEG32SEG32SEG32 SEG31 SEG31
COM3 COM2 COM1 COM3 COM2 COM1
Space not used for display
Figure 13.4 LCD RAM Map (1/3 Duty)
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 393 of 520
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Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1H'F740
H'F747
H'F74F
SEG29SEG30SEG30SEG31SEG31SEG32SEG32 SEG29
COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1
Display space
Space not used for display
Figure 13.5 LCD RAM Map (1/2 Duty)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1H'F740
H'F743
H'F74F
SEG25SEG26SEG27SEG28SEG29SEG30SEG31SEG32
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
Space not
used for
display
Display
space
Figure 13.6 LCD RAM Map (Static Mode)
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 394 of 520
REJ09B0409-0100
1 frame
M
Data
COM1
COM2
COM3
COM4
SEGn
V
1
V
2
V
3
V
SS
V
1
V
2
V
3
V
SS
V
1
V
2
V
3
V
SS
V
1
V
2
V
3
V
SS
V
1
V
2
V
3
V
SS
(a) Waveform with 1/4 duty
1 frame
M
Data
COM1
COM2
COM3
SEGn
V
1
V
2
V
3
V
SS
V
1
V
2
V
3
V
SS
V
1
V
2
V
3
V
SS
V
1
V
2
V
3
V
SS
1 frame
M
Data
COM1
COM2
SEGn
V
1
V
2,
V
3
V
SS
V
1
V
2,
V
3
V
SS
V
1
V
2,
V
3
V
SS
1 frame
M
Data
COM1
SEGn
V
1
V
SS
V
1
V
SS
(b) Waveform with 1/3 duty
(c) Waveform with 1/2 duty
(d) Waveform with static output
M: LCD alternation signal
Figure 13.7 Output Waveforms f or Each Duty Cycle (A Waveform)
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 395 of 520
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M
Data
COM1
COM2
SEGn
V1
V2, V3
VSS
V1
V2, V3
VSS
M
Data
COM1
SEGn
V1
VSS
V1
VSS
(c) Waveform with 1/2 duty M: LCD alternation signal
(d) Waveform with static output
1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame
(b) Waveform with 1/3 duty
M
Data
COM3
SEGn
COM1
V1
V2
V3
VSS
COM2 V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
(a) Waveform with 1/4 duty
M
Data
COM1
COM2
COM3
COM4
SEGn
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame
V1
V2, V3
VSS
Figure 13.8 Output Waveforms f or Each Duty Cycle (B Waveform)
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 396 of 520
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Table 13.3 Output Levels
Data 0 0 1 1
M 0 1 0 1
Static Common output V1 V
SS V
1 V
SS
Segment output V1 V
SS V
SS V
1
1/2 duty Common output V2, V3 V
2, V3 V
1 V
SS
Segment output V1 V
SS V
SS V
1
1/3 duty Common output V3 V
2 V
1 V
SS
Segment output V2 V
3 V
SS V
1
1/4 duty Common output V3 V
2 V
1 V
SS
Segment output V2 V
3 V
SS V
1
M: LCD alternation signal
13.3.3 Operation in Power-Down Modes
This LSI the LCD controller/driver can be operated even in the power-down modes. The operating
state of the LCD controller/driver in the power-down modes is summarized in table 13.4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φw, φw/2, or φw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to the
LCD panel in this case, it is essential to ensure that φw, φw/2, or φw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 397 of 520
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Table 13.4 Power-Down Modes and Display Operation
Mode
Reset
Active
Sleep
Watch
Sub-active
Sub-sleep
Standby Module
Standby
Clock φ Runs Runs Runs Stops Stops Stops Stops Stops*4
φw Runs Runs Runs Runs Runs Runs Stops*1 Stops*4
ACT = 0 Stops Stops Stops Stops Stops Stops Stops*2 Stops Display
operation ACT = 1 Stops Functions Functions Functions*3Functions*3Functions*3 Stops*2 Stops
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if φw, φw/2, or φw/4 is selected as the operating
clock.
4. The clock supplied to the LCD stops.
13.3.4 Boosting the LCD Drive Power Supply
When a large panel is driven, the on-chip power supply capacity may be insufficient. If the power
supply capacity is insufficient when VCC is used as the power supply, the power supply impedance
must be reduced. This can be done by connecting bypass capacitors of around 0.1 to 0.3 µF to pins
V1 to V3, as shown in figure 13.9, or by adding a split-resistance externally.
This LSI
V
CC
V
SS
V
1
V
2
V
3
R
R
R
R = several kΩ to
several MΩ
C = 0.1 to 0.3 µF
R
Figure 13.9 Connection of External Split-Resistance
Section 13 LCD Controller/Driver
Rev. 1.00 Dec. 19, 2007 Page 398 of 520
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Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 399 of 520
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Section 14 Power-On Reset and Low-Voltage Detection
Circuits
14.1 Overview
This LSI can include a power-on reset circuit and low-voltage detection circuit.
The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect)
and LVDR (reset by low voltage detect) circuits.
This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the
power supply voltage fall and to recreate the state before the power supply voltage fall when the
power supply voltage rises again.
Even if the power supply voltage falls, the unstable state when the power supply voltage falls
below the guaranteed operating voltage can be removed by entering standby mode* when
exceeding the guaranteed operating voltage and during normal operation. Thus, system stability
can be improved. If the power supply voltage falls more, the reset state is automatically entered. If
the power supply voltage rises again, the reset state is held for a specified period, then active mode
is automatically entered.
Figure 14.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
Note: * The voltage maintained in standby mode is the same as the RAM data retaining voltage
(VRAM). See section 17.2.2, DC Characteristics, for information on retaining voltage.
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 400 of 520
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14.1.1 Features
The features of the power-on reset circuit and low-voltage detection circuit are described below.
• Power-on reset circuit
Uses an external capacitor to generate an internal reset signal when power is first supplied.
• Low-voltage detection circuit
LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the
voltage falls below a specified value.
LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls
below or rises above respective specified values.
Two pairs of detection levels for reset generation voltage are available: when only the LVDR
circuit is used, or when the LVDI and LVDR circuits are both used. In addition, power supply
rise/drop detection voltages and a detection voltage reference voltage may be input from an
external source, allowing the detection level to be set freely by the user.
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 401 of 520
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14.1.2 Block Diagram
A block diagram of the power-on reset circuit and low-voltage detection circuit are shown in
figure 14.1.
PSS:
LVDCR:
LVDSR:
LVDRES:
LVDINT:
Vreset:
Vint:
extD:
extU:
Vref:
Prescaler S
Low-voltage-detection control register
Low-voltage-detection status register
Low-voltage-detection reset signal
Low-voltage-detection interrupt signal
Reset detection voltage
Power-supply fall/rise detection voltage
Power supply drop detection voltage input pin
Power supply rise detection voltage input pin
Reference voltage input pin
RES
φCK
RPSS
Vcc
R
S
Q
OVF
Vreset
Vref
extU
extD
Vint
External
reference voltage
generator
On-chip
reference voltage
generator
[Legend]
LVDRES
Interrupt
control
circuit
LVDCR
LVDSR
Internal reset
signal
Power-on reset circuit
Low-voltage detection circuit
Interrupt
request
LVDINT
Noise
canceler
Noise
canceler
+
−
+
−
Ladder
resistor
External
ladder
resistor
External
power
supply
Internal data bus
Figure 14.1 Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 402 of 520
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14.1.3 Pin Description
The pins of the power-on reset circuit and low-voltage detection circuit are listed in table 14.1.
Table 14.1 Pin Description
Pin Symbol I/O Function
Low-voltage detection circuit
reference voltage input pin
Vref Input Reference voltage input for low-
voltage detection circuit
Low-voltage detection circuit power
supply drop detection voltage input
pin
extD Input Power supply drop detection voltage
input pin for low-voltage detection
circuit
Low-voltage detection circuit power
supply rise detection voltage input
pin
extU Input Power supply rise detection voltage
input pin for low-voltage detection
circuit
14.1.4 Register Descriptions
The registers of the power-on reset circuit and low-voltage detection circuit are listed in table 14.2.
Table 14.2 Register Descriptions
Name Symbol R/W Initial Value Address
Low-voltage detection control register LVDCR R/W H'00 H'FF86
Low-voltage detection status register LVDSR R/W H'00 H'FF87
Low-voltage detection counter LVDCNT R H'00 H'FFC3
14.2 Individual Register Descriptions
14.2.1 Low-Voltage Detection Control Register (LVDCR)
Bit 7 6 5 4 3 2 1 0
LVDE —
VINTDSEL VINTUSEL LVDSEL LVDRE LVDDE LVDUE
Initial value 0* 0 0 0 0* 0
* 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by power-
on resets and watchdog timer resets.
Section 14 Power-On Reset and Low-Voltage Detection Circuits
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LVDCR is an 8-bit read/write register. It is used to control whether or not the low-voltage
detection circuit is used, settings for external input of power supply rise and drop detection
voltages, the LVDR detection level setting, enabling or disabling of resets triggered by the low-
voltage detection reset circuit (LVDR), and enabling or disabling of interrupts triggered by power
supply voltage drops or rises.
Bit 7—LVD Enable (LVDE )
This bit is used to control whether or not the low-voltage detection circuit is used.
Bit 7
LVDE
Description
0 Low-voltage detection circuit not used (standby status) (initial value)
1 Low-voltage detection circuit used
Bit 6—Reserved
This bit is a read/write enabled reserved bit.
Bit 5—Power Supply Drop (LVDD) Detection Level External Input Select (VINTDSEL)
This bit is used to select the power supply drop detection level.
Bit 5
VINTDSEL
Description
0 LVDD detection level generated by on-chip ladder resistor (initial value)
1 LVDD detection level input to extD pin
Bit 4—Power Supply Rise (LVDU) Detection Level External Input Select (VINTUSEL)
This bit is used to select the power supply rise detection level.
Bit 4
VINTUSEL
Description
0 LVDU detection level generated by on-chip ladder resistor (initial value)
1 LVDU detection level input to extU pin
Section 14 Power-On Reset and Low-Voltage Detection Circuits
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Bit 3—LVDR Detection Level Select (LVDSEL)
This bit is used to select the LVDR detection level. Select 2.3 V (typical) reset if voltage rise and
drop detection interrupts are to be used. For reset detection only, Select 3.3 V (typical) reset.
Bit 3
LVDSEL
Description
0 Reset detection voltage 2.3 V (typ.) (initial value)
1 Reset detection voltage 3.3 V (typ.)
Bit 2—LVDR Enable (LVDRE)
This bit is used to control whether resets triggered by LVDR are enabled or disabled.
Bit 2
LVDRE
Description
0 LVDR resets disabled (initial value)
1 LVDR resets enabled
Bit 1—Voltage Drop Interrupt Enable (LVDDE)
This bit is used to control whether voltage drop interrupt requests are enabled or disabled.
Bit 1
LVDDE
Description
0 Voltage drop interrupt requests disabled (initial value)
1 Voltage drop interrupt requests enabled
Bit 0—Voltage Rise Interrupt Enable (LVDUE)
This bit is used to control whether voltage rise interrupt requests are enabled or disabled.
Bit 0
LVDUE
Description
0 Voltage rise interrupt requests disabled (initial value)
1 Voltage rise interrupt requests enabled
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 405 of 520
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Table 14.3 shows the relationship between LVDCR settings and function selections. Refer to table
14.3 when making settings to LVDCR.
Table 14.3 LVDCR Settings and Function Selections
LVDCR Setting Value
LVDE LVDSEL LVDRE LVDDE LVDUE Power-on
Reset
Low-Voltage
Detection
Reset
Low-Voltage
Detection
Voltage Drop
Interrupt
Low-Voltage
Detection
Voltage Rise
Interrupt
0 * * * * — — —
1 1 1 0 0 — —
1 0 0 1 0 — —
1 0 0 1 1 —
1 0 1 1 1
Note: Setting values marked with an asterisk (*) are invalid.
14.2.2 Low-Voltage Detection Status Regis ter (L VD SR )
Bit 7 6 5 4 3 2 1 0
OVF — — — VREFSEL — LVDDF LVDUF
Initial value 0* 0 0 0 0 0 0* 0
*
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Note: * These bits initialized by resets trigged by LVDR.
LVDSR is an 8-bit read/write register. It is used to control external input selection, indicates when
the reference voltage is stable, and indicates if the power supply voltage goes below or above a
specified range.
Bit 7—LVD Reference Voltage Stabilized Flag (OVF)
This bit indicates when the low-voltage detection counter (LVDCNT) overflows.
Bit 7
OVF
Description
0 [Clearing condition] (initial value)
When 0 is written after reading 1
1 [Setting condition]
When the low-voltage detection counter (LVDCNT) overflows
Section 14 Power-On Reset and Low-Voltage Detection Circuits
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Bits 6 to 4—Reserved
These bits are read/write enabled reserved bits.
Bit 3—Reference Voltage External Input Select (VREFSEL)
This bit is used to select the reference voltage.
Bit 3
VREFSEL
Description
0 The on-chip circuit is used to generate the reference voltage (initial value)
1 The reference voltage is input to the Vref pin from an external source
Bit 2—Reserved
This bit is reserved. It is always read as 0 and cannot be written to.
Bit 1—LVD Power Supply Voltage Drop Flag (LVDDF)
This bit indicates when a power supply voltage drop has been detected.
Bit 1
LVDDF
Description
0 [Clearing condition] (initial value)
When 0 is written after reading 1
1 [Setting condition]
When the power supply voltage drops below Vint(D)
Bit 0—LVD Power Supply Voltage Rise Flag (LVDUF)
This bit indicates when a power supply voltage rise has been detected.
Bit 0
LVDUF
Description
0 [Clearing condition]
When 0 is written after reading 1 (initial value)
1 [Setting condition]
When the power supply voltage drops below Vint(D) while the LVDUE bit in
LVDCR is set to 1, and it rises above Vint(U) before dropping below Vreset1
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 407 of 520
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14.2.3 Low-Voltage Detection Counter (LVDCNT)
Bit 7 6 5 4 3 2 1 0
CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0
Initial value 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R
LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The
counter increments using φ/4 as the clock source until it overflows by switching from H'FF to
H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip
reference voltage generator has stabilized. If the LVD function is used, it is necessary to stand by
until the counter has overflowed. The initial value of LVDCNT is H'00.
14.2.4 Clock Stop Register 2 (CKSTPR2)
Bit 7 6 5 4 3 2 1 0
LVDCKSTP — — PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W — — R/W R/W R/W R/W R/W
CKSTPR2 is an 8-bit read/write register. It is used to control the module’s module standby mode.
Only the bits relevant to the LVD function are described in this section. Refer to the sections on
the other modules for information about the other bits.
Bit 7—LVD Modul e St andby Control (L VD CKSTP)
This bit is used to control setting of the LVD function to module standby status and cancellation of
that status.
Bit 7
LVDCKSTP
Description
0 Sets LVD to module standby status
1 Cancels LVD module standby status (initial value)
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 408 of 520
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14.3 Operation
14.3.1 Power-On Reset Circuit
Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the on-chip pull-up resistor (typ. 100 kΩ). Since the state of the RES pin is transmitted within the
chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin
reaches the specified value, the prescaler S is released from its reset state and it starts counting.
The OVF signal is generated to release the internal reset signal after the prescaler S has counted
131,072 clock (φ) cycles. The noise cancellation circuit of approximately 100 ns is incorporated to
prevent the incorrect operation of the chip by noise on the RES pin.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle after
power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance
which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power
supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) ≤ 80 × CRES (µF) ± 10/fOSC (MHz)
(tPWON ≤ 3000 ms, CRES ≥ 0.22 µF, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 409 of 520
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RES
Vcc
PSS-reset
signal
Internal reset
signal
Vss
Vss
OVF
131,072 cycles
PSS counter starts Reset released
tPWON
Vpor
Figure 14.2 Operational Timing of Power-On Reset Circui t
14.3.2 Low-Voltage Detection Circuit
(1) LVDR (Reset by Low Volta ge Detect) Circuit
Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state
after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait
for 150 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have
stabilized, based on overflow of LVDNT, etc., then set the LVDRE bit in LVDCR to 1. After that,
the output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and
LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.3 V), the LVDR
clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock (φ) cycles, and
then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in
LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 410 of 520
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LVDRES
V
CC
Vreset
V
SS
V
LVDRmin
OVF
PSS-reset
signal
Internal reset
signal 131,072 cycles
PSS counter starts Reset released
Figure 14.3 Operational Timing of LVDR Circuit
(2) LVDI (Interrupt by Low Voltage Detect) Circuit
Figure 14.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after
a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 150
µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized,
based on overflow of LVDNT, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After
that, the output settings of ports must be made. To cancel the low-voltage detection circuit, first
the LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared
to 0. The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits
because incorrect operation may occur.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to standby mode or watch
mode. Until this processing is completed, the power supply voltage must be higher than the lower
limit of the guaranteed operating voltage.
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 411 of 520
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When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above
Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously
generated.
If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function
is performed.
LVDINT
Vcc Vint (D)
Vint (U)
VSS
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
LVDDE
Vreset1
Figure 14.4 Operational Tim ing of LVDI Circuit
The reference voltage, power supply voltage drop detection level, and power supply voltage rise
detection level can be input to the LSI from external sources via the Vref, extD, and extU pins.
Figure 14.5 shows the operational timing using input from the Vref, extD, and extU pins.
First, make sure that the voltages input to pins extD and extU are set to higher levels than the
interrupt detection voltage Vexd. After initial settings are made, a power supply drop interrupt is
generated if the extD input voltage drops below Vexd. After a power supply drop interrupt is
generated, if the external power supply voltage rises and the extU input voltage rises higher than
Vexd, a power supply rise interrupt is generated. As with the on-chip circuit, the above function
should be used in conjunction with LVDR (Vreset1) when the LVDI function is used.
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 412 of 520
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LVDINTD
extD input voltage
extU input voltage
Vreset1
Vexd
(4)
(3)
(2)
(1)
V
SS
LVDINTU
LVDDF
IRQ0 interrupt
generated
IRQ0 interrupt
generated
LVDUF
External power
supply voltage
Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit
(Using Pins Vref, extD, and extU)
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 413 of 520
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Figure 14.6 shows a usage example for the LVD function employing pins Vref, extD, and extU.
Setting conditions:
• Vref = 1.3 V external input (This Vref value results in a Vreset value of 2.5 V.)
• Power supply drop detection voltage input of 2.7 V from extD
• Power supply rise detection voltage input of 2.9 V from extU
• 1 MΩ variable resistor connected externally
Vref
extU
extD
R1 =
517 kΩ
R2 =
33 kΩ
R3 =
450 kΩ
External reference
voltage 1.3 V
On-chip reference
voltage generator
LVDRES
Interrupt
controller
LVDCR
LVDSR
Interrupt
request
LVDINT
+
−
+
−
On-chip
ladder
resistor
External power
supply voltage
R1
R2
D1
U1 U2
D2
Figure 14.6 LVD Function Usage Example Employing Pins Vref, extD, and extU
Below is an explanation of the method for calculating the external resistor values when using the
Vref, extD, and extU pins for input of reference and detection voltages from sources external to
the LSI.
Procedure:
1. First, determine the overall resistance value, R. The current consumed by the resistor is
determined by the value of R. A lower R will result in a greater current flow, and a higher R
will result in a reduced current flow. The value of R is dependent on the configuration of the
system in which the LSI is installed.
2. Determine the power supply drop detection voltage (Vint(D) and the power supply rise
detection voltage (Vint(U).
3. Using a resistance value calculation table like the one shown below, plug in values for R,
Vreset1, Vint(D), and Vint(U) to calculate the values of Vref, R1, R2, and R3.
Section 14 Power-On Reset and Low-Voltage Detection Circuits
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Resistance Value Calculation Table
Ex. No Vref (V) R (kΩ) Vreset1 Vint(D) Vint(U) R1 (kΩ) R2 (kΩ) R3 (kΩ)
1 1.30 1000 2.5 2.7 2.9 517 33 450
2 1.41 1000 2.7 2.9 3 514 16 470
3 1.57 1000 3 3.2 3.5 511 42 447
4 2.09 1000 4 4.5 4.7 536 20 444
4. Using an error calculation table like the one shown below, plug in values for R1, R2, R3, and
Vref to calculate the deviation of Vreset1, Vint(D), and Vint(U). Make sure to double check
the maximum and minimum values for each value.
Error Calculation Table
Resistance Value
Error (%)
Vref (V) R1
(kΩ) R2
(kΩ) R3
(kΩ) 5 Comparator
Error (V)
Vreset1
(V) Vint(D)
(V) Vint(U)
(V)
1.3 517 33 450 R1+Err, R2/R3-Err 0.1 2.59 2.94 3.15
0 2.49 2.84 3.05
-0.1 2.39 2.74 2.95
R1-Err, R2/R3+Err 0.1 2.59 2.66 2.85
0 2.49 2.56 2.75
-0.1 2.39 2.46 2.65
R1/R2/R3 No Err 0.1 2.59 2.79 2.99
0 2.49 2.69 2.89
-0.1 2.39 2.59 2.79
R1/R2+Err, R3-Err 0.1 2.59 2.93 3.16
0 2.49 2.83 3.06
-0.1 2.39 2.73 2.96
R1/R2-Err, R3+Err 0.1 2.59 2.67 2.84
0 2.49 2.57 2.74
-0.1 2.39 2.47 2.64
Section 14 Power-On Reset and Low-Voltage Detection Circuits
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(3) Operation and Cancellation Setting Procedure Using LVDR and LVDI
Settings should be made as indicated below in order to ensure proper operation of the low voltage
detection circuit or to cancel operation. Figure 14.7 shows the setting timing for low voltage
detection circuit operation and cancellation.
1. To turn on the low voltage detection circuit, first set the LVDE bit in LVDCR to 1.
2. After waiting for LVDCNT overflow, etc., to ensure that the stabilization time (tLVDON = 150 µs)
for the reference voltage and low voltage detection power supply has elapsed, clear bits
LVDDF and LVDUF in LVDSR to 0. If necessary, set the LVDRE, LVDDE, and LVDUE bits
in LVDCR to 1.
3. To cancel operation of the low voltage detection circuit, clear bits LVDRE, LVDDE, and
LVDUE to 0, then clear bit LVDE to 0. Bit LVDE should not be cleared at the same time as
bits LVDRE, LVDDE, and LVDUE to avoid malfunction.
LVDRE
LVDDE
LVDUE
tLVDON
LVDE
Figure 14.7 Low Voltage Detec ti on Cir c ui t Operation and Cancellation Setting Timing
Section 14 Power-On Reset and Low-Voltage Detection Circuits
Rev. 1.00 Dec. 19, 2007 Page 416 of 520
REJ09B0409-0100
Section 15 Power Supply Circuit
Rev. 1.00 Dec. 19, 2007 Page 417 of 520
REJ09B0409-0100
Section 15 Power Supply Circuit
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the
internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the
voltage of the power supply connected to the external VCC pin. As a result, the current consumed
when an external power supply is used at 3.0 V or above can be held down to virtually the same
low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the
internal voltage will be practically the same as the external voltage. It is, of course, also possible
to use the same level of external power supply voltage and internal power supply voltage without
using the internal power supply step-down circuit.
15.1 When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1
µF between CVCC and VSS, as shown in figure 15.1. The internal step-down circuit is made effective
simply by adding this external circuit. In the external circuit interface, the external power supply
voltage connected to VCC and the GND potential connected to VSS are the reference levels. For
example, for port input/output levels, the VCC level is the reference for the high level, and the VSS
level is that for the low level. The A/D converter analog power supply is not affected by the
internal step-down circuit.
CV
CC
V
SS
Internal
logic
Step-down circuit
Internal
power
supply
Stabilization
capacitance
(approx. 0.1 µF)
V
CC
V
CC
= 2.7 to 5.5 V
Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used
Section 15 Power Supply Circuit
Rev. 1.00 Dec. 19, 2007 Page 418 of 520
REJ09B0409-0100
15.2 When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply
to the CVCC pin and VCC pin, as shown in figure 15.2. The external power supply is then input
directly to the internal power supply. The permissible range for the power supply voltage is 2.7 V
to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more
than 3.6 V) is input.
CV
CC
V
SS
Internal
logic
Step-down circuit
Internal
power
supply
V
CC
V
CC
= 2.7 to 3.6 V
Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 419 of 520
REJ09B0409-0100
Section 16 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified by functional modules.
• The data bus width is indicated.
• The number of access states is indicated.
2. Register bits
• Bit configurations of the registers are described in the same order as the register addresses.
• Reserved bits are indicated by in the bit name column.
• When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 420 of 520
REJ09B0409-0100
16.1 Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name Abbre-
viation Bit No Address
Module
Name Data Bus
Width Access
State
Flash memory control register 1 FLMCR1 8 H'F020 ROM 8 2
Flash memory control register 2 FLMCR2 8 H'F021 ROM 8 2
Flash memory power control
register
FLPWCR 8 H'F022 ROM 8 2
Erase block register EBR 8 H'F023 ROM 8 2
Flash memory enable register FENR 8 H'F02B ROM 8 2
Low-voltage detection control
register
LVDCR 8 H'FF86 LVD 8 2
Low-voltage detection status
register
LVDSR 8 H'FF87 LVD 8 2
Event counter PWM compare
register H
ECPWCRH 8 H'FF8C AEC*1 8 2
Event counter PWM compare
register L
ECPWCRL 8 H'FF8D AEC*1 8 2
Event counter PWM data register H ECPWDRH 8 H'FF8E AEC*1 8 2
Event counter PWM data register L ECPWDRL 8 H'FF8F AEC*1 8 2
Wakeup edge select register WEGR 8 H'FF90 Interrupts 8 2
Serial port control register SPCR 8 H'FF91 SCI3 8 2
Input pin edge select register AEGSR 8 H'FF92 AEC*1 8 2
Event counter control register ECCR 8 H'FF94 AEC*1 8 2
Event counter control/status
register
ECCSR 8 H'FF95 AEC*1 8 2
Event counter H ECH 8 H'FF96 AEC*1 8 2
Event counter L ECL 8 H'FF97 AEC*1 8 2
Serial mode register SMR 8 H'FFA8 SCI3 8 3
Bit rate register BRR 8 H'FFA9 SCI3 8 3
Serial control register 3 SCR3 8 H'FFAA SCI3 8 3
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 421 of 520
REJ09B0409-0100
Register Name Abbre-
viation Bit No Address
Module
Name Data Bus
Width Access
State
Transmit data register TDR 8 H’FFAB SCI3 8 3
Serial status register SSR 8 H’FFAC SCI3 8 3
Receive data register RDR 8 H’FFAD SCI3 8 3
Timer mode register A TMA 8 H’FFB0 Timer A 8 2
Timer counter A TCA 8 H’FFB1 Timer A 8 2
Timer control/status register W TCSRW 8 H’FFB2 WDT*2 8 2
Timer counter W TCW 8 H’FFB3 WDT*2 8 2
Timer mode register C TMC 8 H’FFB4 Timer C 8 2
Timer counter C /
Timer load register C
TCC/
TLC
8 H’FFB5 Timer C 8 2
Timer control register F TCRF 8 H’FFB6 Timer F 8 2
Timer control status register F TCSRF 8 H’FFB7 Timer F 8 2
8-bit timer counter FH TCFH 8 H’FFB8 Timer F 8 2
8-bit timer counter FL TCFL 8 H’FFB9 Timer F 8 2
Output compare register FH OCRFH 8 H’FFBA Timer F 8 2
Output compare register FL OCRFL 8 H’FFBB Timer F 8 2
Timer mode register G TMG 8 H’FFBC Timer G 8 2
Input capture register GF ICRGF 8 H’FFBD Timer G 8 2
Input capture register GR ICRGR 8 H’FFBE Timer G 8 2
LCD port control register LPCR 8 H’FFC0 LCD*3 8 2
LCD control register LCR 8 H’FFC1 LCD*3 8 2
LCD control register 2 LCR2 8 H’FFC2 LCD*3 8 2
Low-voltage detection counter LVDCNT 8 H’FFC3 LVD 8 2
A/D result register H ADRRH 8 H’FFC4 A/D converter 8 2
A/D result register L ADRRL 8 H’FFC5 A/D converter 8 2
A/D mode register AMR 8 H’FFC6 A/D converter 8 2
A/D start register ADSR 8 H’FFC7 A/D converter 8 2
Port mode register 1 PMR1 8 H'FFC8 I/O port 8 2
Port mode register 2 PMR2 8 H'FFC9 I/O port 8 2
Port mode register 3 PMR3 8 H'FFCA I/O port 8 2
Port mode register 5 PMR5 8 H'FFCC I/O port 8 2
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 422 of 520
REJ09B0409-0100
Register Name Abbre-
viation Bit No Address
Module
Name Data Bus
Width Access
State
PWM2 control register PWCR2 8 H’FFCD 10-bit PWM 8 2
PWM2 data register U PWDRU2 8 H’FFCE 10-bit PWM 8 2
PWM2 data register L PWDRL2 8 H’FFCF 10-bit PWM 8 2
PWM1 control register PWCR1 8 H’FFD0 10-bit PWM 8 2
PWM1 data register U PWDRU1 8 H’FFD1 10-bit PWM 8 2
PWM1 data register L PWDRL1 8 H’FFD2 10-bit PWM 8 2
Port data register 1 PDR1 8 H’FFD4 I/O port 8 2
Port data register 3 PDR3 8 H’FFD6 I/O port 8 2
Port data register 4 PDR4 8 H’FFD7 I/O port 8 2
Port data register 5 PDR5 8 H’FFD8 I/O port 8 2
Port data register 6 PDR6 8 H’FFD9 I/O port 8 2
Port data register 7 PDR7 8 H’FFDA I/O port 8 2
Port data register 8 PDR8 8 H’FFDB I/O port 8 2
Port data register 9 PDR9 8 H’FFDC I/O port 8 2
Port data register A PDRA 8 H’FFDD I/O port 8 2
Port data register B PDRB 8 H’FFDE I/O port 8 2
Port pull-up control register 1 PUCR1 8 H’FFE0 I/O port 8 2
Port pull-up control register 3 PUCR3 8 H’FFE1 I/O port 8 2
Port pull-up control register 5 PUCR5 8 H’FFE2 I/O port 8 2
Port pull-up control register 6 PUCR6 8 H’FFE3 I/O port 8 2
Port control register 1 PCR1 8 H’FFE4 I/O port 8 2
Port control register 3 PCR3 8 H’FFE6 I/O port 8 2
Port control register 4 PCR4 8 H’FFE7 I/O port 8 2
Port control register 5 PCR5 8 H’FFE8 I/O port 8 2
Port control register 6 PCR6 8 H’FFE9 I/O port 8 2
Port control register 7 PCR7 8 H’FFEA I/O port 8 2
Port control register 8 PCR8 8 H’FFEB I/O port 8 2
Port mode register 9 PMR9 8 H’FFEC I/O port 8 2
Port control register A PCRA 8 H’FFED I/O port 8 2
Port mode register B PMRB 8 H’FFEE I/O port 8 2
System control register 1 SYSCR1 8 H’FFF0 SYSTEM 8 2
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 423 of 520
REJ09B0409-0100
Register Name Abbre-
viation Bit No Address
Module
Name Data Bus
Width Access
State
System control register 2 SYSCR2 8 H'FFF1 SYSTEM 8 2
IRQ edge select register IEGR 8 H'FFF2 Interrupts 8 2
Interrupt enable register 1 IENR1 8 H'FFF3 Interrupts 8 2
Interrupt enable register 2 IENR2 8 H'FFF4 Interrupts 8 2
Oscillator control register OSCCR 8 H'FFF5 CPG 8 2
Interrupt request register 1 IRR1 8 H'FFF6 Interrupts 8 2
Interrupt request register 2 IRR2 8 H'FFF7 Interrupts 8 2
Timer mode register W TMW 8 H'FFF8 WDT*2 8 2
Wakeup interrupt request register IWPR 8 H’FFF9 Interrupts 8 2
Clock stop register 1 CKSTPR1 8 H'FFFA SYSTEM 8 2
Clock stop register 2 CKSTPR2 8 H'FFFB SYSTEM 8 2
Notes: 1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 424 of 520
REJ09B0409-0100
16.2 Register Bits
Register bit names of the on-chip peripheral modules are described below.
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
FLMCR1 — SWE ESU PSU EV PV E P ROM
FLMCR2 FLER — — — — — — —
FLPWCR PDWND — — — — — — —
EBR — — — EB4 EB3 EB2 EB1 EB0
FENR FLSHE — — — — — — —
LVDCR LVDE — VINTDSEL VINTUSEL LVDSEL LVDRE LVDDE LVDUE
LVDSR OVF — — — VREFSEL — LVDDF LVDUF
Low-
voltage
detect
circuit
ECPWCRH ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 AEC*1
ECPWCRL ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
ECPWDRH ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
ECPWDRL ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
WEGR WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Interrupts
SPCR — — SPC32 — SCINV3 SCINV2 — — SCI3
AEGSR AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME — AEC*1
ECCR ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 —
ECCSR OVH OVL — CH2 CUEH CUEL CRCH CRCL
ECH ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0
ECL ECL7 ECL6 ECL5 ECL4 ECL3 ECL2 ECL1 ECL0
SMR COM CHR PE PM STOP MP CKS1 CKS0 SCI3
BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
SCR3 TIE RIE TE RE MPIE TEIE CKE1 CKE0
TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0
SSR TDRE RDRF OER FER PER TEND MPBR MPBT
RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0
TMA — — — — TMA3 TMA2 TMA1 TMA0 Timer A
TCA TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0
TCSRW B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST WDT*2
TCW TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 425 of 520
REJ09B0409-0100
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
TMC TMC7 TMC6 TMC5 — — TMC2 TMC1 TMC0 Timer C
TCC/
TLC
TCC7/
TLC7
TCC6/
TLC6
TCC5/
TLC5
TCC4/
TLC4
TCC3/
TLC3
TCC2/
TLC2
TCC1/
TLC1
TCC0/
TLC0
TCRF TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Timer F
TCSRF OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL
TCFH TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0
TCFL TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0
OCRFH OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
OCRFL OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
TMG OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Timer G
ICRGF ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0
ICRGR ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0
LPCR DTS1 DTS0 CMX — SGS3 SGS2 SGS1 SGS0 LCD*3
LCR — PSW ACT DISP CKS3 CKS2 CKS1 CKS0
LCR2 LCDAB — — — CDS3 CDS2 CDS1 CDS0
LVDCNT CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Low-
voltage
detect
circuit
ADRRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2
ADRRL ADR1 ADR0 — — — — — —
A/D
converter
AMR CKS TRGE — — CH3 CH2 CH1 CH0
ADSR ADSF — — — — — — —
PMR1 IRQ3 — — IRQ4 TMIG — — — I/O port
PMR2 — — POF1 — — WDCKS NCS IRQ0
PMR3 AEVL AEVH — — — TMOFH TMOFL UD
PMR5 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0
PWCR2 — — — — — PWCR22 PWCR21 PWCR20
PWDRU2 — — — — — — PWDRU21 PWDRU20
10-bit
PWM
PWDRL2 PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20
PWCR1 — — — — — PWCR12 PWCR11 PWCR10
PWDRU1 — — — — — — PWDRU11 PWDRU10
PWDRL1 PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10
PDR1 P17 — — P14 P13 — — — I/O port
PDR3 P37 P36 P35 P34 P33 P32 P31 P30
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 426 of 520
REJ09B0409-0100
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
PDR4 — — — — P43 P42 P41 P40 I/O port
PDR5 P57 P56 P55 P54 P53 P52 P51 P50
PDR6 P67 P66 P65 P64 P63 P62 P61 P60
PDR7 P77 P76 P75 P74 P73 P72 P71 P70
PDR8 P87 P86 P85 P84 P83 P82 P81 P80
PDR9 — — P95 P94 P93 P92 P91 P90
PDRA — — — — PA3 PA2 PA1 PA0
PDRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PUCR1 PUCR17 — — PUCR14 PUCR13 — — —
PUCR3 PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30
PUCR5 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PUCR6 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
PCR1 PCR17 — — PCR14 PCR13 — — —
PCR3 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30
PCR4 — — — — — PCR42 PCR41 PCR40
PCR5 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50
PCR6 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60
PCR7 PCR77 PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70
PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80
PMR9 — — — — — — PWM2 PWM1
PCRA — — — — PCRA3 PCRA2 PCRA1 PCRA0
PMRB — — — — IRQ1 — — —
SYSCR1 SSBY STS2 STS1 STS0 LSON — MA1 MA0 SYSTEM
SYSCR2 — — — NESEL DTON MSON SA1 SA0
IEGR — — — IEG4 IEG3 — IEG1 IEG0 Interrupts
IENR1 IENTA — IENWP IEN4 IEN3 IENEC2 IEN1 IEN0
IENR2 IENDT IENAD — IENTG IENTFH IENTFL IENTC IENEC
OSCCR SUBSTP — — — — IRQAECF OSCF — CPG
IRR1 IRRTA — — IRRI4 IRRI3 IRREC2 IRRI1 IRRI0 Interrupts
IRR2 IRRDT IRRAD — IRRTG IRRTFH IRRTFL IRRTC IRREC
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 427 of 520
REJ09B0409-0100
Register
Abbreviation
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
TMW — — — — CKS3 CKS2 CKS1 CKS0 WDT*2
IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Interrupts
CKSTPR1 — — S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP SYSTEM
CKSTPR2 LVDCKSTP — — PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Notes: 1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 428 of 520
REJ09B0409-0100
16.3 Register States in Each Operating Mode
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
FLMCR1 Initialized — — Initialized Initialized Initialized Initialized ROM
FLMCR2 Initialized — — — — — —
FLPWCR Initialized — — — — — —
EBR Initialized — — Initialized Initialized Initialized Initialized
FENR Initialized — — — — — —
LVDCR Initialized — — — — — —
LVDSR Initialized — — — — — —
Low-
voltage
detect
circuit
ECPWCRH Initialized — — — — — — AEC*1
ECPWCRL Initialized — — — — — —
ECPWDRH Initialized — — — — — —
ECPWDRL Initialized — — — — — —
WEGR Initialized — — — — — — Interrupts
SPCR Initialized — — — — — — SCI3
AEGSR Initialized — — — — — — AEC*1
ECCR Initialized — — — — — —
ECCSR Initialized — — — — — —
ECH Initialized — — — — — —
ECL Initialized — — — — — —
SMR Initialized — — Initialized — — Initialized SCI3
BRR Initialized — — Initialized — — Initialized
SCR3 Initialized — — Initialized — — Initialized
TDR Initialized — — Initialized — — Initialized
SSR Initialized — — Initialized — — Initialized
RDR Initialized — — Initialized — — Initialized
TMA Initialized — — — — — — Timer A
TCA Initialized — — — — — —
TCSRW Initialized — — — — — — WDT*2
TCW Initialized — — — — — —
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 429 of 520
REJ09B0409-0100
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
TMC Initialized — — — — — — Timer C
TCC Initialized — — — — — —
TLC Initialized — — — — — —
TCRF Initialized — — — — — — Timer F
TCSRF Initialized — — — — — —
TCFH Initialized — — — — — —
TCFL Initialized — — — — — —
OCRFH Initialized — — — — — —
OCRFL Initialized — — — — — —
TMG Initialized — — — — — — Timer G
ICRGF Initialized — — — — — —
ICRGR Initialized — — — — — —
LPCR Initialized — — — — — — LCD*3
LCR Initialized — — — — — —
LCR2 Initialized — — — — — —
LVDCNT Initialized — — — — — — Low-
voltage
detect
circuit
ADRRH — — — — — — —
ADRRL — — — — — — —
A/D
converter
AMR Initialized — — — — — —
ADSR Initialized — — Initialized Initialized Initialized Initialized
PMR1 Initialized — — — — — — I/O port
PMR2 Initialized — — — — — —
PMR3 Initialized — — — — — —
PMR5 Initialized — — — — — —
PWCR2 Initialized — — — — — —
PWDRU2 Initialized — — — — — —
10-bit
PWM
PWDRL2 Initialized — — — — — —
PWCR1 Initialized — — — — — —
PWDRU1 Initialized — — — — — —
PWDRL1 Initialized — — — — — —
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 430 of 520
REJ09B0409-0100
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
PDR1 Initialized — — — — — — I/O port
PDR3 Initialized — — — — — —
PDR4 Initialized — — — — — —
PDR5 Initialized — — — — — —
PDR6 Initialized — — — — — —
PDR7 Initialized — — — — — —
PDR8 Initialized — — — — — —
PDR9 Initialized — — — — — —
PDRA Initialized — — — — — —
PDRB Initialized — — — — — —
PUCR1 Initialized — — — — — —
PUCR3 Initialized — — — — — —
PUCR5 Initialized — — — — — —
PUCR6 Initialized — — — — — —
PCR1 Initialized — — — — — —
PCR3 Initialized — — — — — —
PCR4 Initialized — — — — — —
PCR5 Initialized — — — — — —
PCR6 Initialized — — — — — —
PCR7 Initialized — — — — — —
PCR8 Initialized — — — — — —
PMR9 Initialized — — — — — —
PCRA Initialized — — — — — —
PMRB Initialized — — — — — —
SYSCR1 Initialized — — — — — — SYSTEM
SYSCR2 Initialized — — — — — —
IEGR Initialized — — — — — — Interrupts
IENR1 Initialized — — — — — —
IENR2 Initialized — — — — — —
OSCCR Initialized — — — — — — CPG
IRR1 Initialized — — — — — — Interrupts
IRR2 Initialized — — — — — —
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 431 of 520
REJ09B0409-0100
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Standby
Module
TMW Initialized
— — — — — — WDT*2
IWPR Initialized — — — — — Interrupts
CKSTPR1 Initialized — — — — — — SYSTEM
CKSTPR2 Initialized — — — —
Notes: is not initialized
1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
Section 16 List of Registers
Rev. 1.00 Dec. 19, 2007 Page 432 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 433 of 520
REJ09B0409-0100
Section 17 Electrical Characteristics
17.1 Absolute Maximum Ratings (Flash Memory Version and Mask ROM
Version)
Table 17.1 lists the absolute maximum ratings.
Table 17.1 Absolute Maximum Ratings
Item Symbol Value Unit Note
Power supply voltage VCC –0.3 to +7.0 V *1
CVCC –0.3 to +4.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Input voltage Other than port B Vin –0.3 to VCC +0.3 V
Port B AVin –0.3 to AVCC +0.3 V
Port 9 pin voltage VP9 –0.3 to VCC +0.3 V
Operating temperature Topr –20 to +75*2
(regular specifications)
°C
–40 to +85*2
(wide-range temperature
specifications)
Storage temperature Tstg –55 to +125 °C
Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
2. The operating temperature ranges from –20°C to +75°C when programming or erasing
the flash memory.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 434 of 520
REJ09B0409-0100
17.2 Electrical Characteristics (Flash Memory Version and Mask ROM
Version)
17.2.1 Power Supply Voltage and Operating Ranges
(1) Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator
Selected)
5.5
V
CC
(V)
f
W
(kHz)
• All operating modes
32.768
2.7
2.0
20.0
2.7 5.5
V
CC
(V)
fosc (MHz)
• Active (high-speed) mode
• Sleep (high-speed) mode
(2) Power Supply Voltage and Oscillation Frequency Range (On-Chip Os cillator Selected)
5.5
V
CC
(V)
f
W
(kHz)
• All operating modes
32.768
2.7
0.7
2.0
2.7 5.5
V
CC
(V)
fosc (MHz)
• Active (high-speed) mode
• Sleep (high-speed) mode
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 435 of 520
REJ09B0409-0100
(3) Power Supply Voltage and Operating Frequency Range (Sys tem Clock Oscillator
Selected)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
16.384
8.192
4.096
2.7 5.5
V
CC
(V)
φ
SUB
(kHz)
10.0
1.0
2.7 5.5
V
CC
(V)
φ (MHz)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
1250
15.625
2.7 5.5
V
CC
(V)
φ (kHz)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 436 of 520
REJ09B0409-0100
(4) Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
16.384
8.192
4.096
2.7 5.5
V
CC
(V)
φ
SUB
(kHz)
1.0
0.35
2.7 5.5
V
CC
(V)
φ (MHz)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
125
6.25
2.7 5.5
V
CC
(V)
φ (kHz)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 437 of 520
REJ09B0409-0100
(5) Analog Power Supply Voltage and A/D Converter Operating Range (System Clock
Oscillator Selected)
10.0
1.0
2.7 5.5
AV
CC
(V)
φ (MHz)
• Active (high-speed) mode
• Sleep (high-speed) mode
1000
500
2.7 5.5
AV
CC
(V)
φ (kHz)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
(6) Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip
Oscillator Selected)
1.0
0.35
2.7 5.5
AV
CC
(V)
φ (MHz)
• Active (high-speed) mode
• Sleep (high-speed) mode
125
6.25
2.7 5.5
AV
CC
(V)
φ (kHz)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 438 of 520
REJ09B0409-0100
17.2.2 DC Characteristics
Table 17.2 lists the DC characteristics.
Table 17.2 DC Charac teristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes
VIH V
CC × 0.8 — VCC + 0.3 V VCC = 4.0 V to 5.5 V Input high
voltage
RES,
WKP0 to WKP7,
IRQ0,
IRQ3, IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
VCC × 0.9 — VCC + 0.3 Other than above
RXD32, UD VCC × 0.7 — VCC + 0.3 V VCC = 4.0 V to 5.5 V
V
CC × 0.8 — VCC + 0.3 Other than above
OSC1 V
CC × 0.8 — VCC + 0.3 V VCC = 4.0 V to 5.5 V
V
CC × 0.9 — VCC + 0.3 Other than above
V
CC × 0.7 — VCC + 0.3 V VCC = 4.0 V to 5.5 V
P13, P14, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
VCC × 0.8 — VCC + 0.3 Other than above
PB0 to PB7 V
CC × 0.7 — AVCC + 0.3 V VCC = 4.0 V to 5.5 V
V
CC × 0.8 — AVCC + 0.3 Other than above
IRQAEC, P95
*5 V
CC × 0.8 — VCC + 0.3 V VCC = 4.0 V to 5.5 V
V
CC × 0.9 — VCC + 0.3 Other than above
IRQ1 V
CC × 0.8 — AVCC + 0.3 V VCC = 4.0 V to 5.5 V
V
CC × 0.9 — AVCC + 0.3 Other than above
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 439 of 520
REJ09B0409-0100
Values
Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes
– 0.3 — VCC × 0.2 V VCC = 4.0 V to 5.5 V Input low
voltage
VIL RES,
WKP0 to WKP7,
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC, P95
*5,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK32
– 0.3 — VCC × 0.1 Other than above
RXD32, UD – 0.3 — VCC × 0.3 V VCC = 4.0 V to 5.5 V
– 0.3 — VCC × 0.2 Other than above
OSC1 – 0.3 — VCC × 0.2 V VCC = 4.0 V to 5.5 V
– 0.3 — VCC × 0.1 Other than above
– 0.3 — VCC × 0.3 V VCC = 4.0 V to 5.5 V
P13, P14, P17,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3,
PB0 to PB7
– 0.3 — VCC × 0.2 Other than above
VOH V
CC – 1.0 — — V VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
Output
high
voltage
V
CC – 0.5 — — VCC = 4.0 V to 5.5 V
–IOH = 0.5 mA
P13, P14, P17,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
VCC – 0.3 — — –IOH = 0.1 mA
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 440 of 520
REJ09B0409-0100
Values
Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes
Output low
voltage
VOL — — 0.6 V VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
P13, P14, P17,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
PA0 to PA3
— — 0.5 IOL = 0.4 mA
P30 to P37 — — 1.0 VCC = 4.0 V to 5.5 V
IOL = 10 mA
— — 0.6 VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
— — 0.5 IOL = 0.4 mA
P90 to P95 — — 1.5 VCC = 4.0 V to 5.5 V
IOL = 15 mA
— — 1.0 VCC = 4.0 V to 5.5 V
IOL = 10 mA
— — 0.8 VCC = 4.0 V to 5.5 V
IOL = 8 mA
— — 1.0 IOL = 5 mA
— — 0.6 IOL = 1.6 mA
— — 0.5 IOL = 0.4 mA
| IIL | RES, P43,
P13, P14, P17,
OSC1, X1,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
IRQAEC,
PA0 to PA3,
P90 to P95
— — 1.0 µA VIN = 0.5 V to VCC –
0.5 V
Input/
output
leakage
current
PB0 to PB7 — — 1.0 VIN = 0.5 V to AVCC
– 0.5 V
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 441 of 520
REJ09B0409-0100
Values
Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes
20 — 200 µA VCC = 5.0 V,
VIN = 0.0 V
Pull-up
MOS
current
–Ip P13, P14, P17,
P30 to P37,
P50 to P57,
P60 to P67 — 40 — µA VCC = 2.7 V,
VIN = 0.0 V
Reference
value
Input
capaci-
tance
Cin All input pins
except power
supply pin
— — 15.0 pF f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
Active
mode
supply
current
IOPE1 V
CC — 0.6 — mA Active (high-speed)
mode
VCC = 2.7 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 1.0 — *
2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.8 — Active (high-speed)
mode
VCC = 5 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 1.5 — *
2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 1.6 — Active (high-speed)
mode
VCC = 5 V,
fOSC = 4 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 2.0 — *
2 *3 *4
— 3.3 7.0 *1 *3 *4
— 4.0 7.0
Active (high-speed)
mode
VCC = 5 V,
fOSC = 10 MHz
*2 *3 *4
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 442 of 520
REJ09B0409-0100
Values
Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes
Active
mode
supply
current
IOPE2 V
CC — 0.2 — mA Active (medium-
speed) mode
VCC = 2.7 V,
fOSC = 2 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.5 — *
2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.4 — Active (medium-
speed) mode
VCC = 5 V,
fOSC = 2 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.8 — *2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.6 — Active (medium-
speed) mode
VCC = 5 V,
fOSC = 4 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.9 — *
2 *3 *4
— 0.9 3.0 *1 *3 *4
— 1.2 3.0
Active (medium-
speed) mode
VCC = 5 V,
fOSC = 10 MHz,
φOSC/128
*2 *3 *4
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 443 of 520
REJ09B0409-0100
Values
Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes
Sleep
mode
supply
current
ISLEEP V
CC — 0.3 — mA VCC = 2.7 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.8 — *
2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.5 — VCC = 5 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.9 — *
2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 0.9 — VCC = 5 V,
fOSC = 4 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
— 1.3 — *
2 *3 *4
— 1.5 5.0 *1 *3 *4
— 2.2 5.0
VCC = 5 V,
fOSC = 10 MHz *2 *3 *4
ISUB V
CC — 11.3 — µA *1 *3 *4
Reference
value
Subactive
mode
supply
current — 12.7 —
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/8) *2 *3 *4
Reference
value
— 16.3 50 *1 *3 *4
— 30 50
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/2)
*2 *3 *4
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 444 of 520
REJ09B0409-0100
Values
Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes
Subsleep
mode
supply
current
ISUBSP V
CC — 4.0 16 µA VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/2)
*3 *4
IWATCH V
CC — 1.4 — µA *1 *3 *4
Reference
value
Watch
mode
supply
current — 1.8 —
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator used,
LCD not used *2 *3 *4
Reference
value
— 1.8 6.0 VCC = 2.7 V,
32-kHz crystal
resonator used,
LCD not used
*3 *4
ISTBY V
CC — 0.3 — µA VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
*1 *3 *4
Reference
value
Standby
mode
supply
current
— 0.5 — VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
*2 *3 *4
Reference
value
— 0.05 — VCC = 2.7 V,
Ta = 25°C,
SUBSTP (subclock
oscillator control
register) setting = 1
*2 *4
Reference
value
— 0.6 — VCC = 5.0 V,
Ta = 25°C,
32-kHz crystal
resonator not used
*2 *3 *4
Reference
value
— 0.16 — VCC = 5.0 V,
Ta = 25°C,
SUBSTP (subclock
oscillator control
register) setting = 1
*2 *4
Reference
value
— 1.0 5.0 32-kHz crystal
resonator not used
*3 *4
RAM data
retaining
voltage
VRAM V
CC 2.0 — — V *6
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 445 of 520
REJ09B0409-0100
Values
Item Symbol
Applicable
Pins Min Typ Max Unit
Test
Condition Notes
Allowable output low
current (per pin)
IOL Output pins
except ports 3
and 9
— — 2.0 mA VCC = 4.0 V to
5.5 V
Port 3 — — 10.0 VCC = 4.0 V to
5.5 V
Output pins
except port 9
— — 0.5
Port 9 — — 15.0 VCC = 4.0 V to
5.5 V
— — 5.0 Other than
above
Allowable output low
current (total)
∑IOL Output pins
except ports 3
and 9
— — 40.0 mA VCC = 4.0 V to
5.5 V
Port 3 — — 80.0 VCC = 4.0 V to
5.5 V
Output pins
except port 9
— — 20.0
Port 9 — — 80.0
–IOH All output pins — — 2.0 mA VCC = 4.0 V to
5.5 V
Allowable output high
current (per pin)
— — 0.2 Other than
above
∑–IOH All output pins — — 15.0 mA VCC = 4.0 V to
5.5 V
Allowable output high
current (total)
— — 10.0 Other than
above
VCC start voltage VCCSTART V
CC 0 — 0.1 V *2
VCC rising gradient SVCC V
CC 0.05 — — V/ms *2
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 446 of 520
REJ09B0409-0100
Notes: Connect the TEST pin to VSS.
1. Applies to the mask-ROM version.
2. Applies to the flash memory version.
3. Pin states when supply current is measured.
Mode
RES Pin
Internal State
Other Pins LCD Power
Supply
Oscillator Pins
Active (high-speed)
mode (IOPE1)
Active (medium-
speed) mode (IOPE2)
VCC Only CPU operates VCC Stops
Sleep mode VCC Only all on-chip timers
operate
VCC Stops
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Subactive mode VCC Only CPU operates VCC Stops
Subsleep mode VCC Only all on-chip timers
operate
CPU stops
VCC Stops
Watch mode VCC Only clock time base
operates
CPU stops
VCC Stops
System clock:
crystal resonator
Subclock:
crystal resonator
Standby mode VCC CPU and timers
both stop
VCC Stops System clock:
crystal resonator
Subclock:
Pin X1 = GND
4. Except current which flows to the pull-up MOS or output buffer.
5. Used when user mode or boot mode is determined after canceling a reset in the flash
memory version.
6. Voltage maintained in standby mode.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 447 of 520
REJ09B0409-0100
17.2.3 AC Characteristics
Table 17.3 lists the control signal timing and table 17.4 lists the serial interface timing.
Table 17.3 Control Signal Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item Symbol
Applicable
Pins Min Typ Max Unit Test Condition Reference
Figure
fOSC OSC1, OSC2 2.0 — 20.0 MHz System clock
oscillation
frequency 0.7 — 2.0 On-chip oscillator
selected
*2
OSC clock (φOSC)
cycle time
tOSC OSC1, OSC2 50.0 — 500 ns Figure 17.1
500 — 1429 On-chip oscillator
selected
tcyc 2 — 128 tOSC System clock (φ)
cycle time — — 182 µs
Subclock oscillation
frequency
fW X
1, X2 — 32.768 — kHz
Watch clock (φW)
cycle time
tW X
1, X2 — 30.5 — µs Figure 17.1
Subclock (φSUB)
cycle time
tsubcyc 2 — 8 tW *1
Instruction cycle
time
2 — — tcyc
tsubcyc
Oscillation
stabilization time
trc OSC1,
OSC2
— — 20 ms
t
rc X
1, X2 — — 2.0 s
External clock high
width
tCPH OSC1 20 — — ns Figure 17.1
External clock low
width
tCPL OSC1 20 — — ns Figure 17.1
External clock rise
time
tCPr OSC1 — — 5 ns Figure 17.1
External clock fall
time
tCPf OSC1 — — 5 ns Figure 17.1
RES pin low
width
tREL RES 10 — — tcyc Figure 17.2
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 448 of 520
REJ09B0409-0100
Values
Item Symbol
Applicable
Pins Min Typ Max Unit Test Condition Reference
Figure
Input pin high
width
tIH IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
2 — — tcyc
tsubcyc
Figure 17.3
AEVL, AEVH 0.5 — — tOSC
Input pin low
width
tIL IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
2 — — tcyc
tsubcyc
Figure 17.3
AEVL, AEVH 0.5 — — tOSC
UD pin minimum
transition width
tUDH
tUDL
UD 4 — — tcyc
tsubcyc
Figure 17.6
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. These characteristics are given as ranges between minimum and maximum values in
order to account for factors such as temperature, power supply voltage, and variation
among production lots. When designing systems, make sure to give due consideration
to the SPEC range. Please contact a Renesas sales or support representative for
actual performance data on the product.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 449 of 520
REJ09B0409-0100
Table 17.4 Serial Interface (SCI3) Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item Symbol
Min Typ Max Unit Test
Condition Reference
Figure
Asynchronous tscyc 4 — — Figure 17.4 Input clock
cycle Clocked synchronous 6 — —
tcyc or tsubcyc
Input clock pulse width tSCKW 0.4 — 0.6 tscyc Figure 17.4
Transmit data delay time
(clocked synchronous)
tTXD — — 1 tcyc or tsubcyc Figure 17.5
Receive data setup time
(clocked synchronous)
tRXS 150.0 — — ns Figure 17.5
Receive data hold time
(clocked synchronous)
tRXH 150.0 — — ns Figure 17.5
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 450 of 520
REJ09B0409-0100
17.2.4 A/D Converter Characteristics
Table 17.5 shows the A/D converter characteristics.
Table 17.5 A/D Converter Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item Symbol
Applicable
Pins Min Typ Max Unit Test
Condition Reference
Figure
Analog power supply
voltage
AVCC AVCC 2.7 — 5.5 V
*1
Analog input voltage AVIN AN0 to
AN7
– 0.3 — AVCC + 0.3 V
AIOPE AVCC — — 1.5 mA AVCC = 5.0 V Analog power supply
current AISTOP1 AVCC — 600 — µA
*
2
Reference
value
AISTOP2 AVCC — — 5.0 µA
*
3
Analog input
capacitance
CAIN AN0 to
AN7
— — 15.0 pF
Allowable signal
source impedance
RAIN — — 10.0 kΩ
Resolution (data
length)
— — 10 bit
Nonlinearity error — — ±3.5 LSB AVCC = 4.0 V
to 5.5 V
— — ±7.5 AVCC = 2.7 V
to 5.5 V
Quantization error — — ±0.5 LSB
Absolute accuracy — ±2.0 ±4.0 LSB AVCC = 4.0 V
to 5.5 V
— ±2.0 ±8.0 AVCC = 2.7 V
to 5.5 V
Conversion time 6.2 — 124 µs
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 451 of 520
REJ09B0409-0100
17.2.5 LCD Characteristics
Table 17.6 shows the LCD characteristics.
Table 17.6 LCD Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item Symbol
Applicable
Pins Min Typ Max Unit Test Condition Reference
Figure
Segment driver
step-down voltage
VDS SEG1 to
SEG32
— — 0.6 V ID = 2 µA
V1 = 2.7 V to 5.5 V
*1
Common driver
step-down voltage
VDC COM1 to
COM4
— — 0.3 V ID = 2 µA
V1 = 2.7 V to 5.5 V
*1
LCD power supply
split-resistance
RLCD 1.5 3.0 7.0 MΩ Between V1 and
VSS
Liquid crystal
display voltage VLCD V
1 2.7 — 5.5 V *
2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment pin
or common pin.
2. When the liquid crystal display voltage is supplied from an external power supply,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 452 of 520
REJ09B0409-0100
17.2.6 Flash Memory Characteristi cs
Table 17.7 Flash Mem or y Ch aracteristics
Condition: AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 5.5 V (range of
operating voltage when reading), VCC = 3.0 V to 5.5 V (range of operating voltage
when programming/erasing), Ta = –20°C to +75°C (range of operating temperature
when programming/erasing: product with regular specifications, product with wide-
range temperature specifications)
Values
Item Symbol
Min Typ Max
Unit Test
Conditions
Programming time*1*2*4 t
P — 7 200 ms/128 bytes
Erase time*1*3*5 t
E — 100 1200 ms/block
Reprogramming count NWEC 1000*8 10000*9 — times
Data retain period tDRP 10*10 — — year
Programming Wait time after
SWE-bit setting*1
x 1 — — µs
Wait time after
PSU-bit setting*1
y 50 — — µs
z1 28 30 32 µs 1 ≤ n ≤ 6
z2 198 200 202 µs 7 ≤ n ≤ 1000
Wait time after
P-bit setting*1*4
z3 8 10 12 µs Additional
programming
Wait time after
P-bit clear*1
α 5 — — µs
Wait time after
PSU-bit clear*1
β 5 — — µs
Wait time after
PV-bit setting*1
γ 4 — — µs
Wait time after
dummy write*1
ε 2 — — µs
Wait time after
PV-bit clear*1
η 2 — — µs
Wait time after
SWE-bit clear*1
θ 100 — — µs
Maximum
programming
count*1*4*5
N — — 1000 times
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 453 of 520
REJ09B0409-0100
Values
Item Symbol Min Typ Max Unit
Test
Conditions
Wait time after
SWE-bit setting*1
x 1 — — µs
Wait time after
ESU-bit setting*1
y 100 — — µs
Wait time after
E-bit setting*1*6
z 10 — 100 ms
Wait time after
E-bit clear*1
α 10 — — µs
Wait time after
ESU-bit clear*1
β 10 — — µs
Wait time after
EV-bit setting*1
γ 20 — — µs
Wait time after
dummy write*1
ε 2 — — µs
Wait time after
EV-bit clear*1
η 4 — — µs
Wait time after
SWE-bit clear*1
θ 100 — — µs
Erase
Maximum erase
count*1*6*7
N — — 120 times
Notes: 1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1
is set. It does not include the programming verification time.)
3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximum programming time (tP (max))
tP (max) = Wait time after P-bit setting (z) × maximum number of writes (N)
5. The maximum number of writes (N) should be set according to the actual set value of
z1, z2, and z3 to allow programming within the maximum programming time (tP (max)).
The wait time after P-bit setting (z1 and z2) should be alternated according to the
number of writes (n) as follows:
1 ≤ n ≤ 6 z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Maximum erase time (tE (max))
tE (max) = Wait time after E-bit setting (z) × maximum erase count (N)
7. The maximum number of erases (N) should be set according to the actual set value of z
to allow erasing within the maximum erase time (tE (max)).
8. This minimum value guarantees all characteristics after reprogramming (the guaranteed
range is from 1 to the minimum value).
9. Reference value when the temperature is 25°C (normally reprogramming will be
performed by this count).
10. This is a data retain characteristic when reprogramming is performed within the
specification range including this minimum value.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 454 of 520
REJ09B0409-0100
17.2.7 Power Supply Voltage Detection Circuit Characteristics
Table 17.8 Power Supply Voltage Detection Circuit Characteristics (1)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item Symbol Min Typ Max Unit Test Conditions
LVDR operation drop
voltage*
VLVDRmin 1.0 — — V
LVD stabilization time TLVDON 150 — — µs
Standby mode
supply current
ISTBY — — 100 µA LVDE = 1
VCC = 5.0 V
32 oscillator not
used
Note: * In some cases no reset may occur if the power supply voltage, VCC, drops below
VLVDRmin = 1.0 V and then rises, so thorough evaluation is called for.
Table 17.9 Power Supply Voltage Detection Circuit Characteristics (2)
Using on-chip reference voltage and ladder resistor (VREFSEL = VINTDSEL = VINTUSEL = 0)
Rated Values
Item Symbol Min Typ Max Unit Test Conditions
Power supply drop
detection voltage
Vint(D)*3 3.3 3.7 4.2 V LVDSEL = 0
Power supply rise
detection voltage
Vint(U)*3 3.6 4.0 4.5 V LVDSEL = 0
Reset detection voltage
1*1
Vreset1*3 2.0 2.3 2.7 V LVDSEL = 0
Reset detection voltage
2*2
Vreset2*3 2.7 3.3 3.9 V LVDSEL = 1
Notes: 1. The above function should be used in conjunction with the voltage drop/rise detection
function.
2. Low-voltage detection reset should be selected for low-voltage detection reset only.
3. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.
Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the
minimum values.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 455 of 520
REJ09B0409-0100
Table 17.10 Power Supply Voltage Detection Circuit Characteristics (3)
Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL
and VINTUSEL = 1)
Rated Values
Item Symbol Min Typ Max Unit Test Condition
extD/extU interrupt
detection level
Vexd 0.80 1.20 1.60 V
–0.3 — VCC + 0.3 or AVCC
+ 0.3, whichever is
lower
V VCC = 2.7 to 3.3 V extD/extU pin input
voltage*2
VextD*1
VextU*1
–0.3 — 3.6 or AVCC + 0.3,
whichever is lower
V VCC = 3.3 to 5.5 V
Notes: 1. The VextD voltage must always be greater than the VextU voltage.
2. The maximum input voltage of the extD and extU pins is 3.6 V.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 456 of 520
REJ09B0409-0100
Table 17.11 Power Supply Voltage Detection Circuit Characteristics (4)
Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL =
0)
Rated Values
Item Symbol Min Typ Max Unit
Test
Condition
Power supply drop
detection voltage
Vint(D)*1 3.08 * (Vref1 – 0.1) 3.08 * Vref1 3.08 * (Vref1 + 0.1) V LVDSEL = 0
Vref input voltage
(Vint(D))
Vref1*2 0.98 — 1.68 V Vint(D)
Power supply rise
detection voltage
Vint(U)*1 3.33 * (Vref2 – 0.1) 3.33 * Vref2 3.33 * (Vref2 + 0.1) V LVDSEL = 0
Vref input voltage
(Vint(U))
Vref2*2 0.91 — 1.55 V Vint(U)
Reset detection
voltage 1
Vreset1*1 1.91 * (Vref3 – 0.1) 1.91 * Vref3 1.91 * (Vref3 + 0.1) V LVDSEL = 0
Vref input voltage
(Vreset1)
Vref3*2 0.89 — 2.77 V Vreset1
Reset detection
voltage 2
Vreset2*1 2.76 * (Vref4 – 0.1) 2.76 * Vref4 2.76 * (Vref4 + 0.1) V LVDSEL = 1
Vref input voltage
(Vreset2)
Vref4*2 1.08 — 1.89 V Vreset2
Notes: 1. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.
Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the
minimum values.
2. The Vref input voltage is calculated using the following formula.
2.7 V (= VCC min) < Vint(D), Vint(U), Vreset2 < 5.5 V (= VCC max)
1.5 V (= RAM retention voltage) < Vreset1 < 5.5 V (= VCC max)
Vref1: 2.7 < 3.08 * (Vref1 – 0.1), 3.08 * (Vref1 + 0.1) < 5.5 → 0.98 < Vref1 < 1.68
Vref2: 2.7 < 3.33 * (Vref2 – 0.1), 3.33 * (Vref2 + 0.1) < 5.5 → 0.91 < Vref2 < 1.55
Vref3: 1.5 < 1.91 * (Vref3 – 0.1), 1.91 * (Vref3 + 0.1) < 5.5 → 0.89 < Vref3 < 2.77
Vref4: 2.7 < 2.76 * (Vref4 – 0.1), 2.76 * (Vref4 + 0.1) < 5.5 → 1.08 < Vref4 < 1.89
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 457 of 520
REJ09B0409-0100
Table 17.12 Power Supply Voltage Detection Circuit Characteristics (5)
Using external reference voltage and detect voltage external input (VREFSEL = VINTDSEL =
VINTUSEL = 1)
Rated Values
Item Symbol Min Typ Max Unit Test Condition
Comparator detection
accuracy
Vcdl 0.1 — — V | VextU – Vref |
| VextD – Vref |
–0.3 — VCC + 0.3 or
AVCC + 0.3,
whichever is
lower
V VCC = 2.7 to 3.3 V extD/extU pin input
voltage
VextD*
VextU*
–0.3 — 3.6 or AVCC
+ 0.3, whichever
is lower
V VCC = 3.3 to 5.5 V
Vref pin input voltage Vref5 0.8 — 2.8 V VCC = 2.7 to 5.5 V
Note: * The VextD voltage must always be greater than the VextU voltage.
17.2.8 Power-On Reset Circuit Characteristics
Table 17.13 Power-On Reset Circuit Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item Symbol Min Typ Max Unit Test Condition
RES pin pull-up
resistance
RRES 65 100 — kΩ
Power-on reset start
voltage
Vpor — — 100 mV
Note: Make sure to drop the power supply voltage, VCC, to below Vpor = 100 mV and then raise it
after the RES pin load had thoroughly dissipated. To drain the load of the RES pin,
attaching a diode to the VCC side is recommended. The power-on reset function may not
work properly if the power supply voltage, VCC, is raised from a level exceeding 100 mV.
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 458 of 520
REJ09B0409-0100
17.2.9 Watchdog Timer Characteristics
Table 17.14 Watchdog Timer Characteristics
AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item Symbol
Applicable
Pins Min Typ Max Unit Note
Test
Condition
On-chip oscillator
overflow time
tOVF 0.2 0.4 — s * VCC = 5 V
Note: * When the on-chip oscillator is selected, the timer counts from 0 to 255, indicating the
time remaining until an internal reset is generated.
17.3 Operation Timing
Figures 17.1 to 17.6 show timing diagrams.
t , tw
OSC
VIH
VIL
tCPH tCPL
tCPr
OSC1
x1
tCPf
Figure 17.1 Clock Input Timing
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 459 of 520
REJ09B0409-0100
RES V
IL
t
REL
Figure 17.2 RES Lo w Width
VIH
VIL
tIL
IRQ0, IRQ1, IRQ3, IRQ4,
TMIC, TMIF, TMIG,
ADTRG, WKP0 to WKP7,
IRQAEC, AEVL, AEVH
tIH
Figure 17.3 Input Timing
tscyc
tSCKW
32
SCK
Figure 17.4 SCK3 Input Clock Timing
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 460 of 520
REJ09B0409-0100
32
t
scyc
t
TXD
t
RXS
t
RXH
V
OH
*
V
IH
or V
OH
*
V
IL
or V
OL
*
V
OL
*
OH
OL
SCK
TXD
32
(transmit data)
RXD
32
(receive data)
Note: * Output timing reference levels
Output high
Output low
Load conditions are shown in figure 17.7.
V = 1/2Vcc + 0.2 V
V = 0.8 V
Figure 17.5 SCI3 Synchronous Mode Input/Output Timing
UD V
IL
V
IH
t
UDL
t
UDH
Figure 17.6 UD Pin Minimum Transition Width Timing
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 461 of 520
REJ09B0409-0100
17.4 Output Load Circuit
V
CC
2.4 kΩ
12 kΩ30 pF
Output pin
Figure 17.7 Output Load Condition
17.5 Resonator Equivalent Circuit
C
S
C
O
Frequency
(MHz)
R
S
(max)
C
O
(max)
4
100 Ω
16 pF
4.193
100 Ω
16 pF
10
30 Ω
16 pF
Crystal Resonator Parameters
R
S
OSC
2
OSC
1
L
S
Frequency
(MHz)
R
S
(max)
C
O
(max)
2
18.3 Ω
36.94 pF
4
6.8 Ω
36.72 pF
10
4.6 Ω
32.31 pF
Ceramic Resonator Parameters
Figure 17.8 Resonator Equivalent Circuit (1)
Section 17 Electrical Characteristics
Rev. 1.00 Dec. 19, 2007 Page 462 of 520
REJ09B0409-0100
OSC1
LSCS
CO
RS
OSC2
Crystal Resonator Parameters
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
RS (max)
CO (max)
Manufacturer
Nihon Dempa Kogyo Co., Ltd.
Ceramic Resonator Parameters (1)
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
RS (max)
CO (max)
Manufacturer
Murata Manufacturing Co., Ltd.
Manufacturer
Murata Manufacturing Co., Ltd.
4
100 Ω
16 pF
2
18.3 Ω
36.94 pF
Ceramic Resonator Parameters (2)
(Manufacturer's Publicly Released Values)
Frequency
(MHz)
RS (max)
CO (max)
10
4.6 Ω
32.31 pF
Figure 17.9 Resonator Equivalent Circuit (2)
17.6 Usage Note
The flash memory and mask ROM versions satisfy the electrical characteristics shown in this
manual, but actual electrical characteristic values, operating margins, noise margins, and other
properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns,
and so on.
When system evaluation testing is carried out using the flash memory version, the same evaluation
testing should also be conducted for the mask ROM version when changing over to that version.
Appendix
Rev. 1.00 Dec. 19, 2007 Page 463 of 520
REJ09B0409-0100
Appendix
A. Instruction Set
A.1 Instruction List
Condition Code
Symbol Description
Rd General destination register
Rs General source register
Rn General register
ERd General destination register (address register or 32-bit register)
ERs General source register (address register or 32-bit register)
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
PC Program counter
SP Stack pointer
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
disp Displacement
→ Transfer from the operan d on the left to the operand on the right, or transition from
the state on the left to the state on the right
+ Addition of the operands on b oth sides
– Subtraction of the operand on the right from the operand on the left
× Multiplication of the operands on both sides
÷ Division of the operand on the left by the operand on the right
∧ Logical AND of the operands on both sides
∨ Logical OR of the op erands on both sides
⊕ Logical exclusive OR of the operands on both sides
Appendix
Rev. 1.00 Dec. 19, 2007 Page 464 of 520
REJ09B0409-0100
Symbol Description
¬ NOT (logical complement)
( ), < > Contents of operand
Note: General regist ers include 8-bit registers (R0H to R7H and R0L to R7 L) and 16-bit registers
(R0 to R7 and E0 to E7).
Condition Code Notation (cont)
Symbol Description
↔
Changed according to ex ecution result
* Undetermined (no guaranteed value)
0 Cleared to 0
1 Set to 1
— Not affected by execution of the instruction
∆ Varies depending on conditions, described in notes
Appendix
Rev. 1.00 Dec. 19, 2007 Page 465 of 520
REJ09B0409-0100
Table A.1 Instruction Set
1. Data Transfer Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @ERd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @–ERd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MOV.W @(d:16, ERs), Rd
MOV.W @(d:24, ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16, ERd)
MOV.W Rs, @(d:24, ERd)
Operation
#xx:8 → Rd8
Rs8 → Rd8
@ERs → Rd8
@(d:16, ERs) → Rd8
@(d:24, ERs) → Rd8
@ERs → Rd8
ERs32+1 → ERs32
@aa:8 → Rd8
@aa:16 → Rd8
@aa:24 → Rd8
Rs8 → @ERd
Rs8 → @(d:16, ERd)
Rs8 → @(d:24, ERd)
ERd32–1 → ERd32
Rs8 → @ERd
Rs8 → @aa:8
Rs8 → @aa:16
Rs8 → @aa:24
#xx:16 → Rd16
Rs16 → Rd16
@ERs → Rd16
@(d:16, ERs) → Rd16
@(d:24, ERs) → Rd16
@ERs → Rd16
ERs32+2 → @ERd32
@aa:16 → Rd16
@aa:24 → Rd16
Rs16 → @ERd
Rs16 → @(d:16, ERd)
Rs16 → @(d:24, ERd)
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
2
4
2
2
2
2
2
2
4
8
4
8
4
8
4
8
2
2
2
2
4
6
2
4
6
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
4
6
10
6
4
6
8
4
6
10
6
4
6
8
4
2
4
6
10
6
6
8
4
6
10
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MOV
Appendix
Rev. 1.00 Dec. 19, 2007 Page 466 of 520
REJ09B0409-0100
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
MOV.W Rs, @–ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, ERd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16, ERs), ERd
MOV.L @(d:24, ERs), ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
MOV.L ERs, @(d:16, ERd)
MOV.L ERs, @(d:24, ERd)
MOV.L ERs, @–ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
MOVFPE @aa:16, Rd
MOVTPE Rs, @aa:16
Operation
ERd32–2 → ERd32
Rs16 → @ERd
Rs16 → @aa:16
Rs16 → @aa:24
#xx:32 → ERd32
ERs32 → ERd32
@ERs → ERd32
@(d:16, ERs) → ERd32
@(d:24, ERs) → ERd32
@ERs → ERd32
ERs32+4 → ERs32
@aa:16 → ERd32
@aa:24 → ERd32
ERs32 → @ERd
ERs32 → @(d:16, ERd)
ERs32 → @(d:24, ERd)
ERd32–4 → ERd32
ERs32 → @ERd
ERs32 → @aa:16
ERs32 → @aa:24
@SP → Rn16
SP+2 → SP
@SP → ERn32
SP+4 → SP
SP–2 → SP
Rn16 → @SP
SP–4 → SP
ERn32 → @SP
Cannot be used in
this LSI
Cannot be used in
this LSI
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W
L
W
L
B
B
6
2
4
4
6
10
6
10
2
4
4
4
6
6
8
6
8
4
4
2
4
2
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
6
8
6
2
8
10
14
10
10
12
8
10
14
10
10
12
6
10
6
10
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cannot be used in
this LSI
Cannot be used in
this LSI
MOV
POP
PUSH
MOVFPE
MOVTPE
Appendix
Rev. 1.00 Dec. 19, 2007 Page 467 of 520
REJ09B0409-0100
2. Arithmetic Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
ADDS.L #1, ERd
ADDS.L #2, ERd
ADDS.L #4, ERd
INC.B Rd
INC.W #1, Rd
INC.W #2, Rd
INC.L #1, ERd
INC.L #2, ERd
DAA Rd
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.L #1, ERd
SUBS.L #2, ERd
SUBS.L #4, ERd
DEC.B Rd
DEC.W #1, Rd
DEC.W #2, Rd
Operation
Rd8+#xx:8 → Rd8
Rd8+Rs8 → Rd8
Rd16+#xx:16 → Rd16
Rd16+Rs16 → Rd16
ERd32+#xx:32 →
ERd32
ERd32+ERs32 →
ERd32
Rd8+#xx:8 +C → Rd8
Rd8+Rs8 +C → Rd8
ERd32+1 → ERd32
ERd32+2 → ERd32
ERd32+4 → ERd32
Rd8+1 → Rd8
Rd16+1 → Rd16
Rd16+2 → Rd16
ERd32+1 → ERd32
ERd32+2 → ERd32
Rd8 decimal adjust
→ Rd8
Rd8–Rs8 → Rd8
Rd16–#xx:16 → Rd16
Rd16–Rs16 → Rd16
ERd32–#xx:32 → ERd32
ERd32–ERs32 → ERd32
Rd8–#xx:8–C → Rd8
Rd8–Rs8–C → Rd8
ERd32–1 → ERd32
ERd32–2 → ERd32
ERd32–4 → ERd32
Rd8–1 → Rd8
Rd16–1 → Rd16
Rd16–2 → Rd16
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
W
L
L
B
B
L
L
L
B
W
W
2
4
6
2
4
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(2)
(2)
—
—
—
—
—
—
—
—
*
(1)
(1)
(2)
(2)
—
—
—
—
—
—
2
2
4
2
6
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
6
2
2
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔↔↔↔↔↔
↔↔↔↔↔↔↔
—
—
—
—
—
—
↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔
(3)
(3)
—
—
—
(3)
(3)
—
—
—
↔↔↔
↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔
—
—
—
*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔↔↔↔
↔
↔
↔
↔
↔↔↔
↔↔↔
↔↔↔
ADD
ADDX
ADDS
INC
DAA
SUB
SUBX
SUBS
DEC
Appendix
Rev. 1.00 Dec. 19, 2007 Page 468 of 520
REJ09B0409-0100
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
DEC.L #1, ERd
DEC.L #2, ERd
DAS.Rd
MULXU. B Rs, Rd
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS. W Rs, ERd
DIVXU. B Rs, Rd
DIVXU. W Rs, ERd
DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
Operation
ERd32–1 → ERd32
ERd32–2 → ERd32
Rd8 decimal adjust
→ Rd8
Rd8 × Rs8 → Rd16
(unsigned multiplication)
Rd16 × Rs16 → ERd32
(unsigned multiplication)
Rd8 × Rs8 → Rd16
(signed multiplication)
Rd16 × Rs16 → ERd32
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
Rd8–#xx:8
Rd8–Rs8
Rd16–#xx:16
Rd16–Rs16
ERd32–#xx:32
ERd32–ERs32
L
L
B
B
W
B
W
B
W
B
W
B
B
W
W
L
L
2
4
6
2
2
2
2
2
4
4
2
2
4
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
2
14
22
16
24
14
22
16
24
2
2
4
2
4
2
Normal
Advanced
↔
↔
↔
—
—
*
—
—
—
—
—
—
—
—
(1)
(1)
(2)
(2)
↔
↔
↔
↔
↔
*
—
—
—
—
—
—
—
—
—
—
(7)
(7)
(7)
(7)
—
—
(6)
(6)
(8)
(8)
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
DEC
DAS
MULXU
MULXS
DIVXU
DIVXS
CMP
Appendix
Rev. 1.00 Dec. 19, 2007 Page 469 of 520
REJ09B0409-0100
Mnemonic Operation
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
0–Rd8 → Rd8
0–Rd16 → Rd16
0–ERd32 → ERd32
0 → (<bits 15 to 8>
of Rd16)
0 → (<bits 31 to 16>
of ERd32)
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
B
W
L
W
L
W
L
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
0
0
0
0
0
0
—
—
—
—
↔↔↔↔
↔↔
NEG
EXTU
EXTS
Appendix
Rev. 1.00 Dec. 19, 2007 Page 470 of 520
REJ09B0409-0100
3. Logic Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
NOT.B Rd
NOT.W Rd
NOT.L ERd
Operation
Rd8∧#xx:8 → Rd8
Rd8∧Rs8 → Rd8
Rd16∧#xx:16 → Rd16
Rd16∧Rs16 → Rd16
ERd32∧#xx:32 → ERd32
ERd32∧ERs32 → ERd32
Rd8∨#xx:8 → Rd8
Rd8∨Rs8 → Rd8
Rd16∨#xx:16 → Rd16
Rd16∨Rs16 → Rd16
ERd32∨#xx:32 → ERd32
ERd32∨ERs32 → ERd32
Rd8⊕#xx:8 → Rd8
Rd8⊕Rs8 → Rd8
Rd16⊕#xx:16 → Rd16
Rd16⊕Rs16 → Rd16
ERd32⊕#xx:32 → ERd32
ERd32⊕ERs32 → ERd32
¬ Rd8 → Rd8
¬ Rd16 → Rd16
¬ Rd32 → Rd32
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
W
L
2
4
6
2
4
6
2
4
6
2
2
4
2
2
4
2
2
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
4
2
6
4
2
2
4
2
6
4
2
2
4
2
6
4
2
2
2
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AND
OR
XOR
NOT
Appendix
Rev. 1.00 Dec. 19, 2007 Page 471 of 520
REJ09B0409-0100
4. Shift Instructions
Mnemonic
Operand Size
No. of
States*1
Condition Code
IHNZVC
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
Addressing Mode and
Instruction Length (bytes)
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Operation
MSB LSB
0
C
MSB LSB
0
C
C
MSB LSB
0C
MSB LSB
C
MSB LSB
C
MSB LSB
C
MSB LSB
C
MSB LSB
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SHAL
SHAR
SHLL
SHLR
ROTXL
ROTXR
ROTL
ROTR
Appendix
Rev. 1.00 Dec. 19, 2007 Page 472 of 520
REJ09B0409-0100
5. Bit-Manipulation Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
BLD #xx:3, Rd
Operation
(#xx:3 of Rd8) ← 1
(#xx:3 of @ERd) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
(Rn8 of @ERd) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @ERd) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
(Rn8 of @ERd) ← 0
(Rn8 of @aa:8) ← 0
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
¬ (#xx:3 of Rd8) → Z
¬ (#xx:3 of @ERd) → Z
¬ (#xx:3 of @aa:8) → Z
¬ (Rn8 of @Rd8) → Z
¬ (Rn8 of @ERd) → Z
¬ (Rn8 of @aa:8) → Z
(#xx:3 of Rd8) → C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
2
6
6
2
6
6
2
Normal
Advanced
↔↔↔↔↔↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BSET
BCLR
BNOT
BTST
BLD
Appendix
Rev. 1.00 Dec. 19, 2007 Page 473 of 520
REJ09B0409-0100
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
BIOR #xx:3, Rd
BIOR #xx:3, @ERd
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
Operation
(#xx:3 of @ERd) → C
(#xx:3 of @aa:8) → C
¬ (#xx:3 of Rd8) → C
¬ (#xx:3 of @ERd) → C
¬ (#xx:3 of @aa:8) → C
C → (#xx:3 of Rd8)
C → (#xx:3 of @ERd24)
C → (#xx:3 of @aa:8)
¬ C → (#xx:3 of Rd8)
¬ C → (#xx:3 of @ERd24)
¬ C → (#xx:3 of @aa:8)
C∧(#xx:3 of Rd8) → C
C∧(#xx:3 of @ERd24) → C
C∧(#xx:3 of @aa:8) → C
C∧ ¬ (#xx:3 of Rd8) → C
C∧ ¬ (#xx:3 of @ERd24) → C
C∧ ¬ (#xx:3 of @aa:8) → C
C∨(#xx:3 of Rd8) → C
C∨(#xx:3 of @ERd24) → C
C∨(#xx:3 of @aa:8) → C
C∨ ¬ (#xx:3 of Rd8) → C
C∨ ¬ (#xx:3 of @ERd24) → C
C∨ ¬ (#xx:3 of @aa:8) → C
C⊕(#xx:3 of Rd8) → C
C⊕(#xx:3 of @ERd24) → C
C⊕(#xx:3 of @aa:8) → C
C⊕ ¬ (#xx:3 of Rd8) → C
C⊕ ¬ (#xx:3 of @ERd24) → C
C⊕ ¬ (#xx:3 of @aa:8) → C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
2
6
6
2
8
8
2
8
8
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
Normal
Advanced
↔↔↔↔↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
BLD
BILD
BIST
BST
BAND
BIAND
BOR
BIOR
BXOR
BIXOR
Appendix
Rev. 1.00 Dec. 19, 2007 Page 474 of 520
REJ09B0409-0100
6. Branching Instructions
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Mnemonic
Operand Size
No. of
States
*1
Condition Code
IHNZVC
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
Normal
Advanced
Addressing Mode and
Instruction Length (bytes)
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
Operation
Always
Never
C∨ Z = 0
C∨ Z = 1
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
N⊕V = 0
N⊕V = 1
Z∨ (N⊕V) = 0
Z∨ (N⊕V) = 1
If condition
is true then
PC ← PC+d
else next;
Branch
Condition
Bcc
Appendix
Rev. 1.00 Dec. 19, 2007 Page 475 of 520
REJ09B0409-0100
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
Operation
PC ← ERn
PC ← aa:24
PC ← @aa:8
PC → @–SP
PC ← PC+d:8
PC → @–SP
PC ← PC+d:16
PC → @–SP
PC ← ERn
PC → @–SP
PC ← aa:24
PC → @–SP
PC ← @aa:8
PC ← @SP+
—
—
—
—
—
—
—
—
—
2
2
4
4
2
4
2
2
2
—
—
—
—
—
—
—
—
—
4
6
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
6
8
6
8
8
8
10
8
10
8
10
12
10
JMP
BSR
JSR
RTS
Appendix
Rev. 1.00 Dec. 19, 2007 Page 476 of 520
REJ09B0409-0100
7. System Control Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
RTE
SLEEP
LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
LDC @(d:16, ERs), CCR
LDC @(d:24, ERs), CCR
LDC @ERs+, CCR
LDC @aa:16, CCR
LDC @aa:24, CCR
STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16, ERd)
STC CCR, @(d:24, ERd)
STC CCR, @–ERd
STC CCR, @aa:16
STC CCR, @aa:24
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
Operation
CCR ← @SP+
PC ← @SP+
Transition to power-
down state
#xx:8 → CCR
Rs8 → CCR
@ERs → CCR
@(d:16, ERs) → CCR
@(d:24, ERs) → CCR
@ERs → CCR
ERs32+2 → ERs32
@aa:16 → CCR
@aa:24 → CCR
CCR → Rd8
CCR → @ERd
CCR → @(d:16, ERd)
CCR → @(d:24, ERd)
ERd32–2 → ERd32
CCR → @ERd
CCR → @aa:16
CCR → @aa:24
CCR∧#xx:8 → CCR
CCR∨#xx:8 → CCR
CCR⊕#xx:8 → CCR
PC ← PC+2
—
—
B
B
W
W
W
W
W
W
B
W
W
W
W
W
W
B
B
B
—
2
2
2
2
2
2
4
4
6
10
6
10
4
4
6
8
6
8
2
10
2
2
2
6
8
12
8
8
10
2
6
8
12
8
8
10
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
↔
↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
RTE
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Appendix
Rev. 1.00 Dec. 19, 2007 Page 477 of 520
REJ09B0409-0100
8. Block Transfer Instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
EEPMOV. B
EEPMOV. W
Operation
if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until R4L=0
else next
if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until R4=0
else next
—
—
4
4
—
—
8+
4n*2
Normal
Advanced
—
—
—
—
—
—
—
—
—
—8+
4n*2
EEPMOV
Notes: 1. The numb er of states in cases where the instruction code and its operands are located
in on-chip memory is shown here. For other cases, see appendix A.3, Number of
Execution States.
2. n is the valu e set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carr y; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwi se cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cl eared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Appendix
Rev. 1.00 Dec. 19, 2007 Page 478 of 520
REJ09B0409-0100
A.2 Operation Code Map
Table A.2 Operation Code Map (1)
AH AL 0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
BRA
MULXU
BSET
BRN
DIVXU
BNOT
STC
BHI
MULXU
BCLR
LDC
BLS
DIVXU
BTST
ORC
OR.B
BCC
RTS
OR
XORC
XOR.B
BCS
BSR
XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
ANDC
AND.B
BNE
RTE
AND
LDC
BEQ
TRAPA
BLD
BILD
BST
BIST
BVC
MOV
BPL
JMP
BMI
EEPMOV
ADDX
SUBX
BGT
JSR
BLE
MOV
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
Instruction code:
Table A.2
(2) Table A.2
(2) Table A.2
(2) Table A.2
(2) Table A.2
(2)
BVS BLTBGE
BSR
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2) Table A.2
(2) Table A.2
(3)
1st byte 2nd byte
AH BHAL BL
ADD
SUB
MOV
CMP
MOV.B
Appendix
Rev. 1.00 Dec. 19, 2007 Page 479 of 520
REJ09B0409-0100
Table A.2 Operation Code Map (2)
AH ALBH 0123456789ABCDEF
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
79
7A
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
BHI
CMP
CMP
LDC/STC
BCC
OR
OR
BPL BGT
Instruction code:
BVS
SLEEP
BVC BGE
Table A-2
(3)
Table A-2
(3) Table A-2
(3)
ADD
MOV
SUB
CMP
BNE
AND
AND
INC
EXTU
DEC
BEQ
INC
EXTU
DEC
BCS
XOR
XOR
SHLL
SHLR
ROTXL
ROTXR
NOT
BLS
SUB
SUB
BRN
ADD
ADD
INC
EXTS
DEC
BLT
INC
EXTS
DEC
BLE
SHAL
SHAR
ROTL
ROTR
NEG
BMI
1st byte 2nd byte
AH BHAL BL
SUB
ADDS
SHLL
SHLR
ROTXL
ROTXR
NOT
SHAL
SHAR
ROTL
ROTR
NEG
Appendix
Rev. 1.00 Dec. 19, 2007 Page 480 of 520
REJ09B0409-0100
Table A.2 Operation Code Map (3)
AH
ALBH
BLCH
CL
0123456789ABCDEF
01406
01C05
01D05
01F06
7Cr06
7Cr07
7Dr06
7Dr07
7Eaa6
7Eaa7
7Faa6
7Faa7
MULXS
BSET
BSET
BSET
BSET
DIVXS
BNOT
BNOT
BNOT
BNOT
MULXS
BCLR
BCLR
BCLR
BCLR
DIVXS
BTST
BTST
BTST
BTST
OR XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
AND
BLD
BILD
BST
BIST
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Instruction code:
*
*
*
*
*
*
*
*
1
1
1
1
2
2
2
2
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
Notes: 1.
2. r is the register designation field.
aa is the absolute address field.
1st byte 2nd byte
AH BHAL BL 3rd byte
CH DHCL DL
4th byte
LDCSTC LDC LDC LDC
STC STC STC
Appendix
Rev. 1.00 Dec. 19, 2007 Page 481 of 520
REJ09B0409-0100
A.3 Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on- chip ROM, branch add ress is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Appendix
Rev. 1.00 Dec. 19, 2007 Page 482 of 520
REJ09B0409-0100
Table A.3 Number of Cycles in Each Instruction
Execution Status Access Location
(Instruction Cycle) On-Chip Memory On-Chip Peripheral Module
Instruction fetch SI 2 —
Branch address read SJ
Stack operation SK
Byte data access SL 2 or 3*
Word data access SM —
Internal operation SN 1
Note: * Depends on which on-chip peripheral module is accessed. See section 16.1, Register
Addresses (Address Order).
Appendix
Rev. 1.00 Dec. 19, 2007 Page 483 of 520
REJ09B0409-0100
Table A.4 Number of Cycles in Each Instruction
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ADD ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
1
1
2
1
3
1
ADDS ADDS #1/2/4, ERd 1
ADDX ADDX #xx: 8, Rd
ADDX Rs, Rd
1
1
AND AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
1
1
2
1
3
2
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx: 3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
1
2
2
1
1
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
Appendix
Rev. 1.00 Dec. 19, 2007 Page 484 of 520
REJ09B0409-0100
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
Bcc
BLT d:8
BGT d:8
BLE d:8
BRA d:16(BT d:16)
BRN d:16(BF d:16)
BHI d:16
BLS d:16
BCC d:16(BHS d:16)
BCS d:16(BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BIAND BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
1
2
2
1
1
BILD BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
1
2
2
1
1
Appendix
Rev. 1.00 Dec. 19, 2007 Page 485 of 520
REJ09B0409-0100
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BIOR BIOR #xx:3, Rd
BIOR #xx:3, @ERd
BIOR #xx:3, @aa:8
1
2
2
1
1
BIST BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
1
2
2
2
2
BIXOR BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
1
2
2
1
1
BLD BLD #xx:3, Rd
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
1
2
2
1
1
BNOT BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BOR BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
1
2
2
1
1
BSET BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BSR BSR d:8
BSR d:16
2
2
1
1
2
BST BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
1
2
2
2
2
Appendix
Rev. 1.00 Dec. 19, 2007 Page 486 of 520
REJ09B0409-0100
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BTST BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
1
2
2
1
2
2
1
1
1
1
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
1
2
2
1
1
CMP CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
1
1
2
1
3
1
DAA DAA Rd 1
DAS DAS Rd 1
DEC DEC.B Rd
DEC.W #1/2, Rd
DEC.L #1/2, ERd
1
1
1
DUVXS DIVXS.B Rs, Rd
DIVXS.W Rs, ERd
2
2
12
20
DIVXU DIVXU.B Rs, Rd
DIVXU.W Rs, ERd
1
1
12
20
EEPMOV EEPMOV.B
EEPMOV.W
2
2
2n+2*1
2n+2*1
EXTS EXTS.W Rd
EXTS.L ERd
1
1
EXTU EXTU.W Rd
EXTU.L ERd
1
1
Appendix
Rev. 1.00 Dec. 19, 2007 Page 487 of 520
REJ09B0409-0100
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
INC INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
1
1
1
JMP JMP @ERn
JMP @aa:24
JMP @@aa:8
2
2
2
1
2
2
JSR JSR @ERn
JSR @aa:24
JSR @@aa:8
2
2
2
1
1
1
1
2
LDC LDC #xx:8, CCR
LDC Rs, CCR
LDC@ERs, CCR
LDC@(d:16, ERs), CCR
LDC@(d:24,ERs), CCR
LDC@ERs+, CCR
LDC@aa:16, CCR
LDC@aa:24, CCR
1
1
2
3
5
2
3
4
1
1
1
1
1
1
2
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @Erd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @-ERd
MOV.B Rs, @aa:8
1
1
1
2
4
1
1
2
3
1
2
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
Appendix
Rev. 1.00 Dec. 19, 2007 Page 488 of 520
REJ09B0409-0100
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOV MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MOV.W @(d:16,ERs), Rd
MOV.W @(d:24,ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16,ERd)
MOV.W Rs, @(d:24,ERd)
2
3
2
1
1
2
4
1
2
3
1
2
4
1
1
1
1
1
1
1
1
1
1
1
2
MOV
MOV.W Rs, @-ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, ERd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16,ERs), ERd
MOV.L @(d:24,ERs), ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs,@ERd
MOV.L ER s, @(d:16, E Rd)
MOV.L ER s, @(d:24, ERd)
MOV.L ERs, @-ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
1
2
3
3
1
2
3
5
2
3
4
2
3
5
2
3
4
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MOVFPE MOVFPE @aa:16, Rd*2 2 1
MOVTPE MOVTPE Rs,@aa:16*2 2 1
Appendix
Rev. 1.00 Dec. 19, 2007 Page 489 of 520
REJ09B0409-0100
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MULXS MULXS.B Rs, Rd
MULXS.W Rs, ERd
2
2
12
20
MULXU MULXU.B Rs, Rd
MULXU.W Rs, ERd
1
1
12
20
NEG NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP NOP 1
NOT NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
1
1
2
1
3
2
ORC ORC #xx:8, CCR 1
POP POP.W Rn
POP.L ERn
1
2
1
2
2
2
PUSH PUSH.W Rn
PUSH.L ERn
1
2
1
2
2
2
ROTL ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
1
1
1
ROTR ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
1
1
1
ROTXL ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
1
1
1
Appendix
Rev. 1.00 Dec. 19, 2007 Page 490 of 520
REJ09B0409-0100
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ROTXR ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
1
1
1
RTE RTE 2 2 2
RTS RTS 2 1 2
SHAL SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
1
1
1
SHAR SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
1
1
1
SHLL SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
1
1
1
SHLR SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
1
1
1
SLEEP SLEEP 1
STC STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16,ERd)
STC CCR, @(d:24,ERd)
STC CCR,@-ERd
STC CCR, @aa:16
STC CCR, @aa:24
1
2
3
5
2
3
4
1
1
1
1
1
1
2
SUB SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
1
2
1
3
1
SUBS SUBS #1/2/4, ERd 1
Appendix
Rev. 1.00 Dec. 19, 2007 Page 491 of 520
REJ09B0409-0100
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SUBX SUBX #xx:8, Rd
SUBX. Rs, Rd
1
1
XOR XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
1
1
2
1
3
2
XORC XORC #xx:8, CCR 1
Notes: 1. n: Specifie d value in R4L. The source and destination operands are accessed n+1
times respectively.
2. It cannot be used in this LSI.
Appendix
Rev. 1.00 Dec. 19, 2007 Page 492 of 520
REJ09B0409-0100
A.4 Combinations of Instructions and Addressing Modes
Table A.5 Combinations of Instructions and Addressing Modes
Addressing Mode
MOV
POP, PUSH
MOVFPE,
MOVTPE
ADD, CMP
SUB
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
MULXU,
MULXS,
DIVXU,
DIVXS
NEG
EXTU, EXTS
AND, OR, XOR
NOT
BCC, BSR
JMP, JSR
RTS
RTE
SLEEP
LDC
STC
ANDC, ORC,
XORC
NOP
Data
transfer
instructions
Arithmetic
operations
Logical
operations
Shift operations
Bit manipulations
Branching
instructions
System
control
instructions
Block data transfer instructions
BWL
—
—
BWL
WL
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
B
—
—
#xx
Rn
@ERn
@(d:16.ERn)
@(d:24.ERn)
@ERn+/@ERn
@aa:8
@aa:16
@aa:24
@(d:8.PC)
@(d:16.PC)
@@aa:8
—
BWL
—
—
BWL
BWL
B
L
BWL
B
BW
BWL
WL
BWL
BWL
BWL
B
—
—
—
—
—
B
B
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
Functions Instructions
Appendix
Rev. 1.00 Dec. 19, 2007 Page 493 of 520
REJ09B0409-0100
B. I/O Port Block Diagrams
B.1 Block Diagrams of Port 1
P1
n
V
CC
V
CC
PUCR1
n
PMR1
n
PDR1
n
PCR1
n
Internal data bus
SBY (low level during
reset and in standby
mode)
V
SS
IRQ
m
PDR1:
PCR1:
PMR1:
PUCR1:
n = 7 and 4
m = 4 and 3
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
Figure B.1(a) Port 1 Block Diagram (Pins P17 and P14)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 494 of 520
REJ09B0409-0100
VCC
VCC
SBY
VSS
PUCR13
PMR13
PDR13
PCR13
Timer G
module
TMIG
Internal data bus
P13
PDR1:
PCR1:
PMR1:
PUCR1:
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
Figure B.1(b) Port 1 Block Diagram (Pin P13)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 495 of 520
REJ09B0409-0100
B.2 Block Diagrams of Port 3
P3n
VCC
VCC
PUCR3n
PMR3n
PDR3n
PCR3n
AEC module
Internal data bus
SBY
VSS
AEVH(P36)
AEVL(P37)
PDR3:
PCR3:
PMR3:
PUCR3:
Port data register 3
Port control register 3
Port mode register 3
Port pull-up control register 3
n = 7 and 6
Figure B.2(a) Port 3 Block Diagram (Pins P37 and P36)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 496 of 520
REJ09B0409-0100
P3
5
V
CC
V
CC
PUCR3
5
PMR2
5
PDR3
5
PCR3
5
SBY
V
SS
Internal data bus
PDR3:
PCR3:
PUCR3:
PMR2
Port data register 3
Port control register 3
Port pull-up control register 3
Port mode register 2
Figure B.2(b) Port 3 Block Diagram (Pin P35)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 497 of 520
REJ09B0409-0100
P3nPDR3n
PUCR3n
PCR3n
SBY
VSS
PDR3: Port data register 3
PCR3: Port control register 3
n = 4 and 3
Internal data bus
VCC
VCC
Figure B.2(c) Port 3 Block Diagram (Pins P34 and P33)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 498 of 520
REJ09B0409-0100
P3n
VCC
VCC
PUCR3
n
Internal data bus
PMR3
n
PDR3
n
PCR3
n
SBY
VSS
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
n = 2 and 1
TMOFH (P3
2
)
TMOFL (P3
1
)
Figure B.2(d) Port 3 Block Diagram (Pins P32 and P31)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 499 of 520
REJ09B0409-0100
VCC
VCC
VSS
PUCR30
PDR30
PCR30
UD
SBY
Internal data bus
PDR3:
PCR3:
PMR3:
PUCR3:
Port data register 3
Port control register 3
Port mode register 3
Port pull-up control register 3
P30
Timer C
module
PMR30
Figure B.2(e) Port 3 Block Diagram (Pin P30)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 500 of 520
REJ09B0409-0100
B.3 Block Diagrams of Port 4
P4
3
PMR2
0
Internal data bus
IRQ
0
PMR2: Port mode register 2
Figure B.3(a) Port 4 Block Diagram (Pin P43)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 501 of 520
REJ09B0409-0100
P4
2
SCI3 module
Internal data bus
PDR4
2
SCINV3
PCR4
2
SBY
V
SS
PDR4: Port data register 4
PCR4: Port control register 4
TXD32
V
CC
SPC32
Figure B.3(b) Port 4 Block Diagram (Pin P42)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 502 of 520
REJ09B0409-0100
P4
1
V
CC SCI3 module
PDR4
1
PCR4
1
SBY
V
SS
PDR4: Port data register 4
PCR4: Port control register 4
RE32
RXD32
Internal data bus
SCINV2
Figure B.3(c) Port 4 Block Diagram (Pin P41)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 503 of 520
REJ09B0409-0100
P40
VCC
SCI3 module
PDR40
PCR40
SBY
VSS
PDR4: Port data register 4
PCR4: Port control register 4
SCKIE32
SCKOE32
SCKO32
Internal data bus
SCKI32
Figure B.3(d) Port 4 Block Diagram (Pin P40)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 504 of 520
REJ09B0409-0100
B.4 Block Diagram of Port 5
P5
n
V
CC
V
CC
PUCR5
n
Internal data bus
PMR5
n
PDR5
n
PCR5
n
SBY
V
SS
WKP
n
PDR5: Port data register 5
PCR5: Port control register 5
PMR5: Port mode register 5
PUCR5: Port pull-up control register 5
n = 7 to 0
Figure B.4 Port 5 Block Diagram
Appendix
Rev. 1.00 Dec. 19, 2007 Page 505 of 520
REJ09B0409-0100
B.5 Block Diagram of Port 6
P6
n
V
CC
V
CC
PUCR6
n
PDR6
n
Internal data bus
PCR6
n
SBY
V
SS
PDR6: Port data register 6
PCR6: Port control register 6
PUCR6: Port pull-up control register 6
n = 7 to 0
Figure B.5 Port 6 Block Diagram
Appendix
Rev. 1.00 Dec. 19, 2007 Page 506 of 520
REJ09B0409-0100
B.6 Block Diagram of Port 7
P7
n
V
CC
PDR7
n
Internal data bus
PCR7
n
SBY
V
SS
PDR7: Port data register 7
PCR7: Port control register 7
n = 7 to 0
Figure B.6 Port 7 Block Diagram
Appendix
Rev. 1.00 Dec. 19, 2007 Page 507 of 520
REJ09B0409-0100
B.7 Block Diagram of Port 8
P8
n
V
CC
PDR8
n
Internal data bus
PCR8
n
SBY
V
SS
PDR8:
PCR8:
n = 7 to 0
Port data register 8
Port control register 8
Figure B.7 Port 8 Block Diagram
Appendix
Rev. 1.00 Dec. 19, 2007 Page 508 of 520
REJ09B0409-0100
B.8 Block Diagrams of Port 9
P9
n
PDR9
n
PMR9
n
SBY
V
SS
PDR9:
n = 1 and 0
Port data register 9
PWM module
PWM
n+1
Internal data bus
Figure B.8(a) Port 9 Block Diagram (Pins P91 and P90)
P9
n
PDR9
n
SBY
V
SS
PDR9:
n = 5 to 2
Port data register 9
Internal data bus
Figure B.8(b) Port 9 Block Diagram (Pins P95 to P92)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 509 of 520
REJ09B0409-0100
P93
PDR93
LVD modul
e
VREFSEL
Vref
SBY
VSS
PDR9: Port data register 9
Internal data bus
Figure B.8(c) Port 9 Block Diagram (Pins P93)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 510 of 520
REJ09B0409-0100
B.9 Block Diagram of Port A
PAn
VCC
PDRAn
Internal data bus
PCRAn
SBY
VSS
PDRA: Port data register A
PCRA: Port control register A
n = 3 to 0
Figure B.9 Port A Block Diagram
Appendix
Rev. 1.00 Dec. 19, 2007 Page 511 of 520
REJ09B0409-0100
B.10 Block Diagrams of Port B
PB
n
Internal
data bus
AMR3 to AMR0
A/D module
V
IN
n = 7 to 0
DEC
Figure B.10(a) Port B Block Diagram
Appendix
Rev. 1.00 Dec. 19, 2007 Page 512 of 520
REJ09B0409-0100
PB
0
Internal
data bus
AMR3 to AMR0
A/D module
V
IN
VINTDSEL
LVD module
extD
DEC
Figure B.10(b) Port B Block Diagram (Pin PB0)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 513 of 520
REJ09B0409-0100
PB
1
Internal
data bus
AMR3 to AMR0
A/D module
V
IN
VINTUSEL
LVD module
extU
DEC
Figure B.10(c) Port B Block Diagram (Pin PB1)
Appendix
Rev. 1.00 Dec. 19, 2007 Page 514 of 520
REJ09B0409-0100
C. Port States in the Different Processing States
Table C.1 Port States Overview
Port Reset Sleep Subsleep Standby Watch Subactive Active
P17,
P14, P13
High
impedance
Retained Retained High
impedance*
Retained Functions Functions
P37 to
P30
High
impedance
Retained Retained High
impedance*
Retained Functions Functions
P43 to
P40
High
impedance
Retained Retained High
impedance
Retained Functions Functions
P57 to
P50
High
impedance
Retained Retained High
impedance*
Retained Functions Functions
P67 to
P60
High
impedance
Retained Retained High
impedance*
Retained Functions Functions
P77 to
P70
High
impedance
Retained Retained High
impedance
Retained Functions Functions
P87 to
P80
High
impedance
Retained Retained High
impedance
Retained Functions Functions
P95 to
P90
High
impedance
Retained Retained High
impedance*
Retained Functions Functions
PA3 to
PA0
High
impedance
Retained Retained High
impedance
Retained Functions Functions
PB7 to
PB0
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
Note: * High level output when MOS pull-up is in on state.
Appendix
Rev. 1.00 Dec. 19, 2007 Page 515 of 520
REJ09B0409-0100
D. List of Product Codes
Table D.1 Product Code Lineup
Product Type
Product Code
Mark Code Package
(Package Code)
H8/38524 HD64F38524H F38524H 80-pin QFP (FP-80A)
H8/38524
Group
Flash
memory
versions
Regular
specifications HD64F38524W F38524W 80-pin TQFP (TFP-80C)
HD64F38524HW F38524H 80-pin QFP (FP-80A)
Wide-range
specifications HD64F38524WW F38524W 80-pin TQFP (TFP-80C)
HD64338524H 38524(***)H 80-pin QFP (FP-80A)
Mask ROM
versions
Regular
specifications HD64338524W 38524(***)W 80-pin TQFP (TFP-80C)
HD64338524HW 38524(***)H 80-pin QFP (FP-80A)
Wide-range
specifications HD64338524WW 38524(***)W 80-pin TQFP (TFP-80C)
H8/38523 HD64338523H 38523(***)H 80-pin QFP (FP-80A)
Mask ROM
versions
Regular
specifications HD64338523W 38523(***)W 80-pin TQFP (TFP-80C)
HD64338523HW 38523(***)H 80-pin QFP (FP-80A)
Wide-range
specifications HD64338523WW 38523(***)W 80-pin TQFP (TFP-80C)
H8/38522 HD64F38522H F38522H 80-pin QFP (FP-80A)
Flash
memory
versions
Regular
specifications HD64F38522W F38522W 80-pin TQFP (TFP-80C)
HD64F38522HW F38522H 80-pin QFP (FP-80A)
Wide-range
specifications HD64F38522WW F38522W 80-pin TQFP (TFP-80C)
HD64338522H 38522(***)H 80-pin QFP (FP-80A)
Mask ROM
versions
Regular
specifications HD64338522W 38522(***)W 80-pin TQFP (TFP-80C)
HD64338522HW 38522(***)H 80-pin QFP (FP-80A)
Wide-range
specifications HD64338522WW 38522(***)W 80-pin TQFP (TFP-80C)
H8/38521 HD64338521H 38521(***)H 80-pin QFP (FP-80A)
Mask ROM
versions
Regular
specifications HD64338521W 38521(***)W 80-pin TQFP (TFP-80C)
HD64338521HW 38521(***)H 80-pin QFP (FP-80A)
Wide-range
specifications HD64338521WW 38521(***)W 80-pin TQFP (TFP-80C)
H8/38520 HD64338520H 38520(***)H 80-pin QFP (FP-80A)
Mask ROM
versions
Regular
specifications HD64338520W 38520(***)W 80-pin TQFP (TFP-80C)
HD64338520HW 38520(***)H 80-pin QFP (FP-80A)
Wide-range
specifications HD64338520WW 38520(***)W 80-pin TQFP (TFP-80C)
Note: (***) is the ROM code.
Appendix
Rev. 1.00 Dec. 19, 2007 Page 516 of 520
REJ09B0409-0100
E. Package Dimensions
Dimensional drawings of the packages FP-80A and TFP-80C are shown in figures E.1 and E.2,
below.
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
*2
*3p
E
D
E
D
80
1
F
20
21
61
60 41
40
yxM
Z
Z
E
H
D
H
b
2
1
1
Detail F
c
AA
L
A
L
Terminal cross section
p
1
1
c
b
c
b
0.83
0.83
0.10
0.12
0.65
0° 8°
3.05
0.12 0.17 0.22
0.24 0.32 0.40
0.00
0.30
0.15
0.10 0.25
17.517.216.9
L
1
Z
E
Z
D
y
x
c
b
1
b
p
A
H
D
A
2
E
D
A
1
c
1
e
e
L
H
E
1.6
16.9 17.2 17.5
2.70
14
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.5 0.8 1.1
14
θ
θ
P-QFP80-14x14-0.65 1.2g
MASS[Typ.]
FP-80A/FP-80AVPRQP0080JB-A
RENESAS CodeJEITA Package Code Previous Code
Figure E.1 FP-80A Package Dimensions
Appendix
Rev. 1.00 Dec. 19, 2007 Page 517 of 520
REJ09B0409-0100
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
12
0.60.50.4
MaxNom
Min
Dimension in Millimeters
Symbol
Reference
12
1.00
14.214.013.8
1.0
H
1
L
e
e
c
1
A
1
E
A
2
H
D
A
b
p
b
1
c
x
y
Z
D
Z
E
L
1
D
13.8 14.0 14.2
1.20
0.00 0.10 0.20
0.17 0.22 0.27
0.20
0.12 0.17 0.22
0.15
0° 8°
0.5
0.10
0.10
1.25
1.25
Index mark
*1
*2
*3
y
F
80
1
Mx
20
21
61
60 41
40
D
E
D
E
p
b
H
E
H
D
Z
Z
Detail F
1
12
c
L
A
AA
L
1
1
p
Terminal cross section
b
c
c
b
θ
θ
P-TQFP80-12x12-0.50 0.4g
MASS[Typ.]
TFP-80C/TFP-80CVPTQP0080KC-A
RENESAS CodeJEITA Package Code Previous Code
Figure E.2 TFP-80C Package Dimensions
Appendix
Rev. 1.00 Dec. 19, 2007 Page 518 of 520
REJ09B0409-0100
Rev. 1.00 Dec. 19, 2007 Page 519 of 520
REJ09B0409-0100
Index
A
ADRRH.................................................. 364
ADRRL................................................... 364
ADSR ..................................................... 366
AEGSR................................................... 285
AMR....................................................... 364
B
BRR........................................................ 317
C
CKSTPR1........218, 226, 240, 257, 323, 367
CKSTPR2................277, 292, 358, 388, 407
E
EBR ........................................................ 134
ECCR...................................................... 287
ECCSR ................................................... 288
ECH........................................................ 291
ECL......................................................... 292
ECPWCRH............................................. 283
ECPWCRL ............................................. 283
ECPWDRH............................................. 284
ECPWDRL............................................. 284
F
FENR...................................................... 135
FLMCR1................................................. 130
FLMCR2................................................. 133
FLPWCR................................................ 134
I
ICRGF.....................................................254
ICRGR....................................................254
IEGR.........................................................59
IENR1.......................................................61
IENR2.......................................................63
IRR1..........................................................65
IRR2..........................................................67
IWPR ........................................................69
L
LCR.........................................................384
LCR2.......................................................386
LPCR ......................................................382
LVDCNT................................................407
LVDCR...................................................402
LVDSR ...................................................405
O
OCRF......................................................234
OCRFH...................................................234
OCRFL....................................................234
OSCCR .....................................................86
P
PCR1.......................................................166
PCR3.......................................................173
PCR4.......................................................180
PCR5.......................................................184
PCR6.......................................................189
PCR7.......................................................193
PCR8.......................................................196
PCRA......................................................202
PDR1.......................................................166
Rev. 1.00 Dec. 19, 2007 Page 520 of 520
REJ09B0409-0100
PDR3...................................................... 173
PDR4...................................................... 180
PDR5...................................................... 184
PDR6...................................................... 189
PDR7...................................................... 193
PDR8...................................................... 196
PDR9...................................................... 199
PDRA ..................................................... 201
PDRB...................................................... 205
PMR1...................................................... 167
PMR2...............................168, 174, 181, 278
PMR3...................................................... 175
PMR5...................................................... 185
PMR9...................................................... 199
PMRB..................................................... 205
PUCR1.................................................... 166
PUCR3.................................................... 174
PUCR5.................................................... 185
PUCR6.................................................... 190
PWCR1................................................... 355
PWCR2................................................... 355
PWDRL1................................................ 355
PWDRL2................................................ 355
PWDRU1................................................ 355
PWDRU2................................................ 355
R
RDR........................................................ 305
RSR ........................................................ 305
S
SCR3.......................................................310
SMR........................................................307
SPCR ..............................................209, 324
SSR.........................................................314
SYSCR1..................................................104
SYSCR2..................................................106
T
TCA ........................................................218
TCC ........................................................225
TCF.........................................................233
TCFH......................................................233
TCFL.......................................................233
TCG ........................................................253
TCRF ......................................................235
TCSRF....................................................237
TCSRW...................................................272
TCW .......................................................275
TDR........................................................306
TLC.........................................................225
TMA .......................................................216
TMC........................................................223
TMG .......................................................255
TMW.......................................................276
TSR.........................................................306
W
WEGR.......................................................70
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/38524 Group
Publication Date: Rev.1.00, Dec. 19, 2007
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
RENESAS SALES OFFICES
Colophon 6.2
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
H8/38524 Group
REJ09B0409-0100
Hardware Manual
