1
FEATURES
APPLICATIONS
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
•Wide Charge-Pump Current Range From200 µA to 3mA•High Performance LVPECL, LVDS, LVCMOSPLL Clock Synchronizer •Dedicated Charge-Pump Supply for WideTuning Voltage Range VCOs•Two Reference Clock Inputs (Primary andSecondary Clock) for Redundancy Support •Presets Charge-Pump to V
CC_CP
/2 for Fastwith Manual or Automatic Selection Center-Frequency Setting of VC(X)O,Controlled Via the SPI Bus•Accepts Two Differential Input (LVPECL orLVDS) References up to 500MHz (or Two •SERDES Startup Mode (Depending on VCXOLVCMOS Inputs up to 250MHz) as PLL Range)Reference
•Auxiliary Input: Output 9 can Serve as 2nd•VCXO_IN Clock is Synchronized to One of Two VCXO Input to Drive All Outputs or to Serve asReference Clocks PLL Feedback Signal•VCXO_IN Frequencies up to 1.5GHz (LVPECL) •RESET or HOLD Input Pin to Serve as Reset or800Mhz for LVDS and 250MHz for LVCMOS Hold FunctionsLevel Signaling
•REFERENCE SELECT for Manual Select•Outputs Can be a Combination of LVPECL, Between Primary and Secondary ReferenceLVDS, and LVCMOS (Up to 10 Differential ClocksLVPECL or LVDS Outputs or up to 20 LVCMOS
•POWER DOWN ( PD) to Put Device in StandbyOutputs), Output 9 can be Converted to an
ModeAuxiliary Input as a 2nd VC(X)O.
•Analog and Digital PLL Lock Indicator•Output Divider is Selectable to Divide by 1, 2,
•Internally Generated VBB Bias Voltages for3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36,
Single-Ended Input Signals40, 42, 48, 50, 56, 60, 64, 70, or 80 On Each
•Frequency Hold-Over Mode Activated byOutput Individually up to Eight Dividers.
HOLD Pin or SPI Bus to Improve Fail-Safe(Except for Output 0 and 9, Output 0 Follows
OperationOutput 1 Divider and Output 9 Follows Output
•Input to All Outputs Skew Control8 Divider)
•Individual Skew Control for Each Output with•SPI Controllable Device Setting
Each Output Divider•Individual Output Enable Control via SPI
•Packaged in a QFN-64 PackageInterface
•ESD Protection Exceeds 2kV HBM•Integrated On-Chip Non-Volatile Memory(EEPROM) to Store Settings without the Need •Industrial Temperature Range of – 40 ° C to 85 °to Apply High Voltage to the Device•Optional Configuration Pins to Select Between
•Low Jitter Clock Driver for High-End TelecomTwo Default Settings Stored in EEPROM
and Wireless Applications•Efficient Jitter Cleaning from Low PLL Loop
•High Precision Test EquipmentBandwidth
•Very Low Phase Noise PLL Core•Programmable Phase Offset (Input Referenceto Outputs)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
DESCRIPTION
PFD
Charge
Pump
P
PR
RI
I_
_I
IN
N
S
SE
EC
C_
_I
IN
N
A
Au
ux
xi
il
li
ia
ar
ry
yI
In
np
pu
ut
t
VCXO/VCOIN
EEPROM
OutputDivider1
U0N
U0P
U1N
U1P
U2N
U2P
U3N
U3P
U4N
U4P
U5N
U5P
U6N
U6P
U7N
U7P
U8N
U8P
U9Nor AUXIN–
U9P or AUXIN+
OutputDivider2
OutputDivider3
OutputDivider4
OutputDivider5
OutputDivider6
OutputDivider7
OutputDivider8
PLL_LOCK
REF_SEL
POWERDOWN
RESET HOLDor
MODE_SEL
AUX_SEL
SPI_MISO
SPI_LE(CD1)
SPI_CLK(CD2)
SPI_MOSI(CD3)
Interface
&Control
Feedback
Divider
CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
www.ti.com
The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes aVCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of tworeference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. Thefollowing relationship applies to the dividers:
Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (R*M) / (P*N)
The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filtercomponents. The PLL loop bandwidth and damping factor can be adjusted to meet different systemrequirements.
The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supportsfrequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are userdefinable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. Thebuilt-in synchronization latches ensure that all outputs are synchronized for very low output skew.
All device settings, including output signaling, divider value selection, input selection, and many more, areprogrammable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the devicesettings.
The device operates in a 3.3V environment and is characterized for operation from – 40 ° C to +85 ° C.
Figure 1. High Level Block Diagram of the CDCE72010
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Product Folder Link(s): CDCE72010
PACKAGE
49
1
32
64
33
48
16
17
TopView
BottomView
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 is available in a 64-pin lead-free “ green ” plastic quad flatpack package with enhanced bottomthermal pad for heat dissipation. The Texas Instruments package designator is RGC (S-PQFP-N64).
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
5,8,11,14,19
22,25,28,31 3.3V supply for the output buffers. There is no internal connection between V
CC
and AV
CC
.VCC Power34,37,40, and It is recommended that each V
CC
uses its own supply filter.43VCC_PLL 4, 63 A. Power 3.3V PLL supply voltage for the PLL circuitry.VCC_IN 57, 60 A. Power 3.3V reference input buffers and circuitry supply voltage.VCC_VCXO 51, 54 A. Power 3.3V VCXO input buffer and circuitry supply voltage.GND 32 Ground Ground connected to thermal pad internally.GND PAD Ground Ground on thermal pad. See layout recommendations.VCCA 48, 49 A. Power 3.3V for internal analog circuitry power supplyA.GND_CP 2 Analog ground for charge pumpGround
Charge pump power supply pin used to have the same supply as the external VCO/VCXO.VCC_CP 64 A. Power
It can be set from 2.3V to 3.6V.In SPI mode it is an open drain output and it functions as a master and in slave out as aSPI_MISO 15 DO
serial control data output from the CDCE72010.LVCMOS input, control latch enable for the Serial Programmable Interface (SPI), withSPI_LE
45 I hysteresis in SPI mode.or CD1
In configuration default mode this pin becomes CD1.SPI_CLK LVCMOS input, serial control clock input for the SPI bus interface, with hysteresis. In46 Ior CD2 configuration default mode this pin becomes CD2.LVCMOS input, master out slave in as a serial control data input to CDCE72010 for the SPISPI_MOSI
44 I bus interface. In configuration default mode this pin becomes CD3 and it should be tied toor CD3
GND.
SPI MODE = H; when driven high or left unconnected, it defaults to SPI bus interface mode.CD MODE = L; If tied low the device goes into configuration default mode which isMODE_SEL 16 I configured by CD1, CD2, CD3, and AUX_SEL (CTRL_LE, CTRL_CLK, and CTRL_MOSI).In configuration default mode the device loads various configuration defaults from theEEPROM into memory at start-up.
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CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
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TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
This pin is used in CD mode only. If set to “ 1 ” or left unconnected, it disables output 9 andenables the AUXILIARY input to drive all outputs from output0 to output8 depending on theAUX_SEL 18 I
EEPROM configuration. If driven low in CD mode, it enables output 9 and makes all outputsdriven by the VCXO Input depending on the internal EEPROM configuration.If Auto Reference Select mode is OFF, this pin acts as an External Input Reference SelectPin;
The REF_SEL signal selects one of two input clocks:REF_SEL [1]: PRI_REF is selected;REF_SEL 47 I
REF_SEL [0]: SEC_REF is selected;The input has an internal 150-k Ω pullup resistor and if left unconnected it will default tologic level “ 1 ” .If Auto Reference Select mode in ON, this pin not used.This pin is active low and can be activated externally or by the corresponding bit in the SPIregister (in case of logic high, the SPI setting is valid).POWER_DOWN 17 I This pin switches the device into powerdown modeThe input has an internal 150-k Ω pullup resistor and if left unconnected it will default tologic level “ 1 ” .This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is thedefault function. This pin is active low and can be activated external or via thecorresponding bit in the SPI register.In the case of RESET, the CP (Charge Pump) is switched to 3-state and all counters arereset to zero. The LVPECL outputs are static low (N) and high (P) respectively, and theRESET or HOLD 33 I LVCMOS outputs are all low or high if inverted. In the case of HOLD, the CP (ChargePump) is switched into 3-state mode only. After HOLD is released and with the next validreference clock cycle, the charge pump is switched back into normal operation (CP stays in3-state as long as no reference clock is valid). During HOLD, all outputs are at normaloperation. This mode allows external control of “ frequency hold-over ” mode. The input hasan internal 150-k Ω pullup resistor.VCXO IN+ 53 I VCXO input (+) for LVPECL+, LVDS+, and LVCMOS level inputs.Complementary VCXO input for LVPECL-, LVDS- inputs. In the case of a LVCMOS levelVCXO IN – 52 I
input on VCXO IN+, ground this pin.Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary ReferencePRI REF+ 59 I
Clock.
Universal input buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. InPRI REF – 58 I
the case of LVCMOS signaling, ground this pin.Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the SecondarySEC REF+ 62 I
Reference Clock.Universal input buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock.SEC REF – 61 I
In the case of LVCMOS signaling, ground this pin.Analog Test Point for TI internal testing. Connect a 1k Ωpull-down resistor or leaveTESTOUTA 1 A
unconnected.
LVCMOS output for TI internal testing. Leave unconnected unless it is configured as theSTATUS 55 AO/O
IREF_CP pin. In this case it should be connected to a 12-k Ωresistor to GND.CP_OUT 3 AO Charge pump outputVBB 56 AO Internal voltage bias analog outputLVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock. Thisoutput can be programmed to be a digital lock detect or analog lock detect (see descriptionof Analog Lock). The PLL is locked (set high), if the rising edge of either the PRI_REF orSEC_REF clock and the VCXO_IN clock at the PFD (Phase Frequency Detector) are insidePLL_LOCK 50 AI/O the lock detect window for a predefined number of successive clock cycles.The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF clockand the VCXO_IN clock at the PFD are outside the lock detect window.The lock detect window and the number of successive clock cycles are user definable (viathe SPI interface).
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Product Folder Link(s): CDCE72010
PACKAGE THERMAL RESISTANCE FOR QFN (RGZ) PACKAGE
(1) (2)
ABSOLUTE MAXIMUM RATINGS
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTIONNAME NO.
U0P:U0N 7,6U1P:U1N 10,9U2P:U2N 13,12U3P:U3N 21,20 The main outputs of the CDCE72010 are user definable and can be any combination of upU4P:U4N 24,23 O to 9 LVPECL outputs, 9 LVDS outputs, or up to 18 LVCMOS outputs. The outputs areU5P:U5N 27,26 selectable via the SPI interface. The power-up setting is EEPROM configurable.U6P:U6N 30,29U7P:U7N 36,35U8P:U8N 39,38
Positive universal output buffer 9 can be 3-stated and used as a positive universal auxiliaryU9P or AUXINP 42 I/O input buffer (It requires external termination). The auxiliary input signal can be routed todrive the outputs or the feedback loop to the PLL.Negative universal output buffer 9 can be 3-stated and used as a negative universalU9N or AUXINN 41 I/O auxiliary input buffer (It requires external termination). The auxiliary input signal can berouted to drive the outputs or the feedback loop to the PLL.
AIRFLOW
θ
JP
( ° C/W)
(3)
θ
JA
( ° C/W)(LFM)
0 JEDEC compliant board (6 × 6 VIAs on PAD) 1.5 28100 JEDEC compliant board (6 × 6 VIAs on PAD) 1.5 17.60 Recommended layout (10 × 10 VIAs on PAD) 1.5 22.8100 Recommended layout (10 × 10 VIAs on PAD) 1.5 13.8
(1) The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).(2) Connected to GND with 9 thermal vias (0.3 mm diameter).(3) θ
JP
(Junction – Pad) is used for the QFN package, because the main heat flow is from the junction to the GND-pad of the QFN.
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
,AV
CC
, Supply voltage range
(1)
– 0.5 4.6 VV
CC_CP
V
I
Input voltage range
(2)
– 0.5 V
CC
+ 0.5 VV
O
Output voltage range
(2)
– 0.5 V
CC
+ 0.5 VInput current V
I
< 0, V
I
> V
CC
± 20 mAOutput current for LVPECL/LVCMOS Outputs 0 < V
O
< V
CC
± 50 mAT
J
Junction temperature 125 ° CT
stg
Storage temperature range – 65 150 ° C
(1) All supply voltages have to be supplied simultaneously.(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
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RECOMMENDED OPERATING CONDITIONS
CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
www.ti.com
for the CDCE72010 device for under the specified industrial temperature range of – 40 ° C to 85 ° C
MIN NOM MAX UNIT
Power Supply
V
CC
Supply voltage 3 3.3 3.6 VV
CC_PLL
,V
CC_IN
,
Analog supply voltage 3 3.3 3.6V
CC_VCXO
,V
CCA
V
CC_CP
2.3 V
CC
VREF at 30.72MHz VCXO at Divider 1 set to divide by 8 (DCRP
LVPECL
491.52MHz Outputs are 30%) Divider 2 set to divide by 4 2.9 WLVPECL-HS (DCR 30%) Divider 3 set to divideby 2 (DCR 30%) Divider 4 set toREF at 30.72MHz VCXO atP
LVDS
2.0 Wdivide by 2 (DCR 30%) Divider 5491.52MHz Outputs are LVDS-HS
set to divide by 1 (DCR 30%)Divider 6 set to divide by 1 (DCR0%) Divider 7 set to divide by 1REF at 30.72MHz VCXO atP
LVCMOS
2.2 W(DCR 0%) Divider 8 set to divide by122.88MHz Outputs are LVCMOS
1 (DCR 0%) DCR: Divider CurrentReduction SettingREF at 30.72MHz VCXO at Dividers are disabled. Outputs areP
OFF
775 mW491.52MHz disabled.P
PD
Device is powered down 30 mWTypical Operating Conditions at V
CC
=3.3V and 25 ° C unless otherwise specified.
Differential Input Mode (PRI_REF, SEC_REF, VCXO_IN and AUX_IN)
V
INPP
Input amplitude
(1)
(V
_INP
– V
INN
) 0.1 1.3 VV
ICM
Common-mode input voltage 1.0 V
CC
– 0.3 VDifferential input current high ( NoI
IH
V
I
= V
CC
, V
CC
= 3.6 V 20 µAinternal termination)
Differential input current low( NoI
IL
V
I
= 0 V, V
CC
= 3.6 V – 20 20 µAinternal termination)
Input capacitance on PRI_REF, SEC_REF and VCXO_REF 3 pFInput capacitance on AUX_IN 7 pF
LVCMOS Input Mode (SPI_CLK, SPI_MOSI, SPI_LE, PD, RESET, REF_SEL, MOD_SEL)
V
IL
Low-level input voltage LVCMOS
(2)
0 0.3 V
CC
VV
IH
High-level input voltage LVCMOS
(2)
0.7 V
CC
V
CC
VV
IK
LVCMOS input clamp voltage V
CC
= 3 V, II = – 18 mA – 1.2 VI
IH
LVCMOS input current V
I
= V
CC
, V
CC
= 3.6 V 20 µAI
IL
LVCMOS input V
I
= 0 V, V
CC
= 3.6 V – 10 – 40 µAC
I
Input capacitance (LVCMOS
V
I
= 0 V or V
CC
3 pFsignals)
(1) V
INPP
minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum V
INPP
of150mV.
(2) V
IL
and V
IH
are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an AC couplingto V
CC
/2 is provided.
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TIMING REQUIREMENTS
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
over recommended ranges of supply voltage, load, and operating free-air temperature
(1) (2) (3) (4)
PARAMETER MIN TYP MAX UNIT
PRI_REF/SEC_REFIN
f
REF - Single
For single-ended inputs ( LVCMOS) on PRI_REF and SEC_REF 250 MHzFor differential inputs (LVDS and LVPECL) on PRI_REF andf
REF - Diff
SEC_REF 500 MHz(R divider set to DIV2)Duty Cycle 60%Duty cycle of PRI_REF or SEC_REF at V
CC
/2 40%Single
Duty Cycle
Duty cycle of PRI_REF or SEC_REF at V
CC
/2 40% 60%Diff
VCXO_IN, AUX_IN
f
REF - Single
For single-ended inputs ( LVCMOS) 250 MHzf
REF - Diff
For differential inputs (LVDS and LVPECL) 1500 MHzDuty Cycle 60%Duty cycle of PRI_REF or SEC_REF at V
CC
/2 40%Single
Duty Cycle
Duty cycle of PRI_REF or SEC_REF at V
CC
/2 40% 60%Diff
SPI/Control (SPI Bus Timing)
f
CTRL_CLK
CTRL_CLK frequency 20 MHzt2 SPI_MOSI to SPI_CLK setup time 10 nst3 SPI_MOSI to SPI_CLK hold time 10 nst4 SPI_CLK high duration 25 nst5 SPI_CLK low duration 25 nst1 SPI_LE to SPI_CLK setup time 10 nst6 SPI_CLK to SPI_LE setup time 10 nst7 SPI_LE pulse width 20 nst8 SPI_MISO to SPI_CLK data valid (first valid bit after LE) 10 ns
PD, RESET, Hold, REF_SEL
Rise and fall time of the PD, RESET, Hold, REF_SEL signal from 20%t
r
/t
f
4 nsto 80% of V
CC
(1) From 250MHz to 500MHz is achieved by setting the divide by 2 in P ’(2) If the feedback clock (derived from the VCXO input) is less than 2MHz, the device stays in normal operation mode but the frequencydetection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. Thisaffects the HOLD-Over-Function as well as the PLL_LOCK signal is no longer valid.(3) Use a square wave for lower frequencies ( < 80 MHz).(4) Slew rate requirement
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AC/DC CHARACTERISTICS
CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
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over the specified industrial temperature range of – 40 ° C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
SPI Output (MISO) / PLL Digital (Output Mode)
I
OH
High-level output current V
CC
= 3.3 V V
O
= 1.65 V – 30 mAI
OL
Low-level output current V
CC
= 3.3 V V
O
= 1.65 V 33 mAHigh-level output voltageV
OH
V
CC
= 3 V I
OH
= – 100 µA V
CC
– 0.5 Vfor LVCMOS outputsLow-level output voltageV
OL
V
CC
= 3 V I
OL
= 100 µA 0.3 Vfor LVCMOS outputsOutput capacitance onC
O
V
CC
= 3.3 V; VO = 0 V or V
CC
3 pFMISOI
OZH
3-state output current 5 µAV
O
= V
CCV
O
= 0VI
OZL
3-state output current – 5 µA
PLL Analog (Input Mode)
High-impedance stateI
OZH
LOCK output current for PLL V
O
= 3.3 V ( PD is set low) 22 µALOCK output
(2)
High-impedance stateI
OZL
LOCK output current for PLL V
O
= 0 V ( PD is set low) – 22 µALOCK outputPositive input thresholdV
T+
V
CC
= min to max V
CC
× 0.55 Vvoltage
Negative input thresholdV
T –
V
CC
= min to max V
CC
× 0.35 Vvoltage
VBB
VCXO termination voltagedepends on the settings IBB = – 0.2mAVBB 0.9 1.9 Vof the VCXO/AUX_IN Depending on the settinginput buffers
Input Buffers Internal Termination Resistors (VCXO_IN,PRI_REF and SEC_REF)
Termination resistance
(3)
Single ended 53 Ω
Phase Detector
Maximum charge pumpf
CPmax
Default PFD pulse width delay 100 MHzfrequency
Charge Pump
Charge pump 3-stateICP3St 0.5 V < VCP < V
CC_CP
– 0.5 V 15 nAcurrentICPA ICP absolute accuracy V
CP
= 0.5 V
CC_CP
; internal reference resistor 20 %VCP = 0.5 V
CC_CP
; external reference resistorICPA ICP absolute accuracy 5 %12k Ω(1%)Sink/source current 0.5 V < VCP < V
CC_CP
– 0.5 V, SPI defaultICPM 4 %matching settingsIVCPM ICP vs VCP matching 0.5 V < VCP < V
CC_CP
– 0.5 V 6 %Voltage on STATUS PIN 12-k Ωresitor to GNDV
I_REF_CP
when configured as (External current path for accurate charge 1.24 VI_REF_CP pump current)
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.(2) 160-k Ωpull-down resistor(3) Termination resistor can vary by 20%.
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AC/DC CHARACTERISTICS (CONTINUED)
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
over the specified industrial temperature range of – 40 ° C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
LVCMOS Output
Output frequency (seef
clk
Load = 5 pF to GND 250 MHzFigure 2 )High-level output voltageV
OH
V
CC
= min to max I
OH
= – 100 µA V
CC
– 0.5 Vfor LVCMOS outputsLow-level output voltageV
OL
V
CC
= min to max I
OL
=100 µA 0.3 Vfor LVCMOS outputsI
OH
High-level output current V
CC
= 3.3 V V
O
= 1.65 V – 30 mAI
OL
Low-level output current V
CC
= 3.3 V, V
O
= 1.65 V 33 mAPhase offset without VCXO at 491.52MHz, Output 1 is divide byt
pho
using available delay 16 and reference at 30.72MHz, M and N 13 nsadjustment delays are fixed to one value (set to 0).t
pd(LH)
/ Propagation delay from Crosspoint to V
CC
/2, load = 5 pF, (PLL
3.3 nstpd(HL)
VCXO_IN to Outputs bypass mode)Divide by 1 for all dividers 75Skew, output-to-output
Divide by 16 for all dividers 75t
sk(o)
LVCMOS single-ended psDivide by 1 for divider 1 divide by 16 for alloutput
1400other dividersOutput capacitance on Y0C
O
V
CC
= 3.3 V; V
O
= 0 V or V
CC
5 pFto Y8C
O
Output capacitance on Y9 V
CC
= 3.3 V; V
O
= 0 V or V
CC
5 pF3-state LVCMOS outputI
OZH
V
O
= V
CC
5µAcurrent
3-state LVCMOS outputI
OZL
V
O
= 0V – 5 µAcurrent
Power-down outputI
OPDH
V
O
= V
CC
25 µAcurrent
Power-down outputI
OPDL
V
O
= 0V 5 µAcurrentDuty cycle LVCMOS 50% to 50% 45 55 %t
slew-rate
Output rise/fall slew rate 3.6 5.2 V/ns
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.
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AC/DC CHARACTERISTICS (CONTINUED)
CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
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over the specified industrial temperature range of – 40 ° C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
LVDS Output
f
clk
Output frequency Open loop config. load, See Figure 2 0 800 MHz|V
OD
| Differential output voltage R
L
= 100 Ω160 270 mVLVDS VOD magnitudeΔ
VOD
50 mVchangeV
OS
Offset voltage – 40 ° C to 85 ° C 1.24 V
ΔV
OS
V
OS
magnitude change 40 mVShort circuit V
OUT+
to
V
OUT
= 0 27 mAground
Short circuit V
OUT –
to
V
OUT
= 0 27 mAground
Reference to output VCXO at 491.52MHz, Output 1 is divide byphase offset without using 16 and reference at 30.72MHz, M and Nt
pho
(2)
14 nsavailable delay delays are fixed to one value (set to 0), PFD:adjustment 240kHz, (M and N = 128)t
pd(LH)
/ Propagation delay time,
Crosspoint to crosspoint, load, see Figure 2 3.0 nst
pd(HL)
VCXO_IN to output
Divide by 1 for all dividers 45Skew, output to output Divide by 16 for all dividers 50tsk(o)
(3)
psLVDS output
Divide by 1 for divider 1
2800Divide by 16 for all other dividersOutput capacitance on Y0C
O
V
CC
= 3.3 V; V
O
= 0 V or V
CC
5 pFto Y8C
O
Output capacitance on Y9 V
CC
= 3.3 V; V
O
= 0 V or V
CC
5 7 pFPower-down outputI
OPDH
V
O
= V
CC
25 µAcurrent
Power-down outputI
OPDL
V
O
= 0V 5 µAcurrent
Duty cycle 45 55 %t
r
/t
f
Rise and fall time 20% to 80% of V
outpp
110 140 160 ps
LVCMOS-TO-LVDS
(4)
Output skew betweentsk
P_C
LVCMOS and LVDS Crosspoint to V
CC
/2 0.9 1.4 1.9 nsoutputs
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.(2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M andVCXO delay N).(3) The tsk(o) specification is only valid for equal loading of all outputs.(4) Operating the LVCMOS or LVDS outputs above the maximum frequency will not cause a malfunction to the device, but the output signalswing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.
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AC/DC CHARACTERISTICS (CONTINUED)
CDCE72010
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
over the specified industrial temperature range of – 40 ° C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
LVDS Hi Swing Output
f
clk
Output frequency Open loop config. load, seeFigure 3 0 800 MHz|V
OD
| Differential output voltage R
L
=100 Ω270 550 mVLVDS VOD magnitudeΔ
VOD
50 mVchangeV
OS
Offset voltage – 40 ° C to 85 ° C 1.24 V
ΔV
OS
V
OS
magnitude change 40 mVShort Circuit V
OUT+
to
V
OUT
= 0 27 mAground
Short Circuit V
OUT –
to
V
OUT
= 0 27 mAground
Reference to output VCXO at 491.52MHz, Output 1 is divide byphase offset without using 16 and reference at 30.72MHz. M and Nt
pho
(2)
14 nsavailable delay delays are fixed to one value. (Set to 0) PFD:adjustment 240kHz, (M and N = 128)t
pd(LH)
/ Propagation delay time,
Crosspoint to crosspoint, load Figure 3 3.0 nst
pd(HL)
VCXO_IN to output
Divide by 1 for all dividers 45Divide by 16 for all dividers 50t
sk(o)
(3)
LVDS output skew psDivide by 1 for divider 1
2800Divide by 16 for all other dividersOutput capacitance on Y0C
O
V
CC
= 3.3 V; V
O
= 0 V or V
CC
5 pFto Y8C
O
Output capacitance on Y9 V
CC
= 3.3 V; V
O
= 0 V or V
CC
7 pFPower-down outputIOPDH V
O
= V
CC
25 µAcurrent
Power-down outputIOPDL V
O
= 0V 5 µAcurrentDuty cycle 45 55 %t
r
/t
f
Rise and fall time 20% to 80% of V
outpp
110 160 190 ps
LVCMOS-TO-LVDS
(4)
Output skew betweentsk
P_C
LVCMOS and LVDS Crosspoint to V
CC
/2 0.9 1.4 1.9 nsoutputs
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.(2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M andVCXO delay N).(3) The tsk(o) specification is only valid for equal loading of all outputs.(4) Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the outputsignal swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.
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AC/DC CHARACTERISTICS (CONTINUED)
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over the specified industrial temperature range of – 40 ° C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
LVPECL Output
f
clk
Output frequency Open loop config. 0 1500 MHzLVPECL high-level outputV
OH
Load, see Figure 5 V
CC
– 1.06 V
CC
– 0.88 Vvoltage
LVPECL low-level outputV
OL
Load, see Figure 5 V
CC
– 2.02 V
CC
– 1.58 Vvoltage|VOD| Differential output voltage Load, see Figure 5 610 970 mVReference to output VCXO at 491.52MHz, Output 1 is divide byphase offset without using 16 and reference at 30.72MHz, M and Nt
pho
(2)
14 nsavailable delay delays are fixed to one value (set to 0), PFD:adjustment 240kHz, (M and N = 128)t
pd(LH)
/ Propagation delay time,
Crosspoint to crosspoint, load, see Figure 5 3.4 nst
pd(HL)
VCXO_IN to output
Divide by 1 for all dividers 45Divide by 16 for all dividers 50t
sk(o)
(3)
LVPECL output skew psDivide by 1 for divider 1
2700Divide by 16 for all other dividersOutput capacitance on Y0C
O
V
CC
= 3.3 V; V
O
= 0 V or V
CC
5 pFto Y8C
O
Output capacitance on Y9 V
CC
= 3.3 V; V
O
= 0 V or V
CC
7 pFPower-down outputIOPDH V
O
= V
CC
25 µAcurrent
Power-down outputIOPDL V
O
= 0 V 5 µAcurrent
Duty cycle 45 55 %t
r
/t
f
Rise and fall time 20% to 80% of V
outpp
55 75 135 ps
LVDS-TO-LVPECL
Output skew betweentsk
P_C
LVDS and LVPECL Crosspoint to V
CC
/2; 0.9 1.1 1.3 nsoutputs
LVCMOS-TO-LVPECL
Output skew betweentsk
P_C
LVCMOS and LVPECL Crosspoint to V
CC
/2; – 150 260 700 psoutputs
(4)
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.(2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M andVCXO delay N).(3) The tsk(o) specification is only valid for equal loading of all outputs. :(4) Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the outputsignal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.
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AC/DC CHARACTERISTICS (CONTINUED)
CDCE72010
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
over the specified industrial temperature range of – 40 ° C to 85 ° C
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
LVPECL Hi Swing Output
f
clk
Output frequency Open loop config. 0 1500 MHzLVPECL high-levelV
OH
Load, see Figure 5 V
CC
– 1.11 V
CC
– 0.87 Voutput voltageLVPECL low-level outputV
OL
Load, see Figure 5 V
CC
– 2.06 V
CC
– 1.73 Vvoltage
Differential output|VOD| Load, see Figure 5 760 1160 mVvoltage
Reference to output VCXO at 491.52MHz, Output 1 is divide by 16phase offset without and reference at 30.72MHz, M and N delayst
pho
(2)
14 nsusing available delay are fixed to one value (set to 0), PFD:adjustment 240kHz, (M and N = 128)t
pd(LH)
/ Propagation delay time,
Crosspoint to crosspoint, load, see Figure 5 3.4 nst
pd(HL)
VCXO_IN to output
Divide by 1 for all dividers 45Divide by 16 for all dividers 50t
sk(o)
(3)
LVPECL output skew psDivide by 1 for divider 1
2700Divide by 16 for all other dividersOutput capacitance onC
O
V
CC
= 3.3 V; V
O
= 0 V or V
CC
5 pFY0 to Y8Output capacitance onC
O
V
CC
= 3.3 V; V
O
= 0 V or V
CC
7 pFY9
Power-down outputIOPDH V
O
= V
CC
25 µAcurrent
Power-down outputIOPDL V
O
= 0V 5 µAcurrent
Duty cycle 45 55 %t
r
/t
f
Rise and fall time 20% to 80% of V
outpp
55 75 135 ps
LVDS-TO-LVPECL
Output skew betweentsk
P_C
LVDS and LVPECL Crosspoint to V
CC
/2 0.9 1.1 1.3 nsoutputs
LVCMOS-TO-LVPECL
Output skew betweentsk
P_C
LVCMOS and LVPECL Crosspoint to V
CC
/2 – 150 260 700 psoutputs
(4)
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25 ° C.(2) This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M andVCXO delay N).(3) The tsk(o) specification is only valid for equal loading of all outputs.(4) Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the outputsignal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS andLVPECL.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
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PARAMETER MEASUREMENT INFORMATION
100 WOscilloscope
5pf
LVCMOS
VCC-2
Oscilloscope
50 W
50 W
150 W
Oscilloscope
150 W
50 W
50 W
CDCE72010
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Figure 2. LVCMOS Output Termination Setup Figure 3. LVDS DC Termination Setup
Figure 4. LVPECL AC Termination Setup Figure 5. LVPECL DC Termination Setup
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TYPICAL CHARACTERISTICS
550
600
650
700
750
800
850
900
950
1000
1050
1100
200 400 600 800 1000 1200 1400 1600 1800
(mV)
T =25ºC
A
Load50 toW
VCC - 2C
Frequency-MHz
V =3.0V
CC
V =3.6V
CC
V =3.3V
CC
700
750
800
850
900
950
1000
1050
1100
1150
1200
1250
200 400 600 800 1000 1200 1400 1600 1800
(mV)
T =25ºC
A
Load50 toW
V – 2V
CC
V =3.0V
CC
V =3.6V
CC
V =3.3V
CC
Frequency-MHz
100
140
180
220
260
300
340
380
420
460
500
100 200 300 400 500 600 700 800 900
(mV)
T =25ºC
A
Load100 W
Frequency-MHz
V =3.0V
CC
V =3.3V
CC V =3.6V
CC
60
0
CDCE72010
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
LVPECL OUTPUT SWING Hi Swing LVPECL OUTPUT SWINGvs vsFREQUENCY FREQUENCY
Figure 6. Figure 7.
LVDS OUTPUT SWING Hi Swing LVDS OUTPUT SWINGvs vsFREQUENCY FREQUENCY
Figure 8. Figure 9.
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1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
100 200 300 400 500
V =3.3V
CC
VC
C=3.6V
V =3.0V
CC
T =25ºC
A
Load5pF
(V)
Frequency-MHz
CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)
LVCMOS OUTPUT WINGvsFREQUENCY
Figure 10.
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APPLICATION INFORMATION
PHASE NOISE ANALYSIS
CDCE72010
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Phase noise is measured in a closed loop mode of 491.52MHz VCXO and 30.72MHz reference and a 100Hzloop. Output 1 is measured for divide by one, output 6 for divide by 4, and output 9 for divide by 16.
Table 1. Phase Noise for LVPECL High Swing
Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by4 = 122.88MHz, Divide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA, Loop BW = 100Hz, Output 1 =491.52 MHZ, Output Buffer: LVPECL-HS
PHASE NOISE VCXO OPEN REFERENCE LVPECL-HS LVPECL-HS LVPECL-HS
UNITAT OFFSET LOOP 30.72MHz DIVIDE BY 1 DIVIDE BY 4 DIVIDE BY 16
10Hz – 64 – 107 – 80 – 92 – 105 dBc/Hz100Hz – 99 – 123 – 92 – 104 – 116 dBc/Hz1kHz – 113 – 134 – 115 – 127 – 139 dBc/Hz10kHz – 135 – 153 – 135 – 145 – 158 dBc/Hz100kHz – 148 – 156 – 146 – 155 – 162 dBc/Hz1MHz – 148 – 158 – 146 – 155 – 162 dBc/Hz10MHz – 149 – 147 – 156 dBc/Hz
Table 2. Phase Noise for LVDS High Swing
Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by4 = 122.88MHz, DIvide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA Loop BW = 100Hz, Output 1 =491.52 MHZ, Output Buffer: LVDS-HS
VCXO OPEN LVDS – HS LVDS-HS LVDS-HSPARAMETER REFERENCE UNITLOOP DIVIDE BY 1 DIVIDE BY 4 DIVIDE BY 16
10Hz – 64 – 107 – 82 – 94 – 104 dBc/Hz100Hz – 99 – 123 – 92 – 105 – 117 dBc/Hz1kHz – 113 – 134 – 114 – 127 – 139 dBc/Hz10kHz – 135 – 153 – 135 – 145 – 151 dBc/Hz100kHz – 148 – 156 – 145 – 152 – 153 dBc/Hz1MHz – 148 – 158 – 146 – 152 – 153 dBc/Hz10MHz – 149 – 146 – 152 dBc/Hz
Table 3. Phase Noise for LVCMOS
Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by4 = 122.88MHz, DIvide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA, Loop BW = 100Hz, Output 1 =491.52 MHZ, Output Buffer: LVCMOS
VCXO OPEN LVCMOS LVCMOSPARAMETER REFERENCE N/A UNITLOOP DIVIDE BY 4 DIVIDE BY 16
10Hz – 64 – 107 – 91 – 105 dBc/Hz100Hz – 99 – 123 – 104 – 116 dBc/Hz1kHz – 113 – 134 – 127 – 139 dBc/Hz10kHz – 135 – 153 – 140 – 151 dBc/Hz100kHz – 148 – 156 – 151 – 159 dBc/Hz1MHz – 148 – 158 – 153 – 160 dBc/Hz10MHz – 149 – 154 dBc/Hz
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
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SPI CONTROL INTERFACE
Bit0 Bit1 …… Bit29 Bit30 Bit31
SPI_CLK
SPI_MOSI
SPI_LE
t1
t2 t3
t4 t5
t6
t7
Bit30Bit31
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_LE
Bit0Bit1 Bit2
t2 t3
t6
t7
t8
CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
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The serial interface of the CDCE72010 is a simple bidirectional SPI interface for writing and reading to and fromthe registers of the device. It consists of four control lines: SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_LE. Thereare twelve 28-bit wide registers that can be saved to the EEPROM on-chip, and one status register that is a readonly register. Those registers can be addressed by the four LSBs of a transferred word (bit 0, 1, 2, and bit 3).Every transmitted word must have 32 bits, starting with LSB first. Each word can be written separately. Thetransfer is initiated with the falling edge of SPI_LE; as long as SPI_LE is high, no data can be transferred. DuringSPI_LE low, data can be written. The data has to be applied at SPI_MOSI and has to be stable before the risingedge of SPI_CLK. The transmission is finished by a rising edge of SPI_LE.
Figure 11. Timing Diagram for SPI Write Command
Figure 12. Timing Diagram for SPI Read Command
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Table 4. Register Map
REGISTER COMMENTS WRITE PAYLOAD ( DATA) ADDRESS
WRITE COMMAND ON MOSI 31,30,29,28 … . … … … … .. … … … … … … … … … … … … … … . … … … 4,3,2,1,0
Register0 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0000Register1 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0001Register2 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0010Register3 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0011Register4 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0100Register5 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0101Register6 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0110Register7 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0111Register8 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1000Register9 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1001Register10 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1010Register11 Configuration RAM/EEPROM XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1011Register12 Status/Control RAM Only XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1100Register13 Reserved XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1101Read command (address on 4 LSBs ofInstruction XXXX XXXX XXXX XXXX XXXX XXXX AAAA 1110payload)Instruction Write configuration to EEPROM - UNLOCKED XXXX XXXX XXXX XXXX XXXX XXXX 0001 1111Instruction Write configuration to EEPROM – LOCKED XXXX XXXX XXXX XXXX 1010 XXXX 0011 1111
READ COMMAND ON MISO DATA PAYLOAD IN READ COMMAND
Payload after issuing a read command on
DDDD DDDD DDDD DDDD DDDD DDDD DDDD XXXXMOSI
The SPI serial protocol accepts Word Write operation only. The 12 words include the register settings of theprogrammable functions of the device that can be modified to the customer application by changing one or morebits.
At powerup or if the Power Down ( PD) control signal is applied, the EEPROM loads its content into the registers.When issuing an EEPROM programming (LOCKED or UNLOCKED) instruction, a wait period of 50ms has to beinserted before another instruction is written to the device or power is removed.
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CDCE72010 Default Configuration
CDCE72010
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The CDCE72010 on-board EEPROM has been factory preset to the default settings listed in Table 5
Table 5. CDCE72010 Default Configuration Settings
REGISTER DEFAULT SETTING REGISTER DEFAULT SETTING
REG0000 002C0040 REG0007 EB040717REG0001 83840051 REG0008 010C0158REG0002 83400002 REG0009 01000049REG0003 83400003 REG0010 0BFC07CAREG0004 81800004 REG0011 C000058BREG0005 81800005 REG0012 61E09B0CREG0006 EB040006
The default configuration programmed in the EEPROM is: a 10MHz primary reference single-ended, a491.52MHz LVPECL VCXO running at 80kHz, and PFD with a 10Hz external loop filter. Reference Auto Select isoff, M divider is set for 125, N divider is set to 768, charge pump current is set to 2.2mA, and feedback divider isset to divide by 8. Divider 1 is set to divide by 4, Dividers 2 and 3 are set to divide by 1, Dividers 4 and 5 are setto divide by 2, Dividers 6 and 7 are set to divide by 8, and Divider 8 is set to divide by 16.Output0:LVCMOS,Output1:Hi-LVPECL, Output2: Hi-LVPECL, Output3:Hi_LVPECL, Output4:LVPECL, Output5:LVPECL,Output6:Hi-LVDS, Output7:Hi-LVDS, Output8:LVCMOS and Output9:LVCMOS.
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 0: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT Bit CONDITION
0 A0 Address 0 0
1 A1 Address 1 0
2 A2 Address 2 0
3 A3 Address 3 0
4 0 INBUFSELX
Reference Input Primary and secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)
EEPROMBuffers XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive pin5 1 INBUFSELY
6 2 PRISEL When REFSELCNTRL is set to 1, the following settings apply:If RAM Bits (2,3): 00 – No input buffer is selected/activeReference Input
If RAM Bits (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down EEPROMBuffer7 3 SECSEL
If RAM Bits (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered downIf RAM Bits (2,3): 11 – Auto Select (PRI then SEC).
When set to 0, PRI- or SEC-clock is selected, depending on bits 2 and 3Divider START8 4 VCXOSEL (default) EEPROMDETERM-Block
When set to 1, VCXO/AUX-clock is selected, overwrites bits 2 and 3
Reference Select Control to select if the control of the reference is from theinternal bit in Register 0 RAM bits 2 and 3 or from the external select pin.- When set to 0: the external pin REF_SEL takes over the selection betweenReference
PRI and SEC. Autoselect is not available.9 5 REFSELCNTRL Selection EEPROM- When set to 1: The external pin REF_SEL is ignored. The table in (Register 0Control
< 2 and 3 > ) describes which reference input clock is selected and available(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timingdiagram.
10 6 DELAY_PFD0
PFD pulse width PFD bit 0PFD EEPROMPFD pulse width PFD bit 111 7 DELAY_PFD1
12 8 CP_MODE Selects 3V option [0] or 5V option [1] EEPROMCharge Pump
Determines which direction CP current will regulate (Reference Clock leads to13 9 CP_DIR EEPROMFeedback Clock, Positive CP output current [0], Negative CP output current [1])
Switches the current source in the charge pump on when set to 1 (TI14 10 CP_SRC EEPROMTest-GTME)Charge Pump15 11 CP_SNK Diagnostics Switches the current sink in the charge pump on when set to 1 (TI Test-GTME) EEPROM
16 12 CP_OPA Switches the charge pump op-amp off when set to 1 (TI Test-GTME) EEPROM
17 13 CP_PRE Preset charge pump output voltage to V
CC_CP
/2, on [1], off [0] EEPROM
18 14 ICP0 CP current setting bit 0 EEPROM
19 15 ICP1 Charge Pump CP current setting bit 1 EEPROM
20 16 ICP2 CP current setting bit 2 EEPROM
21 17 ICP3 CP current setting bit 3 EEPROM
22 18 RESERVED EEPROM
23 19 RESERVED EEPROM
Charge Pump Enables the 12-k Ωpull-down resistor at I_REF_CP pin when set to 1 (TI24 20 IREFRES EEPROMDiagnostics Test-GTME)
25 21 PECL0HISWING Output 0 High output voltage swing in LVPECL mode if set to 1 EEPROM
26 22 CMOSMODE0PX
LVCMOS mode select for OUTPUT 0 positive pin.Output 0 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE0PY
28 24 CMOSMODE0NX
LVCMOS mode select for OUTPUT 0 negative pin.Output 0 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE0NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL0X Output 0 22 23 24 25 26 27 EEPROM
LVPECL 000001
LVDS 010111
31 27 OUTBUFSEL0Y Output 0 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.
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Register 1: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT BIT CONDITION
0 A0 Address 0 1
1 A1 Address 1 0
2 A2 Address 2 0
3 A3 Address 3 0
4 0 ACDCSEL Input Buffers If set to 0 AC Termination, If set to 1 DC termination EEPROM
5 1 HYSTEN Input Buffers If set to 1 Input Buffers Hysteresis enabled EEPROM
6 2 TERMSEL Input Buffers If set to 0 Input Buffer Internal Termination enabled EEPROM
7 3 PRIINVBB Input Buffers If set to 1 Primary Input Negative pin biased with internal VBB voltage EEPROM
8 4 SECINVBB Input Buffers If set to 1 Secondary Input Negative pin biased with internal VBB voltage EEPROM
9 5 FAILSAFE Input Buffers If set to 1 Fail Safe is enabled for all input buffers EEPROM
10 6 PH1ADJC0
11 7 PH1ADJC1
12 8 PH1ADJC2
13 9 PH1ADJC3 Output 0 and 1 Coarse phase adjust select for Output Divider 1 EEPROM
14 10 PH1ADJC4
15 11 PH1ADJC5
16 12 PH1ADJC6
17 13 OUT1DIVRSEL0
18 14 OUT1DIVRSEL1
19 15 OUT1DIVRSEL2
Output Divider 1 ratio select20 16 OUT1DIVRSEL3 Output 0 and 1 EEPROM(seeTable 7 )21 17 OUT1DIVRSEL4
22 18 OUT1DIVRSEL5
23 19 OUT1DIVRSEL6
When set to 0, the divider is disabled24 20 EN01DIV Output 0 and 1 EEPROMWhen set to 1, the divider is enabled
25 21 PECL1HISWING Output 1 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE1PX
LVCMOS mode select for OUTPUT 1 Positive Pin.Output 1 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE1PY
28 24 CMOSMODE1NX
LVCMOS mode select for OUTPUT 1 Negative Pin.Output 1 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE1NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL1X Output 1 22 23 24 25 26 27 EEPROM
LVPECL 000001
LVDS 010111
31 27 OUTBUFSEL1Y Output 1 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 2: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT BIT CONDITION
0 A0 Address 0 0
1 A1 Address 1 1
2 A2 Address 2 0
3 A3 Address 3 0
4 0 DLYM0 Reference phase delay M bit0
5 1 DLYM1 DELAY M Reference phase delay M bit1 EEPROM
6 2 DLYM2 Reference phase delay M bit2
7 3 DLYN0 Feedback phase delay N bit0
8 4 DLYN1 DELAY N Feedback phase delay N bit1 EEPROM
9 5 DLYN2 Feedback phase delay N bit2
10 6 PH2ADJC0
11 7 PH2ADJC1
12 8 PH2ADJC2
13 9 PH2ADJC3 Output 2 Coarse phase adjust select for output divider 2 EEPROM
14 10 PH2ADJC4
15 11 PH2ADJC5
16 12 PH2ADJC6
17 13 OUT2DIVRSEL0
18 14 OUT2DIVRSEL1
19 15 OUT2DIVRSEL2
Output Divider 2 ratio select20 16 OUT2DIVRSEL3 Output 2 EEPROM(seeTable 7 )21 17 OUT2DIVRSEL4
22 18 OUT2DIVRSEL5
23 19 OUT2DIVRSEL6
When set to 0, the divider is disabled24 20 EN2DIV Output 2 EEPROMWhen set to 1, the divider is enabled
25 21 PECL2HISWING Output 2 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE2PX
LVCMOS mode select for OUTPUT 2 Positive Pin.Output 2 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE2PY
28 24 CMOSMODE2NX
LVCMOS mode select for OUTPUT 2 Negative Pin.Output 2 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE2NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL2X Output 2 22 23 24 25 26 27 EEPROM
LVPECL 000001
LVDS 010111
31 27 OUTBUFSEL2Y Output 2 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.
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Register 3: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT BIT CONDITION
0 A0 Address 0 1
1 A1 Address 1 1
2 A2 Address 2 0
3 A3 Address 3 0
When set to 0, the REF-clock frequency detector is ON4 0 DIS_FDET_REF PLL Freq. Detect EEPROMWhen set to 1, it is switched OFF
When set to 1, the feedback path frequency detector is switched OFF5 1 DIS_FDET_FB Diagnostics EEPROM(TI Test-GTME)
6 2 BIAS_DIV01 < 0 > When BIAS_DIV01 < 1:0 > =Output Divider 00, No current reduction for all output-divider
EEPROM0 and 1 01, Current reduction for all output-divider by about 20%7 3 BIAS_DIV01 < 1 >
10, Current reduction for all output-divider by about 30%
8 4 BIAS_DIV23 < 0 > When BIAS_DIV23 < 1:0 > =Output Divider 00, No current reduction for all output-divider
EEPROM2 and 3 01, Current reduction for all output-divider by about 20%9 5 BIAS_DIV23 < 1 >
10, Current reduction for all output-divider by about 30%
10 6 PH3ADJC0
11 7 PH3ADJC1
12 8 PH3ADJC2
13 9 PH3ADJC3 Output 3 Coarse phase adjust select for Output Divider 3 EEPROM
14 10 PH3ADJC4
15 11 PH3ADJC5
16 12 PH3ADJC6
17 13 OUT3DIVRSEL0
18 14 OUT3DIVRSEL1
19 15 OUT3DIVRSEL2
Output Divider 3 ratio select20 16 OUT3DIVRSEL3 Output 3 EEPROM(seeTable 7 )21 17 OUT3DIVRSEL4
22 18 OUT3DIVRSEL5
23 19 OUT3DIVRSEL6
When set to 0, the divider is disabled24 20 EN3DIV Output 3 EEPROMWhen set to 1, the divider is enabled
25 21 PECL3HISWING Output 3 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE3PX
LVCMOS mode select for OUTPUT 3 Positive Pin.Output 3 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE3PY
28 24 CMOSMODE3NX
LVCMOS mode select for OUTPUT 3 Negative Pin.Output 3 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE3NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL3X Output 3 22 23 24 25 26 27 EEPROM
LVPECL 000001
LVDS 010111
31 27 OUTBUFSEL3Y Output 3 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 4: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT BIT CONDITION
0 A0 Address 0 0
1 A1 Address 1 0
2 A2 Address 2 1
3 A3 Address 3 0
4 0 RESERVED EEPROM
5 1 RESERVED EEPROM
6 2 RESERVED EEPROM
7 3 RESERVED EEPROM
If set to 1 it will 3-state the charge pump to act as a HOLD on Loss of8 4 HOLDONLOR HOLD-Over EEPROMReference Clocks ( Primary and Secondary)
9 5 RESERVED EEPROM
10 6 PH4ADJC0
11 7 PH4ADJC1
12 8 PH4ADJC2
13 9 PH4ADJC3 Output 4 Coarse phase adjust select for Output Divider 4 EEPROM
14 10 PH4ADJC4
15 11 PH4ADJC5
16 12 PH4ADJC6
17 13 OUT4DIVRSEL0
18 14 OUT4DIVRSEL1
19 15 OUT4DIVRSEL2
Output Divider 4 ratio select20 16 OUT4DIVRSEL3 Output 4 EEPROM(seeTable 7 )21 17 OUT4DIVRSEL4
22 18 OUT4DIVRSEL5
23 19 OUT4DIVRSEL6
When set to 0, the divider is disabled24 20 EN4DIV Output 4 EEPROMWhen set to 1, the divider is enabled
25 21 PECL4HISWING Output 4 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE4PX
LVCMOS mode select for OUTPUT 4 Positive Pin.Output 4 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE4PY
28 24 CMOSMODE4NX
LVCMOS mode select for OUTPUT 4 Negative Pin.Output 4 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE4NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL4X Output 4 22 23 24 25 26 27 EEPROM
LVPECL 000001
LVDS 010111
31 27 OUTBUFSEL4Y Output 4 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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Register 5: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT BIT CONDITION
0 A0 Address 0 1
1 A1 Address 1 0
2 A2 Address 2 1
3 A3 Address 3 0
4 0 BIAS_DIV45 < 0 > When BIAS_DIV45 < 1:0 > =Output Divider 00, No current reduction for all output-divider
EEPROM4 and 5 01, Current reduction for all output-divider by about 20%5 1 BIAS_DIV45 < 1 >
10, Current reduction for all output-divider by about 30%
6 2 BIAS_DIV67 < 0 > When BIAS_DIV67 < 1:0 > =Output Divider 00, No current reduction for all output-divider
EEPROM6 and 7 01, Current reduction for all output-divider by about 20%7 3 BIAS_DIV67 < 1 >
10, Current reduction for all output-divider by about 30%
8 4 RESERVED EEPROM
9 5 RESERVED EEPROM
10 6 PH5ADJC0
11 7 PH5ADJC1
12 8 PH5ADJC2
13 9 PH5ADJC3 Output 5 Coarse phase adjust select for Output Divider 5 EEPROM
14 10 PH5ADJC4
15 11 PH5ADJC5
16 12 PH5ADJC6
17 13 OUT5DIVRSEL0
18 14 OUT5DIVRSEL1
19 15 OUT5DIVRSEL2
Output Divider 5 ratio select20 16 OUT5DIVRSEL3 Output 5 EEPROM(seeTable 7 )21 17 OUT5DIVRSEL4
22 18 OUT5DIVRSEL5
23 19 OUT5DIVRSEL6
When set to 0, the divider is disabled24 20 EN5DIV Output 5 EEPROMWhen set to 1, the divider is enabled
25 21 PECL5HISWING Output 5 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE5PX
LVCMOS mode select for OUTPUT 5 Positive Pin.Output 5 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE5PY
28 24 CMOSMODE5NX
LVCMOS mode select for OUTPUT 5 Negative Pin.Output 5 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE5NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL5X Output 5 22 23 24 25 26 27 EEPROM
LVPECL 0 0 0 0 0 1
LVDS 0 1 0 1 1 1
31 27 OUTBUFSEL5Y Output 5 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
26 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 6: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT BIT CONDITION
0 A0 Address 0 0
1 A1 Address 1 1
2 A2 Address 2 1
3 A3 Address 3 0
0 Feedback Frequency Detector is connected to the Lock Detector4 0 FB_FD_DESEL
1 Feedback Frequency Detector is disconnected from the Lock DetectorLOCK-DET EEPROM5 1 RESERVED Set to 0
0 FB-Deterministic Clock divided by 16 2 FBDETERM_DIV_SEL
1 FB- Deterministic Clock divided by 2FB-
0 FB-Deterministic-DIV2-Block in normal operation7 3 FBDETERM_DIV2_DIS Divider/Deterministi EEPROM1 FB-Deterministic-DIV2 reset (here REG6_RB < 2 > == 0)c Blocks
0 FB-Divider started with delay block (RC), normal operation8 4 FB_START_BYPASS
1 FB-Divider can be started with external REF_SEL-signal (pin)
All Output Dividers 0 Output-Dividers started with delay block (RC), normal operation9 5 DET_START_BYPASS EEPROM1 Output-Dividers can be started with external NRESET-signal (pin)
10 6 PH6ADJC0 Output 6
11 7 PH6ADJC1
12 8 PH6ADJC2
13 9 PH6ADJC3 Coarse phase adjust select for Output Divider 6 EEPROM
14 10 PH6ADJC4
15 11 PH6ADJC5
16 12 PH6ADJC6
17 13 OUT6DIVRSEL0
18 14 OUT6DIVRSEL1
19 15 OUT6DIVRSEL2
Output Divider 6 ratio select20 16 OUT6DIVRSEL3 Output 6 EEPROM(seeTable 7 )21 17 OUT6DIVRSEL4
22 18 OUT6DIVRSEL5
23 19 OUT6DIVRSEL6
When set to 0, the divider is disabled24 20 EN6DIV Output 6 EEPROMWhen set to 1, the divider is enabled
25 21 PECL6HISWING Output 6 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE6PX
LVCMOS mode select for OUTPUT 6 Positive Pin.Output 6 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE6PY
28 24 CMOSMODE6NX
LVCMOS mode select for OUTPUT 6 Negative Pin.Output 6 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE6NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL6X Output 6 22 23 24 25 26 27 EEPROM
LVPECL 000001
LVDS 010111
31 27 OUTBUFSEL6Y Output 6 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22,23,24, and 25 for setting the LVCMOS outputs
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Register 7: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT BIT CONDITION
0 A0 Address 0 1
1 A1 Address 1 1
2 A2 Address 2 1
3 A3 Address 3 0
4 0 LOCKW 0 Lock-detect window Bit 0 (Refer to Reg 9 RAM Bits 6 and 7) EEPROM
5 1 LOCKW 1 Lock-detect window Bit 1 (Refer to Reg 9 RAM Bits 6 and 7)
6 2 RESERVED Set to 0LOCK-DET7 3 LOCKC0 Number of coherent lock events Bit 0 EEPROM
8 4 LOCKC1 Number of coherent lock events Bit 1
9 5 ADLOCK Selects Digital PLL_LOCK 0, Selects Analog PLL_LOCK 1
10 6 PH7ADJC0
11 7 PH7ADJC1
12 8 PH7ADJC2
13 9 PH7ADJC3 Output 7 Coarse phase adjust select for Output Divider 7 EEPROM
14 10 PH7ADJC4
15 11 PH7ADJC5
16 12 PH7ADJC6
17 13 OUT7DIVRSEL0
18 14 OUT7DIVRSEL1
19 15 OUT7DIVRSEL2
Output Divider 7 ratio select20 16 OUT7DIVRSEL3 Output 7 EEPROM(seeTable 7 )21 17 OUT7DIVRSEL4
22 18 OUT7DIVRSEL5
23 19 OUT7DIVRSEL6
When set to 0, the divider is disabled24 20 EN7DIV Output 7 EEPROMWhen set to 1, the divider is enabled
25 21 PECL7HISWING Output 7 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE7PX
LVCMOS mode select for OUTPUT 7 Positive PinOutput 7 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE7PY
28 24 CMOSMODE7NX
LVCMOS mode select for OUTPUT 7 Negative Pin.Output 7 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE7NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL7X Output 7 22 23 24 25 26 27 EEPROM
LVPECL 0 0 0 0 0 1
LVDS 010111
31 27 OUTBUFSEL7Y Output 7 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
28 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 8: SPI ModeSPI RAM POWER UPBIT NAME RELATED BLOCK DESCRIPTION/FUNCTIONBIT BIT CONDITION
0 A0 Address 0 0
1 A1 Address 1 0
2 A2 Address 2 0
3 A3 Address 3 1
4 0 VCXOBUFSELX
VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS)XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin5 1 VCXOBUFSELY
VCXO and AUX6 2 VCXOACDCSEL If Set to 0 AC Termination, If set to 1 DC Termination EEPROMInput Buffers7 3 VCXOHYSTEN If Set to 1 Input Buffers Hysteresis enabled
8 4 VCXOTERMSEL If Set to 0 Input Buffer Internal Termination enabled
9 5 VCXOINVBB VCXO Input Buffer If Set to 1 It Biases VCXO Input negative pin with internal VCXOVBB Voltage EEPROM
10 6 PH8ADJC0
11 7 PH8ADJC1
12 8 PH8ADJC2
13 9 PH8ADJC3 Output 8 and 9 Coarse phase adjust select for Output Divider 8 EEPROM
14 10 PH8ADJC4
15 11 PH8ADJC5
16 12 PH8ADJC6
17 13 OUT8DIVRSEL0
18 14 OUT8DIVRSEL1
19 15 OUT8DIVRSEL2
Output Divider 8 ratio select20 16 OUT8DIVRSEL3 Output 8 and 9 EEPROM(seeTable 7 )21 17 OUT8DIVRSEL4
22 18 OUT8DIVRSEL5
23 19 OUT8DIVRSEL6
When set to 0, the divider is disabled24 20 EN89DIV Output 8 and 9 EEPROMWhen set to 1, the divider is enabled
25 21 PECL8HISWING Output 8 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE8PX
LVCMOS mode select for OUTPUT 8 Positive Pin.Output 8 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE8PY
28 24 CMOSMODE8NX
LVCMOS mode select for OUTPUT 8 Negative Pin.Output 8 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE8NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL8X Output 8 22 23 24 25 26 27 EEPROM
LVPECL 000001
LVDS 010111
31 27 OUTBUFSEL8Y Output 8 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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Register 9: SPI ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 1
1 A1 Address 1 0
2 A2 Address 2 0
3 A3 Address 3 1
Enables the Frequency Hold-Over (External Hold Over Function based on the4 0 HOLDF
external circuitry) on 1, off 0
5 1 RESERVED
6 2 HOLD 3-State Charge Pump 0 - (equal to HOLD pin function)
HOLD function always activated 1 (recommended for test purposes, only)HOLD-Over EEPROMTriggered by analog PLL Lock detect outputs7 3 HOLDTR
If analog PLL Lock Signal is [1] (PLL locked), HOLD is activatedIf analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated
8 4 HOLD_CNT0 HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by(HOLD_CNT0,HOLD_CNT1) : X = Number of Clock Cycles.9 5 HOLD_CNT1
For (00) : X = 64, (01) : X = 128, (10) : X = 256, (11) : X = 512 Clock Cycles
10 6 LOCKW 2 Extended Lock-detect window Bit 2 (also refer to Reg 7 RAM Bits 0 and 1)LOCK-DET EEPROM11 7 LOCKW 3 Extended Lock-detect window Bit 3 (also refer to Reg 7 RAM Bits 0 and 1)
When set to 0, SPI/HOLD_INT and SPI/RESET_INT inverted (default)12 8 NOINV_RESHOL_INT Chip CORE EEPROMWhen set to 1, SPI/HOLD_INT and SPI/RESET_INT not inverted
When GTME = 0, this Bit has no functionality, But when GTME = 1, then:Diagnostic: PLL13 9 DIVSYNC_DIS When set to 0, START-Signal is synchronized to N/M Divider Input Clocks EEPROMN/M Divider
When set to 1, START-Sync N/M Divider in PLL are bypassed
Divider START When set to 0, START-Signal is synchronized to VCXO-Clock14 10 START_BYPASS EEPROMDETERM-Block When set to 1, START-Sync Block is bypassed
Divider START When set to 0, Sync Logic active when VCXO/AUX-Clocks are available15 11 INDET_BP EEPROMDETERM-Block When set to 1, Sync Logic is independent from VCXO- and/or AUX-Clocks
Divider START When set to 0, Sync Logic waits for 1st PLL_LOCK state16 12 PLL_LOCK_BP EEPROMDETERM-Block When set to 1, Sync Logic independent from 1st PLL_LOCK
When set to 0, Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD)Divider START17 13 LOW_FD_FB_EN When set to 1, Sync Logic is started for VCXO/DIV_FB > ~600KHz, stopped for EEPROMDETERM-Block
VCXO/DIV_FB < ~600KHz
PLL When set to 0, M-Divider uses NHOLD as NPRESET18 14 NPRESET_MDIV EEPROMM/FB-Divider When set to 1, M-Divider NOT preseted by NHOLD
19 15 BIAS_DIV_FB < 0 > When BIAS_DIV_FB < 1:0 > =Feedback 00, No current reduction for FB-Divider
EEPROMDivider 01, Current reduction for FB-Divider by about 20%20 16 BIAS_DIV_FB < 1 >
10, Current reduction for FB-Divider by about 30%
21 17 BIAS_DIV89 < 0 > When BIAS_DIV89 < 1:0 > =Output Divider 00, No current reduction for all output-rivider
EEPROM8 and 9 01, Current reduction for all output-divider by about 20%22 18 BIAS_DIV89 < 1 >
10, Current reduction for all output-divider by about 30%
23 19 AUXINVBB If set to 1 it biases AUX Input Negative pin with internal VCXOVBB voltage.AUX Input
EEPROMIf set to 1 AUX in Input Mode Buffer Is disabled. If set to 0 it follows the behavior ofBuffer24 20 DIS_AUX_Y9
FB_MUX_SEL and OUT_MUX_SEL bits settings.
25 21 PECL9HISWING Output 9 High output voltage swing in LVPECL Mode if set to 1 EEPROM
26 22 CMOSMODE9PX
LVCMOS mode select for OUTPUT 9 Positive pin.Output 9 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State27 23 CMOSMODE9PY
28 24 CMOSMODE9NX
LVCMOS mode select for OUTPUT 9 Negative pin.Output 9 EEPROM(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State29 25 CMOSMODE9NY
RAM BITSOUTPUT TYPE30 26 OUTBUFSEL9X Output 9 22 23 24 25 26 27 EEPROM
LVPECL 000001
LVDS 010111
31 27 OUTBUFSEL9Y Output 9 LVCMOS See Settings Above
(1)
0 0 EEPROM
All Outputs Disabled 010110
(1) Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 10: SPI ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 0
1 A1 Address 1 1
2 A2 Address 2 0
3 A3 Address 3 1
4 0 M0 Reference Divider M Bit 0
5 1 M1 Reference Divider M Bit 1
6 2 M2 Reference Divider M Bit 2
7 3 M3 Reference Divider M Bit 3
8 4 M4 Reference Divider M Bit 4
9 5 M5 Reference Divider M Bit 5Reference10 6 M6 Reference Divider M Bit 6(PRI/SEC) Divider EEPROM11 7 M7 Reference Divider M Bit 7M12 8 M8 Reference Divider M Bit 8
13 9 M9 Reference Divider M Bit 9
14 10 M10 Reference Divider M Bit 10
15 11 M11 Reference Divider M Bit 11
16 12 M12 Reference Divider M Bit 12
17 13 M13 Reference Divider M Bit 13
18 14 N0 VCXO Divider N Bit 0
19 15 N1 VCXO Divider N Bit 1
20 16 N2 VCXO Divider N Bit 2
21 17 N3 VCXO Divider N Bit 3
22 18 N4 VCXO Divider N Bit 4
23 19 N5 VCXO Divider N Bit 5
24 20 N6 VCXO Divider N Bit 6VCXO/AUX/SEC
EEPROMDivider N25 21 N7 VCXO Divider N Bit 7
26 22 N8 VCXO Divider N Bit 8
27 23 N9 VCXO Divider N Bit 9
28 24 N10 VCXO Divider N Bit 10
29 25 N11 VCXO Divider N Bit 11
30 26 N12 VCXO Divider N Bit 12
31 27 N13 VCXO Divider N Bit 13
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Register 11: SPI ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 1
1 A1 Address 1 1
2 A2 Address 2 0
3 A3 Address 3 1
4 0 PRI_DIV2 Input Buffers If set to 1 enables Primary Reference Divide by 2 EEPROM
5 1 SEC_DIV2 Input Buffers If set to 1 enables Secondary Reference Divide by 2 EEPROM
FB Path Integer When set to 0, FB divider is active6 2 FB_DIS EEPROMCounter 32 When set to 1, FB divider is disabled
FB Path Integer When set to 0, FB clock is CMOS type7 3 FB_CML_SEL EEPROMCounter 32 When set to 1, FB clock is CML type and uses CML2CMOS converter in PLL
FB-Divider/
When set to 0, Input clock for FB not inverted (normal mode, low speed)8 4 FB_INCLK_INV Deterministic EEPROMWhen set to 1, Input clock for FB inverted (higher speed mode)Blocks
9 5 FB_COUNT32_0 Feedback Counter Bit0
10 6 FB_COUNT32_1 Feedback Counter Bit1
11 7 FB_COUNT32_2 Feedback Counter Bit2FB Path Integer12 8 FB_COUNT32_3 Feedback Counter Bit3 EEPROMCounter 3213 9 FB_COUNT32_4 Feedback Counter Bit4
14 10 FB_COUNT32_5 Feedback Counter Bit5
15 11 FB_COUNT32_6 Feedback Counter Bit6
16 12 FB_PHASE0 Feedback Phase Adjust Bit0
17 13 FB_PHASE1 Feedback Phase Adjust Bit1
18 14 FB_PHASE2 Feedback Phase Adjust Bit2FB Path Integer19 15 FB_PHASE3 Feedback Phase Adjust Bit3 EEPROMCounter 3220 16 FB_PHASE4 Feedback Phase Adjust Bit4
21 17 FB_PHASE5 Feedback Phase Adjust Bit5
22 18 FB_PHASE6 Feedback Phase Adjust Bit6
If set to 0, PLL is in normal mode23 19 PD_PLL PLL EEPROMIf set to 1, PLL is powered down
When set to 0, the VCXO Clock is selected for the Clock Tree and FB-Div andClock Tree andFB_MUX_SEL Det24 20 Deterministic EEPROMSee Table 6 When set to 1, the AUX Clock is selected for the Clock Tree and FB-Div andBlock
Det
OUT_MUX_SEL25 21 Clock Tree If Set to 0 it selects the VCXO Clock and if Set to 1 it selects the AUX Clock EEPROMSee Table 6
Feed Back Path Selects FB/VCXO-Path when set to 0 (TI Test-GTME)26 22 FB_SEL Diagnostics EEPROMThe Secondary Reference clock input is selected when set to 1 (TI Test-GTME)
27 23 NRESHAPE1 Reshapes the Reference Clock Signal 0, Disable Reshape 1 EEPROMReference
If set to 0 it enables short delay for fast operationSelection Control28 24 SEL_DEL1 EEPROMIf Set to 1 Long Delay recommended for Input References below 150Mhz
29 25 RESET_HOLD Reset Circuitry If set to 1 the RESET or HOLD pin acts as HOLD, set to 0 it acts as RESET EEPROM
30 26 EPUNLOCK Status EEPROM Unlock EEPROM
31 27 EPSTATUS Status EEPROM Status EEPROM
Table 6. Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT 9 Selection
FB_MUX_SEL OUT_MUX_SEL PLL FEED AND OUTPUTS FEED AUX INPUT OR OUTPUT 9
0 0 VCXO::PLL, VCXO::Y0 … Y9 and Deterministic Block OUTPUT 9 is enabled1 0 AUXIN::PLL, VCXO::Y0 … Y8 and Deterministic Block AUX IN is enabled0 1 VCXO::PLL, AUXIN::Y0 … Y8 and Deterministic Block AUX IN is enabled1 1 AUXIN::PLL, AUXIN::Y0 … Y8 and Deterministic Block AUX IN is enabled
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 12: SPI Mode (RAM only Register)SPI RAM RELATED PORBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK DEFAULT
0 A0 Address 0 0
1 A1 Address 1 0
2 A2 Address 2 1
3 A3 Address 3 1
4 0 RESERVED RAM
5 1 RESERVED RAM
6 2 RESERVED RAM
7 3 RESERVED RAM
Status8 4 INDET_AUX It indicates that a clock is present at AUX-input (Y9) , when set to 1 RAM(Read Only)
Status9 5 INDET_VCXO It indicates that a clock is present at VCXO-input , when set to 1 RAM(Read Only)
Status10 6 PLL_LOCK It indicates that the PLL is locked when set to 1 RAM(Read Only)
11 7 PD Power Down Power-down mode on when set to 0, Off when set to 1 1 RAM
If set to 0 this bit forces “ RESET or HOLD” depending on the setting ofRESET or12 8 Reset RESET_HOLD bit in Register 11. If set to 0 RESET or HOLD are asserted. 1 RAMHOLD
Set for 1 for normal operation.
General Test Mode Enable, Test Mode is only enabled, if this bit is set to 113 9 GTME Diagnostics 0 RAMThis bit controls many test modes on the device.
14 10 REVISION0 Status Read only: Revision Control Bit 0 RAM
15 11 REVISION1 Status Read only: Revision Control Bit 1 RAM
16 12 REVISION2 Status Read only: Revision Control Bit 2 RAM
When set to 0, all blocks are on. (TI Test-GTME)When set to 1, the VCXO Input, AUX Input and all output buffers and divider17 13 PD_IO Diagnostics 0 RAMblocks are disabled. This test is done to measure the effect of the I/O circuitryon the Charge Pump. (TI Test-GTME)
If set to 0 that Status pin is used as CMOS output to enable TI test modes.18 14 SXOIREF Diagnostics Set to 1 when IREFRES is set to 1 and 12-K Ωresistor is connected. (TI 0 RAMTest-GTME)
19 15 SHOLD Diagnostics Routes the HOLD signal to the PLL_LOCK pin when set to 1 (TI Test-GTME) 0 RAM
20 16 RESERVED 0 RAM
21 17 STATUS0
TI test registers. For TI use only22 18 STATUS1
Route internal signals to external STATUS pin.Diagnostics 1 RAMSTATUS3, STATUS2, STATUS1, STATUS0 (S3, S2, S1, S0) will select that23 19 STATUS2
internal status signal that will be routed to the external STATUS pin.24 20 STATUS3
25 21 TITSTCFG0 Diagnostics TI test registers. For TI use only 0 RAM
26 22 TITSTCFG1 Diagnostics TI test registers. For TI use only 0 RAM
27 23 TITSTCFG2 Diagnostics TI test registers. For TI use only 0 RAM
28 24 TITSTCFG3 Diagnostics TI test registers. For TI use only 0 RAM
29 25 PRIACTIVITY Status It indicates activity on the Primary when set to - (read only bit) RAM
30 26 SECACTIVITY Status It indicates activity on the Secondary when set to - (read only bit) RAM
31 27 RESERVED RAM
NOTE:
If TI test bits (Register 12 < RAM bits 17,18,19, 20> are set to 1000, Reference Selectfrom the Smart Mux will show on the STATUS pin ( Low = Primary REF is selectedand High = Secondary REF is selected).
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OUTPUT DIVIDERS SETTINGS
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SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
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The CDCE72010 has a complex multi stage output divider. The table below describes the setting of Bits 13:19 ofRegister 1 to 8 and the setting for the feedback divider bits 5:11 of register 11. The table below describes dividersettings and the phase relation of the outputs with respect to divide by one clock. To calculate the phase relationbetween 2 different dividers see Output Divider and Phase Adjust Section in this document.
Table 7. Output Dividers and Feedback Divide Settings and Phase Output
FOR REGISTER 1 TO 8 RAM BITS {19[BIT6] TO
DIVIDE BY13[BIT0]} PHASE LAG FROM DIVIDE BY 1TOTALFOR REGISTER 11 RAM BITS {11[BIT6] TO 5[BIT0]}
[Bit 6] [Bit 5] [Bit 4] [Bit 3] [Bit 2] [Bit 1] [Bit 0] Cycle Degree
0 1 0 0 0 0 0 1 0 01 0 0 0 0 0 0 2 0.5 1801 0 0 0 0 0 1 3 0 01 0 0 0 0 1 0 4 0.5 1801 0 0 0 0 1 1 5 0 00 0 0 0 0 0 0 4' 14.5 52200 0 0 0 0 0 1 6 21 75600 0 0 0 0 1 0 8 28.5 102600 0 0 0 0 1 1 10 35 126000 0 0 0 1 0 0 8' 16.5 59400 0 0 0 1 0 1 12 24 86400 0 0 0 1 1 0 16 32.5 117000 0 0 0 1 1 1 20 40 144000 0 0 1 0 0 0 12' 18.5 66600 0 0 1 0 0 1 18 27 97200 0 0 1 0 1 0 24 36.5 131400 0 0 1 0 1 1 30 45 162000 0 0 1 1 0 0 16' 20.5 73800 0 0 1 1 0 1 24' 30 108000 0 0 1 1 1 0 32 40.5 145800 0 0 1 1 1 1 40 50 180000 0 1 0 0 0 0 20' 22.5 81000 0 1 0 0 0 1 30' 33 118800 0 1 0 0 1 0 40' 44.5 160200 0 1 0 0 1 1 50 55 198000 0 1 0 1 0 0 24' 24.5 88200 0 1 0 1 0 1 36 36 129600 0 1 0 1 1 0 48 48.5 174600 0 1 0 1 1 1 60 60 216000 0 1 1 0 0 0 28 26.5 95400 0 1 1 0 0 1 42 39 140400 0 1 1 0 1 0 56 52.5 189000 0 1 1 0 1 1 70 65 234000 0 1 1 1 0 0 32' 28.5 102600 0 1 1 1 0 1 48' 42 151200 0 1 1 1 1 0 64 56.5 203400 0 1 1 1 1 1 80 70 25200
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CONFIGURATION DEFAULT MODE
EEPROM
PLL_LOCK
REF_SEL
POWERDOWN
RESET HOLDor
MODE_SEL
AUX_SEL
SPI_MISO
SPI_LE(CD1)
SPI_CLK(CD2)
SPI_MOSI(CD3)
Interface
&Control
RAMResistors
PLL_LOCK
REF_SEL
POWERDOWN
RESET HOLDor
MODE_SEL
AUX_SEL
CD1
CD2
CD3
EEPROM
Interface
&Control
RAMResistors
CDCE72010
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 has two modes of operation, SPI Interface and Configuration Default Mode. The ConfigurationDefault mode is selected when MODE_SELECT Pin is driven low and it is used where SPI interface is notavailable. In the CD Mode configuration, the SPI interface Pins become static control pins CD1, CD2, CD3 andAUX_SEL as shown in the Pin description. The CD Mode signals are sampled only at power up or after PowerDown are asserted.
In CD Mode BYPASS, CD1 and CD2 are used to switch between EEPROM saved configurations. -CD1 allowsswapping Divider and Phase Adjust value between output couples.•CD2 allows changing the output type for each output.•AUX_SEL Controls the Output Mux between VCXO and AUX Input.•CD3 must be grounded in CD Mode.
Without any interface a single device with a single program can have multiple configurations that can beimplemented on more than one socket.
Figure 13. Writing to EEPROM via SPI Bus in Figure 14. Using CD1, CD2 to Control What is CopiedManufacutring, From EEPROM Into RAM Registers at Power Up3rd Party Vendor or at TI Test
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Register 0: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 0
1 A1 Address 1 0
2 A2 Address 2 0
3 A3 Address 3 0
4 0 INBUFSELX
Reference Input Primary and Secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)
EEPROMBuffers XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin5 1 INBUFSELY
6 2 PRISEL When REFSELCNTRL is set to 1 the following settings apply:If RAM Bit (2,3): 00 – no Input Buffer is selected/activeReference Input
If RAM Bit (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down EEPROMBuffer7 3 SECSEL
If RAM Bit (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered downIf RAM Bit (2,3): 11 – Auto Select (PRI then SEC).
When set to 0, PRI- or SEC-Clocks are selected, depending on Bits 2 and 3Divider START8 4 VCXOSEL (default) EEPROMDETERM-Block
When set to 1, VCXO/AUX-clock selected, overwrites Bits 2 and 3
Reference Select Control to select if the control of the reference is from theinternal bit in Register 0 RAM bits 2 and 3 or from the external select pin.- When set to 0: The external pin REF_SEL takes over the selection betweenReference9 5 REFSELCNTRL PRI and SEC. Autoselect is not available. EEPROMSelection Control
- When set to 1: The external pin REF_SEL is ignored. The Table in (Register 0< 2 and 3 > ) describes, which reference input clock is selected and available at(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing diagram
10 6 DELAY_PFD0 PFD PFD Pulse Width PFD Bit 0 EEPROM
11 7 DELAY_PFD1 PFD PFD Pulse Width PFD Bit 1 EEPROM
12 8 CP_MODE Selects 3V option [0] or 5V option [1] EEPROMCharge Pump
Determines in which direction CP current will regulate (Reference Clock leads to13 9 CP_DIR EEPROMFeedback Clock; Positive CP output current [0]; Negative CP output current [1]
Switches the current source in the Charge Pump on when set to 1 (TI14 10 CP_SRC EEPROMTest-GTME)Diagnostics15 11 CP_SNK Switches the current sink in the Charge Pump on when set to 1 (TI Test-GTME) EEPROM
16 12 CP_OPA Switches the Charge Pump op-amp off when set to 1 (TI Test-GTME) EEPROM
17 13 CP_PRE Preset Charge Pump output voltage to V
CC_CP
/2, on [1], off [0] EEPROM
18 14 ICP0 CP Current Setting Bit 0 EEPROM
19 15 ICP1 Charge Pump CP Current Setting Bit 1 EEPROM
20 16 ICP2 CP Current Setting Bit 2 EEPROM
21 17 ICP3 CP Current Setting Bit 3 EEPROM
22 18 RESERVED EEPROM
23 19 RESERVED EEPROM
Enables the 12k pull-down resistor at I_REF_CP Pin when set to 1 (TI24 20 IREFRES Diagnostics EEPROMTest-GTME)
25 21 PECL0HISWING Output 0 High output voltage swing in LVPECL Mode if set to 1 EEPROM
26 22 RESERVED EEPROM
27 23 RESERVED EEPROM
28 24 OUTBUF0CD2LX
Output Buffer 0 Signaling Selection when CD2 In lowCD2 Low EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF0CD2LY
30 26 OUTBUF0CD2HX
Output Buffer 0 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: output disable31 27 OUTBUF0CD2HY
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Register 1: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 1
1 A1 Address 1 0
2 A2 Address 2 0
3 A3 Address 3 0
4 0 ACDCSEL Input Buffers If Set to 0 AC Termination, If set to 1 DC termination EEPROM
5 1 HYSTEN Input Buffers If Set to 1 Input Buffers Hysteresis enabled EEPROM
6 2 TERMSEL Input Buffers If Set to 0 Input Buffer Internal Termination enabled EEPROM
7 3 PRIINVBB Input Buffers If Set to 1 Primary Input Negative Pin biased with internal VBB voltage. EEPROM
8 4 SECINVBB Input Buffers If Set to 1 Secondary Input Negative Pin biased with internal VBB voltage EEPROM
9 5 FAILSAFE Input Buffers If Set to 1 Fail Safe is enabled for all input buffers. EEPROM
10 6 PH1ADJC0
11 7 PH1ADJC1
12 8 PH1ADJC2
13 9 PH1ADJC3 Output 0 and 1 Coarse phase adjust select for output divider 1 EEPROM
14 10 PH1ADJC4
15 11 PH1ADJC5
16 12 PH1ADJC6
17 13 OUT1DIVRSEL0
18 14 OUT1DIVRSEL1
19 15 OUT1DIVRSEL2
OUTPUT DIVIDER 1 Ratio Select20 16 OUT1DIVRSEL3 Output 0 and 1 EEPROM(See Table 7 )21 17 OUT1DIVRSEL4
22 18 OUT1DIVRSEL5
23 19 OUT1DIVRSEL6
When set to 0, the divider is disabled24 20 EN01DIV Output 0 and 1 EEPROMWhen set to 1, the divider is enabled
25 21 PECL1HISWING Output 1 High output voltage swing in LVPECL Mode if set to 1 EEPROM
CD1 PIN is high and DIVPHA1CD1H is set to lowLoads Output Divider 1 and Phase Adjust 1 into OUTPUT 126 22 DIVPHA1CD1H CD1 High EEPROMCD1 PIN is high and DIVPHA1CD1H is set to highLoads Output Divider 2 and Phase Adjust 2 into OUTPUT 1
CD1 PIN is low and DIVPHA1CD1L is set to lowLoads Output Divider 1 and Phase Adjust 1 into OUTPUT 127 23 DIVPHA1CD1L CD1 Low EEPROMCD1 PIN is low and DIVPHA1CD1L is set to highLoads Output Divider 2 and Phase Adjust 2 into OUTPUT 1
28 24 OUTBUF1CD2LX EEPROMOutput Buffer 1 Signaling Selection when CD2 in lowCD2 Low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF1CD2LY
30 26 OUTBUF1CD2HX EEPROMOutput Buffer 1 Signaling Selection when CD2 in highCD2 High
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF1CD2HY
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Register 2: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 0
1 A1 Address 1 1
2 A2 Address 2 0
3 A3 Address 3 0
4 0 DLYM0 Reference Phase Delay M Bit0
5 1 DLYM1 DELAY M Reference Phase Delay M Bit1 EEPROM
6 2 DLYM2 Reference Phase Delay M Bit2
7 3 DLYN0 Feedback Phase Delay N Bit0
8 4 DLYN1 DELAY N Feedback Phase Delay N Bit1 EEPROM
9 5 DLYN2 Feedback Phase Delay N Bit2
10 6 PH2ADJC0
11 7 PH2ADJC1
12 8 PH2ADJC2
13 9 PH2ADJC3 Output 2 Coarse phase adjust select for output divider 2 EEPROM
14 10 PH2ADJC4
15 11 PH2ADJC5
16 12 PH2ADJC6
17 13 OUT2DIVRSEL0
18 14 OUT2DIVRSEL1
19 15 OUT2DIVRSEL2
OUTPUT DIVIDER 2 Ratio Select20 16 OUT2DIVRSEL3 Output 2 EEPROM(See Table 7 )21 17 OUT2DIVRSEL4
22 18 OUT2DIVRSEL5
23 19 OUT2DIVRSEL6
When set to 0, the divider is disabled24 20 EN2DIV Output 2 EEPROMWhen set to 1, the divider is enabled
25 21 PECL2HISWING Output 2 High output voltage swing in LVPECL Mode if set to 1 EEPROM
CD1 PIN is high and DIVPHA2CD1H is set to lowLoads Output Divider 2 and Phase Adjust 2 into OUTPUT 226 22 DIVPHA2CD1H CD1 High EEPROMCD1 PIN is high and DIVPHA2CD1H is set to highLoads Output Divider 1 and Phase Adjust 1 into OUTPUT 2
CD1 PIN is low and DIVPHA2CD1L is set to lowLoads Output Divider 2 and Phase Adjust 2 into OUTPUT 227 23 DIVPHA2CD1L CD1 Low EEPROMCD1 PIN is low and DIVPHA2CD1L is set to highLoads Output Divider 1 and Phase Adjust 1 into OUTPUT 2
28 24 OUTBUF2CD2LX
Output Buffer 2 Signaling Selection when CD2 in lowCD2 Low EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF2CD2LY
30 26 OUTBUF2CD2HX
Output Buffer 2 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF2CD2HY
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 3: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 1
1 A1 Address 1 1
2 A2 Address 2 0
3 A3 Address 3 0
When set to 0, the REF-clock frequency detector is ON4 0 DIS_FDET_REF PLL Freq. Detect EEPROMWhen set to 1, it is switched OFF
When set to 1, the feedback path frequency detector is switched OFF5 1 DIS_FDET_FB Diagnostics EEPROM(TI Test-GTME)
6 2 BIAS_DIV01 < 0 > When BIAS_DIV01 < 1:0 > = EEPROMOutput Divider 00, No current reduction for all output-divider0 and 1 01, Current reduction for all output-divider by about 20%7 3 BIAS_DIV01 < 1 > EEPROM10, Current reduction for all output-divider by about 30%
8 4 BIAS_DIV23 < 0 > When BIAS_DIV23 < 1:0 > = EEPROMOutput Divider 00, No current reduction for all output-divider2 and 3 01, Current reduction for all output-divider by about 20%9 5 BIAS_DIV23 < 1 > EEPROM10, Current reduction for all output-divider by about 30%
10 6 PH3ADJC0
11 7 PH3ADJC1
12 8 PH3ADJC2
13 9 PH3ADJC3 Output 3 Coarse phase adjust select for output divider 3 EEPROM
14 10 PH3ADJC4
15 11 PH3ADJC5
16 12 PH3ADJC6
17 13 OUT3DIVRSEL0
18 14 OUT3DIVRSEL1
19 15 OUT3DIVRSEL2
OUTPUT DIVIDER 3 Ratio Select20 16 OUT3DIVRSEL3 Output 3 EEPROM(See Table 7 )21 17 OUT3DIVRSEL4
22 18 OUT3DIVRSEL5
23 19 OUT3DIVRSEL6
When set to 0, the divider is disabled24 20 EN3DIV Output 3 EEPROMWhen set to 1, the divider is enabled
25 21 PECL3HISWING Output 3 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
CD1 PIN is high and DIVPHA3CD1H is set to lowLoads Output Divider 3 and Phase Adjust 3 into OUTPUT 326 22 DIVPHA3CD1H CD1 High EEPROMCD1 PIN is high and DIVPHA3CD1H is set to highLoads Output Divider 4 and Phase Adjust 4 into OUTPUT 3
CD1 PIN is Low and DIVPHA3CD1L is set to lowLoads Output Divider 3 and Phase Adjust 3 into OUTPUT 327 23 DIVPHA3CD1L CD1 Low EEPROMCD1 PIN is Low and DIVPHA3CD1L is set to highLoads Output Divider 4 and Phase Adjust 4 into OUTPUT 3
28 24 OUTBUF3CD2LX
Output Buffer 3 Signaling Selection when CD2 in lowCD2 Low EEPROM(X,Y) = 01:LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF3CD2LY
30 26 OUTBUF3CD2HX
Output Buffer 3 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF3CD2HY
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Register 4: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 0
1 A1 Address 1 0
2 A2 Address 2 1
3 A3 Address 3 0
4 0 RESERVED EEPROM
5 1 RESERVED EEPROM
6 2 RESERVED EEPROM
7 3 RESERVED EEPROM
If set to 1 it will 3-state the charge pump to act as a HOLD on Loss of Reference8 4 HOLDONLOR HOLD- Over EEPROMClocks ( Primary and Secondary)
9 5 RESERVED EEPROM
10 6 PH4ADJC0
11 7 PH4ADJC1
12 8 PH4ADJC2
13 9 PH4ADJC3 Output 4 Coarse phase adjust select for output divider 4 EEPROM
14 10 PH4ADJC4
15 11 PH4ADJC5
16 12 PH4ADJC6
17 13 OUT4DIVRSEL0
18 14 OUT4DIVRSEL1
19 15 OUT4DIVRSEL2
OUTPUT DIVIDER 4 Ratio Select20 16 OUT4DIVRSEL3 Output 4 EEPROM(See Table 7 )21 17 OUT4DIVRSEL4
22 18 OUT4DIVRSEL5
23 19 OUT4DIVRSEL6
When set to 0, the divider is disabled24 20 EN4DIV Output 4 EEPROMWhen set to 1, the divider is enabled
25 21 PECL4HISWING Output 4 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
CD1 PIN is high and DIVPHA4CD1H is set to lowLoads Output Divider 4 and Phase Adjust 4 into OUTPUT 426 22 DIVPHA4CD1H CD1 High EEPROMCD1 PIN is high and DIVPHA4CD1H is set to highLoads Output Divider 3 and Phase Adjust 3 into OUTPUT 4
CD1 PIN is low and DIVPHA4CD1L is set to lowLoads Output Divider 4 and Phase Adjust 4 into OUTPUT 427 23 DIVPHA4CD1L CD1 Low EEPROMCD1 PIN is low and DIVPHA4CD1L is set to highLoads Output Divider 3 and Phase Adjust 3 into OUTPUT 4
28 24 OUTBUF4CD2LX
Output Buffer 4 Signaling Selection when CD2 in lowCD2 Low EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF4CD2LY
30 26 OUTBUF4CD2HX
Output Buffer 4 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF4CD2HY
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 5: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 1
1 A1 Address 1 0
2 A2 Address 2 1
3 A3 Address 3 0
4 0 BIAS_DIV45 < 0 > When BIAS_DIV45 < 1:0 > =Output Divider 00, No current reduction for all output-divider
EEPROM4 and 5 01, Current reduction for all output-divider by about 20%5 1 BIAS_DIV45 < 1 >
10, Current reduction for all output-divider by about 30%
6 2 BIAS_DIV67 < 0 > When BIAS_DIV67 < 1:0 > =Output Divider 00, No current reduction for all output-divider
EEPROM6 and 7 01, Current reduction for all output-divider by about 20%7 3 BIAS_DIV67 < 1 >
10, Current reduction for all output-divider by about 30%
8 4 RESERVED EEPROM
9 5 RESERVED EEPROM
10 6 PH5ADJC0
11 7 PH5ADJC1
12 8 PH5ADJC2
13 9 PH5ADJC3 Output 5 Coarse phase adjust select for output divider 5 EEPROM
14 10 PH5ADJC4
15 11 PH5ADJC5
16 12 PH5ADJC6
17 13 OUT5DIVRSEL0
18 14 OUT5DIVRSEL1
19 15 OUT5DIVRSEL2
OUTPUT DIVIDER 5 Ratio Select20 16 OUT5DIVRSEL3 Output 5 EEPROM(See Table 7 )21 17 OUT5DIVRSEL4
22 18 OUT5DIVRSEL5
23 19 OUT5DIVRSEL6
When set to 0, the divider is disabled24 20 EN5DIV Output 5 EEPROMWhen set to 1, the divider is enabled
25 21 PECL5HISWING Output 5 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
CD1 PIN is high and DIVPHA5CD1H is set to lowLoads Output Divider 5 and Phase Adjust 5 into OUTPUT 526 22 DIVPHA5CD1H CD1 High EEPROMCD1 PIN is high and DIVPHA5CD1H is set to highLoads Output Divider 6 and Phase Adjust 6 into OUTPUT 5
CD1 PIN is low and DIVPHA5CD1L is set to lowLoads Output Divider 5 and Phase Adjust 5 into OUTPUT 527 23 DIVPHA5CD1L CD1 Low EEPROMCD1 PIN is low and DIVPHA5CD1L is set to highLoads Output Divider 6 and Phase Adjust 6 into OUTPUT 5
28 24 OUTBUF5CD2LX
Output Buffer 5 Signaling Selection when CD2 in lowCD2 Low EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF5CD2LY
30 26 OUTBUF5CD2HX
Output Buffer 5 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF5CD2HY
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Register 6: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 0
1 A1 Address 1 1
2 A2 Address 2 1
3 A3 Address 3 0
0 Feedback Frequency Detector is connected to the Lock Detector4 0 FB_FD_DESEL
1 Feedback Frequency Detector is disconnected from the Lock DetectorLOCK-DET EEPROM5 1 RESERVED Set to “ 0 ”
0 FB-Deterministic Clock divided by 16 2 FBDETERM_DIV_SEL
1 FB- Deterministic Clock divided by 2FB-Divider /
0 FB-Deterministic-DIV2-Block in normal operation7 3 FBDETERM_DIV2_DIS Deterministic EEPROM1 FB-Deterministic-DIV2 reset (here REG6_RB < 2 > == “ 0 ” )Blocks
0 FB-Divider started with delay block (RC), normal operation8 4 FB_START_BYPASS
1 FB-Divider can be started with external REF_SEL-signal (pin)
All Output 0 Output-Dividers started with delay block (RC), normal operation9 5 DET_START_BYPASS EEPROMDividers 1 Output-Dividers can be started with external NRESET-signal (pin)
10 6 PH6ADJC0
11 7 PH6ADJC1
12 8 PH6ADJC2
13 9 PH6ADJC3 Output 6 Coarse phase adjust select for output divider 6 EEPROM
14 10 PH6ADJC4
15 11 PH6ADJC5
16 12 PH6ADJC6
17 13 OUT6DIVRSEL0
18 14 OUT6DIVRSEL1
19 15 OUT6DIVRSEL2
OUTPUT DIVIDER 6 Ratio Select20 16 OUT6DIVRSEL3 Output 6 EEPROM(See Table 7 )21 17 OUT6DIVRSEL4
22 18 OUT6DIVRSEL5
23 19 OUT6DIVRSEL6
When set to 0, the divider is disabled24 20 EN6DIV Output 6 EEPROMWhen set to 1, the divider is enabled
25 21 PECL6HISWING Output 6 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
CD1 PIN is high and DIVPHA6CD1H is set to lowLoads Output Divider 6 and Phase Adjust 6 into OUTPUT 626 22 DIVPHA6CD1H CD1 High EEPROMCD1 PIN is high and DIVPHA6CD1H is set to highLoads Output Divider 5 and Phase Adjust 5 into OUTPUT 6
CD1 PIN is low and DIVPHA6CD1L is set to lowLoads Output Divider 6 and Phase Adjust 6 into OUTPUT 627 23 DIVPHA6CD1L CD1 Low EEPROMCD1 PIN is low and DIVPHA6CD1L is set to highLoads Output Divider 5 and Phase Adjust 5 into OUTPUT 6
28 24 OUTBUF6CD2LX
Output Buffer 6 Signaling Selection when CD2 in lowCD2 Low EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF6CD2LY
30 26 OUTBUF6CD2HX
Output Buffer 6 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF6CD2HY
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
Register 7: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 1
1 A1 Address 1 1
2 A2 Address 2 1
3 A3 Address 3 0
4 0 LOCKW 0 Lock-detect window bit 0 (Refer to Reg 9 RAM Bits 6 and 7)
5 1 LOCKW 1 Lock-detect window bit 1 (Refer to Reg 9 RAM Bits 6 and 7)
6 2 RESERVED Set to 0LOCK-DET EEPROM7 3 LOCKC0 Number of coherent lock events bit 0
8 4 LOCKC1 Number of coherent lock events bit 1
9 5 ADLOCK Selects Digital PLL_LOCK 0 ,Selects Analog PLL_LOCK 1
10 6 PH7ADJC0
11 7 PH7ADJC1
12 8 PH7ADJC2
13 9 PH7ADJC3 Output 7 Coarse phase adjust select for output divider 7 EEPROM
14 10 PH7ADJC4
15 11 PH7ADJC5
16 12 PH7ADJC6
17 13 OUT7DIVRSEL0
18 14 OUT7DIVRSEL1
19 15 OUT7DIVRSEL2
OUTPUT DIVIDER 7 Ratio Select20 16 OUT7DIVRSEL3 Output 7 EEPROM(See Table 7 )21 17 OUT7DIVRSEL4
22 18 OUT7DIVRSEL5
23 19 OUT7DIVRSEL6
When set to 0, the divider is disabled24 20 EN7DIV Output 7 EEPROMWhen set to 1, the divider is enabled
25 21 PECL7HISWING Output 7 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
CD1 PIN is high and DIVPHA7CD1H is set to lowLoads Output Divider 7 and Phase Adjust 7 into OUTPUT 726 22 DIVPHA7CD1H CD1 High EEPROMCD1 PIN is high and DIVPHA7CD1H is set to highLoads Output Divider 8 and Phase Adjust 8 into OUTPUT 7
CD1 PIN is low and DIVPHA7CD1L is set to lowLoads Output Divider 7 and Phase Adjust 7 into OUTPUT 727 23 DIVPHA7CD1L CD1 Low EEPROMCD1 PIN is low and DIVPHA7CD1L is set to highLoads Output Divider 8 and Phase Adjust 8 into OUTPUT 7
28 24 OUTBUF7CD2LX
Output Buffer 7 Signaling Selection when CD2 in lowCD2 Low EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF7CD2LY
30 26 OUTBUF7CD2HX
Output Buffer 7 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF7CD2HY
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Register 8: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 0
1 A1 Address 1 0
2 A2 Address 2 0
3 A3 Address 3 1
4 0 VCXOBUFSELX VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS)
5 1 VCXOBUFSELY XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive PinVCXO and AUX6 2 VCXOACDCSEL Input Buffers If Set to 0 AC Termination, If set to 1 DC Termination EEPROMVCXO Input Buffer7 3 VCXOHYSTEN If Set to 1 Input Buffers Hysteresis enabled
8 4 VCXOTERMSEL If Set to 0 Input Buffer Internal Termination enabled
9 5 VCXOINVBB VCXO Input Buffer If Set to 1 It biases VCXO Input negative pin with internal VCXOVBB voltage EEPROM
10 6 PH8ADJC0
11 7 PH8ADJC1
12 8 PH8ADJC2
13 9 PH8ADJC3 Output 8 and 9 Coarse phase adjust select for output divider 8 and 9 EEPROM
14 10 PH8ADJC4
15 11 PH8ADJC5
16 12 PH8ADJC6
17 13 OUT8DIVRSEL0
18 14 OUT8DIVRSEL1
19 15 OUT8DIVRSEL2
OUTPUT DIVIDER 8 and 9 Ratio Select20 16 OUT8DIVRSEL3 Output 8 and 9 EEPROM(See Table 7 )21 17 OUT8DIVRSEL4
22 18 OUT8DIVRSEL5
23 19 OUT8DIVRSEL6
When set to 0, the divider is disabled24 20 EN89DIV Output 8 and 9 EEPROMWhen set to 1, the divider is enabled
25 21 PECL8HISWING Output 8 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
CD1 PIN is high and DIVPHA8CD1H is set to lowLoads Output Divider 8 and Phase Adjust 8 into OUTPUT 826 22 DIVPHA8CD1H CD1 High EEPROMCD1 PIN is high and DIVPHA8CD1H is set to highLoads Output Divider 7 and Phase Adjust 7 into OUTPUT 8
CD1 PIN is low and DIVPHA8CD1L is set to lowLoads Output Divider 8 and Phase Adjust 8 into OUTPUT 827 23 DIVPHA8CD1L CD1 Low EEPROMCD1 PIN is low and DIVPHA8CD1L is set to highLoads Output Divider 7 and Phase Adjust 7 into OUTPUT 8
28 24 OUTBUF8CD2LX
Output Buffer 8 Signaling Selection when CD2 in lowCD2 Low EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF8CD2LY
30 26 OUTBUF8CD2HX
Output Buffer 8 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF8CD2HY
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Register 9: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 1
1 A1 Address 1 0
2 A2 Address 2 0
3 A3 Address 3 1
4 0 HOLDF1 Enables the Frequency Hold-Over Function 1 on 1, off 0
5 1 HOLDF2 Enables the Frequency Hold-Over Function 2 on 1, off 0
6 2 HOLD 3-State Charge Pump 0 - (equal to HOLD-Pin function)
HOLD function always activated “ 1 ” (recommended for test purposes, only)HOLD- Over EEPROMTriggered by analog PLL Lock detect outputs7 3 HOLDTR
If analog PLL Lock Signal is [1] (PLL locked), HOLD is activatedIf analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated
8 4 HOLD_CNT0 HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by(HOLD_CNT0,HOLD_CNT1)::X= Number of Clock Cycles.9 5 HOLD_CNT1
For (00)::X=64, (01) ::X=128, (10)::X=256, (11)::X=512 Clock Cycles.
10 6 LOCKW 2 Extended Lock-detect window Bit 2 (Also refer to Reg 7 RAM Bits 0 and 1)LOCK-DET EEPROM11 7 LOCKW 3 Extended Lock-detect window Bit 3 (Also refer to Reg 7 RAM Bits 0 and 1)
NOINV_RESHOL_IN When set to 0, SPI/HOLD_INT and SPI/RESET_INT inverted (default)12 8 Chip CORE EEPROMT When set to 1, SPI/HOLD_INT and SPI/RESET_INT not inverted
When GTME = 0, this bit has no functionality, But when GTME = 1, then:Diagnostic: PLL13 9 DIVSYNC_DIS When set to 0, START-Signal is synchronized to N/M Divider Input Clocks EEPROMN/M Divider
When set to 1, START-Sync N/M Divider in PLL are bypassed
Divider START When set to 0, START-Signal is synchronized to VCXO-Clock14 10 START_BYPASS EEPROMDETERM-Block When set to 1, START-Sync Block is bypassed
Divider START When set to 0, Sync Logic active when VCXO/AUX-Clocks are available15 11 INDET_BP EEPROMDETERM-Block When set to 1, Sync Logic is independent from VCXO- and/or AUX-Clocks
Divider START When set to 0, Sync Logic waits for 1st PLL_LOCK state16 12 PLL_LOCK_BP EEPROMDETERM-Block When set to 1, Sync Logic independent from 1st PLL_LOCK
When set to 0, Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD)Divider START17 13 LOW_FD_FB_EN When set to 1, Sync Logic is started for VCXO/DIV_FB > ~600KHz, EEPROMDETERM-Block
stopped for VCXO/DIV_FB < ~600KHz
PLL When set to 0, M-Divider uses NHOLD1 as NPRESET18 14 NPRESET_MDIV EEPROMM/FB-Divider When set to 1, M-Divider NOT preseted by NHOLD1
19 15 BIAS_DIV_FB < 0 > When BIAS_DIV_FB < 1:0 > =Feedback 00, No current reduction for FB-Divider
EEPROMDivider 01, Current reduction for FB-Divider by about 20%20 16 BIAS_DIV_FB < 1 >
10, Current reduction for FB-Divider by about 30%
21 17 BIAS_DIV89 < 0 > When BIAS_DIV89 < 1:0 > =Output Divider 00, No current reduction for all output-divider
EEPROM8 and 9 01, Current reduction for all output-divider by about 20%22 18 BIAS_DIV89 < 1 >
10, Current reduction for all output-divider by about 30%
23 19 AUXINVBB If Set to 1 it Biases AUX Input Negative Pin with internal VCXOVBB voltage.AUX Buffer EEPROMIf Set to 1 AUX in input Mode Buffer is disabled. If Set to 0 it follows the24 20 DIS_AUX_Y9
behavior of FB_MUX_SEL and OUT_MUX_SEL bits settings.
25 21 PECL9HISWING Output 9 High Output Voltage Swing in LVPECL Mode if set to 1 EEPROM
26 22 RESERVED EEPROM
27 23 RESERVED EEPROM
28 24 OUTBUF9CD2LX
Output Buffer 9 Signaling Selection when CD2 in lowCD2 Low EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable29 25 OUTBUF9CD2LY
30 26 OUTBUF9CD2HX
Output Buffer 9 Signaling Selection when CD2 in highCD2 High EEPROM(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable31 27 OUTBUF9CD2HY
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Register 10: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 0
1 A1 Address 1 1
2 A2 Address 2 0
3 A3 Address 3 1
4 0 M0 Reference Divider M bit 0
5 1 M1 Reference Divider M bit 1
6 2 M2 Reference Divider M bit 2
7 3 M3 Reference Divider M bit 3
8 4 M4 Reference Divider M bit 4
9 5 M5 Reference Divider M bit 5Reference10 6 M6 Reference Divider M bit 6(PRI/SEC) EEPROM11 7 M7 Reference Divider M bit 7Divider M12 8 M8 Reference Divider M bit 8
13 9 M9 Reference Divider M bit 9
14 10 M10 Reference Divider M bit 10
15 11 M11 Reference Divider M bit 11
16 12 M12 Reference Divider M bit 12
17 13 M13 Reference Divider M bit 13
18 14 N0 VCXO Divider N bit 0
19 15 N1 VCXO Divider N bit 1
20 16 N2 VCXO Divider N bit 2
21 17 N3 VCXO Divider N bit 3
22 18 N4 VCXO Divider N bit 4
23 19 N5 VCXO Divider N Bit 5
24 20 N6 VCXO Divider N Bit 6VCXO/AUX/SEC
EEPROMDivider N25 21 N7 VCXO Divider N Bit 7
26 22 N8 VCXO Divider N Bit 8
27 23 N9 VCXO Divider N Bit 9
28 24 N10 VCXO Divider N Bit 10
29 25 N11 VCXO Divider N Bit 11
30 26 N12 VCXO Divider N Bit 12
31 27 N13 VCXO Divider N Bit 13
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Register11: CD ModeSPI RAM RELATED POWER UPBIT NAME DESCRIPTION/FUNCTIONBIT BIT BLOCK CONDITION
0 A0 Address 0 1
1 A1 Address 1 1
2 A2 Address 2 0
3 A3 Address 3 1
4 0 PRI_DIV2 Input Buffers If set to 1 Enables Primary Reference Divide by 2 EEPROM
5 1 SEC_DIV2 Input Buffers If set to 1 Enables Secondary Reference Divide by 2 EEPROM
FB Path Integer When set to 0, FB divider is active6 2 FB_DIS EEPROMCounter 32 When set to 1, FB divider is disabled
FB Path Integer When set to 0, FB clock is CMOS type7 3 FB_CML_SEL EEPROMCounter 32 When set to 1, FB clock is CML type and uses CML2CMOS converter in PLL
FB-Divider /
When set to 0, Input clock for FB not inverted (normal mode, low speed)8 4 FB_INCLK_INV Deterministic EEPROMWhen set to 1, Input clock for FB inverted (higher speed mode)Blocks
9 5 FB_COUNT32_0 Feedback Counter Bit0
10 6 FB_COUNT32_1 Feedback Counter Bit1
11 7 FB_COUNT32_2 Feedback Counter Bit2FB Path Integer12 8 FB_COUNT32_3 Counter 32 Feedback Counter Bit3 EEPROM(P divider)13 9 FB_COUNT32_4 Feedback Counter Bit4
14 10 FB_COUNT32_5 Feedback Counter Bit5
15 11 FB_COUNT32_6 Feedback Counter Bit6
16 12 FB_PHASE0 Feedback Phase Adjust Bit0
17 13 FB_PHASE1 Feedback Phase Adjust Bit1
18 14 FB_PHASE2 Feedback Phase Adjust Bit2FB Path Integer19 15 FB_PHASE3 Counter 32 Feedback Phase Adjust Bit3 EEPROM(P Divider)20 16 FB_PHASE4 Feedback Phase Adjust Bit4
21 17 FB_PHASE5 Feedback Phase Adjust Bit5
22 18 FB_PHASE6 Feedback Phase Adjust Bit6
If set to 0, PLL is in normal mode23 19 PD_PLL PLL EEPROMIf set to 1, PLL is powered down
Clock Tree andFB_MUX_SEL When set to 0, the VCXO Clock is selected for the Clock Tree and FB-Div/Det24 20 Deterministic EEPROMTable 8 When set to 1, the AUX Clock is selected for the Clock Tree and FB-Div/Det.Block
OUT_MUX_SEL25 21 If Set to 0 it selects the VCXO Clock and if Set to 1 it selects the AUX Clock EEPROMTable 8
Feed Back Path Selects FB/VCXO-Path when set to 0 (TI Test-GTME)26 22 FB_SEL Diagnostics EEPROMThe Secondary Reference clock input is selected when set to 1 (TI Test-GTME)
27 23 NRESHAPE1 Reshapes the Reference Clock Signal 0, Disable Reshape 1Reference
EEPROMIf set to 0 it enables short delay for fast operationSelection Control28 24 SEL_DEL1
If Set to 1 Long Delay recommended for input references below 150Mhz.
29 25 RESET_HOLD Reset Circuitry If set to 1 the RESET or HOLD pin acts as HOLD, set to 0 it acts as RESET. EEPROM
30 26 EPUNLOCK Status EEPROM Unlock EEPROM
31 27 EPSTATUS Status EEPROM Status EEPROM
Table 8. Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT 9 Selection
FB_MUX_SEL OUT_MUX_SEL PLL FEED AND OUTPUT FEED AUX INPUT OR OUTPUT 9
0 0 VCXO::PLL, VCXO::Y0 … Y9 and Deterministic Block OUTPUT 9 is Enabled
(1)
1 0 AUXIN::PLL, VCXO::Y0 … Y8 and Deterministic Block AUX IN is Enabled0 1 VCXO::PLL, AUXIN::Y0 … Y8 and Deterministic Block AUX IN is Enabled1 1 AUXIN::PLL, AUXIN::Y0 … Y8 and Deterministic Block AUX IN is Enabled
(1) Default
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Product Folder Link(s): CDCE72010
INTERFACE, CONFIGURATION, AND CONTROL
RAMRegisters
EEPROMCells
Interface&Control
ControlSignals
SPI
UNIVERSAL INPUT AND REFERENCE CLOCK BUFFERS
50W
VBB
1
PRI_REF
SEC_REF
::INBUFSEL
::ACDCSEL
(AC=1,DC=0)
TERMSEL::
PRIINVBB:: X50W
50W
50W
X
X
SECINVBB::
X
X
Y
CDCE72010
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The CDCE72010 is designed to support various applications with SPI bus interface and without. In the casewhere systems lack the SPI bus or a Boot up configuration is required at start up before the management layer isup the built in EEPROM is used to provide this function.
The Interface bus takes the serialized address and data and writes to the specified RAM bits. The content of theRAM bits are connected to logical functions in the device. Changing the content of the RAM bits (high or low)instantly changes the logical functions inside the device.
At power up or after power down is de-asserted the contents of the EEPROM bits are copied to theircorresponding RAM bits. After that the content of RAM can be changed via the SPI bus. When writing toEEPROM commands are detected on the SPI bus the control logic begins writing the content of the RAM bitsinto the corresponding EEPROM bits. This process takes about 50ms. During this time the power supply shouldbe above 3.2V.
Figure 15. Interface Control
The CDCE72010 is designed to support what is referred to as a Universal Input Buffer structure. This type ofbuffer is designed to accept Differential or single ended inputs and it is sensitive enough to act as a LVPECL orLVDS in differential mode and LVCMOS in Single ended mode. With the proper external termination varioustypes of inputs signals can be supported. Those inputs will be discussed in a separate document (applicationNotes).
The CDCE72010 has two internal voltage biasing circuitries. One to set the termination voltage for references(PRI_REF and SEC_REF) and the second biasing circuitry is to set the termination voltage to the VCXO_IN andAUX_IN. This means that we can only have one type of differential signal on PRI_REF and SEC_REF and onlyone type of differential signal on VCXO_IN and AUX_IN.
Figure 16. PRI_REF AND SEC_REF Voltage Biasing Circuitry
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50W
VBB
2
VCXO_IN
AUX_IN
::VCXOBUFSEL
::VCXOACDCSEL
(AC=1,DC=0)
VCXOTERMSEL::
VCXOINVBB::
AUXINVBB::
50W
50W
50W
X
X
X
X
X
Y
AUTOMATIC/MANUAL REFERENCE CLOCK SWITCHING (SMART MUX)
PRI_REF
SEC_REF
Internal
ReferenceClock
VCXOWith
100HzLoop
Auto-Reference
12
1 2 3 4
primary secondary primary
CDCE72010
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Figure 17. VCXO_IN and AUX_IN Voltage Biasing Circuitry
The CDCE72010 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondaryclock input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selectedby the dedicated SPI register. In the manual mode the external REF_SEL signal selects one of the two inputclocks
In the automatic mode the primary clock is selected by default even if both clocks are available. In case theprimary clock is not available or fails, then the input switches to the secondary clock until the primary clock isback. The figure below shows the automatic clock selection.
Figure 18. Automatic Clock Select Timing
In the automatic mode the frequencies of both clock signals has to be similar but may differ by up to 20%. Thereis no limitation placed on the phase relationship between the two inputs.
The clock input circuitry is designed to suppress glitches during switching between the primary and secondaryclock in the manual and automatic mode. This insures that the clock outputs continue to clock reliably when atransition from a clock input occurs.
The phase of the output clock will slowly follow the new input phase. The speed of this transition is determinedby the loop bandwidth. However, there is no phase build-out function supported (like in SONET/SDHapplications).
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PHASE FREQUENCY DETECTOR
PFD Pulse Width Delay (Register 0 RAM Bits [7:6])
MDivider(14Bits)
FeedbackDivider
1,2,3,4,5,6,8,10,12…..80
SmartMux
FeedbackMux
PFDOutto
ChargePump
P Divider
Div1,2
Div1,2
PRI_REF
SEC_REF
R’ Divider
Register11::
DivideFunctionRegister11::
PhaseFunctionRegister11:: 15
::Register10
::Register10
VCXO_IN
AUX_IN
MDelay
NDelay
Register2
RAMBit5:0
14 16 17 18
13
12
8
7910 11
65
NDivider(14Bits)
01
15 16 17 18
14
8
7910 11
65 13
12
3
2 41
0
2221 23 24 2520
19 27
26
CDCE72010
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The main function of the CDCE72010 device is to synchronize a Voltage Control Oscillator (VCO) or a VoltageControl Crystal Oscillator (VCXO) output to a reference clock input. The phase detector compares 2 signals andoutputs the difference between them. It is symbolized by an XOR. The compared signals are derived from theReference clock and from the VCO/VCXO clocks. The Reference clock is divided by the “ R ” Divider (1 or 2) and“ M ” divider (14 Bits) and presented to the PFD. The VCO/VCXO clock is divided by the Feedback Divider (1 to80) and the “ N ” Divider (14 Bits) and presented to the PFD.
Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (R*M) / (P*N)
P is the product of X Divider and FB Divider R and X Divider is set to be divide by 1 or 2
The PFD is a classical style with UP and DOWN signals generating flip-flops and a common reset path. Somespecial functions were implemented:•Bit CP_DIR (register 0 RAM bit < 9> can swap internally the REF- and FB-CLK inputs to the PFD flip-flops.•The reset path can be typically delayed with the bits DELAY_PFD < 1:0> (register 0 RAM bit < 7:6>) from 1.5nsto 6.0ns.
The “ PFD pulse width delay ” gets around the dead zone of the PFD transfer function and reduces phase noiseand reference spurs.
Table 9. PFD Pulse Width Delay
PFD1 PFD0 PFD PULSE WIDTH DELAY
0 0 1.5ns
(1)
0 1 3.0ns1 0 4.5ns1 1 6.0ns
(1) Default
The PFD receives two clocks of the similar frequencies and decides if one is lagging or leading. ThisLagging/Leading signals are feed to the Charge Pump. The Charge Pump in its turn takes the Lagging/Leadingsignals and translate them into current pulses that are feed to the external filter. The Output of the external filteris a DC level that controls the Voltage reference of the VCO/VCXO sitting outside and feeding the CDCE72010at the VCXO Input. The VCO/VCXO drifts its outputs frequency with respect to the voltage applied to its VoltageControl pin. This is how the loop is closed.
Figure 19. Phase Frequency Detection
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Table 10. Feedback Divider SettingsFEEDBACK DIVIDER SETTINGS (REGISTER 11: BITS)
DIVIDER
SETTING11 10 9 8 7 6 5
01000001
10000002
10000013
10000104
10000115
00000004'
00000016
00000108
000001110
00001008'
000010112
000011016
000011120
000100012'
000100118
000101024
000101130
000110016'
000110124'
000111032
000111140
001000020'
001000130'
001001040'
001001150
001010024'
001010136
001011048
001011160
001100028
001100142
001101056
001101170
001110032'
001110148'
001111064
001111180
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PHASE DELAY FOR M AND N
Delay Block in M/N Path
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Table 11. Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment(Register 2 RAM Bits [5:0])
(1)
DLYM2/DLYN2 DLYM1/DLYN1 DLYM0/DLYN0 PHASE OFFSET
0 0 0 0ps
(2)
0 0 1 ± 160ps0 1 0 ± 320ps0 1 1 ± 480ps1 0 0 ± 830ps1 0 1 ± 1130ps1 1 0 ± 1450ps1 1 1 ± 1750ps
(1) If Progr Delay M is set, all Yx outputs are lagging to the Reference Clock according to the value set. If Progr Delay N is set, all Yxoutputs are leading to the Reference Clock according to the value set. Above are typical values at V
CC
= 3.3 V, T
A
= 25 ° C, PECL-outputrelate to Div4 mode.(2) Default
Table 12. Reference Divider M/N 14-Bit (Register 10 RAM Bits [13:0] for M and RAM Bits [27:14] for N)
N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 DIV BY
(1)
0000000 0000000 100000000000001 200000000000010 300000000000011 4•
•
•00000001111111128
(2)
•
•
•1 1 1 1 1 1 1 1 1 1 1 1 0 1 163821 1 1 1 1 1 1 1 1 1 1 1 1 0 163831 1 1 1 1 1 1 1 1 1 1 1 1 1 16384
(1) If the divider value is Q, then the code will be the binary value of (Q - 1).(2) Default
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CHARGE PUMP
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The Charge Pump drives the loop filter that controls the external VCO/VCXO. The Charge pump frequency isdetermined by the PFD frequency since the function of the charge pump is to translate the UP DOWN signals ofthe PFD into current pulses that drives the external filter. The Charge pump current is set by the control vectorICP [3:0]. The error amplifier operates from 0.7V to the V
DD
supply voltage. See the table below for ICP settings.
Table 13. CP, Charge Pump Current (Register 0 RAM Bits [17:14])
TYPICAL CHARGE PUMPICP3 ICP2 ICP1 ICP0
CURRENT
0000 0µA (3-State)0 0 0 1 200 µA0 0 1 0 400 µA0 0 1 1 600 µA0 1 0 0 800 µA0 1 0 1 1.0 mA0 1 1 0 1.2 mA0 1 1 1 1.4 mA1 0 0 0 1.6 mA1 0 0 1 1.8 mA1 0 1 0 2.0 mA1 0 1 1 2.2 mA
(1)
1 1 0 0 2.4 mA1 1 0 1 2.6 mA1 1 1 0 2.8 mA1 1 1 1 3.0 mA
(1) Default
The ‘ Preset Charge-Pump to V
CC_CP
/2 is a useful feature to quickly set the center frequency of the VC(X)O afterPower-up or Reset. The adequate control voltage for the VC(X)O will be provided to the Charge-Pump output byan internal voltage divider of 1K Ω/1K Ωto V
CC_CP
and GND (V
CC_CP
/2).
This feature helps to get the initial frequency accuracy, i.e. required at CPRI (Common Public Radio Interface) orOBSAI (Open Base Station Architecture Initiative).
The Preset Charge-Pump to V
CC_CP
/2 can be set and reset by SPI register.
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p .
V(PFD2)(InternalSignal)
V(PFD1)(InternalSignal)
ChargePumpOutput
CurrentIcp
ChargePumpOutput
CurrentIcp(Inverted)
ReferenceClock After
theNDividerandDelay
ReferenceClock After
theMDividerandDelay
PFDpulsewidthdelayimprovesspurioussuppression.
CDCE72010
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Charge-Pump Current Direction
The direction of the charge-pump (CP) current pulse can be changed by the SPI register settings. It determinesin which direction CP current will regulate (Reference Clock leads to Feedback Clock). Most applications use thepositive CP output current (power-up condition) because of the use of a passive loop filter. The negative CPcurrent is useful when using an active loop filter concept with inverting operational amplifier. The Figure belowshows the internal PFD signal and the corresponding CP current.
Figure 20. Charge Pump
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PLL LOCK FOR ANALOG AND DIGITAL DETECT
t(lockdetect)
SelectedREFatPFD
(clockfedthroughMDivider
andMDelay
VCXO_INatPFD
(clockfedthroughNDivider
andNDelay)
CDCE72010
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...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 supports two PLL Lock indications: the digital lock signal or the analog lock signal. Both signalsindicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition.
The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) andFeedback Clock (VCXO_IN clock) at the PFD (Phase Frequency Detect) are inside a predefined lock detectwindow for a pre-defined number of successive clock cycles.
The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) andFeedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window.
Both, the lock detect window and the number of successive clock cycles are user definable in the SPI registersettings.
Figure 21. PLL Lock
The lock detect window describes the maximum allowed time difference for lock detect between the rising edgeof PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. Therising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lockdetect window, if there is a phase displacement of more than +0.5*t
(lockdetect)
or -0.5*t
(lockdetect)
.
Table 14. Lock-Detect Window (Register 7 RAM Bits [1:0] and Register 9 RAM Bits [7:6])
LOCKW3 LOCKW2 LOCKW1 LOCKW0
PHASE-OFFSET AT PFD-INPUT
(1)[7] [6] [1] [0]
0 0 0 0 1.5 ns1 1 0 1 5.8 ns
(2)
0 0 1 0 15.1 ns0 0 1 1 Reserved0 1 0 0 3.4 ns0 1 0 1 7.7 ns0 1 1 0 17.0 ns0 1 1 1 Reserved1 0 0 0 5.4 ns1 0 0 1 9.7 ns1 0 1 0 19.0 ns1 0 1 1 Reserved1 1 0 0 15.0 ns1 1 0 1 19.3 ns1 1 1 0 28.6 ns1 1 1 1 Reserved
(1) Typical values at V
CC
= 3.3 V, T
A
= 25 ° C(2) Default
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DIGITAL LOCK DETECT
Power_Down
Lock_Out
Lock_In
160kW
5pF
PLL_LOCK
Output
V =0.6V
high CC
V =0.4V
low CC
Lock
t
DigitalLockDetection
Out-of-Lock
VOut
CDCE72010
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Table 15. Number of Successive Lock Events Inside the Lock Detect Window(Register 7 RAM Bits [4:3]) the PLL Lock Signal is Delayed for Number ofFB_CLK Events
NO. OF SUCCESSIVE LOCKLOCKC1 LOCKC0
EVENTS
0010 1 161 0 64
(1)
1 1 256
(1) Default
When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out oflock until a stable lock is detected. A single “ low-to-high ” step can be reached with a wide lock detect windowand high number of successive clock cycles. PLL_LOCK will return to out of lock if just one cycle is outside thelock detect window.
Figure 22. Digital Lock
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Product Folder Link(s): CDCE72010
ANALOG LOCK DETECT
160kW
5pF
110µA
(Lock)
VCC
C
VOut
t
V =1/C*I*t
Out
V =0.55V
high CC
V =0.35V
low CC
Example:
forI=110µA,C=10n,V =3.3Vand
V =V =0.55*V =1.8V
=>t=164µs
CC
high Out CC
Power_Down
110µA
(Out-of-Lock)
Lock_Out
Lock_In
PLL_LOCK
(Output)
FREQUENCY HOLD-OVER MODE
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110 µAcurrent source until logic high-level is reached. Therefore, more time is needed to detect logic high level, butjittering of PLL_LOCK will be suppressed like possible in case of digital lock. The time PLL_LOCK needs toreturn to out of lock depends on the level of V
OUT
, when the current source starts to unload the externalcapacitor.
Figure 23. Analog Lock
The HOLD-Function is a CDCE72010 feature that helps to improve system reliability. The HOLD-Function holdsthe output frequency in case the input reference clock fails or is disrupted. During HOLD, the Charge-Pump isswitched off (3-State) freezing the last valid output frequency. The Hold-Function will be released after a validreference clock is reapplied to the clock input and detected by the CDCE72010. For proper HOLD function, theAnalog PLL-Lock-Detect mode has to be active. The following settings are involved with the HOLD Function:•Lock Detect Window: Defines the window in ns inwhich the Lock is valid. The size is 3.5ns, 8.5ns, 18.5ns.Lock is set if Reference Clock and Feedback Clock are inside this predefined Lock-Detect Window for apre-selected number of successive cycles.•Out-of-Lock: Defines the out-of-lock condition: If the Reference Clock and the Feedback Clock at the PFD areoutside the predefined Lock Detect Window.•Number of Clock Cycles: Defines the number of successive PFD cycles which have to occur inside the lockwindow to set Lock detect. This does not apply for Out-of-Lock condition.•Hold-Function: Selects HOLD-Function (see more details below).•Hold-Trigger: Defines whether the HOLD-Function is always activated or whether it is dependent on the stateof the analog PLL Lock detect output. In the latter case, HOLD is activated if Lock is set (high) andde-activated if Lock is reset (low).•Analog PLL Lock Detect: Analog Lock output charges or discharges an external capacitor with every validLock cycle. The time constant for Lock detect can be set by the value of the capacitor.
The CDCE72010 supports two types of HOLD functions, one external controllable HOLD mode and one internalmode, HOLD.
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EXTERNAL/HOLD FUNCTION
INTERNAL/HOLD FUNCTION
3-State
ChargePump
yes yes
no
PLL
Out-of-Lock
PLL-Lock
OutputSet
no
64PFD
LockCycles
Ref.Clock
isBack
no
no
Start
PLL isout-of-lockifthephase
differenceof ReferenceClock and
FeedbackClock atPFDareoutsidethe
predefinedLock-Detect-Windoworifa
Cycle-Slipoccurs.
FrequencyHold-OverFunctionworksin
combinationwiththe AnalogLock -Detect
Charge-Pumpisswitchedinto 3-State.
PLL hastobeinLOCKtostart
HOLD-Function.
( The AnalogLockoutputisnotresetbythefirstOut-of-
Lockevent. Itstays ‘High’ dependingontheanalogtime
delay ( outputC-load). Thetimedelaymustbelongenough
toguaranteeproperHOLDfunction)
TheCharge-Pumpremainsinto 3-State
untilthe ReferenceClock isback. The 1st
valid ReferenceClock atthePFDreleases
theCharge-Pump.
ThePLL acquire 64 lockcyclestophase
aligntotheinputclock.
CDCE72010
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The Charge Pump can directly be switched into 3-State. This function is also available via SPI register. If logiclow is applied to HOLD pin the Charge Pump will be switched to 3-State. After HOLD pin is released, the chargepump is switched back in to normal operation, with the next valid reference clock cycle at PRI_REF or SEC_REFand the next valid feedback clock cycle at the PFD. During HOLD, all divider and all outputs are at normaloperation.
In Internal HOLD Function or HOLD-Over-Function the PLL has to be in lock to start the HOLD function. Itswitches the Charge Pump in to 3-State when an ‘ out-of-lock ’ event occurs. It leaves the ‘ 3-State Charge Pump ’state when the Reference Clock is back. Then it starts a locking sequence of 64 cycles before it goes back to thebeginning of the HOLD-Over loop.
Figure 24. Frequency Hold Over
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Product Folder Link(s): CDCE72010
OUTPUT DIVIDERS AND PHASE ADJUST
DDDDD
StartDivider
(OUT#DIVSEL#)
(PH#ADJC#)
OutputDivider
CoarsePhase AdjustSelect
Phase AdjustPeriod
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 is designed with individual Output Dividers for Outputs 1 to 8. Output Divider 1 drives Output 1and Output 0 and Output Divider 8 drives Output 8 and Output 9. Each output divider has a bypass function or itis referred to as divide by “ one ” . Since divide by one bypasses the divider block it can address higher operatingfrequencies.
The output divider is designed to address divide by 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40,42, 48, 50, 56, 60, 64, 70 and 80.The output divider includes a coarse phase adjust that shifts the divided clocksignal. The phase adjust resolution is a function of the divide function. The maximum number of phase stepsequals to the divider setting.
If the output is divide by 2, then two phase adjustment settings (0 and 180 degrees) are available. The resolutionof phase adjustment is related to the output divider setting by the following: Phase adjust resolution = (1/OutputDivider settings) X 360 Degrees.
Example: For a 491.52MHz VCXO where one of the outputs of the device is set to divide by 16 for a 30.72MHzdesired output, this will mean that the 30.72MHz clock will have (1/16) X 360 = 22.5 Degrees of phaseadjustment resolution.
Output Divide Select (OUT#DIVSEL#) and Coarse Phase Adjust Select (PH#ADJC#) registers are located inRegister 1 thought 8 for Output 1 thought 8 respectively.
The Phase difference between 2 divider settings on different output can be calculated using the following formulaand referring to the Phase Lag number in the Output Divider Table ( see Table 7 ).
Integer Remainder of [(Phase Lag X - Phase Lag Y)/ Divide X ] as an example if we need to calculate the phasedifference between divide by 4 and divide by 8 with respect to divide by 4 clock.
The Integer Remainder [(28.5 - 0.5)/4] = 0. This means there is 0 Cycle phase delay between Divide by 4 andDivide by 8 with respect to Divide by 4 Clock.
If we need to do the same calculation with respect to Divide by 8 we will have Intger Remainder [(28.5 – 0.5)/8] =0.5 that means that there is 0.5 Cycles between Divide by 4 and divide by 8 with respect to a divide by 8 clock.
Figure 25. Maximum Output Frequency With Phase Alighment
For a complete listing of the coarse phase adjust settings, refer to the "CDCE72010 Coarse Phase Adjust"document.
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Product Folder Link(s): CDCE72010
DEVICE LAYOUT
Onlyonesideofthepinpadsisshown.
Onlytwocapacitorsareillustrated.
TopSideThermalPADLayout
BottomSideThermalPADLayout
Onlytwocapacitorsareillustrated.
CDCE72010
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The CDCE72010 is a high performance device packaged in a QFN-64. The die has all the ground pins boundedto the thermal PAD on the bottom of the package. Therefore it is essential that the connection from the thermalPAD to the ground layers should be low impedance. In addition, the thermal path in a QFN package is via thethermal PAD on the bottom of the package. Therefore, the layout of the PAD is very important and it will affectthe thermal performance as well as the overall performance of the device. The illustration shown providesoptimal performance in terms of thermal issues, inductance and power supply bypassing. The 10 X 10 Filled VIApattern recommended allows for a low inductance connection between the thermal ground pad and the groundplane of the board. This pattern forms a low thermal resistive path for the heat generated by the die to getdissipated through the ground plane and to the exposed bottom side ground pad. It is recommended that soldermask not be used on this bottom side pad to maximize its effectiveness as a thermal heat sink. Therecommended layout drives the thermal conductivity to 22.8 C/W in still air and 13.8 C/W in a 100LFM air flow ifimplemented on a JEDEC compliant test thermal board.
Figure 26. Device Layout
60 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): CDCE72010
DEVICE POWER
0
Power(W)
0
25
50
75
100
125
0 1 2 3 4
Power(W)
DieTemp(C)
JEDEC0LFM25C
JEDEC100LFM25C
RL 0LFM25C
RL 100LFM25C
JEDEC0LFM85C
JEDEC100LFM85C
RL 0LFM85C
RL 100LFM85C
MaxDieTemp
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 is designed as a high performance device, therefore careful attention must be paid to deviceconfiguration with respect to power consumption. Total power consumption of the device can be estimated byadding up the total power consumed by each block in the device.
The Table below describes the blocks used and power consumed per block. The total power of the device canbe calculated by multiplying the number of blocks used by the power consumption per block.
Table 16. Device Power
INTERNAL BLOCK POWER AT 3.3V (Typ) POWER DISSIPATED / BLOCK NUMBER OF BLOCKS / DEVICE
PLL Core and Input and Feedback Circuitries 530mW 1Output Dividers 180mW 8Output Buffers ( LVPECL-HISWING)
(1)
150mW 10Output Buffers (LVDS-HISWING)
(1)
75mW 10Output Buffers (LVCMOS at 122 MHz)
(1)
50mW 20
(1) Output buffers can be a total of 10 LVDS, 10 LVPECL, or 20 LVCMOS.
Figure 27. Die Temperature
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Product Folder Link(s): CDCE72010
LOOP FILTER
VccCP
CDCE72010
C1
C2
R2
R3
C3
Charge
Pump
VCO/VCXO
ClockOut
VccCP
CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
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The CDCE72010 is designed to control an external Voltage Controlled Oscillator (VCO) or a Voltage ControlledCrystal Oscillator (VCXO) and to synchronize the controlled oscillators to the input reference. Controlling theOscillator happens via a DC voltage that is applied to the Voltage control pin. This DC voltage is generated bythe CDCE72010 in the form of AC pulses that get filtered by the external loop filter.
Figure 28. Loop Filter
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Product Folder Link(s): CDCE72010
UNIVERSAL OUTPUT BUFFERS
LVCMOS
LVCMOS
LVPECL
LVDS
Register(0to9)
RAMBits:: 21 22 23 24 25 26 27
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 is designed to drive three types of clock signaling, LVPECL, LVDS, and LVCMOS from each ofthe ten outputs. This super buffer that contains all three drivers is refered to as the Universal Output Buffer. Onlyone driver can be enabled at one time. Each universal output buffer is made from four independent buffers inparallel. When LVPECL mode is selected, only the LVPECL Buffer is enabled and the rest of the buffers are3-stated and in low power mode. When Selecting LVDS, only the LVDS Buffer is enabled and the rest of thebuffers are 3-stated and in low power mode. When LVCMOS mode is selected, both LVCMOS drivers areenabled. One LVCMOS buffer drives the negative side and the other buffer drives the positive pin.
The LVCMOS drivers are driven from the same output divider but have separate control bits. In SPI Mode, bits22, 23, 24, and 25 of Registers 0 to 9 are used to put the LVCMOS buffer in active, inverting, low, or 3-state. InCD Mode, those bits are used for different functions and the LVCMOS buffer can be active when selected or3-state when their not.
Figure 29. Universal Output Buffer
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Output Dividers Synchronization
Reference Clock
REG0<Bit4> VCXOSEL
“1” “0” REG6<Bit5>
DET_START_BYPASS
REG6<Bit2> FB_DETERM_DIV_SEL
“0” Feedback Divider Clock
“1” Divide by 2 Feedback Clock
Any of the Conditions will Produce a Conditional SYNC Start Signal:
1- REG9 <Bit11> INDET_BP is set to “0” & VCXO or AUX_CLK is available
2- REG9<Bit12> PLL_LOCK_BP is set to “0” & we have 1st Lock State
3- REG11<Bit19> PD_PLL is set to “0”& the PLL is ON
4- REG9<Bit13> LOW_FD_FB_EN is set to “1” N Divider Input Frequency above 600KHz
5- Write Activity to the Output Divider (s)
6- REG12<Bit8> Set to 1 ( /RESET Bit is Set to “1”)
7- REG12<Bit7> Set to 1 ( /Power Down Bit is Set to “1”)
/RESET Pin
“0” 1” REG9<Bit10>
STARTBYPASS
Feedback Clock
“0”
“1”
OUTPUT DIVIDERS SYNC SIGNAL
Synchronizing Output Divider SYNC Signal
If the value of the bits described as inverted the function associated with it will be ignored
with respect to the sync start signal generation.
CDCE72010
SCAS858 – JUNE 2008 ......................................................................................................................................................................................................
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The CDCE72010 is a 10 output clock device with 8 output dividers and to insure that all the outputs aresynchronous a synchronization startup circuitry is used. The synchronization circuitry generates a pulse to resetall the dividers in a way, that a predictable synchronous output is generated. The Synchronization signal can begenerated from different sources and can be synchronized to a specific clock. The Block diagram belowillustrates the signal path of the Output Divider Sync Signal. This function is assured up to 500 MHz.
Figure 30. Output Divider Synchronization Block Diagram
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Product Folder Link(s): CDCE72010
POWER UP RESET, POWER DOWN MODE AND RESET OR HOLD
POR
VCC
PDor
Sleep
Reset
or
Hold
ResetSPIInterfaceandRegister12toDefault
Power AllClockingCircuitryDown
-ShutDown All AnalogCircuitry(/PD=0orSleep=0)
-ShutDown AllDigitalCircuitry(/PD=0orSleep=0)
-Disable AllOutputBuffers(/PD=0orSleep=0)
-LoadEEPROMIntoRAMWhenReleased(atRisingEdgeof/PD)
ResetDigitalCircuitry
-Disable AllOutputBuffers(When/RESET=0)
-ResetPLL (LoadWithRAMContentValuesatRisingEdge)
-ResetOutputDividersandPhase AdjustCircuitry(atRisingEdge)
WhenHoldFunctionIs Asserted
-Tri-statetheChargePumpOutputWhen/HOLD=0
HoldFunctionIsDeassertedWhen
-/HOLD=1andWeHaveValidReferenceClock
Reset
Hold
/PD
/Reset_Hold
REG12:
REG11:
REG4:
(ForceSleep/PDand/RESETor/HOLD)
LossofReference
Sleep
11
04
29
12
CDCE72010
www.ti.com
...................................................................................................................................................................................................... SCAS858 – JUNE 2008
The CDCE72010 is designed to address various clock synchronization applications. Some functions can be setto be in automatic and manual mode or some functions can be controlled by software or by the internal circuitry.
Figure 31 below explains the various functionalities of power up reset internal circuitry functionality, power downfunctionality and reset functionality. The hold function shares the same block with Reset and one bit in theEEPROM will select either function.
Figure 31. Powerup, Reset, and Powerdown Block Diagram
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CDCE72010RGCR ACTIVE VQFN RGC 64 2000 TBD Call TI Call TI
CDCE72010RGCT ACTIVE VQFN RGC 64 250 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 23-Jun-2008
Addendum-Page 1
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