Precise and stable Fan out 10TTL load loads/package Electrical Characteristics: VIH_ (High level input voltage) . IIH (High levetinput current) . ViL (Low level input voltage) . . tt (Low level input current . . VOH (High level output voltage) VOL (Low level output voltage) vec (Supply voltage) icc (Supplycurrent)......... Mechanical Specifications: Case: Epoxy filled D.A.P. Leads: Tinned Cu. or equiv. Marking: White epoxy ink Relscreening 10 cycles per method 1010 Cond 8 and 24 hrs. bake per method 1008 Cond B of Mil-Std-883 Integrated circuits per Mil-St TTL input and outputs d-883B delays Reliable hybrid construction No external components required s/tap, 20TTL Operating temperature 55C to 4+125C Storage temperature ~65C to +150C ee eee 2.0 to 5.0V eee eee ee eee 50 A Max. cece eee eee 0.8 V Max. Se ee ee eee -2 ma Max. be eee ee 2.5 V Min. ete eee eee 0.5 V Max. ee eee eee 5.0 V+0.50VDC eee eee 150 ma Max. Input & test conditions are not limiting parameters. All digital delay modules can be operated at conditions other than specified. Since accuracies may be slightly affected, we suggest that the module be evaluated under specific operating conditions. All items comply with applicable portions of Group A and B requirements of Mil-D-23859 a JF Specifications subject to change without notice. deere eS Nominal Delays (in NS) +2 NS or 5% Whichever is Greater Automatic Coll Part Number Total Delay Tap Delay CA601A-101 50 5.0 CA601A-102 75 7.5 CAG01A-103 100 10.0 CA601A-104 150 15.0 CA601A-105 200 20.0 CA 601A-106 250 25.0 CA601A-107 300 30.0 CA601A-108 350 35.0 CA601A-109 400 40.0 CA601A-110 450 45.0 CA601A-1141 500 50.0 CA601A-112 600 60.0 CA601A-113 700 70.0 CA601A-114 800 80.0 CA601A-115 900 90.0 CA601A-116 1000 100.0 Output rise times (TPLH) 4.0 NS max. (0.75 to 2.4 V level). ie 14 PIN DIP Pin numbers for reference onty AXAUTO COIL CAGOTA-XXX DATE CODE No. 1 Pin Index -B800 Max. 6 Equal Spaces Of 100 Ea. 1 1331241151069 8 | DELAY NETWORK GND 7 o___l vec 14 O Test Conditions: 1) All Measurements are made @ 25C 2) VCC is maintained @ 5.0 VDC 3) All measurements are made with no loads on outputs 4) Delays are measured @ 1.5V level 5) Delays & tolerances for leading edges only (TPLH) - falling edges (TPHL) closely matched to TPLH input Conditions: 4) Pulse amplitude: 3.20V 2) Input rise time 3.0 NS (10 to 90%) 3) Pulse width 2 x total delay 4) Duty cycle < 25%