Precision Low Noise, Low Input
Bias Current Operational Amplifiers
OP1177/OP2177/OP4177
Rev. D
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Low offset voltage: 60 μV maximum
Very low offset voltage drift: 0.7 μV/°C maximum
Low input bias current: 2 nA maximum
Low noise: 8 nV/√Hz typical
CMRR, PSRR, and AVO > 120 dB minimum
Low supply current: 400 μA per amplifier
Dual supply operation: ±2.5 V to ±15 V
Unity gain stable
No phase reversal
Inputs internally protected beyond supply voltage
APPLICATIONS
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
PIN CONFIGURATIONS
–IN
+IN
V–
V+
NC
NC
18
OP1177
NC
OUT
NC = NO CONNECT
45
02627-001
1
2
3
4
8
7
6
5
–
IN
V–
+IN
V+
OUT
NC
NC
NC
NC = NO CONNECT
OP1177
02627-002
Figure 1. 8-Lead MSOP (RM-Suffix) Figure 2. 8-Lead SOIC_N (R-Suffix)
–IN A
+IN A
V–
OUT B
+IN B
V+
18
OP2177
OUT A
–IN B
45
02627-003
1
2
3
4
8
7
6
5
–IN A
V–
+IN A
OUT B
–IN B
V+
+IN B
OUT A
OP2177
02627-004
Figure 3. 8-Lead MSOP (RM-Suffix) Figure 4. 8-Lead SOIC_N (R-Suffix)
OUT B 78
+IN B 510
–IN B 69
V+ 411
–IN A 213
+IN A 312
OUT A 114
OUT C
+IN C
–IN C
V–
–IN D
+IN D
OUT D
OP4177
02627-005
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
–IN D
+IN D
V–
OUT D
–IN C
OUT C
+IN C
14
8
1
7
OP4177
02627-006
Figure 5. 14-Lead SOIC_N (R-Suffix) Figure 6. 14-Lead TSSOP (RU-Suffix)
GENERAL DESCRIPTION
The OPx177 family consists of very high precision, single, dual,
and quad amplifiers featuring extremely low offset voltage and
drift, low input bias current, low noise, and low power
consumption. Outputs are stable with capacitive loads of over
1000 pF with no external compensation. Supply current is less
than 500 A per amplifier at 30 V. Internal 500  series resistors
protect the inputs, allowing input signal levels several volts
beyond either supply without phase reversal.
Unlike previous high voltage amplifiers with very low offset
voltages, the OP1177 and OP2177 are available in a tiny
MSOP 8-lead surface-mount package, and the OP4177 is
available in a 14-lead TSSOP. Moreover, specified
performance in the MSOP and the TSSOP is identical to
performance in the SOIC package.
The OPx177 family offers the widest specified temperature
range of any high precision amplifier in surface-mount
packaging. All versions are fully specified for operation from
−40°C to +125°C for the most demanding operating
environments.
Applications for these amplifiers include precision diode
power measurement, voltage and current level setting, and
level detection in optical and wireless transmission
systems. Additional applications include line-powered and
portable instrumentation and controls—thermocouple,
RTD, strain-bridge, and other sensor signal conditioning—
and precision filters.
The OP1177 (single) and the OP2177 (dual) amplifiers are
available in 8lead MSOP and 8lead narrow SOIC packages.
The OP4177 (quad) is available in 14lead TSSOP and 14lead
narrow SOIC packages. MSOP and TSSOP are available in tape
and reel only.
OP1177/OP2177/OP4177
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ................................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Functional Description .................................................................. 14
Total Noise-Including Source Resistors................................... 14
Gain Linearity ............................................................................. 14
Input Overvoltage Protection ................................................... 15
Output Phase Reversal............................................................... 15
Settling Time............................................................................... 15
Overload Recovery Time .......................................................... 15
THD + Noise............................................................................... 16
Capacitive Load Drive ............................................................... 16
Stray Input Capacitance Compensation.................................. 17
Reducing Electromagnetic Interference.................................. 17
Proper Board Layout.................................................................. 18
Difference Amplifiers ................................................................ 18
A High Accuracy Thermocouple Amplifier........................... 19
Low Power Linearized RTD...................................................... 19
Single Operational Amplifier Bridge....................................... 20
Realization of Active Filters .......................................................... 21
Band-Pass KRC or Sallen-Key Filter........................................ 21
Channel Separation.................................................................... 21
References on Noise Dynamics and Flicker Noise ................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 24
REVISION HISTORY
7/06—Rev. C to Rev. D
Changes to Table 4............................................................................ 5
Changes to Figure 51...................................................................... 14
Changes to Figure 52...................................................................... 15
Changes to Figure 54...................................................................... 16
Changes to Figure 58 to Figure 61................................................ 17
Changes to Figure 62 and Figure 63............................................. 18
Changes to Figure 64...................................................................... 19
Changes to Figure 65 and Figure 66............................................. 20
Changes to Figure 67 and Figure 68............................................. 21
Removed SPICE Model Section ................................................... 21
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 24
4/04—Rev. B to Rev. C
Changes to Ordering Guide ............................................................ 4
Changes to TPC 6 ............................................................................. 5
Changes to TPC 26........................................................................... 7
Updated Outline Dimensions....................................................... 17
4/02—Rev. A to Rev. B
Added OP4177.........................................................................Global
Edits to Specifications.......................................................................2
Edits to Electrical Characteristics Headings..................................4
Edits to Ordering Guide ...................................................................4
11/01—Rev. 0 to Rev. A
Edit to Features ..................................................................................1
Edits to TPC 6 ...................................................................................5
7/01—Revision 0: Initial Version
OP1177/OP2177/OP4177
Rev. D | Page 3 of 24
SPECIFICATIONS
VS = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1Max Unit
INPUT CHARACTERISTICS
Offset Voltage
OP1177 VOS 15 60 V
OP2177/OP4177 VOS 15 75 V
OP1177/OP2177 VOS −40°C < TA < +125°C 25 100 V
OP4177 VOS −40°C < TA < +125°C 25 120 V
Input Bias Current IB −40°C < TA < +125°C −2 +0.5 +2 nA
Input Offset Current IOS −40°C < TA < +125°C −1 +0.2 +1 nA
Input Voltage Range −3.5 +3.5 V
Common-Mode Rejection Ratio CMRR VCM = −3.5 V to +3.5 V 120 126 dB
−40°C < TA < +125°C 118 125 dB
Large Signal Voltage Gain AVO R
L = 2 kΩ, VO = –3.5 V to +3.5 V 1000 2000 V/mV
Offset Voltage Drift
OP1177/OP2177 ∆VOS/∆T −40°C < TA < +125°C 0.2 0.7 V/°C
OP4177 ∆VOS/∆T −40°C < TA < +125°C 0.3 0.9 V/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH I
L = 1 mA, −40°C < TA < +125°C +4 +4.1 V
Output Voltage Low VOL I
L = 1 mA, −40°C < TA < +125°C −4.1 −4 V
Output Current IOUT V
DROPOUT < 1.2 V ±10 mA
POWER SUPPLY
Power Supply Rejection Ratio
OP1177 PSRR VS = ±2.5 V to ±15 V 120 130 dB
−40°C < TA < +125°C 115 125 dB
OP2177/OP4177 PSRR VS = ±2.5 V to ±15 V 118 121 dB
−40°C < TA < +125°C 114 120 dB
Supply Current per Amplifier ISY V
O = 0 V 400 500 A
−40°C < TA < +125°C 500 600 A
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 0.7 V/s
Gain Bandwidth Product GBP 1.3 MHz
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.4 V p-p
Voltage Noise Density en f = 1 kHz 7.9 8.5 nV/√Hz
Current Noise Density in f = 1 kHz 0.2 pA/√Hz
MULTIPLE AMPLIFIERS CHANNEL
SEPARATION CS DC 0.01 V/V
f = 100 kHz −120 dB
1 Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as “typical” give unrealistically
low estimates for parameters that can have both positive and negative values.
OP1177/OP2177/OP4177
Rev. D | Page 4 of 24
ELECTRICAL CHARACTERISTICS
VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1Max Unit
INPUT CHARACTERISTICS
Offset Voltage
OP1177 VOS 15 60 V
OP2177/OP4177 VOS 15 75 V
OP1177/OP2177 VOS −40°C < TA < +125°C 25 100 V
OP4177 VOS −40°C < TA < +125°C 25 120 V
Input Bias Current IB −40°C < TA < +125°C −2 +0.5 +2 nA
Input Offset Current IOS −40°C < TA < +125°C −1 +0.2 +1 nA
Input Voltage Range −13.5 +13.5 V
Common-Mode Rejection Ratio CMRR VCM = −13.5 V to +13.5 V,
−40°C < TA < +125°C 120 125 dB
Large Signal Voltage Gain AVO R
L = 2 kΩ, VO = –13.5 V to +13.5 V 1000 3000 V/mV
Offset Voltage Drift
OP1177/OP2177 ∆VOS/∆T −40°C < TA < +125°C 0.2 0.7 V/°C
OP4177 ∆VOS/∆T −40°C < TA < +125°C 0.3 0.9 V/°C
OUTPUT CHARACTERISTICS
Output Voltage High VOH I
L = 1 mA, −40°C < TA < +125°C +14 +14.1 V
Output Voltage Low VOL I
L = 1 mA, −40°C < TA < +125°C −14.1 −14 V
Output Current IOUT V
DROPOUT < 1.2 V ±10 mA
Short-Circuit Current ISC ±35 mA
POWER SUPPLY
Power Supply Rejection Ratio
OP1177 PSRR VS = ±2.5 V to ±15 V 120 130 dB
−40°C < TA < +125°C 115 125 dB
OP2177/OP4177 PSRR VS = ±2.5 V to ±15 V 118 121 dB
−40°C < TA < +125°C 114 120 dB
Supply Current per Amplifier ISY V
O = 0 V 400 500 A
−40°C < TA < +125°C 500 600 A
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ 0.7 V/s
Gain Bandwidth Product GBP 1.3 MHz
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 0.4 V p-p
Voltage Noise Density en f = 1 kHz 7.9 8.5 nV/√Hz
Current Noise Density in f = 1 kHz 0.2 pA/√Hz
MULTIPLE AMPLIFIERS CHANNEL
SEPARATION CS DC 0.01 V/V
f = 100 kHz −120 dB
1 Typical values cover all parts within one standard deviation of the average value. Average values given in many competitor data sheets as “typical” give unrealistically
low estimates for parameters that can have both positive and negative values.
OP1177/OP2177/OP4177
Rev. D | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage 36 V
Input Voltage VS− to VS+
Differential Input Voltage ±Supply Voltage
Storage Temperature Range
R, RM, and RU Packages −65°C to +150°C
Operating Temperature Range
OP1177/OP2177/OP4177 −40°C to +125°C
Junction Temperature Range
R, RM, and RU Packages −65°C to +150°C
Lead Temperature, Soldering (10 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θ
JC Unit
8-Lead MSOP (RM-8)1190 44 °C/W
8-Lead SOIC_N (R-8) 158 43 °C/W
14-Lead SOIC_N (R-14) 120 36 °C/W
14-Lead TSSOP (RU-14) 240 43 °C/W
1 MSOP is only available in tape and reel.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
OP1177/OP2177/OP4177
Rev. D | Page 6 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSETVOLTAGE (µV)
NUMBER OF AMPLIFIERS
45
40
35
30
25
20
15
10
5
–30 –20 –10 0 10 20 30 40
0
50
–40
V
SY
= ±15V
02627-007
Figure 7. Input Offset Voltage Distribution
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
NUMBER OF AMPLIFIERS
80
70
60
50
40
30
20
10
0.15 0.25 0.35 0.45 0.55 0.65
0
90
0.05
V
SY
= ±15V
02627-008
Figure 8. Input Offset Voltage Drift Distribution
INPUT BIAS CURRENT (nA)
NUMBER OF AMPLIFIERS
120
100
80
60
40
20
0.10.20.30.40.50.60.7
0
140
0
V
SY
= ±15V
02627-009
Figure 9. Input Bias Current Distribution
LOAD CURRENT (mA)
ΔOUTPUT VOLTAGE (V)
0.01 0.1 1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
0.001 10
SOURCE
SINK
V
SY
= ±15V
T
A
= 25°C
02627-010
Figure 10. Output Voltage to Supply Rail vs. Load Current
TEMPERATURE (°C)
V
SY
= ±15V
INPUT BIAS CURRENT (nA)
2
1
0
–1
–2
0 50 100
3
–3
–50 150
0
2627-011
Figure 11. Input Bias Current vs. Temperature
FREQUENCY (Hz)
PHASE SHIFT (Degrees)
OPEN-LOOP GAIN (dB)
1M
50
40
30
20
10
0
–10
60
–20
100k 10M
225
180
135
90
45
0
–45
270
–90
GAIN
PHASE
V
SY
= ±15V
C
L
= 0
R
L
=
∞
02627-012
Figure 12. Open-Loop Gain and Phase Shift vs. Frequency
OP1177/OP2177/OP4177
Rev. D | Page 7 of 24
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
10k 100k 1M 10M
100
80
60
40
20
0
–20
–40
–60
120
–80
1k 100M
V
SY
= ±15V
V
IN
= 4mV p-p
C
L
= 0
R
L
=
∞
A
V
= 100
A
V
= 1
A
V
= 10
02627-013
Figure 13. Closed-Loop Gain vs. Frequency
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
1k 10k 100k 1M
450
400
350
300
250
200
150
100
50
100
500
0
VSY = ±15V
VIN = 50mV p-p
A
V
= 10
A
V
= 100
A
V
= 1
0
2627-014
Figure 14. Output Impedance vs. Frequency
TIME (100µs/DIV)
VOLTAGE (1V/DIV)
GND
V
SY
= ±15V
C
L
= 300pF
R
L
= 2kΩ
V
IN
= 4V
A
V
= 1
02627-015
Figure 15. Large Signal Transient Response
TIME (100µs/DIV)
VOLTAGE (100mV/DIV)
GND
VSY = ±15V
CL = 1,000pF
RL = 2kΩ
VIN = 100mV
AV = 1
02627-016
Figure 16. Small Signal Transient Response
CAPACITANCE (pF)
SMALL SIGNAL OVERSHOOT (%)
10 100 1k
1 10k
45
40
35
30
25
20
15
10
5
50
0
+OS
–OS
V
SY
= ±15V
R
L
= 2kΩ
V
IN
= 100mV p-p
02627-017
Figure 17. Small Signal Overshoot vs. Load Capacitance
TIME (10µs/DIV)
+200m
V
0V
–15V
0V
V
SY
= ±15V
R
L
= 10kΩ
A
V
= –100
V
IN
= 200mV
INPUT
OUTPUT
0
2627-018
Figure 18. Positive Overvoltage Recovery
OP1177/OP2177/OP4177
Rev. D | Page 8 of 24
TIME (4µs/DIV)
0V
–
200m
V
0V
15V
V
SY
= ±15V
R
L
= 10kΩ
A
V
= –100
V
IN
= 200mV
INPUT
OUTPUT
0
2627-019
Figure 19. Negative Overvoltage Recovery
FREQUENCY (Hz)
CMRR (dB)
100 1k 10k 100k 1M
120
100
80
60
40
20
140
0
10 10M
V
SY
= ±15V
0
2627-020
Figure 20. CMRR vs. Frequency
FREQUENCY (Hz)
PSRR (dB)
100 1k 10k 100k 1M
120
100
80
60
40
20
140
0
10 10M
V
SY
= ±15V
+PSRR
–PSRR
02627-021
Figure 21. PSRR vs. Frequency
V
NOISE
(0.2µV/DIV)
TIME (1s/DIV)
V
SY
= ±15V
0
2627-022
Figure 22. 0.1 Hz to 10 Hz Input Voltage Noise
FREQUENCY (Hz)
16
14
12
10
8
6
4
18
2
50 100 150 2000 250
V
SY
= ±15V
VOLTAGE NOISE DENSITY (nV/
√
Hz)
02627-023
Figure 23. Voltage Noise Density vs. Frequency
SHORT-CIRCUIT CURRENT (mA)
+I
SC
–I
SC
TEMPERATURE (°C)
30
25
20
15
10
5
0 50 100
35
0
–50 150
V
SY
= ±15V
0
2627-024
Figure 24. Short-Circuit Current vs. Temperature
OP1177/OP2177/OP4177
Rev. D | Page 9 of 24
OUTPUT VOLTAGE SWING (V)
14.40
14.00
14.30
14.05
14.25
14.20
14.15
14.10
14.35
+V
OH
–V
OL
TEMPERATURE (°C)
0 50 100–50 150
V
SY
= ±15V
02627-025
Figure 25. Output Voltage Swing vs. Temperature
TIME FROM POWER SUPPLY TURN-ON (Sec)
ΔOFFSET VOLTAGE (µV)
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
0.5
–0.5
–0.4
20 40 60 80 100 120
01
40
V
SY
= ±15V
02627-026
Figure 26. Warm-Up Drift
INPUT OFFSET VOLTAGE (µV)
0
12
8
4
14
18
2
6
10
16
TEMPERATURE (°C)
V
SY
= ±15V
0 50 100–50 150
02627-027
Figure 27. Input Offset Voltage vs. Temperature
CMRR (dB)
123
127
125
128
129
124
126
130
131
132
133
TEMPERATURE (°C)
VSY = ±15V
0 50 100–50 150
0
2627-028
Figure 28. CMRR vs. Temperature
PSRR (dB)
123
127
125
128
129
124
126
130
131
132
133
TEMPERATURE (°C)
V
SY
= ±15V
0 50 100–50 150
02627-029
Figure 29. PSRR vs. Temperature
INPUT OFFSET VOLTAGE (µV)
NUMBER OF AMPLIFIERS
50
15
0
45
20
10
5
30
25
40
35
V
SY
= ±5V
–40 –30 –20 –10 0 10 20 30 40
0
2627-030
Figure 30. Input Offset Voltage Distribution
OP1177/OP2177/OP4177
Rev. D | Page 10 of 24
ΔOUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
1.4
0.8
0
0.4
0.2
0.6
1.0
1.2
0.01 0.1 1
V
SY
= ±5V
T
A
= 25°C
SINK
SOURCE
0.001 10
02627-031
Figure 31. Output Voltage to Supply Rail vs. Load Current
0
2627-032
FREQUENCY (Hz)
PHASE SHIFT (Degrees)
OPEN-LOOP GAIN (dB)
1M
50
40
30
20
10
0
–10
60
–20
100k 10M
225
180
135
90
45
0
–45
270
–90
GAIN
PHASE
V
SY
= ±5V
C
L
= 0
R
L
=
∞
Figure 32. Open-Loop Gain and Phase Shift vs. Frequency
FREQUENCY (Hz)
CLOSED-LOOP GAIN (dB)
10k 100k 1M 10M
100
80
60
40
20
0
–20
–40
–60
120
–80
1k 100M
V
SY
= ±5V
V
IN
= 4mV p-p
C
L
= 0
R
L
=
∞
A
V
= 100
A
V
= 1
A
V
= 10
0
2627-033
Figure 33. Closed-Loop Gain vs. Frequency
FREQUENCY (Hz)
OUTPUT IMPEDANCE (Ω)
1k 10k 100k
100 1M
450
400
350
300
250
200
150
100
50
500
0
V
SY
= ±5V
V
IN
= 50mV p-p
A
V
= 100 A
V
= 1
A
V
= 10
02627-034
Figure 34. Output Impedance vs. Frequency
TIME (100µs/DIV)
VOLTAGE (1V/DIV)
GND
V
SY
= ±5V
C
L
= 300pF
R
L
= 2kΩ
V
IN
= 1V
A
V
= 1
02627-035
Figure 35. Large Signal Transient Response
TIME (10µs/DIV)
VOLTAGE (50mV/DIV)
GND
V
SY
= ±5V
C
L
= 1,000pF
R
L
= 2kΩ
V
IN
= 100mV
A
V
= 1
02627-036
Figure 36. Small Signal Transient Response
OP1177/OP2177/OP4177
Rev. D | Page 11 of 24
CAPACITANCE (pF)
SMALL SIGNAL OVERSHOOT (%)
10 100 1k
1 10k
45
40
35
30
25
20
15
10
5
50
0
+OS
–OS
V
SY
= ±5V
R
L
= 2kΩ
V
IN
= 100mV
02627-037
Figure 37. Small Signal Overshoot vs. Load Capacitance
TIME (4µs/DIV)
+200mV
0V
–15V
0V
V
SY
= ±5V
R
L
= 10kΩ
A
V
= –100
V
IN
= 200mV
INPUT
OUTPUT
02627-038
Figure 38. Positive Overvoltage Recovery
TIME (4µs/DIV)
0V
–
200m
V
0V
5V
V
SY
= ±5V
R
L
= 10kΩ
A
V
= –100
V
IN
= 200mV
INPUT
OUTPUT
02627-039
Figure 39. Negative Overvoltage Recovery
TIME (200µs/DIV)
VOLTAGE (2V/DIV)
GND
V
S
= ±5V
A
V
= 1
R
L
= 10kΩ
INPUT
OUTPUT
02627-040
Figure 40. No Phase Reversal
FREQUENCY (Hz)
CMRR (dB)
100 1k 10k 100k 1M
120
100
80
60
40
20
140
0
10 10M
V
SY
= ±5V
02627-041
Figure 41. CMRR vs. Frequency
FREQUENCY (Hz)
PSRR (dB)
100 1k 10k 100k 1M
160
120
80
40
200
0
10 10M
V
SY
= ±5V
140
100
60
20
180
+PSRR
–PSRR
02627-042
Figure 42. PSRR vs. Frequency
OP1177/OP2177/OP4177
Rev. D | Page 12 of 24
V
NOISE
(0.2µV/DIV)
TIME (1s/DIV)
V
SY
= ±5V
02627-043
Figure 43. 0.1 Hz to 10 Hz Input Voltage Noise
FREQUENCY (Hz)
16
14
12
10
8
6
4
18
2
50 100 150 2000 250
VSY = ±5V
VOLTAGE NOISE DENSITY (nV/√Hz)
02627-044
Figure 44. Voltage Noise Density vs. Frequency
SHORT-CIRCUIT CURRENT (mA)
+I
SC
–I
SC
TEMPERATURE (°C)
30
25
20
15
10
5
0 50 100
35
0
–50 150
V
SY
= ±5V
02627-045
Figure 45. Short-Circuit Current vs. Temperature
OUTPUT VOLTAGE SWING (V)
4.40
4.00
4.30
4.05
4.25
4.20
4.15
4.10
4.35
+V
OH
–V
OL
TEMPERATURE (°C)
0 50 100–50 150
V
SY
= ±5V
02627-046
Figure 46. Output Voltage Swing vs. Temperature
INPUT OFFSET VOLTAGE (µV)
0
10
5
20
25
15
TEMPERATURE (°C)
V
SY
= ±5V
0 50 100–50 150
02627-047
Figure 47. Input Offset Voltage vs. Temperature
SUPPLY CURRENT (µA)
0
300
200
500
600
400
TEMPERATURE (°C)
0 50 100–50 150
100
V
SY
= ±5V
V
SY
= ±15V
02627-048
Figure 48. Supply Current vs. Temperature
OP1177/OP2177/OP4177
Rev. D | Page 13 of 24
SUPPLY CURRENT (µA)
0
300
200
100
350
450
50
150
250
400
SUPPLY VOLTAGE (V)
5101502025 30 35
T
A
= 25°C
0
2627-049
Figure 49. Supply Current vs. Supply Voltage
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
100 1k 10k 100k
–20
–40
–60
–80
–100
–120
–140
0
–160
10 1M
02627-050
Figure 50. Channel Separation vs. Frequency
OP1177/OP2177/OP4177
Rev. D | Page 14 of 24
FUNCTIONAL DESCRIPTION
The OPx177 series is the fourth generation of Analog Devices,
Inc., industry-standard OP07 amplifier family. OPx177 is a very
high precision, low noise operational amplifier with the highly
desirable combination of extremely low offset voltage and very
low input bias currents. Unlike JFET amplifiers, the low bias
and offset currents are relatively insensitive to ambient
temperatures, even up to 125°C.
For the first time, Analog Devices proprietary process technology
and linear design expertise have produced a high voltage
amplifier with superior performance to the OP07, OP77, and
OP177 in a tiny MSOP 8lead package. Despite its small size, the
OPx177 offers numerous improvements, including low wide-
band noise, very wide input and output voltage range, lower input
bias current, and complete freedom from phase inversion.
OPx177 has the widest specified operating temperature range of
any similar device in a plastic surface-mount package. This is
increasingly important as PC board and overall system sizes
continue to shrink, causing internal system temperatures to rise.
Power consumption is reduced by a factor of four from the
OP177, and bandwidth and slew rate increase by a factor of two.
The low power dissipation and very stable performance vs.
temperature also act to reduce warm-up drift errors to
insignificant levels.
Open-loop gain linearity under heavy loads is superior to
competitive parts, such as the OPA277, improving dc accuracy
and reducing distortion in circuits with high closed-loop gains.
Inputs are internally protected from overvoltage conditions
referenced to either supply rail.
Like any high performance amplifier, maximum performance is
achieved by following appropriate circuit and PC board
guidelines. The following sections provide practical advice on
getting the most out of the OPx177 under a variety of
application conditions.
TOTAL NOISE-INCLUDING SOURCE RESISTORS
The low input current noise and input bias current of the
OPx177 make it useful for circuits with substantial input source
resistance. Input offset voltage increases by less than 1 µV
maximum per 500 Ω of source resistance.
The total noise density of the OPx177 is
()
SS
nn
TOTALn kTRRiee 4
2
2
,++=
where:
en is the input voltage noise density.
in is the input current noise density.
RS is the source resistance at the noninverting terminal.
k is Boltzmann’s constant (1.38 × 10−23 J/K).
T is the ambient temperature in Kelvin (T = 273 + °C).
For RS < 3.9 kΩ, en dominates and
en,TOTAL ≈ en
For 3.9 kΩ < RS < 412 kΩ, voltage noise of the amplifier, current
noise of the amplifier translated through the source resistor, and
thermal noise from the source resistor all contribute to the total
noise.
For RS > 412 kΩ, the current noise dominates and
en,TOTAL ≈ inRS
The total equivalent rms noise over a specific bandwidth is
expressed as
(
)
BWeE TOTALn
n ,
=
where BW is the bandwidth in Hertz.
The preceding analysis is valid for frequencies larger than
50 Hz. When considering lower frequencies, flicker noise (also
known as 1/f noise) must be taken into account.
For a reference on noise calculations, refer to the Band-Pass
KRC or Sallen-Key Filter section.
GAIN LINEARITY
Gain linearity reduces errors in closed-loop configurations. The
straighter the gain curve, the lower the maximum error over the
input signal range is. This is especially true for circuits with
high closed-loop gains.
The OP1177 has excellent gain linearity even with heavy loads,
as shown in Figure 51. Compare its performance to the
OPA277, shown in Figure 52. Both devices are measured under
identical conditions, with RL = 2 kΩ. The OP2177 (dual) has
virtually no distortion at lower voltages. Compared to the
OPA277 at several supply voltages and various loads, OP1177
performance far exceeds that of its counterpart.
(5V/DIV)
OP1177
(10µV/DIV)
V
SY
= ±15V
R
L
= 2kΩ
02627-051
Figure 51. Gain Linearity
OP1177/OP2177/OP4177
Rev. D | Page 15 of 24
(5V/DIV)
OPA277
V
SY
= ±15V
R
L
= 2kΩ
(10µV/DIV)
0
2627-052
Figure 52. Gain Linearity
INPUT OVERVOLTAGE PROTECTION
When their input voltage exceeds the positive or negative
supply voltage, most amplifiers require external resistors to
protect them from damage.
The OPx177 has internal protective circuitry that allows
voltages as high as 2.5 V beyond the supplies to be applied at the
input of either terminal without any harmful effects
Use an additional resistor in series with the inputs if the voltage
exceeds the supplies by more than 2.5 V. The value of the
resistor can be determined from the formula
(
)
mA5
500 ≤
Ω+
−
S
S
IN
R
VV
With the OPx177 low input offset current of <1 nA maximum,
placing a 5 kΩ resistor in series with both inputs adds less than
5 µV to input offset voltage and has a negligible impact on the
overall noise performance of the circuit.
5 kΩ protects the inputs to more than 27 V beyond either
supply. Refer to the THD + Noise section for additional
information on noise vs. source resistance.
OUTPUT PHASE REVERSAL
Phase reversal is defined as a change of polarity in the amplifier
transfer function. Many operational amplifiers exhibit phase
reversal when the voltage applied to the input is greater than the
maximum common-mode voltage. In some instances, this can
cause permanent damage to the amplifier. In feedback loops, it
can result in system lockups or equipment damage. The OPx177
is immune to phase reversal problems even at input voltages
beyond the supplies.
V
SY
=10V
A
V
= 1
TIME (400µs/DIV)
V
IN
V
OUT
VOL
T
AGE (5V/DIV)
02627-053
Figure 53. No Phase Reversal
SETTLING TIME
Settling time is defined as the time it takes an amplifier output
to reach and remain within a percentage of its final value after
application of an input pulse. It is especially important in
measurement and control circuits in which amplifiers buffer
analog-to-digital inputs or digital-to-analog converter outputs.
To minimize settling time in amplifier circuits, use proper
bypassing of power supplies and an appropriate choice of circuit
components. Resistors should be metal film types, because they
have less stray capacitance and inductance than their wire-
wound counterparts. Capacitors should be polystyrene or
polycarbonate types to minimize dielectric absorption.
The leads from the power supply should be kept as short as
possible to minimize capacitance and inductance. The OPx177
has a settling time of about 45 µs to 0.01% (1 mV) with a 10 V
step applied to the input in a noninverting unity gain.
OVERLOAD RECOVERY TIME
Overload recovery is defined as the time it takes the output
voltage of an amplifier to recover from a saturated condition to
its linear response region. A common example is one in which
the output voltage demanded by the circuit’s transfer function
lies beyond the maximum output voltage capability of the
amplifier. A 10 V input applied to an amplifier in a closed-loop
gain of 2 demands an output voltage of 20 V. This is beyond the
output voltage range of the OPx177 when operating at ±15 V
supplies and forces the output into saturation.
Recovery time is important in many applications, particularly
where the operational amplifier must amplify small signals in
the presence of large transient voltages.
OP1177/OP2177/OP4177
Rev. D | Page 16 of 24
OP1177
6
7
2
3
4
V+
V–
R2
100kΩ
V
OUT
10kΩ
R1
1kΩ
+
–
2
00m
V
02627-054
Figure 54. Test Circuit for Overload Recovery Time
Figure 18 shows the positive overload recovery time of the
OP1177. The output recovers in less than 4 µs after being
overdriven by more than 100%.
The negative overload recovery of the OP1177 is 1.4 µs, as seen
in Figure 19.
THD + NOISE
The OPx177 has very low total harmonic distortion. This
indicates excellent gain linearity and makes the OPx177 a great
choice for high closed-loop gain precision circuits.
Figure 55 shows that the OPx177 has approximately
0.00025% distortion in unity gain, the worst-case
configuration for distortion.
FREQUENCY (Hz)
THD + N (%)
100 1k
0.001
0.01
20 6k
0.0001
0.1
02627-055
V
SY
= ±15V
R
L
= 10kΩ
BW = 22kHz
Figure 55. THD + N vs. Frequency
CAPACITIVE LOAD DRIVE
OPx177 is inherently stable at all gains and capable of driving
large capacitive loads without oscillation. With no external
compensation, the OPx177 safely drives capacitive loads up to
1000 pF in any configuration. As with virtually any amplifier,
driving larger capacitive loads in unity gain requires additional
circuitry to assure stability.
In this case, a snubber network is used to prevent oscillation
and reduce the amount of overshoot. A significant advantage of
this method is that it does not reduce the output swing because
the Resistor RS is not inside the feedback loop.
Figure 56 is a scope photograph of the output of the OPx177 in
response to a 400 mV pulse. The load capacitance is 2 nF. The
circuit is configured in positive unity gain, the worst-case
condition for stability.
As shown in Figure 58, placing an R-C network parallel to the
load capacitance (CL) allows the amplifier to drive higher values
of CL without causing oscillation or excessive overshoot.
There is no ringing, and overshoot is reduced from 27% to 5%
using the snubber network.
Optimum values for RS and CS are tabulated in Table 5 for
several capacitive loads, up to 200 nF. Values for other
capacitive loads can be determined experimentally.
Table 5. Optimum Values for Capacitive Loads
CL RS CS
10 nF 20 Ω 0.33 µF
50 nF 30 Ω 6.8 nF
200 nF 200 Ω 0.47 µF
0
GND
VOL
AGE (200mV/DIV)
TIME (10µs/DIV)
VSY = ±5V
RL = 10kΩ
CL = 2nF
0
2627-056
Figure 56. Capacitive Load Drive Without Snubber
GND
VOL
T
AGE (200mV/DIV)
TIME (10µs/DIV)
V
SY
= ±5V
R
L
= 10kΩ
R
S
= 200Ω
C
L
= 2nF
C
S
= 0.47µF
0
2627-057
Figure 57. Capacitive Load Drive with Snubber
OP1177/OP2177/OP4177
Rev. D | Page 17 of 24
OP1177
6
7
2
3
4
V+
V–
VOUT
R
S
+
–
400mV
C
S
C
L
0
2627-058
Figure 58. Snubber Network Configuration
CAUTION: The snubber technique cannot recover the loss of
bandwidth induced by large capacitive loads.
STRAY INPUT CAPACITANCE COMPENSATION
The effective input capacitance in an operational amplifier
circuit (Ct) consists of three components. These are the internal
differential capacitance between the input terminals, the
internal common-mode capacitance of each input to ground,
and the external capacitance including parasitic capacitance. In
the circuit in Figure 59, the closed-loop gain increases as the
signal frequency increases.
The transfer function of the circuit is
()
R1sC
R1
R2
t
++ 1 1
indicating a zero at
()
tt CR2R1R2R1C
R1R2
s / 2
1
π
=
+
=
Depending on the value of R1 and R2, the cutoff frequency of
the closed-loop gain can be well below the crossover frequency.
In this case, the phase margin (Φm) can be severely degraded,
resulting in excessive ringing or even oscillation.
A simple way to overcome this problem is to insert a capacitor
in the feedback path, as shown in Figure 60.
The resulting pole can be positioned to adjust the phase margin.
Setting Cf = (R1/R2) Ct achieves a phase margin of 90°.
R2R1
V1
+
–OP1177
2
3
V
OUT
Ct
02627-059
6
7
4
V+
V–
Figure 59. Stray Input Capacitance
R2R1
V1
+
–OP1177
2
3
V
OUT
Ct
Cf
02627-060
6
7
4
V+
V–
Figure 60. Compensation Using Feedback Capacitor
REDUCING ELECTROMAGNETIC INTERFERENCE
A number of methods can be utilized to reduce the effects of
EMI on amplifier circuits.
In one method, stray signals on either input are coupled to the
opposite input of the amplifier. The result is that the signal is
rejected according to the amplifier’s CMRR.
This is usually achieved by inserting a capacitor between the
inputs of the amplifier, as shown in Figure 61. However, this
method can also cause instability, depending on the value of
capacitance.
R2R1
V1
+
–
OP1177
2
3
V
OUT
C
02627-061
6
7
4
V+
V–
Figure 61. EMI Reduction
Placing a resistor in series with the capacitor (see Figure 62)
increases the dc loop gain and reduces the output error.
Positioning the breakpoint (introduced by R-C) below the
secondary pole of the operational amplifier improves the phase
margin and, therefore, stability.
R can be chosen independently of C for a specific phase margin
according to the formula
()
⎟
⎠
⎞
⎜
⎝
⎛+−= R1
R2
jfa
R2
R
2
1
where:
a is the open-loop gain of the amplifier.
f2 is the frequency at which the phase of a = Φm − 180°.
OP1177/OP2177/OP4177
Rev. D | Page 18 of 24
OP1177
2
3
R
C
R1
R2
V
OUT
V1
+
–
02627-062
6
7
4
V+
V–
Figure 62. Compensation Using Input R-C Network
PROPER BOARD LAYOUT
The OPx177 is a high precision device. To ensure optimum
performance at the PC board level, care must be taken in the
design of the board layout.
To avoid leakage currents, the surface of the board should be
kept clean and free of moisture. Coating the surface creates a
barrier to moisture accumulation and helps reduce parasitic
resistance on the board.
Keeping supply traces short and properly bypassing the power
supplies minimizes power supply disturbances due to output
current variation, such as when driving an ac signal into a heavy
load. Bypass capacitors should be connected as closely as
possible to the device supply pins. Stray capacitances are a
concern at the outputs and the inputs of the amplifier. It is
recommended that signal traces be kept at least 5 mm from
supply lines to minimize coupling.
A variation in temperature across the PC board can cause a
mismatch in the Seebeck voltages at solder joints and other
points where dissimilar metals are in contact, resulting in
thermal voltage errors. To minimize these thermocouple effects,
resistors should be oriented so heat sources warm both ends
equally. Input signal paths should contain matching numbers
and types of components where possible, in order to match the
number and type of thermocouple junctions. For example,
dummy components such as zero value resistors can be used to
match real resistors in the opposite input path. Matching
components should be located in close proximity and should be
oriented in the same manner. Leads should be of equal length
so that thermal conduction is in equilibrium. Heat sources on
the PC board should be kept as far away from amplifier input
circuitry as is practical.
The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and also helps to maintain a constant
temperature across the circuit board.
DIFFERENCE AMPLIFIERS
Difference amplifiers are used in high accuracy circuits to
improve the common-mode rejection ratio (CMRR).
R1
V
1
V
2
R3 = R1 R4 = R1
OP1177
2
3
=
R4
R3
R2
R1
R2
100kΩ
V
OUT
02627-063
6
7
4
V+
V–
Figure 63. Difference Amplifier
In the single instrumentation amplifier (see Figure 63),
where:
R1
R2
R3
R4 =
()
12
OVV
R1
R2
V−=
a mismatch between the ratio R2/R1 and R4/R3 causes the
common-mode rejection ratio to be reduced.
To better understand this effect, consider that, by definition,
CM
DM
A
A
CMRR =
where ADM is the differential gain and ACM is the common-mode
gain.
CM
O
CM
DIFF
O
DM V
V
A
V
V
A and ==
()
21
CM
21
DIFF VVVVVV +=−=
2
1
and
For this circuit to act as a difference amplifier, its output must
be proportional to the differential input signal.
From Figure 63,
21
OV
R4
R3
R1
R2
V
R1
R2
V
1
1
⎥
⎥
⎥
⎥
⎦
⎤
⎢
⎢
⎢
⎢
⎣
⎡
⎟
⎠
⎞
⎜
⎝
⎛+
⎟
⎠
⎞
⎜
⎝
⎛+
+
⎟
⎠
⎞
⎜
⎝
⎛
−=
Arranging terms and combining the equations above yields:
R2R3R4R1
R4R2R3R2R4R1
CMRR 22
2
−
+
+
= (1)
The sensitivity of CMRR with respect to the R1 is obtained
by taking the derivative of CMRR, in Equation 1, with
respect to R1.
OP1177/OP2177/OP4177
Rev. D | Page 19 of 24
⎟
⎠
⎞
⎜
⎝
⎛
−
+
+
−δ
δ
=
δ
δ
R2R3R1R4
R2R3R2R4
R2R3R1R4
R1R4
R1R1
CMRR
22
2
22
()
R1R4
R2R3
R1
CMRR
2
2
1
−
=
δ
δ
Assuming that
R1 ≈ R2 ≈ R3 ≈ R4 ≈ R
and
R(1 − δ) < R1, R2, R3, R4 < R(1 + δ)
the worst-case CMRR error arises when
R1 = R4 = R(1 + δ) and R2 = R3 = R(1 − δ)
Plugging these values into Equation 1 yields
δ
≅2
1
MIN
CMRR
where δ is the tolerance of the resistors.
Lower tolerance value resistors result in higher common-mode
rejection (up to the CMRR of the operational amplifier).
Using 5% tolerance resistors, the highest CMRR that can be
guaranteed is 20 dB. Alternatively, using 0.1% tolerance resistors
results in a common-mode rejection ratio of at least 54 dB
(assuming that the operational amplifier CMRR × 54 dB).
With the CMRR of OPx177 at 120 dB minimum, the resistor
match is the limiting factor in most circuits. A trimming
resistor can be used to further improve resistor matching and
CMRR of the difference amplifier circuit.
A HIGH ACCURACY THERMOCOUPLE AMPLIFIER
A thermocouple consists of two dissimilar metal wires placed in
contact. The dissimilar metals produce a voltage
VTC = α(TJ − TR)
where:
TJ is the temperature at the measurement of the hot junction.
TR is the temperature at the cold junction.
α is the Seebeck coefficient specific to the dissimilar metals used
in the thermocouple.
VTC is the thermocouple voltage. VTC becomes larger with
increasing temperature.
Maximum measurement accuracy requires cold junction
compensation of the thermocouple. To perform the cold
junction compensation, apply a copper wire short across the
terminating junctions (inside the isothermal block) simulating a
0°C point. Adjust the output voltage to zero using the R5
trimming resistor, and remove the copper wire.
The OPx177 is an ideal amplifier for thermocouple circuits
because it has a very low offset voltage, excellent PSRR and
CMRR, and low noise at low frequencies.
It can be used to create a thermocouple circuit with great
linearity. Resistor R1, Resistor R2, and Diode D1, shown in
Figure 64, are mounted in an isothermal block.
V+
7
4
Cu
Cu
TR
TR
D1
D1
ADR293
V
CC
C1
2.2µF
R3
47kΩ
10µF
R2
4.02kΩR8
1kΩ
R7
80.6kΩ
R6
50Ω
R9
200kΩ
0.1µF
10µF
0.1µF
10µF
V–
10µF
R4
50Ω
R5
100Ω
R1
50Ω
ISOTHERMAL
BLOCK
V
TC
T
J
(–)
(+)
6
2
3
OP1177
V
OUT
02627-064
Figure 64. Type K Thermocouple Amplifier Circuit
LOW POWER LINEARIZED RTD
A common application for a single element varying bridge is an
RTD thermometer amplifier, as shown in Figure 65. The
excitation is delivered to the bridge by a 2.5 V reference applied
at the top of the bridge.
RTDs may have thermal resistance as high as 0.5°C to 0.8°C per
mW. In order to minimize errors due to resistor drift, the
current through each leg of the bridge must be kept low. In this
circuit, the amplifier supply current flows through the bridge.
However, at the OPx177 maximum supply current of 600 µA,
the RTD dissipates less than 0.1 mW of power, even at the
highest resistance. Errors due to power dissipation in the bridge
are kept under 0.1°C.
Calibration of the bridge can be made at the minimum value of
temperature to be measured by adjusting RP until the output is zero.
To calibrate the output span, set the full-scale and linearity
potentiometers to midpoint and apply a 500°C temperature to
the sensor or substitute the equivalent 500°C RTD resistance.
Adjust the full-scale potentiometer for a 5 V output. Finally,
apply 250°C or the equivalent RTD resistance and adjust the
linearity potentiometer for 2.5 V output. The circuit achieves
better than ±0.5°C accuracy after adjustment.
OP1177/OP2177/OP4177
Rev. D | Page 20 of 24
0
2627-065
200Ω
500Ω
4.37kΩ
100Ω
100Ω20Ω
4.12kΩ
4.12kΩ
5kΩ
49.9kΩ
ADR421
+15
V
0.1µ
F
V+
100Ω
RTD
1/2
OP2177
7
6
5
1/2
OP2177
1
8
2
3
4
V–
V
OU
T
V
OUT
where δ = ∆R/R is the fractional deviation of the RTD resistance
with respect to the bridge resistance due to the change in
temperature at the RTD.
For δ << 1, the preceding expression becomes
δ
⎥
⎦
⎤
⎢
⎣
⎡⎟
⎠
⎞
⎜
⎝
⎛
+
⎟
⎠
⎞
⎜
⎝
⎛+
⎟
⎠
⎞
⎜
⎝
⎛
=
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
++
δ
⎟
⎠
⎞
⎜
⎝
⎛
≅
REF
REF
O
V
R2
R1
R2
R1
R
R2
R2
R1
R
R1
V
R
R2
V
1
1
With VREF constant, the output voltage is linearly proportional
to δ with a gain factor of
⎥
⎦
⎤
⎢
⎣
⎡⎟
⎠
⎞
⎜
⎝
⎛
+
⎟
⎠
⎞
⎜
⎝
⎛+
⎟
⎠
⎞
⎜
⎝
⎛
R2
R1
R2
R1
R
R2
VREF 1
02627-066
R
R
R
R(1+δ)
ADR421
15V
0.1µ
F
OP1177
6
7
4
2
3
V+
V–
R
F
R
F
V
OUT
Figure 65. Low Power Linearized RTD Circuit
SINGLE OPERATIONAL AMPLIFIER BRIDGE
The low input offset voltage drift of the OP1177 makes it very
effective for bridge amplifier circuits used in RTD signal
conditioning. It is often more economical to use a single bridge
operational amplifier as opposed to an instrumentation amplifier.
In the circuit shown in Figure 66, the output voltage at the
operational amplifier is Figure 66. Single Bridge Amplifier
()
⎥
⎥
⎥
⎥
⎦
⎤
⎢
⎢
⎢
⎢
⎣
⎡
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
δ+
⎟
⎠
⎞
⎜
⎝
⎛++
δ
=
1 1
R2
R1
R
R1
V
R
R2
VREF
O
OP1177/OP2177/OP4177
Rev. D | Page 21 of 24
REALIZATION OF ACTIVE FILTERS
BAND-PASS KRC OR SALLEN-KEY FILTER
The low offset voltage and the high CMRR of the OPx177 make
it an excellent choice for precision filters, such as the band-pass
KRC filter shown in Figure 67. This filter type offers the
capability to tune the gain and the cutoff frequency
independently.
Because the common-mode voltage into the amplifier varies
with the input signal in the KRC filter circuit, a high CMRR is
required to minimize distortion. Also, the low offset voltage of
the OPx177 allows a wider dynamic range when the circuit gain
is chosen to be high.
The circuit of Figure 67 consists of two stages. The first stage is
a simple high-pass filter whose corner frequency (fC) is
C1C2R1R2π2
1 (2)
and whose
R2
R1
KQ = (3)
where K is the dc gain.
Choosing equal capacitor values minimizes the sensitivity and
simplifies Equation 2 to
R1R2
C
π2
1
The value of Q determines the peaking of the gain vs. frequency
(ringing in transient response). Commonly chosen values for Q
are generally near unity.
Setting 2
1
=Q yields minimum gain peaking and minimum
ringing. Determine values for R1 and R2 by using Equation 3.
For ,
2
1
=Q R1/R2 = 2 in the circuit example. Pick R1 = 5 kΩ
and R2 = 10 kΩ for simplicity.
The second stage is a low-pass filter whose corner frequency
can be determined in a similar fashion. For R3 = R4 = R
C4
C3
Q
C4
C3
R
fC2
1
and
2
1
=
π
=
CHANNEL SEPARATION
Multiple amplifiers on a single die are often required to reject
any signals originating from the inputs or outputs of adjacent
channels. OP2177 input and bias circuitry is designed to
prevent feedthrough of signals from one amplifier channel to
the other. As a result, the OP2177 has an impressive channel
separation of greater than −120 dB for frequencies up to
100 kHz and greater than −115 dB for signals up to 1 MHz.
02627-067
C3
680pF
1/2
OP2177
7
8
6
5
4
V+
V–
1/2
OP2177
1
2
3
R2
10kΩ
V1
+
–
R1
20kΩ
C2
10nF
C1
10nF
R3
33kΩ
R4
33kΩ
C4
330pF
V
OUT
Figure 67. Two-Stage, Band-Pass KRC Filter
1
2
3
1/2
OP2177
100Ω
10kΩ
1/2
OP2177
7
8
6
5
4
V+
V–
+
–
0
2627-068
V1
50mV
Figure 68. Channel Separation Test Circuit
REFERENCES ON NOISE DYNAMICS
AND FLICKER NOISE
S. Franco, Design with Operational Amplifiers and Analog
Integrated Circuits. McGraw-Hill, 1998.
Analog Devices, Inc., The Best of Analog Dialogue, 1967 to
1991. Analog Devices, Inc., 1991.
OP1177/OP2177/OP4177
Rev. D | Page 22 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
060506-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 69. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 70. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
OP1177/OP2177/OP4177
Rev. D | Page 23 of 24
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 71. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
4.50
4.40
4.30
14 8
71
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09
8°
0°
0.75
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
OP1177/OP2177/OP4177
Rev. D | Page 24 of 24
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
OP1177AR −40°C to +125°C 8-Lead SOIC_N R-8
OP1177AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
OP1177AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
OP1177ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
OP1177ARZ-REEL1−40°C to +125°C 8-Lead SOIC_N R-8
OP1177ARZ-REEL71−40°C to +125°C 8-Lead SOIC_N R-8
OP1177ARM-R2 −40°C to +125°C 8-Lead MSOP RM-8 AZA
OP1177ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 AZA
OP1177ARMZ-R21−40°C to +125°C 8-Lead MSOP RM-8 AZA#
OP1177ARMZ-REEL1−40°C to +125°C 8-Lead MSOP RM-8 AZA#
OP2177AR −40°C to +125°C 8-Lead SOIC_N R-8
OP2177AR-REEL −40°C to +125°C 8-Lead SOIC_N R-8
OP2177AR-REEL7 −40°C to +125°C 8-Lead SOIC_N R-8
OP2177ARZ1−40°C to +125°C 8-Lead SOIC_N R-8
OP2177ARZ-REEL1−40°C to +125°C 8-Lead SOIC_N R-8
OP2177ARZ-REEL71−40°C to +125°C 8-Lead SOIC_N R-8
OP2177ARM-R2 −40°C to +125°C 8-Lead MSOP RM-8 B2A
OP2177ARM-REEL −40°C to +125°C 8-Lead MSOP RM-8 B2A
OP2177ARMZ-R21−40°C to +125°C 8-Lead MSOP RM-8 B2A#
OP2177ARMZ-REEL1−40°C to +125°C 8-Lead MSOP RM-8 B2A#
OP4177AR −40°C to +125°C 14-Lead SOIC_N R-14
OP4177AR-REEL −40°C to +125°C 14-Lead SOIC_N R-14
OP4177AR-REEL7 −40°C to +125°C 14-Lead SOIC_N R-14
OP4177ARZ1−40°C to +125°C 14-Lead SOIC_N R-14
OP4177ARZ-REEL1−40°C to +125°C 14-Lead SOIC_N R-14
OP4177ARZ-REEL71−40°C to +125°C 14-Lead SOIC_N R-14
OP4177ARU −40°C to +125°C 14-Lead TSSOP RU-14
OP4177ARU-REEL −40°C to +125°C 14-Lead TSSOP RU-14
OP4177ARUZ1−40°C to +125°C 14-Lead TSSOP RU-14
OP4177ARUZ-REEL1−40°C to +125°C 14-Lead TSSOP RU-14
1
Z = Pb-free part; # denotes Pb-free product may be top or bottom marked.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02627-0-7/06(D)