R1RP0404DGE-2PR - Renesas Electronics

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Rev.1.00, Mar.12.2004, page 1 of 11

R1RP0404D Series

4M High Speed SRAM (1-Mword × 4-bit)

REJ03C0116-0100Z

Rev. 1.00

Mar.12.2004

Description

The R1RP0404D is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high speed

access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing

technology. It is most appropriate for the application which requires high speed and high density memory,

such as cache and buffer memory in system. The R1RP0404D is packaged in 400-mil 32-pin SOJ for high

density surface mounting.

Features

• Single 5.0 V supply: 5.0 V ± 10%

• Access time 12 ns (max)

• Completely static memory

 No clock or timing strobe required

• Equal access and cycle times

• Directly TTL compatible

 All inputs and outputs

• Operating current: 130 mA (max)

• TTL standby current: 40 mA (max)

• CMOS standby current : 5 mA (max)

: 1.0 mA (max) (L-version)

• Data retention current: 0.5 mA (max) (L-version)

• Data retention voltage: 2.0 V (min) (L-version)

• Cente r VCC and VSS type pin out

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 2 of 11

Ordering Information

Type No. Access time Package

R1RP0404DGE-2PR 12 ns 400-mil 32-pin plastic SOJ (32P0K)

R1RP0404DGE-2LR 12 ns

Pin Arrangement

CS#

I/O1

I/O2

WE#

A19

A18

A17

A16

A15

OE#

I/O4

I/O3

A14

A13

A12

A11

A10

(Top view)

32-pin SOJ

Pin Description

Pin name Function

A0 to A19 Address input

I/O1 to I/O4 Data input/output

CS# Chip select

OE# Output enable

WE# Write enable

VCC Power supply

VSS Ground

NC No connection

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 3 of 11

Block Diagram

I/O1

I/O4

WE#

Input

data

control

Column I/O

Column decoder

1024-row × 64-column ×

16-block × 4-bit

(4,194,304 bits)

Row

decoder

OE#

CS#

VCC

VSS

A14

A13

A12

A11

A10

A8 A9 A19 A17 A18 A15 A0 A2 A4 A16

(LSB) (MSB)

(LSB)

(MSB)

Internal

voltage

generator

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 4 of 11

Operation Table

CS# OE# WE# Mode VCC current I/O Ref. cycle

H × × Standby ISB, ISB1 High-Z 

L H H Output disable ICC High-Z 

L L H Read ICC D

OUT Read cycle (1) to (3)

L H L Write ICC D

IN Write cycle (1)

L L L Write ICC D

IN Write cycle (2)

Note: H: VIH, L: VIL, ×: VIH or VIL

Absolute Maximum Ratings

Parameter Symbol Value Unit

Supply voltage relative to VSS V

CC −0.5 to +7.0 V

Voltage on any pin relative to VSS V

T −0.5*1 to VCC + 0.5*2 V

Power dissipation PT 1.0 W

Operating temperature Topr 0 to +70 °C

Storage temperature Tstg −55 to +125 °C

Storage temperature under bias Tbias −10 to +85 °C

Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.

2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.

Recommended DC Operating Conditions

(Ta = 0 to +70°C)

Parameter Symbol Min Typ Max Unit

Supply voltage VCC*3 4.5 5.0 5.5 V

SS*4 0 0 0 V

Input voltage VIH 2.2  V

CC + 0.5*2 V

IL −0.5*1  0.8 V

Notes: 1. VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.

2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.

3. The supply voltage with all VCC pins must be on the same level.

4. The supply voltage with all VSS pins must be on the same level.

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 5 of 11

DC Characteristics

(Ta = 0 to +70°C, VCC = 5.0 V ± 10%, VSS = 0 V)

Parameter Symbol Min Max Unit Test conditions

Input leakage current IILII  2 µA VIN = VSS to VCC

Output leakage current IILOI  2 µA VIN = VSS to VCC

Operation power supply current ICC  130 mA Min cycle

CS# = VIL, lOUT = 0 mA

Other inputs = VIH/VIL

Standby power supply current ISB  40 mA Min cycle, CS# = VIH,

Other inputs = VIH/VIL

SB1  5 mA f = 0 MHz

VCC ≥ CS# ≥ VCC − 0.2 V,

(1) 0 V ≤ VIN ≤ 0.2 V or

(2) VCC ≥ VIN ≥ VCC − 0.2 V

*1 1.0*1

Output voltage VOL  0.4 V IOL = 8 mA

OH 2.4  V IOH = −4 mA

Note: 1. This characteristics is guaranteed only for L-version.

Capacitance

(Ta = +25°C, f = 1.0 MHz)

Parameter Symbol Min Max Unit Test conditions

Input capacitance*1 C

IN  6 pF VIN = 0 V

Input/output capacitance*1 C

I/O  8 pF VI/O = 0 V

Note: 1. This parameter is sampled and not 100% tested.

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 6 of 11

AC Characteristics

(Ta = 0 to +70°C, VCC = 5.0 V ± 10%, unless otherwise noted.)

Test Condit ions

• Input pulse levels: 3.0 V/0.0 V

• Input rise and fall time: 3 ns

• Input and output timing reference levels: 1.5 V

• Output load: See figures (Including scope and jig)

OUT

255 Ω

480 Ω

5 V

5 pF

Output load (B)

(for t

CLZ

, t

OLZ

, t

CHZ

, t

OHZ

, t

WHZ

, and t

)

Output load (A)

1.5 V

30 pF

OUT

RL = 50 Ω

Zo = 50 Ω

Read Cycle

R1RP0404D

-2

Parameter Symbol Min Max Unit Notes

Read cycle time tRC 12  ns

Address access time tAA  12 ns

Chip select access time tACS  12 ns

Output enable to output valid tOE  6 ns

Output hold from address change tOH 3  ns

Chip select to output in low-Z tCLZ 3  ns 1

Output enable to output in low-Z tOLZ 0  ns 1

Chip deselect to output in high-Z tCHZ  6 ns 1

Output disable to output in high-Z tOHZ  6 ns 1

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 7 of 11

Write Cycle

R1RP0404D

-2

Parameter Symbol Min Max Unit Notes

Write cycle time tWC 12  ns

Address valid to end of write tAW 8  ns

Chip select to end of write tCW 8  ns 9

Write pulse width tWP 8  ns 8

Address setup time tAS 0  ns 6

Write recovery time tWR 0  ns 7

Data to write time overlap tDW 6  ns

Data hold from write time tDH 0  ns

Write disable to output in low-Z tOW 3  ns 1

Output disable to output in high-Z tOHZ  6 ns 1

Write enable to output in high-Z tWHZ  6 ns 1

Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is

sampled and not 100% tested.

2. Address should be valid prior to or coincident with CS# transition low.

3. WE# and/or CS# must be high during address transition time.

4. If CS# and OE# are low during this period, I/O pins are in the output state. Then, the data input

signals of opposite phase to the outputs must not be applied to them.

5. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#

transition, output remains a high impedance state.

6. tAS is measured from the latest address transition to the later of CS# or WE# going low.

7. tWR is measured from the earlier of CS# or WE# going high to the first address transition.

8. A write occurs during the overlap of a low CS# and a low WE#. A write begins at the latest

transition among CS# going low and WE# going low. A write ends at the earliest transition

among CS# going high and WE# going high. tWP is measured from the beginning of write to the

end of write.

9. tCW is measured from the later of CS# going low to the end of write.

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 8 of 11

Timing Waveforms

Read Timing Waveform (1) (WE# = VIH)

tAA

tACS

tRC

tOE

tCLZ

Valid data

Address

CS#

DOUT

Valid address

High impedance

tOHZ

OE#

tOH

tCHZ

tOLZ

Read Timing Waveform (2) (WE# = VIH, CS# = VIL, OE# = VIL)

Valid data

Address

OUT

Valid address

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 9 of 11

Read Timing Waveform (3) (WE# = VIH, CS# = VIL, OE# = VIL)*2

Valid data

CS#

OUT

High

impedance High

impedance

CLZ

ACS

CHZ

Write Timing Waveform (1) (WE# Controlled)

Address

WE#*

OUT

Valid address

Valid data

CS#*

OHZ

OE#

High impedance*

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 10 of 11

Write Timing Waveform (2) (CS# Controlled)

Address

WE# *3

DOUT

DIN

tWC

tWP

tWR

tCW

tDW tDH

Valid address

tAW

Valid data

tAS

CS# *3

tWHZ tOW

*4*4

High impedance*5

R1RP0404D Series

Rev.1.00, Mar.12.2004, page 11 of 11

Low VCC Data Retention Characteristics

(Ta = 0 to +70°C)

This characteristics is guaranteed only for L-version.

Parameter Symbol Min Max Unit Test conditions

VCC for data retention VDR 2.0  V VCC ≥ CS# ≥ VCC − 0.2 V

(1) 0 V ≤ VIN ≤ 0.2 V or

(2) VCC ≥ VIN ≥ VCC − 0.2 V

Data retention current ICCDR  500 µA VCC = 3 V, VCC ≥ CS# ≥ VCC − 0.2 V

(1) 0 V ≤ VIN ≤ 0.2 V or

(2) VCC ≥ VIN ≥ VCC − 0.2 V

Chip deselect to data

retention time tCDR 0  ns See retention waveform

Operation recovery time tR 5  ms

Low VCC Da ta Retention Timing Waveform

2.2 V

4.5 V

0 V

CS#

CDR

Data retention mode

≥ CS# ≥ V

− 0.2 V

Revision History R1RP0404D Series Data Sheet

Contents of Modification Rev. Date

Page Description

0.01 Oct. 01, 2003  Initial issue

1.00 Mar.12.2004  Deletion of Preliminary

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