_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
19-4822; Rev 0; 7/09
General Description
The MAX3815A cable equalizer automatically provides
compensation for DVI™ and HDMI™ v1.3 cables. It
extends the usable cable distance up to 40 meters
(1.65Gbps) and 35 meters (2.25Gbps). The MAX3815A
is designed to equalize signals encoded in the transition-
minimized differential signaling (TMDS®) format.
The MAX3815A features four CML-differential inputs and
outputs (three data and one clock). It provides a loss-of-
signal (LOS) output that indicates loss-of-clock signal.
The outputs include a disable function. Upon LOS, the
chip is powered down. For direct chip-to-chip communi-
cation, the output drivers can be switched to one-half the
DVI output specification to conserve power and reduce
EMI. The output drive current can also be increased to
allow the use of back termination resistors for improved
signal integrity. Equalization can be automatic or set to
manual control for specific in-cable applications.
The MAX3815A is available in a 7mm x 7mm, 48-pin
TQFP-EP package and operates over a 0°C to +70°C
temperature range.
Applications
Front-Projector HDMI/DVI Inputs
High-Definition Televisions and Displays
HDMI/DVI-D Cable-Extender Modules and Active
Cable Assemblies
LCD Computer Monitors
HDMI 1.3 Deep Color Systems
Features
S Guaranteed Performance to 2.25Gbps (HDMI 1.3),
Improved Jitter Performance at Low Source
Amplitude, and Enhanced Output Driver
S Extends 2.25Gbps TMDS Interface Length
0 to 35 Meters Over HDMI Cable, 24 AWG
0 to 22 Meters Over HDMI Cable, 28 AWG
S Extends 1.65Gbps TMDS Interface Length
0 to 40 Meters Over HDMI Cable, 24 AWG
0 to 28 Meters Over HDMI Cable, 28 AWG
S Compatible with HDTV Resolutions 720p, 1080i,
1080p, and 1080p with 36-Bit Color
S Compatible with Computer Resolutions VGA,
SVGA, XGA, SXGA, UXGA, and WUXGA
S Fully Automatic Equalization, No System Control
Required
S 3.3V Power Supply
S Power Dissipation of 0.6W (typ)
S 7mm x 7mm, 48-Pin TQFP Lead-Free Package
Typical Operating Circuits
Ordering Information
+Denotes a lead(Pb)-free/RoHS compliant package.
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
Typical Operating Circuits continued at end of data sheet.
DVI is a trademark of Digital Display Working Group.
HDMI is a trademark of HDMI Licensing, LLC.
TMDS is a registered trademark of Silicon Image, Inc.
EVALUATION KIT
AVAILABLE
VIDEO SOURCE
UP TO 35m OF HDMI
OR
DVI CABLE
STANDARD LENGTH
DVI-D OR HDMI CABLE
HDMI OR DVI EXTENDER BOX
HDTV
MAX3815A
EQUALIZER
MAX3816A
DDC EXTENDER
PART TEMP RANGE PIN-PACKAGE
MAX3815ACCM+ 0NC to +70NC48 TQFP-EP*
2 ______________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Supply Voltage Range, VCC ................................-0.5V to +4.0V
Voltage Range at Output CML Pins .....................-0.5V to +4.0V
Voltage Range at Input CML Pins, RES, VCC_T,
and GND_T ............................................ -0.5V to (VCC + 0.7V)
Voltage Between Input CML Complementary Pair ........... ±3.3V
Voltage Between Output CML Complementary Pair ........ ±1.4V
Continuous Power Dissipation (TA = +70°C)
48-Pin TQFP (derate 36.2mW/°C above +70°C) ........2896mW
Operating Junction Temperature Range ......... -55°C to +150°C
Storage Temperature Range ............................ -55°C to +150°C
Die Attach Temperature ..................................................+400°C
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.5V, TA = 0°C to +70°C. Typical values are at VCC = +3.3V, external terminations = 50Ω ±1%, MAX3815A in
automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Power-Supply Current ICC Clock present (CLKLOS = HIGH) 210 270 mA
Clock and data absent (CLKLOS = LOW) 12
Supply-Noise Tolerance DC to 500kHz 200 mVP-P
EQUALIZER PERFORMANCE
Residual Output Jitter (Cables
Only) 0.25Gbps to 1.65Gbps
(Notes 1, 2, and 3)
1dB skin-effect loss at 825MHz 0.05
UI
24dB skin-effect loss at 825MHz 0.13 0.21
Residual Output Jitter (Cables
Only) 1.65Gbps to 2.25Gbps
(Notes 1, 2, and 3)
1dB skin-effect loss at 825MHz 0.1
UI
24dB skin-effect loss at 825MHz 0.14 0.28
CID Tolerance 20 Bits
CONTROL AND STATUS
CLKLOS Assert Level
Differential peak-to-peak at EQ input
with max 225MHz clock (see the Typical
Operating Characteristics for more
information)
50 mVP-P
CML INPUTS (CABLE SIDE)
Differential Input-Voltage Swing VID At cable input 800 1000 1200 mVP-P
Common-Mode Input Voltage VCM VCC -
0.4
VCC +
0.1 V
Input Resistance RIN Single-ended 45 50 55 W
CML OUTPUTS (ASIC SIDE)
Differential Output-Voltage Swing VOD
50W load, each side
to VCC
OUTLEVEL = HIGH 800 1000 1200
mVP-P
OUTLEVEL = LOW 500
With back termination as shown in Figure 4,
OUTLEVEL = OPEN 910
Output-Voltage High Single-ended, OUTLEVEL = HIGH VCC mV
Output-Voltage Low Single-ended, OUTLEVEL = HIGH VCC -
600
VCC -
400 mV
Output Voltage During Clock
Absence (CLKLOS = LOW) Single-ended VCC -
10
VCC +
10 mV
_______________________________________________________________________________________ 3
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.5V, TA = 0°C to +70°C. Typical values are at VCC = +3.3V, external terminations = 50Ω ±1%, MAX3815A in
automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25°C, unless otherwise noted.)
Note 1: AC specifications are guaranteed by design and characterization.
Note 2: Cable input swing is 800mV to 1200mV differential peak-to-peak. Residual output jitter is defined as peak-to-peak jitter,
both deterministic plus random, as measured using an oscilloscope histogram with 5000 hits. Source jitter subtracted.
Note 3: Test pattern is a 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros.
Typical Operating Characteristics
(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer
in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.)
SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
MAX3815A toc02
AMBIENT TEMPERATURE (°C)
SUPPLY CURRENT (mA)
605030 402010
160
170
180
190
200
210
220
230
240
250
150
0 70
OUTLEVEL = OPEN, EQCONTROL = VCC,
CLOCK SIGNAL ACTIVE
TMDS SOURCE DC-COUPLED TO MAX3815A
INPUT (NOMINAL AMPLITUDE)
TMDS SOURCE AC-COUPLED TO MAX3815A
INPUT RETURN LOSS vs. FREQUENCY
MAX3815A toc02
FREQUENCY (MHz)
GAIN (dB)
25002000500 1000 1500
-35
-30
-25
-20
-15
-10
-5
0
-40
0 3000
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Common-Mode Output Voltage 50W load, each side to VCC,
OUTLEVEL = HIGH
VCC -
0.25 V
Rise/Fall Time (Note 1) 20% to 80% 80 160 ps
LVTTL CONTROL AND STATUS INTERFACE
LVTTL Input High Voltage VIH 2.0 V
LVTTL Input Low Voltage VIL 0.8 V
LVTTL Input High Current VIH(MIN) < VIN < VCC ±50 µA
LVTTL Input Low Current GND < VIN < VIL(MAX) -100 µA
Open-Collector Output High
Voltage RLOAD ≥ 10kW to VCC 2.4 V
Open-Collector Output Low
Voltage RLOAD ≥ 2kW to VCC 0.4 V
Open-Collector Output Sink
Current 5 mA
OUTLEVEL Input Open-State
Current Tolerance ±5 µA
4 ______________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Typical Operating Characteristics (continued)
(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer
in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.)
SHR is a trademark of DVIGear, Inc.
EQUALIZER INPUT AFTER 100ft OF 26 AWG
CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815A toc03
5ns/div
20mV/div
DATA RATE = 2.25Gbps
30dB CABLE SKIN-EFFECT LOSS AT 1.11GHz
500mV/div
EQUALIZER INPUT EYE AFTER 100ft OF 26 AWG
CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815A toc04
100ps/div
350mV/div
DATA RATE = 2.25Gbps
30dB CABLE SKIN-EFFECT LOSS AT 1.11GHz
EQUALIZER INPUT EYE AFTER 150ft OF 26 AWG
CABLE (TOP) EQUALIZER OUTPUT (BOTTOM)
MAX3815A toc05
300ps/div
350mV/div
DATA RATE = 742.5Mbps
24dB CABLE SKIN-EFFECT LOSS AT 370MHz
TOTAL JITTER vs. DATA RATE
(50m HDMI CABLE)
MAX3815A toc06
DATA RATE (Mbps)
TOTAL JITTER (psP-P)
17501250750
20
40
60
80
100
120
140
160
180
200
0
TOTAL JITTER (UIP-P)
0.1
0.2
0.3
0.4
0.5
0
250 2250
DVIGear SHR™ HDMI CABLE (22 AWG)
PEAK-TO-PEAK JITTER
IN PICOSECONDS
PEAK-TO-PEAK JITTER
IN UNIT INTERVALS
TOTAL JITTER vs. POWER-SUPPLY NOISE
FREQUENCY (DATA RATE = 2.25Gbps)
MAX3815A toc07
FREQUENCY (kHz)
TOTAL JITTER (psP-P)
100010010
110
120
130
140
150
160
170
180
100
1 10,000
NOISE AMPLITUDE: 200mVP-P
DATA THROUGH 50m DVIGear SHR
HDMI CABLE, 22 AWG
_______________________________________________________________________________________ 5
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Typical Operating Characteristics (continued)
(Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer
in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.)
TOTAL JITTER vs. CABLE LENGTH (CARLISLE
INTERCONNECT TECHNOLOGIES TWIN-AX 28 AWG)
MAX3815A toc08
CABLE LENGTH (m)
DETERMINISTIC JITTER (UIP-P)
302010
0.1
0.2
0.3
0.4
0.5
0.6
0
0 40
2.25Gbps
NO EQ
WITH MAX3815A EQ
1.485Mbps
742.5Mbps
TOTAL JITTER vs. SIGNAL AMPLITUDE INPUT
TO CABLE (DATA RATE 2.25Gbps)
MAX3815A toc09
DIFFERENTIAL AMPLITUDE (VP-P)
TOTAL JITTER (psP-P)
1.41.20.6 0.8 1.0
60
70
80
90
100
110
120
130
50
0.4 1.6
50m OF DVIGear SHR HDMI CABLE
WITH 35dB LOSS AT 1.11GHz
EQCONTROL VOLTAGE (RELATIVE TO VCC)
vs. CABLE LENGTH (MANUAL EQ CONTROL)
CABLE LENGTH (m)
EQCONTROL VOLTAGE (V)
2010
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
-0.8
0 30
CABLE IS CARLISLE INTERCONNECT
TECHNOLOGIES TWIN-AX 28 AWG WITH
APPROXIMATELY 1.35dB OF LOSS
PER METER AT 1.11GHz
MAX3815A toc10
RESIDUAL JITTER (psP-P)
0
20
40
60
80
100
120
140
160
180
200
EQCONTROL VOLTAGE
RESIDUAL JITTER
AT 2.25Gbps
LOSS-OF-CLOCK ASSERT THRESHOLD
vs. CABLE LENGTH
MAX3815A toc11
CABLE LENGTH (m)
DIFFERENTIAL CLOCK AMPLITUDE (mVP-P)
302418126
50
100
150
200
250
300
350
0
0 36
CLOCK AMPLITUDE IS AT INPUT OF CABLE
CABLE IS CARLISLE INTERCONNECT
TECHNOLOGIES TWIN-AX, 28 AWG
225MHz CLOCK
FREQUENCY
25MHz CLOCK
FREQUENCY
EQUALIZER OUTPUT EYE AFTER 50m OF 22 AWG
HDMI CABLE (DATA RATE = 2.25Gbps)
MAX3815A toc12
100ps/div
200mV/div
DVIGear SHR HDMI CABLE
6 ______________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Pin Description
PIN NAME FUNCTION
1, 4, 5, 8, 9,
12, 13, 16, 38 VCC Supply Voltage. All pins must be connected to VCC.
2 RX0_IN- Negative Data Input, CML
3 RX0_IN+ Positive Data Input, CML
6 RX1_IN- Negative Data Input, CML
7 RX1_IN+ Positive Data Input, CML
10 RX2_IN- Negative Data Input, CML
11 RX2_IN+ Positive Data Input, CML
14 RXC_IN+ Positive Clock Input, CML
15 RXC_IN- Negative Clock Input, CML
17 EQCONTROL
Equalizer Control. This pin allows the user to control the equalization level of the MAX3815A.
Connect the pin to GND for automatic operation. Set the voltage to VCC - 1V for minimum
equalization, or set the voltage between VCC - 1V and VCC for manual equalization. See the
Applications Information section for more information.
18 CLKLOS Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input
TMDS clock from the cable. Connect pin to VCC through a 4.7kω resistor.
19 N.C. Not Connected. This pin is not internally connected.
20, 23, 24, 25,
28, 29, 32, 33,
36, 37
GND Ground
21 RXC_OUT- Negative Clock Output, CML
22 RXC_OUT+ Positive Clock Output, CML
26 RX2_OUT+ Positive Data Output, CML
27 RX2_OUT- Negative Data Output, CML
30 RX1_OUT+ Positive Data Output, CML
31 RX1_OUT- Negative Data Output, CML
34 RX0_OUT+ Positive Data Output, CML
35 RX0_OUT- Negative Data Output, CML
39 OUTLEVEL
Output-Level Control Input
• HIGH: Standard swing (1000mVP-P differential)
• OPEN: Standard swing (900mVP-P differential) with external 267ω back termination resistor
(see Figure 4)
• LOW: One-half standard swing (500mVP-P differential)
40 OUTON Output-Enable Control Input, LVTTL. This input enables the CML outputs when forced low and
sets a differential logic zero when forced high.
41, 43, 44 VCC_T Reserved. Must be connected to VCC for normal operation.
42 GND_T Reserved. Must be connected to GND for normal operation.
45–48 RES Reserved. Must be left open for normal operation.
— EP Exposed Pad. The exposed pad must be soldered to the circuit-board ground for proper
thermal and electrical operation.
_______________________________________________________________________________________ 7
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Detailed Description
The MAX3815A TMDS equalizer accepts differential
CML input data at rates of 250Mbps up to 2.25Gbps
(individual channel data rate). It automatically adjusts
to skin-effect losses in copper cable. It consists of four
CML input buffers, a loss-of-clock signal detector, three
independent adaptive equalizers, four limiting amplifiers,
and four output buffers (Figure 1).
CML Input Buffers and Output Drivers
The input buffers and the output drivers are implemented
using current-mode logic (CML) (see Figures 4 and 5). The
output drivers are open-collector and can be turned off
with the OUTON pin. The OUTLEVEL pin sets the output
drive current to one of three levels; see the Applications
Information and Pin Description sections for more infor-
mation. For details on interfacing with CML, refer to
Application Note 291: HFAN-01.0: Introduction to LVDS,
PECL, and CML.
Loss-of-Clock Signal Detector
The loss-of-clock signal detector indicates a loss-of-
clock signal at the CLKLOS pin. This is an open-collector
output that must be connected to VCC through a 4.7kω
external pullup. This resistor is required whether or not
the LOS output is used.
Adaptive Equalizer
The three data channels each contain an independent
adaptive equalizer. Each channel analyzes the incom-
ing signal and determines the amount of equalization to
apply.
Limiting Amplifier
The limiting amplifier amplifies the signal from the adap-
tive equalizer and truncates the top and bottom of the
waveform to provide a clean high- and low-level signal
to the output drivers.
Figure 1. Functional Diagram
INPUT
BUFFER
DRIVER
ADAPTIVE
EQ
LIMITING
AMPLIFIER
TERMINATED
3.3V CML
INPUT
BUFFER
DRIVER
ADAPTIVE
EQ
LIMITING
AMPLIFIER
TERMINATED
3.3V CML
INPUT
BUFFER
DRIVER
ADAPTIVE
EQ
LIMITING
AMPLIFIER
TERMINATED
3.3V CML
INPUT
BUFFER
DRIVER
LIMITING
AMPLIFIER
TERMINATED
3.3V CML RXC_OUT+/-
OUTLEVEL
RX2_OUT+/-
RX1_OUT+/-
RX0_OUT+/-
RX0_IN+/-
RX1_IN+/-
RX2_IN+/-
RXC_IN+/-
CLKLOS
EQCONTROL
OUTON
CLOCK LOS
DETECTOR MAX3815A
8 ______________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Applications Information
Typical shielded twisted pair (STP), unshielded twisted
pair (UTP), and twin-ax cables exhibit skin-effect losses,
which attenuate the high-frequency spectrum of a TMDS
signal, eventually causing data errors or even closing
the signal eye altogether given a long enough cable. The
MAX3815A recovers the data and opens the signal eye
through compensating equalization.
The basic TMDS interface is composed of four differential
serial links: three links carry serial data up to 2.25Gbps
each, and the fourth is a one-tenth-rate (0.1x) clock that
operates up to 225MHz. TMDS, as with analog nVGA
links, must handle a variety of resolutions and screen
update rates. The actual range of digital serial rates is
roughly 250Mbps to 2.25Gbps. For applications requir-
ing ultra-high resolutions (e.g., QXGA), a “dual-link” DVI
interface is used and is composed of six data links plus
the clock, requiring two MAX3815A ICs with the clock
going to both ICs. See Figure 2.
The MAX3815A can be used to extend any TMDS inter-
face as used under the following trademarked names:
DVI (digital visual interface), DFP™ (digital flat-panel),
PanelLink, ADC™ (Apple display connector), and HDMI
(high-definition multimedia interface).
Loss-of-Clock Signal (CLKLOS) Output
A loss-of-clock signal is indicated by the CLKLOS out-
put. A low level on CLKLOS indicates that the signal
power on the RXC_IN pins has dropped below a thresh-
old. When there is sufficient input voltage to the channel
(typically greater than 100mVP-P differential), CLKLOS is
high. The CLKLOS output is suitable for indicating prob-
lems with the transmission link caused by, for example,
a broken cable, a defective driver, or a lost connection
to the equalizer. Note that the loss-of-clock circuitry is
sensitive to a DC or AC voltage between the RXC_IN
pins. A DC or AC voltage greater than Q30mV (typical) is
sensed as an active clock signal.
Figure 2. Connection Scheme for MAX3815A in Dual Link
Application
DFP is a trademark of Video Electronics Standards Association (VESA).
ADC is a trademark of Apple Computer, Inc.
Figure 4. Back Termination Circuit
Figure 3. Simplified CLKLOS Output Circuit Schematic
D0
D1
D2
D3
D4
D5
D0
D1
D2
D3
D4
D5
CLK CLK
MAX3815A
MAX3815A
MAX3815A
RX_OUT-
267Ω
50Ω
+3.3V
50Ω
RX_OUT+
12.5mA
HDM/DVI
RECEIVER
VCC
VCC
CLKLOS
TO CHIP POWER-
CONTROL CIRCUITRY
4.7kΩ
MAX3815A
_______________________________________________________________________________________ 9
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
The loss-of-clock circuitry powers down the part when-
ever there is an absence of a clock signal. This mutes
the output and reduces power consumption to 83mW
whenever the input signal is removed. During power-
down, the MAX3815A’s TMDS output pins go to a high-
impedance state.
The CLKLOS is an open-collector output that requires a
resistive pullup to VCC for operation. The pullup resistor
range is 1kω to 10kω (see Figure 3).
Output Level Control (OUTLEVEL) Input
The OUTLEVEL pin is a three-state input that allows the
user to select between three output settings. Forcing this
pin high results in the standard output signal level with
no back terminations; leaving the pin open results in a
standard output swing with 267ω differential back termi-
nation resistors. Forcing this pin low results in one-half
standard output signal level.
Using Back Termination
Using back termination resistance improves signal integ-
rity through absorption of reflections. It also shifts the sin-
gle-ended output voltage high (VH) and low (VL). Table 1
shows the output voltages when using the MAX3815A in
each of its three output configurations.
Equalizer Control (EQCONTROL) Input
The EQCONTROL pin allows the user to control the
equalization in one of two ways: forcing the pin to ground
sets the equalizer in automatic equalization mode,
and forcing a voltage between VCC - 1V to VCC allows
manual control of the equalization level. Set to VCC for
maximum boost (long cable). Set to VCC - 1V for mini-
mum boost (short cable).
Interface Models
Figure 5. Simplified Input Circuit Schematic
Figure 6. Simplified Output Circuit Schematic
Table 1. Output Settings and Swings
VCC
RX_IN+/-
50Ω
MAX3815A
MAX3815A
RX_OUT-
PWRDWN 0 1
RX_OUT+
10mA OUTLEVEL = HIGH
12.5mA OUTLEVEL = OPEN
5mA OUTLEVEL = LOW
TRANSIENT
SUPRESSOR
CLAMP
OUTLEVEL BACK TERMINATION DIFFERENTIAL
SWING (mVP-P)
SINGLE-ENDED HIGH
(VH)
SINGLE-ENDED LOW
(VL)
High Open 1000 VCC VCC - 500mV
Open 267I910 VCC - 85mV VCC - 540mV
Low Open 500 VCC VCC - 250mV
10 _____________________________________________________________________________________
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Output On (OUTON) Input
The OUTON pin is an LVTTL input. Force the pin low to
enable the outputs. Force the pin high to set a differen-
tial zero on the outputs, irrespective of the signal at the
inputs.
Cable Selection
TMDS performance is heavily dependent on cable quality.
Deterministic jitter (DJ) can be caused by differential-to-
common-mode conversion (or vice versa) within a twisted
pair (STP or UTP), usually a result of cable twist or dielectric
imbalance. Refer to Application Note 3353: HFAN-04.5.4:
‘Jitter Happens’ when a Twisted Pair is Unbalanced and
Application Note 4218: Unbalanced Twisted Pairs Can
Give You the Jitters! for more information.
Layout Considerations
The data and clock inputs are the most critical paths for
the MAX3815A and great care should be taken to mini-
mize discontinuities on these transmission lines between
the connector and the IC. Here are some suggestions for
maximizing the performance of the MAX3815A:
• The data and clock inputs should be wired directly
between the cable connector and IC without stubs.
• Place supply filter capacitors close to the MAX3815A
inputs to provide a low inductance path for supply
return currents.
• Input and output data channel designations are only
a guide. Polarity assignments can be swapped and
channel paths can be interchanged.
• An uninterrupted ground plane should be positioned
beneath the high-speed I/Os.
• Ground-path vias should be placed close to the input/
output connectors to allow a low inductance return
current path.
• Maintain 100Ω differential transmission line impedance
into and out of the MAX3815A.
• Use good high-frequency layout techniques and
multilayer boards with an uninterrupted ground plane
to minimize EMI and crosstalk. Refer to Application
Note 3854: MAX3815: Interfacing to the MAX3815
DVI/HDMI Cable Equalizer and the EV kit data sheet,
MAX3815AEVKIT-HDMI.
Exposed-Pad Package
The exposed pad on the 48-pin TQFP-EP provides a very
low thermal resistance path for heat removal from the
IC. The pad is also electrical ground on the MAX3815A
and must be soldered to the circuit board ground
for proper thermal and electrical performance. Refer
to Maxim Application Note 862: HFAN-08.1: Thermal
Considerations of QFN and Other Exposed-Paddle
Packages for additional information.
Chip Information
PROCESS: SiGe BiPOLAR
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
Figure 7. Cable Reach
TYPICAL MAX3815A CABLE REACH
(DATA RATE = 2.25Gbps)
WIRE GAUGE (AWG)
CABLE LENGTH (m)
2426
10
20
30
40
50
60
0
28 22
TYPICAL LIMIT OF CABLE
WITH EQ AT 2.25Gbps
TYPICAL LIMIT OF CABLE
WITHOUT EQ AT 2.25Gbps
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 TQFP-EP C48E+8 21-0065
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 11
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX3815A
TMDS Digital Video Equalizer for
HDMI/DVI Cables
Pin Configuration
Typical Operating Circuits (continued)
RGB/HV
ADC/SYNC
TMDS
DESERIALIZER
SELECT
IMAGE
SCALER AND
PROCESSOR
PANEL
INTERFACE
TIMING AND
DRIVERS
LCD,
DLP,
OR
LCOS
VGA INPUT
DVI-D INPUT
DVI-D CABLE UP
TO 35m OR 120ft
(24 AWG STP)
LAPTOP
VIDEO PROJECTOR
EQUALIZER
MAX3815A
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
VCC
RX0_IN-
RX0_IN+
VCC
VCC
RX1_IN-
RX1_IN+
VCC
VCC
RX2_IN-
RX2_IN+
VCC
RES
RES
RES
RES
VCC_T
VCC_T
GND_T
VCC_T
OUTLEVEL
VCC
GND
GND
RX0_OUT-
RX0_OUT+
GND
GND
RX1_OUT-
RX1_OUT+
GND
GND
RX2_OUT-
RX2_OUT+
GND
VCC
RXC_IN+
RXC_IN-
VCC
EQCONTROL
GND
RXC_OUT-
RXC_OUT+
GND
GND
CLKLOS
N.C.
OUTON
TOP VIEW
*EP
*EXPOSED PAD.
TQFP
+
MAX3815A
