VAC
TSNS
LM3447
FLT1
FLT2
BIAS
HOLD
AUX
VCC
FF
INV
COMP
GATE
ISNS
GND
+
–
+
–
LM3447
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SNOSC65 A –APRIL 2012–REVISED MAY 2012
Phase Dimmable, Primary Side Power Regulated PFC Flyback Controller for LED Lighting
Check for Samples: LM3447
1FEATURES DESCRIPTION
The LM3447 is a versatile power factor correction
• Integrated Phase Angle Decode (PFC) controller designed to meet the performance
– Leading and Trailing Edge Compatible requirements of residential and commercial phase-cut
– Over 50:1 Dimming Range dimmer compatible LED lamp drivers. The device
incorporates a phase decoder circuit and an
• Power Factor Correction with Low Total adjustable hold current circuit to provide smooth,
Harmonic Distortion flicker free dimming operation. A proprietary primary
• Primary Side Control Using Input Voltage side control technique based on input voltage
Feedforward Technique feedforward is used to regulate the input power
• Input Power Regulation Scheme with Improved drawn by the LED driver and to achieve line
regulation over a wide range of input voltage. Valley
Line Regulation switching operation is implemented to minimize
• Constant Power Operation of LEDs to switching loss and reduce EMI. An internal thermal
Compensate for Forward Voltage Variations foldback circuit is provided to protects the LEDs from
Over Temperature and Lifetime damage based on the temperature sensed by a
• Fixed Frequency Discontinuous Conduction single external NTC resistor. Additional features
Mode Operation include LED open circuit and short circuit protection,
cycle-by-cycle FET over-current protection, burst
• Valley Switching Operation to Achieve High mode fault operation using an internal 812ms fault
Efficiency and Low EMI timer and internal thermal shutdown.
• Efficient TRIAC Hold Current Management The LM3447 is ideal for implementing dimmable,
• Thermal Foldback Function for LED Protection isolated single stage LED lamp drivers where
• LED Open Circuit and Short Circuit Protection simplicity, low-component count and small solution
size are of primary importance. This device is
APPLICATIONS currently available in a TSSOP 14-pin package.
• Dimmable A19, R20, PAR30/38 LED Lamps
• Recessed LED Downlights and Pendant Lights
• Industrial and Commercial Solid State Lighting
TYPICAL APPLICATION DIAGRAM
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TEMPERATURE ORDERABLE DEVICE TRANSPORT
RANGE PACKAGE(2) PINS PACKAGE DRAWING QUANTITY
NUMBER MEDIA
(TJ)
LM3447MT Tube 94
–40°C to 125°C TSSOP 14 MTC14 LM3447MTE Tape and Reel 250
LM3447MTX Tape and Reel 2500
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS(1)
All voltages are with respect to GND, –40°C < TJ= TA< 125°C, all currents are positive into and negative out of the specified
terminal (unless otherwise noted) VALUE UNIT
MIN MAX
Supply voltage VCC(2) –0.3 22 V
HOLD(3) –0.3 22 V
Input voltage range VAC(4) –0.3 6 V
TSNS, FLT1, FLT2, FF, INV, COMP, ISNS, AUX –0.3 6 V
Output voltage range GATE(2) (Pulse < 20ns) –1.5 19 V
Continuous input current IBIAS(4) 10 mA
Junction temperature TJ(5) 165 °C
Storage temperature range(5) TSTG –65 150 °C
Lead temperature Soldering, 10s 260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VCC is internally limited to approximately 18.9V. See ELECTRICAL CHARACTERISTICS table.
(3) HOLD current is limited by the internal power dissipation of the device.
(4) Voltage on VAC and BIAS is internally clamped. The clamp level varies with operating conditions. In normal use, VAC and BIAS are
current fed with the voltage internally limited.
(5) Maximum junction temperature is internally limited.
PACKAGE DISSIPATION RATINGS(1) (2)
θJA, THERMAL IMPEDANCE JUNCTION TA= 25°C TA= 70°C TA= 85°C
PACKAGE TO AMBIENT,NO AIRFLOW POWER RATING POWER RATING POWER RATING
(°C/W) (mW) (mW) (mW)
TSSOP–14 (MTC) 155(1) 645(3) 355(3) 258(3)
(1) Tested per JEDEC EIA/JESD51-1. Thermal resistance is a function of board construction and layout. Air flow reduces thermal
resistance. This number is included only as a general guideline; see TI document (SPRA953) device Package Thermal Metrics.
(2) Thermal resistance to the circuit board is lower. Measured with standard single-sided PCB construction. Board temperature, TB,
measured approximately 1 cm from the lead to board interface. This number is provided only as a general guideline.
(3) Maximum junction temperature, TJ, equal to 125°C
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SNOSC65 A –APRIL 2012–REVISED MAY 2012
RECOMMENDED OPERATING CONDITIONS(1)
over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT
VCC Input Voltage 7.5 14 17.5 V
IBIAS BIAS current from a high impedance source 500 μA
IVAC VAC current from a high impedance source 500 μA
TJOperating junction temperature –40 25 125 °C
(1) For specified performance limits and associated test conditions, see the Electrical Characteristics table.
ELECTROSTATIC DISCHARGE (ESD) PROTECTION MAX UNIT
Human Body Model (HBM) 2 kV
Field Induced Charged Device Model (FICDM) 750 V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified –40°C < TJ= TA< 125°C, VCC = 14V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V, SP
IVAC = 100μA, IBIAS = 100μA, CVCC = 10μF, CCOMP = 0.047μF, RHLD = 10kΩ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (VCC)
Rising threshold 9.5 10.5 11.5 V
VCC(UVLO) Falling threshold 6.8 7.5 8.3 V
Hysteresis 3 V
Rising threshold 17.7 18.89 20.1 V
VCC(OVP) Falling threshold 17.5 18.72 19.9 V
Hysteresis 175 mV
Startup current VCC = 6.7V, VINV = 0 V 180 μA
IVCC Standby current VINV = 1.75V, VAUX = 1 V 1.6 mA
Switching current CGATE = 1 nF 3.3 mA
INPUT VOLTAGE FEEDFORWARD and ANGLE DETECTION (VAC, FF)
VAC(CLAMP) VAC clamp voltage 1.24 V
IVAC(ANGLE) Dimmer angle detect threshold Sweep IVAC 66 μA
IVAC(HOLD) HOLD FET turn-on threshold Sweep IVAC, VFLT2 = 0 V 95 μA
IFF Feedforward source current VGATE = VCC, IVAC = 100 µA 10 μA
DIMMING DECODER CIRCUIT (FLT1, FLT2)
FLT1(HIGH) FLT1 voltage high FLT1 open 1.67 1.75 1.83 V
FLT2(MIN) Minimum dimming decode voltage VFLT2 falling 263 290 315 mV
G(DECODE) Decode gain, VINV/VFLT2 0.877
FLT2HOLD(EN) HOLD circuit enable threshold VFLT2 falling 1 V
FLT2HOLD(DIS) HOLD circuit disable threshold VFLT2 rising 1.2 V
HOLD CIRCUIT (HOLD)
RDS(ON) HOLD MOSFET on-resistance IVAC = 50 μA, VFLT2 = 1 V 24 Ω
PRE-REGULATOR GATE BIAS CIRCUIT (BIAS)
BIAS(HIGH) BIAS high voltage clamp VCC < VCC(UVLO) 16.1 17.7 19.3 V
BIAS(LOW) BIAS low voltage clamp VCC > VCC(UVLO) 12.3 13.5 14.7 V
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LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise specified –40°C < TJ= TA< 125°C, VCC = 14V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V, SP
IVAC = 100μA, IBIAS = 100μA, CVCC = 10μF, CCOMP = 0.047μF, RHLD = 10kΩ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT SENSE COMPARATOR (ISNS)
ISNS(TH) Current limit threshold 239 275 305 mV
RISNS(LEB) ISNS pull down impedance 1.13 kΩ
tISNS(LEB) Leading edge blanking time 170 ns
ERROR AMPLIFIER (INV, COMP)
VREF Reference voltage VFLT2 = 1.5 V, VTSNS = 1.75 V 0.95 1 1.05 V
IINV(BIAS) Input bias current VINV = VREF 45 nA
GMTransconductance VCOMP = VREF 100 μmho
Current source capacity VINV = 0 V 77 104 μA
ICOMP Current sink capacity VINV = 2V 50 77 μA
COMP(LOW) Minimum PWM ramp voltage IVAC = 110 μA, VINV = 1 V 280 mV
D(MAX) Maximum duty cycle IVAC = 110 μA, VINV = 0 V 76.5%
VALLEY DETECT CIRCUIT (AUX)
AUX(OVP) Overvoltage protection VAUX rising 1.67 1.75 1.83 V
tAUX(LEB) AUX leading edge blanking 1.84 μs
IAUX(SOURCE) AUX source current VAUX = –0.3 V 207 μA
tAUX(TO) Valley detect timeout VAUX = 1 V 4 μs
PWM OSCILLATOR AND FAULT TIMER
tOSC Oscillator period 13.9 14.5 15.1 μs
tFAULT Fault timer 812 ms
THERMAL FOLDBACK (TSNS)
TSNS(OC) Open circuit voltage 1.67 1.75 1.83 V
TSNS(TH) Thermal foldback threshold VTSNS falling 0.955 1 1.045 V
RTSNS(1) Internal pull-up resistor TJ= 25°C 7.09 7.88 8.67 kΩ
THERMAL SHUTDOWN
TSD(TH) (2) Thermal shutdown temperature 165 °C
TSD(HYS)(2) Thermal shutdown hysteresis 25 °C
(1) Resistance varies with junction temperature and has typical temperature coefficient of 25ppm/°C.
(2) Device performance at or near thermal shutdown temperature is not specified or assured.
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13
Input Voltage
Sense
and
Feedforward
Control
1
5
FET
Turn-on
Logic
Angle
Detection Circuit 3
11
Internal
Regulators
VCC
UVLO / OVP
Thermal
Shutdown
10
UVLO
OVP
DISABLE
S Q
QR
9LEB
+
275mV
14
UVLO
13.5V
4.2V
Angle
Decoding
Circuit
4
Reference
Generator
2Thermal
Foldback
1.75V
7.88k
+
+
6
7
PWM
Comparator
Error
Amplifier
Triggered
Ramp
Generator
2.5V
280mV
Fault
Timer
VREF
12
3.5V
1.75V
Valley Detection
Circuit
8
LEB +
1.75V AUX OVP
Comparator
Logic
and
Control
VAC
FF
FLT2
TSNS
INV
COMP
AUX
HOLD
FLT1
VCC
GATE
ISNS
BIAS
GND
ENHOLD
Hold Enable
OVP
ENHOLD
Hold Enable
ENHOLD
Hold Enable
LM3447
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SNOSC65 A –APRIL 2012–REVISED MAY 2012
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
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1
2
3
4 11
10
9
8
5
6
7
12
13
14
VAC
TSNS
FLT1
FLT2
FF
INV
COMP GND
ISNS
GATE
VCC
AUX
HOLD
BIAS
TSSOP-14 PACKAGE
(Top View)
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
PIN CONFIGURATION
PIN FUNCTIONS
NO. NAME I/O DESCRIPTION
The current at this pin sets the input power level during normal operation. Connect through a resistor to
1 VAC I rectified input line voltage.
2 TSNS I To implement thermal foldback, connect this pin to an external negative temperature coefficient (NTC) resistor.
This pin is the output of angle sense comparator. Connect a series resistor from this pin to a capacitor to
3 FLT1 O ground to establish the low pass filter bandwidth.
Connect this pin to the output of low pass filter from FLT1 pin to enable dimming. This pin is an input to the
4 FLT2 I internal dim decoder circuitry. For non-dimming applications connect this pin to TSNS.
Connect a parallel resistor and capacitor from this pin to ground to filter twice the line frequency ripple. This is
5 FF O the output of the input voltage feedforward circuitry.
This pin is the input of the internal Gm error amplifier. To implement primary side power regulation, connect this
6 INV I to the FF. To implement secondary side current regulation, connect this pin to the output of opto-isolator circuit.
Output of the Gm error amplifier. Connect a capacitor to ground set desired integral loop compensation
7 COMP I/O bandwidth.
8 GND Ground return
Connect to the source of the switching MOSEFT and a resistor ground to sense transistor current. Overcurrent
9 ISNS I protection is engaged when the voltage exceeds 275mV threshold.
10 GATE O This output provides the gate drive for the power switching MOSEFT.
This is the input to the internal pre-regulator. Connect a bypass capacitor to ground. This pin enables and
11 VCC disables general functions of the LM3447 using the UVLO feature. Device enters overvoltage protection mode
when the voltage is >18.9V.
This pin is used to sense the auxiliary winding voltage and perform valley switching operation. Overvoltage
12 AUX I protection is engaged when the voltage exceeds the threshold of 1.75V during off time.
Connect to a holding resistor from the drain of the pre-regulator to this pin. The pin draws current during the
13 HOLD zero crossings of the rectified input line voltage.
Connect to external pre-regulator transistor to enable startup. When VCC is below UVLO threshold the pin is
14 BIAS clamped to 17.7V. After VCC crosses UVLO threshold the pin is clamped to 13.5V.
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93.4
93.8
94.2
94.6
95
95.4
95.8
96.2
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
IVAC(HOLD) (µA)
G006
−55
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
50 100 150 200 250 300 350 400 450 500 550
IVAC (µA)
IFF (µA)
G007
0
0.5
1
1.5
2
2.5
3
3.5
4
0 2 4 6 8 10 12 14 16 18 20
VCC (V)
Bias Current (mA)
VCC Rising
VCC Falling
G004
64.4
64.8
65.2
65.6
66
66.4
66.8
67.2
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
IVAC(ANGLE) (µA)
G005
5
6
7
8
9
10
11
12
13
−40 −25 −10 5 20 35 50 65 80 95 110 125
UVLO Rising
UVLO Falling
Temperature (°C)
VCC (V)
G001
18.5
18.6
18.7
18.8
18.9
19
19.1
19.2
−40 −25 −10 5 20 35 50 65 80 95 110 125
OVP Rising
OVP Falling
Temperature (°C)
VCC (V)
G002
LM3447
www.ti.com
SNOSC65 A –APRIL 2012–REVISED MAY 2012
TYPICAL CHARACTERISTICS
Unless otherwise stated, –40°C ≤TA= TJ≤+125°C, VVCC = 14 V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V,
IVAC = 100 μA, IBIAS = 100μA, CVCC = 10 μF, CCOMP = 0.047 μF
Figure 1. VCC UVLO vs. Junction Temperature Figure 2. VCC OVP vs. Junction Temperature
Figure 3. Operational IVCC vs. Figure 4. Dimmer Angle Detect Threshold Current vs.
VCC Voltage Junction Temperature
Figure 5. Hold MOSFET Turn-on Threshold Current vs. Figure 6. Feedforward Source Current (IFF) vs. VAC Current
(IVAC)
Junction Temperature
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14.4
14.45
14.5
14.55
14.6
14.65
14.7
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
tOSC (µs)
G012
1.746
1.747
1.748
1.749
1.75
1.751
1.752
1.753
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
TSNS(OC) (V)
G013
0.996
0.997
0.998
0.999
1.000
1.001
1.002
1.003
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
VREF (V)
G010
1.746
1.747
1.748
1.749
1.75
1.751
1.752
1.753
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
AUX(OVP) (V)
G011
12
13
14
15
16
17
18
19
20
−40 −25 −10 5 20 35 50 65 80 95 110 125
BIAS High
BIAS Low
Temperature (°C)
VBIAS (V)
G008
274.2
274.4
274.6
274.8
275
275.2
275.4
275.6
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
ISNS(TH) (mV)
G009
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated, –40°C ≤TA= TJ≤+125°C, VVCC = 14 V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V,
IVAC = 100 μA, IBIAS = 100μA, CVCC = 10 μF, CCOMP = 0.047 μF
Figure 7. BIAS Clamp Voltage vs. Figure 8. Current Limit Threshold vs.
Junction Temperature Junction Temperature
Figure 9. VREF vs. Junction Temperature Figure 10. AUX OVP vs. Junction Temperature
Figure 11. Oscillator Period vs. Figure 12. TSNS Open Circuit Voltage vs.
Junction Temperature Junction Temperature
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−10.02
−10.015
−10.01
−10.005
−10
−9.995
−9.99
−9.985
−9.98
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
Feedforward Source Current (µA)
G018
9.6
9.635
9.67
9.705
9.74
9.775
9.81
9.845
9.88
9.915
9.95
9.985
10.02
10.055
10.09
10.125
10.16
10.195
10.23
10.265
10.3
9.6
9.635
9.67
9.705
9.74
9.775
9.81
9.845
9.88
9.915
9.95
9.985
10.02
10.055
10.09
10.125
10.16
10.195
10.23
10.265
10.3
0
3
6
9
12
15
18
Feedforward Source Current (µA)
Number of Units
G017
80
85
90
95
100
105
110
115
120
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
GM (µmho)
G016
0.998
0.9985
0.999
0.9995
1
1.0005
1.001
1.0015
1.002
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
TSNS(TH) (V)
G014
7.82
7.84
7.86
7.88
7.9
7.92
7.94
7.96
7.98
−40 −25 −10 5 20 35 50 65 80 95 110 125
Temperature (°C)
RTSNS (kΩ)
G015
LM3447
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SNOSC65 A –APRIL 2012–REVISED MAY 2012
TYPICAL CHARACTERISTICS (continued)
Unless otherwise stated, –40°C ≤TA= TJ≤+125°C, VVCC = 14 V, VTSNS = 1.75V, VFLT2 = 1.75V, VAUX = 0.5V, VINV = 0V,
IVAC = 100 μA, IBIAS = 100μA, CVCC = 10 μF, CCOMP = 0.047 μF
Figure 13. Thermal Foldback Thershold vs. Figure 14. TSNS Internal Pull-up Resistor vs.
Junction Temperature Junction Temperature
Figure 15. GMvs. Junction Temperature Figure 16. Feedforward Source Current (IFF) Variation
(IVAC=100µA, Temperautre = 25°C)
Figure 17. Feedforward Source Current (IFF) vs.
Junction Temperature
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VAC
TSNS
LM3447
FLT1
FLT2
BIAS
HOLD
AUX
VCC
FF
INV
COMP
GATE
ISNS
GND
+
–
+
–
RAC
CPFC
CFLT RFLT
RFF
RNTC
CFF
CCOMP
RBS
RHLD1
RHLD2
CVCC
RSN
RAUX1
RAUX2
QPASS
QSW
CBULK
RO
PRI SEC
NPNS
NA
AUX
CY1
n:1
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
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Figure 18. Typical Primary Side Power Regulated Flyback LED Driver
APPLICATION INFORMATION
DESCRIPTION
LM3447 is an AC-DC power factor correction (PFC) controller for phase-cut dimmer compatible LED lighting
applications. The device incorporates an innovative primary side input power regulation technique for controlling
the LED light output over a wide input AC voltage and ambient temperature range. Operating LEDs with constant
power allows the controller to compensates for the LED forward voltage variations caused by temperature
modulation and LED aging. This also provides improved lamp lumen output maintenance and higher luminous
efficacy.
Smooth, flicker free LED dimming is performed by varying the power regulation set-point based on the dimmer
phase angle. The device includes internal angle detection and decoding circuitry to accurately interpret the phase
angle from a forward phase (leading edge) and reverse phase (trailing edge) based dimmers Power factor
correction (PFC) with low input current total harmonic distortion (THD) is maintained by forcing discontinuous
conduction mode (DCM) using a trimmed internal oscillator and valley detect circuitry.
These features, along with LED open circuit and short circuit protection, LED thermal foldback and cycle-by-cycle
FET overcurrent protection, make the LM3447 an ideal device for implementing a compact single stage isolated
Flyback AC-DC LED driver for 5–30W power output range. In addition, it is also possible to configure LM3447
with minor modifications to control SEPIC and Cúk based dimmable AC-DC PFC LED drivers. In this datasheet,
a discussion of the LM3447 functionality is presented using a typical Flyback LED driver circuit, as shown in
Figure 18.
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VREC
VBIAS
VCOMP
VCC
VOUT
VGATE
xxxxxxx
xxxxxxx
t0t1t2t3t4time
10.5V
7.5V
17.7V
13.5V
+
±
14
11
VCC
UVLO
8
LM3447
13.5V
4.2V
BIAS
VCC
GNDUVLO
AUX
NA
RBS
QPASS
RHLD1
CPFC
DZBS
RDAMP
CVCC
PRI
NP
Rectified AC Line VREC(t)
+10
7COMP GATE
PWM
CCOMP
(a) (b)
LM3447
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SNOSC65 A –APRIL 2012–REVISED MAY 2012
VCC BIAS SUPPLY AND START-UP
Figure 19. (a) Bias Circuit and (b) Typical Startup Waveforms
The LM3447 is designed to achieve instant turn-on using an external linear regulator circuit, shown in Figure 19
(a). The start-up sequence is internally controlled by the BIAS voltage and VCC undervoltage lockout (UVLO)
circuit and is illustrated in Figure 19 (b). The BIAS input is a low current voltage clamp circuit that provides a
reference to the linear pass transistor, QPASS. The clamp circuit current is set by connecting resistor, RBS,
between the input rectified AC voltage, VREC and BIAS. When power is applied, the BIAS voltage set to 17.7V
and the capacitor, CVCC is rapidly charged by transistor QPASS. Resistor RHLD1 is used to limit the maximum
allowable current, based on the safe operating area (SOA) rating of the transistor. The LM3447 starts operating
when VCC exceeds the UVLO rising threshold of 10.5V, after which the BIAS voltage is reduced to 13.5V. The
GATE drive output is enabled when the COMP voltage exceeds the minimum internal PWM ramp threshold of
280mV. As the output voltage, VOUT, increases, the bootstrap circuit based on an auxiliary winding of the
transformer is energized and begins delivering power to the device. At any time, if VCC falls below 7.5V the
device enters a UVLO state forcing BIAS to step back to 17.7V to initiate a new start-up sequence. The switching
of BIAS voltage between two thresholds, 17.7V to 13.5V, is performed in association with a large VCC UVLO
hysteresis of 3V to allow for a larger variation in auxiliary output voltage.
The key waveforms illustrating the bias circuit operation and start-up sequence under dimming are shown in
Figure 20. The impact of phase-cut dimming on BIAS, VOUT and VCC behavior is highlighted. The chopping of
the input voltage by an external dimmer causes the output voltage, VOUT, to vary along with LED current. As VCC
voltage tracks the output voltage, VOUT, it too fluctuates based on the dimming command. At low dimming levels,
UVLO is engaged as VCC falls below 7.5V and the BIAS switches to 17.7V, initiating a start-up sequence. The
BIAS behavior interacts with the external dimmer circuit, causing the device to enter into a re-start condition,
where VCC fluctuates between UVLO high and low thresholds. With this mode of operation, the LM3447 is
capable of providing quick response to any changes in the dimming command. In the case where the external
dimmer is switched off, VCC is discharged and all of the device operation is ceased. A new start-up cycle is
initiated, when the dimmer is switched on and the device responds in the manner illustrated in Figure 19 (b).
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LM3447
11
VCC
OVP
8
LM3447
VCC
GND
AUX
NA
RDAMP
CVCC
10
GATE
S Q
Q
R
FAULT
TIMER
(812ms)
LOGIC & CONTROL
VREC
VBIAS
VCC
10.5V
7.5V
17.7V
13.5V
VOUT
t1t2t3t4timet5
t0
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
Figure 20. Typical Waveforms and Start-up Sequence Under Dimming Conditions
The value of capacitor CVCC is critical design parameter as it determines VCC ripple voltage during dimming
operation. A X7R ceramic capacitor with value ranging from 22μF to 47μF and 25V voltage rating is
recommended for CVCC as trade-off between size and performance in space constraint applications. At low
dimming levels, large VCC voltage ripple and QPASS threshold voltage variations can intefere with smooth
dimming performance. An external zener doide, DZBS, can be placed in series with BIAS to boost VCC voltage
and eliminate any observable dimming discontinuities. A low power zener diode ( 200mW) with reverse
breakdown voltage ranging from 1.8V to 4.5V is recommended for most dimming application.
VCC OVERVOLTAGE PROTECTION
Figure 21. VCC Overvoltage Protection Circuit
The LM3447 has a built-in overvoltage protection (OVP) mode to protect VCC from exceeding its ABS MAX
rating under fault conditions. The VCC voltage is monitored by a comparator with a rising threshold of 18.9V and
175mV of hysteresis. Upon detecting an overvoltage condition, GATE is pulled low for duration of 812ms,
determined by the internal fault timer. On clearance of the fault, the timer is disabled and normal device
operation resumes. An optional damping resistor, RDAMP in series with the auxiliary winding can be used to
prevent transformer leakage current from peak charging CVCC and false triggering the OVP circuit. Based on the
magnitude of leakage inductance a resistor of 10Ωto 47Ωshould provide proper damping.
12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: LM3447
.
OUT FLY IN
P = η P
,
2 2 2 2
IN(PK) S IN(RMS) IN(RMS) M
IN(AVG) e 2
M e S
M
2S
V D T V V 2L1
P = = = ; R =
4 L R D T
2L
D T
æ ö
ç ÷
ç ÷
è ø
L L
T T
2 2 2 2
IN (PK) S 2
IN (AVG) in in
L L M L
0 0
V D T
2 2 1 2
P = v (t) i (t)dt = sin ( t)dt;
T T 2 L T
´
ò ò p
,
S
2in
in P S
TM
v (t)
1
i (t) = Average (I ) = D T
2 L
in IN(PK)
L
2
v (t) = V sin( t),
T
p
in
REC
P(PK) S S
M M
v (t)
v (t)
I = DT = DT , for
L L
VREC
IP
IIN(AC)
TL2TL
t
t
t
IP
IS
VSW
DTSD2TSTS2TS3TS
IS(PK)
IP(PK)
t
t
t
(a) Over line period, TL(b) Over switching period, TS
LM3447
www.ti.com
SNOSC65 A –APRIL 2012–REVISED MAY 2012
POWER FACTOR CORRECTION
Figure 22. DCM Flyback PFC Waveforms
Power factor correction is performed by operating the Flyback converter in discontinuous conduction mode
(DCM). In this mode, the peak primary current, IP(PK) is given by
(1)
(2)
where vIN(t) is the input voltage, vREC = ||vin|| is the rectified input voltage, LMis the transformer magnetizing
inductance referred to the primary winding, D is the duty cycle, TSis the switching period and TLis the line
period. For a fixed switching frequency controller, if duty cycle D, is held constant over a line cycle, then the peak
primary current, IP(PK), varies in proportion to input voltage, vIN(t), as shown in Figure 22 (a). The resulting input
current, IIN, is obtained by averaging the area under primary current, IP, shown in Figure 22 (b),
(3)
is sinusoidal and in-phase with input voltage, vIN(t). As a result, the DCM Flyback converter behaves much like a
resistor and exhibits a power factor close to unity.
The input power, PIN(AVG) drawn by the Flyback PFC is derived by averaging the product of input voltage, vin(t)
and input current, iin(t), over half line cycle TL/2,
(4)
(5)
The low frequency behavior of the DCM Flyback is defined by an effective resistance, Re. The expression for
average input power is given by Equation 5 and is based on Reand the input RMS voltage VIN(RMS). For a single
stage Flyback PFC driver, the output power, POUT, delivered to the LED load is a function of the converter
efficiency, ηFLY, and is given by
(6)
The average LED current through the string with forward voltage drop VLED = VOUT is
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM3447
FF FF REF
AC M IN S
R G V
=
R 4 L P f
p
VAC
LM3447
VCC
FF
INV
COMP
GATE
+
–INPUT
FEEDFORWARD
IFF = IVAC / 10
INTERNAL
REGULATORS
+
REFERENCE
GENERATOR
+
CTRL
RAMP
PWM
RAC
RFF
CFF
CCOMP
CVCC
RSN
QSW
PRI
NP
LOGIC
&
CONTROL
S Q
QR
VAL
VAL
Rectified AC LineVREC(t)
LM
GND
,
2
OUT (AVG) IN (AVG) IN (RM S)
LED (AVG ) FLY F LY
OUT OUT OUT e
P P V
I = = η = η
V V V R
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
(7)
The LED current will have a ripple component varying at twice line frequency due to the PFC operation. The
magnitude of the ripple component is based on the energy storage capacitor connected in parallel with the LED
string at the output of Flyback PFC. In typical application, a low voltage aluminum electrolytic bulk capacitor is
used as an energy storage device and is connected across the LED string to limit the ripple current within an
acceptable range.
INPUT POWER REGULATION AND INPUT VOLTAGE FEEDFORWARD CONTROL
Using the LM3447, it is possible to regulate the LED current by implementing a control scheme using the duty
cycle, D, as the control variable. The duty cycle is generated using an internal GM error-amplifier and a fixed
frequency, triggered ramp generator, as shown in Figure 23. This technique should not be confused with other
current mode control schemes where switch current, ISW, is used for control.
With the LM3447, LED current can be directly controlled using a series sense resistor and a conventional closed-
loop feedback control scheme. Typically, for systems that need galvanic isolation between primary and
secondary sides of the transformer, feedback control is complicated and expensive as it requires an additional
signal processing amplifier and an opto-isolator. For improved luminous efficacy and simplicity, the LM3447
incorporates an innovative primary side input power regulation scheme based on input voltage feedforward
control techniques. By commanding input power, the DCM Flyback PFC output is matched with the LED load
characteristics to achieve indirect control of LED string current. The feedforward loop, consisting of input voltage
sensing circuitry, the GMerror amplifier and PWM comparator, is able to reject any input voltage disturbance by
adjusting the duty cycle, thus achieving tight line regulation.
Figure 23. Feedforward Control Circuit
The reference power level, PIN, for the LM3447, is set choosing resistors, RFF and RAC, based on the
magnetizing inductance, LM, the internal reference voltage, VREF, the switching frequency, fSand the feedforward
gain, GFF, such that
(8)
The feedforward gain, GFF = IVAC/IFF = 10 and internal reference voltage VREF = 1 V.
14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: LM3447
LM3447
AUX
VCC
GATE
RAUX1
RAUX2
QSW
NA
AUX
IAUX
IAUX
VALLEY
DETECTION
4s
TIMER
+LEB
1.84s
1.75V
CONTROL
&
LOGIC
812ms
FAULT
TIMER
OVP
RAMP
14.5s
VAL RAMP
+1V
FLT2
ENHOLD
RAMP VAL
VAL
VSW
IP
VAUX
VRAMP
t
t
t
t
tTS2TS
(a) (b)
,
FF
FF
1
C2 (10 Hz 12 Hz)R
³
-p
,
R EF
M2
IN S
OUT REC (PK,MIN )
V
L
1 1
4P +
nV V
£
æ ö
ç ÷
ç ÷
è ø
f
LM3447
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SNOSC65 A –APRIL 2012–REVISED MAY 2012
For the above relationship to be valid and for PFC, it is necessary to ensure that the energy in the magnetizing
inductor, LM, is reset every switching cycle and the power stage operates in DCM for the reference power level,
PIN, over the entire range of input voltages. Based on this constraint, the transformer magnetizing inductor should
be chosen as
(9)
where n is the transformer primary to secondary turns-ratio, VOUT = VLED is the LED string voltage and
VREC(PK,MIN) is the minimum peak rectified input voltage. For the LM3447 internal circuit implementation, shown in
Figure 23, the reference voltage, VREF = 1V and the feedforward gain, GFF = 10. To ensure a robust design and
to reject manufacturing variations, a margin of 2% to 10% should be provided when designing the transformer for
magnetizing inductance calculated using Equation 9.
A small capacitor, CFF is connected in parallel with the resistor RFF, to create a low pass filter that can attenuate
twice the line frequency component from the sensed input voltage. It is recommended to set the filter pole
frequency between 10–12Hz to provide 20dB attenuation, such that
(10)
Slow integral compensation is achieved by placing a compensation capacitor CCOMP at the output of the GM
amplifier. A capacitor value ranging from 4.7μF to 10μF is recommended to achieve a low bandwidth loop of 1Hz
to 10Hz, based on the power level and transient response.
AUX CIRCUIT AND VALLEY DETECT
Figure 24. (a) AUX Circuit; (b) Valley Switching Waveforms
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 15
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VFLT 2
VRAMP
VSW
VGATE
time
1.2V
1V
TS= TRAMP + 0.5TOSC TS= TRAMP
ENHOLD
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
Valley switching is implemented by connecting the transformer auxiliary winding to the AUX input of LM3447
through a resistor divider network, RAUX1 and RAUX2, as shown in Figure 24 (a). The valley level is detected by
monitoring the current sourced out of the AUX pin when the voltage at the auxiliary winding of the transformer is
negative with respect to the GND node. The voltage at this node is clamped at approximately 100mV by the
internal circuitry to protect the device during negative voltage excursions of the auxiliary winding. The waveforms
in Figure 24(b) illustrate the sequence of events that have to occur for the LM3447 to initiate a new switching
cycle.
An internal 14.5μs timer is started at the same time as the switching FET (QSW) is turned on. This 14.5μs timer,
set by the internal ramp rise time, is used to set the maximum frequency. After this timer expires the switching
FET (QSW) is allowed to turn back on if a valley is detected (VAL) or the 4µs (tAUX(TO)) catch timer expires. The
catch timer starts immediately after the Ramp signal drops and sets the lowest operating frequency.
The particular valley (1st, 2nd …) in the ringing waveform, where the switch is enabled is a function of the input
voltage and varies over the half line cycle. As a result, the AUX circuit shows increased sensitivity where the
valley detect signal, VAL, overlaps the Ramp period. Here, the switching point is observed to randomly jump
between two adjacent valleys, causing a discrete change in the switching period. Such perturbations in switching
frequency cause the switching ripple component of the input current to increase and interfere with phase
dimming performance. Therefore, valley switching is disabled and hard switching operation with fixed Ramp
period is initiated on detection of external phase dimmers, as shown in Figure 25. The valley switching operation
is controlled by the FLT2 input. The operation is disabled when the VFLT2 falls below 1V and is enabled again
when it rises above 1.2V. A 200mV hysteresis is provided for noise immunity.
A second function of AUX pin is to program the output overvoltage protection or open-LED detection feature. The
output voltage is monitored by sampling the voltage at the auxiliary winding. The voltage is sampled after a fixed
delay of 1.84μs, from the falling edge of the GATE drive signal. The leading edge blanking circuit helps reject the
voltage transients caused by the leakage energy of the transformer thus preventing false tripping of OVP. The
fault condition is detected when the AUX voltage exceeds the internal threshold, VAUX(OVP) (1.75V). In the case of
an overvoltage fault, the switch is turned off for 812ms before attempting to restart the circuit. During this fault
period, the compensation capacitor (CCOMP) is discharged, and the control loop is disabled. When the fault is
cleared, the 812ms fault timer is disengaged and the control loop is activated to resume normal operation.
Figure 25. Waveforms Illustrating Valley Switching Enable and Disable Sequence
The sizing of resistor RAUX1 and RAUX2 govern the AUX circuit behavior. Resistor RAUX1 is also used to limit the
maximum source current from the AUX pin to 200μA and is based on the maximum input voltage and the
transformer primary to auxiliary turns-ratio;
16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: LM3447
,
IN S
P(PK,MAX)
M
P T
I = 2 L
+
±
+
±CBULK
RO
PRI SEC
NPNS
n:1
ISNS
GND
CPFC
QSW
GATE
LEB
+
275mV
S Q
QR 170ns
812ms
FAULT
TIMER
LOGIC
&
CONTROL
RSN
LM3447
OCP
,
AUX2 AUX1
AOUT(OVP)
S
1.75
R = R
NV 1.75
N
æ ö
ç ÷
ç ÷
ç ÷
-
ç ÷
è ø
R EC(PK ,MAX)
A
AUX1 -6
P
V
N
R = ,
N200 10´
LM3447
www.ti.com
SNOSC65 A –APRIL 2012–REVISED MAY 2012
(11)
Resistor RAUX2 is then selected to set the desired output overvoltage threshold, VOUT(OVP) based on the
secondary to auxiliary turns-ratio
(12)
It is necessary to select the transformer’s secondary to auxiliary turns-ratio (NA/NS) to ensure that VAUX(OVP) is
tripped before VCC(OVP).
CURRENT SENSE AND OVERCURRENT PROTECTION
Figure 26. Current Sense Circuit
The LM3447 provides switch overcurrent and LED short circuit protection by sensing the current through the
switching transistor, QSW via a series connected sense resistor, RSN, as shown in Figure 26. At the beginning of
each switching cycle, the Leading Edge Blanking (LEB) circuit pulls the ISNS input low for approximately 170ns.
This prevents false tripping of the protection circuit due to voltage spikes caused by switch turn on transients.
The cycle-by-cycle current limit is realized by comparing the sensed voltage at ISNS with the internal 275mV
overcurrent protection threshold. When the sense voltage exceeds 275mV, the switch is immediately turned off
for a duration of 812ms, set by the fault timer and the COMP capacitor, CCOMP is discharged. Under fault
conditions, the LM3447 enters a hiccup mode, attempting to restart the circuit after a duration of 812ms. Upon
clearance of the fault, normal operation resumes.
The overcurrent limit is set by selecting the sense resistor, RSN. It is typical to limit the switch current to two times
the maximum peak primary current, IP(PK,MAX), where
(13)
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM3447
.
ADET ADET
AC -6
VAC(ANGLE)
V V
R = =
I66 10´
VAC
LM3447
HOLD
RAC
CURRENT
MIRROR
10:1
42k 400mV
1V
VFLT2
+
±
BIAS
RBS
RHLD1
RHLD2 CHLD
QPASS
+
+
280mV
ANGLE
DECODING
CIRCUIT
VDIM
1.75V
+
FLT1
FLT2
ENHOLD
RFLT CFLT
VTFB
VREF
REFERENCE
GENERATOR
-3
SN
P(PK,MAX)
275 10
R =
2I
´
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
and
(14)
For RSN It is recommended to use a film type SMD resistor, with power rating greater than PSN and with low ESL.
ANGLE DETECT CIRCUIT
Figure 27. Phase Angle Detection and HOLD Current Circuit
The LM3447 uses the input voltage, VREC, to detect the conduction phase angle. Figure 27 shows the LM3447
angle detect circuit, where the input voltage, VREC, is scaled by the current mirror circuits and re-generated
across an internal 42kΩresistor. This replica of the input voltage is compared with internal 280mV reference to
obtain the conduction information. The resulting PWM signal, with its on-time proportional to the conduction
period, is buffered and supplied through the FLT1 pin, as shown in Figure 28. To match the external phase
dimmer characteristics with the LM3447 decoding circuit and prevent EMI filter capacitors from interfering with
dimming operation, it is necessary to select an angle detection threshold, VADET(TH). This threshold can then be
programmed using the resistor, RAC, such that
(15)
For best results, set VADET(TH) as follows:
• 25V to 40V for 120V systems
• 50V to 80V for 230V systems
Resistor RAC should also limit the VAC current under worst case operating conditions. The value of RAC should
be optimized to meet both angle detect, VADET, and VAC current, IVAC constraints.
18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: LM3447
.
GS(PASS)
H OLD
H LD1 H LD2
13.5 V
I = (R + R )
-
.
-6
HOLD(TH) AC VAC(HOLD) AC
V = R I = 95 10 R´
VFLT2
1.2V
1V
VFLT1
ENHOLD
IHOLD
1.75V
VREC
VHOLD(TH)
VADET(TH)
t
t
t
t
t
LM3447
www.ti.com
SNOSC65 A –APRIL 2012–REVISED MAY 2012
HOLD CURRENT CIRCUIT
The LM3447 incorporates an efficient hold current circuit to enhance compatibility with TRIAC based leading
edge dimmers. Holding current from an external dimmer is drawn before the Flyback PFC circuit through the
pass transistor, QPASS and limited by resistors RHLD1 and RHLD2, as shown in Figure 27. It should be noted that
the additional current drawn has no effect on the rectified input voltage and therefore does not interfere with the
input power regulation control scheme.
Figure 28. Angle Detection Circuit and Hold Current Circuit Operation
To provide high efficiency, the hold circuit is enabled only when the presence of an external dimmer is detected
based on the FLT2 input. The ENHOLD signal is asserted and hold operation is permitted when VFLT2 falls below
1V. The hold operation is halted when VFLT2 rises above 1.2V. During dimming, the hold current is drawn during
the interval when rectified input voltage is below the VHOLD(TH), based on the external resistor RAC. The FET turn-
on is controlled by an internal comparator with a reference of 400mV (higher than angle detect reference), such
that hold current is always asserted before angle detect threshold VADET(TH). The hold circuit operation is
summarized in Figure 28. The hold trun-on threshold, VHOLD(TH) is given by
(16)
The hold current is based on the BIAS voltage and set by the sum of resistors RHLD1 and RHLD2,
(17)
In selecting the hold current level, it is critical to consider its impact on the average power dissipation and the
operating junction temperature of pass transistor, QPASS under worst case operating conditions. The current
should be limited to a safe value based on the pass transistor specifications or the ABS MAX rating of LM3447
(70mA). For best performance, it is recommended to set the hold current magnitude between 5mA and 20mA. A
capacitor, CHLD of 2.2μF to 10μF, from RHLD2 to GND is connected to limit the rate of change of input current
(diin/dt) caused by the step insertion of holding current. This prevents TRIAC based dimmers from misfiring at low
dimming level.
ANGLE DECODING CIRCUIT AND DIMMING
The LM3447 incorporates a linear decoding circuit that translates the sensed conduction angle into an internal
dimming command, VDIM. The conduction angle information, represented by the PWM signal at FLT1 output, is
processed by an external low pass filter consisting of resistor, RFLT and capacitor, CFLT, which attenuates the
twice line frequency component from the signal. The resulting analog signal at FLT2 is converted into the
dimming command by a linear analog processing circuit. The piecewise linear relationship between the FLT2
input and the dimming command is shown graphically in Figure 29.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM3447
.
o
NTC(BK)
N TC (T )
BK o
R
R =
1 1
exp β T T
é ù
æ ö
-
ê úç ÷
ê ú
è ø
ë û
NTC
TSNS(REF) TSNS(TH)
7.88 kΩ
R = = 10.5 kΩ
V V-
1.2
1
0.8
0.6
0.4
0.2
0
Dimming Command, V - V
DIM
0 0.3 0.6 0.9 1.2 1.5 1.8
FLT 2 Voltage, V - V
FLT2
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
The dimming command, VDIM is
• held constant at 1V for VFLT2 ranging from 1.75V to 1.45V (conduction angle 180° to 150°)
• linearly varied with gain of 0.877 for VFLT2 ranging from 1.45V to 280mV (conduction angle 150° to 30°)
• saturated at 13mV for VFLT2 lower than 280mV (conduction angle less than 30°)
Figure 29. Relationship Between VFLT2 and VDIM
The relationship implemented by the angle decoding circuit is designed to map the non-linear power behavior of
external phase dimmer circuits and enhance Flyback PFC power stage compatibility.
Under normal operating conditions, the dimming command, VDIM is translated into a reference voltage, VREF,
where VREF = VDIM. As dimming progresses, the input power commanded by the feedforward loop is modulated
in accordance with VREF. This causes the output power and hence the LED current to vary based on the input
conduction angle. Using this feedforward control scheme and the internal angle decoding circuit of the LM3447, it
is possible to achieve monotonic, smooth and flicker free dimming with a dimming ratio of more than 50:1.
THERMAL FOLDBACK CIRCUIT
Thermal protection is necessary to prevent the LEDs and other power supply components from sustaining
damage when operated at elevated ambient temperatures. A thermal foldback circuit is incorporated into the
LM3447 to limit the maximum operating temperature of the LEDs by scaling the output power based on the
heatsink temperature. The LED temperature is sensed using an external NTC resistor, RNTC, connected between
the TSNS pin and GND, as shown in Figure 30(a). The thermal protection is engaged when the TSNS voltage
decreases below the thermal foldback threshold voltage, VTSNS(TH), of 1V. The power is scaled by adjusting the
reference voltage, VREF, based on the thermal foldback output voltage, VTFB, according to the relationship shown
in Figure 30(b). The resistor value, RNTC(BK), at which the device enters thermal protection is fixed by the internal
7.88kΩpull-up resistor and the TSNS reference voltage, VTSNS(REF) and is given by
(18)
The temperature break-point, TBK and rate-of-change (slope) are governed by the non-linear characteristics of
the NTC resistor, RNTC, given by its β-value. To achieve a break-point temperature, TBK, the NTC resistor, RNTC
should selected as
(19)
20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: LM3447
,
I N
BU LK
L LED O UT LED(R IP)
P
C2 R V I
³
fp
1.2
1
0.8
0.6
0.4
0.2
0
Reference Voltage, V - V
REF
0 0.3 0.6 0.9 1.2 1.5 1.8
Thermal Foldback Voltage, V - V
TFB
(a) Circuit
(b) Relationship between V and V
TSNS REF
LM3447
www.ti.com
SNOSC65 A –APRIL 2012–REVISED MAY 2012
where, Tois the room temperature in Kelvin, and RNTC(To) is the NTC value at room temperature. A temperature
break-point ranging from 70°C (343K) to 90°C (363K) can be achieved by selecting an NTC resistance ranging
from 100kΩto 220kΩand β-value of 3500K to 4500K.
Figure 30. Thermal Foldback
The precedence between the thermal foldback input, VTFB and the dimming input, VDIM, is decided by the
reference generator circuit. This allows dimming operation to be performed when thermal protection is engaged.
Dimming operation is allowed when the input power demanded by the decoder circuit, VDIM, is lower than the
maximum power limit set by the thermal protection circuit, VTFB. This feature provides optimal lamp utilization
under adverse operating conditions.
OUTPUT BULK CAPACITOR
The output bulk capacitor, CBULK, is required to store energy during the input voltage zero crossing interval and
limit twice the line frequency ripple component flowing through the LEDs. The value of output capacitor is given
by
(20)
where, RLED is the dynamic resistance of LED string, ILED(RIP) is the average to peak LED ripple current and fLis
line frequency. In typical applications, the solution size becomes a limiting factor and dictates the maximum
dimensions of the bulk capacitor. When selecting an electrolytic capacitor, manufacturer recommended de-rating
factors should be applied based on the worst case capacitor ripple current, output voltage and operating
temperature to achieve the desired operating lifetime.
It is essential to provide a minimum load at the output of the PFC to discharge the capacitor after the power is
switched off or during LED open circuit failures. A 20kΩresistor, RO, is recommended for best performance.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM3447
A S A
OUT
VCC
N = N , where N is the auxiliary winding turns
V
,
IN S
P(PK,MAX)
M
P T
I = 2
L
RE F
M2
I N S
OU T RE C(P K ,M IN)
V
L ,
1 1
4P +
nV V
£
æ ö
ç ÷
è ø
f
,
R EC (P K, MI N )
M A X
MA X OU T
V
D
n =
1 D V-
OUT LED
IN
FLY
V I
P =
η
LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
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DESIGN PROCEDURE(1)(2)
STEP VARIABLE DESCRIPTION
1 PIN
where
VOUT = VLED = Typical LED string voltage,
ILED is the average LED current,
ηTOT =ηEMI ×ηFLY,
ηTOT is the LED driver efficiency, ηEMI is the EMI input filter efficiency and ηFLY is the Flyback PFC efficiency.
2 DMAX 0.4 < DMAX < 0.5
where
DMAX is the maximum allowable Flyback PFC duty cycle
3 n:1
VSW = nVOUT + VREC(PK,MAX) + VOS and VSW < Maximum FET (Q1) breakdown voltage.
where
n is the transformer turns-ratio,
VREC(PK,MIN) is the minimum peak rectified input voltage,
VREC(PK,MAX) is the maximum peak rectified input voltage,
VIN(RMS,MIN) is the minimum input RMS voltage,
VIN(RMS,MAX) is the maximum input RMS voltage,
VSW is the switch drain to source voltage,
VOS is the overshoot voltage because of leakage inductance.
4 LM
where
VREF is the internal reference voltage; VREF = 1V,
fSis the fixed switching frequency; fS= 70 kHz.
5 IP(PK,MAX)
where
TSis the switching period, TS= 1/fS
8 NP, NA, NSTransformer Design
• Core geometry (EE, PQ, RM)
• Bobbin (UL Class B or Class F)
LMis the magnetizing inductance referred to primary side
n:1 = NP:NS, primary to secondary winding turns-ratio
BMAX < 0.3T, where BMAX is the maximum operating flux density corresponding to IP(PK,MAX)
(1) See the Electrical Characteristics Table for all constants and measured values, unless otherwise noted.
(2) See Figure 18 for all component locations in the Design Procedure Table.
22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: LM3447
GS(P A SS )
HLD2 HLD1
HO LD
13.5 V
R = R
I
-
-
-3
SN
P(PK,MAX)
275 10
R =
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REC(PK,MAX)
A
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R = N200 10
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R = R
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B IA S (HI G) GS ( PA S S)
HLD1
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V = 1.2 V
V V
R =
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FF
FF
1
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£
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A DET
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V A C(A N GLE )
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R =
I
LM3447
www.ti.com
SNOSC65 A –APRIL 2012–REVISED MAY 2012
STEP VARIABLE DESCRIPTION
6 RAC
where
VADET is the angle detection voltage;
• 25V to 40V for 120V system
• 50V to 80V for 230V system
IVAC(ANGLE) is the angle detection threshold,
7 RFF
where
GFF is the gain of Feedforward circuit; GFF = 10.
8 CFF
9 CCOMP 4.7μF≤CCOMP ≤10μF
10 QPASS, RHLD1
where
VGS(PASS) is the drain to source withstand voltage of pass transistor, QPASS,
ISOA(PASS) is the maximum current through pass transistor based on safe operating area characteristics.
11 RBS
where,
IBIAS is the BIAS current and IBIAS ≤500 μA
12 RAUX1, RAUX2
where,
VOUT(OVP) is the maximum output voltage under OVP condition
13 RSN
14 RFLT, CFLT RFLT = 280 kΩ, CFLT = 0.1 μF
15 RHOLD
where,
IHOLD is the holding current drawn through the external phase dimmer circuit
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM3447
,
I N
B ULK
L LE D OU T LED(RI P)
P
C
2 R V I
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,
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LM3447
SNOSC65 A –APRIL 2012–REVISED MAY 2012
www.ti.com
STEP VARIABLE DESCRIPTION
16 RNTC
where,
RNTC(BK) = 10.5 kΩ, is the fixed break point resistance,
TBK is the break point temperature in Kelvin,
TOis the room temperature in Kelvin,
RNTC(To) is the manufacturer specified NTC resistance at room temperature,
βis the NTC resistor characteristics specified by the manufacturer.
17 CBULK, RO
where,
ILED(RIP) is the average to peak magnitude of twice the line frequency current ripple through LED,
RLED is the dynamic resistance of the LED string,
fLis the line frequency
RO= 20 kΩ, is the recommended bleeder resistance
Spacer REVISION HISTORY
Changes from Original (April 2012) to Revision A Page
• Changed the device From: Product Preview To: Production ...................................................................................... 1
24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated
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