Order Now Product Folder Support & Community Tools & Software Technical Documents LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 LP5523 Nine-Channel RGB- and White-LED Driver With Internal Program Memory and Integrated Charge Pump - DSBGA Package 1 Features 3 Description * The LP5523 is a 9-channel LED driver designed to produce lighting effects for mobile devices. A highefficiency charge pump enables LED driving over full Li-Ion battery voltage range. The device is equipped with an internal program memory, which allows operation without processor control. 1 * * * * * * * * * * * * Three Independent Program Execution Engines, Nine Programmable Outputs with 25.5-mA FullScale Current, 8-Bit Current Setting Resolution, and 12-Bit PWM Control Resolution Adaptive High-Efficiency 1x/1.5x Fractional Charge Pump - Efficiency Up to 94% LED Drive Efficiency Up to 93% Charge Pump With Soft Start and Overcurrent and Short-Circuit Protection Built-in LED Test 200-nA Typical Standby Current Automatic Power-Save Mode IVDD = 10 A (Typical) Two-Wire I2C-Compatible Control Interface Flexible Instruction Set Large SRAM Program Memory Small Application Circuit Source (High-Side) Drivers Architecture Supports Color Control The LP5523 has an I2C-compatible control interface with four pin selectable addresses. The device has a flexible general purpose output (GPO), which can be used as a digital control pin for other devices. INT pin can be used to notify processor when a lighting sequence has ended (interrupt function). Also, the device has a trigger input interface, which allows synchronization, for example, between multiple LP5523 devices. The device requires only four small, low-cost ceramic capacitors. The LP5523 is available in a tiny 25-pin DSBGA package (0.4-mm pitch). 2 Applications * * * * The LP5523 maintains excellent efficiency over a wide operating range by autonomously selecting the best charge-pump gain based on LED forward voltage requirements. The LP5523 is able to automatically enter power-save mode when LED outputs are not active, thus lowering idle current consumption down to 10 A (typical). Fun Lights and Indicator Lights LED Backlighting Haptic Feedback Programmable Current Source Device Information(1) PART NUMBER LP5523 PACKAGE DSBGA (25) BODY SIZE (NOM) 2.26 mm x 2.26 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application C1 C2 0.47 F 0.47 F C1 C2 0.47 F 0.47 F C1+ C1- C2+ C2- VOUT COUT 1 F VIN = 2.7 V TO 5.5 V CIN 1 F COUT 1 F VIN = 2.7 V TO 5.5 V VDD D7 D1 SCL MCU C1+ C1- C2+ C2- VOUT D2 SDA R GPO D8 LP5523 D3 INT TRIG ASEL0 ASEL1 GND D4 D9 MCU R D1 D2 D3 SDA EN D4 CLK LP5523 G D5 GPO B R INT D6 TRIG ASEL0 D7 ASEL1 GND G D5 D6 VDD SCL B EN CLK CIN 1 F G D8 D9 B RGB LED APPLICATION WLED APPLICATION NOTE: D7, D8 AND D9 POWERED DIRECTLY FROM VIN 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 1 1 1 2 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 5 Electrical Characteristics........................................... 5 Charge Pump Electrical Characteristics .................. 6 LED Driver Electrical Characteristics ........................ 6 LED Test Electrical Characteristics .......................... 6 Logic Interface Characteristics ................................. 7 Recommended External Clock Source Conditions . 7 Serial Bus Timing Parameters (SDA, SCL) ............ 8 Typical Characteristics ............................................ 9 Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 7.3 7.4 7.5 7.6 8 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Maps ......................................................... 11 12 17 19 22 Application and Implementation ........................ 49 8.1 Application Information............................................ 49 8.2 Typical Applications ................................................ 49 9 Power Supply Recommendations...................... 53 10 Layout................................................................... 54 10.1 Layout Guidelines ................................................. 54 10.2 Layout Example .................................................... 54 11 Device and Documentation Support ................. 55 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 55 55 55 55 55 55 12 Mechanical, Packaging, and Orderable Information ........................................................... 55 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (May 2013) to Revision E Page * Changed title of data sheet for SEO ..................................................................................................................................... 1 * Added Device Information and Pin Configuration and Functions sections, ESD Ratings and Thermal Information tables, Feature Description, Device Functional Modes, Application and Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical, Packaging, and Orderable Information sections................................................................................................................................................................ 1 * Changed RJA value from "87C/W" to "60.9C/W" ................................................................................................................ 5 * Added values in the Thermal Information table to align with JEDEC standards. .................................................................. 5 Changes from Revision C (April 2013) to Revision D * 2 Page Changed layout of National Semiconductor data sheet to TI format.................................................................................... 53 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 5 Pin Configuration and Functions YFQ Package 25-Pin DSBGA Top View YFQ Package 25-Pin DSBGA Bottom View 5 5 4 4 3 3 2 2 1 1 E A B C D C D B A E Pin Functions (1) PIN TYPE DESCRIPTION NO. NAME A1 D1 A Current source output 1 A2 D2 A Current source output 2 A3 VOUT A Charge pump output A4 C2- A Flying capacitor 2 negative terminal A5 C2+ A Flying capacitor 2 positive terminal B1 D3 A Current source output 3 B2 D4 A Current source output 4 B3 ASEL1 I Serial interface address select input B4 C1- A Flying capacitor 1 negative terminal B5 C1+ A Flying capacitor 1 positive terminal C1 D5 A Current source output 5 C2 D6 A Current source output 6 C3 ASEL0 I Serial interface address select input C4 EN I Enable C5 VDD P Input power supply D1 D7 A Current source output 7 - powered from VDD D2 D8 A Current source output 8 - powered from VDD D3 INT OD/O D4 CLK I 32 kHz clock input. Connect to ground if not used D5 GND G Ground Interrupt for microcontroller unit. Leave unconnected if not used E1 D9 A Current source output 9 - powered from VDD E2 GPO O General purpose output. Leave unconnected if not used E3 TRIG I/OD Trigger. Connect to ground if not used. E4 SDA I/OD Serial interface data E5 SCL I Serial interface clock (1) A: Analog Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin OD: Open Drain Pin Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 3 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT VDD -0.3 6 V Voltage on D1 to D9, C1-, C1+, C2-, C+, VOUT -0.3 VDD + 0.3 V with 6 V maximum V Continuous power dissipation Internally limited Junction temperature, TJ-MAX Storage temperature, Tstg (1) (2) (3) -65 125 C 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, contact the TI Sales Office/Distributors for availability and specifications. All voltages are with respect to the potential at the GND pin. 6.2 ESD Ratings VALUE Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) V(ESD) Electrostatic discharge 2500 Pins D1 to D9 8000 Charged-device model (CDM), per JEDEC All pins specification JESD22-C101 (2) Machine model (1) (2) All pins except D1 to D9 1000 All pins UNIT V 250 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) (2) MIN VDD input voltage MAX UNIT 2.7 5.5 Voltage on logic pins (input or output pins) 0 VDD V Recommended charge pump load current 0 100 mA -30 125 C -30 85 C Junction temperature, TJ Ambient temperature, TA (1) (2) 4 (2) V All voltages are with respect to the potential at the GND pin. In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RJA), as given by the following equation: TA-MAX = TJ-MAX-OP - (RJA x PD-MAX). Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 6.4 Thermal Information LP5523 THERMAL METRIC (1) YFQ (DSBGA) UNIT 25 PINS RJA (2) Junction-to-ambient thermal resistance 60.9 C/W RJC(top) Junction-to-case (top) thermal resistance 0.4 C/W RJB Junction-to-board thermal resistance 9.9 C/W JT Junction-to-top characterization parameter 0.2 C/W JB Junction-to-board characterization parameter 10.0 C/W (1) (2) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. 6.5 Electrical Characteristics Unless otherwise noted: typical limits are for TA = 25C; minimum and maximum limits apply over the operating ambient temperature range (-30C < TA < +85C), specifications apply to the Functional Block Diagram with: VDD = 3.6 V, VEN = 1.65 V, COUT = 1 F, CIN = 1 F, C1-2 = 0.47 F. (1) (2) (3) (4) PARAMETER TEST CONDITIONS MIN VEN = 0V, CHIP_EN=0 (bit), external 32-kHz clock running or not running Standby supply current IVDD Normal mode supply current Power-save mode supply current OSC (1) (2) (3) (4) TYP MAX UNIT 0.2 A CHIP_EN=0 (bit), external 32 kHz clock not running 1 A CHIP_EN=0 (bit), external 32 kHz clock running 1.4 A External 32-kHz clock running, charge pump and current source outputs disabled 0.6 mA Charge pump in 1x mode, no load, current source outputs disabled 0.8 mA Charge pump in 1.5x mode, no load, current source outputs disabled 1.8 mA External 32-kHz clock running 10 A Internal oscillator running 0.6 mA Internal oscillator frequency accuracy -4% 4% -7% 7% The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 5 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 6.6 Charge Pump Electrical Characteristics Unless otherwise noted: typical limits are for TA = 25C; minimum and maximum limits apply over the operating ambient temperature range (-30C < TA < +85C). See (1) (2) (3) PARAMETER TEST CONDITIONS ROUT Charge pump output resistance SW Switching frequency IGND Ground current tON VOUT turnon time (1) (2) (3) (4) MIN TYP Gain = 1.5x MAX 3.5 Gain = 1x 1 1.25 (4) Gain = 1.5x 1.2 Gain = 1x 0.3 VDD = 3.6 V, IOUT = 60 mA 100 UNIT MHz mA s The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Turnon time is measured from the moment the charge pump is activated until the VOUT crosses 90% of its target value. 6.7 LED Driver Electrical Characteristics Unless otherwise noted limits apply for TA = 25C. See (1) (2) (3) PARAMETER TEST CONDITIONS ILEAKAGE Leakage current (outputs D1 to D9) PWM = 0% IMAX Maximum source current Outputs D1 to D9 IOUT Output current accuracy IMATCH Matching LED LED switching frequency VSAT Saturation voltage (1) (2) (3) (4) (5) (4) (4) MIN MAX 0.1 1 UNIT A 25.5 Output current set to 17.5 mA -4% -30C < TA < +85C -5% mA 4% 5% Output current set to 17.5 mA (5) TYP 1% 2.5% 312 Output current set to 17.5 mA Hz 45 100 mV The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Output current accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current outputs on the part (D1 to D9), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX - AVG) / AVG and (AVG - MIN) / AVG. The largest number of the two (worst case) is considered the matching figure. Note that some manufacturers have different definitions in use. Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at VOUT - 1 V. 6.8 LED Test Electrical Characteristics Unless otherwise noted limits apply for TA = 25C. See (1) (2) (3) PARAMETER LSB EABS Total unadjusted error tCONV Conversion time VIN_TEST DC voltage range (1) (2) (3) (4) 6 TEST CONDITIONS MIN Least significant bit TYP MAX 30 (4) VIN_TEST = 0 V to VDD < 3 mV 4 2.7 0 UNIT LSB ms 5 V The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Total unadjusted error includes offset, full-scale, and linearity errors. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 6.9 Logic Interface Characteristics Unless otherwise noted: typical limits are for TA = 25C; minimum and maximum limits apply over the operating ambient temperature range (-30C < TA < +85C).See (1) (2) (3) (4) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC INPUT EN VIL Input low level VIH Input high level 1.2 II Input current -1 tDELAY Input delay (5) 0.5 V 1 A V 2 s LOGIC INPUT SCL, SDA, TRIG, CLK, ASEL0, ASEL1 VIL Input low level VIH Input high level II Input current 0.2 x VEN 0.8 x VEN V V -1 1 A 0.5 V 1 A 0.5 V 1 A LOGIC OUTPUT SDA, TRIG, INT VOL Output low level IOUT = 3 mA (pullup current) IL Output leakage current VOUT = 2.8 V 0.3 LOGIC OUTPUT GPO VOL Output low level IOUT = 3 mA VOH Output high level IOUT = -2 mA IL Output leakage current VOUT = 2.8 V (1) (2) (3) (4) (5) 0.3 VDD - 0.5 VDD - 0.3 The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics. The I2C host must allow at least 500 s before sending data to the LP5523 after the rising edge of the enable line. 6.10 Recommended External Clock Source Conditions Unless otherwise noted limits apply for TA = 25C. See (1) (2) (3) (4) (5) MIN NOM MAX UNIT LOGIC INPUT CLK CLK Clock frequency tCLKH High time 6 tCLKL Low time 6 tr Clock rise time, 10% to 90% 2 s tf Clock fall time, 90% to 10% 2 s (1) (2) (3) (4) (5) 32.7 kHz s s The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Specification is ensured by design and is not tested in production. VEN = 1.65 V to VDD. The ideal external clock signal for the LP5523 is a 0 V to VEN 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz, program execution is faster, and at frequencies below 32.7 kHz program execution is slower. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 7 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 6.11 Serial Bus Timing Parameters (SDA, SCL) Unless otherwise noted limits apply for TA = 25C. See (1) (2) (3) (4) (5) MIN MAX UNIT 400 kHz fSCL Clock frequency 1 Hold time (repeated) START condition 0.6 s 2 Clock low time 1.3 s 3 Clock high time 600 ns 4 Setup TIME FOR A REPEATED START condition 600 ns 5 Data hold time 50 ns 6 Data setup time 100 ns 7 Rise time of SDA and SCL 20+0.1 Cb 300 ns 8 Fall time of SDA and SCL 15+0.1 Cb 300 ns 9 Set-up time for STOP condition 600 10 Bus free time between a STOP and a START condition 1.3 Cb Capacitive load parameter for each bus line. Load of one picofarad corresponds to one nanosecond. 10 (1) (2) (3) (4) (5) ns s 200 ns The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured. All voltages are with respect to the potential at the GND pin. Minimum and maximum limits are ensured by design, test, or statistical analysis. Minimum and maximum limits are ensured by design, test, or statistical analysis. Specification is ensured by design and is not tested in production. VEN = 1.65 V to VDD. Figure 1. External Clock Signals Figure 2. Serial Bus Timing Diagram 8 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 6.12 Typical Characteristics Unless otherwise specified: VDD = 3.6 V, CIN = COUT = 1 F, C1 = C2 = 0.47 F, TA = 25C; CIN, COUT, C1, C2: low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics. Figure 3. Charge Pump 1.5x Efficiency vs Load Current 6 x 1-mA Load 6 Nichia NSCW100 WLEDs on D1 To D6 Figure 5. Gain Change Hysteresis Loop At Factory Settings 17.5-mA Current See note 4 in LED Driver Electrical Characteristics Figure 4. Charge Pump Output Voltage (1.5x) as a Function of Load Current at Four Input Voltage Levels Load = 6 x Nichia NSCW100 WLEDs on D1 To D6 at 100% PWM Figure 6. Effect of Adaptive Hysteresis on the Width of the Hysteresis Loop 17.5-mA Current See note 4 in LED Driver Electrical Characteristics Figure 7. LED Current Matching Distribution Figure 8. LED Current Accuracy Distribution Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 9 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Typical Characteristics (continued) Unless otherwise specified: VDD = 3.6 V, CIN = COUT = 1 F, C1 = C2 = 0.47 F, TA = 25C; CIN, COUT, C1, C2: low-ESR surface-mount ceramic capacitors (MLCCs) used in setting electrical characteristics. 20 1k INTERNAL CLK (LEFT SCALE) SDA 500 10 VOLTAGE (2V/DIV) 15 IVDD (PA) IVDD (PA) 750 EXTERNAL CLK (RIGHT SCALE) 5 250 STOP CONDITION SCL VOUT 2V/DIV 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 0 5.5 TIME (40 Ps/DIV) VDD (V) Charge Pump In 1x Mode If the charge pump is OFF the supply current is even lower. Figure 9. Power-Save Mode Supply Current vs VDD VDD = 3.6 V ILOAD = 60 mA Figure 10. Serial Bus Write (51h To Addr 36h) and Charge-Pump Start-up Waveform 85 95 3 x SHARP GM5WA06270A RGB-LED 6 x NICHIA NSCW100 WLED 75 75 70 EFFICIENCY (%) EFFICIENCY (%) 85 80 80 9 x 10 mA 65 65 60 60 55 10 2.7 3.3 3.9 6 x 15 mA 6 x 10 mA 60 9 x 6.7 mA 55 90 95 85 90 85 80 80 75 75 70 70 65 60 65 55 4.5 55 5.1 2.7 3.3 3.9 4.5 5.1 VDD (V) VDD (V) Figure 11. 100% PWM RGB LED Efficiency vs VDD Figure 12. 100% PWM WLED Efficiency vs VDD Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 7 Detailed Description 7.1 Overview The LP5523 is a fully integrated lighting management unit for producing lighting effects for mobile devices. The LP5523 includes all necessary power management, high-side current sources, temperature compensation, twowire control interface and programmable pattern generators. The overall maximum current for each driver is set by an 8-bit register. The LP5523 controls LED luminance with a pulse width modulation (PWM) scheme with a resolution of 12 bits. Also, the temperature compensation is done by PWM. 7.2 Functional Block Diagram C1 C2 0.47 F 0.47 F C1+ C1- C2+ C2VDD VOUT CIN 1 F 1.25 MHz OSC COUT 1 F CHARGE PUMP 1x/1.5x PWM PATTERN GENERATOR VREF PROGRAM MEMORY 50H TO 6FH; 96 INSTRUCTIONS PWM PATTERN GENERATOR PWM PATTERN GENERATOR BIAS 12-BIT PWM PATTERN CONTROL ASEL0 ASEL1 SCL SERIAL DATA CTRL REG TEMP COMP D1 SDA CONTROL INT CLK DET CURRENT CONTROL D/A VDD EN CLK POR GPO LED ERROR DETECTION TRIG D2 8-BIT MAXIMUM D6 D7 D8 D9 IDAC AND HIGH SIDE LED DRIVERS THERMAL SHUTDOWN GND Copyright (c) 2016, Texas Instruments Incorporated Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 11 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 7.3 Feature Description 7.3.1 Programming The LP5523 provides flexibility and programmability for dimming and sequencing control. Each LED can be controlled directly and independently through the serial bus, or LED drivers can be grouped together for preprogrammed flashing patterns. The LP5523 has three independent program execution engines, so it is possible to form three independently programmable LED banks. LED drivers can be grouped based on their function so that, for example, the first bank of drivers can be assigned to the keypad illumination, the second bank to the funlights, and the third group to the indicator LED(s). Each bank can contain 1 to 9 LED driver outputs. Instructions for program execution engines are stored in the program memory. The total amount of the program memory is 96 instructions, and the user can allocate the memory as required by the engines. 7.3.2 LED Error Detection The LP5523 has built-in LED error detection. Error detection does not only detect open and short circuit, but provides an opportunity to measure the VF of the LEDs. The test event is activated by a serial interface write, and the results can be read through the serial interface during the next cycle. This feature can also be addressed to measure the voltage on VDD, VOUT, and INT pins. Typical example usage includes monitoring battery voltage or using INT pin as a light sensor interface. 7.3.3 Energy Efficiency When charge-pump automatic mode selection is enabled, the LP5523 monitors the voltage over the drivers of D1 to D6 so that the device can select the best charge-pump gain and maintain good efficiency over the whole operating voltage range. The red LED element of an RGB LED typically has a forward voltage of about 2 V. For that reason, the outputs D7, D8, and D9 are internally powered by VDD, since battery voltage is high enough to drive red LEDs over the whole operating voltage range. This allows the driving of three RGB LEDs with good efficiency because the red LEDs do not load the charge pump. The LP5523 is able to automatically enter powersave mode when LED outputs are not active, thus lowering idle current consumption down to 10 A (typical). Also, during the down time of the PWM cycle (constant current output status is low), additional power savings can be achieved when the PWM Powersave feature is enabled. 7.3.4 Temperature Compensation The luminance of an LED is typically a function of its temperature even though the current flowing through the LED remains constant. Because luminance is temperature dependent, many LED applications require some form of temperature compensation to decrease luminance and color purity variations due to temperature changes. The LP5523 has a built-in temperature-sensing element, and PWM duty cycle of the LED drivers changes linearly in relationship to changes in temperature. User can select the slope of the graph (31 slopes) based on the LED characteristics (see Figure 13). This compensation can be done either constantly, or only right after the device wakes up from power-save mode, to avoid error due to self-heating of the device. Linear compensation is considered to be practical and accurate enough for most LED applications. 12 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 Feature Description (continued) 100 MAXIMUM SLOPE VALUE PWM OUTPUT % 75 NO COMP. 50 25 MINIMUM SLOPE VALUE 0 -25 0 25 50 75 TEMPERATURE C Figure 13. Temperature Compensation Principle Compensation is effective over the temperature range -40C to +90C. 7.3.5 Charge Pump Operational Description 7.3.5.1 Overview The LP5523 includes a pre-regulated switched-capacitor charge pump with a programmable voltage multiplication of 1x and 1.5x. In 1.5x mode, by combining the principles of a switched-capacitor charge pump and a linear regulator, a regulated 4.5-V output is generated from the Li-Ion input voltage range. A two-phase non-overlapping clock generated internally controls the operation of the charge pump. During the charge phase, both flying capacitors (C1 and C2) are charged from input voltage. In the pump phase that follows, the flying capacitors are discharged to output. A traditional switched-capacitor charge pump operating in this manner uses switches with very low on-resistance, ideally 0 , to generate an output voltage that is 1.5x the input voltage. The LP5523 regulates the output voltage by controlling the resistance of the input-connected pass-transistor switches in the charge pump. 7.3.5.2 Output Resistance At lower input voltages, the charge pump output voltage may degrade due to effective output resistance (ROUT) of the charge pump. The expected voltage drop can be calculated by using a simple model for the charge pump shown in Figure 14. VIN REG V , ROUT , 1.5X 1.5 x V VOUT Figure 14. Charge Pump Output Resistance Model The model shows a linear pre-regulation block (REG), a voltage multiplier (1.5x), and an output resistance (ROUT). Output resistance models the output voltage drop that is inherent to switched capacitor converters. The output resistance is 3.5 (typical), and it is a function of switching frequency, input voltage, capacitance value of the flying capacitor, internal resistances of the switches, and ESR of the flying capacitors. When the output voltage is in regulation, the regulator in the model controls the voltage V' to keep the output voltage equal to 4.5 V (typical). Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 13 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Feature Description (continued) With increased output current, the voltage drop across ROUT increases. To prevent drop in output voltage, the voltage drop across the regulator is reduced, V' increases, and VOUT remains at 4.5 V. When the output current increases to the point that there is zero voltage drop across the regulator, V' equals the input voltage, and the output voltage is on the edge of regulation. Additional output current causes the output voltage to fall out of regulation, so that the operation is similar to a basic open-loop 1.5x charge pump. In this mode, output current results in output voltage drop proportional to the output resistance of the charge pump. The out-of-regulation output voltage can be approximated by: VOUT = 1.5 x VIN - IOUT x ROUT. 7.3.5.3 Controlling The Charge Pump The charge pump is controlled with two CP_MODE bits in MISC register (address 36H). When both of the bits are low, the charge pump is disabled, and output voltage is pulled down with an internal 300 k (typ.) resistor. The charge pump can be forced to bypass mode, so the battery voltage is connected directly to the current sources; in 1.5xmode output voltage is boosted to 4.5 V. In automatic mode, charge-pump operation mode is determined by saturation of constant current drivers, as described in LED Forward Voltage Monitoring. 7.3.5.4 LED Forward Voltage Monitoring When the charge-pump automatic mode selection is enabled, voltages over LED drivers D1 to D6 are monitored. (Note: Power input for current source outputs D7, D8 and D9 are internally connected to the VDD pin.) If the D1 to D6 drivers do not have enough headroom, charge-pump gain is set to 1.5x. Driver saturation monitor does not have a fixed voltage limit, since saturation voltage is a function of temperature and current. Charge pump gain is set to 1x, when battery voltage is high enough to supply all LEDs. In automatic gain change mode, the charge pump is switched to bypass mode (1x), when LEDs are inactive for over 50 ms. 7.3.5.5 Gain Change Hysteresis Charge-pump-gain control utilizes digital filtering to prevent supply voltage disturbances (for example, the transient voltage on the power supply during the GSM burst) from triggering unnecessary gain changes. Hysteresis is provided to prevent periodic gain changes (which could occur due to LED driver) and charge-pump voltage drop in 1x mode. The hysteresis of the gain change is user-configurable; default setting is factoryprogrammable. Flexible configuration ensures that hysteresis can be minimized or set to desired level in each application. LED forward voltage monitoring and gain control block diagram is shown in Figure 15. MODE CHARGE PUMP VDD VOUT P W M CURRENT SOURCE D1 TO D6 VOFS COMPARATOR SATURATION MONITOR DIGITAL FILTER CONTROL REGISTERS PROGRAM MEMORY COMMAND LOOK-AHEAD MODE CONTROL Figure 15. Forward Voltage Monitoring and Gain Control Block 14 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 Feature Description (continued) 7.3.6 LED Driver Operational Description 7.3.6.1 Overview The LP5523 LED drivers are constant-current sources. Output current can be programmed by control registers up to 25.5 mA. The overall maximum current is set by 8-bit output current control registers with 100-A step size. Each of the 9 LED drivers has a separate output-current control register. LED OUTPUT CURRENT The LED luminance pattern (dimming) is controlled with PWM (pulse width modulation) technique, which has internal resolution of 12 bits (8-bit control can be seen by user). PWM frequency is 312 Hz. See Figure 16. PWM FREQUENCY = 312 Hz 12-BIT PWM PATTERN CONTROL 0% TO 100 % 8-BIT CURRENT SETTING 0 mA TO 25.5 mA TIME Figure 16. LED Pattern and Current Control Principle LED dimming is controlled according to a logarithmic or linear scale, see Figure 17. A logarithmic or linear scheme can be set for both the program execution engine control and direct PWM control. Note: if the temperature compensation is active, the maximum PWM duty cycle is limited to 50% at 25C. This is required to allow enough headroom for temperature compensation over the whole temperature range -40C to +90C. 100,0 100 PWM OUTPUT % 80,0 80 60 60,0 40,0 40 20,0 20 0 0,0 0,0 0 64,0 64 128,0 128 192,0 192 256,0 256 DIMMING CONTROL (DEC) Figure 17. Logarithmic vs Linear Dimming 7.3.6.2 Powering LEDs The LP5523 is very suitable for white LED and general purpose applications, and it is particularly well suited to use with RGB LEDs. The device architecture is optimized for use with three RGB LEDs. Typically, the red LEDs have forward voltages below 2 volts, thus red LEDs can be powered directly from VDD. In the LP5523 device the D7, D8, and D9 drivers are powered from the battery voltage (VDD), not from the charge-pump output. D1 to D6 drivers are internally connected to the charge-pump output, and these outputs can be used for driving green and blue (VF = 2.7 V to 3.7 V typical) or white LEDs. Of course, D7, D8, and D9 outputs can be used for green, blue or white LEDs if the VDD voltage is high enough. An RGB LED configuration example is given in Typical Applications. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 15 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Feature Description (continued) 7.3.6.3 Controlling The High-Side LED Drivers 1. Direct PWM Control: All LP5523 LED drivers, D1 to D9, can be controlled independently through the two-wire serial I2C-compatible interface. For each high-side driver there is a PWM control register. Direct PWM control is active by default. 2. Controlling by Program Execution Engines: Engine control is used when the user wants to create programmed sequences. The program execution engine has a higher priority than direct control registers. Therefore, if the user has set the PWM register to a certain value, it is automatically overridden when the program execution engine controls the driver. LED control and program execution engine operation is described in Control Register Details. 3. Master Fader Control: In addition to LED-by-LED PWM register control, the LP5523 is equipped with socalled master fader control, which allows the user to fade in or fade out multiple LEDs by writing to only one register. This is a useful function to minimize serial-bus traffic between the MCU and the LP5523. The LP5523 has three master fader registers, so it is possible to form three master fader groups. 16 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 7.4 Device Functional Modes 7.4.1 Modes Of Operation RESET In the RESET mode all the internal registers are reset to the default values. Reset is always entered if Reset Register (3DH) is written FFH or internal Power-On Reset is active. Power-On Reset (POR) activates during the chip startup or when the supply voltage VDD fall below 1.5V (typ.). Once VDD rises above 1.5V (typ.), POR deactivates, and the device continues to the STANDBY mode. CHIP_EN control bit is low after POR by default. STANDBY: The STANDBY mode is entered if the register bit CHIP_EN or EN pin is LOW, and Reset is not active. This is the low-power consumption mode, when all circuit functions are disabled. Most registers can be written in this mode if EN pin is risen to high so that control bits are effective right after the startup (see Control Register Details). STARTUP: When CHIP_EN bit is written high and EN pin is high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, bias, oscillator etc.). Startup delay is 500 s. If the chip temperature rises too high, the Thermal shutdown (TSD) disables the chip operation, and the chip waits in STARTUP mode until no thermal shutdown event is present. NORMAL: During NORMAL mode the user controls the chip using the Control Registers. POWER SAVE: In POWER-SAVE mode analog blocks are disabled to minimize power consumption. See Automatic Power-Save Mode for further information. POR RESET Reset Register = FF or POR=H STANDBY EN=H (pin) and CHIP_EN=H (bit) EN=L (pin) or CHIP_EN=L (bit) INTERNAL STARTUP SEQUENCE TSD = H TSD = L NORMAL MODE Exit power save Enter power save POWER SAVE Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 17 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Device Functional Modes (continued) 7.4.1.1 Automatic Power-Save Mode Automatic power-save mode is enabled when POWERSAVE_EN bit in register address 36H is 1. Almost all analog blocks are powered down in power-save if an external clock signal is used. Only the charge-pump protection circuits remain active. However, if the internal clock has been selected, only charge pump and LED drivers are disabled during the power save; the digital part of the LED controller needs to stay active. In both cases the charge pump enters the weak 1x mode. In this mode the charge pump utilizes a passive current limited keep-alive switch, which keeps the output voltage at the battery level. During the program execution LP5523 can enter power save if there is no PWM activity in any of the LED driver outputs. To prevent short power-save sequences during program execution, LP5523 has an instruction look-ahead filter. During program execution engine 1, engine 2 and engine 3 instructions are constantly analyzed, and if there are time intervals of more than 50 ms in length with no PWM activity on LED driver outputs, the device enters power save. In powersave mode program execution continues uninterrupted. When an instruction that requires PWM activity is executed, a fast internal-startup sequence is started automatically. 7.4.1.2 PWM Power-Save Mode PWM cycle power-save mode is enabled when register 36 bit [2] PWM_PS_EN is set to 1. In PWM power-save mode analog blocks are powered down during the "down time" of the PWM cycle. Which blocks are powered down depends whether the external or internal clock is used. While the Automatic Power-Save Mode (see above) saves energy when there is no PWM activity at all, the PWM power-save mode saves energy during PWM cycles. Like the automatic power-save mode, PWM power-save mode also works during program execution. Figure 18 shows the principle of the PWM power-save technique. An LED on D9 output is driven at 50% PWM, 5-mA current (top waveform). After PWM Power-save enable, the LED-current remains the same, but the LP5523 input current drops down to an approximately 50-A level when the LED is OFF, or to an approximately 200-A level when the charge-pump-powered output(s) are used. CURRENT LED CURRENT 5 mA/DIV LP5523 INPUT CURRENT 1 mA/DIV PWM POWERSAVE ENABLED INPUT CURRENT ~50 eA DURING PWM POWERSAVE TIME 1 ms/DIV Figure 18. PWM Power-Save Principle; External Clock, VDD = 3.6 V 18 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 7.5 Programming 7.5.1 I2C-Compatible Control Interface The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the devices connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pullup resistor placed somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data transfer. 7.5.1.1 Data Validity The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when clock signal is LOW. SCL SDA data change allowed data valid data change allowed data valid data change allowed Figure 19. Data Validity Diagram 7.5.1.2 Start and Stop Conditions START and STOP conditions classify the beginning and the end of the data transfer session. A START condition is defined as the SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP condition. During data transmission, the bus master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. 7.5.1.3 Transferring Data Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP5523 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP5523 generates an acknowledge after each byte has been received. There is one exception to the "acknowledge after every byte" rule. When the master is the receiver, it must indicate to the transmitter an end of data by not acknowledging ("negative acknowledge") the last byte clocked out of the slave. This "negative acknowledge" still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. After the START condition, the bus master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (READ or WRITE). The LP5523 address is defined with ASEL0 and ASEL1 pins, and it is 32h when ASEL1 and ASEL0 are connected to GND. For the eighth bit, a "0" indicates a WRITE and a "1" indicates a READ. The second byte selects the register to which the data is written. The third byte contains data to write to the selected register. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 19 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Programming (continued) 7.5.1.4 I2C-Compatible Chip Address ASEL0 and ASEL1 pins configure the chip address for the LP5523 as shown in Table 1. Table 1. LP5523 Chip Address Configuration ASEL1 ASEL0 ADDRESS 8-BIT HEX ADDRESS GND GND (HEX) WRITE/READ 32 GND 64/65 VEN 33 66/67 VEN GND 34 68/69 VEN VEN 35 6A/6B MSB LSB ADR6 bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 0 1 1 0 0 1 0 R/W bit0 2 I C Slave Address (chip address) Figure 20. LP5523 Chip Address ack from slave ack from slave ack from slave start MSB Chip Addr LSB w ack MSB Register Addr LSB ack MSB Data LSB ack stop start id = 32h w ack addr = 40h ack address 40h data ack stop SCL SDA This data pattern writes temperature information to the TEMPERATURE WRITE register (40h). Figure 21. Write Cycle (W = Write; SDA = 0), Id = Chip Address = 32h for LP5523 ack from slave start MSB Chip Addr LSB w ack from slave MSB Register Addr LSB repeated start ack from slave data from slave nack from master rs MSB Chip Address LSB rs id = 32h r MSB Data LSB stop address 3Fh data nack stop SCL SDA start id =32h w ack address = 3Fh ack r ack This data pattern reads temperature information from the TEMPERATURE READ register (3Fh). When a READ function is to be accomplished, a WRITE function must precede the READ function. Figure 22. Read Cycle (R = Read; SDA = 1), Id = Chip Address = 32h for LP5523 20 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 7.5.1.4.1 Control Register Write Cycle * * * * * * * * * Master device generates start condition. Master device sends slave address (7 bits) and the data direction bit (r/w = 0). Slave device sends acknowledge signal if the slave address is correct Master sends control register address (8 bits). Slave sends acknowledge signal. Master sends data byte to be written to the addressed register. Slave sends acknowledge signal. If master sends further data bytes, the slave's control register address is incremented by one after acknowledge signal. In order to reduce program load time, the LP5523 supports address auto incrementation. Register address is incremented after each 8 data bits. For example, the whole program memory page can be written in one serial bus write sequence. Note: serial bus address auto increment is not supported for register addresses from 16 to 1E. Write cycle ends when the master creates stop condition. 7.5.1.4.2 Control Register Read Cycle * * * * * * * * * * * Master device generates a start condition. Master device sends slave address (7 bits) and the data direction bit (r/w = 0). Slave device sends acknowledge signal if the slave address is correct Master sends control register address (8 bits). Slave sends acknowledge signal. Master device generates repeated start condition. Master sends the slave address (7 bits) and the data direction bit (r/w = 1). Slave sends acknowledge signal if the slave address is correct. Slave sends data byte from addressed register. If the master device sends an acknowledge signal, the control register address is incremented by one. Slave device sends data byte from addressed register. Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition 7.5.1.4.3 Auto-Increment Feature The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the LP5523, the internal address index counter is incremented by one, and the next register is written. Example below (Table 2) shows writing sequence to two consecutive registers. Auto-increment feature is enabled by writing EN_AUTO_INCR bit high in the MISC register (addr 36h). Note: serial bus address auto increment is not supported for register addresses from 16 to 1E. Table 2. Auto Increment Example. MASTER START CHIP ADDR =32H REG ADDR WRITE LP5523 ACK DATA ACK DATA ACK STOP ACK Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 21 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 7.6 Register Maps 7.6.1 Register Set The LP5523 is controlled by a set of registers through the two-wire serial interface port. Some register bits are reserved for future use. Table 3 lists device registers, their addresses and their abbreviations. A more detailed description is given in Control Register Details. Table 3. Control Register Map HEX ADDRESS 00 01 02 03 04 22 REGISTER NAME ENABLE / ENGINE CNTRL1 ENGINE CNTRL2 OUTPUT DIRECT/RATIOMETRIC MSB OUTPUT DIRECT/RATIOMETRIC LSB OUTPUT ON/OFF CONTROL MSB BIT(s) READ/ WRITE DEFAULT VALUE AFTER RESET [6] R/W x0xxxxxx CHIP_EN 0 = LP5523 not enabled 1 = LP5523 enabled [5:4] R/W xx00xxxx ENGINE1_EXEC Engine 1 program execution control [3:2] R/W xxxx00xx ENGINE2_EXEC Engine 2 program execution control [1:0] R/W xxxxxx00 ENGINE3_EXEC Engine 3 program execution control [5:4] R/W xx00xxxx ENGINE1_MODE ENGINE 1 mode control [3:2] R/W xxxx00xx ENGINE2_MODE ENGINE 2 mode control [1:0] R/W xxxxxx00 ENGINE3_MODE ENGINE 3 mode control [0] R/W xxxxxxx0 D9_RATIO_EN Enables ratiometric dimming for D9 output. [7] R/W 0xxxxxxx D8_RATIO_EN Enables ratiometric dimming for D8 output. [6] R/W x0xxxxxx D7_RATIO_EN Enables ratiometric dimming for D7 output. [5] R/W xx0xxxxx D6_RATIO_EN Enables ratiometric dimming for D6 output. [4] R/W xxx0xxxx D5_RATIO_EN Enables ratiometric dimming for D5 output. [3] R/W xxxx0xxx D4_RATIO_EN Enables ratiometric dimming for D4 output. [2] R/W xxxxx0xx D3_RATIO_EN Enables ratiometric dimming for D3 output. [1] R/W xxxxxx0x D2_RATIO_EN Enables ratiometric dimming for D2 output. [0] R/W xxxxxxx0 D1_RATIO_EN Enables ratiometric dimming for D1 output. [0] R/W xxxxxxx1 D9_ON ON/OFF control for D9 output Submit Documentation Feedback BIT MNEMONIC AND DESCRIPTION Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 Register Maps (continued) Table 3. Control Register Map (continued) HEX ADDRESS 05 06 07 08 09 0A 0B REGISTER NAME OUTPUT ON/OFF CONTROL LSB D1 CONTROL D2 CONTROL D3 CONTROL D4 CONTROL D5 CONTROL D6 CONTROL BIT(s) READ/ WRITE DEFAULT VALUE AFTER RESET [7] R/W 1xxxxxxx D8_ON ON/OFF control for D8 output [6] R/W x1xxxxxx D7_ON ON/OFF control for D7 output [5] R/W xx1xxxxx D6_ON ON/OFF control for D6 output [4] R/W xxx1xxxx D5_ON ON/OFF control for D5 output [3] R/W xxxx1xxx D4_ON ON/OFF control for D4 output [2] R/W xxxxx1xx D3_ON ON/OFF control for D3 output [1] R/W xxxxxx1x D2_ON ON/OFF control for D2 output [0] R/W xxxxxxx1 D1_ON ON/OFF control for D1 output [7:6] R/W 00xxxxxx MAPPING Mapping for D1 output [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D1 [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D1 output [7:6] R/W 00xxxxxx MAPPING Mapping for D2 output [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D2 output [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D2 output [7:6] R/W 00xxxxxx MAPPING Mapping for D3 output [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D3 output [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D3 output [7:6] R/W 00xxxxxx MAPPING Mapping for D4 output [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D4 output [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D4 output [7:6] R/W 00xxxxxx MAPPING Mapping for D5 ouput [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D5 output [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D5 [7:6] R/W 00xxxxxx MAPPING Mapping for D6 output [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D6 output [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D6 output BIT MNEMONIC AND DESCRIPTION Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 23 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Register Maps (continued) Table 3. Control Register Map (continued) HEX ADDRESS 0C 0D 0E 0F TO 15 D7 CONTROL D8 CONTROL D9 CONTROL BIT(s) READ/ WRITE DEFAULT VALUE AFTER RESET [7:6] R/W 00xxxxxx MAPPING Mapping for D7 output [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D7 output [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D7 output [7:6] R/W 00xxxxxx MAPPING Mapping for D8 output [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D8 output [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D8 output [7:6] R/W 00xxxxxx MAPPING Mapping for D9 output [5] R/W xx0xxxxx LOG_EN Logarithmic dimming control for D9 output [4:0] R/W xxx00000 TEMP COMP Temperature compensation control for D9 output BIT MNEMONIC AND DESCRIPTION RESERVED [7:0] 16 D1 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D1 17 D2 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D2 18 D3 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D3 19 D4 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D4 1A D5 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D5 1B D6 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D6 1C D7 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D7 1D D8 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D8 1E D9 PWM [7:0] R/W 00000000 PWM PWM duty cycle control for D9 RESERVED [7:0] 26 D1 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D1 output current control register. Default 17.5 mA (typical) 27 D2 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D2 output current control register. Default 17.5 mA (typical) 28 D3 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D3 output current control register. Default 17.5 mA (typical) 29 D4 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D4 output current control register. Default current is 17.5 mA (typical) 2A D5 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D5 output current control register. Default current is 17.5 mA (typical) 1F TO 25 24 REGISTER NAME RESERVED FOR FUTURE USE RESERVED FOR FUTURE USE Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 Register Maps (continued) Table 3. Control Register Map (continued) HEX ADDRESS REGISTER NAME BIT(s) READ/ WRITE DEFAULT VALUE AFTER RESET BIT MNEMONIC AND DESCRIPTION 2B D6 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D6 output current control register. Default current is 17.5 mA (typical) 2C D7 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D7 output current control register. Default current is 17.5 mA (typical) 2D D8 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D8 output current control register. Default current is 17.5 mA (typical) 2E D9 CURRENT CONTROL [7:0] R/W 10101111 CURRENT D9 output current control register. Default current is 17.5 mA (typical) RESERVED FOR FUTURE USE [7:0] 2F TO 35 36 MISC RESERVED FOR FUTURE USE [7] R/W 0xxxxxxx VARIABLE_D_SEL Variable D source selection [6] R/W x1xxxxxx EN_AUTO_INCR Serial bus address auto increment enable [5] R/W xx0xxxxx POWERSAVE_EN Powersave mode enable [4:3] R/W xxx00xxx CP_MODE Charge pump gain selection [2] R/W xxxxx0xx PWM_PS_EN PWM cycle powersave enable [1] R/W xxxxxx0x CLK_DET_EN External clock detection [0] R/W xxxxxxx0 INT_CLK_EN Clock source selection 37 ENGINE1 PC [6:0] R/W x0000000 PC Program counter for engine 1 38 ENGINE2 PC [6:0] R/W x0000000 PC Program counter for engine 2 39 ENGINE3 PC [6:0] R/W x0000000 PC Program counter for engine 3 [7] R 0xxxxxxx LEDTEST_MEAS_DONE Indicates when the LED test measurement is done. [6] R x1xxxxxx MASK_BUSY Mask bit for interrupts generated by STARTUP_BUSY or ENGINE_BUSY. [5] R xx0xxxxx START-UP_BUSY This bit indicates that the start-up sequence is running. [4] R xxx0xxxx ENGINE_BUSY This bit indicates that a program execution engine is clearing internal registers. [3] R xxxx0xxx EXT_CLK_USED Indicates when external clock signal is in use. [2] R xxxxx0xx ENG1_INT Interrupt bit for program execution engine 1 [1] R xxxxxx0x ENG2_INT Interrupt bit for program execution engine 2 [0] R xxxxxxx0 ENG3_INT Interrupt bit for program execution engine 3 3A STATUS/INTERRUPT Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 25 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Register Maps (continued) Table 3. Control Register Map (continued) HEX ADDRESS 3B BIT(s) READ/ WRITE DEFAULT VALUE AFTER RESET [2] R/W xxxxx0xx INT_CONF INT pin can be configured to function as a GPO with this bit [0] R/W xxxxxxx0 INT_GPO GPO pin control for INT pin when INT_CONF is set 1 INT/GPO BIT MNEMONIC AND DESCRIPTION 3C VARIABLE [7:0] R/W 00000000 VARIABLE Global 8-bit variable 3D RESET [7:0] R/W 00000000 RESET Writing 11111111 into this register resets the LP5523 [7] R 0xxxxxxx TEMP_MEAS_BUSY Indicates when temperature measurement is active [2] R/W xxxxx0xx EN_TEMP_SENSOR Reads the internal temperature sensor once [1] R/W xxxxxx0x CONTINUOUS_CONV Continuous temperature measurement selection [0] R/W xxxxxxx0 SEL_EXT_TEMP Internal/external temperature sensor selection 3E TEMP ADC CONTROL 3F TEMPERATURE READ [7:0] R 00011001 TEMPERATURE Bits for temperature information 40 TEMPERATURE WRITE [7:0] R/W 00000000 TEMPERATURE Bits for temperature information [7] R/W 0xxxxxxx EN_LED_TEST_ADC [6] R/W x0xxxxxx EN_LED_TEST_INT [5] R/W xx0xxxxx CONTINUOUS_CONV Continuous LED test measurement selection [4:0] R/W xxx00000 LED_TEST_CTRL Control bits for LED test R N/A 41 26 REGISTER NAME LED TEST CONTROL LED_TEST_ADC LED test result 42 LED TEST ADC [7:0] 43 RESERVED [7:0] 44 RESERVED [7:0] 45 ENGINE1 VARIABLE A [7:0] R 00000000 VARIABLE FOR ENGINE1 46 ENGINE2 VARIABLE A [7:0] R 00000000 VARIABLE FOR ENGINE2 47 ENGINE3 VARIABLE A [7:0] R 00000000 VARIABLE FOR ENGINE3 48 MASTER FADER1 [7:0] R/W 00000000 MASTER FADER 49 MASTER FADER2 [7:0] R/W 00000000 MASTER FADER 4A MASTER FADER3 [7:0] R/W 00000000 MASTER FADER 4B RESERVED FOR FUTURE USE 4C ENG1 PROG START ADDR [6:0] R/W x0000000 ADDR 4D ENG2 PROG START ADDR [6:0] R/W x0001000 ADDR 4E ENG3 PROG START ADDR [6:0] R/W x0010000 ADDR 4F PROG MEM PAGE SEL [2:0] R/W xxxxx000 PAGE_SEL RESERVED FOR FUTURE USE RESERVED FOR FUTURE USE RESERVED FOR FUTURE USE Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 Register Maps (continued) Table 3. Control Register Map (continued) HEX ADDRESS REGISTER NAME BIT(s) READ/ WRITE DEFAULT VALUE AFTER RESET PROGRAM MEMORY 00H/10H/20H/30H/40H/50H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 01H/11H/21H/31H/41H/51H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 02H/12H/22H/32H/42H/52H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 03H/13H/23H/33H/43H/53H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 04H/14H/24H/34H/44H/54H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 05H/15H/25H/35H/45H/55H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 06H/16H/26H/36H/46H/56H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 07H/17H/27H/37H/47H/57H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 08H/18H/28H/38H/48H/58H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 09H/19H/29H/39H/49H/59H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 0AH/1AH/2AH/3AH/4AH/5A H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 0BH/1BH/2BH/3BH/4BH/5B H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 0CH/1CH/2CH/3CH/4CH/5 CH [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 0DH/1DH/2DH/36D/46D/5D H [15:8] R/W 00000000 [7:0] R/W 00000000 PROGRAM MEMORY 0EH/1EH/2EH/3EH/4EH/5E H [15:8] R/W 00000000 [7:0] R/W 00000000 [15:8] R/W 00000000 6F PROGRAM MEMORY 0FH/1FH/2FH/3FH/4FH/5F H [7:0] R/W 00000000 70 ENG1 MAPPING MSB [0] R xxxxxxx0 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E BIT MNEMONIC AND DESCRIPTION CMD Every Instruction is 16-bit width. The LP5523 can store 96 instructions. Each instruction consists of 16 bits. Because one register has only 8 bits, one instruction requires two register addresses. In order to reduce program load time the LP5523 supports address auto-incrementation. Register address is incremented after each 8 data bits. Thus the whole program memory page can be written in one serial bus write sequence. D9 Engine 1 mapping information, D9 output Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 27 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Register Maps (continued) Table 3. Control Register Map (continued) HEX ADDRESS 71 72 73 74 75 28 REGISTER NAME BIT(s) READ/ WRITE DEFAULT VALUE AFTER RESET [7] R 0xxxxxxx D8 Engine 1 mapping information, D8 output [6] R x0xxxxxx D7 Engine 1 mapping information, D7 output [5] R xx0xxxxx D6 Engine 1 mapping information, D6 output [4] R xxx0xxxx D5 Engine 1 mapping information, D5 output [3] R xxxx0xxx D4 Engine 1 mapping information, D4 output [2] R xxxxx0xx D3 Engine 1 mapping information, D3 output [1] R xxxxxx0x D2 Engine 1 mapping information, D2 output [0] R xxxxxxx0 D1 Engine 1 mapping information, D1 output [0] R xxxxxxx0 D9 Engine 2 mapping information, D9 output [7] R 0xxxxxxx D8 Engine 2 mapping information, D8 output [6] R x0xxxxxx D7 Engine 2 mapping information, D7 output [5] R xx0xxxxx D6 Engine 2 mapping information, D6 output [4] R xxx0xxxx D5 Engine 2 mapping information, D5 output [3] R xxxx0xxx D4 Engine 2 mapping information, D4 output [2] R xxxxx0xx D3 Engine 2 mapping information, D3 output [1] R xxxxxx0x D2 Engine 2 mapping information, D2 output [0] R xxxxxxx0 D1 Engine 2 mapping information, D1 output [0] R xxxxxxx0 D9 Engine 3 mapping information, D9 output [7] R 0xxxxxxx D8 Engine 3 mapping information, D8 output [6] R x0xxxxxx D7 Engine 3 mapping information, D7 output [5] R xx0xxxxx D6 Engine 3 mapping information, D6 output [4] R xxx0xxxx D5 Engine 3 mapping information, D5 output [3] R xxxx0xxx D4 Engine 3 mapping information, D4 output [2] R xxxxx0xx D3 Engine 3 mapping information, D3 output [1] R xxxxxx0x D2 Engine 3 mapping information, D2 output [0] R xxxxxxx0 D1 Engine 3 mapping information, D1 output ENG1 MAPPING LSB ENG2 MAPPING MSB ENG2 MAPPING LSB ENG3 MAPPING MSB ENG3 MAPPING LSB Submit Documentation Feedback BIT MNEMONIC AND DESCRIPTION Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 Register Maps (continued) Table 3. Control Register Map (continued) HEX ADDRESS 76 REGISTER NAME GAIN CHANGE CTRL BIT(s) READ/ WRITE DEFAULT VALUE AFTER RESET BIT MNEMONIC AND DESCRIPTION [7:6] R/W 00xxxxxx THRESHOLD Threshold voltage (typical) 00 - 400 mV 01 - 300 mV 10 - 200 mV 11 - 100 mV [5] R/W xx0xxxxx ADAPTIVE_THRESH_EN Activates adaptive threshold. [4:3] R/W xxx00xxx TIMER 00 - 5 ms 01 - 10 ms 10 - 50 ms 11 - Infinite [2] R/W xxxxx0xx FORCE_1x Activates 1.5x to 1x timer. 7.6.2 Control Register Details 00 ENABLE/ ENGINE CONTROL1 * 00 - Bit [6] CHIP_EN - 1 = internal start-up sequence powers up all the needed internal blocks and the device enters normal mode. - 0 = standby mode is entered. Control registers can still be written or read, excluding bits[5:0] in reg 00 (this register), registers 16h to 1E (LED PWM registers) and 37h to 39h (program counters). * 00 -- Bits [5:4] ENGINE1_EXEC - Engine 1 program execution control. Execution register bits define how the program is executed. Program start address can be programmed to Program Counter (PC) register 37H. - 00 = hold: Hold causes the execution engine to finish the current instruction and then stop. Program counter (PC) can be read or written only in this mode. - 01 = step: Execute the instruction at the location pointed by the PC, increment the PC by one and then reset ENG1_EXEC bits to 00 (i.e. enter hold). - 10 = free run: Start program execution from the location pointed by the PC. - 11 = execute once: Execute the instruction pointed by the current PC value and reset ENG1_EXEC to 00 (that is, enter hold). The difference between step and execute once is that execute once does not increment the PC. * 00 -- Bits [3:2] ENGINE2_EXEC - Engine 2 program execution control. Equivalent to above definition of control bits. Program start address can be programmed to PC register 38H. * 00 -- Bits [1:0] ENGINE3_EXEC - Engine 3 program execution control. Equivalent to engine 1 control bits. Program start address can be programmed to PC register 39H. 01 ENGINE CONTROL2 * Operation modes are defined in this register. - Disabled: Engines can be configured to disabled mode each one separately. - Load program: Writing to program memory is allowed only when the engine is in load program operation mode and engine busy bit (reg 3A) is not set. Serial bus master should check the busy bit before writing to program memory or allow at least 1ms delay after entering to load mode before memory write, to ensure initalization. All the three engines are in hold while one or more engines are in load program mode. PWM values are frozen, also. Program execution continues when all the engines are out of load program mode. Load program mode resets the program counter of the respective engine. Load program mode can be entered from the disabled mode only. Entering load program mode from the run program mode is not allowed. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 29 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com - Run Program:Run program mode executes the instructions stored in the program memory. Execution register (ENG1_EXEC etc.) bits define how the program is executed (hold, step, free run or execute once). Program start address can be programmed to the PC register. The PC is reset to zero when the PC's upper limit value is reached. - Halt: Instruction execution aborts immediately, and engine operation halts. - 01 -- Bit [5:4] ENGINE1_MODE - 00 = disabled. - 01 = load program to SRAM, reset engine 1 PC. - 10 = run program as defined by ENGINE1_EXEC bits. - 11 = halts the engine. - 01 -- Bits [3:2] ENGINE2_MODE - 00 = disabled. - 01 = load program to SRAM, reset engine 2 PC. - 10 = run program as defined by ENGINE2_EXEC bits. - 11 = halts the engine. - 01 -- Bits [3:2] ENGINE3_MODE - 00 = disabled. - 01 = load program to SRAM, reset engine 3 PC. - 10 = run program as defined by ENGINE3_EXEC bits. - 11 = halts the engine. 02 OUTPUT DIRECT/RATIOMETRIC MSB A particular feature of the LP5523 is the ratiometric up/down dimming of the RGB LEDs. In other words, the LED driver PWM output varies in a ratiometric manner. By a ratiometric approach the emitted color of an RGB LED remains the same regardless of the initial magnitudes of the R/G/B PWM outputs. For example, if the PWM output of the red LED output is doubled, the output of green LED is doubled also. * 02 -- Bit [0] D9_RATIO_EN - 1 = enables ratiometric dimming for D9 output. - 0 = disables ratiometric dimming for D9 output. 03 OUTPUT DIRECT/RATIOMETRIC LSB * 03 -- Bit [7] D8_RATIO_EN - 1 = enables ratiometric dimming for D8 output. - 0 = disables ratiometric dimming for D8 output. - * 03 -- Bit [0] D1_RATIO_EN to Bit [6] D7_RATIO_EN - The options for D1 output to D7 output are the same as previous: see 03 -- Bit [7]. - 30 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 04 OUTPUT ON/OFF CONTROL MSB * 04 -- Bit [0] D9_ON - 1 = D9 output ON. - 0 = D9 output OFF. - Note: Engine mapping overrides this control. 05 OUTPUT ON/OFF CONTROL MSB * 05 -- Bit [7] D8_ON - 1 = D8 output ON. - 0 = D8 output OFF. - Note: Engine mapping over rides this control. * 05 -- Bit [0] D1_ON to Bit [6] D7_ON - The options for D1 output to D7 output are the same as above -- see the "05 -- Bit [7]" section. 06 D1 CONTROL This is the register used to assign the D1 output to the MASTER FADER group 1, 2, or 3, or none of them. Also, this register sets the correction factor for the D1 output temperature compensation and selects between linear and logarithmic PWM brightness adjustment. By using logarithmic PWM-scale the visual effect looks like linear. When the logarithmic adjustment is enabled, the device handles internal PWM values with 12-bit resolution. This allows very fine-grained PWM control at low PWM duty cycles. * 06 -- Bit [7:6] MAPPING - 00 = no master fader set, clears master fader set for D1. Default setting. - 01 = MASTER FADER1 controls the D1 output. - 10 = MASTER FADER2 controls the D1 output. - 11 = MASTER FADER3 controls the D1 output. - The duty cycle on D1 output is the D1 PWM register value (address 16H) multiplied with the value in the MASTER FADER register. * 06 -- Bit [5] LOG_EN - - 0 = linear adjustment. - 1 = logarithmic adjustment. - This bit is effective for both the program execution engine control and direct PWM control. * 06 -- Bit [4:0] TEMP_COMP - The reference temperature is 25C (that is, the temperature at which the compensation has no effect) and the correction factor (slope) can be set in 0.1% 1/C steps to any value between -1.5% 1/C and +1.5% 1/C, with a default to 0.0% 1/C. TEMP_COMP BITS CORRECTION FACTOR (%) 00000 Not activated - default setting after reset. 11111 -1.5 1/C 11110 -1.4 1/C ... ... 10001 -0.1 1/C 10000 0 1/C 00001 +0.1 1/C ... ... 01110 +1.4 1/C 01111 +1.5 1/C Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 31 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com The PWM duty cycle at temperature T (in centigrade) can be obtained as follows: PWMF = [PWMS - (25 - T) x correction factor x PWMS] / 2, where PWMF is the final duty cycle at temperature T, PWMS is the set PWM duty cycle (PWM duty cycle is set in registers 16H to 1EH) and the value of the correction factor is obtained from the table above. For example, if the set PWM duty cycle in register 16H is 90%, temperature T is -10C, and the chosen correction factor is 1.5% 1/C, the final duty-cycle PWMF for D1 output is [90% - (25C - (-10C)) x 1.5% 1/C x 90%] / 2 = [90% - 35 x 0.015 x 90%] / 2 = 21.4%. Default setting 00000 means that the temperature compensation is non-active and the PWM output (0 to 100%) is set solely by PWM registers D1 PWM to D9 PWM. 07 D2 CONTROL to 0E D9 CONTROL * The control registers and control bits for D2 output to D9 output are similar to that given to D1, see previous 06 - Bit [5] and 06 - Bits [4:0]. 16 D1 PWM * This is the PWM duty cycle control for D1 output. D1 PWM register is effective during direct control operation; direct PWM control is active after power up by default. Note: serial bus address auto increment is not supported for register addresses from 16 to 1E. - 16 -- Bits [7:0] PWM - These bits set the D1 output PWM as shown in Figure 23. Note: if the temperature compensation is active, the maximum PWM duty cycle is 50% at 25C. This is required to allow enough headroom for temperature compensation over the temperature range -40C to +90C. 100 PWM % 75 50 25 0 00000000 10000000 11111111 PWM Bits Figure 23. Direct PWM Control Bits vs PWM Duty Cycle 17 D2 PWM to 1E D9 PWM * PWM duty cycle control for outputs D2 to D9. The control registers and control bits for D2 output to D9 output are similar to that given to D1. 26 D1 CURRENT CONTROL * D1 LED driver output current control register. The resolution is 8-bits and step size is 100 A. 32 CURRENT bits OUTPUT CURRENT (TYPICAL) 00000000 0.0 mA 00000001 0.1 mA 00000010 0.2 mA ... ... 10101111 17.5 mA default setting .... .... 11111110 25.4 mA 11111111 25.5 mA Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 27 D2 CURRENT CONTROL to 2E D9 CURRENT CONTROL * The control registers and control bits for D2 output up to D9 output are similar to that given to D1 output. 36 MISC * This register contains miscellaneous control bits. - 36 -- Bit [7] VARIABLE_D_SEL - Variable D source selection - 1 = variable D source is the LED test ADC output (LED TEST ADC). This allows, for example, program execution control with analog signal. - 0 = variable D source is the register 3C (VARIABLE). - 36 -- Bit [6] EN_AUTO_INCR - The automatic increment feature of the serial bus address enables a quick memory write of successive registers within one transmission. - 1 = serial bus address automatic increment is enabled. - 0 = serial bus address automatic increment is disabled. - 36 -- Bit [5] POWERSAVE_EN - 1 = power save mode is enabled. - 0 = power save mode is disabled. See Automatic Power-Save Mode for further details. - 36 -- Bits [4:3] CP_MODE - Charge-pump-operation mode - 00 = OFF - 01 = forced to bypass mode (1x) - 10 = forced to 1.5x mode; output voltage is boosted to 4.5 V - 11 = automatic mode selection - 36 -- Bit [2] PWM_PS_EN - Enables PWM power-save operation. Significant power savings can be achieved, for example, during ramp instruction. - 36 -- Bits [1:0] CLK_DET_EN and INT_CLK_EN - Program execution is clocked with internal 32.7-kHz clock or with an external clock. Clocking is controlled with bits INT_CLK_EN and CLK_DET_EN in the following way: - 00 = forced external clock (CLK pin). - 01 = forced internal clock. - 10 = automatic selection. - 11 = internal clock. - External clock can be used if a clock signal is present on CLK-pin. External clock frequency must be 32.7 kHz for correct operation. If a higher or a lower frequency is used, it affects the program execution engine operation speed. The detector block does not limit the maximum frequency. External clock status can be checked with read only bit EXT_CLK_USED in register address 3A, when the external clock detection is enabled (Bit [1] CLK_DET_EN = high). - If external clock is not used in the application, CLK pin should be connected to GND to avoid oscillation on this pin and extra current consumption. 37 ENGINE1 PC * Program counter starting value for program execution engine 1; a value from 0000000 to 1011111. The maximum value depends on program memory allocation between the three program execution engines. 38 ENGINE2 PC * 38 -- Bits [6:0] PC - Program counter starting value for program execution engine 2; a value from 0000000 to 1011111. 39 ENGINE3 PC * 39 -- Bits [6:0] PC - Program counter starting value for program execution engine 3; a value from 0000000 to 1011111. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 33 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 3A STATUS/INTERRUPT * 3A -- Bit [7] LEDTEST_MEAS_DONE - This bit indicates when the LED test is done, and the result is written to the LED TEST ADC register. Typically the conversion takes 2.7 milliseconds to complete. - 1 = LED test done. - 0 = LED test not done. - This bit is a read-only bit, and it is cleared (to 0) automatically after a read operation. * 3A -- Bit [6] MASK_BUSY - Mask bit for interrupts generated by STARTUP_BUSY or ENGINE_BUSY. - 1 = Interrupt events are masked; that is, no external interrupt is generated from STARTUP_BUSY or ENGINE_BUSY event (default). - 0 = External interrupt are generated when STARTUP_BUSY or ENGINE_BUSY condition is no longer true. Reading the register 3A clears the status bits [5:4] and releases INT pin to high state. * 3A -- Bit [5] STARTUP_BUSY - A status bit which indicates that the device is running the internal start-up sequence. See Modes Of Operation for details. - 1 = internal start-up sequence running Note: STARTUP_BUSY = 1 always when CHIP_EN bit is 0. - 0 = internal start-up sequence completed * 3A -- Bit [4] ENGINE_BUSY - A status bit which indicates that a program execution engine is clearing internal registers. Serial bus master should not write or read program memory, or registers 00H, 37H to 39H or 4CH to 4EH, when this bit is set to 1. - 1 = at least one of the engines is clearing internal registers - 0 = engine ready * 3A -- Bit [3] EXT_CLK_USED - 1 = external clock detected - 0 = external clock not detected - This bit is high when external clock signal on CLK pin is detected. CLK_DET_EN bit high in address 36 enables the clock detection. * 3A -- Bits [2:0] ENG1_INT, ENG2_INT, ENG3_INT - 1 = interrupt set. - 0 = interrupt unset/cleared. - Interrupt bits for program execution engine 1, 2 and 3, respectively. These bits are set by END or INT instruction. Reading the interrupt bit clears the interrupt. 3B GPO The LP5523 has one general purpose output pin (GPO). The status of the pin can be controlled with this register. Also, INT pin can be configured to function as a GPO by setting the bit INT_CONF. When INT is configured to function as a GPO, output level is defined by the VDD voltage. * 3B -- Bit [2] INT_CONF - 0 = INT pin is set to function as an interrupt pin (default). - 1 = INT pin is configured to function as a GPO. * 3B -- Bit [1] GPO - 0 = GPO pin state is low. - 1 = GPO pin state is high. - GPO pin is a digital CMOS output, and no pulldown resistor is needed. * 3B -- Bit [0] INT_GPO - 0 = INT pin state is low (if INT_CONF = 1). - 1 = INT pin state is high (if INT_CONF = 1). - When the GPO function of the INT pin is disabled, it operates as an open drain pin. INT signal is active low; that is, when an interrupt signal is sent, the pin is pulled to GND. External pullup resistor is needed for proper functionality. 34 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 3C VARIABLE * 3C -- Bits [7:0] VARIABLE - These bits are used for storing a global 8-bit variable. Variable can be used to control program flow. 3D RESET * 3D -- Bits [7:0] RESET - Writing 11111111 into this register resets the LP5523. Internal registers are reset to the default values. Reading RESET register returns 00000000. 3E TEMP ADC CONTROL * 3E -- Bit [7] TEMP_MEAS_BUSY - 1 = temperature measurement active - 0 = temperature measurement done or not activated * 3E -- Bit [2] EN_TEMP_SENSOR - 1 = enables internal temperature sensor. Every time when EN_TEMP_SENSOR is written high a new measurement period is started. The length of the measurement period depends on temperature. At 25C a measurement takes 20 milliseconds. Temperature can be read from register 3F. - 0 = temp sensor disabled * 3E -- Bit [1] CONTINUOUS _CONV - This bit is effective when EN_TEMP_SENSOR = 1. - 1 = continuous temperature measurement. Not active when the device is in power save. - 0 = new temperature measurement period initiated during start-up or after exit from power-save mode. * 3E -- Bit [0] SEL_EXT_TEMP - 1 = temperature compensation source register addr 40H - 0 = temperature compensation source register addr 3FH 3F TEMPERATURE READ * 3F -- Bits [7:0] TEMPERATURE - These bits are used for storing an 8-bit temperature reading acquired from the internal temperature sensor. This register is a read-only register. Temperature reading is stored in 8-bit two's complement format -- see the following table: TEMPERATURE READ BITS TEMPERATURE INTERPRETATION (TYPICAL) (C) 11010111 -41 11011000 -40 ... ... 11111110 -2 11111111 -1 00000000 0 00000001 1 00000010 2 ... ... 01011000 88 01011001 89 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 35 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 40 TEMPERATURE WRITE * 40 -- Bits [7:0] TEMPERATURE - These bits are used for storing an 8-bit temperature reading acquired from an external sensor, if such a sensor is used. Temperature reading is stored in 8-bit two's complement format, like in 3F TEMPERATURE READ register. NOTE When writing temperature data outside the range of the temperature compensation: Values greater than 89C are set to 89C; values less than -39C are set to -39C. 41 LED TEST CONTROL * LED test control register - 41 -- Bit [7] EN_LEDTEST_ADC - Writing this bit high (1) fires single LED test conversion. LED test measurement cycle is 2.7 milliseconds. * 41 -- Bit [6] EN_LEDTEST_INT - 1 = interrupt signal is sent to the INT pin when the LED test is accomplished. - 0 = no interrupt signal is sent to the INT pin when the LED test is accomplished. - Interrupt can be cleared by reading STATUS/INTERRUPT register 3A. * 41 -- Bit [5] CONTINUOUS_CONV - 1 = continuous LED test measurement. Not active in power-save mode. - 0 = continuous conversion is disabled. * 41 -- Bits [4:0] LED__TEST_CTRL - These bits are used for choosing the LED driver output to be measured. VDD, INT-pin, and charge-pump output voltage can be measured, also. LED_TEST_CTRL BITS MEASUREMENT 00000 D1 00001 D2 00010 D3 00011 D4 00100 D5 00101 D6 00110 D7 00111 D8 01000 D9 01001 to 01110 Reserved 01111 VOUT 10000 VDD 10001 INT-pin voltage 10010 to 11111 N/A 42 LED TEST ADC * 42 -- Bits [7:0] LED_TEST_ADC - This is used to store the LED test result. Read-only register. LED test ADC's least significant bit corresponds to 30 mV. The measured voltage V (typical) is calculated as follows: V = (RESULT(DEC) x 0.03 - 1.478 V. For example, if the result is 10100110 = 166(DEC), the measured voltage is 3.5 V (typical). See Figure 24. 36 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 5 VOLTAGE (V) 4 3 2 1 0 40 90 140 190 RESULT (DEC) Figure 24. LED Test Results vs Measured Voltage 45 ENGINE1 VARIABLE A * 45 -- Bits [7:0] VARIABLE FOR ENGINE1 - These bits are used for Engine 1 local variable. Read-only register. 46 ENGINE2 VARIABLE A * 46 -- Bits [7:0] VARIABLE FOR ENGINE2 - These bits are used for Engine 2 local variable. Read-only register. 47 ENGINE3 VARIABLE A * 47 -- Bits [7:0] VARIABLE FOR ENGINE3 - These bits are used for Engine 3 local variable. Read-only register. 48 MASTER FADER1 * 48 -- Bits [7:0] MASTER_FADER - An 8-bit register to control all the LED-drivers mapped to MASTER FADER1. Master fader allows the user to control dimming of multiple LEDS with a single serial bus write. This is a faster method to control the dimming of multiple LEDs compared to the dimming done with the PWM registers (address 16H to 1EH), which would need multiple writes. 49 MASTER FADER2 * 49 -- Bits [7:0] MASTER_FADER - An 8-bit register to control all the LED-drivers mapped to MASTER FADER2. See MASTER FADER1 description. 4A MASTER FADER3 * 4A -- Bits [7:0] MASTER_FADER - An 8-bit register to control all the LED-drivers mapped to MASTER FADER3. See MASTER FADER1 description. 4C ENG1 PROG START ADDR * Program memory allocation for program execution engines is defined with PROG START ADDR registers. - 4C -- Bits [6:0] -- ADDR - Engine 1 program start address. 4D ENG2 PROG START ADDR * 4D -- Bits [6:0] -- ADDR - Engine 2 program start address. 4E ENG3 PROG START ADDR * 4E -- Bits [6:0] -- ADDR - Engine 3 program start address. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 37 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 4F PROG MEM PAGE SELECT * 4F -- Bits [2:0] -- PAGE_SEL - These bits select the program memory page. The program memory is divided into six pages of 16 instructions; thus, the total amount of the program memory is 96 instructions. 70H ENG1 MAPPING MSB * Valid engine 1-to-LED -mapping information can be read from ENG1 MAPPING register. * 70H -- Bit [7] GPO - 1 = GPO pin is mapped to the program execution engine 1. - 0 = GPO pin non-mapped to the program execution engine 1. * 70H -- Bit [0] D9 - 1 = D9 pin is mapped to the program execution engine 1. - 0 = D9 pin non-mapped to the program execution engine 1. 71H ENG1 MAPPING LSB * 71H -- Bit [7] D8 - 1 = D8 pin is mapped to the program execution engine 1. - 0 = D8 pin non-mapped to the program execution engine 1. * 71H -- Bit [6] D7 - 1 = D7 pin is mapped to the program execution engine 1. - 0 = D7 pin non-mapped to the program execution engine 1. * 71H -- Bit [5] D6 - 1 = D6 pin is mapped to the program execution engine 1. - 0 = D6 pin non-mapped to the program execution engine 1. * 71H -- Bit [4] D5 - 1 = D5 pin is mapped to the program execution engine 1. - 0 = D5 pin non-mapped to the program execution engine 1. * 71H -- Bit [3] D4 - 1 = D4 pin is mapped to the program execution engine 1. - 0 = D4 pin non-mapped to the program execution engine 1. * 71H -- Bit [2] D3 - 1 = D3 pin is mapped to the program execution engine 1. - 0 = D3 pin non-mapped to the program execution engine 1. * 71H -- Bit [1] D2 - 1 = D2 pin is mapped to the program execution engine 1. - 0 = D2 pin non-mapped to the program execution engine 1. * 71H -- Bit [0] D1 - 1 = D1 pin is mapped to the program execution engine 1. - 0 = D1 pin non-mapped to the program execution engine 1. 72H ENG2 MAPPING MSB * Valid engine 2-to-LED-mapping information can be read from ENG2 MAPPING register. * 72H -- Bit [7] GPO - See description above for ENG1 MAPPING register. * 72H -- Bit [0] D9 - See previous description for ENG1 MAPPING register. 73H ENG2 MAPPING LSB * 73H -- Bit [7] D8 to Bit [0] D1 * See previous description for ENG1 MAPPING register. 74H ENG3 MAPPING MSB * Valid engine 3-to-LED -mapping information can be read from ENG3 MAPPING register. 38 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com * * SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 74H -- Bit [7] GPO - See description above for ENG1 MAPPING register. 74H -- Bit [0] D9 - See description above for ENG1 MAPPING register. 75H ENG3 MAPPING LSB * 75H -- Bit [7] D8 to Bit [0] D1 - See previous description for ENG1 MAPPING register. 76H GAIN_CHANGE_CTRL * With hysteresis and timer bits the user can optimize the charge pump performance to better meet the requirements of the application at hand. Some applications need to be optimized for efficiency and others need to be optimized for minimum EMI, for example. * 76H - Bits[7:6] THRESHOLD - Threshold voltage (typical) pre-setting. Bits set the threshold voltage at which the charge-pump gain changes from 1.5x to 1x. The threshold voltage is defined as the voltage difference between highest voltage output (D1 to D6) and input voltage VDD: VTHRESHOLD = VDD - MAX(voltage on D1 to D6). - If VTHRESHOLD is larger than the set value (100 mV to 400 mV), the charge pump is in 1x mode. - 00 = 400 mV - 01 = 300 mV - 10 = 200 mV - 11 = 100 mV - NOTE Values above are typical and should not be used as product-specification. NOTE Writing to threshold [7:6] bits by the user overrides factory settings. Factory settings aren't user-accessible. * * * * * 76H - Bit [5] ADAPTIVE_TRESH_EN - - 1 = Adaptive threshold enabled.0 = Adaptive threshold disabled. - 0 = Adaptive threshold disabled. Gain-change hysteresis prevents the mode from toggling back and forth (1x -> 1.5x -> 1x...) , which would cause ripple on VIN and LED flicker. When the adaptive threshold is enabled, the width of the hysteresis region depends on the choice of threshold bits (see above), saturation of the current sources, charge pump load current, PWM overlap and temperature. 76H - Bits [4:3] TIMER A forced mode change from 1.5x to 1x is attempted at the interval specified with these bits. Mode change is allowed if there is enough voltage over the LED drivers to ensure proper operation. Set FORCE_1x to 1 (see following 76H - Bit [2] FORCE_1x) to activate this feature. - 00 = 5 ms - 01 = 10 ms - 10 = 50 ms - 11 = infinite. The charge pump switches gain from 1x mode to 1.5x mode only. The gain reset back to 1x is enabled under certain conditions, for example in the powersave mode. Activates forced mode change. In forced mode, charge pump mode change from 1.5x to 1x is attempted at the constant interval specified with the TIMER bits. - 1 = forced-mode changes enabled - 0 = forced-mode changes disabled Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 39 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 7.6.3 Instruction Set The LP5523 has three independent programmable execution engines. All the program execution engines have their own program memory block allocated by the user. Note that in order to access program memory the operation mode needs to be load program, at least for one of the three program execution engines. Program execution is clocked with a 32.7-kHz clock. This clock can be generated internally or external 32-kHz clock can be connected to CLK pin. Using external clock enables synchronization of LED timing to the external clock signal. Supported instruction set is listed in the following tables: Table 4. LP5523 LED Driver Instructions Bit [15] Bit [14] ramp (1) 0 prescale ramp (2) 1 0 0 0 0 1 0 0 set_pwm (1) 0 1 0 0 0 0 0 0 (2) 1 0 0 0 0 1 0 0 0 0 prescale time 0 0 Inst. set_pwm wait (1) (2) Bit [13] Bit [12] Bit [11] Bit [10] Bit [7] Bit [9] Bit [8] step time Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] sign Bit [0] number of increments 0 prescale sign 1 1 0 0 0 step time no. of increments 0 0 0 PWM value 0 0 0 0 PWM value 0 This opcode is used with numerical operands. This opcode is used with variables. Table 5. LP5523 LED Mapping Instructions Bit [15] Bit [14] Bit [13] Bit [12] Bit [11] Bit [10] Bit [9] Bit [8] Bit [7] mux_ld_start 1 0 0 1 1 1 1 0 0 mux_map_start 1 0 0 1 1 1 0 0 0 SRAM address 0-95 mux_ld_end 1 0 0 1 1 1 0 0 1 SRAM address 0 - 95 mux_sel 1 0 0 1 1 1 0 1 0 LED select mux_clr 1 0 0 1 1 1 0 1 0 0 0 0 0 mux_map_next 1 0 0 1 1 1 0 1 1 0 0 0 0 mux_map_prev 1 0 0 1 1 1 0 1 1 1 0 0 mux_ld_next 1 0 0 1 1 1 0 1 1 0 0 mux_ld_prev 1 0 0 1 1 1 0 1 1 1 0 mux_ld_addr 1 0 0 1 1 1 1 1 0 SRAM address 0-95 mux_map_addr 1 0 0 1 1 1 1 1 1 SRAM address 0-95 Inst. 40 Submit Documentation Feedback Bit [6] Bit [5] Bit [1] Bit [0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 Bit [4] Bit [3] Bit [2] SRAM address 0-95 Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 Table 6. LP5523 Branch Instructions Inst. rst Bit [15] Bit [14] Bit [13] Bit [12] Bit [11] Bit [10] Bit [9] Bit [8] Bit [7] 0 0 0 0 0 0 0 0 0 (1) 1 0 1 branch (2) 1 0 0 0 0 1 1 int 1 1 0 0 0 1 0 0 0 0 0 end 1 1 0 int reset 0 0 0 0 0 0 branch Bit [4] Bit [6] Bit [5] 0 0 Bit [3] Bit [2] Bit [1] Bit [0] 0 loop count 0 0 0 0 step number step number wait for trigger loop count 0 0 0 0 0 0 0 0 0 0 E2 E1 send a trigger trigger 1 1 1 ext. trig X (3) X (3) E3 jne 1 0 0 0 1 0 0 Number of instructions to be skipped if the operation returns true variable 1 variable 2 jl 1 0 0 0 1 0 1 Number of instructions to be skipped if the operation returns true variable 1 variable 2 jge 1 0 0 0 1 1 0 Number of instructions to be skipped if the operation returns true variable 1 variable 2 je 1 0 0 0 1 1 1 Number of instructions to be skipped if the operation returns true variable 1 variable 2 (1) (2) (3) E2 E1 ext. trig X (3) X (3) E3 0 This opcode is used with numerical operands. This opcode is used with variables. X means do not care. Table 7. LP5523 Data Transfer And Arithmetic Instructions (1) (2) Inst. Bit [15] Bit [14] Bit [13] Bit [12] ld Bit [11] Bit [10] Bit [9] Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] 1 0 0 1 target variable 0 0 8-bit value add (1) 1 0 0 1 target variable 0 1 8-bit value add (2) 1 0 0 1 target variable 1 1 sub (1) 1 0 0 1 target variable 1 0 sub (2) 1 0 0 1 target variable 1 1 0 0 0 0 Bit [2] variable 1 Bit [1] Bit [0] variable 2 8-bit value 0 0 0 1 variable 1 variable 2 This opcode is used with numerical operands. This opcode is used with variables. 7.6.4 LED Driver Instructions 7.6.4.1 Ramp This is the instruction useful for smoothly changing from one PWM value into another PWM value on the D1 to D9 outputs; in other words, generating ramps (with a negative or positive slope). The LP5523 allows programming very fast and very slow ramps. Ramp instruction generates a PWM ramp, using the effective PWM value as a starting value. At each ramp step the output is incremented/decremented by one unit, unless the number of increments is 0. Time span for one ramp step is defined with prescale bit [14] and step time bits [13:9]. Prescale = 0 sets 0.49 ms cycle time and prescale = 1 sets 15.6 ms cycle time; so the minimum time span for one step is 0.49 ms (prescale x step time span = 0.49 ms x 1) and the maximum time span is 15.6 ms x 31 = 484 ms/step. Number of increments value defines how many steps are taken during one ramp instruction; increment maximum value is 255d, which corresponds increment from zero value to the maximum value. If PWM reaches minimum/maximum value (0/255) during the ramp instruction, ramp instruction is executed to the end regardless of saturation. This enables ramp instruction to be used as a combined ramp and wait instruction. Note: Ramp instruction is wait instruction when the increment bits [7:0] are set to zero. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 41 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Programming ramps with variables is very similar to programming ramps with numerical operands. The only difference is that step time and number of increments are captured from variable registers, when the instruction execution is started. If the variables are updated after starting the instruction execution, it has no effect on instruction execution. Again, at each ramp step the output is incremented/decremented by one unless increment is 0. Time span for one step is defined with prescale and step time bits. Step time is defined with variable A, B, C or D. Variables A, B and C are set with ld-instruction. Variable D is a global variable and can be set by writing the VARIABLE register (address 3C). LED TEST ADC register (address 42) can be used as a source for the variable D, as well. Note: Variable A is the only local variable that can be read throughout the serial bus. Of course, the variable stored in 3CH can be read (and written) as well. Setting register 06H, 07H, or 08H bit LOG_EN high/low sets logarithmic (1) or linear ramp (0). By using the logarithmic ramp setting the visual effect appears like a linear ramp, because the human eye behaves in a logarithmic way. NAME prescale sign VALUE (d) DESCRIPTION 0 Divides master clock (32.7 kHz) by 16 = 2048 Hz -> 0.488 ms cycle time 1 Divides master clock (32.7 kHz) by 512 = 64 Hz -> 15.625 ms cycle time 0 Increase PWM output 1 Decrease PWM output step time (1) 1 - 31 One ramp increment done in (step time) x (prescale). # of increments (1) 0 - 255 The number of increment/decrement cycles. Note: Value 0 takes the same time as increment by 1, but it is the wait instruction. One ramp increment done in (step time) x (prescale). Step time is loaded with the value (5 LSB bits) of the variable defined below. 0 = local variable A step time (2) 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable D value, or register address 42H value. The value of the variable should be from 00001b to 11111b (1d to 31d) for correct operation. The number of increment/decrement cycles. Value is taken from variable following defined: 0 = local variable A # of increments (2) 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable D value, or register address 42H value. (1) (2) Valid for numerical operands. Valid for variables. 7.6.4.2 Ramp Instruction Application Example Suppose that the LED dimming is controlled according to the linear scale and effective PWM value at the moment t = 0 is 140d (approximately 55%), as shown in Figure 25, and goal is to reach a PWM value of 148d (approximately 58%) at the moment t = 1.5 s. The parameters for the RAMP instruction are: * Prescale = 1 15.625 ms cycle time * Step time = 12 step time span is 12 x 15.625 ms = 187.5 ms * Sign = 0 increase PWM output * # of increments = 8 take 8 steps 42 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 DIMMING CONTROL 148 147 146 145 STEP TIME SPAN = 187.5ms 144 143 142 141 140 RAMP INSTRUCTION 375 750 1125 0 0 1 2 3 4 5 6 1500 TIME ELAPSED (ms) 7 8 STEP COUNT Figure 25. Example of Ramp Instruction 7.6.4.3 Set_PWM This instruction is used for setting the PWM value on the outputs D1 to D9 without any ramps. Set PWM output value from 0 to 255 with PWM value bits [7:0]. Instruction execution takes sixteen 32 kHz clock cycles (=488 s). NAME PWM value (i) (1) VALUE (d) 0 - 255 DESCRIPTION PWM output duty cycle 0 - 100% 0 = local variable A variable (ii) (2) 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable D value, or register address 42H value. (1) (2) Valid for numerical operands. Valid for variables. 7.6.4.4 Wait When a wait instruction is executed, the engine is set in wait status, and the PWM values on the outputs are frozen. NAME prescale time VALUE (d) DESCRIPTION 0 Divide master clock (32.7 kHz) by 16 which means 0.488-ms cycle time. 1 Divide master clock (32 768 Hz) by 512 which means 15.625-ms cycle time. 1 - 31 Total wait time is = (time) x (prescale). Maximum 484 ms, minimum 0.488 ms. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 43 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 7.6.5 LED Mapping Instructions These instructions define the engine-to-LED mapping. The mapping information is stored in a table, which is stored in the SRAM (program memory of the LP5523). LP5523 has three program execution engines which can be mapped to 9 LED drivers or to one GPO pin. One engine can control one or multiple LED drivers. There are totally eleven instructions for the engine-to-LED-driver control: mux_ld_start, mux_map_start, mux_ld_end, mux_sel, mux_clr, mux_map_next, mux_map_prev, mux_ld_next, mux_ld_prev, mux_ld_addr and mux_map_addr. MUX_LD_START; MUX_LD_END Mux_ld_start and mux_ld_end define the mapping table location in the memory. NAME SRAM address VALUE (d) 0-95 DESCRIPTION Mapping table start/end address MUX_MAP_START Mux_map_start defines the mapping table start address in the memory, and the first row of the table is activated (mapped) at the same time. NAME SRAM address VALUE (d) 0-95 DESCRIPTION Mapping table start address MUX_SEL With mux_sel instruction one, and only one, LED driver (or the GPO-pin) can be connected to a program execution engine. Connecting multiple LEDs to one engine is done with the mapping table. After the mapping has been released from an LED, PWM register value still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state. NAME VALUE (d) DESCRIPTION 0 = no drivers selected 1 = LED1 selected LED select 0-16 2 = LED2 selected ... 9 = LED9 selected 16 = GPO MUX_CLR Mux_clr clears engine-to-driver mapping. After the mapping has been released from an LED, the PWM register value still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state. MUX_MAP_NEXT This instruction sets the next row active in the mapping table each time it is called. For example, if the 2nd row is active at this moment, after mux_map_next instruction call the 3rd row is active. If the mapping table end address is reached, activation rolls to the mapping table start address next time when the mux_map_next instruction is called. Engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state. MUX_LD_NEXT Similar than the mux_map_next instruction, but only the index pointer is set to point to the next row; that is, no mapping is set, and the engine-to-LED-driver connection is not updated. MUX_MAP_PREV 44 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 This instruction sets the previous row active in the mapping table each time it is called. For example, if the 3rd row is active at this moment, after mux_map_prev instruction call the 2nd row is active. If the mapping table start address is reached, activation rolls to the mapping table end address next time the mux_map_prev instruction is called. Engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state. MUX_LD_PREV Similar than the mux_map_prev instruction, but only the index pointer is set to point to the previous row; that is, no mapping is set, and the engine-to-LED-driver connection is not updated. MUX_MAP_ADDR Mux_map_addr sets the index pointer to point the mapping table row defined by bits [6:0] and sets the row active. Engine does not push a new PWM value to the LED driver output before set_pwm or ramp instruction is executed. If the mapping has been released from an LED, the value in the PWM register still controls the LED brightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state. NAME VALUE (d) SRAM address 0-95 DESCRIPTION Any SRAM address containing mapping data. MUX_LD_ADDR Mux_ld_addr sets the index pointer to point the mapping table row defined by bits [6:0], but the row is not set active. NAME VALUE (d) SRAM address 0-95 DESCRIPTION Any SRAM address containing mapping data. 7.6.6 Branch Instructions BRANCH Branch instruction is mainly indented for repeating a portion of the program code several times. Branch instruction loads step number value to program counter. Loop count parameter defines how many times the instructions inside the loop are repeated. The LP5523 supports nested looping; that is, loop inside loop. The number of nested loops is not limited. Instruction takes sixteen 32 kHz clock cycles. NAME ACCEPTED VALUE (d) DESCRIPTION loop count (1) 0-63 The number of loops to be done. 0 means an infinite loop. step number 0-95 The step number to be loaded to program counter. Selects the variable for loop count value. Loop count is loaded with the value of the variable defined below. loop count (2) 0 = local variable A 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable D value, or register address 42H value (1) (2) Valid for numerical operands. Valid for variables. INT Send interrupt to processor by pulling the INT pin down and setting corresponding status bit high. Interrupt can be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3A. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 45 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 NAME www.ti.com VALUE (d) int DESCRIPTION 0 No interrupt is sent. PWM register values remain intact. 1 Reset program counter value to 0 and send interrupt to processor by pulling the INT pin down and setting corresponding status bit high to notify that program has ended. PWM register values remains intact. Interrupt can be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3A. 0 Reset program counter value to 0 and hold. PWM register values remains intact. Reset program counter value to 0 and hold. PWM register values of the non-mapped drivers remains. PWM register values of the mapped drivers is set to 0000 0000. reset 1 On completion of int instruction with this bit set to 1 the master fader registers are set to zero as follows: Program execution engine 1 sets MASTER FADER 1 (48H) to zero, engine 2 sets MASTER FADER 2 (49H) to zero and engine 3 sets MASTER FADER 3 (4AH) to zero. RST Rst instruction resets Program Counter register (address 37H, 38H, or 39H) and continues executing the program from the program start address defined in 4C-4E. Instruction takes sixteen 32 kHz clock cycles. Note that default value for all program memory registers is 0000H, which is the rst instruction. END End program execution. Instruction takes sixteen 32-kHz clock cycles. TRIGGER Wait or send triggers can be used to, for example, synchronize operation between the program execution engines. Send trigger instruction takes sixteen 32 kHz clock cycles and wait for trigger takes at least sixteen 32 kHz clock cycles. The receiving engine stores the triggers which have been sent. Received triggers are cleared by wait for trigger instruction. Wait for trigger instruction is executed until all the defined triggers have been received. (Note: several triggers can be defined in the same instruction.) External trigger input signal must stay low for at least two 32 kHz clock cycles to be executed. Trigger output signal is three 32 kHz clock cycles long. External trigger signal is active low; that is, when trigger is sent/received the pin is pulled to GND. Send external trigger is masked; that is, the device that has sent the trigger does not recognize it. If send and wait external trigger are used on the same instruction, the send external trigger is executed first, then the wait external trigger. NAME VALUE (d) DESCRIPTION wait for trigger 0 - 31 Wait for trigger from the engine(s). Several triggers can be defined in the same instruction. Bit [7] engages engine 1, bit [8] engine 2, bit [9] engine 3 and bit [12] is for external trigger I/O. Bits [10] and [11] are not in use. send a trigger 0 - 31 Send a trigger to the engine(s). Several triggers can be defined in the same instruction. Bit [1] engages engine 1, bit [2] engine 2, bit [3] engine 3 and bit [6] is for external trigger I/O. Bits [4] and [5] are not in use. The LP5523 instruction set includes the following conditional jump instructions: jne (jump if not equal); jge (jump if greater or equal); jl (jump if less); je (jump if equal). If the condition is true, a certain number of instructions are skipped (that is, the program jumps forward to a location relative to the present location). If condition is false, the next instruction is executed. NAME VALUE (d) DESCRIPTION 0 - 31 The number of instructions to be skipped when the statement is true. Note: value 0 means redundant code. number of instructions to be skipped if the operation returns true. Defines the variable to be used in the test: 0 = local variable A variable 1 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable, or register address 42H value. 46 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 NAME VALUE (d) DESCRIPTION Defines the variable to be used in the test: 0 = local variable A variable 2 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable, or register address 42H value. 7.6.7 Arithmetic Instructions LD This instruction is used to assign a value into a variable; the previous value in that variable is overwritten. Each of the engines have two local variables, called A and B. The variable C is a global variable. NAME VALUE (d) DESCRIPTION 0 = variable A target variable 0-2 1 = variable B 2 = variable C 8-bit value 0 - 255 Variable value ADD Operator either adds 8-bit value to the current value of the target variable, or adds the value of the variable 1 (A, B, C or D) to the value of the variable 2 (A, B, C or D) and stores the result in the register of variable A, B or C. Variables overflow from 255 to 0. NAME VALUE (d) 8-bit value (1) 0 - 255 DESCRIPTION The value to be added. 0 = variable A target variable 0-2 1 = variable B 2 = variable C 0 = local variable A variable 1 (2) 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable, or register address 42H value. 0 = local variable A variable 2 (2) 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable, or register address 42H value. (1) (2) Valid for numerical operands. Valid for variables. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 47 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com SUB SUB Operator either subtracts 8-bit value from the current value of the target variable, or subtracts the value of the variable 2 (A, B, C or D) from the value of the variable 1 (A, B, C or D) and stores the result in the register of target variable (A, B or C). Variables overflow from 0 to 255. NAME 8-bit value (1) VALUE (d) 0 - 255 DESCRIPTION The value to be added. 0 = variable A target variable 0-2 1 = variable B 2 = variable C 0 = local variable A variable 1 (2) 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable, or register address 42H value. 0 = local variable A variable 2 (2) 0-3 1 = local variable B 2 = global variable C 3 = register address 3CH variable, or register address 42H value. (1) (2) 48 Valid for numerical operands. Valid for variables. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LP5523 enables up to four parallel devices together, which can drive up to 12 RGB LEDs or 36 single LEDs. Figure 26 shows the connections for two LP5523 devices for six RGB LEDs. Note that D7, D8, and D9 outputs are used for the red LEDs. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (R3 and R4; the pullup resistors are normally located on the bus master.). In typical applications, values of 1.8 k to 4.7 k are used, depending on the bus capacitance, I/O voltage, and the desired communication speed. INT and TRIG are open-drain pins, which must have pullup resistors. Typical values for R1 and R2 are from 120 k to 180 k for two devices. 8.2 Typical Applications 8.2.1 Using Two LP5523 Devices in Same Application The LP5523 enables up to four parallel devices together, which can drive up to 12 RGB LEDs or 36 single LEDs. This diagram shows the connections for two LP5523 devices for six RGB LEDs. Note that D7, D8 and D9 outputs are used for the red LEDs. The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (R3 and R4; The pullup resistors are normally located on the bus master.). In typical applications values of 1.8 k to 4.7 k are used, depending on the bus capacitance, I/O voltage, and the desired communication speed. INT and TRIG are open-drain pins, so they must have pullup resistors. Typical values for R1 and R2 are from 120 k to 180 k for two devices. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 49 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com Typical Applications (continued) C1 0.47 PF VIN = 2.7V TO 5.5V C2 0.47 PF COUT1 1 PF C1+ C1- C2+ C2- VOUT VDD D1 CIN1 VIO 1 PF D2 D7 R R1 R2 R3 B G B G B G R4 D3 SCL D4 SDA INT MCU TRIG D8 LP5523 R G EN CLK D5 D6 ASEL0 D9 ASEL1 R GND GPO C3 0.47 PF VIN CIN2 1 PF C4 0.47 PF C1+ C1- C2+ C2- VOUT COUT2 1 PF D1 VDD D2 D7 SCL B G R B G R B G D3 SDA D4 INT TRIG R D8 LP5523 EN CLK D5 VIO ASEL0 D6 ASEL1 D9 GND GPO Figure 26. Typical Application Circuits 8.2.1.1 Design Requirements 50 DESIGN PARAMETER EXAMPLE VALUE Input voltage range 2.7 V to 5.5 V LED VF (maximum) 3.6 V LED current 25.5 mA maximum Input capacitor CIN1 = CIN2 = 1 F Output capacitor COUT1 = COUT2 = 1 F Charge pump fly capacitors C1 = C2 = C3 = C4 = 0.47 F Charge pump mode 1.5x or automatic Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Recommended External Components The LP5523 requires 4 external capacitors for proper operation. Surface-mount multi-layer ceramic capacitors are recommended. Tantalum and aluminium capacitors are not recommended because of their high ESR. For the flying capacitors (C1 and C2) always use multi-layer ceramic capacitors. These capacitors are small, inexpensive, and have very low equivalent series resistance (ESR < 20 m typical). Ceramic capacitors with X7R or X5R temperature characteristic are preferred for use with the LP5523. These capacitors have tight capacitance tolerance (as good as 10%) and hold their value over temperature (X7R: 15% over -55C to +125C; X5R: 15% over -55C to +85C). Capacitors with Y5V or Z5U temperature characteristic are generally not recommended for use with the LP5523. Capacitors with these temperature characteristics typically have wide capacitance tolerance (+80%, -20%) and vary significantly over temperature (Y5V: +22%, -82% over -30C to +85C range; Z5U: +22%, -56% over 10C to 85C range). Under some conditions, a nominal 1 F Y5V or Z5U capacitor could have a capacitance of only 0.1 F. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum capacitance requirements of the LP5523. For proper operation it is necessary to have at least 0.24 F of effective capacitance for each of the flying capacitors under all operating conditions. The output capacitor COUT directly affects the magnitude of the output ripple voltage. In general, the higher the value of COUT, the lower the output ripples magnitude. For proper operation TI recommends having at least 0.50 F of effective capacitance for CIN and COUT under all operating conditions. The voltage rating of all four capacitors must be 6.3 V; 10 V is recommended. Table 8 lists recommended external components from some leading ceramic capacitor manufacturers. It is strongly recommended that the LP5523 circuit be thoroughly evaluated early in the design-in process with the mass-production capacitors of choice. This helps ensure that any variability in capacitance does not negatively impact circuit performance. Table 8. Recommended External Components MODEL TYPE VENDOR VOLTAGE RATING PACKAGE SIZE 1 F for COUT and CIN C1005X5R1A105K Ceramic X5R TDK 10V 0402 LMK105BJ105KV-F Ceramic X5R Taiyo Yuden 10V 0402 ECJ0EB1A105M Ceramic X5R Panasonic 10V 0402 ECJUVBPA105M Ceramic X5R, array of two Panasonic 10V 0504 C1005X5R1A474K Ceramic X5R TDK 10V 0402 LMK105BJ474KV-F Ceramic X5R Taiyo Yuden 10V 0402 ECJ0EB0J474K Ceramic X5R Panasonic 6.3V 0402 470 nF for C1 and C2 LEDs User defined. Note that D7, D8 and D9 outputs are powered from VDD when specifying the LEDs. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 51 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 8.2.1.3 Application Curves 3.6V VDD VOLTAGE (500 mV/DIV) VOLTAGE (500 mV/DIV) VDD 3.6V 2.8V 4.5V 4.2V 2.8V 4.2V 3.6V VOUT 3.6V VOUT TIME (2 ms/DIV) TIME (2 ms/DIV) 6 LEDs at 1 mA ,100% PWM 6 LEDs at 1 mA ,100% PWM Figure 28. Line Transient and Charge-Pump Automatic Gain Change (1x To 1.5x) Figure 27. Line Transient and Charge-Pump Automatic Gain Change (1.5x To 1x) 8.2.2 Driving Haptic Feedback with LP5523 C1 0.47 PF C2 0.47 PF C1+ C1- C2+ C2- VOUT COUT 1 PF VIN CIN 1 PF VDD D1 D2 SCL D3 SDA MCU EN D4 CLK TRIG FROM SCREEN CONTROLLER GPO INT D5 LP5523 D6 TRIG ASEL0 D7 ASEL1 GND D8 D9 100 k: APPLICATION PROCESSOR CONTROL (OPTIONAL) { VDD INA OUTA OUTB INB H-DRIVER 240R/100 MHz FERRITE VIBRAP VIBRAN 1 nF 1 nF 100 k: Figure 29. Example Schematic - Vibra Motor Figure 29 depicts an example schematic for LP5523 driving a vibra motor. A vibra motor can be used for haptic feedback with touch screens and also for normal vibra operation (call indication, etc.). Battery-powered D8 and D9 outputs are used for controlling the H-driver (Microchip TC442x-series or equivalent), which drives the vibra motor. (The remaining outputs D1 to D7 can be used for LED driving, of course.) With H-driver the rotation direction of the vibra motor can be changed. For vibra operation user can load several programs to the LP5523 program memory in order to get interesting vibration effects, with changing frequency, ramps, etc. If the application processor has controls for a vibra motor they can be connected to H-Driver INA and INB as shown in Figure 29. In this case the vibra can be controlled directly with application processor and also with LP5523. If application processor control is not needed, then the 100-k resistors should be connected to GND. 52 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 A simple waveform for H-driver control is shown in Figure 30. At first the motor rotates in CW direction for 30 ms, following a rotation of 30 ms in CCW direction. The sequence is started when the TRIG signal is pulled down (active low signal). the TRIG signal is received from the touch screen controller. After the sequence is executed, the LP5523 waits for another TRIG signal to start the sequence again. TRIG signal timing is not critical; it does not have to be pulled down for the whole sequence duration like in the example. For call indication, etc. purposes the program can be changed; for example, rotation times can be adjusted to get desired haptic reaction. Direct control of D8 and D9 output is also possible through the control registers, if programming is not desired. TRIGGER SIGNAL FROM TOUCH SCREEN CONTROLLER TRIG 30 ms CW ROTATION VIBRAP 30 ms CCW ROTATION VIBRAN Figure 30. H-Driver Control Waveform 9 Power Supply Recommendations The device is designed to operate from an input voltage supply range between 2.7 V and 5.5 V. In a typical application this is from single Li-ion battery cell. This input supply must be well regulated and able to withstand maximum input current and maintain stable voltage without voltage drop even at load transition condition (startup or rapid brightness change). The resistance of the input supply rail must be low enough that the input current transient does not cause drop below a 2.7-V level in the LP5523 supply voltage. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 53 LP5523 SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 www.ti.com 10 Layout 10.1 Layout Guidelines Place capacitors as close as possible to the LP5523 device to minimize the current loops. Example of LP5523 PCB layout and component placement is seen in Figure 31. 10.2 Layout Example C1 CIN C2+ C1+ VDD GND SCL 4 C2- C1- EN CLK SDA 3 VOUT ASEL1 ASEL0 INT TRIG 2 D2 D4 D6 D8 GPO 1 D1 D3 D5 D7 D9 A B C D E COUT C2 5 = Layer 1 Routing = Layer 2 Routing = RGB LED Routing = Via Figure 31. LP5523 Layout Example 54 Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 LP5523 www.ti.com SNVS550E - SEPTEMBER 2009 - REVISED JANUARY 2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2009-2017, Texas Instruments Incorporated Product Folder Links: LP5523 55 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) (6) LP5523TM/NOPB ACTIVE DSBGA YFQ 25 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -30 to 85 5523 LP5523TMX/NOPB ACTIVE DSBGA YFQ 25 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -30 to 85 5523 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LP5523TM/NOPB DSBGA YFQ 25 250 178.0 8.4 LP5523TMX/NOPB DSBGA YFQ 25 3000 178.0 8.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.43 2.48 0.75 4.0 8.0 Q1 2.43 2.48 0.75 4.0 8.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Oct-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LP5523TM/NOPB DSBGA YFQ LP5523TMX/NOPB DSBGA YFQ 25 250 210.0 185.0 35.0 25 3000 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA YFQ0025xxx D 0.600 0.075 E TMD25XXX (Rev C) D: Max = 2.29 mm, Min = 2.23 mm E: Max = 2.29 mm, Min = 2.23 mm 4215084/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.com 12/12 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES "AS IS" AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. 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