COMPONENTS 262.144-BIT 8 x 8) ONE T PROGRAMMABLE RAM ADVANCE INFORMATION The TS27C256P is a high speed 256K bits one time electrical, mable ROM ideally suited for applications where fast turn-aro Important requirement The TS27C256P is packaged in a 28-pin dual-in-line plustic pac therefore can not be re-written Programming is performed ace standard THOMSON SEMICONDUCTEURS 255K EPROM proce Compativie to standard TS27C256 (electrical parameters, proc Programming voltage 12.5 V High speed programming 28-pin JEDEC approved pin-out Ideal for automatic insertion Also proposed in PLCC (32 pins JEDES standard) TABLE 1 ORDERING INFORMATION PART NUMBER tacc (ns} tceE (ns) toe (ns) Ven TS27C256-15 150 150 75 BVi: TS27C256-20 200 200 75 5V i TS27C256-25 250 250 100 5V + TS27C256-30 300 300 120 5V + sogram- id is an age and ding to ure amming) Operating temperature range ONE TIME PROGRAMMABLE-ROM cmos 262,144 BIT (32,768 x 8) P SUFFIX PLASTIC PACKAGE 0 Cto+ 70 CCP suffixi, -40 Cto- 85 CIVP suffix 40 Cto 105 C (TP suffix) BLOCK DIAGRAM Veco DATA OUTPUTS 00-0 GNO Ome er oe HII OE # OUTPUT ENABLE o = CHIP ENABLE = OUTPUT cE ANDO PROG LOGIC BUFFERS ~ |~-4 - Y . e DECODER . Y GATING |__.f AQ-AI4 | eo |__| AODRESS | * be INPUTS | x : . 262,144 BITS ae DECOOER : CELL MATRIX }-+4 PIN ASSIGNMENT \ 8 vee (1 I Vee ai2 ()2 2777) aia a7 (3 26f] ar3 as []4 25[] as as 5 241) ag a4 [6 23[] ai a3 7 22[] OF A2 []s 21 aio al 3 200) cE ao [10 191] 07 oo [11 i3[] 06 o1 G2 17{] 08 02 [13 161] 04 Vgg [14 15T] 03 PIN NAMES AQ Al2 Address CE Chip Enable GE Output Enable 00-07 OutputsMAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Operating temperature range Tamb TL 10TH Cc TS27C266 CP Ora+ 70 TS?7C256 VP -40 to + 85 TS27C256 1P - 40 to+ 105 Storage temperature range Tstg 65 10 + 125 Cc Supp:y voltage Vppr -O6 10 +14 Vv Input voltage AS Vint 06 to +135 Vv Except Vpp, AQ ~-0.6 10 +6.25 Max power dissipation PD 15 w Lead temperature + 300 Cc (Soldering . 10 seconds! * With respect to Vsg Note 1 Maximum ratings are those values beyond which the safety o* the device cannot be guaranteed. Except for Operating tem- perature range they are not meant to imply that the devices should be operated at these limits. The table of teristics provides conditions for actual device operation READ OPERATION (Note 2) DC CHARACTERISTICS Tamb > TL toTH, Voc =5V+t10% Vsg Electrical charac- OV (Unless othe wise specified) Characteristic Symbol Min Typ Max Unit (Note 2} input load current (Vin_- Voc or GND) lol 10 LA Ouput leakage current (Vour= Vcc or Vg, CE= VjHI llo _ - 10 uA Vpp read voltage Vpp Vec -0.? Vec v Input low voltage Vit 0.1 - 0.8 v Input high voltage (Note 2) VIH 2.0 - Vcec+l Vv Output tow voltage VoL Vv IOL= 2.1 mA - - 0.45 'OL* OnA - - 01 Output high vaitage Vou Vv IQH= - 400 bA 24 = - IOH=O RA Vee - 04 ~ Vcc supply active current (TTL levels! ] lee? = 10 40 mA aeoG =ViL, Inputs= Vj or Vip, f= 5 MHz, 1 O=0mA I Vcc supply standby current CE Vy OF Inputs Vy or Vig icespt 05 1 mA CE Veo O.1V, OF + Inputs Veo O11 Vgg | O.1Vv lecsB2 1 10 BA Vpp read current (Vpp= Voc= 5.25 V) Ippy - 10 uA AC CHARACTERISTICS (Notes 3, 4,5) Tamb = TL toTH po py oe Maximum values | Characteristic Symbol Min wn a . 1 Unit 1827C256 | T$27C256 | TS27C256 | TS27C256 | : [45 20 25 30 Address to output delay (CE= OE = VL) tACC | | 150 200 CE to output delay (OE=Vy) ICE | 150 | 200 T Output enable to output delay (CE= Vy} tog 75} 75 Output enable high to output float Tipe iNote 4) 0 50 55 (CE= Viv) | | : | doo ee Output hold from addresses, CE or OE , toH 0 whichever occured first (CE = OF = Vi, ) |CAPACITANCE (Note 5} Tamb =+ 25C, f = 1 MHz Characteristic Symbol Min Typ Max Unit Input capacitance (Vj, = OV) Cin = 4 6 pF Output capacitance (Vo47= 0 V) Cout - 8 12 pF Note 2 : Typical conditions are for operation at : Tamb =+ 25C, Voc = 5 V, Vpp = Voc, and Vsg = OV Note 3 : Vcc must be applied at the same time or before Vpp and :emoved after or at the same time as Vpp Vpp may be connected to Vc except during pragram. Note 4 : The tof compare level is determined as follows : High to THREE-STATE, the measured VQH(DC) 0.1V Low to THREE-STATE the measured VoL(DC) + 0.1V. Note 5: Capacitance is guaranteed by periodic testing. Tamb = + 29C, f= 1 MHz. AC TEST CONDITIONS (Figure 1,2) Output Load 1 TTL Gate and Cy 5100 pF input Rise and Fail Times <20ns Input Pulse Levels 0.45V to 2.4V Timing Measurement Reference Level Inputs , Outputs 0 8V and 2V Device under test 24V 2.0V Test points O8v O45 V AC testing inputs are driven at 2.4 V for a logic 1" and 0.45 V fora logic "0 Timing measurements are made at 2.0 V for a logic "1" and O.8V for a logic "0". AC WAVEFORMS (READ MODE} FIGURE 1 OUTPUT LOAD CIRCUIT CL= 100 pF (Includes fig capacitance} ADORESSES ACORESSES en CE / sc! | CE {i oe + be top HIZ ne OUTPUT = VALID CUTPUT - tacc ton Fe HI?HIGH SPEED PROGRAMMING CHARACTERISTICS oc PROGRAMMING CHARACTERISTICS Tamb * 2545C, Vec = 6.0V 40.25 V.Vpp = 12.5V203V_ Note 1) Characteristic Symbol Min Typ Max Unit 4 Input current (att inputs - Vy= Vitor Viy) input low level fall inputs) Vit -04 - 08 Vv Input high level i ~ Vid 2.0 - Veet) Vv Output low voltage during verify (ig, = 21mAl VoL - - 0.45 Vv Output high voltage during verity | lqiy=- 400 A) Vou 2.4 - Z Vv Vec supply current (Program & Verify) iec3 - - 40 mA Vpp supply current (Program - CE= Vj.) Ippo - - 30 mA AC PROGRAMMING CHARACTERISTICS Tamb = 25+ 5C, Veg = 6.0 V = 0.25 V. Vpp = 12.5 V 40.3 V Note 1} Characteristic Address set-up trme OE set-up time Data set-up trme Address hald time _ Data hoid time Output enable to output float delay Vpp setup ume Vee setup time CE initial program pulse width CE overprogram pulse width (Note 2) Data valid from OE AC TEST CONDITIONS Input rise and fall times (10% to 90%) 20ns Input pulse levels 0.45V to 2.4V Input timing reference level 0.8V and 2.0V Ouptut timing reference level 0.8V and 2.0V Note 1: Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. Note 2: topy is defined in flow chartADORESSES DATA Vpp Vii cE Vit VIH OF Vie eno HIGH SPEED PROGRAMMING WAVE FORMS }--- ---_-- PROGRAM - ~- i 22 t te } verry -- ADDRESS STABLE DATA OUT VALIO Sy e tas > ' i _ r# taH 2 DATA IN STABLE DATA OUT VALID a ! | Kt DS > ton | ! | tore i | >a \- ze i ' | VPS > i ! i \ yy! - or PW hg voltage transients which can damage the device. | | |* toes a mt so The input timing reference level is O.8V for Vy_ and 2.0V for Viy tOE and tpFP are characteristics of the device but must be accommodated by the programmer When programming the TS27C256, a 0.1 uF capacitor is *equired across Vpp and ground to suppress spurious TABLE 2. MODE SELECTION 1 Pins CE OE | Ag Vpp Vo Outputs | Mode (20) (22) (24) (1) (Say (11-13 15-19) Read Vin iL x voc Voc Dout Output disable VIL VIH x Voc Voc Hi-Z Standby Vil x x oc Veco | Hi-Z High speed . - programming vie VIH x Vpp Voc On _- { _ Se Lo Program Verify Vio ViL x ; Vpp Voc DoutT Program inhibit VIH VIH x Vpp Vee Hr-Z Electronic | VH . ! ~ ~ signature (Note 3) | VIL | VIL | more 2 | VEC; VEC CODE NOTES 2-VH=12.0V 405V 1-X can be either Vit or Vio 3 All address lines at Vj_ except AQ and AQ that is toagled * Vin (yee code om Vi (manufacturer code: 9B) 041 toHIGH SPEED PROGRAMMING FLOW CHART Start ADOR =First locat Vec=6.0V Vpp=12.5V Program tpy= 1 ms*5~5 Increment X x = 25? No Fat Program tOPWe 3.Xms No . Pass No Increment ADDR Last ADDR? Yes Vec= Vep=5.0V ompar all bytes to griginal data. Device failed Pass Device passed Fail Device failedFUNCTIONAL DESCRIPTION DEVICE OPERATION The seven modes of operation of the TS27C256 are listed in Table 2. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vpp. Read Mode The T$27C256 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, independent of device selection. Assu- ming that addresses are stable, address access time {tacc) is equal to the delay from CE to output (tce). Data is available at the outputs after a delay of tOE from the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc.tOE- Standby Mode The TS27C256 has a standby mode which reduces the maximum power dissipation to 5.25 mW. The TS27C256 is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the out- puts are in a high impedance state, independent of the OE input. Output OR-Tying Because EPROMs are usually used in larger memory arrays, we have provided two control lines which accom- modate this multiple memory connection. The two control lines allow for : a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To use these control lines most efficiently, CE (pin 20} should be decoded and used as the primary device selecting function, while OE (pin 22) should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This assures that al! deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming modes CAUTION : Exceeding 14V on pin 1(Vpp) will damage the TS27C256. Initialy, and after each erasure, all bits of the TS27C256 are in the 1 state. Data is introduced by selectively programming "Os into the desired bit locations. Al- though only 0s will be programmed, both 1" and Qs can be presented in the data word. The only way to change a 0" to a "1" is by ultraviolet light erasure The 7S27C256 is in the programming mode when the Vpp input is at 12.5 V and CE is at TTL tow. It is required that a 0.1 uF capacitor be placed across Vpp, Vcc and ground to suppress spurious voltage transients which may damage the device. The data to be program- med is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. Programming of multiple TS27C256s in parallel with the same data can be easily accomplished due to the simpli- city of the programming requirements. Like inputs of the paralleled TS27C256s may be connected together when they are programmed with the same data. A tow level TTL pulse applied to the CE input programs the paralleled TS27C256s. @ High speed programming The high speed programming algorithm described in the flow chart page 3 rapidly programs TS27C256 using an efficient and reliable method particularly suited to the production programming environment. Typical programming times for individual devices are on the order of 5 minutes. @ Program inhibit Programming of multiple 1S27C256s in parallel with different data is also easily accomplised by using the program inhibit mode. A high level on CE input inhi- bits the other TS27C256s from being programmed Except for CE, all like inputs (including OE) of the parallel TS27C256s may be common. A TTL low level pulse applied to a TS27C256 CE input with Vpp at 12.5 V will program that TS27C256. Program verify A verify may be performed on the programmed bits to determine that they were correctly programmed. The verify is performed with OE at Vic, CE at ViH and Vpp at 12.5 V. @ Electronic signature mode Electronic signature mode allows the reading out of a binary code that will identify the EPROMs manufac- turer and type. This mode is intended for use by programming equip- ment for the purpose of automatically matching the device to be programmed with its corresponding pro- gramming algorithm. This mode is functional in the 25C + 5C ambient temperature range that is requi- red when programming the 7TS27C256. To activate this mode the programming equipment must force 11.5 V to 12.5 V on address line AQ (pin 24) of the TS27C256. Two bytes may then be sequenced from the device outputs by toggling address line AO (Pin 10) from Vi_ to Vi. All other address lines must be held at Vi during electronic signature mode.PHYSICAL DIMENSIONS mm e:254.2 457 man i moe e ee alae a plete! ma a 1oimor g | : 2 1 mom monmom eno: oun by se umeramn | 4 12!) Tese geometrical position Coy 3 be elmer Ltd He 2B ons DIN Y ASIE F 144 CB- 132 cel | DATA JEDEC SITELESC COMPONENTS. - 1310 ELECTRONICS DRIVE TEL.: (214) 466-6000 - CARROLLTON, TEXAS 75006 @ TELEX: 730643 MOSTEK Thomson Components - Mostek Corporation reserves the right to make changes in specifications and other information at any time without prior notice. Information contained herein is believed to be correct, but is provided solely for guidance in product application and not as a warranty of any kind. Thomson Components - Mostek assumes no responsibility for use of this information, nor for any infringements of patents or other rights of third parties resulting from use of this information, nor for the use of any circuitry other than circuitry embodied in a Thomson Components - Mostek product. No license is granted under any patents or patent rights of 2 Thomson Components - Mostek. PRINTED IN USA Aprit 1987 Copyright 1987 by Thorr 008 024 a Publication No. 4430256 All 8