May 2008 FDP8880 / FDB8880 N-Channel PowerTrench(R) MOSFET tmM 30V, 54A, 11.6m Features rDS(ON) = 14.5m, VGS = 4.5V, ID = 40A rDS(ON) = 11.6m, VGS = 10V, ID = 40A High performance trench technology for extremely low General Description This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low r DS(ON) and fast switching speed. r DS(ON) Low gate charge High power and current handling capability RoHS Complicant DRAIN (FLANGE) GATE Application DC / DC Converters (FLANGE) DRAIN D SOURCE DRAIN GATE SOURCE TO-263AB TO-220AB FDB SERIES FDP SERIES (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 1 http://store.iiic.cc/ G S www.fairchildsemicom FDP8880 / FDB8880 0 Symbol VDSS Drain to Source Voltage Parameter Ratings 30 Units V VGS Gate to Source Voltage 20 V 54 A Drain Current Continuous (TC = 25oC, VGS = 10V) o ID Continuous (TC = 25 C, VGS = 4.5V) 48 A Continuous (Tamb = 25oC, VGS = 10V, with RJA = 43oC/W) 11 A Pulsed E AS Figure 4 A 31 mJ Single Pulse Avalanche Energy (Note 1) Power dissipation PD Derate above 25oC TJ, TSTG Operating and Storage Temperature 55 W 0.37 W/oC o -55 to 175 C Thermal Characteristics RJC Thermal Resistance Junction to Case TO-220,TO-263 RJA Thermal Resistance Junction to Ambient TO-220,TO-262 ( Note 2) 2 RJA oC/W 2.73 Thermal Resistance Junction to Ambient TO-263, 1in copper pad area 62 o C/W 43 o C/W Package Marking and Ordering Information Device Marking FDP8880 Device FDP8880 Package TO-220AB Reel Size Tube Tape Width N/A Quantity 50 units FDB8880 FDB8880 TO-263AB 330mm 24mm 800 units F F Electrical Characteristics TC = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units 30 - - - V - 1 - - 250 A - - 100 nA - 2.5 V Off Characteristics BVDSS Drain to Source Breakdown Voltage IDSS Zero Gate Voltage Drain Current IGSS Gate to Source Leakage Current ID = 250A, VGS = 0V V DS = 24V VGS = 0V TC = 150oC VGS = 20V On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 V GS = VDS, ID = 250A 1.2 ID = 40A, VGS = 10V - 0.0095 0.0116 ID = 40A, VGS = 4.5V - 0.012 0.0145 ID = 40A, VGS = 10V, TJ = 175oC - 0.015 0.019 2 http://store.iiic.cc/ www.fairchildsemicom FDP8880 / FDB8880 MOSFET Maximum Ratings TC = 25C unless otherwise noted CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance RG Gate Resistance Qg(TOT) Total Gate Charge at 10V - 1240 - - 255 - pF - 147 - pF VGS = 0.5V, f = 1MHz - 2.7 - VGS = 0V to 10V - 22 29 nC V DS = 15V, VGS = 0V, f = 1MHz Qg(5) Total Gate Charge at 5V VGS = 0V to 5V Qg(TH) Threshold Gate Charge VGS = 0V to 1V Qgs Gate to Source Gate Charge Qgs2 Gate Charge Threshold to Plateau Qgd Gate to Drain "Miller" Charge VDD = 15V ID = 40A Ig = 1.0mA pF - 12 16 nC - 1.6 2.1 nC - 3.2 - nC - 2.0 - nC - 4.8 - nC Switching Characteristics (VGS = 10V) tON Turn-On Time - - 171 ns td(ON) Turn-On Delay Time - 8 - ns tr Rise Time td(OFF) Turn-Off Delay Time tf tOFF - 107 - ns - 47 - ns Fall Time - 51 - ns Turn-Off Time - - 147 ns V V DD = 15V, ID = 40A V GS = 10V, RGS = 13.6 Drain-Source Diode Characteristics ISD = 40A - - 1.25 ISD = 3.5A - - 1.0 V Reverse Recovery Time ISD = 40A, dISD/dt = 100A/s - - 27 ns Reverse Recovered Charge ISD = 40A, dISD/dt = 100A/s - - 18 nC V SD Source to Drain Diode Voltage trr QRR Notes: 1: Starting T J = 25C, L = 34uH, IAS = 43A,Vdd = 27V, Vgs = 10V. 2: Pulse width = 100s. 3 (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 3 http://store.iiic.cc/ www.fairchildsemicom FDP8880 / FDB8880 Dynamic Characteristics FDP8880 / FDB8880 Typical Characteristics TC = 25C unless otherwise noted 60 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 40 20 0.2 0 0 0 25 50 75 100 150 125 175 25 TC , CASE TEMPERATURE (o C) Figure 1. Normalized Power Dissipation vs Case Temperature 50 75 100 125 150 TC, CASE TEMPERATURE (oC) 175 Figure 2. Maximum Continuous Drain Current vs Case Temperature 2 ZJC, NORMALIZED THERMAL IMPEDANCE 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 600 TC = 25o C IDM, PEAK CURRENT (A) FOR TEMPERATURES ABOVE 25o C DERATE PEAK TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V VGS = 4.5V 100 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) Figure 4. Peak Current Capability (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 4 http://store.iiic.cc/ www.fairchildsemicom FDP8880 / FDB8880 Typical Characteristics TC = 25C unless otherwise noted 400 500 IAS, AVALANCHE CURRENT (A) 100 ID, DRAIN CURRENT (A) If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 10s 100s 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 100 STARTING T J = 25o C 10 STARTING TJ = 150oC DC 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 0.001 40 10 100 NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching Capability 80 160 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V VGS = 4.5V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 60 40 TJ = 175oC TJ = 25oC 20 TJ = -55 oC VGS = 3.5V 120 VGS = 10V VGS = 3V 80 TC = 25 oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 VGS = 2.5V 0 0 1.5 2.0 2.5 3.0 3.5 VGS, GATE TO SOURCE VOLTAGE (V) 0 4.0 Figure 7. Transfer Characteristics 1.7 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 0.5 0.75 1.0 Figure 8. Saturation Characteristics 20 ID = 54A 0.25 VDS , DRAIN TO SOURCE VOLTAGE (V) 16 12 ID = 5A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.53 1.36 1.19 1.02 0.85 VGS = 10V, ID = 54A 8 2 4 6 8 0.7 -80 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (o C) 200 Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature 5 http://store.iiic.cc/ www.fairchildsemicom FDP8880 / FDB8880 Typical Characteristics TC = 25C unless otherwise noted 1.1 1.5 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A 1.2 0.9 0.6 0.3 -80 -40 0 40 80 120 160 1.0 0.9 -80 200 -40 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 80 120 160 200 VGS , GATE TO SOURCE VOLTAGE (V) 10 CISS = CGS + C GD 1000 C, CAPACITANCE (pF) 40 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 2000 COSS CDS + CGD C RSS = CGD VDD = 15V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 54A ID = 5A 2 VGS = 0V, f = 1MHz 100 0.1 0 TJ , JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC) 0 0 30 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 13. Capacitance vs Drain to Source Voltage (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 5 10 15 Qg , GATE CHARGE (nC) 20 25 Figure 14. Gate Charge Waveforms for Constant Gate Current 6 http://store.iiic.cc/ www.fairchildsemicom VDS BVDSS tP L VDS VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDD VDD - VGS DUT tP IAS 0V 0 0.01 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS VGS = 10V VGS Qg(5) + Qgs2 VDD VGS = 5V DUT VGS = 1V Ig(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON tOFF td(ON) td(OFF) RL tr VDS tf 90% 90% + VGS VDD - 10% 0 10% DUT 90% RGS VGS 50% 50% PULSE WIDTH VGS 0 Figure 19. Switching Time Test Circuit (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 10% Figure 20. Switching Time Waveforms 7 http://store.iiic.cc/ www.fairchildsemicom FDP8880 / FDB8880 Test Circuits and Waveforms .SUBCKT FDP8880 2 1 3 ; rev October 2004 Ca 12 8 9.5e-10 Cb 15 14 9.5e-10 Cin 6 8 1.15e-9 LDRAIN DPLCAP 10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD RLDRAIN RSLC1 51 5 51 EVTHRES + 19 8 + LGATE GATE 1 ESLC 11 + 17 EBREAK 18 - 50 RDRAIN 6 8 ESG DBREAK + RSLC2 Ebreak 11 7 17 18 32.88 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 DRAIN 2 5 EVTEMP RGATE + 18 22 9 20 21 16 DBODY MWEAK 6 MMED MSTRO RLGATE Lgate 1 9 5.3e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 1.7e-9 LSOURCE CIN 8 7 SOURCE 3 RSOURCE RLSOURCE RLgate 1 9 53 RLdrain 2 5 10 RLsource 3 7 17 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD S1A 12 S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 1.0e-3 Rgate 9 20 2.2 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 Rsource 8 7 RsourceMOD 6.8e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD 5 8 EDS - 19 VBAT + IT 14 + + - 8 22 RVTHRES Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),5))} .MODEL DbodyMOD D (IS=3E-12 IKF=10 N=1.01 RS=5e-3 TRS1=8e-4 TRS2=2e-7 + CJO=4.8e-10 M=0.55 TT=1e-11 XTI=2) .MODEL DbreakMOD D (RS=0.2 TRS1=1e-3 TRS2=-8.8e-6) .MODEL DplcapMOD D (CJO=5.5e-10 IS=1e-30 N=10 M=0.45) .MODEL MstroMOD NMOS (VTO=2.10 KP=170 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=1.75 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.2) .MODEL MweakMOD NMOS (VTO=1.39 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=22 RS=0.1) .MODEL RbreakMOD RES (TC1=8.0e-4 TC2=-8e-7) .MODEL RdrainMOD RES (TC1=-12e-3 TC2=.35e-4) .MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6) .MODEL RsourceMOD RES (TC1=5e-3 TC2=1e-6) .MODEL RvtempMOD RES (TC1=-2.78e-3 TC2=1.5e-6) .MODEL RvthresMOD RES (TC1=-1e-3 TC2=-8.2e-6) MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.3 VOFF=-0.8) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=-1.3) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 8 http://store.iiic.cc/ www.fairchildsemicom FDP8880 / FDB8880 PSPICE Electrical Model rev October 2004 template FDP8880 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=3e-12,ikf=10,nl=1.01,rs=5e-3,trs1=8e-4,trs2=2e-7,cjo=4.8e-10,m=0.55,tt=1e-11,xti=2) dp..model dbreakmod = (rs=0.2,trs1=1e-3,trs2=-8.8e-6) dp..model dplcapmod = (cjo=5.5e-10,isl=10e-30,nl=10,m=0.45) m..model mstrongmod = (type=_n,vto=2.10,kp=170,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=1.75,kp=10,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=1.39,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3.5) LDRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-4) DPLCAP 5 DRAIN 2 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-1.3,voff=-0.8) 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.8,voff=-1.3) RLDRAIN RSLC1 c.ca n12 n8 = 9.5e-10 51 c.cb n15 n14 = 9.5e-10 RSLC2 c.cin n6 n8 = 1.15e-9 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod RDRAIN 6 8 ESG EVTHRES + 19 8 + spe.ebreak n11 n7 n17 n18 = 32.88 spe.eds n14 n8 n5 n8 = 1 GATE spe.egs n13 n8 n6 n8 = 1 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 LGATE EVTEMP RGATE + 18 22 9 20 21 11 DBODY 16 MWEAK 6 EBREAK + 17 18 - MMED MSTRO RLGATE CIN 8 LSOURCE SOURCE 3 7 RSOURCE i.it n8 n17 = 1 RLSOURCE S1A l.lgate n1 n9 = 5.3e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 1.7e-9 res.rlgate n1 n9 = 53 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 17 DBREAK 50 - 12 S2A 13 8 15 14 13 S1B 18 RVTEMP CB 6 8 EGS 19 VBAT 5 8 EDS - IT 14 + + m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 17 S2B 13 CA RBREAK - + 8 22 RVTHRES res.rbreak n17 n18 = 1, tc1=8.0e-4,tc2=-8e-7 res.rdrain n50 n16 = 1.0e-3, tc1=-12e-3,tc2=.35e-4 res.rgate n9 n20 = 2.2 res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 6.8e-3, tc1=5e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-1e-3,tc2=-8.2e-6 res.rvtemp n18 n19 = 1, tc1=-2.78e-3,tc2=1.5e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/170))** 5))} } (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 9 http://store.iiic.cc/ www.fairchildsemicom FDP8880 / FDB8880 SABER Electrical Model th JUNCTION REV 23 December 2003 FDP8880T CTHERM1 TH 6 8e-4 CTHERM2 6 5 1e-3 CTHERM3 5 4 2.5e-3 CTHERM4 4 3 2.6e-3 CTHERM5 3 2 8e-3 CTHERM6 2 TL 1.5e-2 RTHERM1 CTHERM1 6 RTHERM1 TH 6 1.44e-1 RTHERM2 6 5 1.9e-1 RTHERM3 5 4 3.0e-1 RTHERM4 4 3 4.0e-1 RTHERM5 3 2 5.7e-1 RTHERM6 2 TL 5.8e-1 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDP8880T template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =8e-4 ctherm.ctherm2 6 5 =1e-3 ctherm.ctherm3 5 4 =2.5e-3 ctherm.ctherm4 4 3 =2.6e-3 ctherm.ctherm5 3 2 =8e-3 ctherm.ctherm6 2 tl =1.5e-2 RTHERM3 CTHERM3 4 RTHERM4 rtherm.rtherm1 th 6 =1.44e-1 rtherm.rtherm2 6 5 =1.9e-1 rtherm.rtherm3 5 4 =3.0e-1 rtherm.rtherm4 4 3 =4.0e-1 rtherm.rtherm5 3 2 =5.7e-1 rtherm.rtherm6 2 tl =5.8e-1 } CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl (c)2008 Fairchild Semiconductor Corporation FDP8880 / FDB8880 Rev. A1 10 http://store.iiic.cc/ CASE www.fairchildsemicom FDP8880 / FDB8880 PSPICE Thermal Model TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I34 @2008 Fairchild Semiconductor Corporation WWW. fairchildsemicom FDP8880 / FDB8880 Rev.A1 http://store.iiic.cc/